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[PATCH] DOS support: Makefile
by Carl-Daniel Hailfinger 21 Mar '10

21 Mar '10

Prepare the Makefile for DOS cross-compilation support. Some of the changes are pretty hackish, but they shouldn't affect compilation on other systems at all. Please note that the makefile now references files that don't exist in the tree yet, but since these references are only triggered if you're compiling for DOS and DOS support is not yet merged, I think this is OK. If you take the DOS support patch from Rudolf and replace his Makefile patch with mine, you have to call make like this: make CC=i586-pc-msdosdjgpp-gcc STRIP=i586-pc-msdosdjgpp-strip WARNERROR=no OS_ARCH=DOS Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-dos/Makefile =================================================================== --- flashrom-dos/Makefile (Revision 929) +++ flashrom-dos/Makefile (Arbeitskopie) @@ -2,6 +2,7 @@ # This file is part of the flashrom project. # # Copyright (C) 2005 coresystems GmbH <stepan(a)coresystems.de> +# Copyright (C) 2009,2010 Carl-Daniel Hailfinger # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -20,15 +21,22 @@ PROGRAM = flashrom CC ?= gcc -STRIP = strip +STRIP ?= strip INSTALL = install DIFF = diff PREFIX ?= /usr/local MANDIR ?= $(PREFIX)/share/man -CFLAGS ?= -Os -Wall -Werror -Wshadow +CFLAGS ?= -Os -Wall -Wshadow EXPORTDIR ?= . -OS_ARCH = $(shell uname) +WARNERROR ?= yes + +ifeq ($(WARNERROR), yes) +CFLAGS += -Werror +endif + +# FIXME We have to differentiate between host and target arch. +OS_ARCH ?= $(shell uname) ifneq ($(OS_ARCH), SunOS) STRIP_ARGS = -s endif @@ -40,6 +48,13 @@ CPPFLAGS += -I/usr/local/include LDFLAGS += -L/usr/local/lib endif +ifeq ($(OS_ARCH), DOS) +CPPFLAGS += -I. +OS_OBJS = getopt.o +# Bus Pirate and Serprog are not supported under DOS. +CONFIG_BUSPIRATESPI = no +CONFIG_SERPROG = no +endif CHIP_OBJS = jedec.o stm50flw0x0x.o w39v040c.o w39v080fa.o sharplhf00l04.o w29ee011.o \ sst28sf040.o m29f400bt.o 82802ab.o pm49fl00x.o \ @@ -188,14 +203,28 @@ endif ifeq ($(NEED_PCI), yes) -LIBS += -lpci +ifneq ($(OS_ARCH), DOS) +# FIXME This workaround is needed until libpci detection can handle +# cross-compiling for DOS. +CHECK_LIBPCI = yes +endif +endif + +ifeq ($(NEED_PCI), yes) FEATURE_CFLAGS += -D'NEED_PCI=1' PROGRAMMER_OBJS += pcidev.o physmap.o hwaccess.o ifeq ($(OS_ARCH), NetBSD) LIBS += -lpciutils # The libpci we want. LIBS += -l$(shell uname -p) # For (i386|x86_64)_iopl(2). +else +ifeq ($(OS_ARCH), DOS) +# FIXME There needs to be a better way to do this +LIBS += libpci.a +else +LIBS += -lpci endif endif +endif ifeq ($(CONFIG_PRINT_WIKI), yes) FEATURE_CFLAGS += -D'PRINT_WIKI_SUPPORT=1' @@ -205,7 +234,7 @@ # We could use PULLED_IN_LIBS, but that would be ugly. FEATURE_LIBS += $(shell LC_ALL=C grep -q "NEEDLIBZ := yes" .libdeps && printf "%s" "-lz") -OBJS = $(CHIP_OBJS) $(CLI_OBJS) $(PROGRAMMER_OBJS) $(LIB_OBJS) +OBJS = $(CHIP_OBJS) $(CLI_OBJS) $(PROGRAMMER_OBJS) $(LIB_OBJS) $(OS_OBJS) $(PROGRAM): $(OBJS) $(CC) $(LDFLAGS) -o $(PROGRAM) $(OBJS) $(FEATURE_LIBS) $(LIBS) @@ -239,7 +268,7 @@ rm -f .test.c .test; exit 1) @rm -f .test.c .test -ifeq ($(NEED_PCI), yes) +ifeq ($(CHECK_LIBPCI), yes) pciutils: compiler @printf "Checking for libpci headers... " @$(shell ( echo "#include <pci/pci.h>"; \ -- "I do consider assignment statements and pointer variables to be among computer science's most valuable treasures." -- Donald E. Knuth

2 5

[commit] r963 - trunk
by repository service 21 Mar '10

21 Mar '10

Author: hailfinger Date: Sun Mar 21 15:54:57 2010 New Revision: 963 URL: http://flashrom.org/trac/coreboot/changeset/963 Log: Add DOS cross-compilation support to the Makefile. Add a README with build instructions. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Modified: trunk/Makefile trunk/README Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Sun Mar 21 14:36:20 2010 (r962) +++ trunk/Makefile Sun Mar 21 15:54:57 2010 (r963) @@ -2,6 +2,7 @@ # This file is part of the flashrom project. # # Copyright (C) 2005 coresystems GmbH <stepan(a)coresystems.de> +# Copyright (C) 2009,2010 Carl-Daniel Hailfinger # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -20,15 +21,22 @@ PROGRAM = flashrom CC ?= gcc -STRIP = strip +STRIP ?= strip INSTALL = install DIFF = diff PREFIX ?= /usr/local MANDIR ?= $(PREFIX)/share/man -CFLAGS ?= -Os -Wall -Werror -Wshadow +CFLAGS ?= -Os -Wall -Wshadow EXPORTDIR ?= . -OS_ARCH = $(shell uname) +WARNERROR ?= yes + +ifeq ($(WARNERROR), yes) +CFLAGS += -Werror +endif + +# FIXME We have to differentiate between host and target arch. +OS_ARCH ?= $(shell uname) ifneq ($(OS_ARCH), SunOS) STRIP_ARGS = -s endif @@ -40,6 +48,12 @@ CPPFLAGS += -I/usr/local/include LDFLAGS += -L/usr/local/lib endif +ifeq ($(OS_ARCH), DOS) +CPPFLAGS += -I../libgetopt -I../libpci/include +# Bus Pirate and Serprog are not supported under DOS. +CONFIG_BUSPIRATESPI = no +CONFIG_SERPROG = no +endif CHIP_OBJS = jedec.o stm50flw0x0x.o w39v040c.o w39v080fa.o w29ee011.o \ sst28sf040.o m29f400bt.o 82802ab.o pm49fl00x.o \ @@ -188,12 +202,26 @@ endif ifeq ($(NEED_PCI), yes) -LIBS += -lpci +ifneq ($(OS_ARCH), DOS) +# FIXME This workaround is needed until libpci detection can handle +# cross-compiling for DOS. +CHECK_LIBPCI = yes +endif +endif + +ifeq ($(NEED_PCI), yes) FEATURE_CFLAGS += -D'NEED_PCI=1' PROGRAMMER_OBJS += pcidev.o physmap.o hwaccess.o ifeq ($(OS_ARCH), NetBSD) LIBS += -lpciutils # The libpci we want. LIBS += -l$(shell uname -p) # For (i386|x86_64)_iopl(2). +else +ifeq ($(OS_ARCH), DOS) +# FIXME There needs to be a better way to do this +LIBS += ../libpci/lib/libpci.a ../libgetopt/libgetopt.a +else +LIBS += -lpci +endif endif endif @@ -239,7 +267,7 @@ rm -f .test.c .test; exit 1) @rm -f .test.c .test -ifeq ($(NEED_PCI), yes) +ifeq ($(CHECK_LIBPCI), yes) pciutils: compiler @printf "Checking for libpci headers... " @$(shell ( echo "#include <pci/pci.h>"; \ @@ -315,6 +343,9 @@ @rm -rf $(EXPORTDIR)/flashrom-$(RELEASENAME) @echo Created $(EXPORTDIR)/flashrom-$(RELEASENAME).tar.bz2 -.PHONY: all clean distclean dep compiler pciutils features export tarball +djgpp-dos: clean + make CC=i586-pc-msdosdjgpp-gcc STRIP=i586-pc-msdosdjgpp-strip WARNERROR=no OS_ARCH=DOS + +.PHONY: all clean distclean dep compiler pciutils features export tarball dos -include .dependencies Modified: trunk/README ============================================================================== --- trunk/README Sun Mar 21 14:36:20 2010 (r962) +++ trunk/README Sun Mar 21 15:54:57 2010 (r963) @@ -42,7 +42,7 @@ * pciutils / libpci * pciutils-devel / pciutils-dev / libpci-dev - * zlib-devel / zlib1g-dev (only needed if libpci is static) + * zlib-devel / zlib1g-dev (needed if libpci was compiled with libz support) On FreeBSD, you need the following ports: @@ -75,6 +75,25 @@ Install DirectIO from coresystems GmbH. DirectIO is available at http://www.coresystems.de/en/directio. +To cross-compile on Linux for DOS: + + Get RPMs of the cross compiler from the DJGPP site and install them: + djcross-binutils-2.19.1-10ap.i386.rpm + djcross-gcc-tools-4.4.1-1ap.i686.rpm + djcross-gcc-4.3.2-8ap.i686.rpm + Download pciutils 3.1.5 and apply http://assembler.cz/flashrom/pciutils.patch + Download and compile http://assembler.cz/flashrom/libgetopt/ + Compile pciutils, see README.DJGPP for instructions. + Enter the flashrom directory. + ../libpci should contain pciutils source and binaries. + ../libgetopt should contain getopt.a from libgetopt. + Run either (change settings where appropriate) + make CC=i586-pc-msdosdjgpp-gcc STRIP=i586-pc-msdosdjgpp-strip OS_ARCH=DOS + or (above settings hardcoded) + make djgpp-dos + You might have to add WARNERROR=no to the make command line. + To run flashrom.exe, download http://clio.rice.edu/djgpp/csdpmi7b.zip and + make sure CWSDPMI.EXE is in the current directory. Installation ------------

1 0

[PATCH] Board enable for Termtek TK-3370
by Daniel Brandt 21 Mar '10

21 Mar '10

During an intensive IRC session about two weeks ago I got all the help I needed to patch in support for this fairly rare thin client motherboard that I happen to own. I've tested reading, writing and verifying and everything seem to work, so I'm submitting the patch. Also attaching lspci and superiotool output as requested. Regards, Daniel

2 2

[commit] r962 - trunk
by repository service 21 Mar '10

21 Mar '10

Author: mkarcher Date: Sun Mar 21 14:36:20 2010 New Revision: 962 URL: http://flashrom.org/trac/coreboot/changeset/962 Log: Adds board enable to Termtek TK-3370 thin client motherboard. Signed-off-by: Daniel Brandt <dbr(a)mindglow.se> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sat Mar 20 16:15:36 2010 (r961) +++ trunk/board_enable.c Sun Mar 21 14:36:20 2010 (r962) @@ -206,6 +206,17 @@ } /** + * Suited for: + * - Termtek TK-3370 (rev. 2.5b) + */ +static int w836xx_memw_enable_4e(const char *name) +{ + w836xx_memw_enable(0x4E); + + return 0; +} + +/** * */ static int it8705f_write_enable(uint8_t port, const char *name) @@ -1400,6 +1411,7 @@ {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower}, {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, "Tekram", "P6Pro-A5", 256, OK, NULL}, + {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise}, {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise}, {0x1106, 0x5337, 0x1458, 0xb003, 0x1106, 0x287e, 0x1106, 0x337e, NULL, NULL, NULL, "VIA", "PC3500G", 0, OK, it87xx_probe_spi_flash},

1 0

[PATCH] 82802ab and stm50flw0x0x cleanup
by Carl-Daniel Hailfinger 20 Mar '10

20 Mar '10

Kill a few unused functions in 82802ab.c and stm50flw0x0x.c. Replace wait_stm50flw0x0x() with wait_82802ab() as the the read id mode stuff is historic cruft that was never needed. Replace erase_82802ab_block() with erase_82802ab_block_withunlock(). Factor out unlocking from erase_82802ab_block(). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-82802ab_stm50flw0x0x_cleanup/flashchips.c =================================================================== --- flashrom-82802ab_stm50flw0x0x_cleanup/flashchips.c (Revision 947) +++ flashrom-82802ab_stm50flw0x0x_cleanup/flashchips.c (Arbeitskopie) @@ -2315,128 +2315,128 @@ .manufacture_id = INTEL_ID, .model_id = P28F001BXB, .total_size = 128, .page_size = 128 * 1024, /* 8k + 2x4k + 112k */ .feature_bits = 0, .tested = TEST_BAD_WRITE, .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ .block_erasers = { { .eraseblocks = { {8 * 1024, 1}, {4 * 1024, 2}, {112 * 1024, 1}, }, - .block_erase = erase_82802ab_block, + .block_erase = erase_82802ab_block_withunlock, }, }, .write = NULL, .read = read_memmapped, }, { .vendor = "Intel", .name = "28F001BX-T", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, .model_id = P28F001BXT, .total_size = 128, .page_size = 128 * 1024, /* 112k + 2x4k + 8k */ .feature_bits = 0, .tested = TEST_BAD_WRITE, .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ .block_erasers = { { .eraseblocks = { {112 * 1024, 1}, {4 * 1024, 2}, {8 * 1024, 1}, }, - .block_erase = erase_82802ab_block, + .block_erase = erase_82802ab_block_withunlock, }, }, .write = NULL, .read = read_memmapped, }, { .vendor = "Intel", .name = "28F004S5", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, .model_id = E_28F004S5, .total_size = 512, .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_82802ab, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ .block_erasers = { { .eraseblocks = { {64 * 1024, 8} }, - .block_erase = erase_82802ab_block, + .block_erase = erase_82802ab_block_withunlock, }, }, .write = write_82802ab, .read = read_memmapped, }, { .vendor = "Intel", .name = "82802AB", .bustype = CHIP_BUSTYPE_FWH, .manufacture_id = INTEL_ID, .model_id = I_82802AB, .total_size = 512, .page_size = 64 * 1024, .feature_bits = FEATURE_REGISTERMAP, - .tested = TEST_OK_PRW, + .tested = TEST_OK_PR, .probe = probe_82802ab, .probe_timing = TIMING_IGNORED, /* routine does not use probe_timing (82802ab.c) */ .block_erasers = { { .eraseblocks = { {64 * 1024, 8} }, - .block_erase = erase_82802ab_block, + .block_erase = erase_82802ab_block_withunlock, }, }, .write = write_82802ab, .read = read_memmapped, }, { .vendor = "Intel", .name = "82802AC", .bustype = CHIP_BUSTYPE_FWH, .manufacture_id = INTEL_ID, .model_id = I_82802AC, .total_size = 1024, .page_size = 64 * 1024, .feature_bits = FEATURE_REGISTERMAP, - .tested = TEST_OK_PRW, + .tested = TEST_OK_PR, .probe = probe_82802ab, .probe_timing = TIMING_IGNORED, /* routine does not use probe_timing (82802ab.c) */ .block_erasers = { { .eraseblocks = { {64 * 1024, 16} }, - .block_erase = erase_82802ab_block, + .block_erase = erase_82802ab_block_withunlock, }, }, .write = write_82802ab, .read = read_memmapped, }, { .vendor = "Macronix", .name = "MX25L512", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = MX_ID, .model_id = MX_25L512, .total_size = 64, .page_size = 256, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, Index: flashrom-82802ab_stm50flw0x0x_cleanup/stm50flw0x0x.c =================================================================== --- flashrom-82802ab_stm50flw0x0x_cleanup/stm50flw0x0x.c (Revision 947) +++ flashrom-82802ab_stm50flw0x0x_cleanup/stm50flw0x0x.c (Arbeitskopie) @@ -20,52 +20,32 @@ */ /* * This module is designed for supporting the devices * ST M50FLW040A (not yet tested) * ST M50FLW040B (not yet tested) * ST M50FLW080A * ST M50FLW080B (not yet tested) */ #include <string.h> #include <stdlib.h> #include "flash.h" #include "flashchips.h" #include "chipdrivers.h" -static void wait_stm50flw0x0x(chipaddr bios) -{ - chip_writeb(0x70, bios); - if ((chip_readb(bios) & 0x80) == 0) { // it's busy - while ((chip_readb(bios) & 0x80) == 0) ; - } - - // put another command to get out of status register mode - - chip_writeb(0x90, bios); - programmer_delay(10); - - chip_readb(bios); // Read device ID (to make sure?) - - // this is needed to jam it out of "read id" mode - chip_writeb(0xAA, bios + 0x5555); - chip_writeb(0x55, bios + 0x2AAA); - chip_writeb(0xF0, bios + 0x5555); -} - /* * claus.gindhart(a)kontron.com * The ST M50FLW080B and STM50FLW080B chips have to be unlocked, * before you can erase them or write to them. */ int unlock_block_stm50flw0x0x(struct flashchip *flash, int offset) { chipaddr wrprotect = flash->virtual_registers + 2; const uint8_t unlock_sector = 0x00; int j; /* * These chips have to be unlocked before you can erase them or write * to them. The size of the locking sectors depends on the type * of chip. * @@ -100,104 +80,66 @@ return 0; } int erase_block_stm50flw0x0x(struct flashchip *flash, unsigned int block, unsigned int blocksize) { chipaddr bios = flash->virtual_memory + block; // clear status register chip_writeb(0x50, bios); printf_debug("Erase at 0x%lx\n", bios); // now start it chip_writeb(0x20, bios); chip_writeb(0xd0, bios); programmer_delay(10); - wait_stm50flw0x0x(flash->virtual_memory); + wait_82802ab(flash->virtual_memory); if (check_erased_range(flash, block, blocksize)) { fprintf(stderr, "ERASE FAILED!\n"); return -1; } printf("DONE BLOCK 0x%x\n", block); return 0; } int erase_sector_stm50flw0x0x(struct flashchip *flash, unsigned int sector, unsigned int sectorsize) { chipaddr bios = flash->virtual_memory + sector; // clear status register chip_writeb(0x50, bios); printf_debug("Erase at 0x%lx\n", bios); // now start it chip_writeb(0x32, bios); chip_writeb(0xd0, bios); programmer_delay(10); - wait_stm50flw0x0x(flash->virtual_memory); + wait_82802ab(flash->virtual_memory); if (check_erased_range(flash, sector, sectorsize)) { fprintf(stderr, "ERASE FAILED!\n"); return -1; } printf("DONE BLOCK 0x%x\n", sector); return 0; } -int write_page_stm50flw0x0x(chipaddr bios, uint8_t *src, - chipaddr dst, int page_size) -{ - int i, rc = 0; - chipaddr d = dst; - uint8_t *s = src; - - /* transfer data from source to destination */ - for (i = 0; i < page_size; i++) { - chip_writeb(0x40, dst); - chip_writeb(*src++, dst++); - wait_stm50flw0x0x(bios); - } - -/* claus.gindhart(a)kontron.com - * TODO - * I think, that verification is not required, but - * i leave it in anyway - */ - dst = d; - src = s; - for (i = 0; i < page_size; i++) { - if (chip_readb(dst) != *src) { - rc = -1; - break; - } - dst++; - src++; - } - - if (rc) { - fprintf(stderr, " page 0x%lx failed!\n", - (d - bios) / page_size); - } - - return rc; -} - /* I simply erase block by block * I Chip This is not the fastest way, but it works */ int erase_stm50flw0x0x(struct flashchip *flash) { int i; int total_size = flash->total_size * 1024; int page_size = flash->page_size; printf("Erasing page:\n"); for (i = 0; i < total_size / page_size; i++) { printf ("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); printf("%04d at address: 0x%08x ", i, i * page_size); if (unlock_block_stm50flw0x0x(flash, i * page_size)) { fprintf(stderr, "UNLOCK FAILED!\n"); @@ -245,24 +187,24 @@ * Faster, because we only write, what has changed * More secure, because blocks, which are excluded * (with the exclude or layout feature) * are not erased and rewritten; data is retained also * in sudden power off situations */ chip_readn(tmpbuf, bios + i * page_size, page_size); if (!memcmp((void *)(buf + i * page_size), tmpbuf, page_size)) { printf("SKIPPED\n"); continue; } rc = unlock_block_stm50flw0x0x(flash, i * page_size); if (!rc) rc = erase_block_stm50flw0x0x(flash, i * page_size, page_size); if (!rc) - write_page_stm50flw0x0x(bios, buf + i * page_size, + write_page_82802ab(bios, buf + i * page_size, bios + i * page_size, page_size); } printf("\n"); free(tmpbuf); return rc; } Index: flashrom-82802ab_stm50flw0x0x_cleanup/82802ab.c =================================================================== --- flashrom-82802ab_stm50flw0x0x_cleanup/82802ab.c (Revision 947) +++ flashrom-82802ab_stm50flw0x0x_cleanup/82802ab.c (Arbeitskopie) @@ -1,20 +1,21 @@ /* * This file is part of the flashrom project. * * Copyright (C) 2000 Silicon Integrated System Corporation + * Copyright (C) 2010 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ @@ -79,79 +80,75 @@ { uint8_t status; chip_writeb(0x70, bios); if ((chip_readb(bios) & 0x80) == 0) { // it's busy while ((chip_readb(bios) & 0x80) == 0) ; } status = chip_readb(bios); /* Reset to get a clean state */ chip_writeb(0xFF, bios); return status; } +int unlock_82802ab_block(struct flashchip *flash, unsigned int page) +{ + chipaddr wrprotect = flash->virtual_registers + page + 2; + + /* Clear write protect */ + chip_writeb(0, wrprotect); + + return 0; +} + +/* FIXME: Ugly hack. Shoud do unlock separately. */ +int erase_82802ab_block_withunlock(struct flashchip *flash, unsigned int page, unsigned int pagesize) +{ + unlock_82802ab_block(flash, page); + return erase_82802ab_block(flash, page, pagesize); +} + int erase_82802ab_block(struct flashchip *flash, unsigned int page, unsigned int pagesize) { chipaddr bios = flash->virtual_memory; - chipaddr wrprotect = flash->virtual_registers + page + 2; uint8_t status; // clear status register chip_writeb(0x50, bios + page); - // clear write protect - chip_writeb(0, wrprotect); - // now start it chip_writeb(0x20, bios + page); chip_writeb(0xd0, bios + page); programmer_delay(10); // now let's see what the register is status = wait_82802ab(bios); print_82802ab_status(status); if (check_erased_range(flash, page, pagesize)) { fprintf(stderr, "ERASE FAILED!\n"); return -1; } printf("DONE BLOCK 0x%x\n", page); return 0; } -int erase_82802ab(struct flashchip *flash) -{ - int i; - unsigned int total_size = flash->total_size * 1024; - - printf("total_size is %d; flash->page_size is %d\n", - total_size, flash->page_size); - for (i = 0; i < total_size; i += flash->page_size) - if (erase_82802ab_block(flash, i, flash->page_size)) { - fprintf(stderr, "ERASE FAILED!\n"); - return -1; - } - printf("DONE ERASE\n"); - - return 0; -} - void write_page_82802ab(chipaddr bios, uint8_t *src, chipaddr dst, int page_size) { int i; for (i = 0; i < page_size; i++) { /* transfer data from source to destination */ chip_writeb(0x40, dst); chip_writeb(*src++, dst++); wait_82802ab(bios); } } int write_82802ab(struct flashchip *flash, uint8_t *buf) { int i; @@ -171,28 +168,28 @@ printf("%04d at address: 0x%08x", i, i * page_size); /* Auto Skip Blocks, which already contain the desired data * Faster, because we only write, what has changed * More secure, because blocks, which are excluded * (with the exclude or layout feature) * or not erased and rewritten; their data is retained also in * sudden power off situations */ chip_readn(tmpbuf, bios + i * page_size, page_size); if (!memcmp((void *)(buf + i * page_size), tmpbuf, page_size)) { printf("SKIPPED\n"); continue; } /* erase block by block and write block by block; this is the most secure way */ - if (erase_82802ab_block(flash, i * page_size, page_size)) { + if (erase_82802ab_block_withunlock(flash, i * page_size, page_size)) { fprintf(stderr, "ERASE FAILED!\n"); return -1; } write_page_82802ab(bios, buf + i * page_size, bios + i * page_size, page_size); } printf("\n"); free(tmpbuf); return 0; } Index: flashrom-82802ab_stm50flw0x0x_cleanup/chipdrivers.h =================================================================== --- flashrom-82802ab_stm50flw0x0x_cleanup/chipdrivers.h (Revision 947) +++ flashrom-82802ab_stm50flw0x0x_cleanup/chipdrivers.h (Arbeitskopie) @@ -43,34 +43,34 @@ int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_chip_write_1(struct flashchip *flash, uint8_t *buf); int spi_chip_write_256(struct flashchip *flash, uint8_t *buf); int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); uint8_t spi_read_status_register(void); int spi_disable_blockprotect(void); int spi_byte_program(int addr, uint8_t databyte); int spi_nbyte_program(int addr, uint8_t *bytes, int len); int spi_nbyte_read(int addr, uint8_t *bytes, int len); int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); int spi_aai_write(struct flashchip *flash, uint8_t *buf); /* 82802ab.c */ uint8_t wait_82802ab(chipaddr bios); int probe_82802ab(struct flashchip *flash); -int erase_82802ab(struct flashchip *flash); int erase_82802ab_block(struct flashchip *flash, unsigned int page, unsigned int pagesize); +int erase_82802ab_block_withunlock(struct flashchip *flash, unsigned int page, unsigned int pagesize); int write_82802ab(struct flashchip *flash, uint8_t *buf); void print_82802ab_status(uint8_t status); void write_page_82802ab(chipaddr bios, uint8_t *src, chipaddr dst, int page_size); /* jedec.c */ uint8_t oddparity(uint8_t val); void toggle_ready_jedec(chipaddr dst); void data_polling_jedec(chipaddr dst, uint8_t data); int write_byte_program_jedec(chipaddr bios, uint8_t *src, chipaddr dst); int probe_jedec(struct flashchip *flash); int erase_chip_jedec(struct flashchip *flash); int write_jedec(struct flashchip *flash, uint8_t *buf); int write_jedec_1(struct flashchip *flash, uint8_t *buf); int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int pagesize); int erase_block_jedec(struct flashchip *flash, unsigned int page, unsigned int blocksize); @@ -112,23 +112,22 @@ /* sst_fwhub.c */ int printlock_sst_fwhub(struct flashchip *flash); int unlock_sst_fwhub(struct flashchip *flash); /* w39v040c.c */ int printlock_w39v040c(struct flashchip *flash); /* w39V080fa.c */ int unlock_winbond_fwhub(struct flashchip *flash); /* w29ee011.c */ int probe_w29ee011(struct flashchip *flash); /* stm50flw0x0x.c */ int probe_stm50flw0x0x(struct flashchip *flash); -int erase_stm50flw0x0x(struct flashchip *flash); int erase_block_stm50flw0x0x(struct flashchip *flash, unsigned int block, unsigned int blocksize); int erase_sector_stm50flw0x0x(struct flashchip *flash, unsigned int block, unsigned int blocksize); int erase_chip_stm50flw0x0x(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int write_stm50flw0x0x(struct flashchip *flash, uint8_t *buf); #endif /* !__CHIPDRIVERS_H__ */ -- "I do consider assignment statements and pointer variables to be among computer science's most valuable treasures." -- Donald E. Knuth

3 9

[commit] r961 - trunk
by repository service 20 Mar '10

20 Mar '10

Author: snelson Date: Sat Mar 20 16:15:36 2010 New Revision: 961 URL: http://flashrom.org/trac/coreboot/changeset/961 Log: unlock fixup Signed-off-by: Sean Nelson <audiohacked(a)gmail.com> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/82802ab.c trunk/stm50flw0x0x.c Modified: trunk/82802ab.c ============================================================================== --- trunk/82802ab.c Sat Mar 20 04:01:19 2010 (r960) +++ trunk/82802ab.c Sat Mar 20 16:15:36 2010 (r961) @@ -97,7 +97,7 @@ int i; //chipaddr wrprotect = flash->virtual_registers + page + 2; - for (i = 0; i < flash->total_size; i+= flash->page_size) + for (i = 0; i < flash->total_size * 1024; i+= flash->page_size) { chip_writeb(0, flash->virtual_registers + i + 2); } Modified: trunk/stm50flw0x0x.c ============================================================================== --- trunk/stm50flw0x0x.c Sat Mar 20 04:01:19 2010 (r960) +++ trunk/stm50flw0x0x.c Sat Mar 20 16:15:36 2010 (r961) @@ -85,7 +85,7 @@ { int i; - for (i = 0; i < flash->total_size; i+= flash->page_size) { + for (i = 0; i < flash->total_size * 1024; i+= flash->page_size) { if(unlock_block_stm50flw0x0x(flash, i)) { fprintf(stderr, "UNLOCK FAILED!\n"); return -1;

1 0

[commit] r960 - trunk
by repository service 20 Mar '10

20 Mar '10

Author: snelson Date: Sat Mar 20 04:01:19 2010 New Revision: 960 URL: http://flashrom.org/trac/coreboot/changeset/960 Log: The Intel 28F001BX-T/B chips don't have block locks or mention of registers; chip is Old. The Intel 28F004S5 mentions block locks which require a remapping registers. Fixes problems brought up by carldani because of commit r948. Signed-off-by: Sean Nelson <audiohacked(a)gmail.com> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/flashchips.c Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Sat Mar 20 00:01:34 2010 (r959) +++ trunk/flashchips.c Sat Mar 20 04:01:19 2010 (r960) @@ -2316,7 +2316,6 @@ .model_id = P28F001BXB, .total_size = 128, .page_size = 128 * 1024, /* 8k + 2x4k + 112k */ - .feature_bits = 0, .tested = TEST_BAD_WRITE, .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ @@ -2331,7 +2330,6 @@ .block_erase = erase_block_82802ab, }, }, - .unlock = unlock_82802ab, .write = NULL, .read = read_memmapped, }, @@ -2344,7 +2342,6 @@ .model_id = P28F001BXT, .total_size = 128, .page_size = 128 * 1024, /* 112k + 2x4k + 8k */ - .feature_bits = 0, .tested = TEST_BAD_WRITE, .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ @@ -2359,7 +2356,6 @@ .block_erase = erase_block_82802ab, }, }, - .unlock = unlock_82802ab, .write = NULL, .read = read_memmapped, }, @@ -2372,6 +2368,7 @@ .model_id = E_28F004S5, .total_size = 512, .page_size = 256, + .feature_bits = FEATURE_REGISTERMAP, .tested = TEST_UNTESTED, .probe = probe_82802ab, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */

1 0

MCP SPI dump
by Kevin Bosworth 20 Mar '10

20 Mar '10

Hi, I'm not sure if you really need this. But, here it is, the output from flashrom and lspci as mentioned on http://www.phoronix.com/forums/showthread.php?t=21054&highlight=flashrom. The attached info is for the motherboard Nvidia 790i Ultra SLI (part #-132-CK-NF79) by EVGA. Let me know if you need additional info. Thanks. Kevin

1 0

[PATCH 06/11] Rebased Board Enable Patch: Asus P4B533-E Signed-off-by: Michael Karcher <flashrom@mkarcher.dialup.fu-berlin.de>
by Sean Nelson 20 Mar '10

20 Mar '10

--- board_enable.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index 89dad8a..13abc40 100644 --- a/board_enable.c +++ b/board_enable.c @@ -939,26 +939,27 @@ static int intel_ich_gpio19_raise(const char *name) * Suited for: * - Asus P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2. * - Asus P4C800-E Deluxe: socket478 + 875P + ICH5. * - Asus P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R. */ static int intel_ich_gpio21_raise(const char *name) { return intel_ich_gpio_set(21, 1); } /** * Suited for: * - Asus P4B266: socket478 + intel 845D + ICH2. + * - Asus P4B533-E: socket478 + 845E + ICH4 * - Asus P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2 */ static int intel_ich_gpio22_raise(const char *name) { return intel_ich_gpio_set(22, 1); } /** * Suited for HP Vectra VL400: 815 + ICH + PC87360. */ static int board_hp_vl400(const char *name) { -- 1.6.6

1 2

[PATCH 11/11] Rebased Board Enable Patch: iBase MB899.
by Sean Nelson 20 Mar '10

20 Mar '10

Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index b7b62f9..8692a98 100644 --- a/board_enable.c +++ b/board_enable.c @@ -974,26 +974,34 @@ static int board_hp_vl400(const char *name) } /** * Suited for: * - Dell Poweredge 1850: Intel PPGA604 + E7520 + ICH5R. * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R. */ static int intel_ich_gpio23_raise(const char *name) { return intel_ich_gpio_set(23, 1); } /** + * Suited for IBase MB899: i945GM + ICH7. + */ +static int intel_ich_gpio26_raise(const char *name) +{ + return intel_ich_gpio_set(26, 1); +} + +/** * Suited for Acorp 6A815EPD: socket 370 + intel 815 + ICH2. */ static int board_acorp_6a815epd(const char *name) { int ret; /* Lower Blocks Lock -- pin 7 of PLCC32 */ ret = intel_ich_gpio_set(22, 1); if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */ ret = intel_ich_gpio_set(23, 1); return ret; } @@ -1361,26 +1369,27 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, {0x1039, 0x0761, 0, 0, 0x10EC, 0x8168, 0, 0, NULL, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", 0, OK, it87xx_probe_spi_flash}, {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, NULL, "GIGABYTE", "GA-7VT600", 0, OK, it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, {0x10DE, 0x0360, 0x1458, 0x0C11, 0x10DE, 0x0369, 0x1458, 0x5001, NULL, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", 0, OK, it87xx_probe_spi_flash}, {0x10de, 0x03e0, 0, 0, 0x10DE, 0x03D0, 0, 0, NULL, NULL, NULL, "GIGABYTE", "GA-M61P-S3", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x7910, 0x1458, 0x5000, 0x1002, 0x438D, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-MA69VM-S2", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb000, NULL, NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb002, "^GA-MA78GM-S2H$", NULL, NULL, "GIGABYTE", "GA-MA78GM-S2H", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x438d, 0x1458, 0x5001, 0x1002, 0x5956, 0x1002, 0x5956, NULL, NULL, NULL, "GIGABYTE", "GA-MA790FX-DQ6", 0, OK, it87xx_probe_spi_flash}, {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable}, {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400}, {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise}, + {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", "iBASE", "MB899", 0, NT, intel_ich_gpio26_raise}, {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455}, {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi}, {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower}, {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e}, {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m}, {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, "Mitac", "6513WU", 0, OK, board_mitac_6513wu}, {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v}, {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio4_4_raise_2e}, {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v}, {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml}, {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise}, {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio4_4_raise_4e}, {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8N GM2-L)", 0, NT, nvidia_mcp_gpio2_raise}, -- 1.6.6

1 1

[commit] r959 - trunk
by repository service 20 Mar '10

20 Mar '10

Author: snelson Date: Sat Mar 20 00:01:34 2010 New Revision: 959 URL: http://flashrom.org/trac/coreboot/changeset/959 Log: Rebased Board Enable Patch: iBase MB899. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sat Mar 20 00:00:07 2010 (r958) +++ trunk/board_enable.c Sat Mar 20 00:01:34 2010 (r959) @@ -984,6 +984,14 @@ } /** + * Suited for IBase MB899: i945GM + ICH7. + */ +static int intel_ich_gpio26_raise(const char *name) +{ + return intel_ich_gpio_set(26, 1); +} + +/** * Suited for Acorp 6A815EPD: socket 370 + intel 815 + ICH2. */ static int board_acorp_6a815epd(const char *name) @@ -1371,6 +1379,7 @@ {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable}, {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400}, {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise}, + {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", "iBASE", "MB899", 0, NT, intel_ich_gpio26_raise}, {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455}, {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi}, {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower},

1 0

[PATCH 10/11] Rebased Board Enable Patch: Abit AN-M2.
by Sean Nelson 20 Mar '10

20 Mar '10

Ah, right-o, pulled this out of my git repo where it has been sitting since the 24th :) Luc Verhaegen. --- board_enable.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index de274e7..b7b62f9 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1313,26 +1313,27 @@ static int it8712f_gpio3_1_raise(const char *name) * The coreboot ids are used two fold. When running with a coreboot firmware, * the ids uniquely matches the coreboot board identification string. When a * legacy bios is installed and when autodetection is not possible, these ids * can be used to identify the board through the -m command line argument. * * When a board is identified through its coreboot ids (in both cases), the * main pci ids are still required to match, as a safeguard. */ /* Please keep this list alphabetically ordered by vendor/board name. */ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ + {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "Abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, "Abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower}, {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "Abit", "VT6X4", 0, NT, via_apollo_gpo4_lower}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, NULL, "AOpen", "vKM400Am-S", 0, OK, it8705f_write_enable_2e}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V8X", 0, OK, board_asus_a7v8x}, -- 1.6.6

1 1

[commit] r958 - trunk
by repository service 20 Mar '10

20 Mar '10

Author: snelson Date: Sat Mar 20 00:00:07 2010 New Revision: 958 URL: http://flashrom.org/trac/coreboot/changeset/958 Log: Rebased Board Enable Patch: Abit AN-M2. Original patch by: Luc Verhaegen. Signed-off-by: Sean Nelson <audiohacked(a)gmail.com> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Fri Mar 19 23:58:15 2010 (r957) +++ trunk/board_enable.c Sat Mar 20 00:00:07 2010 (r958) @@ -1323,6 +1323,7 @@ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ + {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "Abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, "Abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower},

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[PATCH 08/11] Reversed-engineered board enable for the ASUS A8N-LA. IDs are ISA and SMBus. Added dmi string to match 3 HP boards: Nagami, Nagami2, Nagami2L.
by Sean Nelson 19 Mar '10

19 Mar '10

Signed-off-by: Sean Nelson <audiohacked(a)gmail.com> --- board_enable.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index 731171c..aa9fec8 100644 --- a/board_enable.c +++ b/board_enable.c @@ -531,26 +531,27 @@ static int nvidia_mcp_gpio_set(int gpio, int raise) base += 0xC0; tmp = INB(base + gpio); tmp &= ~0x0F; /* null lower nibble */ tmp |= 0x04; /* gpio -> output. */ if (raise) tmp |= 0x01; OUTB(tmp, base + gpio); return 0; } /** + * Suited for ASUS A8N-LA: nVidia MCP51. * Suited for ASUS M2NBP-VM CSM: nVidia MCP51. */ static int nvidia_mcp_gpio0_raise(const char *name) { return nvidia_mcp_gpio_set(0x00, 1); } /** * Suited for Abit KN8 Ultra: nVidia CK804. */ static int nvidia_mcp_gpio2_lower(const char *name) { return nvidia_mcp_gpio_set(0x02, 0); @@ -1329,26 +1330,27 @@ struct board_pciid_enable board_pciid_enables[] = { {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, NULL, "AOpen", "vKM400Am-S", 0, OK, it8705f_write_enable_2e}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V8X", 0, OK, board_asus_a7v8x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise}, {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e}, {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, "ASUS", "A8JM", 0, NT, intel_ich_gpio34_raise}, {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, "ASUS", "A8N", 0, NT, board_shuttle_fn25}, + {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI", NULL, NULL, "ASUS", "A8N-LA", 0, NT, nvidia_mcp_gpio0_raise}, {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise}, {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise}, {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise}, {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, OK, board_asus_p5a}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, NULL, "Biostar", "P4M80-M4", 0, OK, it8705f_write_enable_2e}, {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise}, {0x1039, 0x5513, 0x1019, 0x0A41, 0x1039, 0x0018, 0, 0, NULL, NULL, NULL, "Elitegroup", "K7S6A", 0, OK, it8705f_write_enable_2e}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, OK, it8705f_write_enable_2e}, -- 1.6.6

1 1

[commit] r957 - trunk
by repository service 19 Mar '10

19 Mar '10

Author: snelson Date: Fri Mar 19 23:58:15 2010 New Revision: 957 URL: http://flashrom.org/trac/coreboot/changeset/957 Log: Reversed-engineered board enable for the ASUS A8N-LA. Rebased. IDs are ISA and SMBus. Added dmi string to match 3 HP boards: Nagami, Nagami2, Nagami2L. This could match any HP Nagami board. Needs testing. Signed-off-by: Sean Nelson <audiohacked(a)gmail.com> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Fri Mar 19 23:55:48 2010 (r956) +++ trunk/board_enable.c Fri Mar 19 23:58:15 2010 (r957) @@ -541,6 +541,7 @@ } /** + * Suited for ASUS A8N-LA: nVidia MCP51. * Suited for ASUS M2NBP-VM CSM: nVidia MCP51. */ static int nvidia_mcp_gpio0_raise(const char *name) @@ -1339,6 +1340,7 @@ {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e}, {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, "ASUS", "A8JM", 0, NT, intel_ich_gpio34_raise}, {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, "ASUS", "A8N", 0, NT, board_shuttle_fn25}, + {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI", NULL, NULL, "ASUS", "A8N-LA", 0, NT, nvidia_mcp_gpio0_raise}, {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise}, {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise},

1 0

[PATCH 09/11] Rebased Board Enable Patch: 2nd attempt to fix board detection on GA-MA74GM-S2H.
by Sean Nelson 19 Mar '10

19 Mar '10

This board (GA-MA74GM-S2H) has the same list of pciids as the GA-MA78M-S2H, so I narroved search conditions by populating corresponding board_pciid_enable entry for GA-MA78M-S2H with DMI pattern. I don't have GA-MA78M-S2H available, so, please, test whether this works or not. P.S. I made a typo in the previous patch, so this is a fixed one. Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- board_enable.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/board_enable.c b/board_enable.c index aa9fec8..de274e7 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1355,27 +1355,27 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1039, 0x5513, 0x1019, 0x0A41, 0x1039, 0x0018, 0, 0, NULL, NULL, NULL, "Elitegroup", "K7S6A", 0, OK, it8705f_write_enable_2e}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, OK, it8705f_write_enable_2e}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e}, {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise}, {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", "EPoX", "EP-BX3", 0, OK, board_epox_ep_bx3}, {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, {0x1039, 0x0761, 0, 0, 0x10EC, 0x8168, 0, 0, NULL, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", 0, OK, it87xx_probe_spi_flash}, {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, NULL, "GIGABYTE", "GA-7VT600", 0, OK, it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, {0x10DE, 0x0360, 0x1458, 0x0C11, 0x10DE, 0x0369, 0x1458, 0x5001, NULL, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", 0, OK, it87xx_probe_spi_flash}, {0x10de, 0x03e0, 0, 0, 0x10DE, 0x03D0, 0, 0, NULL, NULL, NULL, "GIGABYTE", "GA-M61P-S3", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x7910, 0x1458, 0x5000, 0x1002, 0x438D, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-MA69VM-S2", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb000, NULL, NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H", 0, OK, it87xx_probe_spi_flash}, - {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb002, NULL, NULL, NULL, "GIGABYTE", "GA-MA78GM-S2H", 0, OK, it87xx_probe_spi_flash}, + {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb002, "^GA-MA78GM-S2H$", NULL, NULL, "GIGABYTE", "GA-MA78GM-S2H", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x438d, 0x1458, 0x5001, 0x1002, 0x5956, 0x1002, 0x5956, NULL, NULL, NULL, "GIGABYTE", "GA-MA790FX-DQ6", 0, OK, it87xx_probe_spi_flash}, {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable}, {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400}, {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise}, {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455}, {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi}, {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower}, {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e}, {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m}, {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, "Mitac", "6513WU", 0, OK, board_mitac_6513wu}, {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v}, {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio4_4_raise_2e}, {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v}, -- 1.6.6

1 1

[commit] r956 - trunk
by repository service 19 Mar '10

19 Mar '10

Author: snelson Date: Fri Mar 19 23:55:48 2010 New Revision: 956 URL: http://flashrom.org/trac/coreboot/changeset/956 Log: Rebased Board Enable Patch: 2nd attempt to fix board detection on GA-MA74GM-S2H. This board (GA-MA74GM-S2H) has the same list of pciids as the GA-MA78M-S2H, so I narroved search conditions by populating corresponding board_pciid_enable entry for GA-MA78M-S2H with DMI pattern. Untested! Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Fri Mar 19 23:52:00 2010 (r955) +++ trunk/board_enable.c Fri Mar 19 23:55:48 2010 (r956) @@ -1363,7 +1363,7 @@ {0x10de, 0x03e0, 0, 0, 0x10DE, 0x03D0, 0, 0, NULL, NULL, NULL, "GIGABYTE", "GA-M61P-S3", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x7910, 0x1458, 0x5000, 0x1002, 0x438D, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-MA69VM-S2", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb000, NULL, NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H", 0, OK, it87xx_probe_spi_flash}, - {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb002, NULL, NULL, NULL, "GIGABYTE", "GA-MA78GM-S2H", 0, OK, it87xx_probe_spi_flash}, + {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb002, "^GA-MA78GM-S2H$", NULL, NULL, "GIGABYTE", "GA-MA78GM-S2H", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x438d, 0x1458, 0x5001, 0x1002, 0x5956, 0x1002, 0x5956, NULL, NULL, NULL, "GIGABYTE", "GA-MA790FX-DQ6", 0, OK, it87xx_probe_spi_flash}, {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable}, {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400},

1 0

[commit] r955 - trunk
by repository service 19 Mar '10

19 Mar '10

Author: snelson Date: Fri Mar 19 23:52:00 2010 New Revision: 955 URL: http://flashrom.org/trac/coreboot/changeset/955 Log: Rebased Board Enable Patch: Asus P4B533-E Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Fri Mar 19 23:49:09 2010 (r954) +++ trunk/board_enable.c Fri Mar 19 23:52:00 2010 (r955) @@ -949,6 +949,7 @@ /** * Suited for: * - Asus P4B266: socket478 + intel 845D + ICH2. + * - Asus P4B533-E: socket478 + 845E + ICH4 * - Asus P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2 */ static int intel_ich_gpio22_raise(const char *name) @@ -1342,6 +1343,7 @@ {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise}, {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise}, {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, OK, board_asus_p5a},

1 0

[PATCH 07/11] Rebased Board Enable Patch: Factor out Via Apollo GPO setting
by Sean Nelson 19 Mar '10

19 Mar '10

Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- board_enable.c | 47 ++++++++++++++++++++++++++++++++++++++--------- 1 files changed, 38 insertions(+), 9 deletions(-) diff --git a/board_enable.c b/board_enable.c index 13abc40..731171c 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1004,64 +1004,92 @@ static int board_kontron_986lcd_m(const char *name) { int ret; ret = intel_ich_gpio_set(34, 1); /* #TBL */ if (!ret) ret = intel_ich_gpio_set(35, 1); /* #WP */ return ret; } /** * Suited for Soyo SY-7VCA: Pro133A + VT82C686. */ -static int board_soyo_sy_7vca(const char *name) +static int via_apollo_gpo_set(int gpio, int raise) { - struct pci_dev *dev; + struct pci_dev *dev; uint32_t base; - uint8_t tmp; + uint32_t tmp; /* VT82C686 Power management */ dev = pci_dev_find(0x1106, 0x3057); if (!dev) { fprintf(stderr, "\nERROR: VT82C686 PM device not found.\n"); return -1; } - /* GPO0 output from PM IO base + 0x4C */ + printf("\nVIA Apollo ACPI: %sing GPIO%02d.\n", + raise ? "Rais" : "Dropp", gpio); + + /* select GPO function on multiplexed pins */ tmp = pci_read_byte(dev, 0x54); - tmp &= ~0x03; + switch(gpio) + { + case 0: + tmp &= ~0x03; + break; + case 1: + tmp |= 0x04; + break; + case 2: + tmp |= 0x08; + break; + case 3: + tmp |= 0x10; + break; + } pci_write_byte(dev, 0x54, tmp); /* PM IO base */ base = pci_read_long(dev, 0x48) & 0x0000FF00; /* Drop GPO0 */ - tmp = INB(base + 0x4C); - tmp &= ~0x01; - OUTB(tmp, base + 0x4C); + tmp = INL(base + 0x4C); + if (raise) + tmp |= 1U << gpio; + else + tmp &= ~(1U << gpio); + OUTL(tmp, base + 0x4C); return 0; } /** * Suited for Abit VT6X5: Pro133x + VT82C686A */ static int via_apollo_gpo4_lower(const char *name) { return via_apollo_gpo_set(4, 0); } /** + * Suited for Soyo SY-7VCA: Pro133A + VT82C686. + */ +static int via_apollo_gpo0_lower(const char *name) +{ + return via_apollo_gpo_set(0, 0); +} + +/** * Enable some GPIO pin on SiS southbridge. * Suited for MSI 651M-L: SiS651 / SiS962 */ static int board_msi_651ml(const char *name) { struct pci_dev *dev; uint16_t base, temp; dev = pci_dev_find(0x1039, 0x0962); if (!dev) { fprintf(stderr, "Expected south bridge not found\n"); return 1; } @@ -1305,26 +1333,27 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, NULL, "AOpen", "vKM400Am-S", 0, OK, it8705f_write_enable_2e}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V8X", 0, OK, board_asus_a7v8x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise}, {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e}, {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, "ASUS", "A8JM", 0, NT, intel_ich_gpio34_raise}, {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, "ASUS", "A8N", 0, NT, board_shuttle_fn25}, {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise}, {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise}, {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise}, {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, OK, board_asus_p5a}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, NULL, "Biostar", "P4M80-M4", 0, OK, it8705f_write_enable_2e}, {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise}, {0x1039, 0x5513, 0x1019, 0x0A41, 0x1039, 0x0018, 0, 0, NULL, NULL, NULL, "Elitegroup", "K7S6A", 0, OK, it8705f_write_enable_2e}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, OK, it8705f_write_enable_2e}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e}, {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise}, {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", "EPoX", "EP-BX3", 0, OK, board_epox_ep_bx3}, {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, {0x1039, 0x0761, 0, 0, 0x10EC, 0x8168, 0, 0, NULL, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", 0, OK, it87xx_probe_spi_flash}, @@ -1346,27 +1375,27 @@ struct board_pciid_enable board_pciid_enables[] = { {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m}, {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, "Mitac", "6513WU", 0, OK, board_mitac_6513wu}, {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v}, {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio4_4_raise_2e}, {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v}, {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml}, {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise}, {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio4_4_raise_4e}, {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8N GM2-L)", 0, NT, nvidia_mcp_gpio2_raise}, {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, - {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, OK, board_soyo_sy_7vca}, + {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower}, {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, "Tekram", "P6Pro-A5", 256, OK, NULL}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise}, {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise}, {0x1106, 0x5337, 0x1458, 0xb003, 0x1106, 0x287e, 0x1106, 0x337e, NULL, NULL, NULL, "VIA", "PC3500G", 0, OK, it87xx_probe_spi_flash}, { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */ }; /** * Match boards on coreboot table gathered vendor and part name. * Require main PCI IDs to match too as extra safety. */ -- 1.6.6

1 1

[commit] r954 - trunk
by repository service 19 Mar '10

19 Mar '10

Author: snelson Date: Fri Mar 19 23:49:09 2010 New Revision: 954 URL: http://flashrom.org/trac/coreboot/changeset/954 Log: Rebased Board Enable Patch: Factor out Via Apollo GPO setting VT6X4 actually depended on this commit, blame snelson. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Fri Mar 19 23:39:24 2010 (r953) +++ trunk/board_enable.c Fri Mar 19 23:49:09 2010 (r954) @@ -1013,11 +1013,11 @@ /** * Suited for Soyo SY-7VCA: Pro133A + VT82C686. */ -static int board_soyo_sy_7vca(const char *name) +static int via_apollo_gpo_set(int gpio, int raise) { - struct pci_dev *dev; + struct pci_dev *dev; uint32_t base; - uint8_t tmp; + uint32_t tmp; /* VT82C686 Power management */ dev = pci_dev_find(0x1106, 0x3057); @@ -1026,18 +1026,38 @@ return -1; } - /* GPO0 output from PM IO base + 0x4C */ + printf("\nVIA Apollo ACPI: %sing GPIO%02d.\n", + raise ? "Rais" : "Dropp", gpio); + + /* select GPO function on multiplexed pins */ tmp = pci_read_byte(dev, 0x54); - tmp &= ~0x03; + switch(gpio) + { + case 0: + tmp &= ~0x03; + break; + case 1: + tmp |= 0x04; + break; + case 2: + tmp |= 0x08; + break; + case 3: + tmp |= 0x10; + break; + } pci_write_byte(dev, 0x54, tmp); /* PM IO base */ base = pci_read_long(dev, 0x48) & 0x0000FF00; /* Drop GPO0 */ - tmp = INB(base + 0x4C); - tmp &= ~0x01; - OUTB(tmp, base + 0x4C); + tmp = INL(base + 0x4C); + if (raise) + tmp |= 1U << gpio; + else + tmp &= ~(1U << gpio); + OUTL(tmp, base + 0x4C); return 0; } @@ -1051,6 +1071,14 @@ } /** + * Suited for Soyo SY-7VCA: Pro133A + VT82C686. + */ +static int via_apollo_gpo0_lower(const char *name) +{ + return via_apollo_gpo_set(0, 0); +} + +/** * Enable some GPIO pin on SiS southbridge. * Suited for MSI 651M-L: SiS651 / SiS962 */ @@ -1355,7 +1383,7 @@ {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, - {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, OK, board_soyo_sy_7vca}, + {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower}, {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, "Tekram", "P6Pro-A5", 256, OK, NULL}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise},

1 0

[PATCH 04/11] Rebased Board Enable Patch: Abit KN8 Ultra
by Sean Nelson 19 Mar '10

19 Mar '10

patch by Chris <zinx+flashrom(a)zenthought.org> --- board_enable.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index 4fe3fa1..36bf6e4 100644 --- a/board_enable.c +++ b/board_enable.c @@ -539,26 +539,34 @@ static int nvidia_mcp_gpio_set(int gpio, int raise) return 0; } /** * Suited for ASUS M2NBP-VM CSM: nVidia MCP51. */ static int nvidia_mcp_gpio0_raise(const char *name) { return nvidia_mcp_gpio_set(0x00, 1); } /** + * Suited for Abit KN8 Ultra: nVidia CK804. + */ +static int nvidia_mcp_gpio2_lower(const char *name) +{ + return nvidia_mcp_gpio_set(0x02, 0); +} + +/** * Suited for MSI K8N Neo4: nVidia CK804. * Suited for MSI K8N GM2-L: nVidia MCP51. */ static int nvidia_mcp_gpio2_raise(const char *name) { return nvidia_mcp_gpio_set(0x02, 1); } /** * Suited for ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04. */ static int nvidia_mcp_gpio10_raise(const char *name) { @@ -1269,26 +1277,27 @@ static int it8712f_gpio3_1_raise(const char *name) * legacy bios is installed and when autodetection is not possible, these ids * can be used to identify the board through the -m command line argument. * * When a board is identified through its coreboot ids (in both cases), the * main pci ids are still required to match, as a safeguard. */ /* Please keep this list alphabetically ordered by vendor/board name. */ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, + {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, "Abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower}, {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "Abit", "VT6X4", 0, NT, via_apollo_gpo4_lower}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, NULL, "AOpen", "vKM400Am-S", 0, OK, it8705f_write_enable_2e}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V8X", 0, OK, board_asus_a7v8x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise}, {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e}, {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, "ASUS", "A8N", 0, NT, board_shuttle_fn25}, -- 1.6.6

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[commit] r953 - trunk
by repository service 19 Mar '10

19 Mar '10

Author: snelson Date: Fri Mar 19 23:39:24 2010 New Revision: 953 URL: http://flashrom.org/trac/coreboot/changeset/953 Log: Rebased Board Enable Patch: A8JM board_enable patch Signed-off-by: James Lancaster <deathstalker(a)gmail.com> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Fri Mar 19 23:37:29 2010 (r952) +++ trunk/board_enable.c Fri Mar 19 23:39:24 2010 (r953) @@ -920,6 +920,14 @@ } /** + * Suited for ASUS A8JM: Intel 945 + ICH7 + */ +static int intel_ich_gpio34_raise(const char *name) +{ + return intel_ich_gpio_set(34, 1); +} + +/** * Suited for MSI MS-7046: LGA775 + 915P + ICH6. */ static int intel_ich_gpio19_raise(const char *name) @@ -1300,6 +1308,7 @@ {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V8X", 0, OK, board_asus_a7v8x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise}, {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e}, + {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, "ASUS", "A8JM", 0, NT, intel_ich_gpio34_raise}, {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, "ASUS", "A8N", 0, NT, board_shuttle_fn25}, {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise}, {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise}, @@ -1333,7 +1342,7 @@ {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi}, {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower}, {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e}, - {0x8086, 0x27A0, 0, 0, 0x8086, 0x27b8, 0, 0, NULL, "kontron", "986lcd-m", "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m}, + {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m}, {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, "Mitac", "6513WU", 0, OK, board_mitac_6513wu}, {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v}, {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio4_4_raise_2e},

1 0

[commit] r952 - trunk
by repository service 19 Mar '10

19 Mar '10

Author: snelson Date: Fri Mar 19 23:37:29 2010 New Revision: 952 URL: http://flashrom.org/trac/coreboot/changeset/952 Log: Rebased Board Enable Patch: Abit KN8 Ultra patch by Chris <zinx+flashrom(a)zenthought.org> Signed-off-by: Sean Nelson <audiohacked(a)gmail.com> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Fri Mar 19 23:35:21 2010 (r951) +++ trunk/board_enable.c Fri Mar 19 23:37:29 2010 (r952) @@ -549,6 +549,14 @@ } /** + * Suited for Abit KN8 Ultra: nVidia CK804. + */ +static int nvidia_mcp_gpio2_lower(const char *name) +{ + return nvidia_mcp_gpio_set(0x02, 0); +} + +/** * Suited for MSI K8N Neo4: nVidia CK804. * Suited for MSI K8N GM2-L: nVidia MCP51. */ @@ -1279,6 +1287,7 @@ /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, + {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, "Abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower}, {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "Abit", "VT6X4", 0, NT, via_apollo_gpo4_lower}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise},

1 0

[PATCH 03/11] Rebased Board Enable Patch: Intel SE440BX-2
by Sean Nelson 19 Mar '10

19 Mar '10

This board has no subsystem IDs, but thankfully the DMI patch is in now, which is a real life safer. There are *WAY* to many 440BX/PIIX4 boards out there to match this without DMI. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- board_enable.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index 7b1fa12..4fe3fa1 100644 --- a/board_enable.c +++ b/board_enable.c @@ -693,26 +693,34 @@ static int intel_piix4_gpo_set(unsigned int gpo, int raise) return 0; } /** * Suited for EPoX EP-BX3, and maybe some other Intel 440BX based boards. */ static int board_epox_ep_bx3(const char *name) { return intel_piix4_gpo_set(22, 1); } /** + * Suited for Intel SE440BX-2 + */ +static int intel_piix4_gpo27_lower(const char *name) +{ + return intel_piix4_gpo_set(27, 0); +} + +/** * Set a GPIO line on a given intel ICH LPC controller. */ static int intel_ich_gpio_set(int gpio, int raise) { /* table mapping the different intel ICH LPC chipsets. */ static struct { uint16_t id; uint8_t base_reg; uint32_t bank0; uint32_t bank1; uint32_t bank2; } intel_ich_gpio_table[] = { {0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */ @@ -1304,26 +1312,27 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, NULL, "GIGABYTE", "GA-7VT600", 0, OK, it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, {0x10DE, 0x0360, 0x1458, 0x0C11, 0x10DE, 0x0369, 0x1458, 0x5001, NULL, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", 0, OK, it87xx_probe_spi_flash}, {0x10de, 0x03e0, 0, 0, 0x10DE, 0x03D0, 0, 0, NULL, NULL, NULL, "GIGABYTE", "GA-M61P-S3", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x7910, 0x1458, 0x5000, 0x1002, 0x438D, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-MA69VM-S2", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb000, NULL, NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb002, NULL, NULL, NULL, "GIGABYTE", "GA-MA78GM-S2H", 0, OK, it87xx_probe_spi_flash}, {0x1002, 0x438d, 0x1458, 0x5001, 0x1002, 0x5956, 0x1002, 0x5956, NULL, NULL, NULL, "GIGABYTE", "GA-MA790FX-DQ6", 0, OK, it87xx_probe_spi_flash}, {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable}, {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400}, {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise}, {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455}, {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi}, + {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower}, {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e}, {0x8086, 0x27A0, 0, 0, 0x8086, 0x27b8, 0, 0, NULL, "kontron", "986lcd-m", "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m}, {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, "Mitac", "6513WU", 0, OK, board_mitac_6513wu}, {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v}, {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio4_4_raise_2e}, {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v}, {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml}, {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise}, {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio4_4_raise_4e}, {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8N GM2-L)", 0, NT, nvidia_mcp_gpio2_raise}, {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, it8705f_write_enable_2e}, -- 1.6.6

1 1

[commit] r951 - trunk
by repository service 19 Mar '10

19 Mar '10

Author: snelson Date: Fri Mar 19 23:35:21 2010 New Revision: 951 URL: http://flashrom.org/trac/coreboot/changeset/951 Log: Rebased Board Enable Patch: Intel SE440BX-2 This board has no subsystem IDs, but thankfully the DMI patch is in now, which is a real life safer. There are *WAY* to many 440BX/PIIX4 boards out there to match this without DMI. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Fri Mar 19 23:30:49 2010 (r950) +++ trunk/board_enable.c Fri Mar 19 23:35:21 2010 (r951) @@ -703,6 +703,14 @@ } /** + * Suited for Intel SE440BX-2 + */ +static int intel_piix4_gpo27_lower(const char *name) +{ + return intel_piix4_gpo_set(27, 0); +} + +/** * Set a GPIO line on a given intel ICH LPC controller. */ static int intel_ich_gpio_set(int gpio, int raise) @@ -1314,6 +1322,7 @@ {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise}, {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455}, {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi}, + {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower}, {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e}, {0x8086, 0x27A0, 0, 0, 0x8086, 0x27b8, 0, 0, NULL, "kontron", "986lcd-m", "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m}, {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, "Mitac", "6513WU", 0, OK, board_mitac_6513wu},

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