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[PATCH] Avoid transaction errors on ICH SPI
by Carl-Daniel Hailfinger 28 May '10

28 May '10

ICH SPI can enforces address restrictions for all accesses which take an address (well, it could if the chipset implementation was not broken). Since exploiting the broken implementation is harder than conforming to the address restrictions wherever possible, conform to the address restrictions instead. This patch will eliminate a lot of transaction errors people were seeing (for probe, anyway). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-ichspi_avoid_transaction_error_use_bbar/flash.h =================================================================== --- flashrom-ichspi_avoid_transaction_error_use_bbar/flash.h (Revision 1015) +++ flashrom-ichspi_avoid_transaction_error_use_bbar/flash.h (Arbeitskopie) @@ -663,6 +663,8 @@ uint32_t spi_get_valid_read_addr(void); /* ichspi.c */ +extern int ichspi_lock; +extern uint32_t ichspi_bbar; int ich_init_opcodes(void); int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); Index: flashrom-ichspi_avoid_transaction_error_use_bbar/spi.c =================================================================== --- flashrom-ichspi_avoid_transaction_error_use_bbar/spi.c (Revision 1015) +++ flashrom-ichspi_avoid_transaction_error_use_bbar/spi.c (Arbeitskopie) @@ -207,8 +207,22 @@ return spi_programmer[spi_controller].write_256(flash, buf); } +/* + * Get the lowest allowed address for read accesses. This often happens to + * be the lowest allowed address for all commands which take an address. + * This is a programmer limitation. + */ uint32_t spi_get_valid_read_addr(void) { - /* Need to return BBAR for ICH chipsets. */ - return 0; + switch (spi_controller) { +#if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) + case SPI_CONTROLLER_ICH7: + /* Return BBAR for ICH chipsets. */ + return ichspi_bbar; +#endif +#endif + default: + return 0; + } } Index: flashrom-ichspi_avoid_transaction_error_use_bbar/chipset_enable.c =================================================================== --- flashrom-ichspi_avoid_transaction_error_use_bbar/chipset_enable.c (Revision 1015) +++ flashrom-ichspi_avoid_transaction_error_use_bbar/chipset_enable.c (Arbeitskopie) @@ -36,8 +36,6 @@ #if defined(__i386__) || defined(__x86_64__) -extern int ichspi_lock; - static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) { uint8_t tmp; @@ -515,8 +513,9 @@ msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, mmio_readl(spibar + offs + 4), i); } + ichspi_bbar = mmio_readl(spibar + 0x50); msg_pdbg("0x50: 0x%08x (BBAR)\n", - mmio_readl(spibar + 0x50)); + ichspi_bbar); msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(spibar + 0x54)); msg_pdbg("0x56: 0x%04x (OPTYPE)\n", @@ -587,8 +586,9 @@ mmio_readl(spibar + 0x98)); msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", mmio_readl(spibar + 0x9C)); + ichspi_bbar = mmio_readl(spibar + 0xA0); msg_pdbg("0xA0: 0x%08x (BBAR)\n", - mmio_readl(spibar + 0xA0)); + ichspi_bbar); msg_pdbg("0xB0: 0x%08x (FDOC)\n", mmio_readl(spibar + 0xB0)); if (tmp2 & (1 << 15)) { Index: flashrom-ichspi_avoid_transaction_error_use_bbar/ichspi.c =================================================================== --- flashrom-ichspi_avoid_transaction_error_use_bbar/ichspi.c (Revision 1015) +++ flashrom-ichspi_avoid_transaction_error_use_bbar/ichspi.c (Arbeitskopie) @@ -103,6 +103,8 @@ /* ICH SPI configuration lock-down. May be set during chipset enabling. */ int ichspi_lock = 0; +uint32_t ichspi_bbar = 0; + typedef struct _OPCODE { uint8_t opcode; //This commands spi opcode uint8_t spi_type; //This commands spi type @@ -327,6 +329,35 @@ return 0; } +/* + * Try to set BBAR (BIOS Base Address Register), but read back the value in case + * it didn't stick. + */ +void ich_set_bbar(uint32_t minaddr) +{ + switch (spi_controller) { + case SPI_CONTROLLER_ICH7: + mmio_writel(minaddr, spibar + 0x50); + ichspi_bbar = mmio_readl(spibar + 0x50); + /* We don't have any option except complaining. */ + if (ichspi_bbar != minaddr) + msg_perr("Setting BBAR failed!\n"); + break; + case SPI_CONTROLLER_ICH9: + mmio_writel(minaddr, spibar + 0xA0); + ichspi_bbar = mmio_readl(spibar + 0xA0); + /* We don't have any option except complaining. */ + if (ichspi_bbar != minaddr) + msg_perr("Setting BBAR failed!\n"); + break; + default: + /* Not sure if BBAR actually exists on VIA. */ + msg_pdbg("Setting BBAR is not implemented for VIA yet.\n"); + break; + } + +} + /* This function generates OPCODES from or programs OPCODES to ICH according to * the chipset's SPI configuration lock. * @@ -341,13 +372,18 @@ return 0; if (ichspi_lock) { - msg_pdbg("Generating OPCODES... "); + msg_pdbg("Reading OPCODES... "); curopcodes_done = &O_EXISTING; rc = generate_opcodes(curopcodes_done); } else { msg_pdbg("Programming OPCODES... "); curopcodes_done = &O_ST_M25P; rc = program_opcodes(curopcodes_done); + /* Technically not part of opcode init, but it allows opcodes + * to run without transaction errors by setting the lowest + * allowed address to zero. + */ + ich_set_bbar(0); } if (rc) { -- http://www.hailfinger.org/

2 3

[commit] r1016 - trunk
by repository service 28 May '10

28 May '10

Author: hailfinger Date: Fri May 28 17:53:08 2010 New Revision: 1016 URL: http://flashrom.org/trac/coreboot/changeset/1016 Log: ICH SPI can enforce address restrictions for all accesses which take an address (well, it could if the chipset implementation was not broken). Since exploiting the broken implementation is harder than conforming to the address restrictions wherever possible, conform to the address restrictions instead. This patch eliminates a lot of transaction errors people were seeing on chip probe. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/chipset_enable.c trunk/flash.h trunk/ichspi.c trunk/spi.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Thu May 27 00:29:51 2010 (r1015) +++ trunk/chipset_enable.c Fri May 28 17:53:08 2010 (r1016) @@ -36,8 +36,6 @@ #if defined(__i386__) || defined(__x86_64__) -extern int ichspi_lock; - static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) { uint8_t tmp; @@ -515,8 +513,9 @@ msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, mmio_readl(spibar + offs + 4), i); } + ichspi_bbar = mmio_readl(spibar + 0x50); msg_pdbg("0x50: 0x%08x (BBAR)\n", - mmio_readl(spibar + 0x50)); + ichspi_bbar); msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(spibar + 0x54)); msg_pdbg("0x56: 0x%04x (OPTYPE)\n", @@ -587,8 +586,9 @@ mmio_readl(spibar + 0x98)); msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", mmio_readl(spibar + 0x9C)); + ichspi_bbar = mmio_readl(spibar + 0xA0); msg_pdbg("0xA0: 0x%08x (BBAR)\n", - mmio_readl(spibar + 0xA0)); + ichspi_bbar); msg_pdbg("0xB0: 0x%08x (FDOC)\n", mmio_readl(spibar + 0xB0)); if (tmp2 & (1 << 15)) { Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Thu May 27 00:29:51 2010 (r1015) +++ trunk/flash.h Fri May 28 17:53:08 2010 (r1016) @@ -663,6 +663,8 @@ uint32_t spi_get_valid_read_addr(void); /* ichspi.c */ +extern int ichspi_lock; +extern uint32_t ichspi_bbar; int ich_init_opcodes(void); int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Thu May 27 00:29:51 2010 (r1015) +++ trunk/ichspi.c Fri May 28 17:53:08 2010 (r1016) @@ -103,6 +103,8 @@ /* ICH SPI configuration lock-down. May be set during chipset enabling. */ int ichspi_lock = 0; +uint32_t ichspi_bbar = 0; + typedef struct _OPCODE { uint8_t opcode; //This commands spi opcode uint8_t spi_type; //This commands spi type @@ -327,6 +329,34 @@ return 0; } +/* + * Try to set BBAR (BIOS Base Address Register), but read back the value in case + * it didn't stick. + */ +void ich_set_bbar(uint32_t minaddr) +{ + switch (spi_controller) { + case SPI_CONTROLLER_ICH7: + mmio_writel(minaddr, spibar + 0x50); + ichspi_bbar = mmio_readl(spibar + 0x50); + /* We don't have any option except complaining. */ + if (ichspi_bbar != minaddr) + msg_perr("Setting BBAR failed!\n"); + break; + case SPI_CONTROLLER_ICH9: + mmio_writel(minaddr, spibar + 0xA0); + ichspi_bbar = mmio_readl(spibar + 0xA0); + /* We don't have any option except complaining. */ + if (ichspi_bbar != minaddr) + msg_perr("Setting BBAR failed!\n"); + break; + default: + /* Not sure if BBAR actually exists on VIA. */ + msg_pdbg("Setting BBAR is not implemented for VIA yet.\n"); + break; + } +} + /* This function generates OPCODES from or programs OPCODES to ICH according to * the chipset's SPI configuration lock. * @@ -341,13 +371,18 @@ return 0; if (ichspi_lock) { - msg_pdbg("Generating OPCODES... "); + msg_pdbg("Reading OPCODES... "); curopcodes_done = &O_EXISTING; rc = generate_opcodes(curopcodes_done); } else { msg_pdbg("Programming OPCODES... "); curopcodes_done = &O_ST_M25P; rc = program_opcodes(curopcodes_done); + /* Technically not part of opcode init, but it allows opcodes + * to run without transaction errors by setting the lowest + * allowed address to zero. + */ + ich_set_bbar(0); } if (rc) { @@ -743,6 +778,19 @@ opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { addr = (writearr[1] << 16) | (writearr[2] << 8) | (writearr[3] << 0); + switch (spi_controller) { + case SPI_CONTROLLER_ICH7: + case SPI_CONTROLLER_ICH9: + if (addr < ichspi_bbar) { + msg_perr("%s: Address 0x%06x below allowed " + "range 0x%06x-0xffffff\n", __func__, + addr, ichspi_bbar); + return SPI_INVALID_ADDRESS; + } + break; + default: + break; + } } /* translate read/write array/count */ Modified: trunk/spi.c ============================================================================== --- trunk/spi.c Thu May 27 00:29:51 2010 (r1015) +++ trunk/spi.c Fri May 28 17:53:08 2010 (r1016) @@ -207,8 +207,22 @@ return spi_programmer[spi_controller].write_256(flash, buf); } +/* + * Get the lowest allowed address for read accesses. This often happens to + * be the lowest allowed address for all commands which take an address. + * This is a programmer limitation. + */ uint32_t spi_get_valid_read_addr(void) { - /* Need to return BBAR for ICH chipsets. */ - return 0; + switch (spi_controller) { +#if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) + case SPI_CONTROLLER_ICH7: + /* Return BBAR for ICH chipsets. */ + return ichspi_bbar; +#endif +#endif + default: + return 0; + } }

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[PATCH 1/3] Sort boards alphabetically.
by Peter Lemenkov 27 May '10

27 May '10

Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- board_enable.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board_enable.c b/board_enable.c index 4251601..963bf58 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1402,12 +1402,12 @@ struct board_pciid_enable board_pciid_enables[] = { {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, "Abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise}, {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "Abit", "VT6X4", 0, OK, via_apollo_gpo4_lower}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, - {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, NULL, "AOpen", "vKM400Am-S", 0, OK, it8705f_write_enable_2e}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x}, + {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V8X", 0, OK, board_asus_a7v8x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise}, @@ -1457,9 +1457,9 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower}, - {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, "Tekram", "P6Pro-A5", 256, OK, NULL}, {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, + {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise}, {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise}, #endif -- 1.6.6.1

2 2

[PATCH 2/3] This board is not an 'Albatron PM266A' but a 'Albatron PM266A Pro'.
by Peter Lemenkov 27 May '10

27 May '10

It seems that this board is actually a 'Pro' version. At least it's addressed as 'Pro' in the list of boards, which requires board_enable. Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- board_enable.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/board_enable.c b/board_enable.c index 963bf58..f6462d9 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1403,7 +1403,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "Abit", "VT6X4", 0, OK, via_apollo_gpo4_lower}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e}, - {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A", 0, OK, w836xx_memw_enable_2e}, + {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, NULL, "AOpen", "vKM400Am-S", 0, OK, it8705f_write_enable_2e}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x}, -- 1.6.6.1

2 1

[commit] r1015 - trunk
by repository service 27 May '10

27 May '10

Author: uwe Date: Thu May 27 00:29:51 2010 New Revision: 1015 URL: http://flashrom.org/trac/coreboot/changeset/1015 Log: It seems that this board is actually a 'Pro' version. At least it's addressed as 'Pro' in the list of boards, which requires board_enable. See also: http://www.flashrom.org/pipermail/flashrom/2009-July/000003.html Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Thu May 27 00:26:44 2010 (r1014) +++ trunk/board_enable.c Thu May 27 00:29:51 2010 (r1015) @@ -1403,7 +1403,7 @@ {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "Abit", "VT6X4", 0, OK, via_apollo_gpo4_lower}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e}, - {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A", 0, OK, w836xx_memw_enable_2e}, + {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, NULL, "AOpen", "vKM400Am-S", 0, OK, it8705f_write_enable_2e}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x},

1 0

[commit] r1014 - trunk
by repository service 27 May '10

27 May '10

Author: uwe Date: Thu May 27 00:26:44 2010 New Revision: 1014 URL: http://flashrom.org/trac/coreboot/changeset/1014 Log: Sort boards in board-enable table alphabetically. Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Wed May 26 03:45:41 2010 (r1013) +++ trunk/board_enable.c Thu May 27 00:26:44 2010 (r1014) @@ -1402,23 +1402,23 @@ {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, "Abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise}, {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "Abit", "VT6X4", 0, OK, via_apollo_gpo4_lower}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, - {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, NULL, "AOpen", "vKM400Am-S", 0, OK, it8705f_write_enable_2e}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x}, + {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise}, + {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V8X", 0, OK, board_asus_a7v8x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise}, - {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e}, {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, "ASUS", "A8JM", 0, NT, intel_ich_gpio34_raise}, - {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, "ASUS", "A8N", 0, NT, board_shuttle_fn25}, {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI", NULL, NULL, "ASUS", "A8N-LA", 0, NT, nvidia_mcp_gpio0_raise}, + {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, "ASUS", "A8N", 0, NT, board_shuttle_fn25}, {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise}, {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise}, - {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise}, {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise}, {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise}, {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, @@ -1431,8 +1431,8 @@ {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e}, {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise}, {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", "EPoX", "EP-BX3", 0, OK, board_epox_ep_bx3}, - {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, NULL, "GIGABYTE", "GA-7VT600", 0, OK, it8705f_write_enable_2e}, + {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable}, {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400}, @@ -1444,6 +1444,7 @@ {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e}, {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m}, {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, "Mitac", "6513WU", 0, OK, board_mitac_6513wu}, + {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v}, {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio4_4_raise_2e}, {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v}, @@ -1451,15 +1452,14 @@ {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise}, {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio4_4_raise_4e}, {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8N GM2-L)", 0, NT, nvidia_mcp_gpio2_raise}, - {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0}, {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower}, - {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, "Tekram", "P6Pro-A5", 256, OK, NULL}, {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, + {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise}, {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise}, #endif

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[PATCH 1/1] Unify board info handling
by Peter Lemenkov 26 May '10

26 May '10

Hello All! I'm requesting for your comments for this change. With this patch boards info is stored in one common place. Previously, the information about different boards was spreaded between few different places, and manual synchronization was required (which already led to some discrepancies between them). So with this patch marking new boards as working based on user's status reports would me much easy than before. Additionally, there is no artificial separation of boards for 'working', 'working with board enable procedure' and 'does not working' - all boards are listed in one big table with proper status mark. This should improve usability, because user would no longer require to traverse all these lists while checking the status of his board. I also ensured that boards are sorted alphabetically and changed name for Albatron's PM266A board to match one, listed among boards which requires write-enable (PM266A Pro). Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- board.h | 235 ++++++++++++++++++++++++++++++++ board_enable.c | 6 +- flash.h | 9 -- print.c | 255 +++++------------------------------- print_wiki.c | 407 +++++--------------------------------------------------- 5 files changed, 305 insertions(+), 607 deletions(-) create mode 100644 board.h diff --git a/board.h b/board.h new file mode 100644 index 0000000..92a8d36 --- /dev/null +++ b/board.h @@ -0,0 +1,235 @@ +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#if INTERNAL_SUPPORT == 1 + +struct board_info { + const char *vendor; + const char *name; + const char *url; + const char *note; + int working; + int write_enable; +}; + +/* Please keep this list alphabetically ordered by vendor/board. */ +const static struct board_info boards_known[] = { +#if defined(__i386__) || defined(__x86_64__) + /* Verified working boards that don't need write-enables. */ + { "A-Trend", "ATC-6220", "http://www.motherboard.cz/mb/atrend/atc6220.htm", NULL, 1, 0 }, + { "Abit", "AX8", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=…", NULL, 1, 0 }, + { "Abit", "Fatal1ty F-I90HD", "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?pMODEL_NA…", NULL, 1, 0 }, + { "Abit", "IP35", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=LG…", NULL, 1, 1 }, + { "Abit", "IP35 Pro", "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?fMTYPE=LG…", NULL, 1, 1 }, + { "Abit", "IS-10", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NA…", NULL, 0, 0 }, + { "Abit", "NF7-S", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=So…", NULL, 1, 1 }, + { "Abit", "VT6X4", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=Sl…", NULL, 1, 1 }, + { "Acorp", "6A815EPD", "http://web.archive.org/web/20021206163652/www.acorp.com.tw/English/default.…", NULL, 1, 1 }, + { "Advantech", "PCM-5820", "http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm", NULL, 1, 0 }, + { "agami", "Aruma", "http://web.archive.org/web/20080212111524/http://www.agami.com/site/ais-600…", NULL, 1, 1 }, + { "Albatron", "PM266A Pro", "http://www.albatron.com.tw/English/Product/MB/pro_detail.asp?rlink=Overview…", NULL, 1, 1 }, /* FIXME */ + { "AOpen", "vKM400Am-S", "http://usa.aopen.com/products_detail.aspx?Auno=824", NULL, 1, 1 }, + { "Artec Group", "DBE61", "http://wiki.thincan.org/DBE61", NULL, 1, 1 }, + { "Artec Group", "DBE62", "http://wiki.thincan.org/DBE62", NULL, 1, 1 }, + { "ASI", "MB-5BLMP", "http://www.hojerteknik.com/winnet.htm", "Used in the IGEL WinNET III thin client.", 1, 0 }, + { "ASRock", "A770CrossFire", "http://www.asrock.com/mb/overview.asp?Model=A770CrossFire&s=AM2\%2b", NULL, 1, 0 }, + { "ASRock", "K7VT4A+", "http://www.asrock.com/mb/overview.asp?Model=K7VT4A%%2b&s=", NULL, 0, 0 }, + { "ASRock", "K8S8X", "http://www.asrock.com/mb/overview.asp?Model=K8S8X", "The Super I/O isn't found on this board. See http://www.flashrom.org/pipermail/flashrom/2009-November/000937.html.", 1, 0 }, + { "ASRock", "P4i65GV", NULL, NULL, 1, 1}, + { "ASRock", "M3A790GXH/128M", "http://www.asrock.com/MB/overview.asp?Model=M3A790GXH/128M", NULL, 1, 0 }, + { "ASUS", "A7N8X Deluxe", "http://www.asus.com/product.aspx?P_ID=wAsRYm41KTp78MFC", NULL, 1, 0 }, + { "ASUS", "A7N8X-E Deluxe", "http://www.asus.com/product.aspx?P_ID=TmQtPJv4jIxmL9C2", NULL, 1, 0 }, + { "ASUS", "A7V133", "ftp://ftp.asus.com.tw/pub/ASUS/mb/socka/kt133a/a7v133/", NULL, 1, 0 }, + { "ASUS", "A7V400-MX", "http://www.asus.com/product.aspx?P_ID=hORgEHRBDLMfwAwx", NULL, 1, 0 }, + { "ASUS", "A7V600-X", "http://www.asus.com/product.aspx?P_ID=L2XYS0rmtCjeOr4k", NULL, 1, 1 }, + { "ASUS", "A7V8X", "http://www.asus.com/product.aspx?P_ID=qfpaGrAy2kLVo0f2", NULL, 1, 1 }, + { "ASUS", "A7V8X-MX", "http://www.asus.com/product.aspx?P_ID=SEJOOYqfuQPitx2H", NULL, 1, 0 }, + { "ASUS", "A7V8X-MX SE", "http://www.asus.com/product.aspx?P_ID=1guVBT1qV5oqhHyZ", NULL, 1, 1 }, + { "ASUS", "A7V8X-X", "http://www.asus.com/product.aspx?P_ID=YcXfRrWHZ9RKoVmw", NULL, 1, 1 }, + { "ASUS", "A8N-E", "http://www.asus.com/product.aspx?P_ID=DzbA8hgqchMBOVRz", NULL, 1, 0 }, + { "ASUS", "A8N-SLI", "http://www.asus.com/product.aspx?P_ID=J9FKa8z2xVId3pDK", NULL, 1, 0 }, + { "ASUS", "A8N-SLI Premium", "http://www.asus.com/product.aspx?P_ID=nbulqxniNmzf0mH1", NULL, 1, 0 }, + { "ASUS", "A8NE-FM/S", "http://www.hardwareschotte.de/hardware/preise/proid_1266090/preis_ASUS+A8NE…", NULL, 1, 0 }, + { "ASUS", "A8V Deluxe", "http://www.asus.com/product.aspx?P_ID=tvpdgPNCPaABZRVU", NULL, 1, 0 }, + { "ASUS", "A8V-E Deluxe", "http://www.asus.com/product.aspx?P_ID=hQBPIJWEZnnGAZEh", NULL, 1, 0 }, + { "ASUS", "A8V-E SE", "http://www.asus.com/product.aspx?P_ID=VMfiJJRYTHM4gXIi", "See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html.", 1, 0 }, + { "ASUS", "K8V", "http://www.asus.com/product.aspx?P_ID=fG2KZOWF7v6MRFRm", NULL, 1, 0 }, + { "ASUS", "K8V SE Deluxe", "http://www.asus.com/product.aspx?P_ID=65HeDI8XM1u6Uy6o", NULL, 1, 0 }, + { "ASUS", "K8V-X SE", "http://www.asus.com/product.aspx?P_ID=lzDXlbBVHkdckHVr", NULL, 1, 0 }, + { "ASUS", "M2A-MX", "http://www.asus.com/product.aspx?P_ID=BmaOnPewi1JgltOZ", NULL, 1, 0 }, + { "ASUS", "M2A-VM", "http://www.asus.com/product.aspx?P_ID=St3pWpym8xXpROQS", "See http://www.coreboot.org/pipermail/coreboot/2007-September/025281.html.", 1, 0 }, + { "ASUS", "M2N-E", "http://www.asus.com/product.aspx?P_ID=NFlvt10av3F7ayQ9", "If the machine doesn't come up again after flashing, try resetting the NVRAM(CMOS). The MAC address of the onboard network card will change to the value stored in the new image, so backup the old address first. See http://www.flashrom.org/pipermail/flashrom/2009-November/000879.html", 1, 0 }, + { "ASUS", "M2NBP-VM CSM", "http://www.asus.com/product.aspx?P_ID=MnOfzTGd2KkwG0rF", NULL, 1, 1 }, + { "ASUS", "M2V", "http://www.asus.com/product.aspx?P_ID=OqYlEDFfF6ZqZGvp", NULL, 1, 0 }, + { "ASUS", "M2V-MX", "http://www.asus.com/product.aspx?P_ID=7grf8Ci4yxnqzt3z", NULL, 1, 1 }, + { "ASUS", "M3A78-EM", "http://www.asus.com/product.aspx?P_ID=KjpYqzmAd9vsTM2D", NULL, 1, 0 }, + { "ASUS", "MEW-AM", "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/", NULL, 0, 0 }, + { "ASUS", "MEW-VM", "http://www.elhvb.com/mboards/OEM/HP/manual/ASUS%20MEW-VM.htm", NULL, 0, 0 }, + { "ASUS", "P2B", "ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b/", NULL, 1, 0 }, + { "ASUS", "P2B-D", "ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-d/", NULL, 1, 0 }, + { "ASUS", "P2B-DS", "ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-ds/", NULL, 1, 0 }, + { "ASUS", "P2B-F", "ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-d/", NULL, 1, 0 }, + { "ASUS", "P2L97-S", "ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440lx/p2l97-s/", NULL, 1, 0 }, + { "ASUS", "P3B-F", "ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p3b-f/", NULL, 0, 0 }, + { "ASUS", "P4B266", "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock478/p4b266/", NULL, 1, 1 }, + { "ASUS", "P4B266-LM", "http://esupport.sony.com/US/perl/swu-list.pl?mdl=PCVRX650", NULL, 1, 1 }, + { "ASUS", "P4C800-E Deluxe", "http://www.asus.com/product.aspx?P_ID=cFuVCr9bXXCckmcK", NULL, 1, 1 }, + { "ASUS", "P4P800-E Deluxe", "http://www.asus.com/product.aspx?P_ID=INIJUvLlif7LHp3g", NULL, 1, 1 }, + { "ASUS", "P5A", "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock7/ali/p5a/", NULL, 1, 1 }, + { "ASUS", "P5B", "ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/P5B/", NULL, 1, 0 }, + { "ASUS", "P5B-Deluxe", "http://www.asus.com/product.aspx?P_ID=bswT66IBSb2rEWNa", NULL, 1, 0 }, + { "ASUS", "P5BV-M", "ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/P5B-VM/", NULL, 0, 0 }, + { "ASUS", "P5KC", "http://www.asus.com/product.aspx?P_ID=fFZ8oUIGmLpwNMjj", NULL, 1, 0 }, + { "ASUS", "P5L-MX", "http://www.asus.com/product.aspx?P_ID=X70d3NCzH2DE9vWH", NULL, 1, 0 }, + { "ASUS", "P5ND2-SLI Deluxe", "http://www.asus.com/product.aspx?P_ID=WY7XroDuUImVbgp5", NULL, 1, 1 }, + { "ASUS", "P6T Deluxe", "http://www.asus.com/product.aspx?P_ID=vXixf82co6Q5v0BZ", NULL, 1, 0 }, + { "ASUS", "P6T Deluxe V2", "http://www.asus.com/product.aspx?P_ID=iRlP8RG9han6saZx", NULL, 1, 0 }, + { "BCOM", "WinNET100", "http://www.coreboot.org/BCOM_WINNET100", "Used in the IGEL-316 thin client.", 1, 0 }, + { "Biostar", "M6TBA", "ftp://ftp.biostar-usa.com/manuals/M6TBA/", NULL, 0, 0 }, + { "Biostar", "P4M80-M4", "http://www.biostar-usa.com/mbdetails.asp?model=p4m80-m4", NULL, 1, 1 }, + { "Boser", "HS-6637", "http://www.boser.com.tw/manual/HS-62376637v3.4.pdf", NULL, 0, 0 }, + { "Dell", "PowerEdge 1850", "http://support.dell.com/support/edocs/systems/pe1850/en/index.htm", NULL, 1, 1 }, + { "DFI", "855GME-MGF", "http://www.dfi.com.tw/portal/CM/cmproduct/XX_cmproddetail/XX_WbProdsWindow?…", NULL, 0, 0 }, + { "DFI", "Blood-Iron P35 T2RL", "http://lp.lanparty.com.tw/portal/CM/cmproduct/XX_cmproddetail/XX_WbProdsWin…", NULL, 1, 0 }, + { "Elitegroup", "K7S5A", "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=279&…", NULL, 1, 0 }, + { "Elitegroup", "K7S6A", "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=77&C…", NULL, 1, 1 }, + { "Elitegroup", "K7VTA3", "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=264&…", NULL, 1, 1 }, + { "Elitegroup", "P6VAP-A+", "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=117&…", NULL, 1, 0 }, + { "EPoX", "EP-8K5A2", "http://www.epox.com/product.asp?ID=EP-8K5A2", NULL, 1, 1 }, + { "EPoX", "EP-8RDA3+", "http://www.epox.com/product.asp?ID=EP-8RDA3plus", NULL, 1, 1 }, + { "EPoX", "EP-BX3", "http://www.epox.com/product.asp?ID=EP-BX3", NULL, 1, 1 }, + { "FIC", "VA-502", "ftp://ftp.fic.com.tw/motherboard/manual/socket7/va-502/", NULL, 0, 0 }, + { "GIGABYTE", "GA-2761GXDK", "http://www.computerbase.de/news/hardware/mainboards/amd-systeme/2007/mai/gi…", NULL, 1, 0 }, + { "GIGABYTE", "GA-6BXC", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…", NULL, 1, 0 }, + { "GIGABYTE", "GA-6BXDU", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…", NULL, 1, 0 }, + { "GIGABYTE", "GA-6ZMA", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…", NULL, 1, 0 }, + { "GIGABYTE", "GA-7VT600", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…", NULL, 1, 1 }, + { "GIGABYTE", "GA-7ZM", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…", "Works fine if you remove jumper JP9 on the board and disable the flash protection BIOS option.", 1, 1 }, + { "GIGABYTE", "GA-965P-DS4", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…", NULL, 1, 0 }, + { "GIGABYTE", "GA-EP35-DS3L", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…", NULL, 1, 0 }, + { "GIGABYTE", "GA-EX58-UD4P", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…", NULL, 1, 0 }, + { "GIGABYTE", "GA-K8N-SLI", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…", NULL, 1, 1 }, + { "GIGABYTE", "GA-M57SLI-S4", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…", NULL, 1, 0 }, + { "GIGABYTE", "GA-M61P-S3", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…", NULL, 1, 0 }, + { "GIGABYTE", "GA-MA69VM-S2", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…", NULL, 1, 0 }, + { "GIGABYTE", "GA-MA770T-UD3P", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…", NULL, 1, 0 }, + { "GIGABYTE", "GA-MA78G-DS3H", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…", NULL, 1, 0 }, /* TODO: Rev 1.x or 2.x? */ + { "GIGABYTE", "GA-MA78GM-S2H", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…", NULL, 1, 0 }, /* TODO: Rev. 1.0, 1.1, or 2.x? */ + { "GIGABYTE", "GA-MA78GPM-DS2H", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…", NULL, 1, 0 }, + { "GIGABYTE", "GA-MA790FX-DQ6", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…", NULL, 1, 0 }, + { "GIGABYTE", "GA-MA790GP-DS4H", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…", NULL, 1, 0 }, + { "HP", "DL145 G3", "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c008…", NULL, 1, 1 }, + { "HP", "Vectra VL400 PC", "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c000…", NULL, 1, 1 }, + { "HP", "Vectra VL420 SFF PC", "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c000…", NULL, 1, 1 }, + { "IBM", "x3455", "http://www-03.ibm.com/systems/x/hardware/rack/x3455/index.html", NULL, 1, 1 }, + { "Intel", "D201GLY", "http://www.intel.com/support/motherboards/desktop/d201gly/index.htm", NULL, 1, 1 }, + { "Intel", "EP80759", NULL, NULL, 1, 0 }, + { "IWILL", "DK8-HTX", "http://web.archive.org/web/20060507170150/http://www.iwill.net/product_2.as…", NULL, 1, 1 }, + { "Jetway", "J7F4K1G5D-PB", "http://www.jetway.com.tw/jetway/system/productshow2.asp?id=389&proname=J7F4…", NULL, 1, 0 }, + { "Kontron", "986LCD-M", "http://de.kontron.com/products/boards+and+mezzanines/embedded+motherboards/…", NULL, 1, 1 }, + { "Mitac", "6513WU", "http://web.archive.org/web/20050313054828/http://www.mitac.com/micweb/produ…", NULL, 1, 1 }, + { "MSI", "MS-6153", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=336", NULL, 1, 0 }, + { "MSI", "MS-6156", "http://uk.ts.fujitsu.com/rl/servicesupport/techsupport/boards/Motherboards/…", NULL, 1, 0 }, + { "MSI", "MS-6178", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=343", "Immediately powers off if you try to hot-plug the chip. However, this does '''not''' happen if you use coreboot.", 0, 0 }, + { "MSI", "MS-6330 (K7T Turbo)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=327", NULL, 1, 0 }, + { "MSI", "MS-6570 (K7N2)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=519", NULL, 1, 0 }, + { "MSI", "MS-6590 (KT4 Ultra)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=502", NULL, 1, 1 }, + { "MSI", "MS-6702E (K8T Neo2-F)","http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=588", NULL, 1, 1 }, + { "MSI", "MS-6712 (KT4V)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=505", NULL, 1, 1 }, + { "MSI", "MS-7005 (651M-L)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=559", NULL, 1, 1 }, + { "MSI", "MS-7046", "http://www.heimir.de/ms7046/", NULL, 1, 1 }, + { "MSI", "MS-7065", "http://browse.geekbench.ca/geekbench2/view/53114", NULL, 1, 0 }, + { "MSI", "MS-7135 (K8N Neo3)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=170", NULL, 1, 1 }, + { "MSI", "MS-7168 (Orion)", "http://support.packardbell.co.uk/uk/item/index.php?i=spec_orion&pi=platform…", NULL, 1, 0 }, + { "MSI", "MS-7236 (945PL Neo3)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1173", NULL, 1, 0 }, + { "MSI", "MS-7255 (P4M890M)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1082", NULL, 1, 0 }, + { "MSI", "MS-7260 (K9N Neo)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=255", "Interestingly flashrom does not work when the vendor BIOS is booted, but it ''does'' work flawlessly when the machine is booted with coreboot.", 0, 0 }, + { "MSI", "MS-7312 (K9MM-V)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1104", NULL, 1, 0 }, + { "MSI", "MS-7345 (P35 Neo2-FIR)","http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1261", NULL, 1, 0 }, + { "MSI", "MS-7368 (K9AG Neo2-Digital)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1241", NULL, 1, 0 }, + { "MSI", "MS-7376 (K9A2 Platinum)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1332", NULL, 1, 0 }, + { "NEC", "PowerMate 2000", "http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/", NULL, 1, 0 }, + { "Nokia", "IP530", NULL, NULL, 1, 1}, + { "PC Engines", "Alix.1c", "http://pcengines.ch/alix1c.htm", NULL, 1, 0 }, + { "PC Engines", "Alix.2c2", "http://pcengines.ch/alix2c2.htm", NULL, 1, 0 }, + { "PC Engines", "Alix.2c3", "http://pcengines.ch/alix2c3.htm", NULL, 1, 0 }, + { "PC Engines", "Alix.3c3", "http://pcengines.ch/alix3c3.htm", NULL, 1, 0 }, + { "PC Engines", "Alix.3d3", "http://pcengines.ch/alix3d3.htm", NULL, 1, 0 }, + { "PC Engines", "WRAP.2E", "http://pcengines.ch/wrap2e1.htm", NULL, 1, 0 }, + { "RCA", "RM4100", "http://www.settoplinux.org/index.php?title=RCA_RM4100", NULL, 1, 0 }, + { "Shuttle", "AK31", "http://www.motherboard.cz/mb/shuttle/AK31.htm", NULL, 1, 1 }, + { "Shuttle", "AK38N", "http://eu.shuttle.com/en/desktopdefault.aspx/tabid-36/558_read-9889/", NULL, 1, 1 }, + { "Shuttle", "FD37", "http://www.shuttle.eu/products/discontinued/barebones/sd37p2/", NULL, 1, 0 }, + { "Shuttle", "FN25", "http://www.shuttle.eu/products/discontinued/barebones/sn25p/?0=", NULL, 1, 1 }, + { "Soyo", "SY-5VD", "http://www.soyo.com/content/Downloads/163/&c=80&p=464&l=English", NULL, 0, 0 }, + { "Soyo", "SY-7VCA", "http://www.tomshardware.com/reviews/12-socket-370-motherboards,196-15.html", NULL, 1, 1 }, + { "Sun", "Blade x6250", "http://www.sun.com/servers/blades/x6250/", NULL, 1, 0 }, + { "Sun", "Fire x4150", "http://www.sun.com/servers/x64/x4150/", NULL, 0, 0 }, + { "Sun", "Fire x4200", "http://www.sun.com/servers/entry/x4200/", NULL, 0, 0 }, + { "Sun", "Fire x4540", "http://www.sun.com/servers/x64/x4540/", NULL, 0, 0 }, + { "Sun", "Fire x4600", "http://www.sun.com/servers/x64/x4600/", NULL, 0, 0 }, + { "Supermicro", "H8QC8", "http://www.supermicro.com/Aplus/motherboard/Opteron/nforce/H8QC8.cfm", NULL, 1, 0 }, + { "Supermicro", "X8DTT-F", "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTT-F.cfm", NULL, 1, 0 }, + { "T-Online", "S-100", "http://wiki.freifunk-hannover.de/T-Online_S_100", NULL, 1, 0 }, + { "Tekram", "P6Pro-A5", "http://www.motherboard.cz/mb/tekram/P6Pro-A5.htm", NULL, 1, 1 }, + { "Termtek", "TK-3370 (Rev:2.5B)", NULL, NULL, 1, 1 }, + { "Thomson", "IP1000", "http://www.settoplinux.org/index.php?title=Thomson_IP1000", NULL, 1, 0 }, + { "TriGem", "Lomita", "http://www.e4allupgraders.info/dir1/motherboards/socket370/lomita.shtml", NULL, 1, 0 }, + { "Tyan", "iS5375-1U", "http://www.tyan.com/product_board_detail.aspx?pid=610", NULL, 1, 0 }, + { "Tyan", "S1846", "http://www.tyan.com/archive/products/html/tsunamiatx.html", NULL, 1, 0 }, + { "Tyan", "S2466", "http://www.tyan.com/product_board_detail.aspx?pid=461", NULL, 1, 0 }, + { "Tyan", "S2498 (Tomcat K7M)", "http://www.tyan.com/archive/products/html/tomcatk7m.html", NULL, 1, 1 }, + { "Tyan", "S2881", "http://www.tyan.com/product_board_detail.aspx?pid=115", NULL, 1, 0 }, + { "Tyan", "S2882", "http://www.tyan.com/product_board_detail.aspx?pid=121", NULL, 1, 0 }, + { "Tyan", "S2882-D", "http://www.tyan.com/product_board_detail.aspx?pid=127", NULL, 1, 0 }, + { "Tyan", "S2891", "http://www.tyan.com/product_board_detail.aspx?pid=144", NULL, 1, 0 }, + { "Tyan", "S2892", "http://www.tyan.com/product_board_detail.aspx?pid=145", NULL, 1, 0 }, + { "Tyan", "S2895", "http://www.tyan.com/archive/products/html/thunderk8we.html", NULL, 1, 0 }, + { "Tyan", "S3095", "http://www.tyan.com/product_board_detail.aspx?pid=181", NULL, 1, 0 }, + { "Tyan", "S5180", "http://www.tyan.com/product_board_detail.aspx?pid=456", NULL, 1, 0 }, + { "Tyan", "S5191", "http://www.tyan.com/product_board_detail.aspx?pid=343", NULL, 1, 0 }, + { "Tyan", "S5197", "http://www.tyan.com/product_board_detail.aspx?pid=349", NULL, 1, 0 }, + { "Tyan", "S5211", "http://www.tyan.com/product_board_detail.aspx?pid=591", NULL, 1, 0 }, + { "Tyan", "S5211-1U", "http://www.tyan.com/product_board_detail.aspx?pid=593", NULL, 1, 0 }, + { "Tyan", "S5220", "http://www.tyan.com/product_board_detail.aspx?pid=597", NULL, 1, 0 }, + { "Tyan", "S5375", "http://www.tyan.com/product_board_detail.aspx?pid=566", NULL, 1, 0 }, + { "Tyan", "S5376G2NR/S5376WAG2NR","http://www.tyan.com/product_board_detail.aspx?pid=605", NULL, 1, 0 }, + { "Tyan", "S5377", "http://www.tyan.com/product_SKU_spec.aspx?ProductType=MB&pid=642&SKU=600000…", NULL, 1, 0 }, + { "Tyan", "S5382 (Tempest i5000PW)", "http://www.tyan.com/product_board_detail.aspx?pid=439", NULL, 1, 0 }, + { "Tyan", "S5397", "http://www.tyan.com/product_board_detail.aspx?pid=560", NULL, 1, 0 }, + { "VIA", "EPIA M/MII/...", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…", NULL, 1, 1 }, /* EPIA-MII link for now */ + { "VIA", "EPIA SP", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…", NULL, 1, 0 }, + { "VIA", "EPIA-CN", "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…", NULL, 1, 0 }, + { "VIA", "EPIA-EX15000G", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…", NULL, 1, 0 }, + { "VIA", "EPIA-LN", "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…", NULL, 1, 0 }, + { "VIA", "EPIA-M700", "http://via.com.tw/servlet/downloadSvl?motherboard_id=670&download_file_id=3…", NULL, 1, 0 }, + { "VIA", "EPIA-N/NL", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…", NULL, 1, 1 }, /* EPIA-N link for now */ + { "VIA", "EPIA-NX15000G", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…", NULL, 1, 0 }, + { "VIA", "NAB74X0", "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…", NULL, 1, 0 }, + { "VIA", "pc2500e", "http://www.via.com.tw/en/initiatives/empowered/pc2500_mainboard/index.jsp", NULL, 1, 0 }, + { "VIA", "PC3500G", "http://www.via.com.tw/en/initiatives/empowered/pc3500_mainboard/index.jsp", NULL, 1, 0 }, + { "VIA", "VB700X", "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…", NULL, 1, 0 }, +#endif /* defined(__i386__) || defined(__x86_64__) */ + + {}, +}; + +/* Please keep this list alphabetically ordered by vendor/board. */ +const static struct board_info laptops_known[] = { +#if defined(__i386__) || defined(__x86_64__) + { "Acer", "Aspire 1520", "http://support.acer.com/us/en/acerpanam/notebook/0000/Acer/Aspire1520/Aspir…", NULL, 1, 0 }, + { "Acer", "Aspire One", NULL, "http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html", 0, 0 }, + { "ASUS", "Eee PC 701 4G", "http://www.asus.com/product.aspx?P_ID=h6SPd3tEzLEsrEiS", "It seems the chip (25X40VSIG) is behind some SPI flash translation layer (likely in the EC, the ENE KB3310).", 0, 0 }, + { "Dell", "Latitude CPi A366XT", "http://www.coreboot.org/Dell_Latitude_CPi_A366XT", "The laptop immediately powers off if you try to hot-swap the chip. It's not yet tested if write/erase would work on this laptop.", 0, 0 }, + { "HP/Compaq", "nx9010", "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us…", "Hangs upon '''flashrom -V''' (needs hard power-cycle then).", 0, 0 }, + { "IBM/Lenovo", "Thinkpad T40p", "http://www.thinkwiki.org/wiki/Category:T40p", 0, 0 }, + { "IBM/Lenovo", "240", "http://www.stanford.edu/~bresnan//tp240.html", "Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later.", 0, 0 }, + { "Lenovo", "3000 V100 TF05Cxx", "http://www5.pc.ibm.com/europe/products.nsf/products?openagent&brand=Lenovo3…", NULL, 1, 0 }, +#endif /* defined(__i386__) || defined(__x86_64__) */ + + {}, +}; + +#endif + +#endif /* __BOARD_H__ */ diff --git a/board_enable.c b/board_enable.c index 4251601..f6462d9 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1402,12 +1402,12 @@ struct board_pciid_enable board_pciid_enables[] = { {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, "Abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise}, {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "Abit", "VT6X4", 0, OK, via_apollo_gpo4_lower}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, - {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e}, - {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A", 0, OK, w836xx_memw_enable_2e}, + {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, NULL, "AOpen", "vKM400Am-S", 0, OK, it8705f_write_enable_2e}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x}, + {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V8X", 0, OK, board_asus_a7v8x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise}, @@ -1457,9 +1457,9 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower}, - {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, "Tekram", "P6Pro-A5", 256, OK, NULL}, {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, + {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise}, {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise}, #endif diff --git a/flash.h b/flash.h index a201af3..c59f252 100644 --- a/flash.h +++ b/flash.h @@ -300,15 +300,6 @@ struct board_pciid_enable { extern struct board_pciid_enable board_pciid_enables[]; -struct board_info { - const char *vendor; - const char *name; -}; - -extern const struct board_info boards_ok[]; -extern const struct board_info boards_bad[]; -extern const struct board_info laptops_ok[]; -extern const struct board_info laptops_bad[]; #endif /* udelay.c */ diff --git a/print.c b/print.c index a8da65f..9df0816 100644 --- a/print.c +++ b/print.c @@ -22,6 +22,7 @@ #include <string.h> #include <stdlib.h> #include "flash.h" +#include "board.h" #include "flashchips.h" /* @@ -168,59 +169,46 @@ void print_supported_chipsets(void) } } -void print_supported_boards_helper(const struct board_info *b, const char *msg) -{ - int i, j, boardcount = 0; - - for (i = 0; b[i].vendor != NULL; i++) - boardcount++; - - printf("\n%s (total: %d):\n\n", msg, boardcount); - - for (i = 0; b[i].vendor != NULL; i++) { - printf("%s", b[i].vendor); - for (j = 0; j < 25 - strlen(b[i].vendor); j++) - printf(" "); - printf("%s", b[i].name); - for (j = 0; j < 28 - strlen(b[i].name); j++) - printf(" "); - printf("\n"); - } -} - -void print_supported_boards(void) +void print_supported_boards_helper(const struct board_info *boards, const char *devicetype) { int i, j, boardcount = 0; struct board_pciid_enable *b = board_pciid_enables; - for (i = 0; b[i].vendor_name != NULL; i++) + /* Print known mainboards */ + for (i = 0; boards[i].vendor != NULL; i++) boardcount++; - printf("\nSupported boards which need write-enable code (total: %d):" - "\n\nVendor: Board: " - "Required option:\n\n", boardcount); + printf("\nKnown %s (total: %d):" + "\n\nVendor: Board: Status: Write-enable option?" + "\n\n", devicetype, boardcount); - for (i = 0; b[i].vendor_name != NULL; i++) { - printf("%s", b[i].vendor_name); - for (j = 0; j < 25 - strlen(b[i].vendor_name); j++) + for (i = 0; boards[i].vendor != NULL; i++) { + printf("%s", boards[i].vendor); + for (j = 0; j < 25 - strlen(boards[i].vendor); j++) printf(" "); - printf("%s", b[i].board_name); - for (j = 0; j < 30 - strlen(b[i].board_name); j++) + printf("%s", boards[i].name); + for (j = 0; j < 28 - strlen(boards[i].name); j++) printf(" "); - if (b[i].lb_vendor != NULL) - printf("-m %s:%s\n", b[i].lb_vendor, b[i].lb_part); + if(boards[i].working) + printf(" good "); else - printf("(none, board is autodetected)\n"); - } + printf(" BAD! "); + + if(boards[i].write_enable){ + for (j = 0; b[j].vendor_name != NULL; j++) { + if ((strcmp(b[j].vendor_name, boards[i].vendor) == 0) && (strcmp(b[j].board_name, boards[i].name) == 0)){ + if (b[j].lb_vendor != NULL) + printf("-m %s:%s", b[j].lb_vendor, b[j].lb_part); + else + printf("(none, board is autodetected)"); + } + } + } + else + printf(" -"); - print_supported_boards_helper(boards_ok, - "Supported boards which don't need write-enable code"); - print_supported_boards_helper(boards_bad, - "Boards which have been verified to NOT work yet"); - print_supported_boards_helper(laptops_ok, - "Laptops which have been verified to work"); - print_supported_boards_helper(laptops_bad, - "Laptops which have been verified to NOT work yet"); + printf("\n"); + } } #endif @@ -229,7 +217,8 @@ void print_supported(void) print_supported_chips(); #if INTERNAL_SUPPORT == 1 print_supported_chipsets(); - print_supported_boards(); + print_supported_boards_helper(boards_known, "boards"); + print_supported_boards_helper(laptops_known, "laptops"); #endif #if (NIC3COM_SUPPORT == 1) || (GFXNVIDIA_SUPPORT == 1) || (DRKAISER_SUPPORT == 1) || (SATASII_SUPPORT == 1) printf("\nSupported PCI devices flashrom can use " @@ -256,183 +245,3 @@ void print_supported(void) #endif } - -#if INTERNAL_SUPPORT == 1 -/* Please keep this list alphabetically ordered by vendor/board. */ -const struct board_info boards_ok[] = { - /* Verified working boards that don't need write-enables. */ -#if defined(__i386__) || defined(__x86_64__) - { "Abit", "AX8", }, - { "Abit", "Fatal1ty F-I90HD", }, - { "Advantech", "PCM-5820", }, - { "ASI", "MB-5BLMP", }, - { "ASRock", "A770CrossFire", }, - { "ASRock", "K8S8X", }, - { "ASRock", "M3A790GXH/128M" }, - { "ASUS", "A7N8X Deluxe", }, - { "ASUS", "A7N8X-E Deluxe", }, - { "ASUS", "A7V133", }, - { "ASUS", "A7V400-MX", }, - { "ASUS", "A7V8X-MX", }, - { "ASUS", "A8N-E", }, - { "ASUS", "A8NE-FM/S", }, - { "ASUS", "A8N-SLI", }, - { "ASUS", "A8N-SLI Premium", }, - { "ASUS", "A8V Deluxe", }, - { "ASUS", "A8V-E Deluxe", }, - { "ASUS", "A8V-E SE", }, - { "ASUS", "K8V", }, - { "ASUS", "K8V SE Deluxe", }, - { "ASUS", "K8V-X SE", }, - { "ASUS", "M2A-MX", }, - { "ASUS", "M2A-VM", }, - { "ASUS", "M2N-E", }, - { "ASUS", "M2V", }, - { "ASUS", "M3A78-EM", }, - { "ASUS", "P2B", }, - { "ASUS", "P2B-D", }, - { "ASUS", "P2B-DS", }, - { "ASUS", "P2B-F", }, - { "ASUS", "P2L97-S", }, - { "ASUS", "P5B", }, - { "ASUS", "P5B-Deluxe", }, - { "ASUS", "P5KC", }, - { "ASUS", "P5L-MX", }, - { "ASUS", "P6T Deluxe", }, - { "ASUS", "P6T Deluxe V2", }, - { "A-Trend", "ATC-6220", }, - { "BCOM", "WinNET100", }, - { "DFI", "Blood-Iron P35 T2RL", }, - { "Elitegroup", "K7S5A", }, - { "Elitegroup", "P6VAP-A+", }, - { "GIGABYTE", "GA-2761GXDK", }, - { "GIGABYTE", "GA-6BXC", }, - { "GIGABYTE", "GA-6BXDU", }, - { "GIGABYTE", "GA-6ZMA", }, - { "GIGABYTE", "GA-7ZM", }, - { "GIGABYTE", "GA-965P-DS4", }, - { "GIGABYTE", "GA-EP35-DS3L", }, - { "GIGABYTE", "GA-EX58-UD4P", }, - { "GIGABYTE", "GA-M57SLI-S4", }, - { "GIGABYTE", "GA-M61P-S3", }, - { "GIGABYTE", "GA-MA69VM-S2", }, - { "GIGABYTE", "GA-MA770T-UD3P", }, - { "GIGABYTE", "GA-MA78G-DS3H", }, - { "GIGABYTE", "GA-MA78GM-S2H", }, - { "GIGABYTE", "GA-MA78GPM-DS2H", }, - { "GIGABYTE", "GA-MA790FX-DQ6", }, - { "GIGABYTE", "GA-MA790GP-DS4H", }, - { "Intel", "EP80759", }, - { "Jetway", "J7F4K1G5D-PB", }, - { "MSI", "MS-6153", }, - { "MSI", "MS-6156", }, - { "MSI", "MS-6330 (K7T Turbo)", }, - { "MSI", "MS-6570 (K7N2)", }, - { "MSI", "MS-7065", }, - { "MSI", "MS-7168 (Orion)", }, - { "MSI", "MS-7236 (945PL Neo3)", }, - { "MSI", "MS-7255 (P4M890M)", }, - { "MSI", "MS-7312 (K9MM-V)", }, - { "MSI", "MS-7345 (P35 Neo2-FIR)", }, - { "MSI", "MS-7368 (K9AG Neo2-Digital)", }, - { "MSI", "MS-7376 (K9A2 Platinum)", }, - { "NEC", "PowerMate 2000", }, - { "PC Engines", "Alix.1c", }, - { "PC Engines", "Alix.2c2", }, - { "PC Engines", "Alix.2c3", }, - { "PC Engines", "Alix.3c3", }, - { "PC Engines", "Alix.3d3", }, - { "PC Engines", "WRAP.2E", }, - { "RCA", "RM4100", }, - { "Shuttle", "FD37", }, - { "Sun", "Blade x6250", }, - { "Supermicro", "H8QC8", }, - { "Supermicro", "X8DTT-F", }, - { "Thomson", "IP1000", }, - { "TriGem", "Lomita", }, - { "T-Online", "S-100", }, - { "Tyan", "iS5375-1U", }, - { "Tyan", "S1846", }, - { "Tyan", "S2466", }, - { "Tyan", "S2881", }, - { "Tyan", "S2882", }, - { "Tyan", "S2882-D", }, - { "Tyan", "S2891", }, - { "Tyan", "S2892", }, - { "Tyan", "S2895", }, - { "Tyan", "S3095", }, - { "Tyan", "S5180", }, - { "Tyan", "S5191", }, - { "Tyan", "S5197", }, - { "Tyan", "S5211", }, - { "Tyan", "S5211-1U", }, - { "Tyan", "S5220", }, - { "Tyan", "S5375", }, - { "Tyan", "S5376G2NR/S5376WAG2NR", }, - { "Tyan", "S5377", }, - { "Tyan", "S5382 (Tempest i5000PW)", }, - { "Tyan", "S5397", }, - { "VIA", "EPIA-CN", }, - { "VIA", "EPIA-EX15000G", }, - { "VIA", "EPIA-LN", }, - { "VIA", "EPIA-M700", }, - { "VIA", "EPIA-NX15000G", }, - { "VIA", "EPIA-SP", }, - { "VIA", "NAB74X0", }, - { "VIA", "pc2500e", }, - { "VIA", "PC3500G", }, - { "VIA", "VB700X", }, -#endif - {}, -}; - -/* Please keep this list alphabetically ordered by vendor/board. */ -const struct board_info boards_bad[] = { - /* Verified non-working boards (for now). */ -#if defined(__i386__) || defined(__x86_64__) - { "Abit", "IS-10", }, - { "ASRock", "K7VT4A+", }, - { "ASUS", "MEW-AM", }, - { "ASUS", "MEW-VM", }, - { "ASUS", "P3B-F", }, - { "ASUS", "P5BV-M", }, - { "Biostar", "M6TBA", }, - { "Boser", "HS-6637", }, - { "DFI", "855GME-MGF", }, - { "FIC", "VA-502", }, - { "MSI", "MS-6178", }, - { "MSI", "MS-7260 (K9N Neo)", }, - { "Soyo", "SY-5VD", }, - { "Sun", "Fire x4150", }, - { "Sun", "Fire x4200", }, - { "Sun", "Fire x4540", }, - { "Sun", "Fire x4600", }, -#endif - {}, -}; - -/* Please keep this list alphabetically ordered by vendor/board. */ -const struct board_info laptops_ok[] = { - /* Verified working laptops. */ -#if defined(__i386__) || defined(__x86_64__) - { "Lenovo", "3000 V100 TF05Cxx", }, - { "Acer", "Aspire 1520", }, -#endif - {}, -}; - -/* Please keep this list alphabetically ordered by vendor/board. */ -const struct board_info laptops_bad[] = { - /* Verified non-working laptops (for now). */ -#if defined(__i386__) || defined(__x86_64__) - { "Acer", "Aspire One", }, - { "ASUS", "Eee PC 701 4G", }, - { "Dell", "Latitude CPi A366XT", }, - { "HP/Compaq", "nx9010", }, - { "IBM/Lenovo", "Thinkpad T40p", }, - { "IBM/Lenovo", "240", }, -#endif - {}, -}; -#endif - diff --git a/print_wiki.c b/print_wiki.c index 3d51bfa..926c745 100644 --- a/print_wiki.c +++ b/print_wiki.c @@ -23,22 +23,9 @@ #include <stdlib.h> #include <time.h> #include "flash.h" +#include "board.h" #include "flashchips.h" -#if INTERNAL_SUPPORT == 1 -struct board_info_url { - const char *vendor; - const char *name; - const char *url; -}; - -struct board_info_notes { - const char *vendor; - const char *name; - const char *note; -}; -#endif - const char *wiki_header = "= Supported devices =\n\n\ <div style=\"margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; \ background-color:#eeeeee; align:right; border:1px solid #aabbcc;\"><small>\n\ @@ -56,11 +43,6 @@ const char *board_th = "{| border=\"0\" style=\"font-size: smaller\" \ valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ ! align=\"left\" | Mainboard\n! align=\"left\" | Status\n\n"; -const char *board_th2 = "{| border=\"0\" style=\"font-size: smaller\" \ -valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ -! align=\"left\" | Mainboard\n! align=\"left\" | Required option\n\ -! align=\"left\" | Status\n\n"; - const char *board_intro = "\ \n== Supported mainboards ==\n\n\ In general, it is very likely that flashrom works out of the box even if your \ @@ -101,292 +83,6 @@ background-color:#ff6666; align:right; border:1px solid #000000;\">\n\ untested laptops unless you have a means to recover from a flashing that goes \ wrong (a working backup flash chip and/or good soldering skills).\n</div>\n"; -/* Please keep these lists alphabetically ordered by vendor/board. */ -const struct board_info_url boards_url[] = { - /* Verified working boards that don't need write-enables. */ -#if defined(__i386__) || defined(__x86_64__) - { "Abit", "AX8", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=…" }, - { "Abit", "Fatal1ty F-I90HD", "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?pMODEL_NA…" }, - { "Advantech", "PCM-5820", "http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm" }, - { "ASI", "MB-5BLMP", "http://www.hojerteknik.com/winnet.htm" }, - { "ASRock", "A770CrossFire", "http://www.asrock.com/mb/overview.asp?Model=A770CrossFire&s=AM2\%2b" }, - { "ASRock", "K8S8X", "http://www.asrock.com/mb/overview.asp?Model=K8S8X" }, - { "ASRock", "M3A790GXH/128M" "http://www.asrock.com/MB/overview.asp?Model=M3A790GXH/128M" }, - { "ASUS", "A7N8X Deluxe", "http://www.asus.com/product.aspx?P_ID=wAsRYm41KTp78MFC" }, - { "ASUS", "A7N8X-E Deluxe", "http://www.asus.com/product.aspx?P_ID=TmQtPJv4jIxmL9C2" }, - { "ASUS", "A7V133", "ftp://ftp.asus.com.tw/pub/ASUS/mb/socka/kt133a/a7v133/" }, - { "ASUS", "A7V400-MX", "http://www.asus.com/product.aspx?P_ID=hORgEHRBDLMfwAwx" }, - { "ASUS", "A7V8X-MX", "http://www.asus.com/product.aspx?P_ID=SEJOOYqfuQPitx2H" }, - { "ASUS", "A8N-E", "http://www.asus.com/product.aspx?P_ID=DzbA8hgqchMBOVRz" }, - { "ASUS", "A8NE-FM/S", "http://www.hardwareschotte.de/hardware/preise/proid_1266090/preis_ASUS+A8NE…" }, - { "ASUS", "A8N-SLI", "http://www.asus.com/product.aspx?P_ID=J9FKa8z2xVId3pDK" }, - { "ASUS", "A8N-SLI Premium", "http://www.asus.com/product.aspx?P_ID=nbulqxniNmzf0mH1" }, - { "ASUS", "A8V Deluxe", "http://www.asus.com/product.aspx?P_ID=tvpdgPNCPaABZRVU" }, - { "ASUS", "A8V-E Deluxe", "http://www.asus.com/product.aspx?P_ID=hQBPIJWEZnnGAZEh" }, - { "ASUS", "A8V-E SE", "http://www.asus.com/product.aspx?P_ID=VMfiJJRYTHM4gXIi" }, - { "ASUS", "K8V", "http://www.asus.com/product.aspx?P_ID=fG2KZOWF7v6MRFRm" }, - { "ASUS", "K8V SE Deluxe", "http://www.asus.com/product.aspx?P_ID=65HeDI8XM1u6Uy6o" }, - { "ASUS", "K8V-X SE", "http://www.asus.com/product.aspx?P_ID=lzDXlbBVHkdckHVr" }, - { "ASUS", "M2A-MX", "http://www.asus.com/product.aspx?P_ID=BmaOnPewi1JgltOZ" }, - { "ASUS", "M2A-VM", "http://www.asus.com/product.aspx?P_ID=St3pWpym8xXpROQS" }, - { "ASUS", "M2N-E", "http://www.asus.com/product.aspx?P_ID=NFlvt10av3F7ayQ9" }, - { "ASUS", "M2V", "http://www.asus.com/product.aspx?P_ID=OqYlEDFfF6ZqZGvp" }, - { "ASUS", "M3A78-EM", "http://www.asus.com/product.aspx?P_ID=KjpYqzmAd9vsTM2D" }, - { "ASUS", "P2B", "ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b/" }, - { "ASUS", "P2B-D", "ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-d/" }, - { "ASUS", "P2B-DS", "ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-ds/" }, - { "ASUS", "P2B-F", "ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-d/" }, - { "ASUS", "P2L97-S", "ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440lx/p2l97-s/" }, - { "ASUS", "P5B", "ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/P5B/" }, - { "ASUS", "P5B-Deluxe", "http://www.asus.com/product.aspx?P_ID=bswT66IBSb2rEWNa" }, - { "ASUS", "P5KC", "http://www.asus.com/product.aspx?P_ID=fFZ8oUIGmLpwNMjj" }, - { "ASUS", "P5L-MX", "http://www.asus.com/product.aspx?P_ID=X70d3NCzH2DE9vWH" }, - { "ASUS", "P6T Deluxe", "http://www.asus.com/product.aspx?P_ID=vXixf82co6Q5v0BZ" }, - { "ASUS", "P6T Deluxe V2", "http://www.asus.com/product.aspx?P_ID=iRlP8RG9han6saZx" }, - { "A-Trend", "ATC-6220", "http://www.motherboard.cz/mb/atrend/atc6220.htm" }, - { "BCOM", "WinNET100", "http://www.coreboot.org/BCOM_WINNET100" }, - { "DFI", "Blood-Iron P35 T2RL", "http://lp.lanparty.com.tw/portal/CM/cmproduct/XX_cmproddetail/XX_WbProdsWin…" }, - { "Elitegroup", "K7S5A", "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=279&…" }, - { "Elitegroup", "P6VAP-A+", "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=117&…" }, - { "GIGABYTE", "GA-6BXC", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "GIGABYTE", "GA-6BXDU", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "GIGABYTE", "GA-6ZMA", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "GIGABYTE", "GA-965P-DS4", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "GIGABYTE", "GA-EX58-UD4P", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "GIGABYTE", "GA-EP35-DS3L", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "GIGABYTE", "GA-MA69VM-S2", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "GIGABYTE", "GA-MA790GP-DS4H", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "GIGABYTE", "GA-MA78GPM-DS2H", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "GIGABYTE", "GA-MA770T-UD3P", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "Intel", "EP80759", NULL }, - { "Jetway", "J7F4K1G5D-PB", "http://www.jetway.com.tw/jetway/system/productshow2.asp?id=389&proname=J7F4…" }, - { "MSI", "MS-6153", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=336" }, - { "MSI", "MS-6156", "http://uk.ts.fujitsu.com/rl/servicesupport/techsupport/boards/Motherboards/…" }, - { "MSI", "MS-6330 (K7T Turbo)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=327" }, - { "MSI", "MS-6570 (K7N2)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=519" }, - { "MSI", "MS-7065", "http://browse.geekbench.ca/geekbench2/view/53114" }, - { "MSI", "MS-7168 (Orion)", "http://support.packardbell.co.uk/uk/item/index.php?i=spec_orion&pi=platform…" }, - { "MSI", "MS-7236 (945PL Neo3)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1173" }, - { "MSI", "MS-7255 (P4M890M)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1082" }, - { "MSI", "MS-7345 (P35 Neo2-FIR)","http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1261" }, - { "MSI", "MS-7312 (K9MM-V)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1104" }, - { "MSI", "MS-7368 (K9AG Neo2-Digital)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1241" }, - { "MSI", "MS-7376 (K9A2 Platinum)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1332" }, - { "NEC", "PowerMate 2000", "http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/" }, - { "PC Engines", "Alix.1c", "http://pcengines.ch/alix1c.htm" }, - { "PC Engines", "Alix.2c2", "http://pcengines.ch/alix2c2.htm" }, - { "PC Engines", "Alix.2c3", "http://pcengines.ch/alix2c3.htm" }, - { "PC Engines", "Alix.3c3", "http://pcengines.ch/alix3c3.htm" }, - { "PC Engines", "Alix.3d3", "http://pcengines.ch/alix3d3.htm" }, - { "PC Engines", "WRAP.2E", "http://pcengines.ch/wrap2e1.htm" }, - { "RCA", "RM4100", "http://www.settoplinux.org/index.php?title=RCA_RM4100" }, - { "Shuttle", "FD37", "http://www.shuttle.eu/products/discontinued/barebones/sd37p2/" }, - { "Sun", "Blade x6250", "http://www.sun.com/servers/blades/x6250/" }, - { "Supermicro", "H8QC8", "http://www.supermicro.com/Aplus/motherboard/Opteron/nforce/H8QC8.cfm" }, - { "Supermicro", "X8DTT-F", "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTT-F.cfm" }, - { "Tekram", "P6Pro-A5", "http://www.motherboard.cz/mb/tekram/P6Pro-A5.htm" }, - { "Thomson", "IP1000", "http://www.settoplinux.org/index.php?title=Thomson_IP1000" }, - { "TriGem", "Lomita", "http://www.e4allupgraders.info/dir1/motherboards/socket370/lomita.shtml" }, - { "T-Online", "S-100", "http://wiki.freifunk-hannover.de/T-Online_S_100" }, - { "Tyan", "iS5375-1U", "http://www.tyan.com/product_board_detail.aspx?pid=610" }, - { "Tyan", "S1846", "http://www.tyan.com/archive/products/html/tsunamiatx.html" }, - { "Tyan", "S2466", "http://www.tyan.com/product_board_detail.aspx?pid=461" }, - { "Tyan", "S2881", "http://www.tyan.com/product_board_detail.aspx?pid=115" }, - { "Tyan", "S2882", "http://www.tyan.com/product_board_detail.aspx?pid=121" }, - { "Tyan", "S2882-D", "http://www.tyan.com/product_board_detail.aspx?pid=127" }, - { "Tyan", "S2891", "http://www.tyan.com/product_board_detail.aspx?pid=144" }, - { "Tyan", "S2892", "http://www.tyan.com/product_board_detail.aspx?pid=145" }, - { "Tyan", "S2895", "http://www.tyan.com/archive/products/html/thunderk8we.html" }, - { "Tyan", "S3095", "http://www.tyan.com/product_board_detail.aspx?pid=181" }, - { "Tyan", "S5180", "http://www.tyan.com/product_board_detail.aspx?pid=456" }, - { "Tyan", "S5191", "http://www.tyan.com/product_board_detail.aspx?pid=343" }, - { "Tyan", "S5197", "http://www.tyan.com/product_board_detail.aspx?pid=349" }, - { "Tyan", "S5211", "http://www.tyan.com/product_board_detail.aspx?pid=591" }, - { "Tyan", "S5211-1U", "http://www.tyan.com/product_board_detail.aspx?pid=593" }, - { "Tyan", "S5220", "http://www.tyan.com/product_board_detail.aspx?pid=597" }, - { "Tyan", "S5375", "http://www.tyan.com/product_board_detail.aspx?pid=566" }, - { "Tyan", "S5376G2NR/S5376WAG2NR","http://www.tyan.com/product_board_detail.aspx?pid=605" }, - { "Tyan", "S5377", "http://www.tyan.com/product_SKU_spec.aspx?ProductType=MB&pid=642&SKU=600000…" }, - { "Tyan", "S5382 (Tempest i5000PW)", "http://www.tyan.com/product_board_detail.aspx?pid=439" }, - { "Tyan", "S5397", "http://www.tyan.com/product_board_detail.aspx?pid=560" }, - { "VIA", "EPIA-EX15000G", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…" }, - { "VIA", "EPIA-LN", "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…" }, - { "VIA", "EPIA-M700", "http://via.com.tw/servlet/downloadSvl?motherboard_id=670&download_file_id=3…" }, - { "VIA", "EPIA-NX15000G", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…" }, - { "VIA", "NAB74X0", "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…" }, - { "VIA", "pc2500e", "http://www.via.com.tw/en/initiatives/empowered/pc2500_mainboard/index.jsp" }, - { "VIA", "VB700X", "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…" }, - - /* Verified working boards that DO need write-enables. */ - { "Abit", "VT6X4", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=Sl…" }, - { "Abit", "IP35", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=LG…" }, - { "Abit", "IP35 Pro", "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?fMTYPE=LG…" }, - { "Abit", "NF7-S", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=So…"}, - { "Acorp", "6A815EPD", "http://web.archive.org/web/20021206163652/www.acorp.com.tw/English/default.…" }, - { "agami", "Aruma", "http://web.archive.org/web/20080212111524/http://www.agami.com/site/ais-600…" }, - { "Albatron", "PM266A Pro", "http://www.albatron.com.tw/English/Product/MB/pro_detail.asp?rlink=Overview…" }, /* FIXME */ - { "AOpen", "vKM400Am-S", "http://usa.aopen.com/products_detail.aspx?Auno=824" }, - { "Artec Group", "DBE61", "http://wiki.thincan.org/DBE61" }, - { "Artec Group", "DBE62", "http://wiki.thincan.org/DBE62" }, - { "ASUS", "A7V600-X", "http://www.asus.com/product.aspx?P_ID=L2XYS0rmtCjeOr4k" }, - { "ASUS", "A7V8X", "http://www.asus.com/product.aspx?P_ID=qfpaGrAy2kLVo0f2" }, - { "ASUS", "A7V8X-MX SE", "http://www.asus.com/product.aspx?P_ID=1guVBT1qV5oqhHyZ" }, - { "ASUS", "A7V8X-X", "http://www.asus.com/product.aspx?P_ID=YcXfRrWHZ9RKoVmw" }, - { "ASUS", "M2NBP-VM CSM", "http://www.asus.com/product.aspx?P_ID=MnOfzTGd2KkwG0rF" }, - { "ASUS", "M2V-MX", "http://www.asus.com/product.aspx?P_ID=7grf8Ci4yxnqzt3z" }, - { "ASUS", "P4B266", "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock478/p4b266/" }, - { "ASUS", "P4C800-E Deluxe", "http://www.asus.com/product.aspx?P_ID=cFuVCr9bXXCckmcK" }, - { "ASUS", "P4B266-LM", "http://esupport.sony.com/US/perl/swu-list.pl?mdl=PCVRX650" }, - { "ASUS", "P4P800-E Deluxe", "http://www.asus.com/product.aspx?P_ID=INIJUvLlif7LHp3g" }, - { "ASUS", "P5ND2-SLI Deluxe", "http://www.asus.com/product.aspx?P_ID=WY7XroDuUImVbgp5" }, - { "ASUS", "P5A", "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock7/ali/p5a/" }, - { "Biostar", "P4M80-M4", "http://www.biostar-usa.com/mbdetails.asp?model=p4m80-m4" }, - { "Dell", "PowerEdge 1850", "http://support.dell.com/support/edocs/systems/pe1850/en/index.htm" }, - { "Elitegroup", "K7S6A", "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=77&C…" }, - { "Elitegroup", "K7VTA3", "http://www.ecs.com.tw/ECSWebSite/Products/ProductsDetail.aspx?detailid=264&…" }, - { "EPoX", "EP-8K5A2", "http://www.epox.com/product.asp?ID=EP-8K5A2" }, - { "EPoX", "EP-8RDA3+", "http://www.epox.com/product.asp?ID=EP-8RDA3plus" }, - { "EPoX", "EP-BX3", "http://www.epox.com/product.asp?ID=EP-BX3" }, - { "GIGABYTE", "GA-2761GXDK", "http://www.computerbase.de/news/hardware/mainboards/amd-systeme/2007/mai/gi…" }, - { "GIGABYTE", "GA-7VT600", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "GIGABYTE", "GA-7ZM", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "GIGABYTE", "GA-K8N-SLI", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "GIGABYTE", "GA-M57SLI-S4", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "GIGABYTE", "GA-M61P-S3", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "GIGABYTE", "GA-MA78G-DS3H", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, /* TODO: Rev 1.x or 2.x? */ - { "GIGABYTE", "GA-MA78GM-S2H", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, /* TODO: Rev. 1.0, 1.1, or 2.x? */ - { "GIGABYTE", "GA-MA790FX-DQ6", "http://www.gigabyte.com.tw/Products/Motherboard/Products_Spec.aspx?ProductI…" }, - { "HP", "DL145 G3", "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c008…" }, - { "HP", "Vectra VL400 PC", "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c000…" }, - { "HP", "Vectra VL420 SFF PC", "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c000…" }, - { "IBM", "x3455", "http://www-03.ibm.com/systems/x/hardware/rack/x3455/index.html" }, - { "Intel", "D201GLY", "http://www.intel.com/support/motherboards/desktop/d201gly/index.htm" }, - { "IWILL", "DK8-HTX", "http://web.archive.org/web/20060507170150/http://www.iwill.net/product_2.as…" }, - { "Kontron", "986LCD-M", "http://de.kontron.com/products/boards+and+mezzanines/embedded+motherboards/…" }, - { "Mitac", "6513WU", "http://web.archive.org/web/20050313054828/http://www.mitac.com/micweb/produ…" }, - { "MSI", "MS-6590 (KT4 Ultra)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=502" }, - { "MSI", "MS-6702E (K8T Neo2-F)","http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=588" }, - { "MSI", "MS-6712 (KT4V)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=505" }, - { "MSI", "MS-7005 (651M-L)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=559" }, - { "MSI", "MS-7046", "http://www.heimir.de/ms7046/" }, - { "MSI", "MS-7135 (K8N Neo3)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=170" }, - { "Shuttle", "AK31", "http://www.motherboard.cz/mb/shuttle/AK31.htm" }, - { "Shuttle", "AK38N", "http://eu.shuttle.com/en/desktopdefault.aspx/tabid-36/558_read-9889/" }, - { "Shuttle", "FN25", "http://www.shuttle.eu/products/discontinued/barebones/sn25p/?0=" }, - { "Soyo", "SY-7VCA", "http://www.tomshardware.com/reviews/12-socket-370-motherboards,196-15.html" }, - { "Tyan", "S2498 (Tomcat K7M)", "http://www.tyan.com/archive/products/html/tomcatk7m.html" }, - { "VIA", "EPIA-CN", "http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_i…" }, - { "VIA", "EPIA M/MII/...", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…" }, /* EPIA-MII link for now */ - { "VIA", "EPIA-N/NL", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…" }, /* EPIA-N link for now */ - { "VIA", "EPIA SP", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…" }, - { "VIA", "PC3500G", "http://www.via.com.tw/en/initiatives/empowered/pc3500_mainboard/index.jsp" }, -#endif - - /* Verified non-working boards (for now). */ -#if defined(__i386__) || defined(__x86_64__) - { "Abit", "IS-10", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NA…" }, - { "ASRock", "K7VT4A+", "http://www.asrock.com/mb/overview.asp?Model=K7VT4A%%2b&s=" }, - { "ASUS", "MEW-AM", "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/" }, - { "ASUS", "MEW-VM", "http://www.elhvb.com/mboards/OEM/HP/manual/ASUS%20MEW-VM.htm" }, - { "ASUS", "P3B-F", "ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p3b-f/" }, - { "ASUS", "P5BV-M", "ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/P5B-VM/" }, - { "Biostar", "M6TBA", "ftp://ftp.biostar-usa.com/manuals/M6TBA/" }, - { "Boser", "HS-6637", "http://www.boser.com.tw/manual/HS-62376637v3.4.pdf" }, - { "DFI", "855GME-MGF", "http://www.dfi.com.tw/portal/CM/cmproduct/XX_cmproddetail/XX_WbProdsWindow?…" }, - { "FIC", "VA-502", "ftp://ftp.fic.com.tw/motherboard/manual/socket7/va-502/" }, - { "MSI", "MS-6178", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=343" }, - { "MSI", "MS-7260 (K9N Neo)", "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=255" }, - { "Soyo", "SY-5VD", "http://www.soyo.com/content/Downloads/163/&c=80&p=464&l=English" }, - { "Sun", "Fire x4540", "http://www.sun.com/servers/x64/x4540/" }, - { "Sun", "Fire x4150", "http://www.sun.com/servers/x64/x4150/" }, - { "Sun", "Fire x4200", "http://www.sun.com/servers/entry/x4200/" }, - { "Sun", "Fire x4600", "http://www.sun.com/servers/x64/x4600/" }, -#endif - - /* Verified working laptops. */ -#if defined(__i386__) || defined(__x86_64__) - { "Acer", "Aspire 1520", "http://support.acer.com/us/en/acerpanam/notebook/0000/Acer/Aspire1520/Aspir…" }, - { "Lenovo", "3000 V100 TF05Cxx", "http://www5.pc.ibm.com/europe/products.nsf/products?openagent&brand=Lenovo3…" }, -#endif - - /* Verified non-working laptops (for now). */ -#if defined(__i386__) || defined(__x86_64__) - { "Acer", "Aspire One", NULL }, - { "ASUS", "Eee PC 701 4G", "http://www.asus.com/product.aspx?P_ID=h6SPd3tEzLEsrEiS" }, - { "Dell", "Latitude CPi A366XT", "http://www.coreboot.org/Dell_Latitude_CPi_A366XT" }, - { "HP/Compaq", "nx9010", "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us…" }, - { "IBM/Lenovo", "Thinkpad T40p", "http://www.thinkwiki.org/wiki/Category:T40p" }, - { "IBM/Lenovo", "240", "http://www.stanford.edu/~bresnan//tp240.html" }, -#endif - - { NULL, NULL, 0 }, -}; - -/* Please keep these lists alphabetically ordered by vendor/board. */ -const struct board_info_notes boards_notes[] = { - /* Verified working boards that don't need write-enables. */ -#if defined(__i386__) || defined(__x86_64__) - { "ASI", "MB-5BLMP", "Used in the IGEL WinNET III thin client." }, - { "ASRock", "K8S8X", "The Super I/O isn't found on this board. See http://www.flashrom.org/pipermail/flashrom/2009-November/000937.html." }, - { "ASUS", "A8V-E SE", "See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html." }, - { "ASUS", "M2A-VM", "See http://www.coreboot.org/pipermail/coreboot/2007-September/025281.html." }, - { "BCOM", "WinNET100", "Used in the IGEL-316 thin client." }, - { "GIGABYTE", "GA-7ZM", "Works fine if you remove jumper JP9 on the board and disable the flash protection BIOS option." }, - { "ASUS", "M2N-E", "If the machine doesn't come up again after flashing, try resetting the NVRAM(CMOS). The MAC address of the onboard network card will change to the value stored in the new image, so backup the old address first. See http://www.flashrom.org/pipermail/flashrom/2009-November/000879.html" }, -#endif - - /* Verified working boards that DO need write-enables. */ -#if defined(__i386__) || defined(__x86_64__) - { "Acer", "Aspire One", "See http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html." }, -#endif - - /* Verified non-working boards (for now). */ -#if defined(__i386__) || defined(__x86_64__) - { "MSI", "MS-6178", "Immediately powers off if you try to hot-plug the chip. However, this does '''not''' happen if you use coreboot." }, - { "MSI", "MS-7260 (K9N Neo)", "Interestingly flashrom does not work when the vendor BIOS is booted, but it ''does'' work flawlessly when the machine is booted with coreboot." }, -#endif - - /* Verified working laptops. */ - /* None which need comments, yet... */ - - /* Verified non-working laptops (for now). */ -#if defined(__i386__) || defined(__x86_64__) - { "Acer", "Aspire One", "http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html" }, - { "ASUS", "Eee PC 701 4G", "It seems the chip (25X40VSIG) is behind some SPI flash translation layer (likely in the EC, the ENE KB3310)." }, - { "Dell", "Latitude CPi A366XT", "The laptop immediately powers off if you try to hot-swap the chip. It's not yet tested if write/erase would work on this laptop." }, - { "HP/Compaq", "nx9010", "Hangs upon '''flashrom -V''' (needs hard power-cycle then)." }, - { "IBM/Lenovo", "Thinkpad T40p", "Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later." }, -#endif - - { NULL, NULL, 0 }, -}; - -static int url(const char *vendor, const char *board) -{ - int i; - const struct board_info_url *b = boards_url; - - for (i = 0; b[i].vendor != NULL; i++) { - if (!strcmp(vendor, b[i].vendor) && !strcmp(board, b[i].name)) - return i; - } - - return -1; -} - -static int note(const char *vendor, const char *board) -{ - int i; - const struct board_info_notes *n = boards_notes; - - for (i = 0; n[i].vendor != NULL; i++) { - if (!strcmp(vendor, n[i].vendor) && !strcmp(board, n[i].name)) - return i; - } - - return -1; -} - static void print_supported_chipsets_wiki(int cols) { int i, j, enablescount = 0, color = 1; @@ -421,40 +117,51 @@ static void print_supported_chipsets_wiki(int cols) printf("\n|}\n\n|}\n"); } -static void wiki_helper(const char *heading, const char *status, - int cols, const struct board_info boards[]) +static void wiki_helper(const char *devicetype, int cols, const struct board_info boards[]) { - int i, j, k, c, boardcount = 0, color = 1, num_notes = 0; - const struct board_info *b; - const struct board_info_url *u = boards_url; + int i, j, k = 0, boardcount = 0, color = 1, num_notes = 0; char *notes = calloc(1, 1); char tmp[900 + 1]; + struct board_pciid_enable *b = board_pciid_enables; + - for (b = boards; b->vendor != NULL; b++) + for (i = 0; boards[i].vendor != NULL; i++) boardcount++; - printf("\n'''%s'''\n\nTotal amount of boards: '''%d'''\n\n" + printf("\n\nTotal amount of known %s: '''%d'''\n\n" "{| border=\"0\" valign=\"top\"\n| valign=\"top\"|\n\n%s", - heading, boardcount, board_th); + devicetype, boardcount, board_th); + + for (i = 0, j = 0; boards[i].vendor != NULL; i++, j++) { - for (i = 0, j = 0, b = boards; b[i].vendor != NULL; i++, j++) { /* Alternate colors if the vendor changes. */ - if (i > 0 && strcmp(b[i].vendor, b[i - 1].vendor)) + if (i > 0 && strcmp(boards[i].vendor, boards[i - 1].vendor)) color = !color; - k = url(b[i].vendor, b[i].name); - c = note(b[i].vendor, b[i].name); - - printf("|- bgcolor=\"#%s\"\n| %s || %s%s %s%s ||" - " {{%s}}", (color) ? "eeeeee" : "dddddd", b[i].vendor, - (k != -1 && u[k].url) ? "[" : "", - (k != -1 && u[k].url) ? u[k].url : "", - b[i].name, (k != -1 && u[k].url) ? "]" : "", status); + if(boards[i].write_enable){ + k = 0; + while ((b[k].vendor_name != NULL) && (strcmp(b[k].vendor_name, boards[i].vendor) != 0) && (strcmp(b[k].board_name, boards[i].name) != 0)){ + k++; + } + } - if (c != -1) { + printf("|- bgcolor=\"#%s\"\n| %s || %s%s %s%s || %s%s%s%s || {{%s}}\n", + (color) ? "eeeeee" : "dddddd", + boards[i].vendor, + boards[i].url ? "[" : "", + boards[i].url ? boards[i].url : "", + boards[i].name, + boards[i].url ? "]" : "", + b[k].lb_vendor ? "-m " : "—", + b[k].lb_vendor ? b[k].lb_vendor : "", + b[k].lb_vendor ? ":" : "", + b[k].lb_vendor ? b[k].lb_part : "", + boards[i].working ? "OK" : "No"); + + if (boards[i].note){ printf("<sup>%d</sup>\n", num_notes + 1); snprintf((char *)&tmp, 900, "<sup>%d</sup> %s<br />\n", - 1 + num_notes++, boards_notes[c].note); + 1 + num_notes++, boards[i].note); notes = strcat_realloc(notes, (char *)&tmp); } else { printf("\n"); @@ -474,58 +181,14 @@ static void wiki_helper(const char *heading, const char *status, free(notes); } -static void wiki_helper2(const char *heading, int cols) -{ - int i, j, k, boardcount = 0, color = 1; - struct board_pciid_enable *b; - const struct board_info_url *u = boards_url; - - for (b = board_pciid_enables; b->vendor_name != NULL; b++) - boardcount++; - - printf("\n'''%s'''\n\nTotal amount of boards: '''%d'''\n\n" - "{| border=\"0\" valign=\"top\"\n| valign=\"top\"|\n\n%s", - heading, boardcount, board_th2); - - b = board_pciid_enables; - for (i = 0, j = 0; b[i].vendor_name != NULL; i++, j++) { - /* Alternate colors if the vendor changes. */ - if (i > 0 && strcmp(b[i].vendor_name, b[i - 1].vendor_name)) - color = !color; - - k = url(b[i].vendor_name, b[i].board_name); - - printf("|- bgcolor=\"#%s\"\n| %s || %s%s %s%s " - "|| %s%s%s%s || {{%s}}\n", (color) ? "eeeeee" : "dddddd", - b[i].vendor_name, (k != -1 && u[k].url) ? "[" : "", - (k != -1 && u[k].url) ? u[k].url : "", b[i].board_name, - (k != -1 && u[k].url) ? "]" : "", - (b[i].lb_vendor) ? "-m " : "—", - (b[i].lb_vendor) ? b[i].lb_vendor : "", - (b[i].lb_vendor) ? ":" : "", - (b[i].lb_vendor) ? b[i].lb_part : "", - (b[i].status == OK) ? "OK" : "?3"); - - /* Split table in 'cols' columns. */ - if (j >= (boardcount / cols + 1)) { - printf("\n|}\n\n| valign=\"top\"|\n\n%s", board_th2); - j = 0; - } - } - - printf("\n|}\n\n|}\n"); -} - static void print_supported_boards_wiki(void) { printf("%s", board_intro); - wiki_helper("Known good (worked out of the box)", "OK", 3, boards_ok); - wiki_helper2("Known good (with write-enable code in flashrom)", 2); - wiki_helper("Not supported (yet)", "No", 3, boards_bad); + wiki_helper("boards", 3, boards_known); printf("%s", laptop_intro); - wiki_helper("Known good (worked out of the box)", "OK", 1, laptops_ok); - wiki_helper("Not supported (yet)", "No", 1, laptops_bad); + wiki_helper("laptops", 1, laptops_known); + } #endif -- 1.6.6.1

2 3

[PATCH] Try to handle non-x86 sanely
by Carl-Daniel Hailfinger 26 May '10

26 May '10

flashrom is very x86 centric. It does work on other architectures if you get it to compile. Try to fix the worst compile errors on non-x86 for a full build. Should work in theory with a default build if you exclude nic3com. Will pretty sure break compilation on Alpha. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-ioport_x86_only/hwaccess.c =================================================================== --- flashrom-ioport_x86_only/hwaccess.c (Revision 984) +++ flashrom-ioport_x86_only/hwaccess.c (Arbeitskopie) @@ -26,6 +26,8 @@ #include <errno.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + #if defined(__FreeBSD__) || defined(__DragonFly__) int io_fd; #endif @@ -54,6 +56,22 @@ #endif } +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + +void get_io_perms(void) +{ +} + +void release_io_perms(void) +{ +} + +#else + +#error Unknown architecture + +#endif + #ifdef __DJGPP__ extern unsigned short segFS; Index: flashrom-ioport_x86_only/hwaccess.h =================================================================== --- flashrom-ioport_x86_only/hwaccess.h (Revision 984) +++ flashrom-ioport_x86_only/hwaccess.h (Arbeitskopie) @@ -31,6 +31,8 @@ #include <pci/pci.h> #endif +#if defined(__i386__) || defined(__x86_64__) + /* for iopl and outb under Solaris */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) #include <strings.h> @@ -162,4 +164,11 @@ int freebsd_wrmsr(int addr, msr_t msr); #endif +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) +/* Port I/O is not available on PowerPC. */ + +#else +#error Unknown architecture +#endif + #endif /* !__HWACCESS_H__ */ Index: flashrom-ioport_x86_only/it87spi.c =================================================================== --- flashrom-ioport_x86_only/it87spi.c (Revision 984) +++ flashrom-ioport_x86_only/it87spi.c (Arbeitskopie) @@ -29,6 +29,8 @@ #include "chipdrivers.h" #include "spi.h" +#if defined(__i386__) || defined(__x86_64__) + #define ITE_SUPERIO_PORT1 0x2e #define ITE_SUPERIO_PORT2 0x4e @@ -347,3 +349,5 @@ return 0; } + +#endif Index: flashrom-ioport_x86_only/physmap.c =================================================================== --- flashrom-ioport_x86_only/physmap.c (Revision 984) +++ flashrom-ioport_x86_only/physmap.c (Arbeitskopie) @@ -238,6 +238,8 @@ return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO); } +#if defined(__i386__) || defined(__x86_64__) + #ifdef __linux__ /* * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr, @@ -455,4 +457,6 @@ #endif #endif #endif - +#else +/* Does MSR exist on non-x86 architectures? */ +#endif Index: flashrom-ioport_x86_only/nic3com.c =================================================================== --- flashrom-ioport_x86_only/nic3com.c (Revision 984) +++ flashrom-ioport_x86_only/nic3com.c (Arbeitskopie) @@ -23,6 +23,8 @@ #include <sys/types.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + #define BIOS_ROM_ADDR 0x04 #define BIOS_ROM_DATA 0x08 #define INT_STATUS 0x0e @@ -112,3 +114,7 @@ OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); return INB(io_base_addr + BIOS_ROM_DATA); } + +#else +#error Unknown architecture +#endif Index: flashrom-ioport_x86_only/wbsio_spi.c =================================================================== --- flashrom-ioport_x86_only/wbsio_spi.c (Revision 984) +++ flashrom-ioport_x86_only/wbsio_spi.c (Arbeitskopie) @@ -23,6 +23,8 @@ #include "chipdrivers.h" #include "spi.h" +#if defined(__i386__) || defined(__x86_64__) + #define WBSIO_PORT1 0x2e #define WBSIO_PORT2 0x4e @@ -199,3 +201,5 @@ return spi_chip_write_1(flash, buf); } + +#endif Index: flashrom-ioport_x86_only/chipset_enable.c =================================================================== --- flashrom-ioport_x86_only/chipset_enable.c (Revision 984) +++ flashrom-ioport_x86_only/chipset_enable.c (Arbeitskopie) @@ -34,6 +34,8 @@ #include <fcntl.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + extern int ichspi_lock; static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) @@ -1285,8 +1287,11 @@ return 0; } +#endif + /* Please keep this list alphabetically sorted by vendor/device. */ const struct penable chipset_enables[] = { +#if defined(__i386__) || defined(__x86_64__) {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533}, {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111}, {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, @@ -1417,7 +1422,7 @@ {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111}, {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111}, - +#endif {}, }; Index: flashrom-ioport_x86_only/board_enable.c =================================================================== --- flashrom-ioport_x86_only/board_enable.c (Revision 984) +++ flashrom-ioport_x86_only/board_enable.c (Arbeitskopie) @@ -28,6 +28,7 @@ #include <fcntl.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) /* * Helper functions for many Winbond Super I/Os of the W836xx range. */ @@ -1299,6 +1300,8 @@ return it8712f_gpio_set(32, 1); } +#endif + /** * Below is the list of boards which need a special "board enable" code in * flashrom before their ROM chip can be accessed/written to. @@ -1342,6 +1345,7 @@ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ +#if defined(__i386__) || defined(__x86_64__) {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "Abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, @@ -1407,7 +1411,7 @@ {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise}, {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise}, - +#endif { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */ }; -- http://www.hailfinger.org/

5 16

[commit] r1013 - trunk
by repository service 26 May '10

26 May '10

Author: hailfinger Date: Wed May 26 03:45:41 2010 New Revision: 1013 URL: http://flashrom.org/trac/coreboot/changeset/1013 Log: Handle the following architectures in generic flashrom code: - x86/x86_64 (little endian) - PowerPC (big endian) - MIPS (big+little endian) No changes to programmer specific code. This means any drivers with MMIO access will _not_ suddenly start working on big endian systems, but with this patch everything is in place to fix them. Compilation should work on all architectures listed above for all drivers except nic3com and nicrealtek which require PCI Port IO which is x86-only for now. To compile without nic3com and nicrealtek, run make distclean make CONFIG_NIC3COM=no CONFIG_NICREALTEK=no Thanks to Misha Manulis for testing early versions of this patch on PowerPC (big endian) with the satasii programmer. Thanks to Segher Boessenkool for design review and for helping out with compiler tricks and pointing out that we need eieio on PowerPC. Thanks to Vladimir Serbinenko for compile testing on MIPS (little endian) and PowerPC (big endian) and for runtime testing on MIPS (little endian). Thanks to David Daney for compile testing on MIPS (big endian). Thanks to Uwe Hermann for compile and runtime testing on x86_64. DO NOT RUN FLASHROM ON NON-X86 AFTER APPLYING THIS PATCH! This patch only provides the infrastructure, but does not convert any drivers, so flashrom will compile, but it won't do the right thing on non-x86 platforms. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Misha Manulis <misha(a)manulis.com> Acked-by: Vladimir 'phcoder/φ-coder' Serbinenko <phcoder(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Segher Boessenkool <segher(a)kernel.crashing.org> Modified: trunk/Makefile trunk/board_enable.c trunk/chipset_enable.c trunk/flash.h trunk/flashrom.c trunk/hwaccess.c trunk/hwaccess.h trunk/ichspi.c trunk/internal.c trunk/it87spi.c trunk/nic3com.c trunk/nicrealtek.c trunk/physmap.c trunk/print.c trunk/print_wiki.c trunk/sb600spi.c trunk/spi.c trunk/spi25.c trunk/wbsio_spi.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Wed May 26 01:27:44 2010 (r1012) +++ trunk/Makefile Wed May 26 03:45:41 2010 (r1013) @@ -124,7 +124,9 @@ ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'INTERNAL_SUPPORT=1' -PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o it87spi.o ichspi.o sb600spi.o wbsio_spi.o internal.o +PROGRAMMER_OBJS += chipset_enable.o board_enable.o cbtable.o dmi.o internal.o +# FIXME: The PROGRAMMER_OBJS below should only be included on x86. +PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o NEED_PCI := yes endif @@ -260,7 +262,7 @@ rm -f .dependencies .features .libdeps dep: - @$(CC) $(CPPFLAGS) $(SVNDEF) -MM *.c > .dependencies + @$(CC) $(CPPFLAGS) $(SVNDEF) -MM $(OBJS:.o=.c) > .dependencies strip: $(PROGRAM) $(STRIP) $(STRIP_ARGS) $(PROGRAM) Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Wed May 26 01:27:44 2010 (r1012) +++ trunk/board_enable.c Wed May 26 03:45:41 2010 (r1013) @@ -28,6 +28,7 @@ #include <fcntl.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) /* * Helper functions for many Winbond Super I/Os of the W836xx range. */ @@ -1348,6 +1349,8 @@ return it8712f_gpio_set(32, 1); } +#endif + /** * Below is the list of boards which need a special "board enable" code in * flashrom before their ROM chip can be accessed/written to. @@ -1391,6 +1394,7 @@ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ +#if defined(__i386__) || defined(__x86_64__) {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "Abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise}, {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, @@ -1458,7 +1462,7 @@ {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise}, {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise}, - +#endif { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */ }; Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Wed May 26 01:27:44 2010 (r1012) +++ trunk/chipset_enable.c Wed May 26 03:45:41 2010 (r1013) @@ -34,6 +34,8 @@ #include <fcntl.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + extern int ichspi_lock; static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) @@ -1285,8 +1287,11 @@ return 0; } +#endif + /* Please keep this list alphabetically sorted by vendor/device. */ const struct penable chipset_enables[] = { +#if defined(__i386__) || defined(__x86_64__) {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533}, {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111}, {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, @@ -1425,7 +1430,7 @@ {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111}, {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111}, - +#endif {}, }; Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Wed May 26 01:27:44 2010 (r1012) +++ trunk/flash.h Wed May 26 03:45:41 2010 (r1013) @@ -63,8 +63,10 @@ PROGRAMMER_ATAHPT, #endif #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) PROGRAMMER_IT87SPI, #endif +#endif #if FT2232_SPI_SUPPORT == 1 PROGRAMMER_FT2232SPI, #endif @@ -407,6 +409,12 @@ uint8_t mmio_readb(void *addr); uint16_t mmio_readw(void *addr); uint32_t mmio_readl(void *addr); +void mmio_le_writeb(uint8_t val, void *addr); +void mmio_le_writew(uint16_t val, void *addr); +void mmio_le_writel(uint32_t val, void *addr); +uint8_t mmio_le_readb(void *addr); +uint16_t mmio_le_readw(void *addr); +uint32_t mmio_le_readl(void *addr); /* programmer.c */ int noop_shutdown(void); @@ -603,6 +611,7 @@ enum spi_controller { SPI_CONTROLLER_NONE, #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, SPI_CONTROLLER_IT87XX, @@ -610,6 +619,7 @@ SPI_CONTROLLER_VIA, SPI_CONTROLLER_WBSIO, #endif +#endif #if FT2232_SPI_SUPPORT == 1 SPI_CONTROLLER_FT2232, #endif Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Wed May 26 01:27:44 2010 (r1012) +++ trunk/flashrom.c Wed May 26 03:45:41 2010 (r1013) @@ -276,6 +276,7 @@ #endif #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) { .name = "it87spi", .init = it87spi_init, @@ -293,6 +294,7 @@ .delay = internal_delay, }, #endif +#endif #if FT2232_SPI_SUPPORT == 1 { @@ -1208,16 +1210,21 @@ #endif #endif #ifdef __clang__ - msg_ginfo(" LLVM %i/clang %i", __llvm__, __clang__); + msg_ginfo(" LLVM %i/clang %i, ", __llvm__, __clang__); #elif defined(__GNUC__) msg_ginfo(" GCC"); #ifdef __VERSION__ - msg_ginfo(" %s", __VERSION__); + msg_ginfo(" %s,", __VERSION__); +#else + msg_ginfo(" unknown version,"); +#endif #else - msg_ginfo(" unknown version"); + msg_ginfo(" unknown compiler,"); #endif +#if defined (__FLASHROM_LITTLE_ENDIAN__) + msg_ginfo(" little endian"); #else - msg_ginfo(" unknown compiler"); + msg_ginfo(" big endian"); #endif msg_ginfo("\n"); } Modified: trunk/hwaccess.c ============================================================================== --- trunk/hwaccess.c Wed May 26 01:27:44 2010 (r1012) +++ trunk/hwaccess.c Wed May 26 03:45:41 2010 (r1013) @@ -26,6 +26,15 @@ #include <errno.h> #include "flash.h" +#if defined(__i386__) || defined(__x86_64__) + +/* sync primitive is not needed because x86 uses uncached accesses + * which have a strongly ordered memory model. + */ +static inline void sync_primitive(void) +{ +} + #if defined(__FreeBSD__) || defined(__DragonFly__) int io_fd; #endif @@ -54,19 +63,68 @@ #endif } +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + +static inline void sync_primitive(void) +{ + /* Prevent reordering and/or merging of reads/writes to hardware. + * Such reordering and/or merging would break device accesses which + * depend on the exact access order. + */ + asm("eieio" : : : "memory"); +} + +/* PCI port I/O is not yet implemented on PowerPC. */ +void get_io_perms(void) +{ +} + +/* PCI port I/O is not yet implemented on PowerPC. */ +void release_io_perms(void) +{ +} + +#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) + +/* sync primitive is not needed because /dev/mem on MIPS uses uncached accesses + * in mode 2 which has a strongly ordered memory model. + */ +static inline void sync_primitive(void) +{ +} + +/* PCI port I/O is not yet implemented on MIPS. */ +void get_io_perms(void) +{ +} + +/* PCI port I/O is not yet implemented on MIPS. */ +void release_io_perms(void) +{ +} + +#else + +#error Unknown architecture + +#endif + void mmio_writeb(uint8_t val, void *addr) { *(volatile uint8_t *) addr = val; + sync_primitive(); } void mmio_writew(uint16_t val, void *addr) { *(volatile uint16_t *) addr = val; + sync_primitive(); } void mmio_writel(uint32_t val, void *addr) { *(volatile uint32_t *) addr = val; + sync_primitive(); } uint8_t mmio_readb(void *addr) @@ -83,3 +141,33 @@ { return *(volatile uint32_t *) addr; } + +void mmio_le_writeb(uint8_t val, void *addr) +{ + mmio_writeb(cpu_to_le8(val), addr); +} + +void mmio_le_writew(uint16_t val, void *addr) +{ + mmio_writew(cpu_to_le16(val), addr); +} + +void mmio_le_writel(uint32_t val, void *addr) +{ + mmio_writel(cpu_to_le32(val), addr); +} + +uint8_t mmio_le_readb(void *addr) +{ + return le_to_cpu8(mmio_readb(addr)); +} + +uint16_t mmio_le_readw(void *addr) +{ + return le_to_cpu16(mmio_readw(addr)); +} + +uint32_t mmio_le_readl(void *addr) +{ + return le_to_cpu32(mmio_readl(addr)); +} Modified: trunk/hwaccess.h ============================================================================== --- trunk/hwaccess.h Wed May 26 01:27:44 2010 (r1012) +++ trunk/hwaccess.h Wed May 26 03:45:41 2010 (r1013) @@ -24,13 +24,139 @@ #ifndef __HWACCESS_H__ #define __HWACCESS_H__ 1 +#if defined (__i386__) || defined (__x86_64__) #if defined(__GLIBC__) #include <sys/io.h> #endif +#endif + #if NEED_PCI == 1 #include <pci/pci.h> #endif +#if defined (__i386__) || defined (__x86_64__) + +/* All x86 is little-endian. */ +#define __FLASHROM_LITTLE_ENDIAN__ 1 + +#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) + +/* MIPS can be either endian. */ +#if defined (__MIPSEL) || defined (__MIPSEL__) || defined (_MIPSEL) || defined (MIPSEL) +#define __FLASHROM_LITTLE_ENDIAN__ 1 +#elif defined (__MIPSEB) || defined (__MIPSEB__) || defined (_MIPSEB) || defined (MIPSEB) +#define __FLASHROM_BIG_ENDIAN__ 1 +#endif + +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + +/* PowerPC can be either endian. */ +#if defined (_BIG_ENDIAN) || defined (__BIG_ENDIAN__) +#define __FLASHROM_BIG_ENDIAN__ 1 +/* Error checking in case some weird header has #defines for LE as well. */ +#if defined (_LITTLE_ENDIAN) || defined (__LITTLE_ENDIAN__) +#error Conflicting endianness #define +#endif +#else +#error Little-endian PowerPC #defines are unknown +#endif + +#endif + +#if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__) +/* Nonstandard libc-specific macros for determining endianness. */ +#if defined(__GLIBC__) +#include <endian.h> +#if BYTE_ORDER == LITTLE_ENDIAN +#define __FLASHROM_LITTLE_ENDIAN__ 1 +#elif BYTE_ORDER == BIG_ENDIAN +#define __FLASHROM_BIG_ENDIAN__ 1 +#endif +#endif +#endif + +#if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__) +#error Unable to determine endianness. Please add support for your arch or libc. +#endif + +#define ___constant_swab8(x) ((uint8_t) ( \ + (((uint8_t)(x) & (uint8_t)0xffU)))) + +#define ___constant_swab16(x) ((uint16_t) ( \ + (((uint16_t)(x) & (uint16_t)0x00ffU) << 8) | \ + (((uint16_t)(x) & (uint16_t)0xff00U) >> 8))) + +#define ___constant_swab32(x) ((uint32_t) ( \ + (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \ + (((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \ + (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >> 8) | \ + (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24))) + +#define ___constant_swab64(x) ((uint64_t) ( \ + (((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \ + (((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \ + (((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \ + (((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) << 8) | \ + (((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \ + (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \ + (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \ + (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56))) + +#if defined (__FLASHROM_BIG_ENDIAN__) + +#define cpu_to_le(bits) \ +static inline uint##bits##_t cpu_to_le##bits(uint##bits##_t val) \ +{ \ + return ___constant_swab##bits(val); \ +} + +cpu_to_le(8) +cpu_to_le(16) +cpu_to_le(32) +cpu_to_le(64) + +#define cpu_to_be8 +#define cpu_to_be16 +#define cpu_to_be32 +#define cpu_to_be64 + +#elif defined (__FLASHROM_LITTLE_ENDIAN__) + +#define cpu_to_be(bits) \ +static inline uint##bits##_t cpu_to_be##bits(uint##bits##_t val) \ +{ \ + return ___constant_swab##bits(val); \ +} + +cpu_to_be(8) +cpu_to_be(16) +cpu_to_be(32) +cpu_to_be(64) + +#define cpu_to_le8 +#define cpu_to_le16 +#define cpu_to_le32 +#define cpu_to_le64 + +#else + +#error Could not determine endianness. + +#endif + +#define be_to_cpu8 cpu_to_be8 +#define be_to_cpu16 cpu_to_be16 +#define be_to_cpu32 cpu_to_be32 +#define be_to_cpu64 cpu_to_be64 +#define le_to_cpu8 cpu_to_le8 +#define le_to_cpu16 cpu_to_le16 +#define le_to_cpu32 cpu_to_le32 +#define le_to_cpu64 cpu_to_le64 + +#if defined (__i386__) || defined (__x86_64__) + +#define __FLASHROM_HAVE_OUTB__ 1 + /* for iopl and outb under Solaris */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) #include <strings.h> @@ -162,4 +288,18 @@ int freebsd_wrmsr(int addr, msr_t msr); #endif +#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) + +/* PCI port I/O is not yet implemented on PowerPC. */ + +#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) + +/* PCI port I/O is not yet implemented on MIPS. */ + +#else + +#error Unknown architecture, please check if it supports PCI port IO. + +#endif + #endif /* !__HWACCESS_H__ */ Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Wed May 26 01:27:44 2010 (r1012) +++ trunk/ichspi.c Wed May 26 03:45:41 2010 (r1013) @@ -33,6 +33,8 @@ * */ +#if defined(__i386__) || defined(__x86_64__) + #include <string.h> #include "flash.h" #include "chipdrivers.h" @@ -832,3 +834,5 @@ } return ret; } + +#endif Modified: trunk/internal.c ============================================================================== --- trunk/internal.c Wed May 26 01:27:44 2010 (r1012) +++ trunk/internal.c Wed May 26 03:45:41 2010 (r1013) @@ -99,10 +99,12 @@ #endif #if INTERNAL_SUPPORT == 1 -struct superio superio = {}; int force_boardenable = 0; int force_boardmismatch = 0; +#if defined(__i386__) || defined(__x86_64__) +struct superio superio = {}; + void probe_superio(void) { superio = probe_superio_ite(); @@ -112,8 +114,9 @@ superio = probe_superio_winbond(); #endif } +#endif -int is_laptop; +int is_laptop = 0; int internal_init(void) { @@ -166,10 +169,13 @@ * mainboard specific flash enable sequence. */ coreboot_init(); + +#if defined(__i386__) || defined(__x86_64__) dmi_init(); /* Probe for the Super I/O chip and fill global struct superio. */ probe_superio(); +#endif /* Warn if a laptop is detected. */ if (is_laptop) { @@ -203,8 +209,10 @@ "will most likely fail.\n"); } +#if defined(__i386__) || defined(__x86_64__) /* Probe for IT87* LPC->SPI translation unconditionally. */ it87xx_probe_spi_flash(NULL); +#endif board_flash_enable(lb_vendor, lb_part); Modified: trunk/it87spi.c ============================================================================== --- trunk/it87spi.c Wed May 26 01:27:44 2010 (r1012) +++ trunk/it87spi.c Wed May 26 03:45:41 2010 (r1013) @@ -23,6 +23,8 @@ * Contains the ITE IT87* SPI specific routines */ +#if defined(__i386__) || defined(__x86_64__) + #include <string.h> #include <stdlib.h> #include "flash.h" @@ -351,3 +353,5 @@ return 0; } + +#endif Modified: trunk/nic3com.c ============================================================================== --- trunk/nic3com.c Wed May 26 01:27:44 2010 (r1012) +++ trunk/nic3com.c Wed May 26 03:45:41 2010 (r1013) @@ -18,6 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if defined(__i386__) || defined(__x86_64__) + #include <stdlib.h> #include <string.h> #include <sys/types.h> @@ -112,3 +114,7 @@ OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); return INB(io_base_addr + BIOS_ROM_DATA); } + +#else +#error PCI port I/O access is not supported on this architecture yet. +#endif Modified: trunk/nicrealtek.c ============================================================================== --- trunk/nicrealtek.c Wed May 26 01:27:44 2010 (r1012) +++ trunk/nicrealtek.c Wed May 26 03:45:41 2010 (r1013) @@ -18,6 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if defined(__i386__) || defined(__x86_64__) + #include <stdlib.h> #include <string.h> #include <sys/types.h> @@ -93,3 +95,7 @@ return val; } + +#else +#error PCI port I/O access is not supported on this architecture yet. +#endif Modified: trunk/physmap.c ============================================================================== --- trunk/physmap.c Wed May 26 01:27:44 2010 (r1012) +++ trunk/physmap.c Wed May 26 03:45:41 2010 (r1013) @@ -241,6 +241,8 @@ return physmap_common(descr, phys_addr, len, PHYSMAP_MAYFAIL, PHYSMAP_RO); } +#if defined(__i386__) || defined(__x86_64__) + #ifdef __linux__ /* * Reading and writing to MSRs, however requires instructions rdmsr/wrmsr, @@ -462,4 +464,6 @@ #endif #endif #endif - +#else +/* Does MSR exist on non-x86 architectures? */ +#endif Modified: trunk/print.c ============================================================================== --- trunk/print.c Wed May 26 01:27:44 2010 (r1012) +++ trunk/print.c Wed May 26 03:45:41 2010 (r1013) @@ -261,6 +261,7 @@ /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info boards_ok[] = { /* Verified working boards that don't need write-enables. */ +#if defined(__i386__) || defined(__x86_64__) { "Abit", "AX8", }, { "Abit", "Fatal1ty F-I90HD", }, { "Advantech", "PCM-5820", }, @@ -381,13 +382,14 @@ { "VIA", "pc2500e", }, { "VIA", "PC3500G", }, { "VIA", "VB700X", }, - +#endif {}, }; /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info boards_bad[] = { /* Verified non-working boards (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Abit", "IS-10", }, { "ASRock", "K7VT4A+", }, { "ASUS", "MEW-AM", }, @@ -405,29 +407,31 @@ { "Sun", "Fire x4200", }, { "Sun", "Fire x4540", }, { "Sun", "Fire x4600", }, - +#endif {}, }; /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info laptops_ok[] = { /* Verified working laptops. */ +#if defined(__i386__) || defined(__x86_64__) { "Lenovo", "3000 V100 TF05Cxx", }, { "Acer", "Aspire 1520", }, - +#endif {}, }; /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info laptops_bad[] = { /* Verified non-working laptops (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire One", }, { "ASUS", "Eee PC 701 4G", }, { "Dell", "Latitude CPi A366XT", }, { "HP/Compaq", "nx9010", }, { "IBM/Lenovo", "Thinkpad T40p", }, { "IBM/Lenovo", "240", }, - +#endif {}, }; #endif Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Wed May 26 01:27:44 2010 (r1012) +++ trunk/print_wiki.c Wed May 26 03:45:41 2010 (r1013) @@ -104,6 +104,7 @@ /* Please keep these lists alphabetically ordered by vendor/board. */ const struct board_info_url boards_url[] = { /* Verified working boards that don't need write-enables. */ +#if defined(__i386__) || defined(__x86_64__) { "Abit", "AX8", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=…" }, { "Abit", "Fatal1ty F-I90HD", "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?pMODEL_NA…" }, { "Advantech", "PCM-5820", "http://www.emacinc.com/sbc_pc_compatible/pcm_5820.htm" }, @@ -279,8 +280,10 @@ { "VIA", "EPIA-N/NL", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…" }, /* EPIA-N link for now */ { "VIA", "EPIA SP", "http://www.via.com.tw/en/products/embedded/ProductDetail.jsp?productLine=1&…" }, { "VIA", "PC3500G", "http://www.via.com.tw/en/initiatives/empowered/pc3500_mainboard/index.jsp" }, +#endif /* Verified non-working boards (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Abit", "IS-10", "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NA…" }, { "ASRock", "K7VT4A+", "http://www.asrock.com/mb/overview.asp?Model=K7VT4A%%2b&s=" }, { "ASUS", "MEW-AM", "ftp://ftp.asus.com.tw/pub/ASUS/mb/sock370/810/mew-am/" }, @@ -298,18 +301,23 @@ { "Sun", "Fire x4150", "http://www.sun.com/servers/x64/x4150/" }, { "Sun", "Fire x4200", "http://www.sun.com/servers/entry/x4200/" }, { "Sun", "Fire x4600", "http://www.sun.com/servers/x64/x4600/" }, +#endif /* Verified working laptops. */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire 1520", "http://support.acer.com/us/en/acerpanam/notebook/0000/Acer/Aspire1520/Aspir…" }, { "Lenovo", "3000 V100 TF05Cxx", "http://www5.pc.ibm.com/europe/products.nsf/products?openagent&brand=Lenovo3…" }, +#endif /* Verified non-working laptops (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire One", NULL }, { "ASUS", "Eee PC 701 4G", "http://www.asus.com/product.aspx?P_ID=h6SPd3tEzLEsrEiS" }, { "Dell", "Latitude CPi A366XT", "http://www.coreboot.org/Dell_Latitude_CPi_A366XT" }, { "HP/Compaq", "nx9010", "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us…" }, { "IBM/Lenovo", "Thinkpad T40p", "http://www.thinkwiki.org/wiki/Category:T40p" }, { "IBM/Lenovo", "240", "http://www.stanford.edu/~bresnan//tp240.html" }, +#endif { NULL, NULL, 0 }, }; @@ -317,6 +325,7 @@ /* Please keep these lists alphabetically ordered by vendor/board. */ const struct board_info_notes boards_notes[] = { /* Verified working boards that don't need write-enables. */ +#if defined(__i386__) || defined(__x86_64__) { "ASI", "MB-5BLMP", "Used in the IGEL WinNET III thin client." }, { "ASRock", "K8S8X", "The Super I/O isn't found on this board. See http://www.flashrom.org/pipermail/flashrom/2009-November/000937.html." }, { "ASUS", "A8V-E SE", "See http://www.coreboot.org/pipermail/coreboot/2007-October/026496.html." }, @@ -324,23 +333,30 @@ { "BCOM", "WinNET100", "Used in the IGEL-316 thin client." }, { "GIGABYTE", "GA-7ZM", "Works fine if you remove jumper JP9 on the board and disable the flash protection BIOS option." }, { "ASUS", "M2N-E", "If the machine doesn't come up again after flashing, try resetting the NVRAM(CMOS). The MAC address of the onboard network card will change to the value stored in the new image, so backup the old address first. See http://www.flashrom.org/pipermail/flashrom/2009-November/000879.html" }, +#endif /* Verified working boards that DO need write-enables. */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire One", "See http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html." }, +#endif /* Verified non-working boards (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "MSI", "MS-6178", "Immediately powers off if you try to hot-plug the chip. However, this does '''not''' happen if you use coreboot." }, { "MSI", "MS-7260 (K9N Neo)", "Interestingly flashrom does not work when the vendor BIOS is booted, but it ''does'' work flawlessly when the machine is booted with coreboot." }, +#endif /* Verified working laptops. */ /* None which need comments, yet... */ /* Verified non-working laptops (for now). */ +#if defined(__i386__) || defined(__x86_64__) { "Acer", "Aspire One", "http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html" }, { "ASUS", "Eee PC 701 4G", "It seems the chip (25X40VSIG) is behind some SPI flash translation layer (likely in the EC, the ENE KB3310)." }, { "Dell", "Latitude CPi A366XT", "The laptop immediately powers off if you try to hot-swap the chip. It's not yet tested if write/erase would work on this laptop." }, { "HP/Compaq", "nx9010", "Hangs upon '''flashrom -V''' (needs hard power-cycle then)." }, { "IBM/Lenovo", "Thinkpad T40p", "Seems to (partially) work at first, but one block/sector cannot be written which then leaves you with a bricked laptop. Maybe this can be investigated and fixed in software later." }, +#endif { NULL, NULL, 0 }, }; Modified: trunk/sb600spi.c ============================================================================== --- trunk/sb600spi.c Wed May 26 01:27:44 2010 (r1012) +++ trunk/sb600spi.c Wed May 26 03:45:41 2010 (r1013) @@ -21,6 +21,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if defined(__i386__) || defined(__x86_64__) + #include <string.h> #include "flash.h" #include "chipdrivers.h" @@ -166,3 +168,5 @@ return 0; } + +#endif Modified: trunk/spi.c ============================================================================== --- trunk/spi.c Wed May 26 01:27:44 2010 (r1012) +++ trunk/spi.c Wed May 26 03:45:41 2010 (r1013) @@ -42,6 +42,7 @@ }, #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) { /* SPI_CONTROLLER_ICH7 */ .command = ich_spi_send_command, .multicommand = ich_spi_send_multicommand, @@ -84,6 +85,7 @@ .write_256 = wbsio_spi_write_1, }, #endif +#endif #if FT2232_SPI_SUPPORT == 1 { /* SPI_CONTROLLER_FT2232 */ Modified: trunk/spi25.c ============================================================================== --- trunk/spi25.c Wed May 26 01:27:44 2010 (r1012) +++ trunk/spi25.c Wed May 26 03:45:41 2010 (r1013) @@ -172,12 +172,14 @@ /* only some SPI chipsets support 4 bytes commands */ switch (spi_controller) { #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_ICH9: case SPI_CONTROLLER_VIA: case SPI_CONTROLLER_SB600: case SPI_CONTROLLER_WBSIO: #endif +#endif #if FT2232_SPI_SUPPORT == 1 case SPI_CONTROLLER_FT2232: #endif @@ -996,11 +998,13 @@ switch (spi_controller) { #if INTERNAL_SUPPORT == 1 +#if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_WBSIO: msg_cerr("%s: impossible with Winbond SPI masters," " degrading to byte program\n", __func__); return spi_chip_write_1(flash, buf); #endif +#endif default: break; } Modified: trunk/wbsio_spi.c ============================================================================== --- trunk/wbsio_spi.c Wed May 26 01:27:44 2010 (r1012) +++ trunk/wbsio_spi.c Wed May 26 03:45:41 2010 (r1013) @@ -18,6 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if defined(__i386__) || defined(__x86_64__) + #include <string.h> #include "flash.h" #include "chipdrivers.h" @@ -199,3 +201,5 @@ return spi_chip_write_1(flash, buf); } + +#endif

1 0

[PATCH] Debian: Missing build dependency: subversion
by adrian.glaubitz＠googlemail.com 26 May '10

26 May '10

Hi, the Debian package of flashrom misses the build dependency on subversion in its control file. Subversion is not installed when choosing "Standard system" and "Desktop system" with tasksel. I tried to build flashrom on a freshly installed Debian unstable machine (alpha) and I couldn't check-out the source because of the missing subversion. Adrian

4 3

[PATCH] Mark some more chips as tested
by Uwe Hermann 26 May '10

26 May '10

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

2 2

[commit] r1012 - trunk
by repository service 26 May '10

26 May '10

Author: uwe Date: Wed May 26 01:27:44 2010 New Revision: 1012 URL: http://flashrom.org/trac/coreboot/changeset/1012 Log: Mark the following chips as OK: - PMC Pm49FL004 - SST SST49LF020 - SST SST49LF020A - SST SST49LF040B - SST SST49LF080A - Winbond W39V040B I tested all operations on hardware using r997. Only on SST49LF040B write/erase does not seem to work, will investigate later (probe/read works, though). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashchips.c Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Mon May 24 19:39:14 2010 (r1011) +++ trunk/flashchips.c Wed May 26 01:27:44 2010 (r1012) @@ -3557,7 +3557,7 @@ .total_size = 512, .page_size = 64 * 1024, .feature_bits = FEATURE_REGISTERMAP | FEATURE_EITHER_RESET, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* routine is wrapper to probe_jedec (pm49fl00x.c) */ .block_erasers = @@ -4470,7 +4470,7 @@ .total_size = 256, .page_size = 16 * 1024, .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 1, /* 150 ns */ .block_erasers = @@ -4499,7 +4499,7 @@ .total_size = 256, .page_size = 4 * 1024, .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 1, /* 150 ns */ .block_erasers = @@ -4557,7 +4557,7 @@ .total_size = 512, .page_size = 64 * 1024, .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PR, .probe = probe_jedec, .probe_timing = 1, /* 150ns */ .block_erasers = @@ -4586,7 +4586,7 @@ .total_size = 1024, .page_size = 4096, .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = TIMING_FIXME, .block_erasers = @@ -6034,7 +6034,7 @@ .total_size = 512, .page_size = 64 * 1024, .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_OK_PRW, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 10, .block_erasers =

1 0

HP ProBook 4510s flashrom rev1010 probe/read SUCCESS!
by Антон Кочков 25 May '10

25 May '10

spec: http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c017… I'm try to read bios with flashrom. All works fine -- Best regards, XVilka.

1 0

Platform preprocessor #defines: MinGW
by Uwe Hermann 24 May '10

24 May '10

This is from a Windows XP box with MinGW (gcc 3.4.5): 'uname' or 'uname -s': MINGW32_NT-5.1 'uname -p': unknown 'uname -a': MINGW32_NT-5.1 COMPUTER 1.0.11(0.46/3/2) 2009-07-11 17:46 i686 Msys echo | gcc -E -dM -: #define __DBL_MIN_EXP__ (-1021) #define __FLT_MIN__ 1.17549435e-38F #define __CHAR_BIT__ 8 #define __WCHAR_MAX__ 65535U #define __DBL_DENORM_MIN__ 4.9406564584124654e-324 #define __FLT_EVAL_METHOD__ 2 #define __DBL_MIN_10_EXP__ (-307) #define __FINITE_MATH_ONLY__ 0 #define __GNUC_PATCHLEVEL__ 5 #define _stdcall __attribute__((__stdcall__)) #define __SHRT_MAX__ 32767 #define __LDBL_MAX__ 1.18973149535723176502e+4932L #define __LDBL_MAX_EXP__ 16384 #define __SCHAR_MAX__ 127 #define __USER_LABEL_PREFIX__ _ #define __STDC_HOSTED__ 1 #define __WIN32 1 #define __LDBL_HAS_INFINITY__ 1 #define __DBL_DIG__ 15 #define __FLT_EPSILON__ 1.19209290e-7F #define __tune_i686__ 1 #define __LDBL_MIN__ 3.36210314311209350626e-4932L #define __DECIMAL_DIG__ 21 #define __LDBL_HAS_QUIET_NAN__ 1 #define __GNUC__ 3 #define _cdecl __attribute__((__cdecl__)) #define __DBL_MAX__ 1.7976931348623157e+308 #define __WINNT 1 #define __DBL_HAS_INFINITY__ 1 #define __WINNT__ 1 #define _fastcall __attribute__((__fastcall__)) #define __USING_SJLJ_EXCEPTIONS__ 1 #define __DBL_MAX_EXP__ 1024 #define __WIN32__ 1 #define __LONG_LONG_MAX__ 9223372036854775807LL #define __GXX_ABI_VERSION 1002 #define __FLT_MIN_EXP__ (-125) #define __DBL_MIN__ 2.2250738585072014e-308 #define __DBL_HAS_QUIET_NAN__ 1 #define __REGISTER_PREFIX__ #define __cdecl __attribute__((__cdecl__)) #define __NO_INLINE__ 1 #define __i386 1 #define __FLT_MANT_DIG__ 24 #define __VERSION__ "3.4.5 (mingw-vista special r3)" #define _WIN32 1 #define _X86_ 1 #define i386 1 #define __i386__ 1 #define __SIZE_TYPE__ unsigned int #define __FLT_RADIX__ 2 #define __LDBL_EPSILON__ 1.08420217248550443401e-19L #define __MSVCRT__ 1 #define __FLT_HAS_QUIET_NAN__ 1 #define __FLT_MAX_10_EXP__ 38 #define __LONG_MAX__ 2147483647L #define __FLT_HAS_INFINITY__ 1 #define __stdcall __attribute__((__stdcall__)) #define __LDBL_MANT_DIG__ 64 #define __WCHAR_TYPE__ short unsigned int #define __FLT_DIG__ 6 #define __INT_MAX__ 2147483647 #define WIN32 1 #define __MINGW32__ 1 #define __FLT_MAX_EXP__ 128 #define __DBL_MANT_DIG__ 53 #define __WINT_TYPE__ short unsigned int #define __LDBL_MIN_EXP__ (-16381) #define __LDBL_MAX_10_EXP__ 4932 #define __DBL_EPSILON__ 2.2204460492503131e-16 #define __tune_pentiumpro__ 1 #define __fastcall __attribute__((__fastcall__)) #define WINNT 1 #define __FLT_DENORM_MIN__ 1.40129846e-45F #define __FLT_MAX__ 3.40282347e+38F #define __FLT_MIN_10_EXP__ (-37) #define __GNUC_MINOR__ 4 #define __DBL_MAX_10_EXP__ 308 #define __LDBL_DENORM_MIN__ 3.64519953188247460253e-4951L #define __PTRDIFF_TYPE__ int #define __LDBL_MIN_10_EXP__ (-4931) #define __LDBL_DIG__ 18 #define __declspec(x) __attribute__((x)) HTH, Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

1 0

Fwd: Asus M2N flashrom write/erase failed!
by Антон Кочков 24 May '10

24 May '10

Hello! I have an Asus M2N board Chipset nForce 430 MCP61 I tryed to write some modified bios image in flash and flashrom failed. on erasing I try to read new flash to bios2.bin and see that only 0000-ffff range are corrupted (FF) Corrupted image in bios2.rom file -- Best regards, XVilka.

1 0

[commit] r1011 - trunk
by repository service 24 May '10

24 May '10

Author: uwe Date: Mon May 24 19:39:14 2010 New Revision: 1011 URL: http://flashrom.org/trac/coreboot/changeset/1011 Log: Various nicrealtek fixes: - Add missing entries for 'flashrom -L' output and wiki output. - Add missing entries in the manpage. - nicrealtek.c: Coding style fixes and cosmetics. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/flashrom.8 trunk/nicrealtek.c trunk/print.c trunk/print_wiki.c Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Mon May 24 18:03:57 2010 (r1010) +++ trunk/flashrom.8 Mon May 24 19:39:14 2010 (r1011) @@ -152,6 +152,10 @@ .sp .BR "* nic3com" " (for flash ROMs on 3COM network cards)" .sp +.BR "* nicrealtek" " (for flash ROMs on Realtek network cards)" +.sp +.BR "* nicsmc1211" " (for flash ROMs on RTL8139-compatible SMC2 network cards)" +.sp .BR "* gfxnvidia" " (for flash ROMs on NVIDIA graphics cards)" .sp .BR "* drkaiser" " (for flash ROMs on Dr. Kaiser PC-Waechter PCI cards)" @@ -276,7 +280,7 @@ Example: .B "flashrom -p dummy:lpc,fwh" .TP -.BR "nic3com" , " gfxnvidia" , " satasii " and " atahpt " programmers +.BR "nic3com" , " nicrealtek" , " nicsmc1211" , " gfxnvidia" , " satasii " and " atahpt " programmers These programmers have an option to specify the PCI address of the card your want to use, which must be specified if more than one card supported by the selected programmer is installed in your system. The syntax is Modified: trunk/nicrealtek.c ============================================================================== --- trunk/nicrealtek.c Mon May 24 18:03:57 2010 (r1010) +++ trunk/nicrealtek.c Mon May 24 19:39:14 2010 (r1011) @@ -30,34 +30,34 @@ #define BIOS_ROM_DATA 0xD7 struct pcidev_status nics_realtek[] = { - {0x10ec, 0x8139, OK, "Realtek","rtl8139b/c PCI 10/100 Mbps"}, + {0x10ec, 0x8139, OK, "Realtek", "RTL8139/8139C/8139C+"}, {}, }; struct pcidev_status nics_realteksmc1211[] = { - {0x1113, 0x1211, OK, "SMC", "SMC 1211TX rtl8139 clone 10/100 Mbps"}, - {} + {0x1113, 0x1211, OK, "SMC2", "1211TX"}, /* RTL8139 clone */ + {}, }; - int nicrealtek_init(void) { get_io_perms(); + io_base_addr = pcidev_init(PCI_VENDOR_ID_REALTEK, PCI_BASE_ADDRESS_0, - nics_realtek, programmer_param); - + nics_realtek, programmer_param); + buses_supported = CHIP_BUSTYPE_PARALLEL; return 0; } - int nicsmc1211_init(void) { get_io_perms(); + io_base_addr = pcidev_init(PCI_VENDOR_ID_SMC1211, PCI_BASE_ADDRESS_0, - nics_realteksmc1211, programmer_param); - + nics_realteksmc1211, programmer_param); + buses_supported = CHIP_BUSTYPE_PARALLEL; return 0; @@ -73,17 +73,23 @@ void nicrealtek_chip_writeb(uint8_t val, chipaddr addr) { - OUTL(((uint32_t)addr &0x01FFFF)|0x0A0000| (val << 24), io_base_addr + BIOS_ROM_ADDR); - OUTL(((uint32_t)addr &0x01FFFF)|0x1E0000| (val << 24), io_base_addr + BIOS_ROM_ADDR); + OUTL(((uint32_t)addr & 0x01FFFF) | 0x0A0000 | (val << 24), + io_base_addr + BIOS_ROM_ADDR); + OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24), + io_base_addr + BIOS_ROM_ADDR); } uint8_t nicrealtek_chip_readb(const chipaddr addr) - { - uint8_t val=INB(io_base_addr + BIOS_ROM_DATA); - OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24), io_base_addr + BIOS_ROM_ADDR); - val=INB(io_base_addr + BIOS_ROM_DATA); - OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24), io_base_addr + BIOS_ROM_ADDR); - return val ; + uint8_t val; + + val = INB(io_base_addr + BIOS_ROM_DATA); + OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24), + io_base_addr + BIOS_ROM_ADDR); + + val = INB(io_base_addr + BIOS_ROM_DATA); + OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24), + io_base_addr + BIOS_ROM_ADDR); + return val; } Modified: trunk/print.c ============================================================================== --- trunk/print.c Mon May 24 18:03:57 2010 (r1010) +++ trunk/print.c Mon May 24 19:39:14 2010 (r1011) @@ -238,6 +238,10 @@ #if NIC3COM_SUPPORT == 1 print_supported_pcidevs(nics_3com); #endif +#if NICREALTEK_SUPPORT == 1 + print_supported_pcidevs(nics_realtek); + print_supported_pcidevs(nics_realteksmc1211); +#endif #if GFXNVIDIA_SUPPORT == 1 print_supported_pcidevs(gfx_nvidia); #endif Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Mon May 24 18:03:57 2010 (r1010) +++ trunk/print_wiki.c Mon May 24 19:39:14 2010 (r1011) @@ -592,6 +592,10 @@ #if NIC3COM_SUPPORT == 1 print_supported_pcidevs_wiki(nics_3com); #endif +#if NICREALTEK_SUPPORT == 1 + print_supported_pcidevs_wiki(nics_realtek); + print_supported_pcidevs_wiki(nics_realteksmc1211); +#endif #if GFXNVIDIA_SUPPORT == 1 print_supported_pcidevs_wiki(gfx_nvidia); #endif

1 0

Nokia IP530 lspci for flashrom
by mbertens 24 May '10

24 May '10

On request, but now the the file, sorry for that Marc

1 1

[commit] r1010 - trunk
by repository service 24 May '10

24 May '10

Author: mkarcher Date: Mon May 24 18:03:57 2010 New Revision: 1010 URL: http://flashrom.org/trac/coreboot/changeset/1010 Log: Board enable for IP530 Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Marc Bertens <mbertens(a)xs4all.nl> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Mon May 24 17:28:12 2010 (r1009) +++ trunk/board_enable.c Mon May 24 18:03:57 2010 (r1010) @@ -96,6 +96,48 @@ #endif /** + * SMSC FDC37B787: Raise GPIO50 + */ + +static int fdc37b787_gpio50_raise(uint16_t port, const char * name) +{ + uint8_t id, val; + + OUTB(0x55, port); /* enter conf mode */ + id = sio_read(port, 0x20); + if (id != 0x44) { + fprintf(stderr, "\nERROR: %s: FDC37B787: Wrong ID 0x%02X.\n", + name, id); + OUTB(0xAA, port); /* leave conf mode */ + return -1; + } + + sio_write(port, 0x07, 0x08); /* Select Aux I/O subdevice */ + + val = sio_read(port, 0xC8); /* GP50 */ + if ((val & 0x1B) != 0x10) /* output, no invert, GPIO */ + { + fprintf(stderr, "\nERROR: %s: GPIO50 mode 0x%02X unexpected.\n", + name, val); + OUTB(0xAA, port); + return -1; + } + + sio_mask(port, 0xF9, 0x01, 0x01); + + OUTB(0xAA, port); /* Leave conf mode */ + return 0; +} + +/** + * Suited for Nokia IP530: Intel 440BX + PIIX4 + FDC37B787 + */ +static int fdc37b787_gpio50_raise_3f0(const char *name) +{ + return fdc37b787_gpio50_raise(0x3f0, name); +} + +/** * Winbond W83627HF: Raise GPIO24. * * Suited for: @@ -1406,6 +1448,7 @@ {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio4_4_raise_4e}, {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8N GM2-L)", 0, NT, nvidia_mcp_gpio2_raise}, {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, + {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0}, {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, OK, board_shuttle_fn25},

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[commit] r1009 - trunk
by repository service 24 May '10

24 May '10

Author: uwe Date: Mon May 24 17:28:12 2010 New Revision: 1009 URL: http://flashrom.org/trac/coreboot/changeset/1009 Log: Various wiki output improvements as per IRC discussion (trivial). - Use '?3' wiki template (light greenish, not gray) for untested stuff. - Reduce page width a bit to improve readability on smaller screens. - Generalize some functions a bit (pass in how many columns to generate). - Mark untested board-enables as such (were incorrectly marked "OK" so far). - Drop some useless 'valign=top' entries. - Make a few more functions 'static' while we're at it. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/print_wiki.c Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Sat May 22 09:31:50 2010 (r1008) +++ trunk/print_wiki.c Mon May 24 17:28:12 2010 (r1009) @@ -371,7 +371,7 @@ return -1; } -void print_supported_chipsets_wiki(void) +static void print_supported_chipsets_wiki(int cols) { int i, j, enablescount = 0, color = 1; const struct penable *e; @@ -389,14 +389,14 @@ if (i > 0 && strcmp(e[i].vendor_name, e[i - 1].vendor_name)) color = !color; - printf("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s " + printf("|- bgcolor=\"#%s\"\n| %s || %s " "|| %04x:%04x || %s\n", (color) ? "eeeeee" : "dddddd", e[i].vendor_name, e[i].device_name, e[i].vendor_id, e[i].device_id, - (e[i].status == OK) ? "{{OK}}" : "?"); + (e[i].status == OK) ? "{{OK}}" : "{{?3}}"); - /* Split table in three columns. */ - if (j >= (enablescount / 3 + 1)) { + /* Split table in 'cols' columns. */ + if (j >= (enablescount / cols + 1)) { printf("\n|}\n\n| valign=\"top\"|\n\n%s", chipset_th); j = 0; } @@ -429,7 +429,7 @@ k = url(b[i].vendor, b[i].name); c = note(b[i].vendor, b[i].name); - printf("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s%s %s%s ||" + printf("|- bgcolor=\"#%s\"\n| %s || %s%s %s%s ||" " {{%s}}", (color) ? "eeeeee" : "dddddd", b[i].vendor, (k != -1 && u[k].url) ? "[" : "", (k != -1 && u[k].url) ? u[k].url : "", @@ -479,17 +479,18 @@ k = url(b[i].vendor_name, b[i].board_name); - printf("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s%s %s%s " - "|| %s%s%s%s || {{OK}}\n", (color) ? "eeeeee" : "dddddd", + printf("|- bgcolor=\"#%s\"\n| %s || %s%s %s%s " + "|| %s%s%s%s || {{%s}}\n", (color) ? "eeeeee" : "dddddd", b[i].vendor_name, (k != -1 && u[k].url) ? "[" : "", (k != -1 && u[k].url) ? u[k].url : "", b[i].board_name, (k != -1 && u[k].url) ? "]" : "", (b[i].lb_vendor) ? "-m " : "—", (b[i].lb_vendor) ? b[i].lb_vendor : "", (b[i].lb_vendor) ? ":" : "", - (b[i].lb_vendor) ? b[i].lb_part : ""); + (b[i].lb_vendor) ? b[i].lb_part : "", + (b[i].status == OK) ? "OK" : "?3"); - /* Split table in three columns. */ + /* Split table in 'cols' columns. */ if (j >= (boardcount / cols + 1)) { printf("\n|}\n\n| valign=\"top\"|\n\n%s", board_th2); j = 0; @@ -499,11 +500,11 @@ printf("\n|}\n\n|}\n"); } -void print_supported_boards_wiki(void) +static void print_supported_boards_wiki(void) { printf("%s", board_intro); wiki_helper("Known good (worked out of the box)", "OK", 3, boards_ok); - wiki_helper2("Known good (with write-enable code in flashrom)", 3); + wiki_helper2("Known good (with write-enable code in flashrom)", 2); wiki_helper("Not supported (yet)", "No", 3, boards_bad); printf("%s", laptop_intro); @@ -512,7 +513,7 @@ } #endif -void print_supported_chips_wiki(void) +static void print_supported_chips_wiki(int cols) { int i = 0, c = 1, chipcount = 0; struct flashchip *f, *old = NULL; @@ -535,21 +536,21 @@ c = !c; t = f->tested; - printf("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s || %d " + printf("|- bgcolor=\"#%s\"\n| %s || %s || %d " "|| %s || {{%s}} || {{%s}} || {{%s}} || {{%s}}\n", (c == 1) ? "eeeeee" : "dddddd", f->vendor, f->name, f->total_size, flashbuses_to_text(f->bustype), (t & TEST_OK_PROBE) ? "OK" : - (t & TEST_BAD_PROBE) ? "No" : ((c) ? "?2" : "?"), + (t & TEST_BAD_PROBE) ? "No" : "?3", (t & TEST_OK_READ) ? "OK" : - (t & TEST_BAD_READ) ? "No" : ((c) ? "?2" : "?"), + (t & TEST_BAD_READ) ? "No" : "?3", (t & TEST_OK_ERASE) ? "OK" : - (t & TEST_BAD_ERASE) ? "No" : ((c) ? "?2" : "?"), + (t & TEST_BAD_ERASE) ? "No" : "?3", (t & TEST_OK_WRITE) ? "OK" : - (t & TEST_BAD_WRITE) ? "No" : ((c) ? "?2" : "?")); + (t & TEST_BAD_WRITE) ? "No" : "?3"); - /* Split table into three columns. */ - if (i >= (chipcount / 3 + 1)) { + /* Split table into 'cols' columns. */ + if (i >= (chipcount / cols + 1)) { printf("\n|}\n\n| valign=\"top\"|\n\n%s", chip_th); i = 0; } @@ -560,7 +561,7 @@ printf("\n|}\n\n|}\n"); } -void print_supported_pcidevs_wiki(struct pcidev_status *devs) +static void print_supported_pcidevs_wiki(struct pcidev_status *devs) { int i = 0; static int c = 0; @@ -569,11 +570,11 @@ c = !c; for (i = 0; devs[i].vendor_name != NULL; i++) { - printf("|- bgcolor=\"#%s\" valign=\"top\"\n| %s || %s || " + printf("|- bgcolor=\"#%s\"\n| %s || %s || " "%04x:%04x || {{%s}}\n", (c) ? "eeeeee" : "dddddd", devs[i].vendor_name, devs[i].device_name, devs[i].vendor_id, devs[i].device_id, - (devs[i].status == NT) ? (c) ? "?2" : "?" : "OK"); + (devs[i].status == NT) ? "?3" : "OK"); } } @@ -583,8 +584,8 @@ printf(wiki_header, ctime(&t), flashrom_version); #if INTERNAL_SUPPORT == 1 - print_supported_chips_wiki(); - print_supported_chipsets_wiki(); + print_supported_chips_wiki(2); + print_supported_chipsets_wiki(3); print_supported_boards_wiki(); #endif printf("%s", programmer_section);

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Nokia IP530 lspci for flashrom
by mbertens 24 May '10

24 May '10

On request Marc

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new version flashrom with Nokia IP530
by mbertens 24 May '10

24 May '10

hi all, i checked out the new version of flashrom, but it seems it was missing the patches that where done for the Nokia IP530 Marc

1 0

flash not found on Gigabyte GA-K8VM800M
by Guenter 24 May '10

24 May '10

Hi, just came over a Gigabyte MB GA-K8VM800M, and flash chip was not found; attached verbose output. Gün.

1 0

DOS version of flashrom
by Andrew Goodbody 23 May '10

23 May '10

Hi, I tried to build flashrom for DOS on Ubuntu 10.04 following the instructions in the flashrom README. There are quite a few issues with missing steps and stuff that simply does not work. I finally gave up when it could not resolve _valloc. I would very much like to know the rest of the instructions for a successful cross compile to DOS. I saw that Carl-Daniel Hailfinger has offered to proved a tar ball of the cross compiler etc but it would be really good to be able to fix the instructions in the README. Then I found the flashrom mailing list archive with a reference to a prebuilt version on Rudolf Marek's site - thanks. I have now run this and apart from not being able to find 'dmidecode' it managed to correctly identify the SPI device (a W25x32) on the system behind an ICH9M-E which is in descriptor mode but not locked down. Andrew

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Re: [flashrom] spi_block_erase_d8 failed during command execution
by Michael Karcher 23 May '10

23 May '10

Am Sonntag, den 23.05.2010, 11:31 +0200 schrieb Dominic Fandrey: > I suspect I just bricked my notebook. I tried to flash it with a > BIOS image I exchanged some device IDs in. It failed with the subject > error and I tried to flash again with the backup, which failed in > the same manner (needless to say I dare not reboot at the moment). > > Attached are the error output and the dmidecode output. I can also > supply the BIOS images to you. [attachment edited to remove repetitive part] > Kind regards, > Dominic Fandrey

2 2

[PATCH] Make satasii driver more robust
by Carl-Daniel Hailfinger 23 May '10

23 May '10

Make the satasii driver more robust. Untested. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-satasii_robust/satasii.c =================================================================== --- flashrom-satasii_robust/satasii.c (Revision 1005) +++ flashrom-satasii_robust/satasii.c (Arbeitskopie) @@ -44,6 +44,7 @@ { uint32_t addr; uint16_t reg_offset; + uint32_t tmp; get_io_perms(); @@ -59,12 +60,19 @@ reg_offset = 0x50; } - sii_bar = physmap("SATA SIL registers", addr, 0x100) + reg_offset; + sii_bar = physmap("SATA SiI registers", addr, 0x100) + reg_offset; /* Check if ROM cycle are OK. */ if ((id != 0x0680) && (!(mmio_readl(sii_bar) & (1 << 26)))) msg_pinfo("Warning: Flash seems unconnected.\n"); + msg_pdbg("Using BAR5 access method.\n"); + tmp = pci_read_long(pcidev_dev, 0x40) & (1 << 1); + msg_pdbg("BAR5 Indirect Access is %snabled\n", tmp ? "en" : "dis"); + /* This bit has contradicting definitions in the 3512 datasheet. */ + tmp = pci_read_long(pcidev_dev, 0x88) & (1 << 16); + msg_pdbg("BAR5 Access is %snabled\n", tmp ? "en" : "dis"); + buses_supported = CHIP_BUSTYPE_PARALLEL; return 0; @@ -81,6 +89,7 @@ void satasii_chip_writeb(uint8_t val, chipaddr addr) { uint32_t ctrl_reg, data_reg; + int i = 0; while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; @@ -92,12 +101,19 @@ mmio_writel(data_reg, (sii_bar + 4)); mmio_writel(ctrl_reg, sii_bar); - while (mmio_readl(sii_bar) & (1 << 25)) ; + while (mmio_readl(sii_bar) & (1 << 25)) { + if (++i > 10000) { + msg_perr("%s: control reg stuck at %08x, aborting\n", + __func__, mmio_readl(sii_bar)); + break; + } + } } uint8_t satasii_chip_readb(const chipaddr addr) { uint32_t ctrl_reg; + int i = 0; while ((ctrl_reg = mmio_readl(sii_bar)) & (1 << 25)) ; @@ -107,7 +123,13 @@ mmio_writel(ctrl_reg, sii_bar); - while (mmio_readl(sii_bar) & (1 << 25)) ; + while (mmio_readl(sii_bar) & (1 << 25)) { + if (++i > 10000) { + msg_perr("%s: control reg stuck at %08x, aborting\n", + __func__, mmio_readl(sii_bar)); + break; + } + } return (mmio_readl(sii_bar + 4)) & 0xff; } -- http://www.hailfinger.org/

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