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flashrom -V
by Jim Lunsford 20 Jun '10

20 Jun '10

my first flashrom -V is attached as document jim lunsford do you want others?

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[PATCH] Fill in buses_supported for remaining Intel chipsets
by Carl-Daniel Hailfinger 20 Jun '10

20 Jun '10

Fill in buses_supported for remaining Intel chipsets (ICH0-ICH5, Poulsbo). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-ich_bustype/chipset_enable.c =================================================================== --- flashrom-ich_bustype/chipset_enable.c (revision 1033) +++ flashrom-ich_bustype/chipset_enable.c (working copy) @@ -286,6 +286,7 @@ * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and * FB_DEC_EN2. */ + buses_supported = CHIP_BUSTYPE_FWH; return enable_flash_ich(dev, name, 0x4e); } @@ -399,6 +400,7 @@ if (new != old) pci_write_byte(dev, 0xd9, new); + buses_supported = CHIP_BUSTYPE_FWH; return 0; } -- http://www.hailfinger.org/

2 2

[commit] r1055 - trunk
by repository service 20 Jun '10

20 Jun '10

Author: hailfinger Date: Sun Jun 20 13:04:26 2010 New Revision: 1055 URL: http://flashrom.org/trac/coreboot/changeset/1055 Log: Fill in buses_supported for remaining Intel chipsets (ICH0-ICH5, Poulsbo). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/chipset_enable.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Sun Jun 20 13:02:33 2010 (r1054) +++ trunk/chipset_enable.c Sun Jun 20 13:04:26 2010 (r1055) @@ -288,6 +288,7 @@ * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and * FB_DEC_EN2. */ + buses_supported = CHIP_BUSTYPE_FWH; return enable_flash_ich(dev, name, 0x4e); } @@ -401,6 +402,7 @@ if (new != old) pci_write_byte(dev, 0xd9, new); + buses_supported = CHIP_BUSTYPE_FWH; return 0; }

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[PATCH] Kill fake SPI D8 chip erase
by Carl-Daniel Hailfinger 20 Jun '10

20 Jun '10

The SPI opcode 0xd8 is not a chip erase opcode on any chip out there. Besides that, the function as implemented just walks the chip and ignores sector sizes. Sector erase with SPI opcode 0xd8 is of course still supported. Kill a declaration for a nonexisting function while we're at it. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-kill_fake_spi_chip_erase_d8/spi25.c =================================================================== --- flashrom-kill_fake_spi_chip_erase_d8/spi25.c (Revision 1028) +++ flashrom-kill_fake_spi_chip_erase_d8/spi25.c (Arbeitskopie) @@ -652,29 +652,6 @@ return 0; } -int spi_chip_erase_d8(struct flashchip *flash) -{ - int i, rc = 0; - int total_size = flash->total_size * 1024; - int erase_size = 64 * 1024; - - spi_disable_blockprotect(); - - msg_cinfo("Erasing chip: \n"); - - for (i = 0; i < total_size / erase_size; i++) { - rc = spi_block_erase_d8(flash, i * erase_size, erase_size); - if (rc) { - msg_cerr("Error erasing block at 0x%x\n", i); - break; - } - } - - msg_cinfo("\n"); - - return rc; -} - /* Sector size is usually 4k, though Macronix eliteflash has 64k */ int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen) { Index: flashrom-kill_fake_spi_chip_erase_d8/chipdrivers.h =================================================================== --- flashrom-kill_fake_spi_chip_erase_d8/chipdrivers.h (Revision 1028) +++ flashrom-kill_fake_spi_chip_erase_d8/chipdrivers.h (Arbeitskopie) @@ -35,8 +35,6 @@ int spi_write_disable(void); int spi_chip_erase_60(struct flashchip *flash); int spi_chip_erase_c7(struct flashchip *flash); -int spi_chip_erase_60_c7(struct flashchip *flash); -int spi_chip_erase_d8(struct flashchip *flash); int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d7(struct flashchip *flash, unsigned int addr, unsigned int blocklen); -- http://www.hailfinger.org/

2 2

[commit] r1054 - trunk
by repository service 20 Jun '10

20 Jun '10

Author: hailfinger Date: Sun Jun 20 13:02:33 2010 New Revision: 1054 URL: http://flashrom.org/trac/coreboot/changeset/1054 Log: The SPI opcode 0xd8 is not a chip erase opcode on any chip out there. Besides that, the function as implemented just walks the chip and ignores sector sizes. Sector erase with SPI opcode 0xd8 is of course still supported. Kill a declaration for a nonexisting function while we're at it. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/chipdrivers.h trunk/spi25.c Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Sun Jun 20 12:58:32 2010 (r1053) +++ trunk/chipdrivers.h Sun Jun 20 13:02:33 2010 (r1054) @@ -35,8 +35,6 @@ int spi_write_disable(void); int spi_chip_erase_60(struct flashchip *flash); int spi_chip_erase_c7(struct flashchip *flash); -int spi_chip_erase_60_c7(struct flashchip *flash); -int spi_chip_erase_d8(struct flashchip *flash); int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d7(struct flashchip *flash, unsigned int addr, unsigned int blocklen); Modified: trunk/spi25.c ============================================================================== --- trunk/spi25.c Sun Jun 20 12:58:32 2010 (r1053) +++ trunk/spi25.c Sun Jun 20 13:02:33 2010 (r1054) @@ -646,29 +646,6 @@ return 0; } -int spi_chip_erase_d8(struct flashchip *flash) -{ - int i, rc = 0; - int total_size = flash->total_size * 1024; - int erase_size = 64 * 1024; - - spi_disable_blockprotect(); - - msg_cinfo("Erasing chip: \n"); - - for (i = 0; i < total_size / erase_size; i++) { - rc = spi_block_erase_d8(flash, i * erase_size, erase_size); - if (rc) { - msg_cerr("Error erasing block at 0x%x\n", i); - break; - } - } - - msg_cinfo("\n"); - - return rc; -} - /* Sector size is usually 4k, though Macronix eliteflash has 64k */ int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen) {

1 0

[PATCH] Add SPI chip read support to dummy flasher
by Carl-Daniel Hailfinger 20 Jun '10

20 Jun '10

Add SPI chip read support to the dummy flasher. This allows using the dummy flasher for SPI read debugging. Tested, works. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-dummy_spi_chip_read/flash.h =================================================================== --- flashrom-dummy_spi_chip_read/flash.h (Revision 1049) +++ flashrom-dummy_spi_chip_read/flash.h (Arbeitskopie) @@ -454,6 +454,7 @@ void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); +int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); #endif /* nic3com.c */ Index: flashrom-dummy_spi_chip_read/spi.c =================================================================== --- flashrom-dummy_spi_chip_read/spi.c (Revision 1049) +++ flashrom-dummy_spi_chip_read/spi.c (Arbeitskopie) @@ -99,7 +99,7 @@ { /* SPI_CONTROLLER_DUMMY */ .command = dummy_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = NULL, + .read = dummy_spi_read, .write_256 = NULL, }, #endif Index: flashrom-dummy_spi_chip_read/dummyflasher.c =================================================================== --- flashrom-dummy_spi_chip_read/dummyflasher.c (Revision 1049) +++ flashrom-dummy_spi_chip_read/dummyflasher.c (Arbeitskopie) @@ -23,6 +23,7 @@ #include <ctype.h> #include <sys/types.h> #include "flash.h" +#include "chipdrivers.h" int dummy_init(void) { @@ -157,3 +158,10 @@ msg_pspew("\n"); return 0; } + +int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + /* Maximum read length is unlimited, use 64kB. */ + return spi_read_chunked(flash, buf, start, len, 64 * 1024); +} + -- http://www.hailfinger.org/

2 2

[commit] r1053 - trunk
by repository service 20 Jun '10

20 Jun '10

Author: hailfinger Date: Sun Jun 20 12:58:32 2010 New Revision: 1053 URL: http://flashrom.org/trac/coreboot/changeset/1053 Log: Add SPI chip read support to the dummy flasher. This allows using the dummy flasher for SPI read debugging. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/dummyflasher.c trunk/flash.h trunk/spi.c Modified: trunk/dummyflasher.c ============================================================================== --- trunk/dummyflasher.c Sun Jun 20 12:41:35 2010 (r1052) +++ trunk/dummyflasher.c Sun Jun 20 12:58:32 2010 (r1053) @@ -23,6 +23,7 @@ #include <ctype.h> #include <sys/types.h> #include "flash.h" +#include "chipdrivers.h" int dummy_init(void) { @@ -157,3 +158,10 @@ msg_pspew("\n"); return 0; } + +int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + /* Maximum read length is unlimited, use 64kB. */ + return spi_read_chunked(flash, buf, start, len, 64 * 1024); +} + Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Sun Jun 20 12:41:35 2010 (r1052) +++ trunk/flash.h Sun Jun 20 12:58:32 2010 (r1053) @@ -454,6 +454,7 @@ void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); +int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); #endif /* nic3com.c */ Modified: trunk/spi.c ============================================================================== --- trunk/spi.c Sun Jun 20 12:41:35 2010 (r1052) +++ trunk/spi.c Sun Jun 20 12:58:32 2010 (r1053) @@ -99,7 +99,7 @@ { /* SPI_CONTROLLER_DUMMY */ .command = dummy_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = NULL, + .read = dummy_spi_read, .write_256 = NULL, }, #endif

1 0

[PATCH] Modernize SPI AAI code
by Carl-Daniel Hailfinger 20 Jun '10

20 Jun '10

Modernize SPI AAI code, blacklist IT87 SPI for AAI, allow AAI to run without warnings on ICH/VIA SPI. Add some code to make conversion to partial write possible for AAI. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_aai_modernize/spi25.c =================================================================== --- flashrom-spi_aai_modernize/spi25.c (Revision 1049) +++ flashrom-spi_aai_modernize/spi25.c (Arbeitskopie) @@ -1018,15 +1018,44 @@ int spi_aai_write(struct flashchip *flash, uint8_t *buf) { - uint32_t pos = 2, size = flash->total_size * 1024; - unsigned char w[6] = {0xad, 0, 0, 0, buf[0], buf[1]}; + uint32_t addr = 0; + uint32_t len = flash->total_size * 1024; + uint32_t pos = addr; int result; + unsigned char cmd[JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE] = { + JEDEC_AAI_WORD_PROGRAM, + }; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_AAI_WORD_PROGRAM_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_AAI_WORD_PROGRAM, + (pos >> 16) & 0xff, + (pos >> 8) & 0xff, + (pos & 0xff), + buf[0], + buf[1] + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; switch (spi_controller) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) + case SPI_CONTROLLER_IT87XX: case SPI_CONTROLLER_WBSIO: - msg_cerr("%s: impossible with Winbond SPI masters," + msg_cerr("%s: impossible with this SPI controller," " degrading to byte program\n", __func__); return spi_chip_write_1(flash, buf); #endif @@ -1034,24 +1063,46 @@ default: break; } + + /* The data sheet requires a start address with the low bit cleared. */ + if (addr % 2) { + msg_cerr("%s: start address not even! Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); + return SPI_GENERIC_ERROR; + } + /* The data sheet requires total AAI write length to be even. */ + if (len % 2) { + msg_cerr("%s: total write length not even! Please report a " + "bug at flashrom(a)flashrom.org\n", __func__); + return SPI_GENERIC_ERROR; + } + if (erase_flash(flash)) { msg_cerr("ERASE FAILED!\n"); return -1; } - /* FIXME: This will fail on ICH/VIA SPI. */ - result = spi_write_enable(); - if (result) + + result = spi_send_multicommand(cmds); + if (result) { + msg_cerr("%s failed during start command execution\n", + __func__); return result; - spi_send_command(6, 0, w, NULL); + } while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - programmer_delay(5); /* SST25VF040B Tbp is max 10us */ - while (pos < size) { - w[1] = buf[pos++]; - w[2] = buf[pos++]; - spi_send_command(3, 0, w, NULL); + programmer_delay(10); + + /* We already wrote 2 bytes in the multicommand step. */ + pos += 2; + + while (pos < addr + len) { + cmd[1] = buf[pos++]; + cmd[2] = buf[pos++]; + spi_send_command(JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE, 0, cmd, NULL); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - programmer_delay(5); /* SST25VF040B Tbp is max 10us */ + programmer_delay(10); } + + /* Use WRDI to exit AAI mode. */ spi_write_disable(); return 0; } Index: flashrom-spi_aai_modernize/spi.h =================================================================== --- flashrom-spi_aai_modernize/spi.h (Revision 1049) +++ flashrom-spi_aai_modernize/spi.h (Arbeitskopie) @@ -112,6 +112,12 @@ #define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05 #define JEDEC_BYTE_PROGRAM_INSIZE 0x00 +/* Write AAI word (SST25VF080B) */ +#define JEDEC_AAI_WORD_PROGRAM 0xad +#define JEDEC_AAI_WORD_PROGRAM_OUTSIZE 0x06 +#define JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE 0x06 +#define JEDEC_AAI_WORD_PROGRAM_INSIZE 0x00 + /* Error codes */ #define SPI_GENERIC_ERROR -1 #define SPI_INVALID_OPCODE -2 -- http://www.hailfinger.org/

2 2

[commit] r1052 - trunk
by repository service 20 Jun '10

20 Jun '10

Author: hailfinger Date: Sun Jun 20 12:41:35 2010 New Revision: 1052 URL: http://flashrom.org/trac/coreboot/changeset/1052 Log: Modernize SPI AAI code, blacklist IT87 SPI for AAI, allow AAI to run without warnings on ICH/VIA SPI. Add some code to make conversion to partial write possible for AAI. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/spi.h trunk/spi25.c Modified: trunk/spi.h ============================================================================== --- trunk/spi.h Sun Jun 20 12:39:33 2010 (r1051) +++ trunk/spi.h Sun Jun 20 12:41:35 2010 (r1052) @@ -112,6 +112,12 @@ #define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05 #define JEDEC_BYTE_PROGRAM_INSIZE 0x00 +/* Write AAI word (SST25VF080B) */ +#define JEDEC_AAI_WORD_PROGRAM 0xad +#define JEDEC_AAI_WORD_PROGRAM_OUTSIZE 0x06 +#define JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE 0x06 +#define JEDEC_AAI_WORD_PROGRAM_INSIZE 0x00 + /* Error codes */ #define SPI_GENERIC_ERROR -1 #define SPI_INVALID_OPCODE -2 Modified: trunk/spi25.c ============================================================================== --- trunk/spi25.c Sun Jun 20 12:39:33 2010 (r1051) +++ trunk/spi25.c Sun Jun 20 12:41:35 2010 (r1052) @@ -1012,15 +1012,44 @@ int spi_aai_write(struct flashchip *flash, uint8_t *buf) { - uint32_t pos = 2, size = flash->total_size * 1024; - unsigned char w[6] = {0xad, 0, 0, 0, buf[0], buf[1]}; + uint32_t addr = 0; + uint32_t len = flash->total_size * 1024; + uint32_t pos = addr; int result; + unsigned char cmd[JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE] = { + JEDEC_AAI_WORD_PROGRAM, + }; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_AAI_WORD_PROGRAM_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_AAI_WORD_PROGRAM, + (pos >> 16) & 0xff, + (pos >> 8) & 0xff, + (pos & 0xff), + buf[0], + buf[1] + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; switch (spi_controller) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) + case SPI_CONTROLLER_IT87XX: case SPI_CONTROLLER_WBSIO: - msg_cerr("%s: impossible with Winbond SPI masters," + msg_cerr("%s: impossible with this SPI controller," " degrading to byte program\n", __func__); return spi_chip_write_1(flash, buf); #endif @@ -1028,24 +1057,46 @@ default: break; } + + /* The data sheet requires a start address with the low bit cleared. */ + if (addr % 2) { + msg_cerr("%s: start address not even! Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); + return SPI_GENERIC_ERROR; + } + /* The data sheet requires total AAI write length to be even. */ + if (len % 2) { + msg_cerr("%s: total write length not even! Please report a " + "bug at flashrom(a)flashrom.org\n", __func__); + return SPI_GENERIC_ERROR; + } + if (erase_flash(flash)) { msg_cerr("ERASE FAILED!\n"); return -1; } - /* FIXME: This will fail on ICH/VIA SPI. */ - result = spi_write_enable(); - if (result) + + result = spi_send_multicommand(cmds); + if (result) { + msg_cerr("%s failed during start command execution\n", + __func__); return result; - spi_send_command(6, 0, w, NULL); + } while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - programmer_delay(5); /* SST25VF040B Tbp is max 10us */ - while (pos < size) { - w[1] = buf[pos++]; - w[2] = buf[pos++]; - spi_send_command(3, 0, w, NULL); + programmer_delay(10); + + /* We already wrote 2 bytes in the multicommand step. */ + pos += 2; + + while (pos < addr + len) { + cmd[1] = buf[pos++]; + cmd[2] = buf[pos++]; + spi_send_command(JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE, 0, cmd, NULL); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - programmer_delay(5); /* SST25VF040B Tbp is max 10us */ + programmer_delay(10); } + + /* Use WRDI to exit AAI mode. */ spi_write_disable(); return 0; }

1 0

[PATCH] SPI fixups
by Carl-Daniel Hailfinger 20 Jun '10

20 Jun '10

Fix message printing for SPI RES on spew level. Use a blacklist instead of a whitelist for 4-byte SPI RDID. Tell users where to report bugs. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_fixups/spi25.c =================================================================== --- flashrom-spi_fixups/spi25.c (Revision 1049) +++ flashrom-spi_fixups/spi25.c (Arbeitskopie) @@ -72,6 +72,7 @@ unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 }; uint32_t readaddr; int ret; + int i; ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr); if (ret == SPI_INVALID_ADDRESS) { @@ -84,7 +85,10 @@ } if (ret) return ret; - msg_cspew("RES returned %02x. ", readarr[0]); + msg_cspew("RES returned"); + for (i = 0; i < bytes; i++) + msg_cspew(" 0x%02x", readarr[i]); + msg_cspew(". "); return 0; } @@ -122,7 +126,9 @@ if (!oddparity(readarr[0])) msg_cdbg("RDID byte 0 parity violation. "); - /* Check if this is a continuation vendor ID */ + /* Check if this is a continuation vendor ID. + * FIXME: Handle continuation device IDs. + */ if (readarr[0] == 0x7f) { if (!oddparity(readarr[1])) msg_cdbg("RDID byte 1 parity violation. "); @@ -166,35 +172,23 @@ return probe_spi_rdid_generic(flash, 3); } -/* support 4 bytes flash ID */ int probe_spi_rdid4(struct flashchip *flash) { - /* only some SPI chipsets support 4 bytes commands */ + /* Some SPI controllers do not support commands with writecnt=1 and + * readcnt=4. + */ switch (spi_controller) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_ICH9: - case SPI_CONTROLLER_VIA: - case SPI_CONTROLLER_SB600: + case SPI_CONTROLLER_IT87XX: case SPI_CONTROLLER_WBSIO: + msg_cinfo("4 byte RDID not supported on this SPI controller\n"); + return 0; + break; #endif #endif -#if CONFIG_FT2232_SPI == 1 - case SPI_CONTROLLER_FT2232: -#endif -#if CONFIG_DUMMY == 1 - case SPI_CONTROLLER_DUMMY: -#endif -#if CONFIG_BUSPIRATE_SPI == 1 - case SPI_CONTROLLER_BUSPIRATE: -#endif -#if CONFIG_DEDIPROG == 1 - case SPI_CONTROLLER_DEDIPROG: -#endif - return probe_spi_rdid_generic(flash, 4); default: - msg_cinfo("4b ID not supported on this SPI controller\n"); + return probe_spi_rdid_generic(flash, 4); } return 0; Index: flashrom-spi_fixups/spi.c =================================================================== --- flashrom-spi_fixups/spi.c (Revision 1049) +++ flashrom-spi_fixups/spi.c (Arbeitskopie) @@ -132,7 +132,8 @@ { if (!spi_programmer[spi_controller].command) { msg_perr("%s called, but SPI is unsupported on this " - "hardware. Please report a bug.\n", __func__); + "hardware. Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); return 1; } @@ -144,7 +145,8 @@ { if (!spi_programmer[spi_controller].multicommand) { msg_perr("%s called, but SPI is unsupported on this " - "hardware. Please report a bug.\n", __func__); + "hardware. Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); return 1; } @@ -183,8 +185,9 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) { if (!spi_programmer[spi_controller].read) { - msg_perr("%s called, but SPI read is unsupported on this" - " hardware. Please report a bug.\n", __func__); + msg_perr("%s called, but SPI read is unsupported on this " + "hardware. Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); return 1; } @@ -198,8 +201,9 @@ int spi_chip_write_256(struct flashchip *flash, uint8_t *buf) { if (!spi_programmer[spi_controller].write_256) { - msg_perr("%s called, but SPI page write is unsupported " - " on this hardware. Please report a bug.\n", __func__); + msg_perr("%s called, but SPI page write is unsupported on this " + "hardware. Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); return 1; } -- http://www.hailfinger.org/

2 2

[commit] r1051 - trunk
by repository service 20 Jun '10

20 Jun '10

Author: hailfinger Date: Sun Jun 20 12:39:33 2010 New Revision: 1051 URL: http://flashrom.org/trac/coreboot/changeset/1051 Log: Fix message printing for SPI RES on spew level. Use a blacklist instead of a whitelist for 4-byte SPI RDID. Tell users where to report bugs. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/spi.c trunk/spi25.c Modified: trunk/spi.c ============================================================================== --- trunk/spi.c Sun Jun 20 00:06:35 2010 (r1050) +++ trunk/spi.c Sun Jun 20 12:39:33 2010 (r1051) @@ -132,7 +132,8 @@ { if (!spi_programmer[spi_controller].command) { msg_perr("%s called, but SPI is unsupported on this " - "hardware. Please report a bug.\n", __func__); + "hardware. Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); return 1; } @@ -144,7 +145,8 @@ { if (!spi_programmer[spi_controller].multicommand) { msg_perr("%s called, but SPI is unsupported on this " - "hardware. Please report a bug.\n", __func__); + "hardware. Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); return 1; } @@ -183,8 +185,9 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) { if (!spi_programmer[spi_controller].read) { - msg_perr("%s called, but SPI read is unsupported on this" - " hardware. Please report a bug.\n", __func__); + msg_perr("%s called, but SPI read is unsupported on this " + "hardware. Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); return 1; } @@ -198,8 +201,9 @@ int spi_chip_write_256(struct flashchip *flash, uint8_t *buf) { if (!spi_programmer[spi_controller].write_256) { - msg_perr("%s called, but SPI page write is unsupported " - " on this hardware. Please report a bug.\n", __func__); + msg_perr("%s called, but SPI page write is unsupported on this " + "hardware. Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); return 1; } Modified: trunk/spi25.c ============================================================================== --- trunk/spi25.c Sun Jun 20 00:06:35 2010 (r1050) +++ trunk/spi25.c Sun Jun 20 12:39:33 2010 (r1051) @@ -72,6 +72,7 @@ unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 }; uint32_t readaddr; int ret; + int i; ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr); if (ret == SPI_INVALID_ADDRESS) { @@ -84,7 +85,10 @@ } if (ret) return ret; - msg_cspew("RES returned %02x. ", readarr[0]); + msg_cspew("RES returned"); + for (i = 0; i < bytes; i++) + msg_cspew(" 0x%02x", readarr[i]); + msg_cspew(". "); return 0; } @@ -122,7 +126,9 @@ if (!oddparity(readarr[0])) msg_cdbg("RDID byte 0 parity violation. "); - /* Check if this is a continuation vendor ID */ + /* Check if this is a continuation vendor ID. + * FIXME: Handle continuation device IDs. + */ if (readarr[0] == 0x7f) { if (!oddparity(readarr[1])) msg_cdbg("RDID byte 1 parity violation. "); @@ -166,35 +172,23 @@ return probe_spi_rdid_generic(flash, 3); } -/* support 4 bytes flash ID */ int probe_spi_rdid4(struct flashchip *flash) { - /* only some SPI chipsets support 4 bytes commands */ + /* Some SPI controllers do not support commands with writecnt=1 and + * readcnt=4. + */ switch (spi_controller) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_ICH9: - case SPI_CONTROLLER_VIA: - case SPI_CONTROLLER_SB600: + case SPI_CONTROLLER_IT87XX: case SPI_CONTROLLER_WBSIO: + msg_cinfo("4 byte RDID not supported on this SPI controller\n"); + return 0; + break; #endif #endif -#if CONFIG_FT2232_SPI == 1 - case SPI_CONTROLLER_FT2232: -#endif -#if CONFIG_DUMMY == 1 - case SPI_CONTROLLER_DUMMY: -#endif -#if CONFIG_BUSPIRATE_SPI == 1 - case SPI_CONTROLLER_BUSPIRATE: -#endif -#if CONFIG_DEDIPROG == 1 - case SPI_CONTROLLER_DEDIPROG: -#endif - return probe_spi_rdid_generic(flash, 4); default: - msg_cinfo("4b ID not supported on this SPI controller\n"); + return probe_spi_rdid_generic(flash, 4); } return 0;

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[commit] r1050 - trunk
by repository service 20 Jun '10

20 Jun '10

Author: mkarcher Date: Sun Jun 20 00:06:35 2010 New Revision: 1050 URL: http://flashrom.org/trac/coreboot/changeset/1050 Log: Add EMST F25L008A SPI chip Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Thu Jun 17 02:01:56 2010 (r1049) +++ trunk/flashchips.c Sun Jun 20 00:06:35 2010 (r1050) @@ -1366,6 +1366,37 @@ }, { + .vendor = "EMST", + .name = "F25L008A", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = EMST_ID, + .model_id = EMST_F25L008A, + .total_size = 1024, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .write = spi_aai_write, + .read = read_memmapped, + }, + + { .vendor = "Eon", .name = "EN25B05", .bustype = CHIP_BUSTYPE_SPI, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Thu Jun 17 02:01:56 2010 (r1049) +++ trunk/flashchips.h Sun Jun 20 00:06:35 2010 (r1050) @@ -151,6 +151,7 @@ #define CATALYST_ID 0x31 /* Catalyst */ #define EMST_ID 0x8C /* EMST / EFST Elite Flash Storage */ +#define EMST_F25L008A 0x2014 #define EMST_F49B002UA 0x00 /*

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Re: [flashrom] [PATCH] Add EMST E25L008A SPI chip
by Sean Nelson 20 Jun '10

20 Jun '10

On 6/12/10 10:49 AM, Michael Karcher wrote: > Sorry for the late replay, somehow I forgot to send the patch for your > board. > > Signed-off-by: Michael Karcher<flashrom(a)mkarcher.dialup.fu-berlin.de> > Acked-by: Sean Nelson <audiohacked(a)gmail.com>

2 1

Abit IP35 board enable not working
by Gunter Keilholz 20 Jun '10

20 Jun '10

hi, although my board is supposed to be supported by flashrom i couldn't update my bios. i have attached several logfiles. motherboard: Abit IP35 latest BIOS download link: http://file.abit.com.tw/pub/download/bios/ip35//m630a18.zip gunter

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Re: [flashrom] Flash erasing failed mid way on Atmel AT25DF321 flash chip
by Carl-Daniel Hailfinger 19 Jun '10

19 Jun '10

Hi Ramakrishna, On 18.06.2010 17:28, Ramakrishna.Koduri(a)emerson.com wrote: > On June 18, 2010 5:27 AM, Carl-Daniel Hailfinger wrote: >> is this a production system you have to recover now, or can you reflash >> externally if something goes wrong? > > Yes. It is the production that I need to recover. This failure wiped > out the existing BIOS on the flash. > I am exploring to see any other option other than JTAG interface for > bringing back. > Do you have a SPI connector on the board? If yes, you can use flashrom to attach a Bus Pirate or a SPIPGM parallel port programmer or a FT2232H USB-serial controller to recover. > Flashrom worked many times for this. I don't know somehow this got > failed in this attempt. > > >> On 17.06.2010 16:26, Ramakrishna.Koduri(a)emerson.com wrote: >>> I have tried upgrading BIOS image using flashrom v0.9.2-r1001. >>> Surprisingly it failed in this attempt. >>> >>> I did many times upgrade of BIOS using flashrom utility of above said >>> version. >>> Earlier it was done by internal programmer with erase function-2. >>> >>> [root@localhost images]# flashrom -V -w atca-7360-cpu-v1.1.1.rom >>> flashrom v0.9.2-r1001 on Linux 2.6.18-194.el5xen (x86_64), built with The failing flashrom run happened on a Xen kernel. >>> libpci 2.2.3, GCC 4.1.2 20080704 (Red Hat 4.1.2-48) >>> Initializing internal programmer >>> No coreboot table found. >>> DMI string system-manufacturer: "Emerson" >>> DMI string system-product-name: "PCA,ATCA-7360/R1.0/6E " >>> DMI string system-version: "R1.0 " >>> DMI string baseboard-manufacturer: "Emerson" >>> DMI string baseboard-product-name: "ATCA-7360/7365" >>> DMI string baseboard-version: "0106865F01A " >>> DMI string chassis-type: "" >>> Found chipset "Intel ICH10R", enabling flash write... >>> Maximum FWH chip size: 0x380000 bytes >>> BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is >>> 0x9 >>> Root Complex Register Block address = 0xfed1c000 GCS = 0x460: BIOS >>> Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 >>> (SPI) >>> Top Swap : not enabled >>> SPIBAR = 0xfed1c000 + 0x3800 >>> 0x04: 0x6008 (HSFS) >>> FLOCKDN 0, FDV 1, FDOPSS 1, SCIP 0, BERASE 1, AEL 0, FCERR 0, FDONE 0 >>> 0x50: 0x00001b1b (FRAP) >>> BMWAG 0, BMRAG 0, BRWA 27, BRRA 27 >>> 0x54: 0x00010000 (FREG0) >>> 0x58: 0x03ff0080 (FREG1) >>> 0x5C: 0x00001fff (FREG2) >>> 0x60: 0x00030002 (FREG3) >>> 0x64: 0x007f0004 (FREG4) >>> 0x74: 0x00000000 (PR0) >>> 0x78: 0x00000000 (PR1) >>> 0x7C: 0x00000000 (PR2) >>> 0x80: 0x00000000 (PR3) >>> 0x84: 0x00000000 (PR4) >>> 0x90: 0x007f100c (SSFS, SSFC) >>> 0x94: 0x0006 (PREOP) >>> 0x96: 0x463b (OPTYPE) >>> 0x98: 0x05d80302 (OPMENU) >>> 0x9C: 0xc79f0190 (OPMENU+4) >>> 0xA0: 0x00000000 (BBAR) >>> 0xB0: 0x00004000 (FDOC) >>> Programming OPCODES... >>> program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 done >>> SPI Read Configuration: prefetching enabled, caching enabled, OK. >>> This chipset supports the following protocols: FWH,SPI. >>> Calibrating delay loop... 1062M loops per second, 10 myus = 12 us, 100 >>> myus = 101 us, 1000 myus = 999 us, 10000 myus = 10005 us, OK. >>> Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 >>> 0x1f, >>> id2 0x4700 >>> Chip status register is 10 >>> Found chip "Atmel AT25DF321" (4096 KB, SPI) at physical address >>> 0xffc00000. >>> Flash image seems to be a legacy BIOS. Disabling checks. >>> Writing flash chip... Some block protection in effect, disabling >>> Erasing flash before programming... Erasing flash chip... Looking at >>> blockwise erase function 0... trying... 0x000000-0x000fff, >>> ich_spi_send_multicommand: FIXME: Add on-the-fly reprogramming of the >>> chipset opcode list. >>> Invalid OPCODE 0x20 >>> spi_block_erase_20 failed during command execution at address 0x0 >>> >>> Looking at blockwise erase function 1... trying... 0x000000-0x007fff, >>> ich_spi_send_multicommand: FIXME: Add on-the-fly reprogramming of the >>> chipset opcode list. >>> Invalid OPCODE 0x52 >>> spi_block_erase_52 failed during command execution at address 0x0 >>> >>> Looking at blockwise erase function 2... trying... 0x000000-0x00ffff, >>> 0x010000-0x01ffff, 0x020000-0x02ffff, 0x030000-0x03ffff, >>> 0x040000-0x04ffff, 0x050000-0x05ffff, 0x060000-0x06ffff, >>> 0x070000-0x07ffff, 0x080000-0x08ffff, 0x090000-0x09ffff, >>> 0x0a0000-0x0affff, ERASE FAILED at 0x000a0800! Expected=0xff, >>> Read=0x1f,Transaction error! >>> run OPCODE 0x03 failed >>> Transaction error! >>> [...] >>> run OPCODE 0x03 failed >>> Transaction error! >> Ah yes. This means your current BIOS version somehow blocks reading of >> some regions. You could try flashrom r1016 or later which has improved >> region protection handling. > > I am surprised to see why it should block some regions. > May be once the board is UP, I shall give a try using flashrom r1016 > version. > > >>> failed byte count from 0x000a0000-0x000affff: 0x1a ERASE FAILED! >>> >>> Looking at blockwise erase function 3... trying... 0x000000-0x3fffff, >>> Some block protection in effect, disabling >>> ich_spi_send_multicommand: FIXME: Add on-the-fly reprogramming of the >>> chipset opcode list. >>> Invalid OPCODE 0x60 >>> spi_chip_erase_60 failed during command execution >>> >>> Looking at blockwise erase function 4... trying... 0x000000-0x3fffff, >>> Some block protection in effect, disabling >> It would be interesting to check if reading the complete chip works. >> I think it probably won't work. Please report back with the verbose >> results of a pure read test. > > The current state of the system is not usable any more due to > boardreset immediately after the flashrom failed. > It didn't give me any chance to repair system back. > Oh, that is very unfortunate. The board should not have resetted. > I have the traces of previously successful write operation. Please > find the same here. > > [root@localhost flashrom-0.9.2]# ./flashrom -V -l layout -w > atca7360-bios.img -i part_2000_4000.log > What does "-i part_2000_4000.log" do? > flashrom v0.9.2-r1001 on Linux 2.6.18-194.el5PAE (i686), built with > libpci 2.2.3, GCC 4.1.2 20080704 (Red Hat 4.1.2-48) > The working flashrom run happened on a PAE kernel. > flashrom is free software, get the source code at > http://www.flashrom.org > romlayout 00002000 - 00003fff named > /mnt/root/ramki/flashrom-0.9.2/part_2000_4000.log > Looking for "part_2000_4000.log"... not found. > It seems you told flashrom that part_2000_4000.log is the image name in the layout file. Is that intentional? > Initializing internal programmer > No coreboot table found. > DMI string system-manufacturer: "Emerson" > DMI string system-product-name: "PCA,ATCA-7360/R1.0/6E > " > DMI string system-version: "R1.0 " > DMI string baseboard-manufacturer: "Emerson" > DMI string baseboard-product-name: "ATCA-7360/7365" > DMI string baseboard-version: "0106865F01A " > DMI string chassis-type: "" > Found chipset "Intel ICH10R", enabling flash write... > Maximum FWH chip size: 0x380000 bytes > BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x9 > Root Complex Register Block address = 0xfed1c000 > GCS = 0x460: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 > (SPI) > Top Swap : not enabled > SPIBAR = 0xfed1c000 + 0x3800 > 0x04: 0x6008 (HSFS) > FLOCKDN 0, FDV 1, FDOPSS 1, SCIP 0, BERASE 1, AEL 0, FCERR 0, FDONE 0 > 0x50: 0x00001b1b (FRAP) > BMWAG 0, BMRAG 0, BRWA 27, BRRA 27 > 0x54: 0x00010000 (FREG0) > 0x58: 0x03ff0080 (FREG1) > 0x5C: 0x00001fff (FREG2) > 0x60: 0x00030002 (FREG3) > 0x64: 0x007f0004 (FREG4) > 0x74: 0x00000000 (PR0) > 0x78: 0x00000000 (PR1) > 0x7C: 0x00000000 (PR2) > 0x80: 0x00000000 (PR3) > 0x84: 0x00000000 (PR4) > 0x90: 0x007f100c (SSFS, SSFC) > 0x94: 0x0006 (PREOP) > 0x96: 0x463b (OPTYPE) > 0x98: 0x05d80302 (OPMENU) > 0x9C: 0xc79f0190 (OPMENU+4) > 0xA0: 0x00000000 (BBAR) > 0xB0: 0x00004000 (FDOC) > Programming OPCODES... > program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 > done > SPI Read Configuration: prefetching enabled, caching enabled, OK. > This chipset supports the following protocols: FWH,SPI. > Calibrating delay loop... 1091M loops per second, 10 myus = 10 us, 100 > myus = 103 us, 1000 myus = 1029 us, 10000 myus = 10073 us, OK. > Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0x1f, > id2 0x4700 > Chip status register is 10 > Found chip "Atmel AT25DF321" (4096 KB, SPI) at physical address > 0xffc00000. > Flash image seems to be a legacy BIOS. Disabling checks. > Writing flash chip... Some block protection in effect, disabling > Erasing flash before programming... Erasing flash chip... Looking at > blockwise erase function 0... trying... 0x000000-0x000fff, > ich_spi_send_multicommand: FIXME: Add on-the-fly reprogramming of the > chipset opcode list. > Invalid OPCODE 0x20 > spi_block_erase_20 failed during command execution at address 0x0 > > Looking at blockwise erase function 1... trying... 0x000000-0x007fff, > ich_spi_send_multicommand: FIXME: Add on-the-fly reprogramming of the > chipset opcode list. > Invalid OPCODE 0x52 > spi_block_erase_52 failed during command execution at address 0x0 > > Looking at blockwise erase function 2... trying... 0x000000-0x00ffff, > 0x010000-0x01ffff, 0x020000-0x02ffff, 0x030000-0x03ffff, > 0x040000-0x04ffff, 0x050000-0x05ffff, 0x060000-0x06ffff, > 0x070000-0x07ffff, 0x080000-0x08ffff, 0x090000-0x09ffff, > 0x0a0000-0x0affff, 0x0b0000-0x0bffff, 0x0c0000-0x0cffff, > 0x0d0000-0x0dffff, 0x0e0000-0x0effff, 0x0f0000-0x0fffff, > 0x100000-0x10ffff, 0x110000-0x11ffff, 0x120000-0x12ffff, > 0x130000-0x13ffff, 0x140000-0x14ffff, 0x150000-0x15ffff, > 0x160000-0x16ffff, 0x170000-0x17ffff, 0x180000-0x18ffff, > 0x190000-0x19ffff, 0x1a0000-0x1affff, 0x1b0000-0x1bffff, > 0x1c0000-0x1cffff, 0x1d0000-0x1dffff, 0x1e0000-0x1effff, > 0x1f0000-0x1fffff, 0x200000-0x20ffff, 0x210000-0x21ffff, > 0x220000-0x22ffff, 0x230000-0x23ffff, 0x240000-0x24ffff, > 0x250000-0x25ffff, 0x260000-0x26ffff, 0x270000-0x27ffff, > 0x280000-0x28ffff, 0x290000-0x29ffff, 0x2a0000-0x2affff, > 0x2b0000-0x2bffff, 0x2c0000-0x2cffff, 0x2d0000-0x2dffff, > 0x2e0000-0x2effff, 0x2f0000-0x2fffff, 0x300000-0x30ffff, > 0x310000-0x31ffff, 0x320000-0x32ffff, 0x330000-0x33ffff, > 0x340000-0x34ffff, 0x350000-0x35ffff, 0x360000-0x36ffff, > 0x370000-0x37ffff, 0x380000-0x38ffff, 0x390000-0x39ffff, > 0x3a0000-0x3affff, 0x3b0000-0x3bffff, 0x3c0000-0x3cffff, > 0x3d0000-0x3dffff, 0x3e0000-0x3effff, 0x3f0000-0x3fffff, > SUCCESS. > done. > Programming page: > > COMPLETE. > Verifying flash... VERIFIED. > I think that the crash was related to the Xen kernel. Regards, Carl-Daniel -- http://www.hailfinger.org/

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New BIOS chip
by Wolfgang Schnitker 19 Jun '10

19 Jun '10

Hi there, as requested, please find attached file for output of flashrom -V for my computer. Regards Wolfgang Schnitker

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Re: [flashrom] Flash erasing failed mid way on Atmel AT25DF321 flash chip
by Carl-Daniel Hailfinger 18 Jun '10

18 Jun '10

Hi Ramakrishna, is this a production system you have to recover now, or can you reflash externally if something goes wrong? On 17.06.2010 16:26, Ramakrishna.Koduri(a)emerson.com wrote: > I have tried upgrading BIOS image using flashrom v0.9.2-r1001. > Surprisingly it failed in this attempt. > > I did many times upgrade of BIOS using flashrom utility of above said > version. > Earlier it was done by internal programmer with erase function-2. > > [root@localhost images]# flashrom -V -w atca-7360-cpu-v1.1.1.rom > flashrom v0.9.2-r1001 on Linux 2.6.18-194.el5xen (x86_64), built with > libpci 2.2.3, GCC 4.1.2 20080704 (Red Hat 4.1.2-48) > Initializing internal programmer > No coreboot table found. > DMI string system-manufacturer: "Emerson" > DMI string system-product-name: "PCA,ATCA-7360/R1.0/6E > " > DMI string system-version: "R1.0 " > DMI string baseboard-manufacturer: "Emerson" > DMI string baseboard-product-name: "ATCA-7360/7365" > DMI string baseboard-version: "0106865F01A " > DMI string chassis-type: "" > Found chipset "Intel ICH10R", enabling flash write... > Maximum FWH chip size: 0x380000 bytes > BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x9 > > Root Complex Register Block address = 0xfed1c000 > GCS = 0x460: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 > (SPI) > Top Swap : not enabled > SPIBAR = 0xfed1c000 + 0x3800 > 0x04: 0x6008 (HSFS) > FLOCKDN 0, FDV 1, FDOPSS 1, SCIP 0, BERASE 1, AEL 0, FCERR 0, FDONE 0 > 0x50: 0x00001b1b (FRAP) > BMWAG 0, BMRAG 0, BRWA 27, BRRA 27 > 0x54: 0x00010000 (FREG0) > 0x58: 0x03ff0080 (FREG1) > 0x5C: 0x00001fff (FREG2) > 0x60: 0x00030002 (FREG3) > 0x64: 0x007f0004 (FREG4) > 0x74: 0x00000000 (PR0) > 0x78: 0x00000000 (PR1) > 0x7C: 0x00000000 (PR2) > 0x80: 0x00000000 (PR3) > 0x84: 0x00000000 (PR4) > 0x90: 0x007f100c (SSFS, SSFC) > 0x94: 0x0006 (PREOP) > 0x96: 0x463b (OPTYPE) > 0x98: 0x05d80302 (OPMENU) > 0x9C: 0xc79f0190 (OPMENU+4) > 0xA0: 0x00000000 (BBAR) > 0xB0: 0x00004000 (FDOC) > Programming OPCODES... > program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 > done > SPI Read Configuration: prefetching enabled, caching enabled, OK. > This chipset supports the following protocols: FWH,SPI. > Calibrating delay loop... 1062M loops per second, 10 myus = 12 us, 100 > myus = 101 us, 1000 myus = 999 us, 10000 myus = 10005 us, OK. > Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0x1f, > id2 0x4700 > Chip status register is 10 > Found chip "Atmel AT25DF321" (4096 KB, SPI) at physical address > 0xffc00000. > Flash image seems to be a legacy BIOS. Disabling checks. > Writing flash chip... Some block protection in effect, disabling > Erasing flash before programming... Erasing flash chip... Looking at > blockwise erase function 0... trying... 0x000000-0x000fff, > ich_spi_send_multicommand: FIXME: Add on-the-fly reprogramming of the > chipset opcode list. > Invalid OPCODE 0x20 > spi_block_erase_20 failed during command execution at address 0x0 > > Looking at blockwise erase function 1... trying... 0x000000-0x007fff, > ich_spi_send_multicommand: FIXME: Add on-the-fly reprogramming of the > chipset opcode list. > Invalid OPCODE 0x52 > spi_block_erase_52 failed during command execution at address 0x0 > > Looking at blockwise erase function 2... trying... 0x000000-0x00ffff, > 0x010000-0x01ffff, 0x020000-0x02ffff, 0x030000-0x03ffff, > 0x040000-0x04ffff, 0x050000-0x05ffff, 0x060000-0x06ffff, > 0x070000-0x07ffff, 0x080000-0x08ffff, 0x090000-0x09ffff, > 0x0a0000-0x0affff, ERASE FAILED at 0x000a0800! Expected=0xff, > Read=0x1f,Transaction error! > run OPCODE 0x03 failed > Transaction error! > [...] > run OPCODE 0x03 failed > Transaction error! > Ah yes. This means your current BIOS version somehow blocks reading of some regions. You could try flashrom r1016 or later which has improved region protection handling. > failed byte count from 0x000a0000-0x000affff: 0x1a > ERASE FAILED! > > Looking at blockwise erase function 3... trying... 0x000000-0x3fffff, > Some block protection in effect, disabling > ich_spi_send_multicommand: FIXME: Add on-the-fly reprogramming of the > chipset opcode list. > Invalid OPCODE 0x60 > spi_chip_erase_60 failed during command execution > > Looking at blockwise erase function 4... trying... 0x000000-0x3fffff, > Some block protection in effect, disabling > It would be interesting to check if reading the complete chip works. I think it probably won't work. Please report back with the verbose results of a pure read test. Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

SPI Flashing via Bus-Pirate to DFI T3H6
by Daniel Flinkmann 18 Jun '10

18 Jun '10

Hi, I am trying to use the current flashrom together with a Bus-Pirate to re-flash my DFI T3H6 BIOS as it was broken by the official bios update. I am using a second computer running Linux and connected the Bus-Pirate to the SPI-Flash Header (DFI call it Bios Download). I can only offer the first part, as I had to stop the flashing and will restart it tonight. The erasing of the 8Mbit Flash needed around 60-70 minutes. After that I can't see any progress, as -V is pretty silent when writing the flash and -VV dumps far too much to have an overview. I would like to have a block-wise info when writing or verifying the flash, as it will be done when erasing the flash. It would help to have a feeling about the aprox. time it needs and if the flashing is still ongoing. What is you typical experience with erasing and writing a flash. How many time longer do the writing of the flash need when comparing it with the erasing ? Kind regards, Daniel Flashrom-Log (had to stop flashing, as I had to leave the home to get to work). # flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -w JX58D422.BIN -V flashrom v0.9.2-r1048 on Linux 2.6.32-22-server (x86_64), built with libpci 3.0.0, GCC 4.4.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 299M loops per second, 10 myus = 11 us, 100 myus = 101 us, 1000 myus = 999 us, 10000 myus = 10113 us, 4 myus = 5 us, OK. Initializing buspirate_spi programmer SPI speed is 8MHz Raw bitbang mode version 1 Raw SPI mode version 1 Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for ASD AE49F2008, 256 KB: skipped. Probing for Atmel AT25DF021, 256 KB: RDID byte 0 parity violation. probe_spi_rdid_generic: id1 0x00, id2 0x00 Probing for Atmel AT25DF041A, 512 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Atmel AT25DF081, 1024 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Atmel AT25DF161, 2048 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Atmel AT25DF321A, 4096 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Atmel AT25DF641, 8192 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Atmel AT25F512B, 64 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Atmel AT25FS010, 128 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Atmel AT25FS040, 512 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Atmel AT26DF041, 512 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Atmel AT26DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Atmel AT26DF161, 2048 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Atmel AT26DF161A, 2048 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Atmel AT26F004, 512 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Atmel AT45DB011D, 128 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Atmel AT45DB021D, 256 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Atmel AT45DB041D, 512 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Atmel AT45DB081D, 1024 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Atmel AT45DB161D, 2048 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Atmel AT45DB321C, 4224 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Atmel AT45DB321D, 4096 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Atmel AT45DB642D, 8192 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F020, 256 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for AMIC A25L40PT, 512 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for AMIC A25L40PU, 512 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: skipped. Probing for EMST F49B002UA, 256 KB: skipped. Probing for Eon EN25B05, 64 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Eon EN25B05T, 64 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Eon EN25B10, 128 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Eon EN25B10T, 128 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Eon EN25B20, 256 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Eon EN25B20T, 256 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Eon EN25B40, 512 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Eon EN25B40T, 512 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Eon EN25B80, 1024 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Eon EN25B80T, 1024 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Eon EN25B16, 2048 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Eon EN25B16T, 2048 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Eon EN25B32, 4096 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Eon EN25B32T, 4096 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Eon EN25B64, 8192 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Eon EN25B64T, 8192 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Eon EN25D16, 2048 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Eon EN25F05, 64 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Eon EN25F10, 128 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Eon EN25F20, 256 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Eon EN25F40, 512 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Eon EN25F80, 1024 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Eon EN25F16, 2048 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Eon EN25F32, 4096 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Eon EN29F010, 128 KB: skipped. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Intel 28F001BX-B, 128 KB: skipped. Probing for Intel 28F001BX-T, 128 KB: skipped. Probing for Intel 28F004S5, 512 KB: skipped. Probing for Intel 28F004BV/BE-B, 512 KB: skipped. Probing for Intel 28F004BV/BE-T, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-B, 512 KB: skipped. Probing for Intel 28F400BV/CV/CE-T, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: skipped. Probing for Intel 82802AC, 1024 KB: skipped. Probing for Macronix MX25L512, 64 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Macronix MX25L1005, 128 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Macronix MX25L2005, 256 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Macronix MX25L4005, 512 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Macronix MX25L1635D, 2048 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Macronix MX25L3205, 4096 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Macronix MX25L3235D, 4096 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Macronix MX25L6405, 8192 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Macronix MX25L12805, 16384 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for Numonyx M25PE10, 128 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Numonyx M25PE20, 256 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Numonyx M25PE40, 512 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Numonyx M25PE80, 1024 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Numonyx M25PE16, 2048 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for PMC Pm25LV010, 128 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for PMC Pm25LV016B, 2048 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for PMC Pm25LV020, 256 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for PMC Pm25LV040, 512 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for PMC Pm25LV080B, 1024 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for PMC Pm25LV512, 64 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: skipped. Probing for PMC Pm49FL004, 512 KB: skipped. Probing for Sanyo LF25FW203A, 2048 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Sharp LHF00L04, 1024 KB: skipped. Probing for Spansion S25FL008A, 1024 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Spansion S25FL016A, 2048 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for SST SST25VF016B, 2048 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for SST SST25VF032B, 4096 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for SST SST25VF040.REMS, 512 KB: probe_spi_rems: id1 0xbf, id2 0x8e Probing for SST SST25VF040B, 512 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for SST SST25LF040A.RES, 512 KB: probe_spi_res2: id1 0xbf, id2 0x8e Probing for SST SST25VF040B.REMS, 512 KB: probe_spi_rems: id1 0xbf, id2 0x8e Probing for SST SST25VF080B, 1024 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Chip status register is 1c Chip status register: Block Protect Write Disable (BPL) is not set Chip status register: Auto Address Increment Programming (AAI) is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is set Chip status register: Bit 3 / Block Protect 1 (BP1) is set Chip status register: Bit 2 / Block Protect 0 (BP0) is set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found chip "SST SST25VF080B" (1024 KB, SPI) at physical address 0xfff00000. Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: skipped. Probing for SST SST49LF003A/B, 384 KB: skipped. Probing for SST SST49LF004A/B, 512 KB: skipped. Probing for SST SST49LF004C, 512 KB: skipped. Probing for SST SST49LF008A, 1024 KB: skipped. Probing for SST SST49LF008C, 1024 KB: skipped. Probing for SST SST49LF016C, 2048 KB: skipped. Probing for SST SST49LF020, 256 KB: skipped. Probing for SST SST49LF020A, 256 KB: skipped. Probing for SST SST49LF040, 512 KB: skipped. Probing for SST SST49LF040B, 512 KB: skipped. Probing for SST SST49LF080A, 1024 KB: skipped. Probing for SST SST49LF160C, 2048 KB: skipped. Probing for ST M25P05-A, 64 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for ST M25P05.RES, 64 KB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for ST M25P10.RES, 128 KB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for ST M25P40, 512 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for ST M25P40-old, 512 KB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for ST M25P16, 2048 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for ST M25P32, 4096 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for ST M25P64, 8192 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for ST M25P128, 16384 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: skipped. Probing for ST M50FLW040B, 512 KB: skipped. Probing for ST M50FLW080A, 1024 KB: skipped. Probing for ST M50FLW080B, 1024 KB: skipped. Probing for ST M50FW002, 256 KB: skipped. Probing for ST M50FW016, 2048 KB: skipped. Probing for ST M50FW040, 512 KB: skipped. Probing for ST M50FW080, 1024 KB: skipped. Probing for ST M50LPW116, 2048 KB: skipped. Probing for SyncMOS S29C31004T, 512 KB: skipped. Probing for SyncMOS S29C51001T, 128 KB: skipped. Probing for SyncMOS S29C51002T, 256 KB: skipped. Probing for SyncMOS S29C51004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Winbond W25Q16, 2048 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Winbond W25Q32, 4096 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Winbond W25x10, 128 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Winbond W25x20, 256 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Winbond W25x40, 512 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Winbond W25x80, 1024 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Winbond W25x16, 2048 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Winbond W25x32, 4096 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Winbond W25x64, 8192 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Winbond W29C011, 128 KB: skipped. Probing for Winbond W29C020C, 256 KB: skipped. Probing for Winbond W29C040P, 512 KB: skipped. Probing for Winbond W29EE011, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: skipped. Probing for Winbond W39V040B, 512 KB: skipped. Probing for Winbond W39V040C, 512 KB: skipped. Probing for Winbond W39V040FA, 512 KB: skipped. Probing for Winbond W39V080A, 1024 KB: skipped. Probing for Winbond W49F002U, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: skipped. Probing for Winbond W49V002FA, 256 KB: skipped. Probing for Winbond W39V080FA, 1024 KB: skipped. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Probing for Atmel unknown Atmel SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for EON unknown EON SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Macronix unknown Macronix SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for PMC unknown PMC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for SST unknown SST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for ST unknown ST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Sanyo unknown Sanyo SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Generic unknown SPI chip (RDID), 0 KB: probe_spi_rdid_generic: id1 0xbf, id2 0x258e Probing for Generic unknown SPI chip (REMS), 0 KB: probe_spi_rems: id1 0xbf, id2 0x8e === This flash part has status UNTESTED for operations: ERASE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Thanks for your help! === Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Some block protection in effect, disabling Erasing flash before programming... Erasing flash chip... Looking at blockwise erase function 0... trying... 0x000000-0x000fff, 0x001000-0x001fff, 0x002000-0x002fff, 0x003000-0x003fff, 0x004000-0x004fff, 0x005000-0x005fff, 0x006000-0x006fff, 0x007000-0x007fff, 0x008000-0x008fff, 0x009000-0x009fff, 0x00a000-0x00afff, 0x00b000-0x00bfff, 0x00c000-0x00cfff, 0x00d000-0x00dfff, 0x00e000-0x00efff, 0x00f000-0x00ffff, 0x010000-0x010fff, 0x011000-0x011fff, 0x012000-0x012fff, 0x013000-0x013fff, 0x014000-0x014fff, 0x015000-0x015fff, 0x016000-0x016fff, 0x017000-0x017fff, 0x018000-0x018fff, 0x019000-0x019fff, 0x01a000-0x01afff, 0x01b000-0x01bfff, 0x01c000-0x01cfff, 0x01d000-0x01dfff, 0x01e000-0x01efff, 0x01f000-0x01ffff, 0x020000-0x020fff, 0x021000-0x021fff, 0x022000-0x022fff, 0x023000-0x023fff, 0x024000-0x024fff, 0x025000-0x025fff, 0x026000-0x026fff, 0x027000-0x027fff, 0x028000-0x028fff, 0x029000-0x029fff, 0x02a000-0x02afff, 0x02b000-0x02bfff, 0x02c000-0x02cfff, 0x02d000-0x02dfff, 0x02e000-0x02efff, 0x02f000-0x02ffff, 0x030000-0x030fff, 0x031000-0x031fff, 0x032000-0x032fff, 0x033000-0x033fff, 0x034000-0x034fff, 0x035000-0x035fff, 0x036000-0x036fff, 0x037000-0x037fff, 0x038000-0x038fff, 0x039000-0x039fff, 0x03a000-0x03afff, 0x03b000-0x03bfff, 0x03c000-0x03cfff, 0x03d000-0x03dfff, 0x03e000-0x03efff, 0x03f000-0x03ffff, 0x040000-0x040fff, 0x041000-0x041fff, 0x042000-0x042fff, 0x043000-0x043fff, 0x044000-0x044fff, 0x045000-0x045fff, 0x046000-0x046fff, 0x047000-0x047fff, 0x048000-0x048fff, 0x049000-0x049fff, 0x04a000-0x04afff, 0x04b000-0x04bfff, 0x04c000-0x04cfff, 0x04d000-0x04dfff, 0x04e000-0x04efff, 0x04f000-0x04ffff, 0x050000-0x050fff, 0x051000-0x051fff, 0x052000-0x052fff, 0x053000-0x053fff, 0x054000-0x054fff, 0x055000-0x055fff, 0x056000-0x056fff, 0x057000-0x057fff, 0x058000-0x058fff, 0x059000-0x059fff, 0x05a000-0x05afff, 0x05b000-0x05bfff, 0x05c000-0x05cfff, 0x05d000-0x05dfff, 0x05e000-0x05efff, 0x05f000-0x05ffff, 0x060000-0x060fff, 0x061000-0x061fff, 0x062000-0x062fff, 0x063000-0x063fff, 0x064000-0x064fff, 0x065000-0x065fff, 0x066000-0x066fff, 0x067000-0x067fff, 0x068000-0x068fff, 0x069000-0x069fff, 0x06a000-0x06afff, 0x06b000-0x06bfff, 0x06c000-0x06cfff, 0x06d000-0x06dfff, 0x06e000-0x06efff, 0x06f000-0x06ffff, 0x070000-0x070fff, 0x071000-0x071fff, 0x072000-0x072fff, 0x073000-0x073fff, 0x074000-0x074fff, 0x075000-0x075fff, 0x076000-0x076fff, 0x077000-0x077fff, 0x078000-0x078fff, 0x079000-0x079fff, 0x07a000-0x07afff, 0x07b000-0x07bfff, 0x07c000-0x07cfff, 0x07d000-0x07dfff, 0x07e000-0x07efff, 0x07f000-0x07ffff, 0x080000-0x080fff, 0x081000-0x081fff, 0x082000-0x082fff, 0x083000-0x083fff, 0x084000-0x084fff, 0x085000-0x085fff, 0x086000-0x086fff, 0x087000-0x087fff, 0x088000-0x088fff, 0x089000-0x089fff, 0x08a000-0x08afff, 0x08b000-0x08bfff, 0x08c000-0x08cfff, 0x08d000-0x08dfff, 0x08e000-0x08efff, 0x08f000-0x08ffff, 0x090000-0x090fff, 0x091000-0x091fff, 0x092000-0x092fff, 0x093000-0x093fff, 0x094000-0x094fff, 0x095000-0x095fff, 0x096000-0x096fff, 0x097000-0x097fff, 0x098000-0x098fff, 0x099000-0x099fff, 0x09a000-0x09afff, 0x09b000-0x09bfff, 0x09c000-0x09cfff, 0x09d000-0x09dfff, 0x09e000-0x09efff, 0x09f000-0x09ffff, 0x0a0000-0x0a0fff, 0x0a1000-0x0a1fff, 0x0a2000-0x0a2fff, 0x0a3000-0x0a3fff, 0x0a4000-0x0a4fff, 0x0a5000-0x0a5fff, 0x0a6000-0x0a6fff, 0x0a7000-0x0a7fff, 0x0a8000-0x0a8fff, 0x0a9000-0x0a9fff, 0x0aa000-0x0aafff, 0x0ab000-0x0abfff, 0x0ac000-0x0acfff, 0x0ad000-0x0adfff, 0x0ae000-0x0aefff, 0x0af000-0x0affff, 0x0b0000-0x0b0fff, 0x0b1000-0x0b1fff, 0x0b2000-0x0b2fff, 0x0b3000-0x0b3fff, 0x0b4000-0x0b4fff, 0x0b5000-0x0b5fff, 0x0b6000-0x0b6fff, 0x0b7000-0x0b7fff, 0x0b8000-0x0b8fff, 0x0b9000-0x0b9fff, 0x0ba000-0x0bafff, 0x0bb000-0x0bbfff, 0x0bc000-0x0bcfff, 0x0bd000-0x0bdfff, 0x0be000-0x0befff, 0x0bf000-0x0bffff, 0x0c0000-0x0c0fff, 0x0c1000-0x0c1fff, 0x0c2000-0x0c2fff, 0x0c3000-0x0c3fff, 0x0c4000-0x0c4fff, 0x0c5000-0x0c5fff, 0x0c6000-0x0c6fff, 0x0c7000-0x0c7fff, 0x0c8000-0x0c8fff, 0x0c9000-0x0c9fff, 0x0ca000-0x0cafff, 0x0cb000-0x0cbfff, 0x0cc000-0x0ccfff, 0x0cd000-0x0cdfff, 0x0ce000-0x0cefff, 0x0cf000-0x0cffff, 0x0d0000-0x0d0fff, 0x0d1000-0x0d1fff, 0x0d2000-0x0d2fff, 0x0d3000-0x0d3fff, 0x0d4000-0x0d4fff, 0x0d5000-0x0d5fff, 0x0d6000-0x0d6fff, 0x0d7000-0x0d7fff, 0x0d8000-0x0d8fff, 0x0d9000-0x0d9fff, 0x0da000-0x0dafff, 0x0db000-0x0dbfff, 0x0dc000-0x0dcfff, 0x0dd000-0x0ddfff, 0x0de000-0x0defff, 0x0df000-0x0dffff, 0x0e0000-0x0e0fff, 0x0e1000-0x0e1fff, 0x0e2000-0x0e2fff, 0x0e3000-0x0e3fff, 0x0e4000-0x0e4fff, 0x0e5000-0x0e5fff, 0x0e6000-0x0e6fff, 0x0e7000-0x0e7fff, 0x0e8000-0x0e8fff, 0x0e9000-0x0e9fff, 0x0ea000-0x0eafff, 0x0eb000-0x0ebfff, 0x0ec000-0x0ecfff, 0x0ed000-0x0edfff, 0x0ee000-0x0eefff, 0x0ef000-0x0effff, 0x0f0000-0x0f0fff, 0x0f1000-0x0f1fff, 0x0f2000-0x0f2fff, 0x0f3000-0x0f3fff, 0x0f4000-0x0f4fff, 0x0f5000-0x0f5fff, 0x0f6000-0x0f6fff, 0x0f7000-0x0f7fff, 0x0f8000-0x0f8fff, 0x0f9000-0x0f9fff, 0x0fa000-0x0fafff, 0x0fb000-0x0fbfff, 0x0fc000-0x0fcfff, 0x0fd000-0x0fdfff, 0x0fe000-0x0fefff, 0x0ff000-0x0fffff, SUCCESS. done. -- -- www.Flinkmann.de : Unix, Mac, Photography -- -- www.Hijet.de : Daihatsu and Japan related stuff --

3 17

Ibex Peak Support
by Adonis Ranin 18 Jun '10

18 Jun '10

Hello, I initially posted my question on the irc channel but was instructed to e-mail instead. My question is, if there is already development in the works, when will there be support for the Intel Ibex Peak chipset? I see that the SPI MMIO registers are pretty much the same as those of other older ICH10's. However, if I add this device (LPC controller PCI ID 0x3b16) to the list in chipset_enable.c, it does not quite work. It is able to probe the SPI flash device (JEDEC-ID, etc.), but when reading (opcode 03h), the SCIP stays busy. Any help/tip/hint is much appreciated. Thanks! Adonis

1 0

Need all the help I can get
by Mike 18 Jun '10

18 Jun '10

Hi I work for laptopuniverse.com and we deal with a lot of optical drives. From time to time we get requests for certain firmwares on drives and sometimes they cannot be downloaded or backed up from original(no manufacturer tools). So one day I saw your website and convinced my Boss to buy DLP-USB1232H to try and extract some firmware. We are trying to extract from macronix chips in the MX25L1605 family. exact part numbers are 25L1605AM2C and 25L1605DM2I. There are other for which compatibility would be nice but I was wondering if you could point me in the right direction for how to readd from and write to these chips. Flashrom returns this - Generic unknown SPI chip (RDID)" (0 KB, SPI) at physical address 0x0 . Is there something I am doing wrong the chip is really small and hard to solder leads too could I be burning the chip? the first one I did got so hot the model numbers could no longer be seen on it, but my second try looks pretty good. I can send you samples to work on if that would help. If you know of a better setup to accomplish firmware extraction without manufacturer support please let me know. Thank You, Mike LaptopUniverse.com

2 1

flashrom-log (unsupported chipset)
by Halim Sahin 17 Jun '10

17 Jun '10

hello, In the attachment you find a flashrom log from latest flashrom snapshot flashrom v0.9.2-r1049 on Linux 2.6.31.5-0.1-default (i686), built with libpci 3... my chipset seems not supported currently. Maybe you can add it?? Thax for you work. BR. Halim

2 2

[PATCH 1/1] Sort flashchips defines alphabetically
by Peter Lemenkov 17 Jun '10

17 Jun '10

Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- flashchips.h | 200 +++++++++++++++++++++++++++++----------------------------- 1 files changed, 100 insertions(+), 100 deletions(-) diff --git a/flashchips.h b/flashchips.h index a04edef..2e1b0d7 100644 --- a/flashchips.h +++ b/flashchips.h @@ -40,16 +40,16 @@ #define ALLIANCE_ID 0x52 /* Alliance Semiconductor */ #define AMD_ID 0x01 /* AMD */ -#define AM_29DL400BT 0x0C #define AM_29DL400BB 0x0F -#define AM_29DL800BT 0x4A +#define AM_29DL400BT 0x0C #define AM_29DL800BB 0xCB +#define AM_29DL800BT 0x4A #define AM_29F002BB 0x34 /* Same as Am29F002NBB */ #define AM_29F002BT 0xB0 /* Same as Am29F002NBT */ #define AM_29F004BB 0x7B #define AM_29F004BT 0x77 -#define AM_29F016D 0xAD #define AM_29F010B 0x20 /* Same as Am29F010A */ +#define AM_29F016D 0xAD #define AM_29F040B 0xA4 #define AM_29F080B 0xD5 #define AM_29F200BB 0x57 @@ -68,9 +68,9 @@ #define AM_29LV080B 0x38 /* Same as Am29LV081B */ #define AM_29LV200BB 0xBF #define AM_29LV200BT 0x3B -#define AM_29LV800BB 0x5B /* Same as Am29LV800DB */ -#define AM_29LV400BT 0xB9 #define AM_29LV400BB 0xBA +#define AM_29LV400BT 0xB9 +#define AM_29LV800BB 0x5B /* Same as Am29LV800DB */ #define AM_29LV800BT 0xDA /* Same as Am29LV800DT */ #define AMIC_ID 0x7F37 /* AMIC */ @@ -113,9 +113,9 @@ #define AT_26DF161A 0x4601 #define AT_26DF321 0x4700 /* Same as 25DF321 */ #define AT_26F004 0x0400 -#define AT_29C040A 0xA4 #define AT_29C010A 0xD5 #define AT_29C020 0xDA +#define AT_29C040A 0xA4 #define AT_29C512 0x5D #define AT_45BR3214B /* No ID available */ #define AT_45CS1282 0x2920 @@ -144,9 +144,9 @@ #define AT_45DB642 /* No ID available */ #define AT_45DB642D 0x2800 #define AT_49BV512 0x03 -#define AT_49F020 0x0B #define AT_49F002N 0x07 /* for AT49F002(N) */ #define AT_49F002NT 0x08 /* for AT49F002(N)T */ +#define AT_49F020 0x0B #define CATALYST_ID 0x31 /* Catalyst */ @@ -165,44 +165,44 @@ #define EON_ID 0x7F1C /* EON Silicon Devices */ #define EON_ID_NOPREFIX 0x1C /* EON, missing 0x7F prefix */ #define EN_25B05 0x2010 /* Same as P05, 2^19 kbit or 2^16 kByte */ -#define EN_25B05T 0x25 #define EN_25B05B 0x95 +#define EN_25B05T 0x25 #define EN_25B10 0x2011 /* Same as P10 */ -#define EN_25B10T 0x40 #define EN_25B10B 0x30 -#define EN_25B20 0x2012 /* Same as P20 */ -#define EN_25B20T 0x41 -#define EN_25B20B 0x31 -#define EN_25B40 0x2013 /* Same as P40 */ -#define EN_25B40T 0x42 -#define EN_25B40B 0x32 -#define EN_25B80 0x2014 /* Same as P80 */ -#define EN_25B80T 0x43 -#define EN_25B80B 0x33 +#define EN_25B10T 0x40 #define EN_25B16 0x2015 /* Same as P16 */ -#define EN_25B16T 0x44 #define EN_25B16B 0x34 +#define EN_25B16T 0x44 +#define EN_25B20 0x2012 /* Same as P20 */ +#define EN_25B20B 0x31 +#define EN_25B20T 0x41 #define EN_25B32 0x2016 /* Same as P32 */ -#define EN_25B32T 0x45 #define EN_25B32B 0x35 +#define EN_25B32T 0x45 +#define EN_25B40 0x2013 /* Same as P40 */ +#define EN_25B40B 0x32 +#define EN_25B40T 0x42 #define EN_25B64 0x2017 /* Same as P64 */ -#define EN_25B64T 0x46 #define EN_25B64B 0x36 +#define EN_25B64T 0x46 +#define EN_25B80 0x2014 /* Same as P80 */ +#define EN_25B80B 0x33 +#define EN_25B80T 0x43 #define EN_25D16 0x3015 #define EN_25F05 0x3110 #define EN_25F10 0x3111 +#define EN_25F16 0x3115 #define EN_25F20 0x3112 +#define EN_25F32 0x3116 #define EN_25F40 0x3113 #define EN_25F80 0x3114 -#define EN_25F16 0x3115 -#define EN_25F32 0x3116 -#define EN_29F512 0x7F21 +#define EN_29F002B 0x7F97 /* Same as EN29F002AN */ +#define EN_29F002T 0x7F92 /* Same as EN29F002A */ #define EN_29F010 0x20 #define EN_29F040A 0x7F04 +#define EN_29F512 0x7F21 #define EN_29LV010 0x7F6E #define EN_29LV040A 0x7F4F /* EN_29LV040(A) */ -#define EN_29F002T 0x7F92 /* Same as EN29F002A */ -#define EN_29F002B 0x7F97 /* Same as EN29F002AN */ #define FUJITSU_ID 0x04 /* Fujitsu */ #define MBM29DL400BC 0x0F @@ -236,16 +236,16 @@ #define MBM29LV800TA 0xDA /* Same as MBM29LV800TE */ #define HYUNDAI_ID 0xAD /* Hyundai */ -#define HY_29F400T 0x23 /* Same as HY_29F400AT */ -#define HY_29F800B 0x58 /* Same as HY_29F800AB */ -#define HY_29LV800B 0x5B -#define HY_29F040A 0xA4 -#define HY_29F400B 0xAB /* Same as HY_29F400AB */ #define HY_29F002 0xB0 -#define HY_29LV400T 0xB9 -#define HY_29LV400B 0xBA +#define HY_29F040A 0xA4 #define HY_29F080 0xD5 +#define HY_29F400B 0xAB /* Same as HY_29F400AB */ +#define HY_29F400T 0x23 /* Same as HY_29F400AT */ +#define HY_29F800B 0x58 /* Same as HY_29F800AB */ #define HY_29F800T 0xD6 /* Same as HY_29F800AT */ +#define HY_29LV400B 0xBA +#define HY_29LV400T 0xB9 +#define HY_29LV800B 0x5B #define HY_29LV800T 0xDA #define IMT_ID 0x7F1F /* Integrated Memory Technologies */ @@ -253,17 +253,17 @@ #define IM_29F004T 0xAF #define INTEL_ID 0x89 /* Intel */ -#define I_82802AB 0xAD -#define I_82802AC 0xAC #define E_28F004S5 0xA7 #define E_28F008S5 0xA6 #define E_28F016S5 0xAA -#define P28F001BXT 0x94 /* 28F001BX-T */ +#define I_82802AB 0xAD +#define I_82802AC 0xAC #define P28F001BXB 0x95 /* 28F001BX-B */ -#define P28F004BT 0x78 /* 28F004BV/BE-T */ +#define P28F001BXT 0x94 /* 28F001BX-T */ #define P28F004BB 0x79 /* 28F004BV/BE-B */ -#define P28F400BT 0x70 /* 28F400BV/CV/CE-T */ +#define P28F004BT 0x78 /* 28F004BV/BE-T */ #define P28F400BB 0x71 /* 28F400BV/CV/CE-B */ +#define P28F400BT 0x70 /* 28F400BV/CV/CE-T */ #define SHARP_LH28F008SA 0xA2 /* Sharp chip, Intel Vendor ID */ #define SHARP_LH28F008SC 0xA6 /* Sharp chip, Intel Vendor ID */ @@ -276,17 +276,17 @@ * and use the same set of IDs. */ #define MX_ID 0xC2 /* Macronix (MX) */ -#define MX_25L512 0x2010 /* Same as MX25V512 */ #define MX_25L1005 0x2011 -#define MX_25L2005 0x2012 -#define MX_25L4005 0x2013 /* MX25L4005{,A} */ -#define MX_25L8005 0x2014 /* Same as MX25V8005 */ -#define MX_25L1605 0x2015 /* MX25L1605{,A,D} */ -#define MX_25L3205 0x2016 /* MX25L3205{,A} */ -#define MX_25L6405 0x2017 /* MX25L3205{,D} */ #define MX_25L12805 0x2018 /* MX25L12805 */ +#define MX_25L1605 0x2015 /* MX25L1605{,A,D} */ #define MX_25L1635D 0x2415 +#define MX_25L2005 0x2012 +#define MX_25L3205 0x2016 /* MX25L3205{,A} */ #define MX_25L3235D 0x5E16 /* MX25L3225D/MX25L3235D/MX25L3237D */ +#define MX_25L4005 0x2013 /* MX25L4005{,A} */ +#define MX_25L512 0x2010 /* Same as MX25V512 */ +#define MX_25L6405 0x2017 /* MX25L3205{,D} */ +#define MX_25L8005 0x2014 /* Same as MX25V8005 */ #define MX_29F001B 0x19 #define MX_29F001T 0x18 #define MX_29F002B 0x34 /* Same as MX29F002NB */ @@ -333,20 +333,20 @@ */ #define PMC_ID 0x7F9D /* PMC */ #define PMC_ID_NOPREFIX 0x9D /* PMC, missing 0x7F prefix */ -#define PMC_25LV512 0x7B #define PMC_25LV010 0x7C +#define PMC_25LV016B 0x14 #define PMC_25LV020 0x7D #define PMC_25LV040 0x7E #define PMC_25LV080B 0x13 -#define PMC_25LV016B 0x14 -#define PMC_29F002T 0x1D +#define PMC_25LV512 0x7B #define PMC_29F002B 0x2D -#define PMC_39LV512 0x1B +#define PMC_29F002T 0x1D #define PMC_39F010 0x1C /* Same as Pm39LV010 */ -#define PMC_39LV020 0x3D -#define PMC_39LV040 0x3E #define PMC_39F020 0x4D #define PMC_39F040 0x4E +#define PMC_39LV020 0x3D +#define PMC_39LV040 0x3E +#define PMC_39LV512 0x1B #define PMC_49FL002 0x6D #define PMC_49FL004 0x6E @@ -359,8 +359,8 @@ #define SANYO_LE25FW203A 0x1600 #define SHARP_ID 0xB0 /* Sharp */ -#define SHARP_LH28F008BJxxPT 0xEC #define SHARP_LH28F008BJxxPB 0xED +#define SHARP_LH28F008BJxxPT 0xEC #define SHARP_LH28F800BVxxBTL 0x4B #define SHARP_LH28F800BVxxBV 0x4D #define SHARP_LH28F800BVxxTV 0x4C @@ -381,61 +381,61 @@ * byte of device ID is related to log(bitsize) at least for some chips. */ #define SST_ID 0xBF /* SST */ -#define SST_25WF512 0x2501 -#define SST_25WF010 0x2502 -#define SST_25WF020 0x2503 -#define SST_25WF040 0x2504 -#define SST_25VF512A_REMS 0x48 /* REMS or RES opcode */ #define SST_25VF010_REMS 0x49 /* REMS or RES opcode */ +#define SST_25VF016B 0x2541 #define SST_25VF020_REMS 0x43 /* REMS or RES opcode */ -#define SST_25VF040_REMS 0x44 /* REMS or RES opcode, same as SST25LF040A */ +#define SST_25VF032B 0x254A +#define SST_25VF032B_REMS 0x4A /* REMS or RES opcode */ #define SST_25VF040B 0x258D #define SST_25VF040B_REMS 0x8D /* REMS or RES opcode */ -#define SST_25VF080_REMS 0x80 /* REMS or RES opcode */ +#define SST_25VF040_REMS 0x44 /* REMS or RES opcode, same as SST25LF040A */ #define SST_25VF080B 0x258E #define SST_25VF080B_REMS 0x8E /* REMS or RES opcode */ -#define SST_25VF016B 0x2541 -#define SST_25VF032B 0x254A -#define SST_25VF032B_REMS 0x4A /* REMS or RES opcode */ +#define SST_25VF080_REMS 0x80 /* REMS or RES opcode */ +#define SST_25VF512A_REMS 0x48 /* REMS or RES opcode */ +#define SST_25WF010 0x2502 +#define SST_25WF020 0x2503 +#define SST_25WF040 0x2504 +#define SST_25WF512 0x2501 #define SST_26VF016 0x2601 #define SST_26VF032 0x2602 -#define SST_27SF512 0xA4 #define SST_27SF010 0xA5 #define SST_27SF020 0xA6 +#define SST_27SF512 0xA4 #define SST_27VF010 0xA9 #define SST_27VF020 0xAA #define SST_28SF040 0x04 -#define SST_29EE512 0x5D #define SST_29EE010 0x07 -#define SST_29LE010 0x08 /* Same as SST29VE010 */ #define SST_29EE020A 0x10 /* Same as SST29EE020 */ +#define SST_29EE512 0x5D +#define SST_29LE010 0x08 /* Same as SST29VE010 */ #define SST_29LE020 0x12 /* Same as SST29VE020 */ #define SST_29SF020 0x24 -#define SST_29VF020 0x25 #define SST_29SF040 0x13 +#define SST_29VF020 0x25 #define SST_29VF040 0x14 -#define SST_39SF512 0xB4 #define SST_39SF010 0xB5 #define SST_39SF020 0xB6 /* Same as 39SF020A */ #define SST_39SF040 0xB7 -#define SST_39VF512 0xD4 +#define SST_39SF512 0xB4 #define SST_39VF010 0xD5 #define SST_39VF020 0xD6 /* Same as 39LF020 */ #define SST_39VF040 0xD7 /* Same as 39LF040 */ #define SST_39VF080 0xD8 /* Same as 39LF080/39VF080/39VF088 */ -#define SST_49LF040B 0x50 -#define SST_49LF040 0x51 -#define SST_49LF020 0x61 -#define SST_49LF020A 0x52 -#define SST_49LF030A 0x1C -#define SST_49LF080A 0x5B +#define SST_39VF512 0xD4 #define SST_49LF002A 0x57 #define SST_49LF003A 0x1B #define SST_49LF004A 0x60 /* Same as 49LF004B */ -#define SST_49LF008A 0x5A #define SST_49LF004C 0x54 +#define SST_49LF008A 0x5A #define SST_49LF008C 0x59 #define SST_49LF016C 0x5C +#define SST_49LF020 0x61 +#define SST_49LF020A 0x52 +#define SST_49LF030A 0x1C +#define SST_49LF040 0x51 +#define SST_49LF040B 0x50 +#define SST_49LF080A 0x5B #define SST_49LF160C 0x4C /* @@ -447,52 +447,52 @@ #define ST_M25P05_RES 0x10 /* Same code as M25P10. */ #define ST_M25P10A 0x2011 #define ST_M25P10_RES 0x10 /* Same code as M25P05. */ +#define ST_M25P128 0x2018 +#define ST_M25P16 0x2015 #define ST_M25P20 0x2012 +#define ST_M25P32 0x2016 #define ST_M25P40 0x2013 #define ST_M25P40_RES 0x12 -#define ST_M25P80 0x2014 -#define ST_M25P16 0x2015 -#define ST_M25P32 0x2016 #define ST_M25P64 0x2017 -#define ST_M25P128 0x2018 +#define ST_M25P80 0x2014 #define ST_M25PE10 0x8011 +#define ST_M25PE16 0x8015 #define ST_M25PE20 0x8012 #define ST_M25PE40 0x8013 #define ST_M25PE80 0x8014 -#define ST_M25PE16 0x8015 -#define ST_M50FLW040A 0x08 -#define ST_M50FLW040B 0x28 -#define ST_M50FLW080A 0x80 -#define ST_M50FLW080B 0x81 -#define ST_M50FW002 0x29 -#define ST_M50FW040 0x2C -#define ST_M50FW080 0x2D -#define ST_M50FW016 0x2E -#define ST_M50LPW116 0x30 #define ST_M29F002B 0x34 /* Same as M29F002BB */ #define ST_M29F002T 0xB0 /* Same as M29F002BT/M29F002NT/M29F002BNT */ #define ST_M29F040B 0xE2 /* Same as M29F040 */ #define ST_M29F080 0xF1 -#define ST_M29F200BT 0xD3 #define ST_M29F200BB 0xD4 -#define ST_M29F400BT 0xD5 /* Same as M29F400T */ +#define ST_M29F200BT 0xD3 #define ST_M29F400BB 0xD6 /* Same as M29F400B */ +#define ST_M29F400BT 0xD5 /* Same as M29F400T */ #define ST_M29F800DB 0x58 #define ST_M29F800DT 0xEC #define ST_M29W010B 0x23 #define ST_M29W040B 0xE3 #define ST_M29W512B 0x27 +#define ST_M50FLW040A 0x08 +#define ST_M50FLW040B 0x28 +#define ST_M50FLW080A 0x80 +#define ST_M50FLW080B 0x81 +#define ST_M50FW002 0x29 +#define ST_M50FW016 0x2E +#define ST_M50FW040 0x2C +#define ST_M50FW080 0x2D +#define ST_M50LPW116 0x30 #define SYNCMOS_ID 0x40 /* SyncMOS and Mosel Vitelic */ +#define S29C31004T 0x63 #define S29C51001T 0x01 #define S29C51002T 0x02 #define S29C51004T 0x03 -#define S29C31004T 0x63 #define TI_ID 0x97 /* Texas Instruments */ #define TI_OLD_ID 0x01 /* TI chips from last century */ -#define TI_TMS29F002RT 0xB0 #define TI_TMS29F002RB 0x34 +#define TI_TMS29F002RT 0xB0 /* * W25X chips are SPI, first byte of device ID is memory type, second @@ -500,26 +500,26 @@ */ #define WINBOND_ID 0xDA /* Winbond */ #define WINBOND_NEX_ID 0xEF /* Winbond (ex Nexcom) serial flashes */ +#define W_25Q16 0x4015 +#define W_25Q32 0x4016 +#define W_25Q80 0x4014 #define W_25X10 0x3011 -#define W_25X20 0x3012 -#define W_25X40 0x3013 -#define W_25X80 0x3014 #define W_25X16 0x3015 +#define W_25X20 0x3012 #define W_25X32 0x3016 +#define W_25X40 0x3013 #define W_25X64 0x3017 -#define W_25Q80 0x4014 -#define W_25Q16 0x4015 -#define W_25Q32 0x4016 +#define W_25X80 0x3014 #define W_29C011 0xC1 #define W_29C020C 0x45 /* Same as W29C020 and ASD AE29F2008 */ #define W_29C040P 0x46 /* Same as W29C040 */ #define W_29EE011 0xC1 #define W_39L020 0xB5 #define W_39L040 0xB6 -#define W_39V040FA 0x34 #define W_39V040A 0x3D #define W_39V040B 0x54 #define W_39V040C 0x50 +#define W_39V040FA 0x34 #define W_39V080A 0xD0 #define W_39V080FA 0xD3 #define W_39V080FA_DM 0x93 -- 1.7.0.1

2 1

jetway PA78VM5 spi flashing
by Qing Pei Wang 17 Jun '10

17 Jun '10

hi all, Recently i found that the mainboard which i used(Jetway PA78VM-H-LF) is not stable, most of the spi flashing caused data error. the data writing is ok, but the bios data does not as the same as the original. the SPI FLASH is Winbond W25X80A In the other hand, the board can not boot correctly, i am wondering if it's because of the CPU. Olsen, have you ever met this problem? -- Wang Qing Pei MSN:wangqingpei@hotmail.com <MSN%3Awangqingpei(a)hotmail.com> Gmail:wangqingpei@gmail.com <Gmail%3Awangqingpei(a)gmail.com> Phone:86+13426369984

2 4

[PATCH] SPI read/write progress bar hack
by Carl-Daniel Hailfinger 17 Jun '10

17 Jun '10

SPI read/write progress bar hack. Prints a dot for every page read/written. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Daniel, this patch (together with the protocol violation 3x speedup patch) should print roughly 4 dots per second for read/erase on your system. I suggest you only try with read to check if read time is affected by this. If read time is unaffected, erase time will be unaffected as well. I expect one dot every 9 seconds for write, but I also suggest you wait with another write attempt until I get around to posting the AAI patch for you. Index: flashrom-spi_progressbar_hack/spi25.c =================================================================== --- flashrom-spi_progressbar_hack/spi25.c (Revision 1049) +++ flashrom-spi_progressbar_hack/spi25.c (Arbeitskopie) @@ -922,6 +922,8 @@ * page as well, the loop condition uses <=. */ for (i = start / page_size; i <= (start + len - 1) / page_size; i++) { + /* Simple progress printing, one dot per page. */ + msg_cdbg("."); /* Byte position of the first byte in the range in this page. */ /* starthere is an offset to the base address of the chip. */ starthere = max(start, i * page_size); @@ -966,6 +968,8 @@ * page as well, the loop condition uses <=. */ for (i = start / page_size; i <= (start + len - 1) / page_size; i++) { + /* Simple progress printing, one dot per page. */ + msg_cdbg("."); /* Byte position of the first byte in the range in this page. */ /* starthere is an offset to the base address of the chip. */ starthere = max(start, i * page_size); @@ -1006,6 +1010,9 @@ } msg_cinfo("done.\n"); for (i = 0; i < total_size; i++) { + /* Simple progress printing, one dot per page. */ + if (i % flash->page_size == 0) + msg_cdbg("."); result = spi_byte_program(i, buf[i]); if (result) return 1; -- http://www.hailfinger.org/

1 0

Set maximum flash size for 3Com NICs to 128kb = 1Mbit
by Peter Stuge 17 Jun '10

17 Jun '10

Benjamin, great to meet you during LinuxTag! I committed the attached patch to flashrom as r1049 - it should make flashrom warn about larger flash chips when using these cards. I'm sorry that such a stupid bug in flashrom wasted your time. :\ //Peter

1 0

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