- flashrom - mail.coreboot.org

[RFC] Chip ID #defines
by Carl-Daniel Hailfinger 22 Jul '10

22 Jul '10

Parts of flashrom codebase are really old any nobody ever got around to cleaning them up. flashchips.h is one of those places with organic growth on top of historic cruft. Right now, most chip ID #defines have underscores somewhere in the first few characters of the name. For a sizable portion of flash chips this underscore does not make any sense if you look at the original chip name. My best guess is that someone originally thought that having a vendor name as part of the chip ID #define. For chips which have the vendor name as part of the chip name anyway this might make sense. A prominent example is SST_49LF080A. OTOH, stuff like W_25X10 is just really ugly. Besides that, grepping for those identifiers requires a lot of guesswork if you only know the chip name as printed on the chip. I am not sure if we really want to have underscores in random places in all those IDs. Nobody ever bothered to make those #defines look sane or consistent. Should we kill the underscore inside the chip name completely and instead use $VENDORNAME_$CHIPNAME for the #defines? IMHO that looks more natural and makes grepping easier. We'd still have to decide whether we should use the vendor name as it is used in $VENDOR_ID or a different form. For SST (and a few other manufacturers) this is not a problem because the vendor ID #define is SST_ID. However, for Winbond it gets a bit more difficult because we have WINBOND_ID and WINBOND_NEX_ID. W_25X10 would become either WINBOND_NEX_W25X10 or WINBOND_W25X10. I think the former variant makes it easier to visually cross-check if the vendor and chip ID combination makes sense. Sometimes multiple chips have the same ID. That's not a problem if the chips have identical characteristics and if they share one common entry in flashchips.c. We could add .alias_vendor and .alias_name fields (or any similar solution) to struct flashchip to accommodate chips where the vendor and chip name changed a few times in a way that can't be expressed easily with "oldname/newname". We also should definitely talk about evil twins. Those are chips with identical IDs but distinct/incompatible programming strategies. I sent a patch to mark some of them as evil twins, but we still have to decide if those evil twins should use the same #define for the ID or if they should use different #defines. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[commit] r1096 - trunk
by repository service 22 Jul '10

22 Jul '10

Author: hailfinger Date: Thu Jul 22 13:44:38 2010 New Revision: 1096 URL: http://flashrom.org/trac/coreboot/changeset/1096 Log: Add support for the following AMIC SPI chips: http://www.amictechnology.com/pdf/A25L20P.pdf covers: AMIC A25L05PT AMIC A25L05PU AMIC A25L10PT AMIC A25L10PU AMIC A25L20PT AMIC A25L20PU http://www.amictechnology.com/pdf/A25L16P.pdf covers: AMIC A25L16PT AMIC A25L16PU Clarify the situation surrounding the A25L40PT and A25L40PU chips which share the same RDID values, despite the fact that their erase block layouts are different. Rudolf Marek tested and confirmed the distinct erase block layouts of these chips. Add a pretty-printer for the AMIC SPI chip status register Add a generic AMIC chip type. Signed-off-by: Daniel Lenski <dlenski(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashchips.c trunk/flashchips.h trunk/spi25.c Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Wed Jul 21 17:12:07 2010 (r1095) +++ trunk/flashchips.c Thu Jul 22 13:44:38 2010 (r1096) @@ -1169,14 +1169,207 @@ .read = read_memmapped, }, - /* The next two chip definitions have top/bottom boot blocks, but has no - device differentiation between the two */ + { + .vendor = "AMIC", + .name = "A25L05PT", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = AMIC_ID, + .model_id = AMIC_A25L05PT, + .total_size = 64, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid4, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {32 * 1024, 1}, + {16 * 1024, 1}, + {8 * 1024, 1}, + {4 * 1024, 2}, + }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "AMIC", + .name = "A25L05PU", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = AMIC_ID, + .model_id = AMIC_A25L05PU, + .total_size = 64, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid4, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {4 * 1024, 2}, + {8 * 1024, 1}, + {16 * 1024, 1}, + {32 * 1024, 1}, + }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "AMIC", + .name = "A25L10PT", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = AMIC_ID, + .model_id = AMIC_A25L10PT, + .total_size = 128, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid4, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 1}, + {32 * 1024, 1}, + {16 * 1024, 1}, + {8 * 1024, 1}, + {4 * 1024, 2}, + }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "AMIC", + .name = "A25L10PU", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = AMIC_ID, + .model_id = AMIC_A25L10PU, + .total_size = 128, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid4, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {4 * 1024, 2}, + {8 * 1024, 1}, + {16 * 1024, 1}, + {32 * 1024, 1}, + {64 * 1024, 1}, + }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "AMIC", + .name = "A25L20PT", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = AMIC_ID, + .model_id = AMIC_A25L20PT, + .total_size = 256, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid4, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 3}, + {32 * 1024, 1}, + {16 * 1024, 1}, + {8 * 1024, 1}, + {4 * 1024, 2}, + }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "AMIC", + .name = "A25L20PU", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = AMIC_ID, + .model_id = AMIC_A25L20PU, + .total_size = 256, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid4, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {4 * 1024, 2}, + {8 * 1024, 1}, + {16 * 1024, 1}, + {32 * 1024, 1}, + {64 * 1024, 3}, + }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + /* The A25L40P{T,U} chips are distinguished by their + * erase block layouts, but without any distinction in RDID. + * This inexplicable quirk was verified by Rudolf Marek + * and discussed on the flashrom mailing list on 2010-07-12. + */ { .vendor = "AMIC", .name = "A25L40PT", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = AMIC_ID, - .model_id = AMIC_A25L40P, + .model_id = AMIC_A25L40PT, .total_size = 512, .page_size = 256, .tested = TEST_OK_PRW, @@ -1208,7 +1401,7 @@ .name = "A25L40PU", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = AMIC_ID, - .model_id = AMIC_A25L40P, + .model_id = AMIC_A25L40PU, .total_size = 512, .page_size = 256, .tested = TEST_OK_PRW, @@ -1269,6 +1462,76 @@ { .vendor = "AMIC", + .name = "A25L16PT", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = AMIC_ID, + .model_id = AMIC_A25L16PT, + .total_size = 2048, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid4, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 31}, + {32 * 1024, 1}, + {16 * 1024, 1}, + {8 * 1024, 1}, + {4 * 1024, 2}, + }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2048 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2048 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "AMIC", + .name = "A25L16PU", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = AMIC_ID, + .model_id = AMIC_A25L16PU, + .total_size = 2048, + .page_size = 256, + .tested = TEST_OK_PRW, + .probe = probe_spi_rdid4, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {4 * 1024, 2}, + {8 * 1024, 1}, + {16 * 1024, 1}, + {32 * 1024, 1}, + {64 * 1024, 31}, + }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2048 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2048 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "AMIC", .name = "A29002B", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = AMIC_ID_NOPREFIX, @@ -6678,6 +6941,21 @@ }, { + .vendor = "AMIC", + .name = "unknown AMIC SPI chip", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = AMIC_ID, + .model_id = GENERIC_DEVICE_ID, + .total_size = 0, + .page_size = 256, + .tested = TEST_BAD_PREW, + .probe = probe_spi_rdid4, + .probe_timing = TIMING_ZERO, + .write = NULL, + .read = NULL, + }, + + { .vendor = "Atmel", .name = "unknown Atmel SPI chip", .bustype = CHIP_BUSTYPE_SPI, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Wed Jul 21 17:12:07 2010 (r1095) +++ trunk/flashchips.h Thu Jul 22 13:44:38 2010 (r1096) @@ -75,8 +75,19 @@ #define AMIC_ID 0x7F37 /* AMIC */ #define AMIC_ID_NOPREFIX 0x37 /* AMIC */ -#define AMIC_A25L40P 0x2013 -#define AMIC_A25L80P 0x2014 +#define AMIC_A25L05PT 0x2020 +#define AMIC_A25L05PU 0x2010 +#define AMIC_A25L10PT 0x2021 +#define AMIC_A25L10PU 0x2011 +#define AMIC_A25L20PT 0x2022 +#define AMIC_A25L20PU 0x2012 +#define AMIC_A25L40PT 0x2013 /* Datasheet says T and U have + same device ID. Confirmed by + hardware testing. */ +#define AMIC_A25L40PU 0x2013 +#define AMIC_A25L80P 0x2014 /* Seems that no A25L80PT exists */ +#define AMIC_A25L16PT 0x2025 +#define AMIC_A25L16PU 0x2015 #define AMIC_A29002B 0x0d #define AMIC_A29002T 0x8C /* Same as A290021T */ #define AMIC_A29040B 0x86 Modified: trunk/spi25.c ============================================================================== --- trunk/spi25.c Wed Jul 21 17:12:07 2010 (r1095) +++ trunk/spi25.c Thu Jul 22 13:44:38 2010 (r1096) @@ -328,6 +328,16 @@ } /* Prettyprint the status register. Works for + * AMIC A25L series + */ +void spi_prettyprint_status_register_amic_a25l(uint8_t status) +{ + msg_cdbg("Chip status register: Status Register Write Disable " + "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); + spi_prettyprint_status_register_common(status); +} + +/* Prettyprint the status register. Works for * ST M25P series * MX MX25L series */ @@ -389,6 +399,10 @@ status = spi_read_status_register(); msg_cdbg("Chip status register is %02x\n", status); switch (flash->manufacture_id) { + case AMIC_ID: + if ((flash->model_id & 0xff00) == 0x2000) + spi_prettyprint_status_register_amic_a25l(status); + break; case ST_ID: if (((flash->model_id & 0xff00) == 0x2000) || ((flash->model_id & 0xff00) == 0x2500))

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[PATCH] RayeR speedups, variable port
by Carl-Daniel Hailfinger 21 Jul '10

21 Jul '10

Speed up RayeR SPIPGM driver in flashrom by a factor of 2. Allow specification of an alternate base port with flashrom -p rayer_spi:lptport=0x278 Any port number is allowed as long as it is nonzero, below 65536 and a multiple of four. Untested, should work. Martin, this one should hopefully reach the speed of SPIPGM.exe for reads. I'll ask Idwer to provide a DOS binary for you. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-bitbang_spi_rayer_faster/flashrom.8 =================================================================== --- flashrom-bitbang_spi_rayer_faster/flashrom.8 (Revision 1093) +++ flashrom-bitbang_spi_rayer_faster/flashrom.8 (Arbeitskopie) @@ -394,7 +394,18 @@ (in Hz). The default is the maximum frequency of 8 MHz. .TP .BR "rayer_spi " programmer -No parameters defined yet. More information about the hardware is available at +The default I/O base address used for the parallel port is 0x378 and you can use +the optional +.B lptport +parameter to specify an alternate base I/O address with the +.sp +.B " flashrom \-p rayer_spi:lptport=portnum" +.sp +syntax where +.B portnum +is the I/O port number of your parallel port which must be a multiple of 4. +.sp +More information about the hardware is available at http://rayer.ic.cz/elektro/spipgm.htm .SH EXIT STATUS flashrom exits with 0 on success, 1 on most failures but with 2 if /dev/mem Index: flashrom-bitbang_spi_rayer_faster/rayer_spi.c =================================================================== --- flashrom-bitbang_spi_rayer_faster/rayer_spi.c (Revision 1093) +++ flashrom-bitbang_spi_rayer_faster/rayer_spi.c (Arbeitskopie) @@ -30,6 +30,7 @@ */ #if defined(__i386__) || defined(__x86_64__) +#include <stdlib.h> #include "flash.h" /* We have two sets of pins, out and in. The numbers for both sets are @@ -42,7 +43,7 @@ /* Pins for slave->master direction */ #define SPI_MISO_PIN 6 -static int lpt_iobase; +static uint16_t lpt_iobase; /* FIXME: All rayer_bitbang_set_* functions could use caching of the value * stored at port lpt_iobase to avoid unnecessary INB. In theory, only one @@ -50,37 +51,31 @@ * value. */ -void rayer_bitbang_set_cs(int val) +/* Cached value of last byte sent. */ +static uint8_t lpt_outval; + +static void rayer_bitbang_set_cs(int val) { - uint8_t tmp; - - tmp = INB(lpt_iobase); - tmp &= ~(1 << SPI_CS_PIN); - tmp |= (val << SPI_CS_PIN); - OUTB(tmp, lpt_iobase); + lpt_outval &= ~(1 << SPI_CS_PIN); + lpt_outval |= (val << SPI_CS_PIN); + OUTB(lpt_outval, lpt_iobase); } -void rayer_bitbang_set_sck(int val) +static void rayer_bitbang_set_sck(int val) { - uint8_t tmp; - - tmp = INB(lpt_iobase); - tmp &= ~(1 << SPI_SCK_PIN); - tmp |= (val << SPI_SCK_PIN); - OUTB(tmp, lpt_iobase); + lpt_outval &= ~(1 << SPI_SCK_PIN); + lpt_outval |= (val << SPI_SCK_PIN); + OUTB(lpt_outval, lpt_iobase); } -void rayer_bitbang_set_mosi(int val) +static void rayer_bitbang_set_mosi(int val) { - uint8_t tmp; - - tmp = INB(lpt_iobase); - tmp &= ~(1 << SPI_MOSI_PIN); - tmp |= (val << SPI_MOSI_PIN); - OUTB(tmp, lpt_iobase); + lpt_outval &= ~(1 << SPI_MOSI_PIN); + lpt_outval |= (val << SPI_MOSI_PIN); + OUTB(lpt_outval, lpt_iobase); } -int rayer_bitbang_get_miso(void) +static int rayer_bitbang_get_miso(void) { uint8_t tmp; @@ -99,16 +94,49 @@ int rayer_spi_init(void) { - /* Pick a default value for now. */ - lpt_iobase = 0x378; + char *portpos = NULL; + /* Non-default port requested? */ + portpos = extract_programmer_param("lptport"); + if (portpos) { + char *endptr = NULL; + unsigned long tmp; + tmp = strtoul(portpos, &endptr, 0); + /* Port 0, port >0x1000, unaligned ports and garbage strings + * are rejected. + */ + if (!tmp || (tmp >= 0x10000) || (tmp & 0x3) || + (*endptr != '\0')) { + /* Using ports below 0x100 is a really bad idea, and + * should only be done if no port between 0x100 and + * 0xfffc works due to routing issues. + */ + msg_perr("Error: lptport specified, but no valid " + "port specified.\nPort must be a multiple of " + "0x4 and lie between 0x100 and 0xfffc.\n"); + free(portpos); + return 1; + } else { + lpt_iobase = (uint16_t)tmp; + msg_pinfo("Non-default I/O base requested. This will " + "not change the hardware settings.\n"); + } + } else { + /* Pick a default value for the I/O base. */ + lpt_iobase = 0x378; + } + free(portpos); + msg_pdbg("Using port 0x%x as I/O base for parallel port access.\n", lpt_iobase); get_io_perms(); - /* 1 usec halfperiod delay for now. */ - if (bitbang_spi_init(&bitbang_spi_master_rayer, 1)) + /* Get the initial value before writing to any line. */ + lpt_outval = INB(lpt_iobase); + + /* Zero halfperiod delay. */ + if (bitbang_spi_init(&bitbang_spi_master_rayer, 0)) return 1; buses_supported = CHIP_BUSTYPE_SPI; -- http://www.hailfinger.org/

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[commit] r1095 - trunk
by repository service 21 Jul '10

21 Jul '10

Author: hailfinger Date: Wed Jul 21 17:12:07 2010 New Revision: 1095 URL: http://flashrom.org/trac/coreboot/changeset/1095 Log: Add nicnatsemi to print.c and print_wiki.c. Change the nicnatsemi address mask to use MA0-MA16 and set the maximum decode size to 128KB. Signed-off-by: Andrew Morgan <ziltro(a)ziltro.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/nicnatsemi.c trunk/print.c trunk/print_wiki.c Modified: trunk/nicnatsemi.c ============================================================================== --- trunk/nicnatsemi.c Wed Jul 21 17:02:22 2010 (r1094) +++ trunk/nicnatsemi.c Wed Jul 21 17:12:07 2010 (r1095) @@ -43,6 +43,14 @@ buses_supported = CHIP_BUSTYPE_PARALLEL; + /* The datasheet shows address lines MA0-MA16 in one place and MA0-MA15 + * in another. My NIC has MA16 connected to A16 on the boot ROM socket + * so I'm assuming it is accessible. If not then next line wants to be + * max_rom_decode.parallel = 65536; and the mask in the read/write + * functions below wants to be 0x0000FFFF. + */ + max_rom_decode.parallel = 131072; + return 0; } @@ -55,7 +63,7 @@ void nicnatsemi_chip_writeb(uint8_t val, chipaddr addr) { - OUTL((uint32_t)addr & 0x0000FFFF, io_base_addr + BOOT_ROM_ADDR); + OUTL((uint32_t)addr & 0x0001FFFF, io_base_addr + BOOT_ROM_ADDR); /* * The datasheet requires 32 bit accesses to this register, but it seems * that requirement might only apply if the register is memory mapped. @@ -69,7 +77,7 @@ uint8_t nicnatsemi_chip_readb(const chipaddr addr) { - OUTL(((uint32_t)addr & 0x0000FFFF), io_base_addr + BOOT_ROM_ADDR); + OUTL(((uint32_t)addr & 0x0001FFFF), io_base_addr + BOOT_ROM_ADDR); /* * The datasheet requires 32 bit accesses to this register, but it seems * that requirement might only apply if the register is memory mapped. Modified: trunk/print.c ============================================================================== --- trunk/print.c Wed Jul 21 17:02:22 2010 (r1094) +++ trunk/print.c Wed Jul 21 17:12:07 2010 (r1095) @@ -228,7 +228,7 @@ print_supported_boards_helper(boards_known, "boards"); print_supported_boards_helper(laptops_known, "laptops"); #endif -#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT >= 1 +#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT >= 1 printf("\nSupported PCI devices flashrom can use " "as programmer:\n\n"); #endif @@ -239,6 +239,9 @@ print_supported_pcidevs(nics_realtek); print_supported_pcidevs(nics_realteksmc1211); #endif +#if CONFIG_NICNATSEMI == 1 + print_supported_pcidevs(nics_natsemi); +#endif #if CONFIG_GFXNVIDIA == 1 print_supported_pcidevs(gfx_nvidia); #endif Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Wed Jul 21 17:02:22 2010 (r1094) +++ trunk/print_wiki.c Wed Jul 21 17:12:07 2010 (r1095) @@ -280,6 +280,9 @@ print_supported_pcidevs_wiki(nics_realtek); print_supported_pcidevs_wiki(nics_realteksmc1211); #endif +#if CONFIG_NICNATSEMI == 1 + print_supported_pcidevs_wiki(nics_natsemi); +#endif #if CONFIG_GFXNVIDIA == 1 print_supported_pcidevs_wiki(gfx_nvidia); #endif

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[RFC] National Semiconductor DP83815 NIC patch
by Andrew Morgan 21 Jul '10

21 Jul '10

Hi, I have a couple of Netgear FA311 network cards, which have DP83815DVNG chips on board, and a space to mount a 32-pin boot ROM socket. Looking at the datasheet for the chip I have created this patch. The datasheet suggests that reads and writes must be done 32 bits at a time, and only at 32 bit offsets. This seems strange for chips which have an 8 bit data bus. I don't think this code is ready for inclusion in flashrom yet, but if anyone has a card with this chip and can test it out then give it a go. I'm pretty sure it won't just work though. It might even destroy your computer/house/planet. I can't test it yet because the cards don't have a 32pin socket mounted on them. If and when I can add one then I can do some tests. This is my first 'large' patch so let me know what I have got wrong. :) Signed-off-by: Andrew Morgan <ziltro(a)ziltro.com> -- Andrew.

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[PATCH] Add SST25VF064C SPI flash
by Ed Swierk 21 Jul '10

21 Jul '10

Add definition for the SST25VF064C SPI flash chip. Signed-off-by: Ed Swierk <eswierk(a)aristanetworks.com> --- Index: flashrom-0.9.2-r1057/flashchips.c =================================================================== --- flashrom-0.9.2-r1057.orig/flashchips.c +++ flashrom-0.9.2-r1057/flashchips.c @@ -3871,6 +3871,40 @@ struct flashchip flashchips[] = { { .vendor = "SST", + .name = "SST25VF064C", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = SST_ID, + .model_id = SST_25VF064C, + .total_size = 8192, + .page_size = 256, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 256} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .write = spi_chip_write_1, + .read = spi_chip_read, + }, + + { + .vendor = "SST", .name = "SST25VF040.REMS", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = SST_ID, Index: flashrom-0.9.2-r1057/flashchips.h =================================================================== --- flashrom-0.9.2-r1057.orig/flashchips.h +++ flashrom-0.9.2-r1057/flashchips.h @@ -399,6 +399,7 @@ #define SST_25VF016B 0x2541 #define SST_25VF032B 0x254A #define SST_25VF032B_REMS 0x4A /* REMS or RES opcode */ +#define SST_25VF064C 0x254B #define SST_26VF016 0x2601 #define SST_26VF032 0x2602 #define SST_27SF512 0xA4

2 1

[commit] r1094 - trunk
by repository service 21 Jul '10

21 Jul '10

Author: hailfinger Date: Wed Jul 21 17:02:22 2010 New Revision: 1094 URL: http://flashrom.org/trac/coreboot/changeset/1094 Log: Add support for the SST25VF064C SPI flash chip. Signed-off-by: Ed Swierk <eswierk(a)aristanetworks.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Wed Jul 21 12:26:01 2010 (r1093) +++ trunk/flashchips.c Wed Jul 21 17:02:22 2010 (r1094) @@ -3971,6 +3971,41 @@ { .vendor = "SST", + .name = "SST25VF064C", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = SST_ID, + .model_id = SST_25VF064C, + .total_size = 8192, + .page_size = 256, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 256} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_1, + .read = spi_chip_read, + }, + + { + .vendor = "SST", .name = "SST25VF040.REMS", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = SST_ID, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Wed Jul 21 12:26:01 2010 (r1093) +++ trunk/flashchips.h Wed Jul 21 17:02:22 2010 (r1094) @@ -400,6 +400,7 @@ #define SST_25VF016B 0x2541 #define SST_25VF032B 0x254A #define SST_25VF032B_REMS 0x4A /* REMS or RES opcode */ +#define SST_25VF064C 0x254B #define SST_26VF016 0x2601 #define SST_26VF032 0x2602 #define SST_27SF512 0xA4

1 0

[PATCH] Board enable for Dell OptiPlex GX1 400L+
by Mattias Mattsson 21 Jul '10

21 Jul '10

Board enable for Dell OptiPlex GX1 400L+ Logs and lspci output attached. Probe/Read/Write/Erase works. (After applying patch to add definition for 28F002BC/BL/BV/BX-T chip). Signed-off-by: Mattias Mattsson <vitplister(a)gmail.com> Index: board_enable.c =================================================================== --- board_enable.c (revision 1093) +++ board_enable.c (working copy) @@ -1035,6 +1035,14 @@ } /** + * Suited for Dell OptiPlex GX1 400L+ + */ +static int intel_piix4_gpo30_lower(void) +{ + return intel_piix4_gpo_set(30, 0); +} + +/** * Set a GPIO line on a given Intel ICH LPC controller. */ static int intel_ich_gpio_set(int gpio, int raise) @@ -1679,6 +1687,7 @@ {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, OK, board_asus_p5a}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, + {0x10b7, 0x9055, 0x1028, 0x0082, 0x1002, 0x4742, 0x1028, 0x0082, NULL, NULL, NULL, "Dell", "OptiPlex GX1 400L+", 0, OK, intel_piix4_gpo30_lower}, {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise}, {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, OK, NULL}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e},

1 0

Re: [flashrom] [PATCH] Add support for RayeR SPIPGM hardware.
by Carl-Daniel Hailfinger 21 Jul '10

21 Jul '10

Hi, On 02.06.2010 09:47, RayeR wrote: > Carl-Daniel Hailfinger wrote: >> On 01.06.2010 11:54, rayer wrote: >>> it still hangs while autodetecting flash chip at AE49F2008 (is >>> displayed as last probed), >>> only with -c option it works. >>> >> Does it really work with -c CHIPNAME or do you need -f as well? >> > Yes, no -f needed. > Btw still problem with calibrating delay loop. The delay loop problem is now fixed. >> I found a bug in the bitbanging SPI core (buffer confusion) and fixed >> it. >> This version also reduces reach chunk size to 256 bytes instead of 65536 >> bytes. That makes buffer management more efficient (only one round of >> memory allocations). >> > I did't tested lpt-spi yet, I'll have to prepare some flash chip first... It would be cool if you could test the lpt-spi code. New flashrom.exe is available at http://khepri.openbios.org/~idwer/flashrom/r1039-patchwork-1441/ flashrom -p rayer_bitbang_spi -V Regards, Carl-Daniel -- http://www.hailfinger.org/

3 9

[commit] r1093 - trunk
by repository service 21 Jul '10

21 Jul '10

Author: hailfinger Date: Wed Jul 21 12:26:01 2010 New Revision: 1093 URL: http://flashrom.org/trac/coreboot/changeset/1093 Log: Add support for RayeR SPIPGM hardware as described in http://rayer.ic.cz/elektro/spipgm.htm To use the RayeR driver, run flashrom -p rayer_spi -V Known bugs/limitations: - Won't compile/work on non-x86 architectures. - Will always use direct port I/O access. Log follows: flashrom v0.9.2-r1039 on MS-DOS 7 (i686), built with libpci 3.1.5, GCC 4.3.2, little endian Calibrating delay loop... OK. Initializing rayer_bitbang_spi programmer Using port 0x378 as I/O base for parallel port access. ... Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 ... Found chip "Macronix MX25L1605" (2048 KB, SPI) at physical address 0xffe00000. ... No operations were specified. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Martin Rehak <rayer(a)seznam.cz> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Added: trunk/rayer_spi.c Modified: trunk/Makefile trunk/flash.h trunk/flashrom.8 trunk/flashrom.c trunk/spi.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Sun Jul 18 16:42:28 2010 (r1092) +++ trunk/Makefile Wed Jul 21 12:26:01 2010 (r1093) @@ -111,8 +111,15 @@ # Always enable serprog for now. Needs to be disabled on Windows. CONFIG_SERPROG ?= yes -# Bitbanging SPI infrastructure is not used yet. +# RayeR SPIPGM hardware support +CONFIG_RAYER_SPI ?= yes + +# Bitbanging SPI infrastructure, default off unless needed. +ifeq ($(CONFIG_RAYER_SPI), yes) +override CONFIG_BITBANG_SPI = yes +else CONFIG_BITBANG_SPI ?= no +endif # Always enable 3Com NICs for now. CONFIG_NIC3COM ?= yes @@ -166,6 +173,13 @@ NEED_NET := yes endif +ifeq ($(CONFIG_RAYER_SPI), yes) +FEATURE_CFLAGS += -D'CONFIG_RAYER_SPI=1' +PROGRAMMER_OBJS += rayer_spi.o +# Actually, NEED_PCI is wrong. NEED_IOPORT_ACCESS would be more correct. +NEED_PCI := yes +endif + ifeq ($(CONFIG_BITBANG_SPI), yes) FEATURE_CFLAGS += -D'CONFIG_BITBANG_SPI=1' PROGRAMMER_OBJS += bitbang_spi.o Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Sun Jul 18 16:42:28 2010 (r1092) +++ trunk/flash.h Wed Jul 21 12:26:01 2010 (r1093) @@ -81,6 +81,9 @@ #if CONFIG_DEDIPROG == 1 PROGRAMMER_DEDIPROG, #endif +#if CONFIG_RAYER_SPI == 1 + PROGRAMMER_RAYER_SPI, +#endif PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -129,6 +132,9 @@ enum bitbang_spi_master_type { BITBANG_SPI_INVALID = 0, /* This must always be the first entry. */ +#if CONFIG_RAYER_SPI == 1 + BITBANG_SPI_MASTER_RAYER, +#endif }; struct bitbang_spi_master { @@ -531,6 +537,11 @@ int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); +/* rayer_spi.c */ +#if CONFIG_RAYER_SPI == 1 +int rayer_spi_init(void); +#endif + /* bitbang_spi.c */ int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod); int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); @@ -650,6 +661,9 @@ #if CONFIG_DEDIPROG == 1 SPI_CONTROLLER_DEDIPROG, #endif +#if CONFIG_RAYER_SPI == 1 + SPI_CONTROLLER_RAYER, +#endif SPI_CONTROLLER_INVALID /* This must always be the last entry. */ }; extern const int spi_programmer_count; Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Sun Jul 18 16:42:28 2010 (r1092) +++ trunk/flashrom.8 Wed Jul 21 12:26:01 2010 (r1093) @@ -187,6 +187,9 @@ .sp .BR "* buspirate_spi" " (for SPI flash ROMs attached to a Bus Pirate)" .sp +.BR "* rayer_spi" " (for SPI flash ROMs attached to a RayeR parport \ +based programmer)" +.sp Some programmers have optional or mandatory parameters which are described in detail in the .B PROGRAMMER SPECIFIC INFO @@ -389,6 +392,10 @@ can be any of .BR 30k ", " 125k ", " 250k ", " 1M ", " 2M ", " 2.6M ", " 4M ", " 8M (in Hz). The default is the maximum frequency of 8 MHz. +.TP +.BR "rayer_spi " programmer +No parameters defined yet. More information about the hardware is available at +http://rayer.ic.cz/elektro/spipgm.htm .SH EXIT STATUS flashrom exits with 0 on success, 1 on most failures but with 2 if /dev/mem (/dev/xsvc on Solaris) can not be opened and with 3 if a call to mmap() fails. @@ -411,6 +418,9 @@ .BR gfxnvidia " and " drkaiser need PCI configuration space access and raw memory access. .sp +.B rayer_spi +needs raw I/O port access. +.sp .B satasii needs PCI configuration space read access and raw memory access. .sp Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sun Jul 18 16:42:28 2010 (r1092) +++ trunk/flashrom.c Wed Jul 21 12:26:01 2010 (r1093) @@ -48,7 +48,7 @@ * if more than one of them is selected. If only one is selected, it is clear * that the user wants that one to become the default. */ -#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG > 1 +#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG+CONFIG_RAYER_SPI > 1 #error Please enable either CONFIG_DUMMY or CONFIG_INTERNAL or disable support for all programmers except one. #endif enum programmer programmer = @@ -86,6 +86,9 @@ #if CONFIG_DEDIPROG == 1 PROGRAMMER_DEDIPROG #endif +#if CONFIG_RAYER_SPI == 1 + PROGRAMMER_RAYER_SPI +#endif ; #endif @@ -380,6 +383,25 @@ .map_flash_region = fallback_map, .unmap_flash_region = fallback_unmap, .chip_readb = noop_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = noop_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, + .delay = internal_delay, + }, +#endif + +#if CONFIG_RAYER_SPI == 1 + { + .name = "rayer_spi", + .init = rayer_spi_init, + .shutdown = noop_shutdown, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .chip_readb = noop_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, .chip_readn = fallback_chip_readn, Added: trunk/rayer_spi.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/rayer_spi.c Wed Jul 21 12:26:01 2010 (r1093) @@ -0,0 +1,122 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2009,2010 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Driver for the SPIPGM hardware by "RayeR" Martin Rehak. + * See http://rayer.ic.cz/elektro/spipgm.htm for schematics and instructions. + */ + +/* This driver uses non-portable direct I/O port accesses which won't work on + * any non-x86 platform, and even on x86 there is a high chance there will be + * collisions with any loaded parallel port drivers. + * The big advantage of direct port I/O is OS independence and speed because + * most OS parport drivers will perform many unnecessary accesses although + * this driver just treats the parallel port as a GPIO set. + */ +#if defined(__i386__) || defined(__x86_64__) + +#include "flash.h" + +/* We have two sets of pins, out and in. The numbers for both sets are + * independent and are bitshift values, not real pin numbers. + */ +/* Pins for master->slave direction */ +#define SPI_CS_PIN 5 +#define SPI_SCK_PIN 6 +#define SPI_MOSI_PIN 7 +/* Pins for slave->master direction */ +#define SPI_MISO_PIN 6 + +static int lpt_iobase; + +/* FIXME: All rayer_bitbang_set_* functions could use caching of the value + * stored at port lpt_iobase to avoid unnecessary INB. In theory, only one + * INB(lpt_iobase) would be needed on programmer init to get the initial + * value. + */ + +void rayer_bitbang_set_cs(int val) +{ + uint8_t tmp; + + tmp = INB(lpt_iobase); + tmp &= ~(1 << SPI_CS_PIN); + tmp |= (val << SPI_CS_PIN); + OUTB(tmp, lpt_iobase); +} + +void rayer_bitbang_set_sck(int val) +{ + uint8_t tmp; + + tmp = INB(lpt_iobase); + tmp &= ~(1 << SPI_SCK_PIN); + tmp |= (val << SPI_SCK_PIN); + OUTB(tmp, lpt_iobase); +} + +void rayer_bitbang_set_mosi(int val) +{ + uint8_t tmp; + + tmp = INB(lpt_iobase); + tmp &= ~(1 << SPI_MOSI_PIN); + tmp |= (val << SPI_MOSI_PIN); + OUTB(tmp, lpt_iobase); +} + +int rayer_bitbang_get_miso(void) +{ + uint8_t tmp; + + tmp = INB(lpt_iobase + 1); + tmp = (tmp >> SPI_MISO_PIN) & 0x1; + return tmp; +} + +static const struct bitbang_spi_master bitbang_spi_master_rayer = { + .type = BITBANG_SPI_MASTER_RAYER, + .set_cs = rayer_bitbang_set_cs, + .set_sck = rayer_bitbang_set_sck, + .set_mosi = rayer_bitbang_set_mosi, + .get_miso = rayer_bitbang_get_miso, +}; + +int rayer_spi_init(void) +{ + /* Pick a default value for now. */ + lpt_iobase = 0x378; + + msg_pdbg("Using port 0x%x as I/O base for parallel port access.\n", + lpt_iobase); + + get_io_perms(); + + /* 1 usec halfperiod delay for now. */ + if (bitbang_spi_init(&bitbang_spi_master_rayer, 1)) + return 1; + + buses_supported = CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_RAYER; + + return 0; +} + +#else +#error PCI port I/O access is not supported on this architecture yet. +#endif Modified: trunk/spi.c ============================================================================== --- trunk/spi.c Sun Jul 18 16:42:28 2010 (r1092) +++ trunk/spi.c Wed Jul 21 12:26:01 2010 (r1093) @@ -121,6 +121,15 @@ }, #endif +#if CONFIG_RAYER_SPI == 1 + { /* SPI_CONTROLLER_RAYER */ + .command = bitbang_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = bitbang_spi_read, + .write_256 = bitbang_spi_write_256, + }, +#endif + {}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */ };

1 0

[PATCH] Intel chip id fix-up
by Mattias Mattsson 21 Jul '10

21 Jul '10

Strip package prefix in constant names (everything before "28F"). Prefix every constant name with I_ as in "Intel". Sort intel chip constants by id. Rename the following constants to their "canonical" name: P28F400BT (0x70) -> I_28F400T (28F400BV/BX/CE/CV-T) P28F400BB (0x71) -> I_28F400B (28F400BV/BX/CE/CV-B) P28F004BT (0x78) -> I_28F004T (28F004B5/BE/BV/BX-T) P28F004BB (0x79) -> I_28F004B (28F004B5/BE/BV/BX-B) E_28F008S5 (0xA6) -> I_28F008S3 (28F008S3/S5/SC) E_28F004S5 (0xA7) -> I_28F004S3 (28F008S3/S5/SC) P28F001BXT (0x94) -> I_28F001T (28F001BN/BX-T) P28F001BXB (0x95) -> I_28F001B (28F001BN/BX-B) E_28F016S5 (0xAA) -> I_28F016S3 (28F016S3/S5/SC) Also add chip ids for the following chips: 28F320J5 28F640J5 28F320J3 28F640J3 28F128J3 28F256J3 28F200BL/BV/BX/CV-T 28F200BL/BV/BX/CV-B 28F002BC/BL/BV/BX-T 28F002BL/BV/BX-B 28F008BE/BV-T 28F008BE/BV-B 28F800B5/BV/CE/CV-T 28F800B5/BV/CE/CV-B 28F016SA/SV 28F008SA 28F008S3/S5/SC 28F008S3/S5/SC 28F016XS 28F010 28F512 28F256A 28F020 28F016B3-T 28F016B3-B 28F008B3-T 28F008B3-B 28F004B3-T 28F004B3-B Signed-off-by: Mattias Mattsson <vitplister(a)gmail.com> Index: flashchips.c =================================================================== --- flashchips.c (revision 1092) +++ flashchips.c (working copy) @@ -2499,10 +2499,10 @@ { .vendor = "Intel", - .name = "28F001BX-B", + .name = "28F001BN/BX-B", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, - .model_id = P28F001BXB, + .model_id = I_28F001B, .total_size = 128, .page_size = 128 * 1024, /* 8k + 2x4k + 112k */ .tested = TEST_UNTESTED, @@ -2525,10 +2525,10 @@ { .vendor = "Intel", - .name = "28F001BX-T", + .name = "28F001BN/BX-T", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, - .model_id = P28F001BXT, + .model_id = I_28F001T, .total_size = 128, .page_size = 128 * 1024, /* 112k + 2x4k + 8k */ .tested = TEST_UNTESTED, @@ -2551,10 +2551,10 @@ { .vendor = "Intel", - .name = "28F004S5", + .name = "28F008S3/S5/SC", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, - .model_id = E_28F004S5, + .model_id = I_28F004S3, .total_size = 512, .page_size = 256, .tested = TEST_UNTESTED, @@ -2574,10 +2574,10 @@ { .vendor = "Intel", - .name = "28F004BV/BE-B", + .name = "28F004B5/BE/BV/BX-B", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, - .model_id = P28F004BB, + .model_id = I_28F004B, .total_size = 512, .page_size = 128 * 1024, /* maximal block size */ .tested = TEST_UNTESTED, @@ -2601,10 +2601,10 @@ { .vendor = "Intel", - .name = "28F004BV/BE-T", + .name = "28F004B5/BE/BV/BX-T", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, - .model_id = P28F004BT, + .model_id = I_28F004T, .total_size = 512, .page_size = 128 * 1024, /* maximal block size */ .tested = TEST_UNTESTED, @@ -2628,10 +2628,10 @@ { .vendor = "Intel", - .name = "28F400BV/CV/CE-B", + .name = "28F400BV/BX/CE/CV-B", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, - .model_id = P28F400BB, + .model_id = I_28F400B, .total_size = 512, .page_size = 128 * 1024, /* maximal block size */ .feature_bits = FEATURE_ADDR_SHIFTED, @@ -2656,10 +2656,10 @@ { .vendor = "Intel", - .name = "28F400BV/CV/CE-T", + .name = "28F400BV/BX/CE/CV-T", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = INTEL_ID, - .model_id = P28F400BT, + .model_id = I_28F400T, .total_size = 512, .page_size = 128 * 1024, /* maximal block size */ .feature_bits = FEATURE_ADDR_SHIFTED, Index: flashchips.h =================================================================== --- flashchips.h (revision 1092) +++ flashchips.h (working copy) @@ -256,17 +256,45 @@ #define IM_29F004T 0xAF #define INTEL_ID 0x89 /* Intel */ +#define I_28F320J5 0x14 +#define I_28F640J5 0x15 +#define I_28F320J3 0x16 +#define I_28F640J3 0x17 +#define I_28F128J3 0x18 +#define I_28F256J3 0x1D +#define I_28F400T 0x70 /* 28F400BV/BX/CE/CV-T */ +#define I_28F400B 0x71 /* 28F400BV/BX/CE/CV-B */ +#define I_28F200T 0x74 /* 28F200BL/BV/BX/CV-T */ +#define I_28F200B 0x75 /* 28F200BL/BV/BX/CV-B */ +#define I_28F004T 0x78 /* 28F004B5/BE/BV/BX-T */ +#define I_28F004B 0x79 /* 28F004B5/BE/BV/BX-B */ +#define I_28F002T 0x7C /* 28F002BC/BL/BV/BX-T */ +#define I_28F002B 0x7D /* 28F002BL/BV/BX-B */ +#define I_28F001T 0x94 /* 28F001BN/BX-T */ +#define I_28F001B 0x95 /* 28F001BN/BX-B */ +#define I_28F008T 0x98 /* 28F008BE/BV-T */ +#define I_28F008B 0x99 /* 28F008BE/BV-B */ +#define I_28F800T 0x9C /* 28F800B5/BV/CE/CV-T */ +#define I_28F800B 0x9D /* 28F800B5/BV/CE/CV-B */ +#define I_28F016SV 0xA0 /* 28F016SA/SV */ +#define I_28F008SA 0xA2 +#define I_28F008S3 0xA6 /* 28F008S3/S5/SC */ +#define I_28F004S3 0xA7 /* 28F008S3/S5/SC */ +#define I_28F016XS 0xA8 +#define I_28F016S3 0xAA /* 28F016S3/S5/SC */ +#define I_82802AC 0xAC #define I_82802AB 0xAD -#define I_82802AC 0xAC -#define E_28F004S5 0xA7 -#define E_28F008S5 0xA6 -#define E_28F016S5 0xAA -#define P28F001BXT 0x94 /* 28F001BX-T */ -#define P28F001BXB 0x95 /* 28F001BX-B */ -#define P28F004BT 0x78 /* 28F004BV/BE-T */ -#define P28F004BB 0x79 /* 28F004BV/BE-B */ -#define P28F400BT 0x70 /* 28F400BV/CV/CE-T */ -#define P28F400BB 0x71 /* 28F400BV/CV/CE-B */ +#define I_28F010 0xB4 +#define I_28F512 0xB8 +#define I_28F256A 0xB9 +#define I_28F020 0xBD +#define I_28F016B3T 0xD0 /* 28F016B3-T */ +#define I_28F016B3B 0xD1 /* 28F016B3-B */ +#define I_28F008B3T 0xD2 /* 28F008B3-T */ +#define I_28F008B3B 0xD3 /* 28F008B3-B */ +#define I_28F004B3T 0xD4 /* 28F004B3-T */ +#define I_28F004B3B 0xD5 /* 28F004B3-B */ + #define SHARP_LH28F008SA 0xA2 /* Sharp chip, Intel Vendor ID */ #define SHARP_LH28F008SC 0xA6 /* Sharp chip, Intel Vendor ID */

1 0

Problem with FLASHROM, results in error while updating BIOS. Please help me urgently..
by Ajay Pai P: 21 Jul '10

21 Jul '10

Dear Sir, I had troubles in booting my system (ASUS A8N-Vm motherboard with AMI BIOS) ie. it would boot only every alternate times. So the first time I boot it, the motherboard seems to run fine (with all the necessary lights on and the cpu fan running) however there is no output on my monitor and the monitor power led simply keeps blinking. All I have to do is shut it down once by pressing the Power off/on button for long and then again switch on after which it boots simply fine. It doesnt seem to be because of cold start because even if i switch off my system after keeping it on for a long time, and try to boot it immediately, I have to again follow this procedure.I got my monitor tested and its fine. So i doubt my BIOS now. I tried updating it with Flashrom as follows and it results in error: $ sudo flashrom -w /media/BACKUP/Backups/OS\ backups/windows/A8N-VM-ASUS-0902.ROM flashrom v0.9.2-r1001 on Linux 2.6.31-ARCH (x86_64), built with libpci 3.1.7, GCC 4.5.0 20100520 (prerelease) flashrom is free software, get the source code at http://www.flashrom.org No coreboot table found. Found chipset "NVIDIA MCP51", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash chip... ERASE FAILED at 0x00000008! Expected=0xff, Read=0x90, failed byte count from 0x00000000-0x00000fff: 0xfe7 ERASE FAILED! ERASE FAILED at 0x00000008! Expected=0xff, Read=0x90, failed byte count from 0x00000000-0x0000ffff: 0xfefe ERASE FAILED! FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! Now I am not able to decide what is to be done. I am not sure if I ran the commands properly or if the BIOS chip is fine or not. I hereby request you to please guide me and help me overcome this problem and get my PC running fine. I shall be looking forward to your reply with crossed fingers. Thanking you in advance. -- Regards.... Ajay Pai P

2 1

Flashrom output
by Marco Schröder 21 Jul '10

21 Jul '10

Hello Gys, I`m so sorry but my english ist not perfect. I will send the output of flashrom -V for my Bios. Chipset: MCP61 Manufakter: ECS GeForce6100SM-M2 On the external Part of this email i have included two PDF: once of the Motherboard and once of the flashrom output. Thanks Best regards -- Two non-text attachments have been stripped from this message: GeForce6100SM-M2_V1.0A.pdf flashrom-output.pdf

2 1

Re: [flashrom] [coreboot] SPI in-system programming
by Carl-Daniel Hailfinger 19 Jul '10

19 Jul '10

Hi Corey, [adding flashrom(a)flashrom.org to CC] On 18.07.2010 11:54, Corey Osgood wrote: > I need a way that I can test images without actually being in the same > location as the board I'll be testing them on. What would you guys > recommend for programming an SPI chip with it still on the > motherboard? flashrom. > There is no ISP header, and the flash chip is socketed, > the board will be a Zotac Atom/NM10 ITX board. You could stack two SPI chips easily, and switch the CS# pin. > I've seen programmers > that explain how to isolate the signals so their programmer can be > used to do it, but does it require a special programmer, or is it > something that could be done with a $20 ebay programmer and a little > wire? And can the board be operated with the programmer still > attached? I'm getting a lot of conflicting info, hoping someone can > clarify this. > If you want to reflash with an external programmer, it gets complicated really fast. Reflashing a chip which is connected to a running system is extremely risky, and you may fry your board. One way around that is to hook some buffer in between, but you'd need one which is fast enough for 33 MHz operation (and you want a safety margin to not disturb communication, so shooting for one with a delay around 10 ns is a good idea), and then electrically disconnect the flash chip from the board while flashing. Maybe flashing a chip in a powered down system with an external programmer works, but you can't be sure if the external programmer has enough power to feed 3.3V to the whole board (if the flash chip is connected there) and you may see undesirable side effects as well. > If this doesn't work out, how can I flip back and forth between a pair > of SPI chips? > Switching the CS# pin should do the trick. Regards, Carl-Daniel -- http://www.hailfinger.org/

5 5

flashrom on iMac4,1
by Mattias Mattsson 19 Jul '10

19 Jul '10

Hi, I ran latest flashrom (r1092) on an Intel iMac4,1. Probe, read, verify works. Write/Erase fails (nothing is erased or written). Logs attached. -mattias

1 0

[PATCH] Winbond chip id fix-up
by Mattias Mattsson 19 Jul '10

19 Jul '10

Kill incorrect ASD chip and vendor id. Group Winbond SPI and Parallell chips separately (they have different vendor ids). Change constant names to the "canonical" chip name for the following ids: W_29C020C (0x45) -> W_29C020 (Same as W29C020C, W29C022 and ASD AE29F2008) W_29C040P (0x46) -> W_29C040 ("P" is for package type [32-pin PLCC], irrelevant) W_29C011 + W_29EE011 (0xC1) -> W_29C010M (Same as W29C011A, W29EE011, W29EE012, and ASD AE29F1008) Also add ids for the following Winbond chips: W25Q40 W25Q128 W19B160BB W19B160BT W19B320SB/W19L320SB W19B320ST/W19L320ST W19B322MB W19B322MT W19B323MB W19B323MT W19B324MB W19B324MT W29C512A/W29EE512 W39L010 W39L040A W39L512 W49F002/W49F002B Signed-off-by: Mattias Mattsson <vitplister(a)gmail.com> Index: flashchips.c =================================================================== --- flashchips.c (revision 1091) +++ flashchips.c (working copy) @@ -275,37 +275,6 @@ }, { - .vendor = "ASD", - .name = "AE49F2008", - .bustype = CHIP_BUSTYPE_PARALLEL, - .manufacture_id = ASD_ID, - .model_id = ASD_AE49F2008, - .total_size = 256, - .page_size = 128, - .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_UNTESTED, - .probe = probe_jedec, - .probe_timing = TIMING_FIXME, - .block_erasers = - { - { - .eraseblocks = { - {128 * 1024, 1}, - {96 * 1024, 1}, - {8 * 1024, 2}, - {16 * 1024, 1}, - }, - .block_erase = erase_sector_jedec, - }, { - .eraseblocks = { {256 * 1024, 1} }, - .block_erase = erase_chip_block_jedec, - } - }, - .write = write_jedec, - .read = read_memmapped, - }, - - { .vendor = "Atmel", .name = "AT25DF021", .bustype = CHIP_BUSTYPE_SPI, @@ -6249,7 +6218,7 @@ .name = "W29C011", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = WINBOND_ID, - .model_id = W_29C011, + .model_id = W_29C010M, .total_size = 128, .page_size = 128, .feature_bits = FEATURE_LONG_RESET, @@ -6272,7 +6241,7 @@ .name = "W29C020C", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = WINBOND_ID, - .model_id = W_29C020C, + .model_id = W_29C020, .total_size = 256, .page_size = 128, .feature_bits = FEATURE_LONG_RESET, @@ -6295,7 +6264,7 @@ .name = "W29C040P", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = WINBOND_ID, - .model_id = W_29C040P, + .model_id = W_29C040, .total_size = 512, .page_size = 256, .feature_bits = FEATURE_LONG_RESET, @@ -6318,7 +6287,7 @@ .name = "W29EE011", .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = WINBOND_ID, - .model_id = W_29C011, + .model_id = W_29C010M, .total_size = 128, .page_size = 128, .feature_bits = FEATURE_LONG_RESET, Index: flashchips.h =================================================================== --- flashchips.h (revision 1091) +++ flashchips.h (working copy) @@ -91,10 +91,6 @@ #define AMIC_A29L040 0x92 #define AMIC_A49LF040A 0x9d -/* This chip vendor/device ID is probably a misinterpreted LHA header. */ -#define ASD_ID 0x25 /* ASD, not listed in JEP106W */ -#define ASD_AE49F2008 0x52 - #define ATMEL_ID 0x1F /* Atmel */ #define AT_25DF021 0x4300 #define AT_25DF041A 0x4401 @@ -501,7 +497,6 @@ * W25X chips are SPI, first byte of device ID is memory type, second * byte of device ID is related to log(bitsize). */ -#define WINBOND_ID 0xDA /* Winbond */ #define WINBOND_NEX_ID 0xEF /* Winbond (ex Nexcom) serial flashes */ #define W_25X10 0x3011 #define W_25X20 0x3012 @@ -510,26 +505,44 @@ #define W_25X16 0x3015 #define W_25X32 0x3016 #define W_25X64 0x3017 +#define W_25Q40 0x4013 #define W_25Q80 0x4014 #define W_25Q16 0x4015 #define W_25Q32 0x4016 #define W_25Q64 0x4017 -#define W_29C011 0xC1 -#define W_29C020C 0x45 /* Same as W29C020 and ASD AE29F2008 */ -#define W_29C040P 0x46 /* Same as W29C040 */ -#define W_29EE011 0xC1 -#define W_39L020 0xB5 -#define W_39L040 0xB6 -#define W_39V040FA 0x34 -#define W_39V040A 0x3D -#define W_39V040B 0x54 -#define W_39V040C 0x50 -#define W_39V080A 0xD0 -#define W_39V080FA 0xD3 -#define W_39V080FA_DM 0x93 -#define W_49F002U 0x0B -#define W_49F020 0x8C -#define W_49V002A 0xB0 -#define W_49V002FA 0x32 +#define W_25Q128 0x4018 +#define WINBOND_ID 0xDA /* Winbond */ +#define W_19B160BB 0x49 +#define W_19B160BT 0xC4 +#define W_19B320SB 0x2A /* Same as W19L320SB */ +#define W_19B320ST 0xBA /* Same as W19L320ST */ +#define W_19B322MB 0x92 +#define W_19B322MT 0x10 +#define W_19B323MB 0x94 +#define W_19B323MT 0x13 +#define W_19B324MB 0x97 +#define W_19B324MT 0x16 +#define W_29C010 0xC1 /* Same as W29C010M, W29C011A, W29EE011, W29EE012, and ASD AE29F1008 */ +#define W_29C020 0x45 /* Same as W29C020C, W29C022 and ASD AE29F2008 */ +#define W_29C040 0x46 /* Same as W29C040P */ +#define W_29C512A 0xC8 /* Same as W29EE512 */ +#define W_39L010 0x31 +#define W_39L020 0xB5 +#define W_39L040 0xB6 +#define W_39L040A 0xD6 +#define W_39L512 0x38 +#define W_39V040A 0x3D +#define W_39V040FA 0x34 +#define W_39V040B 0x54 /* Same as W39V040FB */ +#define W_39V040C 0x50 /* Same as W39V040FC */ +#define W_39V080A 0xD0 +#define W_39V080FA 0xD3 +#define W_39V080FA_DM 0x93 /* W39V080FA dual mode */ +#define W_49F002 0x25 /* Same as W49F002B */ +#define W_49F002U 0x0B /* Same as W49F002N and ASD AE49F2008 */ +#define W_49F020 0x8C +#define W_49V002A 0xB0 +#define W_49V002FA 0x32 + #endif /* !FLASHCHIPS_H */

1 1

[PATCH] kill central list of SPI programmers
by Michael Karcher 18 Jul '10

18 Jul '10

This version really compiles. Forgot the forward declaration after moving code initially. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- buspirate_spi.c | 18 +++++++-- dediprog.c | 15 ++++++- dummyflasher.c | 18 +++++++-- flash.h | 49 ++--------------------- flashrom.c | 4 -- ft2232_spi.c | 11 +++++- ichspi.c | 59 ++++++++++++++++++++-------- it87spi.c | 18 +++++++-- sb600spi.c | 17 ++++++-- spi.c | 115 +++++-------------------------------------------------- spi25.c | 4 +- wbsio_spi.c | 16 ++++++- 12 files changed, 149 insertions(+), 195 deletions(-) diff --git a/buspirate_spi.c b/buspirate_spi.c index 55e71c2..36eaa9a 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -44,6 +44,8 @@ static int buspirate_serialport_setup(char *dev) #define sp_flush_incoming(...) 0 #endif +static const struct spi_programmer spi_programmer_buspirate; + static int buspirate_sendrecv(unsigned char *buf, unsigned int writecnt, unsigned int readcnt) { int i, ret = 0; @@ -210,7 +212,7 @@ int buspirate_spi_init(void) } buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_BUSPIRATE; + spi_programmer = &spi_programmer_buspirate; return 0; } @@ -250,7 +252,7 @@ int buspirate_spi_shutdown(void) return 0; } -int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { static unsigned char *buf = NULL; @@ -304,12 +306,20 @@ int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, return ret; } -int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { return spi_read_chunked(flash, buf, start, len, 12); } -int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +static int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { return spi_write_chunked(flash, buf, start, len, 12); } + +static const struct spi_programmer spi_programmer_buspirate = { + .type = SPI_CONTROLLER_BUSPIRATE, + .command = buspirate_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = buspirate_spi_read, + .write_256 = buspirate_spi_write_256, +}; diff --git a/dediprog.c b/dediprog.c index 0b92983..c21c801 100644 --- a/dediprog.c +++ b/dediprog.c @@ -25,6 +25,7 @@ #define DEFAULT_TIMEOUT 3000 static usb_dev_handle *dediprog_handle; +static const struct spi_programmer spi_programmer_dediprog; #if 0 /* Might be useful for other pieces of code as well. */ @@ -145,14 +146,14 @@ static int dediprog_set_spi_speed(uint16_t speed) } #endif -int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { msg_pspew("%s, start=0x%x, len=0x%x\n", __func__, start, len); /* Chosen read length is 16 bytes for now. */ return spi_read_chunked(flash, buf, start, len, 16); } -int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int ret; @@ -318,7 +319,7 @@ int dediprog_init(void) return 1; buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_DEDIPROG; + spi_programmer = &spi_programmer_dediprog; /* RE leftover, leave in until the driver is complete. */ #if 0 @@ -394,3 +395,11 @@ int dediprog_shutdown(void) } return 0; } + +static const struct spi_programmer spi_programmer_dediprog = { + .type = SPI_CONTROLLER_DEDIPROG, + .command = dediprog_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = dediprog_spi_read, + .write_256 = spi_chip_write_1_new, +}; diff --git a/dummyflasher.c b/dummyflasher.c index 241dcee..b1bbcf2 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -25,6 +25,8 @@ #include "flash.h" #include "chipdrivers.h" +static const struct spi_programmer spi_programmer_dummy; + static void tolower_string(char *str) { for (; *str != '\0'; str++) @@ -59,7 +61,7 @@ int dummy_init(void) } if (strstr(bustext, "spi")) { buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_DUMMY; + spi_programmer = &spi_programmer_dummy; msg_pdbg("Enabling support for %s flash.\n", "SPI"); } if (buses_supported == CHIP_BUSTYPE_NONE) @@ -140,7 +142,7 @@ void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len) return; } -int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; @@ -161,7 +163,7 @@ int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, return 0; } -int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { /* Maximum read length is unlimited, use 64kB. */ return spi_read_chunked(flash, buf, start, len, 64 * 1024); @@ -171,7 +173,15 @@ int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) * never be successful, and the current frontend refuses to write in that case. * Other frontends may allow writing even for non-detected chips, though. */ -int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { return spi_write_chunked(flash, buf, start, len, 256); } + +static const struct spi_programmer spi_programmer_dummy = { + .type = SPI_CONTROLLER_DUMMY, + .command = dummy_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = dummy_spi_read, + .write_256 = dummy_spi_write_256, +}; diff --git a/flash.h b/flash.h index 8ebea29..fb06207 100644 --- a/flash.h +++ b/flash.h @@ -452,10 +452,6 @@ uint8_t dummy_chip_readb(const chipaddr addr); uint16_t dummy_chip_readw(const chipaddr addr); uint32_t dummy_chip_readl(const chipaddr addr); void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); -int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); #endif /* nic3com.c */ @@ -527,9 +523,6 @@ extern const struct pcidev_status ata_hpt[]; #define FTDI_FT2232H 0x6010 #define FTDI_FT4232H 0x6011 int ft2232_spi_init(void); -int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* bitbang_spi.c */ int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod); @@ -544,15 +537,10 @@ struct buspirate_spispeeds { }; int buspirate_spi_init(void); int buspirate_spi_shutdown(void); -int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* dediprog.c */ int dediprog_init(void); int dediprog_shutdown(void); -int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); /* flashrom.c */ enum write_granularity { @@ -627,32 +615,18 @@ int handle_romentries(uint8_t *buffer, struct flashchip *flash); /* spi.c */ enum spi_controller { - SPI_CONTROLLER_NONE, -#if CONFIG_INTERNAL == 1 -#if defined(__i386__) || defined(__x86_64__) SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, SPI_CONTROLLER_IT87XX, SPI_CONTROLLER_SB600, SPI_CONTROLLER_VIA, SPI_CONTROLLER_WBSIO, -#endif -#endif -#if CONFIG_FT2232_SPI == 1 SPI_CONTROLLER_FT2232, -#endif -#if CONFIG_DUMMY == 1 SPI_CONTROLLER_DUMMY, -#endif -#if CONFIG_BUSPIRATE_SPI == 1 SPI_CONTROLLER_BUSPIRATE, -#endif -#if CONFIG_DEDIPROG == 1 SPI_CONTROLLER_DEDIPROG, -#endif - SPI_CONTROLLER_INVALID /* This must always be the last entry. */ }; -extern const int spi_programmer_count; + struct spi_command { unsigned int writecnt; unsigned int readcnt; @@ -660,6 +634,7 @@ struct spi_command { unsigned char *readarr; }; struct spi_programmer { + enum spi_controller type; int (*command)(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int (*multicommand)(struct spi_command *cmds); @@ -669,8 +644,8 @@ struct spi_programmer { int (*write_256)(struct flashchip *flash, uint8_t *buf, int start, int len); }; -extern enum spi_controller spi_controller; -extern const struct spi_programmer spi_programmer[]; +const struct spi_programmer *spi_programmer; + int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int spi_send_multicommand(struct spi_command *cmds); @@ -684,11 +659,6 @@ extern uint32_t ichspi_bbar; void ich_init_spi(struct pci_dev *dev, uint32_t base, void * rcrb, int ich_generation); int via_init_spi(struct pci_dev * dev); -int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len); -int ich_spi_send_multicommand(struct spi_command *cmds); /* it87spi.c */ void enter_conf_mode_ite(uint16_t port); @@ -696,23 +666,12 @@ void exit_conf_mode_ite(uint16_t port); struct superio probe_superio_ite(void); int init_superio_ite(void); int it87spi_init(void); -int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* sb600spi.c */ void sb600_probe_spi(struct pci_dev * dev); -int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* wbsio_spi.c */ int wbsio_check_for_spi(void); -int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); /* serprog.c */ int serprog_init(void); diff --git a/flashrom.c b/flashrom.c index fe173a7..dc262d5 100644 --- a/flashrom.c +++ b/flashrom.c @@ -1354,10 +1354,6 @@ int selfcheck(void) msg_gerr("Programmer table miscompilation!\n"); ret = 1; } - if (spi_programmer_count - 1 != SPI_CONTROLLER_INVALID) { - msg_gerr("SPI programmer table miscompilation!\n"); - ret = 1; - } for (flash = flashchips; flash && flash->name; flash++) if (selfcheck_eraseblocks(flash)) ret = 1; diff --git a/ft2232_spi.c b/ft2232_spi.c index c8711e9..b45ba42 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -45,6 +45,7 @@ #define BITMODE_BITBANG_NORMAL 1 #define BITMODE_BITBANG_SPI 2 +static const struct spi_programmer spi_programmer_ft2232; static struct ftdi_context ftdic_context; static int send_buf(struct ftdi_context *ftdic, const unsigned char *buf, int size) @@ -192,7 +193,7 @@ int ft2232_spi_init(void) // msg_pdbg("\nft2232 chosen\n"); buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_FT2232; + spi_programmer = &spi_programmer_ft2232; return 0; } @@ -293,4 +294,12 @@ int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int l return spi_write_chunked(flash, buf, start, len, 256); } +static const struct spi_programmer spi_programmer_ft2232 = { + .type = SPI_CONTROLLER_FT2232, + .command = ft2232_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = ft2232_spi_read, + .write_256 = ft2232_spi_write_256, +}; + #endif diff --git a/ichspi.c b/ichspi.c index 246f3ae..ae9a5f4 100644 --- a/ichspi.c +++ b/ichspi.c @@ -106,6 +106,9 @@ static int ichspi_lock = 0; uint32_t ichspi_bbar = 0; static void *ich_spibar = NULL; +static const struct spi_programmer spi_programmer_ich7; +static const struct spi_programmer spi_programmer_ich9; +static const struct spi_programmer spi_programmer_via; typedef struct _OPCODE { uint8_t opcode; //This commands spi opcode @@ -234,7 +237,7 @@ static int generate_opcodes(OPCODES * op) return -1; } - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: preop = REGREAD16(ICH7_REG_PREOP); @@ -309,7 +312,7 @@ int program_opcodes(OPCODES * op) } msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: REGWRITE16(ICH7_REG_PREOP, preop); @@ -337,7 +340,7 @@ int program_opcodes(OPCODES * op) */ void ich_set_bbar(uint32_t minaddr) { - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: mmio_writel(minaddr, ich_spibar + 0x50); ichspi_bbar = mmio_readl(ich_spibar + 0x50); @@ -448,19 +451,19 @@ void ich_init_spi(struct pci_dev *dev, uint32_t base, void * rcrb, switch (ich_generation) { case 7: buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_ICH7; + spi_programmer = &spi_programmer_ich7; spibar_offset = 0x3020; break; case 8: buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_ICH9; + spi_programmer = &spi_programmer_ich9; spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_ICH9; + spi_programmer = &spi_programmer_ich9; spibar_offset = 0x3800; break; } @@ -471,7 +474,7 @@ void ich_init_spi(struct pci_dev *dev, uint32_t base, void * rcrb, /* Assign Virtual Address */ ich_spibar = rcrb + spibar_offset; - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); @@ -600,7 +603,7 @@ int via_init_spi(struct pci_dev * dev) /* Not sure if it speaks all these bus protocols. */ buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_VIA; + spi_programmer = &spi_programmer_via; ich_init_opcodes(); return 0; @@ -848,7 +851,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, static int run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data) { - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_VIA: if (datalength > 16) { msg_perr("%s: Internal command size error for " @@ -881,27 +884,27 @@ static int run_opcode(OPCODE op, uint32_t offset, return -1; } -int ich_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) +static int ich_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) { int maxdata = 64; - if (spi_controller == SPI_CONTROLLER_VIA) + if (spi_programmer->type == SPI_CONTROLLER_VIA) maxdata = 16; return spi_read_chunked(flash, buf, start, len, maxdata); } -int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len) +static int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len) { int maxdata = 64; - if (spi_controller == SPI_CONTROLLER_VIA) + if (spi_programmer->type == SPI_CONTROLLER_VIA) maxdata = 16; return spi_write_chunked(flash, buf, start, len, maxdata); } -int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int result; @@ -966,7 +969,7 @@ int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { addr = (writearr[1] << 16) | (writearr[2] << 8) | (writearr[3] << 0); - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_ICH9: if (addr < ichspi_bbar) { @@ -1001,7 +1004,7 @@ int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, return result; } -int ich_spi_send_multicommand(struct spi_command *cmds) +static int ich_spi_send_multicommand(struct spi_command *cmds) { int ret = 0; int i; @@ -1071,4 +1074,28 @@ int ich_spi_send_multicommand(struct spi_command *cmds) return ret; } +static const struct spi_programmer spi_programmer_ich7 = { + .type = SPI_CONTROLLER_ICH7, + .command = ich_spi_send_command, + .multicommand = ich_spi_send_multicommand, + .read = ich_spi_read, + .write_256 = ich_spi_write_256, +}; + +static const struct spi_programmer spi_programmer_ich9 = { + .type = SPI_CONTROLLER_ICH9, + .command = ich_spi_send_command, + .multicommand = ich_spi_send_multicommand, + .read = ich_spi_read, + .write_256 = ich_spi_write_256, +}; + +static const struct spi_programmer spi_programmer_via = { + .type = SPI_CONTROLLER_VIA, + .command = ich_spi_send_command, + .multicommand = ich_spi_send_multicommand, + .read = ich_spi_read, + .write_256 = ich_spi_write_256, +}; + #endif diff --git a/it87spi.c b/it87spi.c index cf3d3b9..dddb5a9 100644 --- a/it87spi.c +++ b/it87spi.c @@ -34,6 +34,8 @@ #define ITE_SUPERIO_PORT1 0x2e #define ITE_SUPERIO_PORT2 0x4e +static const struct spi_programmer spi_programmer_it87xx; + uint16_t it8716f_flashport = 0; /* use fast 33MHz SPI (<>0) or slow 16MHz (0) */ static int fast_spi = 1; @@ -175,7 +177,7 @@ static uint16_t it87spi_probe(uint16_t port) it8716f_flashport = flashport; if (buses_supported & CHIP_BUSTYPE_SPI) msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); - spi_controller = SPI_CONTROLLER_IT87XX; + spi_programmer = &spi_programmer_it87xx; buses_supported |= CHIP_BUSTYPE_SPI; return 0; } @@ -227,7 +229,7 @@ int it87spi_init(void) * commands with the address in inverse wire order. That's why the register * ordering in case 4 and 5 may seem strange. */ -int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { uint8_t busy, writeenc; @@ -320,7 +322,7 @@ static int it8716f_spi_page_program(struct flashchip *flash, uint8_t *buf, int s * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles * Need to read this big flash using firmware cycles 3 byte at a time. */ -int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) { int total_size = 1024 * flash->total_size; fast_spi = 0; @@ -334,7 +336,7 @@ int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int return 0; } -int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +static int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { /* * IT8716F only allows maximum of 512 kb SPI chip size for memory @@ -371,4 +373,12 @@ int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, return 0; } +static const struct spi_programmer spi_programmer_it87xx = { + .type = SPI_CONTROLLER_IT87XX, + .command = it8716f_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = it8716f_spi_chip_read, + .write_256 = it8716f_spi_chip_write_256, +}; + #endif diff --git a/sb600spi.c b/sb600spi.c index e42b20b..866e309 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -41,6 +41,7 @@ */ static uint8_t *sb600_spibar = NULL; +static const struct spi_programmer spi_programmer_sb600; void sb600_probe_spi(struct pci_dev * dev) { @@ -114,16 +115,16 @@ void sb600_probe_spi(struct pci_dev * dev) return; buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_SB600; + spi_programmer = &spi_programmer_sb600; } -int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { /* Maximum read length is 8 bytes. */ return spi_read_chunked(flash, buf, start, len, 8); } -int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +static int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { return spi_write_chunked(flash, buf, start, len, 5); } @@ -144,7 +145,7 @@ static void execute_command(void) ; } -int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int count; @@ -227,4 +228,12 @@ int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, return 0; } +static const struct spi_programmer spi_programmer_sb600 = { + .type = SPI_CONTROLLER_SB600, + .command = sb600_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = sb600_spi_read, + .write_256 = sb600_spi_write_256, +}; + #endif diff --git a/spi.c b/spi.c index 2b64463..dc4da9f 100644 --- a/spi.c +++ b/spi.c @@ -27,129 +27,34 @@ #include "chipdrivers.h" #include "spi.h" -enum spi_controller spi_controller = SPI_CONTROLLER_NONE; - void spi_prettyprint_status_register(struct flashchip *flash); -const struct spi_programmer spi_programmer[] = { - { /* SPI_CONTROLLER_NONE */ - .command = NULL, - .multicommand = NULL, - .read = NULL, - .write_256 = NULL, - }, - -#if CONFIG_INTERNAL == 1 -#if defined(__i386__) || defined(__x86_64__) - { /* SPI_CONTROLLER_ICH7 */ - .command = ich_spi_send_command, - .multicommand = ich_spi_send_multicommand, - .read = ich_spi_read, - .write_256 = ich_spi_write_256, - }, - - { /* SPI_CONTROLLER_ICH9 */ - .command = ich_spi_send_command, - .multicommand = ich_spi_send_multicommand, - .read = ich_spi_read, - .write_256 = ich_spi_write_256, - }, - - { /* SPI_CONTROLLER_IT87XX */ - .command = it8716f_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = it8716f_spi_chip_read, - .write_256 = it8716f_spi_chip_write_256, - }, - - { /* SPI_CONTROLLER_SB600 */ - .command = sb600_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = sb600_spi_read, - .write_256 = sb600_spi_write_256, - }, - - { /* SPI_CONTROLLER_VIA */ - .command = ich_spi_send_command, - .multicommand = ich_spi_send_multicommand, - .read = ich_spi_read, - .write_256 = ich_spi_write_256, - }, - - { /* SPI_CONTROLLER_WBSIO */ - .command = wbsio_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = wbsio_spi_read, - .write_256 = spi_chip_write_1_new, - }, -#endif -#endif - -#if CONFIG_FT2232_SPI == 1 - { /* SPI_CONTROLLER_FT2232 */ - .command = ft2232_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = ft2232_spi_read, - .write_256 = ft2232_spi_write_256, - }, -#endif - -#if CONFIG_DUMMY == 1 - { /* SPI_CONTROLLER_DUMMY */ - .command = dummy_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = dummy_spi_read, - .write_256 = dummy_spi_write_256, - }, -#endif - -#if CONFIG_BUSPIRATE_SPI == 1 - { /* SPI_CONTROLLER_BUSPIRATE */ - .command = buspirate_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = buspirate_spi_read, - .write_256 = buspirate_spi_write_256, - }, -#endif - -#if CONFIG_DEDIPROG == 1 - { /* SPI_CONTROLLER_DEDIPROG */ - .command = dediprog_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = dediprog_spi_read, - .write_256 = spi_chip_write_1_new, - }, -#endif - - {}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */ -}; - -const int spi_programmer_count = ARRAY_SIZE(spi_programmer); +const struct spi_programmer *spi_programmer; int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { - if (!spi_programmer[spi_controller].command) { + if (!spi_programmer->command) { msg_perr("%s called, but SPI is unsupported on this " "hardware. Please report a bug at " "flashrom(a)flashrom.org\n", __func__); return 1; } - return spi_programmer[spi_controller].command(writecnt, readcnt, + return spi_programmer->command(writecnt, readcnt, writearr, readarr); } int spi_send_multicommand(struct spi_command *cmds) { - if (!spi_programmer[spi_controller].multicommand) { + if (!spi_programmer->multicommand) { msg_perr("%s called, but SPI is unsupported on this " "hardware. Please report a bug at " "flashrom(a)flashrom.org\n", __func__); return 1; } - return spi_programmer[spi_controller].multicommand(cmds); + return spi_programmer->multicommand(cmds); } int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, @@ -183,14 +88,14 @@ int default_spi_send_multicommand(struct spi_command *cmds) int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) { - if (!spi_programmer[spi_controller].read) { + if (!spi_programmer->read) { msg_perr("%s called, but SPI read is unsupported on this " "hardware. Please report a bug at " "flashrom(a)flashrom.org\n", __func__); return 1; } - return spi_programmer[spi_controller].read(flash, buf, start, len); + return spi_programmer->read(flash, buf, start, len); } /* @@ -202,14 +107,14 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) /* real chunksize is up to 256, logical chunksize is 256 */ int spi_chip_write_256_new(struct flashchip *flash, uint8_t *buf, int start, int len) { - if (!spi_programmer[spi_controller].write_256) { + if (!spi_programmer->write_256) { msg_perr("%s called, but SPI page write is unsupported on this " "hardware. Please report a bug at " "flashrom(a)flashrom.org\n", __func__); return 1; } - return spi_programmer[spi_controller].write_256(flash, buf, start, len); + return spi_programmer->write_256(flash, buf, start, len); } /* Wrapper function until the generic code is converted to partial writes. */ @@ -239,7 +144,7 @@ int spi_chip_write_256(struct flashchip *flash, uint8_t *buf) */ uint32_t spi_get_valid_read_addr(void) { - switch (spi_controller) { + switch (spi_programmer->type) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_ICH7: diff --git a/spi25.c b/spi25.c index 32bb73c..d9dae35 100644 --- a/spi25.c +++ b/spi25.c @@ -177,7 +177,7 @@ int probe_spi_rdid4(struct flashchip *flash) /* Some SPI controllers do not support commands with writecnt=1 and * readcnt=4. */ - switch (spi_controller) { + switch (spi_programmer->type) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_IT87XX: @@ -1019,7 +1019,7 @@ int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len) .readarr = NULL, }}; - switch (spi_controller) { + switch (spi_programmer->type) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_IT87XX: diff --git a/wbsio_spi.c b/wbsio_spi.c index b8f8b38..6288340 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -28,6 +28,7 @@ #define WBSIO_PORT2 0x4e static uint16_t wbsio_spibase = 0; +static const struct spi_programmer spi_programmer_wbsio; static uint16_t wbsio_get_spibase(uint16_t port) { @@ -68,7 +69,7 @@ int wbsio_check_for_spi(void) msg_pspew("\nwbsio_spibase = 0x%x\n", wbsio_spibase); buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_WBSIO; + spi_programmer = &spi_programmer_wbsio; msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " "1024 KB!\n", __func__); max_rom_decode.spi = 1024 * 1024; @@ -96,7 +97,7 @@ int wbsio_check_for_spi(void) * Would one more byte of RAM in the chip (to get all 24 bits) really make * such a big difference? */ -int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; @@ -180,9 +181,18 @@ int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, return 0; } -int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { return read_memmapped(flash, buf, start, len); } +static const struct spi_programmer spi_programmer_wbsio = { + .type = SPI_CONTROLLER_WBSIO, + .command = wbsio_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = wbsio_spi_read, + .write_256 = spi_chip_write_1_new, +}; + + #endif -- 1.7.1

1 0

[PATCH] Safety checks for SPI bitbang init
by Carl-Daniel Hailfinger 18 Jul '10

18 Jul '10

Check during SPI bitbang init that SPI bitbang master configuration is correct. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-bitbang_spi_init_errorcheck/flash.h =================================================================== --- flashrom-bitbang_spi_init_errorcheck/flash.h (Revision 1091) +++ flashrom-bitbang_spi_init_errorcheck/flash.h (Arbeitskopie) @@ -128,7 +128,7 @@ void programmer_delay(int usecs); enum bitbang_spi_master_type { - BITBANG_SPI_DUMMY /* remove as soon as there is a real entry */ + BITBANG_SPI_INVALID = 0, /* This must always be the first entry. */ }; struct bitbang_spi_master { Index: flashrom-bitbang_spi_init_errorcheck/bitbang_spi.c =================================================================== --- flashrom-bitbang_spi_init_errorcheck/bitbang_spi.c (Revision 1091) +++ flashrom-bitbang_spi_init_errorcheck/bitbang_spi.c (Arbeitskopie) @@ -54,6 +54,16 @@ int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod) { + /* BITBANG_SPI_INVALID is 0, so if someone forgot to initialize ->type, + * we catch it here. Same goes for missing initialization of bitbanging + * functions. + */ + if (!master || master->type == BITBANG_SPI_INVALID || !master->set_cs || + !master->set_sck || !master->set_mosi || !master->get_miso) { + msg_perr("Incomplete bitbanging SPI master setting! Please " + "report a bug at flashrom(a)flashrom.org\n"); + return 1; + } bitbang_spi_master = master; bitbang_spi_half_period = halfperiod; -- http://www.hailfinger.org/

2 2

[commit] r1092 - trunk
by repository service 18 Jul '10

18 Jul '10

Author: hailfinger Date: Sun Jul 18 16:42:28 2010 New Revision: 1092 URL: http://flashrom.org/trac/coreboot/changeset/1092 Log: Check during SPI bitbang init that SPI bitbang master configuration is correct. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/bitbang_spi.c trunk/flash.h Modified: trunk/bitbang_spi.c ============================================================================== --- trunk/bitbang_spi.c Sun Jul 18 01:27:47 2010 (r1091) +++ trunk/bitbang_spi.c Sun Jul 18 16:42:28 2010 (r1092) @@ -54,6 +54,16 @@ int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod) { + /* BITBANG_SPI_INVALID is 0, so if someone forgot to initialize ->type, + * we catch it here. Same goes for missing initialization of bitbanging + * functions. + */ + if (!master || master->type == BITBANG_SPI_INVALID || !master->set_cs || + !master->set_sck || !master->set_mosi || !master->get_miso) { + msg_perr("Incomplete bitbanging SPI master setting! Please " + "report a bug at flashrom(a)flashrom.org\n"); + return 1; + } bitbang_spi_master = master; bitbang_spi_half_period = halfperiod; Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Sun Jul 18 01:27:47 2010 (r1091) +++ trunk/flash.h Sun Jul 18 16:42:28 2010 (r1092) @@ -128,7 +128,7 @@ void programmer_delay(int usecs); enum bitbang_spi_master_type { - BITBANG_SPI_DUMMY /* remove as soon as there is a real entry */ + BITBANG_SPI_INVALID = 0, /* This must always be the first entry. */ }; struct bitbang_spi_master {

1 0

[PATCH 3/3] kill central list of SPI programmers
by Michael Karcher 18 Jul '10

18 Jul '10

Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- buspirate_spi.c | 18 +++++++-- dediprog.c | 15 ++++++- dummyflasher.c | 18 +++++++-- flash.h | 49 ++--------------------- flashrom.c | 4 -- ft2232_spi.c | 11 +++++- ichspi.c | 56 +++++++++++++++++++-------- it87spi.c | 18 +++++++-- sb600spi.c | 17 ++++++-- spi.c | 115 +++++-------------------------------------------------- spi25.c | 4 +- wbsio_spi.c | 16 ++++++- 12 files changed, 146 insertions(+), 195 deletions(-) diff --git a/buspirate_spi.c b/buspirate_spi.c index 55e71c2..36eaa9a 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -44,6 +44,8 @@ static int buspirate_serialport_setup(char *dev) #define sp_flush_incoming(...) 0 #endif +static const struct spi_programmer spi_programmer_buspirate; + static int buspirate_sendrecv(unsigned char *buf, unsigned int writecnt, unsigned int readcnt) { int i, ret = 0; @@ -210,7 +212,7 @@ int buspirate_spi_init(void) } buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_BUSPIRATE; + spi_programmer = &spi_programmer_buspirate; return 0; } @@ -250,7 +252,7 @@ int buspirate_spi_shutdown(void) return 0; } -int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { static unsigned char *buf = NULL; @@ -304,12 +306,20 @@ int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, return ret; } -int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { return spi_read_chunked(flash, buf, start, len, 12); } -int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +static int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { return spi_write_chunked(flash, buf, start, len, 12); } + +static const struct spi_programmer spi_programmer_buspirate = { + .type = SPI_CONTROLLER_BUSPIRATE, + .command = buspirate_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = buspirate_spi_read, + .write_256 = buspirate_spi_write_256, +}; diff --git a/dediprog.c b/dediprog.c index 0b92983..c21c801 100644 --- a/dediprog.c +++ b/dediprog.c @@ -25,6 +25,7 @@ #define DEFAULT_TIMEOUT 3000 static usb_dev_handle *dediprog_handle; +static const struct spi_programmer spi_programmer_dediprog; #if 0 /* Might be useful for other pieces of code as well. */ @@ -145,14 +146,14 @@ static int dediprog_set_spi_speed(uint16_t speed) } #endif -int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { msg_pspew("%s, start=0x%x, len=0x%x\n", __func__, start, len); /* Chosen read length is 16 bytes for now. */ return spi_read_chunked(flash, buf, start, len, 16); } -int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int ret; @@ -318,7 +319,7 @@ int dediprog_init(void) return 1; buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_DEDIPROG; + spi_programmer = &spi_programmer_dediprog; /* RE leftover, leave in until the driver is complete. */ #if 0 @@ -394,3 +395,11 @@ int dediprog_shutdown(void) } return 0; } + +static const struct spi_programmer spi_programmer_dediprog = { + .type = SPI_CONTROLLER_DEDIPROG, + .command = dediprog_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = dediprog_spi_read, + .write_256 = spi_chip_write_1_new, +}; diff --git a/dummyflasher.c b/dummyflasher.c index 241dcee..b1bbcf2 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -25,6 +25,8 @@ #include "flash.h" #include "chipdrivers.h" +static const struct spi_programmer spi_programmer_dummy; + static void tolower_string(char *str) { for (; *str != '\0'; str++) @@ -59,7 +61,7 @@ int dummy_init(void) } if (strstr(bustext, "spi")) { buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_DUMMY; + spi_programmer = &spi_programmer_dummy; msg_pdbg("Enabling support for %s flash.\n", "SPI"); } if (buses_supported == CHIP_BUSTYPE_NONE) @@ -140,7 +142,7 @@ void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len) return; } -int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; @@ -161,7 +163,7 @@ int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, return 0; } -int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { /* Maximum read length is unlimited, use 64kB. */ return spi_read_chunked(flash, buf, start, len, 64 * 1024); @@ -171,7 +173,15 @@ int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) * never be successful, and the current frontend refuses to write in that case. * Other frontends may allow writing even for non-detected chips, though. */ -int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { return spi_write_chunked(flash, buf, start, len, 256); } + +static const struct spi_programmer spi_programmer_dummy = { + .type = SPI_CONTROLLER_DUMMY, + .command = dummy_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = dummy_spi_read, + .write_256 = dummy_spi_write_256, +}; diff --git a/flash.h b/flash.h index 8ebea29..fb06207 100644 --- a/flash.h +++ b/flash.h @@ -452,10 +452,6 @@ uint8_t dummy_chip_readb(const chipaddr addr); uint16_t dummy_chip_readw(const chipaddr addr); uint32_t dummy_chip_readl(const chipaddr addr); void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); -int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); #endif /* nic3com.c */ @@ -527,9 +523,6 @@ extern const struct pcidev_status ata_hpt[]; #define FTDI_FT2232H 0x6010 #define FTDI_FT4232H 0x6011 int ft2232_spi_init(void); -int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* bitbang_spi.c */ int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod); @@ -544,15 +537,10 @@ struct buspirate_spispeeds { }; int buspirate_spi_init(void); int buspirate_spi_shutdown(void); -int buspirate_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int buspirate_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* dediprog.c */ int dediprog_init(void); int dediprog_shutdown(void); -int dediprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int dediprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); /* flashrom.c */ enum write_granularity { @@ -627,32 +615,18 @@ int handle_romentries(uint8_t *buffer, struct flashchip *flash); /* spi.c */ enum spi_controller { - SPI_CONTROLLER_NONE, -#if CONFIG_INTERNAL == 1 -#if defined(__i386__) || defined(__x86_64__) SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, SPI_CONTROLLER_IT87XX, SPI_CONTROLLER_SB600, SPI_CONTROLLER_VIA, SPI_CONTROLLER_WBSIO, -#endif -#endif -#if CONFIG_FT2232_SPI == 1 SPI_CONTROLLER_FT2232, -#endif -#if CONFIG_DUMMY == 1 SPI_CONTROLLER_DUMMY, -#endif -#if CONFIG_BUSPIRATE_SPI == 1 SPI_CONTROLLER_BUSPIRATE, -#endif -#if CONFIG_DEDIPROG == 1 SPI_CONTROLLER_DEDIPROG, -#endif - SPI_CONTROLLER_INVALID /* This must always be the last entry. */ }; -extern const int spi_programmer_count; + struct spi_command { unsigned int writecnt; unsigned int readcnt; @@ -660,6 +634,7 @@ struct spi_command { unsigned char *readarr; }; struct spi_programmer { + enum spi_controller type; int (*command)(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int (*multicommand)(struct spi_command *cmds); @@ -669,8 +644,8 @@ struct spi_programmer { int (*write_256)(struct flashchip *flash, uint8_t *buf, int start, int len); }; -extern enum spi_controller spi_controller; -extern const struct spi_programmer spi_programmer[]; +const struct spi_programmer *spi_programmer; + int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int spi_send_multicommand(struct spi_command *cmds); @@ -684,11 +659,6 @@ extern uint32_t ichspi_bbar; void ich_init_spi(struct pci_dev *dev, uint32_t base, void * rcrb, int ich_generation); int via_init_spi(struct pci_dev * dev); -int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len); -int ich_spi_send_multicommand(struct spi_command *cmds); /* it87spi.c */ void enter_conf_mode_ite(uint16_t port); @@ -696,23 +666,12 @@ void exit_conf_mode_ite(uint16_t port); struct superio probe_superio_ite(void); int init_superio_ite(void); int it87spi_init(void); -int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* sb600spi.c */ void sb600_probe_spi(struct pci_dev * dev); -int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); -int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* wbsio_spi.c */ int wbsio_check_for_spi(void); -int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); -int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); /* serprog.c */ int serprog_init(void); diff --git a/flashrom.c b/flashrom.c index fe173a7..dc262d5 100644 --- a/flashrom.c +++ b/flashrom.c @@ -1354,10 +1354,6 @@ int selfcheck(void) msg_gerr("Programmer table miscompilation!\n"); ret = 1; } - if (spi_programmer_count - 1 != SPI_CONTROLLER_INVALID) { - msg_gerr("SPI programmer table miscompilation!\n"); - ret = 1; - } for (flash = flashchips; flash && flash->name; flash++) if (selfcheck_eraseblocks(flash)) ret = 1; diff --git a/ft2232_spi.c b/ft2232_spi.c index c8711e9..b45ba42 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -45,6 +45,7 @@ #define BITMODE_BITBANG_NORMAL 1 #define BITMODE_BITBANG_SPI 2 +static const struct spi_programmer spi_programmer_ft2232; static struct ftdi_context ftdic_context; static int send_buf(struct ftdi_context *ftdic, const unsigned char *buf, int size) @@ -192,7 +193,7 @@ int ft2232_spi_init(void) // msg_pdbg("\nft2232 chosen\n"); buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_FT2232; + spi_programmer = &spi_programmer_ft2232; return 0; } @@ -293,4 +294,12 @@ int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int l return spi_write_chunked(flash, buf, start, len, 256); } +static const struct spi_programmer spi_programmer_ft2232 = { + .type = SPI_CONTROLLER_FT2232, + .command = ft2232_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = ft2232_spi_read, + .write_256 = ft2232_spi_write_256, +}; + #endif diff --git a/ichspi.c b/ichspi.c index 246f3ae..2627c60 100644 --- a/ichspi.c +++ b/ichspi.c @@ -234,7 +234,7 @@ static int generate_opcodes(OPCODES * op) return -1; } - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: preop = REGREAD16(ICH7_REG_PREOP); @@ -309,7 +309,7 @@ int program_opcodes(OPCODES * op) } msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: REGWRITE16(ICH7_REG_PREOP, preop); @@ -337,7 +337,7 @@ int program_opcodes(OPCODES * op) */ void ich_set_bbar(uint32_t minaddr) { - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: mmio_writel(minaddr, ich_spibar + 0x50); ichspi_bbar = mmio_readl(ich_spibar + 0x50); @@ -448,19 +448,19 @@ void ich_init_spi(struct pci_dev *dev, uint32_t base, void * rcrb, switch (ich_generation) { case 7: buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_ICH7; + spi_programmer = &spi_programmer_ich7; spibar_offset = 0x3020; break; case 8: buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_ICH9; + spi_programmer = &spi_programmer_ich9; spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_ICH9; + spi_programmer = &spi_programmer_ich9; spibar_offset = 0x3800; break; } @@ -471,7 +471,7 @@ void ich_init_spi(struct pci_dev *dev, uint32_t base, void * rcrb, /* Assign Virtual Address */ ich_spibar = rcrb + spibar_offset; - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); @@ -600,7 +600,7 @@ int via_init_spi(struct pci_dev * dev) /* Not sure if it speaks all these bus protocols. */ buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_VIA; + spi_programmer = &spi_programmer_via; ich_init_opcodes(); return 0; @@ -848,7 +848,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, static int run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data) { - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_VIA: if (datalength > 16) { msg_perr("%s: Internal command size error for " @@ -881,27 +881,27 @@ static int run_opcode(OPCODE op, uint32_t offset, return -1; } -int ich_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) +static int ich_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) { int maxdata = 64; - if (spi_controller == SPI_CONTROLLER_VIA) + if (spi_programmer->type == SPI_CONTROLLER_VIA) maxdata = 16; return spi_read_chunked(flash, buf, start, len, maxdata); } -int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len) +static int ich_spi_write_256(struct flashchip *flash, uint8_t * buf, int start, int len) { int maxdata = 64; - if (spi_controller == SPI_CONTROLLER_VIA) + if (spi_programmer->type == SPI_CONTROLLER_VIA) maxdata = 16; return spi_write_chunked(flash, buf, start, len, maxdata); } -int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int result; @@ -966,7 +966,7 @@ int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { addr = (writearr[1] << 16) | (writearr[2] << 8) | (writearr[3] << 0); - switch (spi_controller) { + switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_ICH9: if (addr < ichspi_bbar) { @@ -1001,7 +1001,7 @@ int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, return result; } -int ich_spi_send_multicommand(struct spi_command *cmds) +static int ich_spi_send_multicommand(struct spi_command *cmds) { int ret = 0; int i; @@ -1071,4 +1071,28 @@ int ich_spi_send_multicommand(struct spi_command *cmds) return ret; } +static const struct spi_programmer spi_programmer_ich7 = { + .type = SPI_CONTROLLER_ICH7, + .command = ich_spi_send_command, + .multicommand = ich_spi_send_multicommand, + .read = ich_spi_read, + .write_256 = ich_spi_write_256, +}; + +static const struct spi_programmer spi_programmer_ich9 = { + .type = SPI_CONTROLLER_ICH9, + .command = ich_spi_send_command, + .multicommand = ich_spi_send_multicommand, + .read = ich_spi_read, + .write_256 = ich_spi_write_256, +}; + +static const struct spi_programmer spi_programmer_via = { + .type = SPI_CONTROLLER_VIA, + .command = ich_spi_send_command, + .multicommand = ich_spi_send_multicommand, + .read = ich_spi_read, + .write_256 = ich_spi_write_256, +}; + #endif diff --git a/it87spi.c b/it87spi.c index cf3d3b9..dddb5a9 100644 --- a/it87spi.c +++ b/it87spi.c @@ -34,6 +34,8 @@ #define ITE_SUPERIO_PORT1 0x2e #define ITE_SUPERIO_PORT2 0x4e +static const struct spi_programmer spi_programmer_it87xx; + uint16_t it8716f_flashport = 0; /* use fast 33MHz SPI (<>0) or slow 16MHz (0) */ static int fast_spi = 1; @@ -175,7 +177,7 @@ static uint16_t it87spi_probe(uint16_t port) it8716f_flashport = flashport; if (buses_supported & CHIP_BUSTYPE_SPI) msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); - spi_controller = SPI_CONTROLLER_IT87XX; + spi_programmer = &spi_programmer_it87xx; buses_supported |= CHIP_BUSTYPE_SPI; return 0; } @@ -227,7 +229,7 @@ int it87spi_init(void) * commands with the address in inverse wire order. That's why the register * ordering in case 4 and 5 may seem strange. */ -int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { uint8_t busy, writeenc; @@ -320,7 +322,7 @@ static int it8716f_spi_page_program(struct flashchip *flash, uint8_t *buf, int s * IT8716F only allows maximum of 512 kb SPI mapped to LPC memory cycles * Need to read this big flash using firmware cycles 3 byte at a time. */ -int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) { int total_size = 1024 * flash->total_size; fast_spi = 0; @@ -334,7 +336,7 @@ int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int return 0; } -int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +static int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { /* * IT8716F only allows maximum of 512 kb SPI chip size for memory @@ -371,4 +373,12 @@ int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, return 0; } +static const struct spi_programmer spi_programmer_it87xx = { + .type = SPI_CONTROLLER_IT87XX, + .command = it8716f_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = it8716f_spi_chip_read, + .write_256 = it8716f_spi_chip_write_256, +}; + #endif diff --git a/sb600spi.c b/sb600spi.c index e42b20b..866e309 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -41,6 +41,7 @@ */ static uint8_t *sb600_spibar = NULL; +static const struct spi_programmer spi_programmer_sb600; void sb600_probe_spi(struct pci_dev * dev) { @@ -114,16 +115,16 @@ void sb600_probe_spi(struct pci_dev * dev) return; buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_SB600; + spi_programmer = &spi_programmer_sb600; } -int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { /* Maximum read length is 8 bytes. */ return spi_read_chunked(flash, buf, start, len, 8); } -int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) +static int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) { return spi_write_chunked(flash, buf, start, len, 5); } @@ -144,7 +145,7 @@ static void execute_command(void) ; } -int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int count; @@ -227,4 +228,12 @@ int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, return 0; } +static const struct spi_programmer spi_programmer_sb600 = { + .type = SPI_CONTROLLER_SB600, + .command = sb600_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = sb600_spi_read, + .write_256 = sb600_spi_write_256, +}; + #endif diff --git a/spi.c b/spi.c index 2b64463..dc4da9f 100644 --- a/spi.c +++ b/spi.c @@ -27,129 +27,34 @@ #include "chipdrivers.h" #include "spi.h" -enum spi_controller spi_controller = SPI_CONTROLLER_NONE; - void spi_prettyprint_status_register(struct flashchip *flash); -const struct spi_programmer spi_programmer[] = { - { /* SPI_CONTROLLER_NONE */ - .command = NULL, - .multicommand = NULL, - .read = NULL, - .write_256 = NULL, - }, - -#if CONFIG_INTERNAL == 1 -#if defined(__i386__) || defined(__x86_64__) - { /* SPI_CONTROLLER_ICH7 */ - .command = ich_spi_send_command, - .multicommand = ich_spi_send_multicommand, - .read = ich_spi_read, - .write_256 = ich_spi_write_256, - }, - - { /* SPI_CONTROLLER_ICH9 */ - .command = ich_spi_send_command, - .multicommand = ich_spi_send_multicommand, - .read = ich_spi_read, - .write_256 = ich_spi_write_256, - }, - - { /* SPI_CONTROLLER_IT87XX */ - .command = it8716f_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = it8716f_spi_chip_read, - .write_256 = it8716f_spi_chip_write_256, - }, - - { /* SPI_CONTROLLER_SB600 */ - .command = sb600_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = sb600_spi_read, - .write_256 = sb600_spi_write_256, - }, - - { /* SPI_CONTROLLER_VIA */ - .command = ich_spi_send_command, - .multicommand = ich_spi_send_multicommand, - .read = ich_spi_read, - .write_256 = ich_spi_write_256, - }, - - { /* SPI_CONTROLLER_WBSIO */ - .command = wbsio_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = wbsio_spi_read, - .write_256 = spi_chip_write_1_new, - }, -#endif -#endif - -#if CONFIG_FT2232_SPI == 1 - { /* SPI_CONTROLLER_FT2232 */ - .command = ft2232_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = ft2232_spi_read, - .write_256 = ft2232_spi_write_256, - }, -#endif - -#if CONFIG_DUMMY == 1 - { /* SPI_CONTROLLER_DUMMY */ - .command = dummy_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = dummy_spi_read, - .write_256 = dummy_spi_write_256, - }, -#endif - -#if CONFIG_BUSPIRATE_SPI == 1 - { /* SPI_CONTROLLER_BUSPIRATE */ - .command = buspirate_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = buspirate_spi_read, - .write_256 = buspirate_spi_write_256, - }, -#endif - -#if CONFIG_DEDIPROG == 1 - { /* SPI_CONTROLLER_DEDIPROG */ - .command = dediprog_spi_send_command, - .multicommand = default_spi_send_multicommand, - .read = dediprog_spi_read, - .write_256 = spi_chip_write_1_new, - }, -#endif - - {}, /* This entry corresponds to SPI_CONTROLLER_INVALID. */ -}; - -const int spi_programmer_count = ARRAY_SIZE(spi_programmer); +const struct spi_programmer *spi_programmer; int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { - if (!spi_programmer[spi_controller].command) { + if (!spi_programmer->command) { msg_perr("%s called, but SPI is unsupported on this " "hardware. Please report a bug at " "flashrom(a)flashrom.org\n", __func__); return 1; } - return spi_programmer[spi_controller].command(writecnt, readcnt, + return spi_programmer->command(writecnt, readcnt, writearr, readarr); } int spi_send_multicommand(struct spi_command *cmds) { - if (!spi_programmer[spi_controller].multicommand) { + if (!spi_programmer->multicommand) { msg_perr("%s called, but SPI is unsupported on this " "hardware. Please report a bug at " "flashrom(a)flashrom.org\n", __func__); return 1; } - return spi_programmer[spi_controller].multicommand(cmds); + return spi_programmer->multicommand(cmds); } int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, @@ -183,14 +88,14 @@ int default_spi_send_multicommand(struct spi_command *cmds) int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) { - if (!spi_programmer[spi_controller].read) { + if (!spi_programmer->read) { msg_perr("%s called, but SPI read is unsupported on this " "hardware. Please report a bug at " "flashrom(a)flashrom.org\n", __func__); return 1; } - return spi_programmer[spi_controller].read(flash, buf, start, len); + return spi_programmer->read(flash, buf, start, len); } /* @@ -202,14 +107,14 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len) /* real chunksize is up to 256, logical chunksize is 256 */ int spi_chip_write_256_new(struct flashchip *flash, uint8_t *buf, int start, int len) { - if (!spi_programmer[spi_controller].write_256) { + if (!spi_programmer->write_256) { msg_perr("%s called, but SPI page write is unsupported on this " "hardware. Please report a bug at " "flashrom(a)flashrom.org\n", __func__); return 1; } - return spi_programmer[spi_controller].write_256(flash, buf, start, len); + return spi_programmer->write_256(flash, buf, start, len); } /* Wrapper function until the generic code is converted to partial writes. */ @@ -239,7 +144,7 @@ int spi_chip_write_256(struct flashchip *flash, uint8_t *buf) */ uint32_t spi_get_valid_read_addr(void) { - switch (spi_controller) { + switch (spi_programmer->type) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_ICH7: diff --git a/spi25.c b/spi25.c index 32bb73c..d9dae35 100644 --- a/spi25.c +++ b/spi25.c @@ -177,7 +177,7 @@ int probe_spi_rdid4(struct flashchip *flash) /* Some SPI controllers do not support commands with writecnt=1 and * readcnt=4. */ - switch (spi_controller) { + switch (spi_programmer->type) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_IT87XX: @@ -1019,7 +1019,7 @@ int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len) .readarr = NULL, }}; - switch (spi_controller) { + switch (spi_programmer->type) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_IT87XX: diff --git a/wbsio_spi.c b/wbsio_spi.c index b8f8b38..6288340 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -28,6 +28,7 @@ #define WBSIO_PORT2 0x4e static uint16_t wbsio_spibase = 0; +static const struct spi_programmer spi_programmer_wbsio; static uint16_t wbsio_get_spibase(uint16_t port) { @@ -68,7 +69,7 @@ int wbsio_check_for_spi(void) msg_pspew("\nwbsio_spibase = 0x%x\n", wbsio_spibase); buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_WBSIO; + spi_programmer = &spi_programmer_wbsio; msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " "1024 KB!\n", __func__); max_rom_decode.spi = 1024 * 1024; @@ -96,7 +97,7 @@ int wbsio_check_for_spi(void) * Would one more byte of RAM in the chip (to get all 24 bits) really make * such a big difference? */ -int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, +static int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; @@ -180,9 +181,18 @@ int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, return 0; } -int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +static int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { return read_memmapped(flash, buf, start, len); } +static const struct spi_programmer spi_programmer_wbsio = { + .type = SPI_CONTROLLER_WBSIO, + .command = wbsio_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = wbsio_spi_read, + .write_256 = spi_chip_write_1_new, +}; + + #endif -- 1.7.1

1 0

[PATCH 2/3] Move SB600 SPI initialization to sb600spi.c
by Michael Karcher 18 Jul '10

18 Jul '10

Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- chipset_enable.c | 79 ++--------------------------------------------------- flash.h | 2 +- sb600spi.c | 77 +++++++++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 80 insertions(+), 78 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index 7434d65..ad3b732 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -683,10 +683,8 @@ static int enable_flash_amd8111(struct pci_dev *dev, const char *name) static int enable_flash_sb600(struct pci_dev *dev, const char *name) { - uint32_t tmp, prot; + uint32_t prot; uint8_t reg; - struct pci_dev *smbus_dev; - int has_spi = 1; /* Clear ROM protect 0-3. */ for (reg = 0x50; reg < 0x60; reg += 4) { @@ -710,80 +708,9 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name) (prot & 0xfffffc00) + ((prot & 0x3ff) << 8)); } - /* Read SPI_BaseAddr */ - tmp = pci_read_long(dev, 0xa0); - tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */ - msg_pdbg("SPI base address is at 0x%x\n", tmp); - - /* If the BAR has address 0, it is unlikely SPI is used. */ - if (!tmp) - has_spi = 0; - - if (has_spi) { - /* Physical memory has to be mapped at page (4k) boundaries. */ - sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, - 0x1000); - /* The low bits of the SPI base address are used as offset into - * the mapped page. - */ - sb600_spibar += tmp & 0xfff; - - tmp = pci_read_long(dev, 0xa0); - msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " - "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, - (tmp & 0x4) >> 2); - tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2; - msg_pdbg("PrefetchEnSPIFromIMC=%i, ", tmp); - - tmp = pci_read_byte(dev, 0xbb); - msg_pdbg("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", - tmp & 0x1, (tmp & 0x20) >> 5); - tmp = mmio_readl(sb600_spibar); - msg_pdbg("SpiArbEnable=%i, SpiAccessMacRomEn=%i, " - "SpiHostAccessRomEn=%i, ArbWaitCount=%i, " - "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n", - (tmp >> 19) & 0x1, (tmp >> 22) & 0x1, - (tmp >> 23) & 0x1, (tmp >> 24) & 0x7, - (tmp >> 27) & 0x1, (tmp >> 28) & 0x1); - } - - /* Look for the SMBus device. */ - smbus_dev = pci_dev_find(0x1002, 0x4385); - - if (has_spi && !smbus_dev) { - msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); - has_spi = 0; - } - if (has_spi) { - /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */ - /* GPIO11/SPI_DO and GPIO12/SPI_DI status */ - reg = pci_read_byte(smbus_dev, 0xAB); - reg &= 0xC0; - msg_pdbg("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO"); - msg_pdbg("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI"); - if (reg != 0x00) - has_spi = 0; - /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */ - reg = pci_read_byte(smbus_dev, 0x83); - reg &= 0xC0; - msg_pdbg("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD"); - msg_pdbg("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS"); - /* SPI_HOLD is not used on all boards, filter it out. */ - if ((reg & 0x80) != 0x00) - has_spi = 0; - /* GPIO47/SPI_CLK status */ - reg = pci_read_byte(smbus_dev, 0xA7); - reg &= 0x40; - msg_pdbg("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK"); - if (reg != 0x00) - has_spi = 0; - } - buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; - if (has_spi) { - buses_supported |= CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_SB600; - } + + sb600_probe_spi(dev); /* Read ROM strap override register. */ OUTB(0x8f, 0xcd6); diff --git a/flash.h b/flash.h index a8ca6d7..8ebea29 100644 --- a/flash.h +++ b/flash.h @@ -702,11 +702,11 @@ int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* sb600spi.c */ +void sb600_probe_spi(struct pci_dev * dev); int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int sb600_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); -extern uint8_t *sb600_spibar; /* wbsio_spi.c */ int wbsio_check_for_spi(void); diff --git a/sb600spi.c b/sb600spi.c index caf1a99..e42b20b 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -40,7 +40,82 @@ *}; */ -uint8_t *sb600_spibar = NULL; +static uint8_t *sb600_spibar = NULL; + +void sb600_probe_spi(struct pci_dev * dev) +{ + struct pci_dev *smbus_dev; + uint32_t tmp; + uint8_t reg; + /* Read SPI_BaseAddr */ + tmp = pci_read_long(dev, 0xa0); + tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */ + msg_pdbg("SPI base address is at 0x%x\n", tmp); + + /* If the BAR has address 0, it is unlikely SPI is used. */ + if (!tmp) + return; + + /* Physical memory has to be mapped at page (4k) boundaries. */ + sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, + 0x1000); + /* The low bits of the SPI base address are used as offset into + * the mapped page. + */ + sb600_spibar += tmp & 0xfff; + + tmp = pci_read_long(dev, 0xa0); + msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, " + "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1, + (tmp & 0x4) >> 2); + tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2; + msg_pdbg("PrefetchEnSPIFromIMC=%i, ", tmp); + + tmp = pci_read_byte(dev, 0xbb); + msg_pdbg("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n", + tmp & 0x1, (tmp & 0x20) >> 5); + tmp = mmio_readl(sb600_spibar); + msg_pdbg("SpiArbEnable=%i, SpiAccessMacRomEn=%i, " + "SpiHostAccessRomEn=%i, ArbWaitCount=%i, " + "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n", + (tmp >> 19) & 0x1, (tmp >> 22) & 0x1, + (tmp >> 23) & 0x1, (tmp >> 24) & 0x7, + (tmp >> 27) & 0x1, (tmp >> 28) & 0x1); + + /* Look for the SMBus device. */ + smbus_dev = pci_dev_find(0x1002, 0x4385); + + if (!smbus_dev) { + msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n"); + return; + } + + /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */ + /* GPIO11/SPI_DO and GPIO12/SPI_DI status */ + reg = pci_read_byte(smbus_dev, 0xAB); + reg &= 0xC0; + msg_pdbg("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO"); + msg_pdbg("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI"); + if (reg != 0x00) + return; + /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */ + reg = pci_read_byte(smbus_dev, 0x83); + reg &= 0xC0; + msg_pdbg("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD"); + msg_pdbg("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS"); + /* SPI_HOLD is not used on all boards, filter it out. */ + if ((reg & 0x80) != 0x00) + return; + /* GPIO47/SPI_CLK status */ + reg = pci_read_byte(smbus_dev, 0xA7); + reg &= 0x40; + msg_pdbg("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK"); + if (reg != 0x00) + return; + + buses_supported |= CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_SB600; +} int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) { -- 1.7.1

1 0

[PATCH 1/3] Move Intel SPI initialisation to ichspi.c
by Michael Karcher 18 Jul '10

18 Jul '10

Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- chipset_enable.c | 202 +-------------------------------------------------- flash.h | 6 +- ichspi.c | 214 +++++++++++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 218 insertions(+), 204 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index dc0e55f..7434d65 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -417,69 +417,15 @@ static int enable_flash_poulsbo(struct pci_dev *dev, const char *name) static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name) { - uint32_t mmio_base; - /* Do we really need no write enable? */ - mmio_base = (pci_read_long(dev, 0xbc)) << 8; - msg_pdbg("MMIO base at = 0x%x\n", mmio_base); - ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); - - msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n", - mmio_readw(ich_spibar + 0x6c)); - - /* Not sure if it speaks all these bus protocols. */ - buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_VIA; - ich_init_opcodes(); - - return 0; -} - -#define ICH_BMWAG(x) ((x >> 24) & 0xff) -#define ICH_BMRAG(x) ((x >> 16) & 0xff) -#define ICH_BRWA(x) ((x >> 8) & 0xff) -#define ICH_BRRA(x) ((x >> 0) & 0xff) - -#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff) -#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff) - -static void do_ich9_spi_frap(uint32_t frap, int i) -{ - const char *access_names[4] = { - "locked", "read-only", "write-only", "read-write" - }; - const char *region_names[5] = { - "Flash Descriptor", "BIOS", "Management Engine", - "Gigabit Ethernet", "Platform Data" - }; - uint32_t base, limit; - int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) | - (((ICH_BRRA(frap) >> i) & 1) << 0); - int offset = 0x54 + i * 4; - uint32_t freg = mmio_readl(ich_spibar + offset); - - msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n", - offset, freg, i, region_names[i]); - - base = ICH_FREG_BASE(freg); - limit = ICH_FREG_LIMIT(freg); - if (base == 0x1fff && limit == 0) { - /* this FREG is disabled */ - msg_pdbg("%s region is unused.\n", region_names[i]); - return; - } - - msg_pdbg("0x%08x-0x%08x is %s\n", - (base << 12), (limit << 12) | 0x0fff, - access_names[rwperms]); + return via_init_spi(dev); } static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, int ich_generation) { - int ret, i; - uint8_t old, new, bbs, buc; - uint16_t spibar_offset, tmp2; + int ret; + uint8_t bbs, buc; uint32_t tmp, gcs; void *rcrb; //TODO: These names are incorrect for EP80579. For that, the solution would look like the commented line @@ -518,147 +464,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, return ret; } - switch (ich_generation) { - case 7: - buses_supported = CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_ICH7; - spibar_offset = 0x3020; - break; - case 8: - buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_ICH9; - spibar_offset = 0x3020; - break; - case 9: - case 10: - default: /* Future version might behave the same */ - buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; - spi_controller = SPI_CONTROLLER_ICH9; - spibar_offset = 0x3800; - break; - } - - /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */ - msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset); - - /* Assign Virtual Address */ - ich_spibar = rcrb + spibar_offset; - - switch (spi_controller) { - case SPI_CONTROLLER_ICH7: - msg_pdbg("0x00: 0x%04x (SPIS)\n", - mmio_readw(ich_spibar + 0)); - msg_pdbg("0x02: 0x%04x (SPIC)\n", - mmio_readw(ich_spibar + 2)); - msg_pdbg("0x04: 0x%08x (SPIA)\n", - mmio_readl(ich_spibar + 4)); - for (i = 0; i < 8; i++) { - int offs; - offs = 8 + (i * 8); - msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs, - mmio_readl(ich_spibar + offs), i); - msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, - mmio_readl(ich_spibar + offs + 4), i); - } - ichspi_bbar = mmio_readl(ich_spibar + 0x50); - msg_pdbg("0x50: 0x%08x (BBAR)\n", - ichspi_bbar); - msg_pdbg("0x54: 0x%04x (PREOP)\n", - mmio_readw(ich_spibar + 0x54)); - msg_pdbg("0x56: 0x%04x (OPTYPE)\n", - mmio_readw(ich_spibar + 0x56)); - msg_pdbg("0x58: 0x%08x (OPMENU)\n", - mmio_readl(ich_spibar + 0x58)); - msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", - mmio_readl(ich_spibar + 0x5c)); - for (i = 0; i < 4; i++) { - int offs; - offs = 0x60 + (i * 4); - msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, - mmio_readl(ich_spibar + offs), i); - } - msg_pdbg("\n"); - if (mmio_readw(ich_spibar) & (1 << 15)) { - msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); - ichspi_lock = 1; - } - ich_init_opcodes(); - break; - case SPI_CONTROLLER_ICH9: - tmp2 = mmio_readw(ich_spibar + 4); - msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); - msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1)); - msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1); - msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1); - msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1); - msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3); - msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1); - msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1); - msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1); - - tmp = mmio_readl(ich_spibar + 0x50); - msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); - msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); - msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); - msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp)); - msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp)); - - /* print out the FREGx registers along with FRAP access bits */ - for(i = 0; i < 5; i++) - do_ich9_spi_frap(tmp, i); - - msg_pdbg("0x74: 0x%08x (PR0)\n", - mmio_readl(ich_spibar + 0x74)); - msg_pdbg("0x78: 0x%08x (PR1)\n", - mmio_readl(ich_spibar + 0x78)); - msg_pdbg("0x7C: 0x%08x (PR2)\n", - mmio_readl(ich_spibar + 0x7C)); - msg_pdbg("0x80: 0x%08x (PR3)\n", - mmio_readl(ich_spibar + 0x80)); - msg_pdbg("0x84: 0x%08x (PR4)\n", - mmio_readl(ich_spibar + 0x84)); - msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n", - mmio_readl(ich_spibar + 0x90)); - msg_pdbg("0x94: 0x%04x (PREOP)\n", - mmio_readw(ich_spibar + 0x94)); - msg_pdbg("0x96: 0x%04x (OPTYPE)\n", - mmio_readw(ich_spibar + 0x96)); - msg_pdbg("0x98: 0x%08x (OPMENU)\n", - mmio_readl(ich_spibar + 0x98)); - msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", - mmio_readl(ich_spibar + 0x9C)); - ichspi_bbar = mmio_readl(ich_spibar + 0xA0); - msg_pdbg("0xA0: 0x%08x (BBAR)\n", - ichspi_bbar); - msg_pdbg("0xB0: 0x%08x (FDOC)\n", - mmio_readl(ich_spibar + 0xB0)); - if (tmp2 & (1 << 15)) { - msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); - ichspi_lock = 1; - } - ich_init_opcodes(); - break; - default: - /* Nothing */ - break; - } - - old = pci_read_byte(dev, 0xdc); - msg_pdbg("SPI Read Configuration: "); - new = (old >> 2) & 0x3; - switch (new) { - case 0: - case 1: - case 2: - msg_pdbg("prefetching %sabled, caching %sabled, ", - (new & 0x2) ? "en" : "dis", - (new & 0x1) ? "dis" : "en"); - break; - default: - msg_pdbg("invalid prefetching/caching settings, "); - break; - } - + ich_init_spi(dev, tmp, rcrb, ich_generation); return ret; } diff --git a/flash.h b/flash.h index c3302c4..a8ca6d7 100644 --- a/flash.h +++ b/flash.h @@ -680,10 +680,10 @@ int default_spi_send_multicommand(struct spi_command *cmds); uint32_t spi_get_valid_read_addr(void); /* ichspi.c */ -extern int ichspi_lock; extern uint32_t ichspi_bbar; -extern void *ich_spibar; -int ich_init_opcodes(void); +void ich_init_spi(struct pci_dev *dev, uint32_t base, void * rcrb, + int ich_generation); +int via_init_spi(struct pci_dev * dev); int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); diff --git a/ichspi.c b/ichspi.c index d6f9118..246f3ae 100644 --- a/ichspi.c +++ b/ichspi.c @@ -101,11 +101,11 @@ #define ICH7_REG_OPMENU 0x58 /* 64 Bits */ /* ICH SPI configuration lock-down. May be set during chipset enabling. */ -int ichspi_lock = 0; +static int ichspi_lock = 0; uint32_t ichspi_bbar = 0; -void *ich_spibar = NULL; +static void *ich_spibar = NULL; typedef struct _OPCODE { uint8_t opcode; //This commands spi opcode @@ -364,7 +364,7 @@ void ich_set_bbar(uint32_t minaddr) * * It should be called before ICH sends any spi command. */ -int ich_init_opcodes(void) +static int ich_init_opcodes(void) { int rc = 0; OPCODES *curopcodes_done; @@ -398,6 +398,214 @@ int ich_init_opcodes(void) } } +#define ICH_BMWAG(x) ((x >> 24) & 0xff) +#define ICH_BMRAG(x) ((x >> 16) & 0xff) +#define ICH_BRWA(x) ((x >> 8) & 0xff) +#define ICH_BRRA(x) ((x >> 0) & 0xff) + +#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff) +#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff) + +static void do_ich9_spi_frap(uint32_t frap, int i) +{ + const char *access_names[4] = { + "locked", "read-only", "write-only", "read-write" + }; + const char *region_names[5] = { + "Flash Descriptor", "BIOS", "Management Engine", + "Gigabit Ethernet", "Platform Data" + }; + uint32_t base, limit; + int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) | + (((ICH_BRRA(frap) >> i) & 1) << 0); + int offset = 0x54 + i * 4; + uint32_t freg = mmio_readl(ich_spibar + offset); + + msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n", + offset, freg, i, region_names[i]); + + base = ICH_FREG_BASE(freg); + limit = ICH_FREG_LIMIT(freg); + if (base == 0x1fff && limit == 0) { + /* this FREG is disabled */ + msg_pdbg("%s region is unused.\n", region_names[i]); + return; + } + + msg_pdbg("0x%08x-0x%08x is %s\n", + (base << 12), (limit << 12) | 0x0fff, + access_names[rwperms]); +} + +void ich_init_spi(struct pci_dev *dev, uint32_t base, void * rcrb, + int ich_generation) +{ + int i; + uint8_t old, new; + uint16_t spibar_offset, tmp2; + uint32_t tmp; + + switch (ich_generation) { + case 7: + buses_supported = CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_ICH7; + spibar_offset = 0x3020; + break; + case 8: + buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_ICH9; + spibar_offset = 0x3020; + break; + case 9: + case 10: + default: /* Future version might behave the same */ + buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_ICH9; + spibar_offset = 0x3800; + break; + } + + /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */ + msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", base, spibar_offset); + + /* Assign Virtual Address */ + ich_spibar = rcrb + spibar_offset; + + switch (spi_controller) { + case SPI_CONTROLLER_ICH7: + msg_pdbg("0x00: 0x%04x (SPIS)\n", + mmio_readw(ich_spibar + 0)); + msg_pdbg("0x02: 0x%04x (SPIC)\n", + mmio_readw(ich_spibar + 2)); + msg_pdbg("0x04: 0x%08x (SPIA)\n", + mmio_readl(ich_spibar + 4)); + for (i = 0; i < 8; i++) { + int offs; + offs = 8 + (i * 8); + msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs, + mmio_readl(ich_spibar + offs), i); + msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, + mmio_readl(ich_spibar + offs + 4), i); + } + ichspi_bbar = mmio_readl(ich_spibar + 0x50); + msg_pdbg("0x50: 0x%08x (BBAR)\n", + ichspi_bbar); + msg_pdbg("0x54: 0x%04x (PREOP)\n", + mmio_readw(ich_spibar + 0x54)); + msg_pdbg("0x56: 0x%04x (OPTYPE)\n", + mmio_readw(ich_spibar + 0x56)); + msg_pdbg("0x58: 0x%08x (OPMENU)\n", + mmio_readl(ich_spibar + 0x58)); + msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", + mmio_readl(ich_spibar + 0x5c)); + for (i = 0; i < 4; i++) { + int offs; + offs = 0x60 + (i * 4); + msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, + mmio_readl(ich_spibar + offs), i); + } + msg_pdbg("\n"); + if (mmio_readw(ich_spibar) & (1 << 15)) { + msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); + ichspi_lock = 1; + } + ich_init_opcodes(); + break; + case SPI_CONTROLLER_ICH9: + tmp2 = mmio_readw(ich_spibar + 4); + msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); + msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1)); + msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1); + msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1); + msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1); + msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3); + msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1); + msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1); + msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1); + + tmp = mmio_readl(ich_spibar + 0x50); + msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); + msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); + msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); + msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp)); + msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp)); + + /* print out the FREGx registers along with FRAP access bits */ + for(i = 0; i < 5; i++) + do_ich9_spi_frap(tmp, i); + + msg_pdbg("0x74: 0x%08x (PR0)\n", + mmio_readl(ich_spibar + 0x74)); + msg_pdbg("0x78: 0x%08x (PR1)\n", + mmio_readl(ich_spibar + 0x78)); + msg_pdbg("0x7C: 0x%08x (PR2)\n", + mmio_readl(ich_spibar + 0x7C)); + msg_pdbg("0x80: 0x%08x (PR3)\n", + mmio_readl(ich_spibar + 0x80)); + msg_pdbg("0x84: 0x%08x (PR4)\n", + mmio_readl(ich_spibar + 0x84)); + msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n", + mmio_readl(ich_spibar + 0x90)); + msg_pdbg("0x94: 0x%04x (PREOP)\n", + mmio_readw(ich_spibar + 0x94)); + msg_pdbg("0x96: 0x%04x (OPTYPE)\n", + mmio_readw(ich_spibar + 0x96)); + msg_pdbg("0x98: 0x%08x (OPMENU)\n", + mmio_readl(ich_spibar + 0x98)); + msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", + mmio_readl(ich_spibar + 0x9C)); + ichspi_bbar = mmio_readl(ich_spibar + 0xA0); + msg_pdbg("0xA0: 0x%08x (BBAR)\n", + ichspi_bbar); + msg_pdbg("0xB0: 0x%08x (FDOC)\n", + mmio_readl(ich_spibar + 0xB0)); + if (tmp2 & (1 << 15)) { + msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); + ichspi_lock = 1; + } + ich_init_opcodes(); + break; + default: + /* Nothing */ + break; + } + + old = pci_read_byte(dev, 0xdc); + msg_pdbg("SPI Read Configuration: "); + new = (old >> 2) & 0x3; + switch (new) { + case 0: + case 1: + case 2: + msg_pdbg("prefetching %sabled, caching %sabled, ", + (new & 0x2) ? "en" : "dis", + (new & 0x1) ? "dis" : "en"); + break; + default: + msg_pdbg("invalid prefetching/caching settings, "); + break; + } +} + +int via_init_spi(struct pci_dev * dev) +{ + uint32_t mmio_base; + + mmio_base = (pci_read_long(dev, 0xbc)) << 8; + msg_pdbg("MMIO base at = 0x%x\n", mmio_base); + ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); + + msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n", + mmio_readw(ich_spibar + 0x6c)); + + /* Not sure if it speaks all these bus protocols. */ + buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; + spi_controller = SPI_CONTROLLER_VIA; + ich_init_opcodes(); + + return 0; +} + static int ich7_run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data, int maxdata) { -- 1.7.1

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i think i made a mistake
by Antoine Visier 18 Jul '10

18 Jul '10

Hello. Sorry for my stupidity, and my english, i don't speak very well. Today, i tryed to update the bios of my computer. I used flashrom. I 've probably made a mistake and now i got an error message. My computer is the MP945-X The bios version i used is R1.14 and the release date is 4/25/2007 I followed this page : http://doc.ubuntu-fr.org/flasher_le_bios I download the latest version of the bios located on the Aopen download website. http://download.aopen.com.tw/userdownload_List.aspx?RecNo=11314&Model=2210 I unzip the wiab1e.zip and i used the file named IAB1E.BIN (i don't use the two other .exe files) After the first error message, i tried to return to the inital bios (i've got two backup, called* *backup.bin and A7Tversion.ROM) I put the file i used attached to this mail. I 've typed those commands : @a-desktop:~$* sudo dmidecode -s bios-version* i945GMx-FX R1.08 Aug.25.2006 AOpen Inc. a@a-desktop:~$ *sudo flashrom* flashrom v0.9.1-r946 No coreboot table found. Found chipset "Intel ICH7M", enabling flash write... OK. This chipset supports the following protocols: FWH. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. No operations were specified. a@a-desktop:~$ *sudo flashrom -r backup.bin* flashrom v0.9.1-r946 No coreboot table found. Found chipset "Intel ICH7M", enabling flash write... OK. This chipset supports the following protocols: FWH. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Reading flash... done. a@a-desktop:~$ sudo dmidecode -s bios-version i945GMx-FX R1.08 Aug.25.2006 AOpen Inc. a@a-desktop:~$ *sudo flashrom -w IAB1E.BIN * flashrom v0.9.1-r946 No coreboot table found. Found chipset "Intel ICH7M", enabling flash write... OK. This chipset supports the following protocols: FWH. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x00000fff: 0x481 ERASE FAILED! ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x0000ffff: 0xc74 ERASE FAILED! FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! a@a-desktop:~$ *sudo flashrom -w backup.bin* flashrom v0.9.1-r946 No coreboot table found. Found chipset "Intel ICH7M", enabling flash write... OK. This chipset supports the following protocols: FWH. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x00000fff: 0x481 ERASE FAILED! ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x0000ffff: 0xc74 ERASE FAILED! FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! a@a-desktop:~$* sudo flashrom -w A7Tversion.ROM * flashrom v0.9.1-r946 No coreboot table found. Found chipset "Intel ICH7M", enabling flash write... OK. This chipset supports the following protocols: FWH. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x00000fff: 0x481 ERASE FAILED! ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x0000ffff: 0xc74 ERASE FAILED! FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! a@a-desktop:~$ *sudo dmidecode -s bios-version* i945GMx-FX R1.08 Aug.25.2006 AOpen Inc. a@a-desktop:~$ sudo flashrom -w IAB1E.BIN flashrom v0.9.1-r946 No coreboot table found. Found chipset "Intel ICH7M", enabling flash write... OK. This chipset supports the following protocols: FWH. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x00000fff: 0x481 ERASE FAILED! ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x0000ffff: 0xc74 ERASE FAILED! FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! a@a-desktop:~$ *sudo dmidecode -s bios-version* i945GMx-FX R1.08 Aug.25.2006 AOpen Inc. Thanks for any help. I keep my computer on Antoine ---- Attachments have been stripped: "IAB1E.BIN", "backup.bin", "A7Tversion.ROM"

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Re: [flashrom] [PATCH] Use struct pointer instead of enum to set bitbang adapter
by Carl-Daniel Hailfinger 18 Jul '10

18 Jul '10

On 18.07.2010 01:19, Michael Karcher wrote: > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > Thanks for the patch. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

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[commit] r1091 - trunk
by repository service 18 Jul '10

18 Jul '10

Author: mkarcher Date: Sun Jul 18 01:27:47 2010 New Revision: 1091 URL: http://flashrom.org/trac/coreboot/changeset/1091 Log: Use struct pointer instead of enum to set bitbang adapter Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/bitbang_spi.c trunk/flash.h trunk/flashrom.c Modified: trunk/bitbang_spi.c ============================================================================== --- trunk/bitbang_spi.c Sun Jul 18 01:21:12 2010 (r1090) +++ trunk/bitbang_spi.c Sun Jul 18 01:27:47 2010 (r1091) @@ -29,45 +29,34 @@ /* Length of half a clock period in usecs. */ static int bitbang_spi_half_period; -static enum bitbang_spi_master bitbang_spi_master = BITBANG_SPI_INVALID; - -static const struct bitbang_spi_master_entry bitbang_spi_master_table[] = { - {}, /* This entry corresponds to BITBANG_SPI_INVALID. */ -}; - -const int bitbang_spi_master_count = ARRAY_SIZE(bitbang_spi_master_table); +static const struct bitbang_spi_master *bitbang_spi_master = NULL; /* Note that CS# is active low, so val=0 means the chip is active. */ static void bitbang_spi_set_cs(int val) { - bitbang_spi_master_table[bitbang_spi_master].set_cs(val); + bitbang_spi_master->set_cs(val); } static void bitbang_spi_set_sck(int val) { - bitbang_spi_master_table[bitbang_spi_master].set_sck(val); + bitbang_spi_master->set_sck(val); } static void bitbang_spi_set_mosi(int val) { - bitbang_spi_master_table[bitbang_spi_master].set_mosi(val); + bitbang_spi_master->set_mosi(val); } static int bitbang_spi_get_miso(void) { - return bitbang_spi_master_table[bitbang_spi_master].get_miso(); + return bitbang_spi_master->get_miso(); } -int bitbang_spi_init(enum bitbang_spi_master master, int halfperiod) +int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod) { bitbang_spi_master = master; bitbang_spi_half_period = halfperiod; - if (bitbang_spi_master == BITBANG_SPI_INVALID) { - msg_perr("Invalid bitbang SPI master. \n" - "Please report a bug at flashrom(a)flashrom.org\n"); - return 1; - } bitbang_spi_set_cs(1); bitbang_spi_set_sck(0); bitbang_spi_set_mosi(0); Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Sun Jul 18 01:21:12 2010 (r1090) +++ trunk/flash.h Sun Jul 18 01:27:47 2010 (r1091) @@ -127,13 +127,14 @@ void chip_readn(uint8_t *buf, const chipaddr addr, size_t len); void programmer_delay(int usecs); -enum bitbang_spi_master { - BITBANG_SPI_INVALID /* This must always be the last entry. */ +enum bitbang_spi_master_type { + BITBANG_SPI_DUMMY /* remove as soon as there is a real entry */ }; -extern const int bitbang_spi_master_count; +struct bitbang_spi_master { + enum bitbang_spi_master_type type; -struct bitbang_spi_master_entry { + /* Note that CS# is active low, so val=0 means the chip is active. */ void (*set_cs) (int val); void (*set_sck) (int val); void (*set_mosi) (int val); @@ -531,7 +532,7 @@ int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); /* bitbang_spi.c */ -int bitbang_spi_init(enum bitbang_spi_master master, int halfperiod); +int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod); int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sun Jul 18 01:21:12 2010 (r1090) +++ trunk/flashrom.c Sun Jul 18 01:27:47 2010 (r1091) @@ -1358,12 +1358,6 @@ msg_gerr("SPI programmer table miscompilation!\n"); ret = 1; } -#if CONFIG_BITBANG_SPI == 1 - if (bitbang_spi_master_count - 1 != BITBANG_SPI_INVALID) { - msg_gerr("Bitbanging SPI master table miscompilation!\n"); - ret = 1; - } -#endif for (flash = flashchips; flash && flash->name; flash++) if (selfcheck_eraseblocks(flash)) ret = 1;

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