- flashrom - mail.coreboot.org

[PATCH] Constify flashchips array
by Carl-Daniel Hailfinger 03 May '11

03 May '11

Constify flashchips array. This moves 99.5% of the .data section to .rodata (which ends up in .text). Disadvantages: We have one additional memcpy with sizeof(struct flashchip) per executed probe. This is purely startup cost and won't have any impact on operation after probing. Tests would be appreciated, especially with machines having multiple chips. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-const_flashchips/flash.h =================================================================== --- flashrom-const_flashchips/flash.h (Revision 1252) +++ flashrom-const_flashchips/flash.h (Arbeitskopie) @@ -173,7 +173,7 @@ #define TIMING_IGNORED -1 #define TIMING_ZERO -2 -extern struct flashchip flashchips[]; +extern const struct flashchip flashchips[]; /* print.c */ char *flashbuses_to_text(enum chipbustype bustype); @@ -193,7 +193,7 @@ void map_flash_registers(struct flashchip *flash); int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len); int erase_flash(struct flashchip *flash); -struct flashchip *probe_flash(struct flashchip *first_flash, int force); +int probe_flash(int startchip, struct flashchip *fill_flash, int force); int read_flash_to_file(struct flashchip *flash, char *filename); int min(int a, int b); int max(int a, int b); Index: flashrom-const_flashchips/cli_classic.c =================================================================== --- flashrom-const_flashchips/cli_classic.c (Revision 1252) +++ flashrom-const_flashchips/cli_classic.c (Arbeitskopie) @@ -100,7 +100,11 @@ { unsigned long size; /* Probe for up to three flash chips. */ - struct flashchip *flash, *flashes[3]; + const struct flashchip *flash; + struct flashchip flashes[3]; + struct flashchip *fill_flash; + int startchip = 0; + int chipcount = 0; const char *name; int namelen; int opt; @@ -359,49 +363,47 @@ exit(1); } - /* FIXME: Delay calibration should happen in programmer code. */ for (i = 0; i < ARRAY_SIZE(flashes); i++) { - flashes[i] = - probe_flash(i ? flashes[i - 1] + 1 : flashchips, 0); - if (!flashes[i]) - for (i++; i < ARRAY_SIZE(flashes); i++) - flashes[i] = NULL; + startchip = probe_flash(startchip, &flashes[i], 0); + if (startchip == -1) + break; + chipcount++; } - if (flashes[1]) { + if (chipcount > 1) { printf("Multiple flash chips were detected:"); - for (i = 0; i < ARRAY_SIZE(flashes) && flashes[i]; i++) - printf(" %s", flashes[i]->name); + for (i = 0; i < chipcount; i++) + printf(" %s", flashes[i].name); printf("\nPlease specify which chip to use with the -c <chipname> option.\n"); programmer_shutdown(); exit(1); - } else if (!flashes[0]) { + } else if (!chipcount) { printf("No EEPROM/flash device found.\n"); if (!force || !chip_to_probe) { printf("Note: flashrom can never write if the flash chip isn't found automatically.\n"); } if (force && read_it && chip_to_probe) { printf("Force read (-f -r -c) requested, pretending the chip is there:\n"); - flashes[0] = probe_flash(flashchips, 1); - if (!flashes[0]) { + startchip = probe_flash(0, &flashes[0], 1); + if (startchip == -1) { printf("Probing for flash chip '%s' failed.\n", chip_to_probe); programmer_shutdown(); exit(1); } printf("Please note that forced reads most likely contain garbage.\n"); - return read_flash_to_file(flashes[0], filename); + return read_flash_to_file(&flashes[0], filename); } // FIXME: flash writes stay enabled! programmer_shutdown(); exit(1); } - flash = flashes[0]; + fill_flash = &flashes[0]; - check_chip_supported(flash); + check_chip_supported(fill_flash); - size = flash->total_size * 1024; - if (check_max_decode((buses_supported & flash->bustype), size) && + size = fill_flash->total_size * 1024; + if (check_max_decode((buses_supported & fill_flash->bustype), size) && (!force)) { fprintf(stderr, "Chip is too big for this programmer " "(-V gives details). Use --force to override.\n"); @@ -432,5 +434,5 @@ * Give the chip time to settle. */ programmer_delay(100000); - return doit(flash, force, filename, read_it, write_it, erase_it, verify_it); + return doit(fill_flash, force, filename, read_it, write_it, erase_it, verify_it); } Index: flashrom-const_flashchips/print_wiki.c =================================================================== --- flashrom-const_flashchips/print_wiki.c (Revision 1252) +++ flashrom-const_flashchips/print_wiki.c (Arbeitskopie) @@ -201,7 +201,7 @@ static void print_supported_chips_wiki(int cols) { int i = 0, c = 1, chipcount = 0; - struct flashchip *f, *old = NULL; + const struct flashchip *f, *old = NULL; uint32_t t; for (f = flashchips; f->name != NULL; f++) Index: flashrom-const_flashchips/flashchips.c =================================================================== --- flashrom-const_flashchips/flashchips.c (Revision 1252) +++ flashrom-const_flashchips/flashchips.c (Arbeitskopie) @@ -32,7 +32,7 @@ * Please keep the list sorted by vendor name and chip name, so that * the output of 'flashrom -L' is alphabetically sorted. */ -struct flashchip flashchips[] = { +const struct flashchip flashchips[] = { /* * .vendor = Vendor name Index: flashrom-const_flashchips/flashrom.c =================================================================== --- flashrom-const_flashchips/flashrom.c (Revision 1252) +++ flashrom-const_flashchips/flashrom.c (Arbeitskopie) @@ -1123,15 +1123,15 @@ return 1; } -struct flashchip *probe_flash(struct flashchip *first_flash, int force) +int probe_flash(int startchip, struct flashchip *fill_flash, int force) { - struct flashchip *flash; + const struct flashchip *flash; unsigned long base = 0; uint32_t size; enum chipbustype buses_common; char *tmp; - for (flash = first_flash; flash && flash->name; flash++) { + for (flash = flashchips + startchip; flash && flash->name; flash++) { if (chip_to_probe && strcmp(flash->name, chip_to_probe) != 0) continue; msg_gdbg("Probing for %s %s, %d KB: ", @@ -1158,25 +1158,35 @@ size = flash->total_size * 1024; check_max_decode(buses_common, size); + /* Start filling in the dynamic data. */ + *fill_flash = *flash; + base = flashbase ? flashbase : (0xffffffff - size + 1); - flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); + fill_flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); if (force) break; - if (flash->probe(flash) != 1) + if (fill_flash->probe(fill_flash) != 1) goto notfound; - if (first_flash == flashchips - || flash->model_id != GENERIC_DEVICE_ID) + /* If this is the first chip found, accept it. + * If this is not the first chip found, accept it only if it is + * a non-generic match. + * We could either make chipcount global or provide it as + * parameter, or we assume that startchip==0 means this call to + * probe_flash() is the first one and thus no chip has been + * found before. + */ + if (startchip == 0 || fill_flash->model_id != GENERIC_DEVICE_ID) break; notfound: - programmer_unmap_flash_region((void *)flash->virtual_memory, size); + programmer_unmap_flash_region((void *)fill_flash->virtual_memory, size); } if (!flash || !flash->name) - return NULL; + return -1; msg_cinfo("%s chip \"%s %s\" (%d KB, %s) at physical address 0x%lx.\n", force ? "Assuming" : "Found", @@ -1187,10 +1197,11 @@ * may be stored in registers, so avoid lock info printing. */ if (!force) - if (flash->printlock) - flash->printlock(flash); + if (fill_flash->printlock) + fill_flash->printlock(fill_flash); - return flash; + /* Return position of matching chip. */ + return flash - flashchips; } int verify_flash(struct flashchip *flash, uint8_t *buf) @@ -1299,7 +1310,7 @@ * walk_eraseregions(). * Even if an error is found, the function will keep going and check the rest. */ -static int selfcheck_eraseblocks(struct flashchip *flash) +static int selfcheck_eraseblocks(const struct flashchip *flash) { int i, j, k; int ret = 0; @@ -1676,7 +1687,7 @@ int selfcheck(void) { int ret = 0; - struct flashchip *flash; + const struct flashchip *flash; /* Safety check. Instead of aborting after the first error, check * if more errors exist. @@ -1695,7 +1706,7 @@ return ret; } -void check_chip_supported(struct flashchip *flash) +void check_chip_supported(const struct flashchip *flash) { if (TEST_OK_MASK != (flash->tested & TEST_OK_MASK)) { msg_cinfo("===\n"); Index: flashrom-const_flashchips/programmer.h =================================================================== --- flashrom-const_flashchips/programmer.h (Revision 1252) +++ flashrom-const_flashchips/programmer.h (Arbeitskopie) @@ -497,7 +497,7 @@ extern struct decode_sizes max_rom_decode; extern int programmer_may_write; extern unsigned long flashbase; -void check_chip_supported(struct flashchip *flash); +void check_chip_supported(const struct flashchip *flash); int check_max_decode(enum chipbustype buses, uint32_t size); char *extract_programmer_param(char *param_name); Index: flashrom-const_flashchips/print.c =================================================================== --- flashrom-const_flashchips/print.c (Revision 1252) +++ flashrom-const_flashchips/print.c (Arbeitskopie) @@ -78,7 +78,7 @@ { int okcol = 0, pos = 0, i, chipcount = 0; int maxchiplen = 0, maxvendorlen = 0; - struct flashchip *f; + const struct flashchip *f; for (f = flashchips; f->name != NULL; f++) { /* Ignore "unknown XXXX SPI chip" entries. */ -- http://www.hailfinger.org/

3 7

[commit] r1293 - trunk
by repository service 03 May '11

03 May '11

Author: hailfinger Date: Wed May 4 02:39:50 2011 New Revision: 1293 URL: http://flashrom.org/trac/flashrom/changeset/1293 Log: Constify flashchips array. This moves 99.5% of the .data section to .rodata (which ends up in .text). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/cli_classic.c trunk/flash.h trunk/flashchips.c trunk/flashrom.c trunk/print.c trunk/print_wiki.c trunk/programmer.h Modified: trunk/cli_classic.c ============================================================================== --- trunk/cli_classic.c Tue May 3 23:49:41 2011 (r1292) +++ trunk/cli_classic.c Wed May 4 02:39:50 2011 (r1293) @@ -100,7 +100,11 @@ { unsigned long size; /* Probe for up to three flash chips. */ - struct flashchip *flash, *flashes[3]; + const struct flashchip *flash; + struct flashchip flashes[3]; + struct flashchip *fill_flash; + int startchip = 0; + int chipcount = 0; const char *name; int namelen; int opt; @@ -359,49 +363,47 @@ exit(1); } - /* FIXME: Delay calibration should happen in programmer code. */ for (i = 0; i < ARRAY_SIZE(flashes); i++) { - flashes[i] = - probe_flash(i ? flashes[i - 1] + 1 : flashchips, 0); - if (!flashes[i]) - for (i++; i < ARRAY_SIZE(flashes); i++) - flashes[i] = NULL; + startchip = probe_flash(startchip, &flashes[i], 0); + if (startchip == -1) + break; + chipcount++; } - if (flashes[1]) { + if (chipcount > 1) { printf("Multiple flash chips were detected:"); - for (i = 0; i < ARRAY_SIZE(flashes) && flashes[i]; i++) - printf(" %s", flashes[i]->name); + for (i = 0; i < chipcount; i++) + printf(" %s", flashes[i].name); printf("\nPlease specify which chip to use with the -c <chipname> option.\n"); programmer_shutdown(); exit(1); - } else if (!flashes[0]) { + } else if (!chipcount) { printf("No EEPROM/flash device found.\n"); if (!force || !chip_to_probe) { printf("Note: flashrom can never write if the flash chip isn't found automatically.\n"); } if (force && read_it && chip_to_probe) { printf("Force read (-f -r -c) requested, pretending the chip is there:\n"); - flashes[0] = probe_flash(flashchips, 1); - if (!flashes[0]) { + startchip = probe_flash(0, &flashes[0], 1); + if (startchip == -1) { printf("Probing for flash chip '%s' failed.\n", chip_to_probe); programmer_shutdown(); exit(1); } printf("Please note that forced reads most likely contain garbage.\n"); - return read_flash_to_file(flashes[0], filename); + return read_flash_to_file(&flashes[0], filename); } // FIXME: flash writes stay enabled! programmer_shutdown(); exit(1); } - flash = flashes[0]; + fill_flash = &flashes[0]; - check_chip_supported(flash); + check_chip_supported(fill_flash); - size = flash->total_size * 1024; - if (check_max_decode((buses_supported & flash->bustype), size) && + size = fill_flash->total_size * 1024; + if (check_max_decode((buses_supported & fill_flash->bustype), size) && (!force)) { fprintf(stderr, "Chip is too big for this programmer " "(-V gives details). Use --force to override.\n"); @@ -432,5 +434,5 @@ * Give the chip time to settle. */ programmer_delay(100000); - return doit(flash, force, filename, read_it, write_it, erase_it, verify_it); + return doit(fill_flash, force, filename, read_it, write_it, erase_it, verify_it); } Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Tue May 3 23:49:41 2011 (r1292) +++ trunk/flash.h Wed May 4 02:39:50 2011 (r1293) @@ -173,7 +173,7 @@ #define TIMING_IGNORED -1 #define TIMING_ZERO -2 -extern struct flashchip flashchips[]; +extern const struct flashchip flashchips[]; /* print.c */ char *flashbuses_to_text(enum chipbustype bustype); @@ -193,7 +193,7 @@ void map_flash_registers(struct flashchip *flash); int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len); int erase_flash(struct flashchip *flash); -struct flashchip *probe_flash(struct flashchip *first_flash, int force); +int probe_flash(int startchip, struct flashchip *fill_flash, int force); int read_flash_to_file(struct flashchip *flash, char *filename); int min(int a, int b); int max(int a, int b); Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Tue May 3 23:49:41 2011 (r1292) +++ trunk/flashchips.c Wed May 4 02:39:50 2011 (r1293) @@ -32,7 +32,7 @@ * Please keep the list sorted by vendor name and chip name, so that * the output of 'flashrom -L' is alphabetically sorted. */ -struct flashchip flashchips[] = { +const struct flashchip flashchips[] = { /* * .vendor = Vendor name Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Tue May 3 23:49:41 2011 (r1292) +++ trunk/flashrom.c Wed May 4 02:39:50 2011 (r1293) @@ -1109,16 +1109,16 @@ return 1; } -struct flashchip *probe_flash(struct flashchip *first_flash, int force) +int probe_flash(int startchip, struct flashchip *fill_flash, int force) { - struct flashchip *flash; + const struct flashchip *flash; unsigned long base = 0; char location[64]; uint32_t size; enum chipbustype buses_common; char *tmp; - for (flash = first_flash; flash && flash->name; flash++) { + for (flash = flashchips + startchip; flash && flash->name; flash++) { if (chip_to_probe && strcmp(flash->name, chip_to_probe) != 0) continue; msg_gdbg("Probing for %s %s, %d KB: ", @@ -1145,25 +1145,35 @@ size = flash->total_size * 1024; check_max_decode(buses_common, size); + /* Start filling in the dynamic data. */ + *fill_flash = *flash; + base = flashbase ? flashbase : (0xffffffff - size + 1); - flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); + fill_flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); if (force) break; - if (flash->probe(flash) != 1) + if (fill_flash->probe(fill_flash) != 1) goto notfound; - if (first_flash == flashchips - || flash->model_id != GENERIC_DEVICE_ID) + /* If this is the first chip found, accept it. + * If this is not the first chip found, accept it only if it is + * a non-generic match. + * We could either make chipcount global or provide it as + * parameter, or we assume that startchip==0 means this call to + * probe_flash() is the first one and thus no chip has been + * found before. + */ + if (startchip == 0 || fill_flash->model_id != GENERIC_DEVICE_ID) break; notfound: - programmer_unmap_flash_region((void *)flash->virtual_memory, size); + programmer_unmap_flash_region((void *)fill_flash->virtual_memory, size); } if (!flash || !flash->name) - return NULL; + return -1; #if CONFIG_INTERNAL == 1 if (programmer_table[programmer].map_flash_region == physmap) @@ -1181,10 +1191,11 @@ * may be stored in registers, so avoid lock info printing. */ if (!force) - if (flash->printlock) - flash->printlock(flash); + if (fill_flash->printlock) + fill_flash->printlock(fill_flash); - return flash; + /* Return position of matching chip. */ + return flash - flashchips; } int verify_flash(struct flashchip *flash, uint8_t *buf) @@ -1293,7 +1304,7 @@ * walk_eraseregions(). * Even if an error is found, the function will keep going and check the rest. */ -static int selfcheck_eraseblocks(struct flashchip *flash) +static int selfcheck_eraseblocks(const struct flashchip *flash) { int i, j, k; int ret = 0; @@ -1670,7 +1681,7 @@ int selfcheck(void) { int ret = 0; - struct flashchip *flash; + const struct flashchip *flash; /* Safety check. Instead of aborting after the first error, check * if more errors exist. @@ -1689,7 +1700,7 @@ return ret; } -void check_chip_supported(struct flashchip *flash) +void check_chip_supported(const struct flashchip *flash) { if (TEST_OK_MASK != (flash->tested & TEST_OK_MASK)) { msg_cinfo("===\n"); Modified: trunk/print.c ============================================================================== --- trunk/print.c Tue May 3 23:49:41 2011 (r1292) +++ trunk/print.c Wed May 4 02:39:50 2011 (r1293) @@ -78,7 +78,7 @@ { int okcol = 0, pos = 0, i, chipcount = 0; int maxchiplen = 0, maxvendorlen = 0; - struct flashchip *f; + const struct flashchip *f; for (f = flashchips; f->name != NULL; f++) { /* Ignore "unknown XXXX SPI chip" entries. */ Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Tue May 3 23:49:41 2011 (r1292) +++ trunk/print_wiki.c Wed May 4 02:39:50 2011 (r1293) @@ -201,7 +201,7 @@ static void print_supported_chips_wiki(int cols) { int i = 0, c = 1, chipcount = 0; - struct flashchip *f, *old = NULL; + const struct flashchip *f, *old = NULL; uint32_t t; for (f = flashchips; f->name != NULL; f++) Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Tue May 3 23:49:41 2011 (r1292) +++ trunk/programmer.h Wed May 4 02:39:50 2011 (r1293) @@ -515,7 +515,7 @@ extern struct decode_sizes max_rom_decode; extern int programmer_may_write; extern unsigned long flashbase; -void check_chip_supported(struct flashchip *flash); +void check_chip_supported(const struct flashchip *flash); int check_max_decode(enum chipbustype buses, uint32_t size); char *extract_programmer_param(char *param_name);

1 0

[PATCH] Revert MMIO space writes on shutdown as needed.
by Carl-Daniel Hailfinger 03 May '11

03 May '11

Revert MMIO space writes on shutdown as needed. Reversible MMIO space writes now use rmmio_write*(). MMIO space writes which are one-shot (e.g. communication with some chip) should continue to use the permanent mmio_write* variants. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-mmio_shutdown_restore/hwaccess.c =================================================================== --- flashrom-mmio_shutdown_restore/hwaccess.c (Revision 1234) +++ flashrom-mmio_shutdown_restore/hwaccess.c (Arbeitskopie) @@ -184,3 +184,71 @@ { return le_to_cpu32(mmio_readl(addr)); } + +enum mmio_write_type { + mmio_write_type_b, + mmio_write_type_w, + mmio_write_type_l, +}; + +struct undo_mmio_write_data { + void *addr; + int reg; + enum mmio_write_type type; + union { + uint8_t bdata; + uint16_t wdata; + uint32_t ldata; + }; +}; + +void undo_mmio_write(void *p) +{ + struct undo_mmio_write_data *data = p; + msg_pdbg("Restoring MMIO space at %p\n", data->addr); + switch (data->type) { + case mmio_write_type_b: + mmio_writeb(data->bdata, data->addr); + break; + case mmio_write_type_w: + mmio_writeb(data->wdata, data->addr); + break; + case mmio_write_type_l: + mmio_writeb(data->ldata, data->addr); + break; + } + /* p was allocated in register_undo_mmio_write. */ + free(p); +} + +#define register_undo_mmio_write(a, c) \ +{ \ + struct undo_mmio_write_data *undo_mmio_write_data; \ + undo_mmio_write_data = malloc(sizeof(struct undo_mmio_write_data)); \ + undo_mmio_write_data->addr = a; \ + undo_mmio_write_data->type = mmio_write_type_##c; \ + undo_mmio_write_data->c##data = mmio_read##c(a); \ + register_shutdown(undo_mmio_write, undo_mmio_write_data); \ +} + +#define register_undo_mmio_writeb(a) register_undo_mmio_write(a, b) +#define register_undo_mmio_writew(a) register_undo_mmio_write(a, w) +#define register_undo_mmio_writel(a) register_undo_mmio_write(a, l) + +void rmmio_writeb(uint8_t val, void *addr) +{ + register_undo_mmio_writeb(addr); + mmio_writeb(val, addr); +} + +void rmmio_writew(uint16_t val, void *addr) +{ + register_undo_mmio_writew(addr); + mmio_writew(val, addr); +} + +void rmmio_writel(uint32_t val, void *addr) +{ + register_undo_mmio_writel(addr); + mmio_writel(val, addr); +} Index: flashrom-mmio_shutdown_restore/ichspi.c =================================================================== --- flashrom-mmio_shutdown_restore/ichspi.c (Revision 1234) +++ flashrom-mmio_shutdown_restore/ichspi.c (Arbeitskopie) @@ -382,16 +382,16 @@ switch (spi_controller) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: - REGWRITE16(ICH7_REG_PREOP, preop); - REGWRITE16(ICH7_REG_OPTYPE, optype); - REGWRITE32(ICH7_REG_OPMENU, opmenu[0]); - REGWRITE32(ICH7_REG_OPMENU + 4, opmenu[1]); + rmmio_writew(preop, ich_spibar + ICH7_REG_PREOP); + rmmio_writew(optype, ich_spibar + ICH7_REG_OPTYPE); + rmmio_writew(opmenu[0], ich_spibar + ICH7_REG_OPMENU); + rmmio_writew(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4); break; case SPI_CONTROLLER_ICH9: - REGWRITE16(ICH9_REG_PREOP, preop); - REGWRITE16(ICH9_REG_OPTYPE, optype); - REGWRITE32(ICH9_REG_OPMENU, opmenu[0]); - REGWRITE32(ICH9_REG_OPMENU + 4, opmenu[1]); + rmmio_writew(preop, ich_spibar + ICH9_REG_PREOP); + rmmio_writew(optype, ich_spibar + ICH9_REG_OPTYPE); + rmmio_writew(opmenu[0], ich_spibar + ICH9_REG_OPMENU); + rmmio_writew(opmenu[1], ich_spibar + ICH9_REG_OPMENU + 4); break; default: msg_perr("%s: unsupported chipset\n", __func__); @@ -409,16 +409,20 @@ { switch (spi_controller) { case SPI_CONTROLLER_ICH7: - mmio_writel(minaddr, ich_spibar + 0x50); + rmmio_writel(minaddr, ich_spibar + 0x50); ichspi_bbar = mmio_readl(ich_spibar + 0x50); - /* We don't have any option except complaining. */ + /* We don't have any option except complaining. And if the write + * failed, the restore will fail as well, so no problem there. + */ if (ichspi_bbar != minaddr) msg_perr("Setting BBAR failed!\n"); break; case SPI_CONTROLLER_ICH9: - mmio_writel(minaddr, ich_spibar + 0xA0); + rmmio_writel(minaddr, ich_spibar + 0xA0); ichspi_bbar = mmio_readl(ich_spibar + 0xA0); - /* We don't have any option except complaining. */ + /* We don't have any option except complaining. And if the write + * failed, the restore will fail as well, so no problem there. + */ if (ichspi_bbar != minaddr) msg_perr("Setting BBAR failed!\n"); break; Index: flashrom-mmio_shutdown_restore/nicintel_spi.c =================================================================== --- flashrom-mmio_shutdown_restore/nicintel_spi.c (Revision 1234) +++ flashrom-mmio_shutdown_restore/nicintel_spi.c (Arbeitskopie) @@ -149,6 +149,7 @@ nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, 4096); + /* Automatic restore is not possible because we only change two bits. */ tmp = pci_mmio_readl(nicintel_spibar + EECD); tmp &= ~FLASH_WRITES_DISABLED; tmp |= FLASH_WRITES_ENABLED; @@ -168,6 +169,7 @@ { uint32_t tmp; + /* Automatic restore is not possible because we only change two bits. */ tmp = pci_mmio_readl(nicintel_spibar + EECD); tmp &= ~FLASH_WRITES_ENABLED; tmp |= FLASH_WRITES_DISABLED; Index: flashrom-mmio_shutdown_restore/programmer.h =================================================================== --- flashrom-mmio_shutdown_restore/programmer.h (Revision 1234) +++ flashrom-mmio_shutdown_restore/programmer.h (Arbeitskopie) @@ -311,6 +311,9 @@ #define pci_mmio_readb mmio_le_readb #define pci_mmio_readw mmio_le_readw #define pci_mmio_readl mmio_le_readl +void rmmio_writeb(uint8_t val, void *addr); +void rmmio_writew(uint16_t val, void *addr); +void rmmio_writel(uint32_t val, void *addr); /* programmer.c */ int noop_shutdown(void); -- http://www.hailfinger.org/

2 4

[commit] r1292 - trunk
by repository service 03 May '11

03 May '11

Author: hailfinger Date: Tue May 3 23:49:41 2011 New Revision: 1292 URL: http://flashrom.org/trac/flashrom/changeset/1292 Log: Revert MMIO space writes on shutdown as needed. Reversible MMIO space writes now use rmmio_write*(). Reversible PCI MMIO space writes now use pci_rmmio_write*(). If a MMIO value needs to be queued for restore without writing it, use rmmio_val*(). MMIO space writes which are one-shot (e.g. communication with some chip) should continue to use the permanent mmio_write* variants. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> David tested it successfully on some NM10/ICH7 platforms which switch between SPI and LPC targets (x86 BIOS ROM vs. EC firmware ROM). Acked-by: David Hendricks <dhendrix(a)google.com> Modified: trunk/hwaccess.c trunk/ichspi.c trunk/nicintel_spi.c trunk/programmer.h trunk/satamv.c Modified: trunk/hwaccess.c ============================================================================== --- trunk/hwaccess.c Sat Apr 30 01:53:09 2011 (r1291) +++ trunk/hwaccess.c Tue May 3 23:49:41 2011 (r1292) @@ -184,3 +184,104 @@ { return le_to_cpu32(mmio_readl(addr)); } + +enum mmio_write_type { + mmio_write_type_b, + mmio_write_type_w, + mmio_write_type_l, +}; + +struct undo_mmio_write_data { + void *addr; + int reg; + enum mmio_write_type type; + union { + uint8_t bdata; + uint16_t wdata; + uint32_t ldata; + }; +}; + +void undo_mmio_write(void *p) +{ + struct undo_mmio_write_data *data = p; + msg_pdbg("Restoring MMIO space at %p\n", data->addr); + switch (data->type) { + case mmio_write_type_b: + mmio_writeb(data->bdata, data->addr); + break; + case mmio_write_type_w: + mmio_writew(data->wdata, data->addr); + break; + case mmio_write_type_l: + mmio_writel(data->ldata, data->addr); + break; + } + /* p was allocated in register_undo_mmio_write. */ + free(p); +} + +#define register_undo_mmio_write(a, c) \ +{ \ + struct undo_mmio_write_data *undo_mmio_write_data; \ + undo_mmio_write_data = malloc(sizeof(struct undo_mmio_write_data)); \ + undo_mmio_write_data->addr = a; \ + undo_mmio_write_data->type = mmio_write_type_##c; \ + undo_mmio_write_data->c##data = mmio_read##c(a); \ + register_shutdown(undo_mmio_write, undo_mmio_write_data); \ +} + +#define register_undo_mmio_writeb(a) register_undo_mmio_write(a, b) +#define register_undo_mmio_writew(a) register_undo_mmio_write(a, w) +#define register_undo_mmio_writel(a) register_undo_mmio_write(a, l) + +void rmmio_writeb(uint8_t val, void *addr) +{ + register_undo_mmio_writeb(addr); + mmio_writeb(val, addr); +} + +void rmmio_writew(uint16_t val, void *addr) +{ + register_undo_mmio_writew(addr); + mmio_writew(val, addr); +} + +void rmmio_writel(uint32_t val, void *addr) +{ + register_undo_mmio_writel(addr); + mmio_writel(val, addr); +} + +void rmmio_le_writeb(uint8_t val, void *addr) +{ + register_undo_mmio_writeb(addr); + mmio_le_writeb(val, addr); +} + +void rmmio_le_writew(uint16_t val, void *addr) +{ + register_undo_mmio_writew(addr); + mmio_le_writew(val, addr); +} + +void rmmio_le_writel(uint32_t val, void *addr) +{ + register_undo_mmio_writel(addr); + mmio_le_writel(val, addr); +} + +void rmmio_valb(void *addr) +{ + register_undo_mmio_writeb(addr); +} + +void rmmio_valw(void *addr) +{ + register_undo_mmio_writew(addr); +} + +void rmmio_vall(void *addr) +{ + register_undo_mmio_writel(addr); +} Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Sat Apr 30 01:53:09 2011 (r1291) +++ trunk/ichspi.c Tue May 3 23:49:41 2011 (r1292) @@ -163,7 +163,7 @@ static int find_opcode(OPCODES *op, uint8_t opcode); static int find_preop(OPCODES *op, uint8_t preop); static int generate_opcodes(OPCODES * op); -static int program_opcodes(OPCODES * op); +static int program_opcodes(OPCODES *op, int enable_undo); static int run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data); @@ -269,7 +269,7 @@ int oppos=2; // use original JEDEC_BE_D8 offset curopcodes->opcode[oppos].opcode = opcode; curopcodes->opcode[oppos].spi_type = spi_type; - program_opcodes(curopcodes); + program_opcodes(curopcodes, 0); oppos = find_opcode(curopcodes, opcode); msg_pdbg ("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos); return oppos; @@ -357,7 +357,7 @@ return 0; } -int program_opcodes(OPCODES * op) +static int program_opcodes(OPCODES *op, int enable_undo) { uint8_t a; uint16_t preop, optype; @@ -391,16 +391,30 @@ switch (spi_controller) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: - REGWRITE16(ICH7_REG_PREOP, preop); - REGWRITE16(ICH7_REG_OPTYPE, optype); - REGWRITE32(ICH7_REG_OPMENU, opmenu[0]); - REGWRITE32(ICH7_REG_OPMENU + 4, opmenu[1]); + /* Register undo only for enable_undo=1, i.e. first call. */ + if (enable_undo) { + rmmio_valw(ich_spibar + ICH7_REG_PREOP); + rmmio_valw(ich_spibar + ICH7_REG_OPTYPE); + rmmio_vall(ich_spibar + ICH7_REG_OPMENU); + rmmio_vall(ich_spibar + ICH7_REG_OPMENU + 4); + } + mmio_writew(preop, ich_spibar + ICH7_REG_PREOP); + mmio_writew(optype, ich_spibar + ICH7_REG_OPTYPE); + mmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU); + mmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4); break; case SPI_CONTROLLER_ICH9: - REGWRITE16(ICH9_REG_PREOP, preop); - REGWRITE16(ICH9_REG_OPTYPE, optype); - REGWRITE32(ICH9_REG_OPMENU, opmenu[0]); - REGWRITE32(ICH9_REG_OPMENU + 4, opmenu[1]); + /* Register undo only for enable_undo=1, i.e. first call. */ + if (enable_undo) { + rmmio_valw(ich_spibar + ICH9_REG_PREOP); + rmmio_valw(ich_spibar + ICH9_REG_OPTYPE); + rmmio_vall(ich_spibar + ICH9_REG_OPMENU); + rmmio_vall(ich_spibar + ICH9_REG_OPMENU + 4); + } + mmio_writew(preop, ich_spibar + ICH9_REG_PREOP); + mmio_writew(optype, ich_spibar + ICH9_REG_OPTYPE); + mmio_writel(opmenu[0], ich_spibar + ICH9_REG_OPMENU); + mmio_writel(opmenu[1], ich_spibar + ICH9_REG_OPMENU + 4); break; default: msg_perr("%s: unsupported chipset\n", __func__); @@ -426,9 +440,11 @@ msg_pdbg("Reserved bits in BBAR not zero: 0x%04x", ichspi_bbar); ichspi_bbar |= minaddr; - mmio_writel(ichspi_bbar, ich_spibar + 0x50); + rmmio_writel(ichspi_bbar, ich_spibar + 0x50); ichspi_bbar = mmio_readl(ich_spibar + 0x50); - /* We don't have any option except complaining. */ + /* We don't have any option except complaining. And if the write + * failed, the restore will fail as well, so no problem there. + */ if (ichspi_bbar != minaddr) msg_perr("Setting BBAR failed!\n"); break; @@ -438,9 +454,11 @@ msg_pdbg("Reserved bits in BBAR not zero: 0x%04x", ichspi_bbar); ichspi_bbar |= minaddr; - mmio_writel(ichspi_bbar, ich_spibar + 0xA0); + rmmio_writel(ichspi_bbar, ich_spibar + 0xA0); ichspi_bbar = mmio_readl(ich_spibar + 0xA0); - /* We don't have any option except complaining. */ + /* We don't have any option except complaining. And if the write + * failed, the restore will fail as well, so no problem there. + */ if (ichspi_bbar != minaddr) msg_perr("Setting BBAR failed!\n"); break; @@ -470,7 +488,7 @@ } else { msg_pdbg("Programming OPCODES... "); curopcodes_done = &O_ST_M25P; - rc = program_opcodes(curopcodes_done); + rc = program_opcodes(curopcodes_done, 1); /* Technically not part of opcode init, but it allows opcodes * to run without transaction errors by setting the lowest * allowed address to zero. Modified: trunk/nicintel_spi.c ============================================================================== --- trunk/nicintel_spi.c Sat Apr 30 01:53:09 2011 (r1291) +++ trunk/nicintel_spi.c Tue May 3 23:49:41 2011 (r1292) @@ -148,6 +148,11 @@ nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, 4096); + /* Automatic restore of EECD on shutdown is not possible because EECD + * does not only contain FLASH_WRITES_DISABLED|FLASH_WRITES_ENABLED, + * but other bits with side effects as well. Those other bits must be + * left untouched. + */ tmp = pci_mmio_readl(nicintel_spibar + EECD); tmp &= ~FLASH_WRITES_DISABLED; tmp |= FLASH_WRITES_ENABLED; @@ -167,6 +172,9 @@ { uint32_t tmp; + /* Disable writes manually. See the comment about EECD in + * nicintel_spi_init() for details. + */ tmp = pci_mmio_readl(nicintel_spibar + EECD); tmp &= ~FLASH_WRITES_ENABLED; tmp |= FLASH_WRITES_DISABLED; Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Sat Apr 30 01:53:09 2011 (r1291) +++ trunk/programmer.h Tue May 3 23:49:41 2011 (r1292) @@ -316,6 +316,18 @@ #define pci_mmio_readb mmio_le_readb #define pci_mmio_readw mmio_le_readw #define pci_mmio_readl mmio_le_readl +void rmmio_writeb(uint8_t val, void *addr); +void rmmio_writew(uint16_t val, void *addr); +void rmmio_writel(uint32_t val, void *addr); +void rmmio_le_writeb(uint8_t val, void *addr); +void rmmio_le_writew(uint16_t val, void *addr); +void rmmio_le_writel(uint32_t val, void *addr); +#define pci_rmmio_writeb rmmio_le_writeb +#define pci_rmmio_writew rmmio_le_writew +#define pci_rmmio_writel rmmio_le_writel +void rmmio_valb(void *addr); +void rmmio_valw(void *addr); +void rmmio_vall(void *addr); /* programmer.c */ int noop_shutdown(void); Modified: trunk/satamv.c ============================================================================== --- trunk/satamv.c Sat Apr 30 01:53:09 2011 (r1291) +++ trunk/satamv.c Tue May 3 23:49:41 2011 (r1292) @@ -102,8 +102,7 @@ msg_pspew("BAR2Sz=0x%01x\n", (tmp >> 19) & 0x7); tmp &= 0xffffffc0; tmp |= 0x0000001f; - /* FIXME: This needs to be an auto-reversible write. */ - pci_mmio_writel(tmp, mv_bar + PCI_BAR2_CONTROL); + pci_rmmio_writel(tmp, mv_bar + PCI_BAR2_CONTROL); /* Enable flash: GPIO Port Control Register 0x104f0 */ tmp = pci_mmio_readl(mv_bar + GPIO_PORT_CONTROL); @@ -114,8 +113,7 @@ "values!\n"); tmp &= 0xfffffffc; tmp |= 0x2; - /* FIXME: This needs to be an auto-reversible write. */ - pci_mmio_writel(tmp, mv_bar + GPIO_PORT_CONTROL); + pci_rmmio_writel(tmp, mv_bar + GPIO_PORT_CONTROL); /* Get I/O BAR location. */ tmp = pci_read_long(pcidev_dev, PCI_BASE_ADDRESS_2) &

1 0

RIVA TNT2 Model 64/Model 64 Pro
by Benjamin Henrion 03 May '11

03 May '11

Hi, I own such a card: RIVA TNT2 Model 64/Model 64 Pro http://www.zoobab.com/flashrom-tnt2-m64 Which is listed by the flashrom wiki as a working programmer. Any idea how to connect a DIP32 over this card? There is a Holtek Eeprom on it, and I would like to know if I could flash LPC chips with (the bus type seems to be CHIP_BUSTYPE_PARALLEL). Any idea? Best, -- Benjamin Henrion <bhenrion at ffii.org> FFII Brussels - +32-484-566109 - +32-2-4148403 "In July 2005, after several failed attempts to legalise software patents in Europe, the patent establishment changed its strategy. Instead of explicitly seeking to sanction the patentability of software, they are now seeking to create a central European patent court, which would establish and enforce patentability rules in their favor, without any possibility of correction by competing courts or democratically elected legislators."

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Re: [flashrom] [PATCH 2/6] some additional comments for ichspi.c
by Michael Karcher 02 May '11

02 May '11

Am Freitag, den 01.04.2011, 14:33 +0200 schrieb Stefan Tauner: > - uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1 > + uint8_t atomic; //Use preop: (0: none, 1: preop0 only, 2: both) Nack. The ICH10 data sheet is explicit on SPOP selecting "one of the two programmed prefix opcodes". So 2 does not mean both, but preop1. Regards, Michael Karcher

2 1

Supermicro X8DTU-F
by Jimmie Tauriainen 02 May '11

02 May '11

-- Jimmie Tauriainen South Pole AB Phone: +46 8 56237100 Anderstorpsvägen 16 Mobile: +46 707 777651 SE - 17154 Solna e-mail: jimmie(a)southpole.se www.southpole.se

1 0

Re: [flashrom] GigaByte GA-K8NS
by Denis S. Soldatov 02 May '11

02 May '11

В Сб., 30/04/2011 в 14:27 +0200, Stefan Tauner пишет: > hey > > you quit irc yesterday... so i fear that you have tried to reboot > although we warned you multiply times. > we would like to hear from you again in any case to know what happened > and to be able to try the patch we have created for you. > Hi, Thanks for your support today can not, but tomorrow will try as soon as the time and immediately accomplish your goal in the channel irc

1 0

here's the now completely fixed patch.
by Brandon Dowdy 01 May '11

01 May '11

I think this patch is fixed now.

1 0

Gigabyte M68M-S2P Support
by Sascha Conradi 30 Apr '11

30 Apr '11

Hi.. I call for support for Gigabyte M68M-S2P thanks..

1 0

Flash Marvell 91xx Config PROM
by PETER ANDERSON 30 Apr '11

30 Apr '11

Hi, I have a Asus motherboard (p7p55d-e pro) with (I believe) an onboard Marvell 9120 Sata 3 controller. I also have an add on card Sata controller with a Marvell 9123 chip. When I updated my firmware, both devices were found and updated but upon reboot the "on board" Marvell Controller is bricked. It no longer appears in the boot up/bios sequence. I'm looking for a way to flash the chip back preferably in circuit. Is this something flashrom can do? The Marvell Flash device is macronix MX25L4005A. Thanks, Pete I'm pretty sure this is the controller that's not responding 0a:00.1 IDE interface [0101]: Device [1b4b:91a4] (rev 11) (prog-if 8f [Master SecP SecO PriP PriO]) Subsystem: Device [1b4b:91a4] Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin B routed to IRQ 16 Region 0: I/O ports at dc00 [size=8] Region 1: I/O ports at d880 [size=4] Region 2: I/O ports at d800 [size=8] Region 3: I/O ports at d480 [size=4] Region 4: I/O ports at d400 [size=16] Region 5: Memory at f7effc00 (32-bit, non-prefetchable) [size=16] Expansion ROM at f7ee0000 [disabled] [size=64K] Capabilities: <access denied> 00: 4b 1b a4 91 03 01 10 00 11 8f 01 01 08 00 80 00 10: 01 dc 00 00 81 d8 00 00 01 d8 00 00 81 d4 00 00 20: 01 d4 00 00 00 fc ef f7 00 00 00 00 4b 1b a4 91 30: 00 00 ee f7 40 00 00 00 00 00 00 00 0a 02 00 0

1 0

FAILED: motherboard update bios fail (gigabyte-X58A-UD3R (rev. 2.0))
by healthly 30 Apr '11

30 Apr '11

Dear flashrom, I use flashrom to update bios under centos5.5.then there is following output(please help me!) : flashrom v0.9.3-r1288 on Linux 2.6.18-194.26.1.el5xen (x86_64), built with libpci 2.2.3, GCC 4.1.2 20080704 (Red Hat 4.1.2-48), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1414M loops per second, 10 myus = 11 us, 100 myus = 101 us, 1000 myus = 999 us, 10000 myus = 9991 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Gigabyte Technology Co., Ltd." DMI string system-product-name: "X58A-UD3R" DMI string system-version: " " DMI string baseboard-manufacturer: "Gigabyte Technology Co., Ltd." DMI string baseboard-product-name: "X58A-UD3R" DMI string baseboard-version: "x.x" DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8720. Found chipset "Intel ICH10R", enabling flash write... chipset PCI ID is 8086:3a16, 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x4 0x7fffffff/0x7fffffff FWH IDSEL: 0x5 0x7fffffff/0x7fffffff FWH IDSEL: 0x6 0x7fffffff/0x7fffffff FWH IDSEL: 0x7 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 Root Complex Register Block address = 0xfed1c000 GCS = 0x464: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0x0000 (HSFS) FLOCKDN 0, FDV 0, FDOPSS 0, SCIP 0, BERASE 0, AEL 0, FCERR 0, FDONE 0 0x50: 0x0000ffff (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff 0x54: 0x00001fff (FREG0: Flash Descriptor) Flash Descriptor region is unused. 0x58: 0x00001fff (FREG1: BIOS) BIOS region is unused. 0x5C: 0x00001fff (FREG2: Management Engine) Management Engine region is unused. 0x60: 0x00001fff (FREG3: Gigabit Ethernet) Gigabit Ethernet region is unused. 0x64: 0x00001fff (FREG4: Platform Data) Platform Data region is unused. 0x74: 0x00000000 (PR0) 0x78: 0x00000000 (PR1) 0x7C: 0x00000000 (PR2) 0x80: 0x00000000 (PR3) 0x84: 0x00000000 (PR4) 0x90: 0x04 (SSFS) AEL 0, FCERR 0, FDONE 1, SCIP 0 0x91: 0x007f10 (SSFC) 0x94: 0x5006 (PREOP) 0x96: 0x462b (OPTYPE) 0x98: 0x05ab0302 (OPMENU) 0x9C: 0xc79f0190 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xB0: 0x00000000 (FDOC) Programming OPCODES... program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 done SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: FWH,SPI. No IT87* serial flash segment enabled. Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F016D, 2048 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F040B, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F080B, 1024 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29LV001BB, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29LV001BT, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29LV002BB, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29LV002BT, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29LV004BB, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29LV004BT, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29LV008BB, 1024 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29LV008BT, 1024 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29LV040B, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29LV081B, 1024 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMIC A25L05PT, 64 KB: RDID returned 0xc2 0x20 0x15 0xc2. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L05PU, 64 KB: RDID returned 0xc2 0x20 0x15 0xc2. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L10PT, 128 KB: RDID returned 0xc2 0x20 0x15 0xc2. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L10PU, 128 KB: RDID returned 0xc2 0x20 0x15 0xc2. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L20PT, 256 KB: RDID returned 0xc2 0x20 0x15 0xc2. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L20PU, 256 KB: RDID returned 0xc2 0x20 0x15 0xc2. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L40PT, 512 KB: RDID returned 0xc2 0x20 0x15 0xc2. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L40PU, 512 KB: RDID returned 0xc2 0x20 0x15 0xc2. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L80P, 1024 KB: RDID returned 0xc2 0x20 0x15 0xc2. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L16PT, 2048 KB: RDID returned 0xc2 0x20 0x15 0xc2. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L16PU, 2048 KB: RDID returned 0xc2 0x20 0x15 0xc2. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L512, 64 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L010, 128 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L020, 256 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L040, 512 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L080, 1024 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L016, 2048 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25L032, 4096 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A25LQ032, 4096 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for AMIC A29002B, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMIC A29002T, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMIC A29040B, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for AMIC A49LF040A, 512 KB: skipped. Host bus type FWH,SPI and chip bus type LPC are incompatible. Probing for Atmel AT25DF021, 256 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT25DF041A, 512 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT25DF081, 1024 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT25DF081A, 1024 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT25DF161, 2048 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT25DF321, 4096 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT25DF321A, 4096 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT25DF641, 8192 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT25DQ161, 2048 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT25F512B, 64 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT25FS010, 128 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT25FS040, 512 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT26DF041, 512 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT26DF081A, 1024 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT26DF161, 2048 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT26DF161A, 2048 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT26F004, 512 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT29C512, 64 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Atmel AT29C010A, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Atmel AT29C020, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Atmel AT29C040A, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Atmel AT45CS1282, 16896 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT45DB011D, 128 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT45DB021D, 256 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT45DB041D, 512 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT45DB081D, 1024 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT45DB161D, 2048 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT45DB321C, 4224 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT45DB321D, 4096 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT45DB642D, 8192 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Atmel AT49BV512, 64 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Atmel AT49F020, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N), 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Bright BM29F040, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for EMST F49B002UA, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for EMST F25L008A, 1024 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B05, 64 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B05T, 64 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B10, 128 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B10T, 128 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B20, 256 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B20T, 256 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B40, 512 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B40T, 512 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B80, 1024 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B80T, 1024 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B16, 2048 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B16T, 2048 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B32, 4096 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B32T, 4096 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B64, 8192 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25B64T, 8192 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25D16, 2048 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25F05, 64 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25F10, 128 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25F20, 256 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25F40, 512 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25F80, 1024 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25F16, 2048 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN25F32, 4096 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Eon EN29F010, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Eon EN29F002(A)(N)B, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Eon EN29F002(A)(N)T, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Hyundai HY29F002T, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Hyundai HY29F002B, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Hyundai HY29F040A, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F001BN/BX-B, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F001BN/BX-T, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F002BC/BL/BV/BX-T, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F008S3/S5/SC, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F004B5/BE/BV/BX-B, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F004B5/BE/BV/BX-T, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F400BV/BX/CE/CV-B, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F400BV/BX/CE/CV-T, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x24, id2 0xdb, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0x25, id2 0x96, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Macronix MX25L1005, 128 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Macronix MX25L2005, 256 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Macronix MX25L4005, 512 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Macronix MX25L8005, 1024 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Macronix MX25L1605, 2048 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found chip "Macronix MX25L1605" (2048 KB, SPI) at physical address 0xffe00000. Probing for Macronix MX25L1635D, 2048 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Macronix MX25L1635E, 2048 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Macronix MX25L3205, 4096 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Macronix MX25L3235D, 4096 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Macronix MX25L6405, 8192 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Macronix MX25L12805, 16384 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29F040, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for MoselVitelic V29C51000B, 64 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for MoselVitelic V29C51000T, 64 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for MoselVitelic V29C51400B, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for MoselVitelic V29C51400T, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for MoselVitelic V29LC51000, 64 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for MoselVitelic V29LC51001, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for MoselVitelic V29LC51002, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Numonyx M25PE10, 128 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Numonyx M25PE20, 256 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Numonyx M25PE40, 512 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Numonyx M25PE80, 1024 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Numonyx M25PE16, 2048 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for PMC Pm25LV010, 128 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for PMC Pm25LV016B, 2048 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for PMC Pm25LV020, 256 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for PMC Pm25LV040, 512 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for PMC Pm25LV080B, 1024 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for PMC Pm25LV512, 64 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for PMC Pm29F002T, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for PMC Pm29F002B, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for PMC Pm39LV020, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for PMC Pm39LV040, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0x7d, id2 0x80, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0x24, id2 0xdb, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0x25, id2 0x96, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL004A, 512 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Spansion S25FL008A, 1024 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Spansion S25FL016A, 2048 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Spansion S25FL032A, 4096 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Spansion S25FL064A, 8192 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for SST SST25VF010.REMS, 128 KB: REMS returned c2 14. probe_spi_rems: id1 0xc2, id2 0x14 Probing for SST SST25VF016B, 2048 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for SST SST25VF032B, 4096 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for SST SST25VF064C, 8192 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for SST SST25VF040.REMS, 512 KB: REMS returned c2 14. probe_spi_rems: id1 0xc2, id2 0x14 Probing for SST SST25VF040B, 512 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for SST SST25LF040A.RES, 512 KB: program_opcodes: preop=5006 optype=462b opmenu=05ab0302c79f0190 on-the-fly OPCODE (0xAB) re-programmed, op-pos=2 RES returned 0x14 0x14. probe_spi_res2: id1 0x14, id2 0x14 Probing for SST SST25VF040B.REMS, 512 KB: REMS returned c2 14. probe_spi_rems: id1 0xc2, id2 0x14 Probing for SST SST25VF080B, 1024 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for SST SST28SF040A, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST29EE010, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST29LE010, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST29EE020A, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST29LE020, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF512, 64 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF010A, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF020A, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF040, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF512, 64 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF010, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF020, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF040, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF080, 1024 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0x7d, id2 0x80, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0x27, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0x24, id2 0xdb, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0x24, id2 0xdb, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0x25, id2 0x96, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0x25, id2 0x96, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 KB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 KB: skipped. Host bus type FWH,SPI and chip bus type LPC are incompatible. Probing for SST SST49LF020A, 256 KB: skipped. Host bus type FWH,SPI and chip bus type LPC are incompatible. Probing for SST SST49LF040, 512 KB: skipped. Host bus type FWH,SPI and chip bus type LPC are incompatible. Probing for SST SST49LF040B, 512 KB: skipped. Host bus type FWH,SPI and chip bus type LPC are incompatible. Probing for SST SST49LF080A, 1024 KB: skipped. Host bus type FWH,SPI and chip bus type LPC are incompatible. Probing for SST SST49LF160C, 2048 KB: skipped. Host bus type FWH,SPI and chip bus type LPC are incompatible. Probing for ST M25P05-A, 64 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for ST M25P05.RES, 64 KB: RDID returned 0xc2 0x20 0x15. Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for ST M25P10.RES, 128 KB: RDID returned 0xc2 0x20 0x15. Ignoring RES in favour of RDID. Probing for ST M25P20, 256 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for ST M25P40, 512 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for ST M25P40-old, 512 KB: RDID returned 0xc2 0x20 0x15. Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for ST M25P16, 2048 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for ST M25P32, 4096 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for ST M25P64, 8192 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for ST M25P128, 16384 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for ST M25PX16, 2048 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for ST M25PX32, 4096 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for ST M25PX64, 8192 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for ST M29F002B, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29F040B, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29F400BB, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29F400BT, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29W010B, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29W040B, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29W512B, 64 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x24, id2 0xdb, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x24, id2 0xdb, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0x25, id2 0x96, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0x25, id2 0x96, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0x7d, id2 0x80, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 KB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x24, id2 0xdb, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0x25, id2 0x96, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 KB: skipped. Host bus type FWH,SPI and chip bus type LPC are incompatible. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W25Q80, 1024 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Winbond W25Q16, 2048 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Winbond W25Q32, 4096 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Winbond W25Q64, 8192 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Winbond W25x10, 128 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Winbond W25x20, 256 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Winbond W25x40, 512 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Winbond W25x80, 1024 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Winbond W25x16, 2048 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Winbond W25x32, 4096 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Winbond W25x64, 8192 KB: RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W29C020(C)/W29C022, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W29C040/P, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W39L040, 512 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W39V040A, 512 KB: skipped. Host bus type FWH,SPI and chip bus type LPC are incompatible. Probing for Winbond W39V040B, 512 KB: skipped. Host bus type FWH,SPI and chip bus type LPC are incompatible. Probing for Winbond W39V040C, 512 KB: skipped. Host bus type FWH,SPI and chip bus type LPC are incompatible. Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0x24, id2 0xdb, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 KB: probe_jedec_common: id1 0x24, id2 0xdb, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 KB: probe_jedec_common: id1 0x24, id2 0xdb, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 KB: skipped. Host bus type FWH,SPI and chip bus type LPC are incompatible. Probing for Winbond W49F002U/N, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W49F020, 256 KB: skipped. Host bus type FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W49V002A, 256 KB: skipped. Host bus type FWH,SPI and chip bus type LPC are incompatible. Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0x7d, id2 0x80, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 KB: probe_jedec_common: id1 0x25, id2 0x96, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 KB: probe_jedec_common: id1 0x24, id2 0xdb, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC unknown AMIC SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xc2 0x20 0x15 0xc2. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Not unmapping zero size at 0xffffffffffffffff Probing for Atmel unknown Atmel SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Not unmapping zero size at 0xffffffffffffffff Probing for Eon unknown Eon SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Not unmapping zero size at 0xffffffffffffffff Probing for Macronix unknown Macronix SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Not unmapping zero size at 0xffffffffffffffff Probing for PMC unknown PMC SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Not unmapping zero size at 0xffffffffffffffff Probing for SST unknown SST SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Not unmapping zero size at 0xffffffffffffffff Probing for ST unknown ST SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Not unmapping zero size at 0xffffffffffffffff Probing for Sanyo unknown Sanyo SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Not unmapping zero size at 0xffffffffffffffff Probing for Generic unknown SPI chip (RDID), 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xc2 0x20 0x15. probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Not unmapping zero size at 0xffffffffffffffff Probing for Generic unknown SPI chip (REMS), 0 KB: Not mapping flash chip, zero size at 0x00000000. REMS returned c2 14. probe_spi_rems: id1 0xc2, id2 0x14 Not unmapping zero size at 0xffffffffffffffff Flash image seems to be a legacy BIOS. Disabling checks. Reading old flash chip contents... Erasing and writing flash chip... Looking at blockwise erase function 0... trying... 0x000000-0x000fff:S, 0x001000-0x001fff:S, 0x002000-0x002fff:S, 0x003000-0x003fff:S, 0x004000-0x004fff:S, 0x005000-0x005fff:S, 0x006000-0x006fff:S, 0x007000-0x007fff:S, 0x008000-0x008fff:S, 0x009000-0x009fff:S, 0x00a000-0x00afff:S, 0x00b000-0x00bfff:S, 0x00c000-0x00cfff:S, 0x00d000-0x00dfff:S, 0x00e000-0x00efff:S, 0x00f000-0x00ffff:S, 0x010000-0x010fff:S, 0x011000-0x011fff:S, 0x012000-0x012fff:S, 0x013000-0x013fff:S, 0x014000-0x014fff:S, 0x015000-0x015fff:S, 0x016000-0x016fff:S, 0x017000-0x017fff:S, 0x018000-0x018fff:S, 0x019000-0x019fff:S, 0x01a000-0x01afff:S, 0x01b000-0x01bfff:S, 0x01c000-0x01cfff:S, 0x01d000-0x01dfff:S, 0x01e000-0x01efff:S, 0x01f000-0x01ffff:S, 0x020000-0x020fff:S, 0x021000-0x021fff:S, 0x022000-0x022fff:S, 0x023000-0x023fff:S, 0x024000-0x024fff:S, 0x025000-0x025fff:S, 0x026000-0x026fff:S, 0x027000-0x027fff:S, 0x028000-0x028fff:S, 0x029000-0x029fff:S, 0x02a000-0x02afff:S, 0x02b000-0x02bfff:S, 0x02c000-0x02cfff:S, 0x02d000-0x02dfff:S, 0x02e000-0x02efff:S, 0x02f000-0x02ffff:S, 0x030000-0x030fff:S, 0x031000-0x031fff:S, 0x032000-0x032fff:S, 0x033000-0x033fff:S, 0x034000-0x034fff:S, 0x035000-0x035fff:S, 0x036000-0x036fff:S, 0x037000-0x037fff:S, 0x038000-0x038fff:S, 0x039000-0x039fff:S, 0x03a000-0x03afff:S, 0x03b000-0x03bfff:S, 0x03c000-0x03cfff:S, 0x03d000-0x03dfff:S, 0x03e000-0x03efff:S, 0x03f000-0x03ffff:S, 0x040000-0x040fff:S, 0x041000-0x041fff:S, 0x042000-0x042fff:S, 0x043000-0x043fff:S, 0x044000-0x044fff:S, 0x045000-0x045fff:S, 0x046000-0x046fff:S, 0x047000-0x047fff:S, 0x048000-0x048fff:S, 0x049000-0x049fff:S, 0x04a000-0x04afff:S, 0x04b000-0x04bfff:S, 0x04c000-0x04cfff:S, 0x04d000-0x04dfff:S, 0x04e000-0x04efff:S, 0x04f000-0x04ffff:S, 0x050000-0x050fff:S, 0x051000-0x051fff:S, 0x052000-0x052fff:S, 0x053000-0x053fff:S, 0x054000-0x054fff:S, 0x055000-0x055fff:S, 0x056000-0x056fff:S, 0x057000-0x057fff:S, 0x058000-0x058fff:S, 0x059000-0x059fff:S, 0x05a000-0x05afff:S, 0x05b000-0x05bfff:S, 0x05c000-0x05cfff:S, 0x05d000-0x05dfff:S, 0x05e000-0x05efff:S, 0x05f000-0x05ffff:S, 0x060000-0x060fff:S, 0x061000-0x061fff:S, 0x062000-0x062fff:S, 0x063000-0x063fff:S, 0x064000-0x064fff:S, 0x065000-0x065fff:S, 0x066000-0x066fff:S, 0x067000-0x067fff:S, 0x068000-0x068fff:S, 0x069000-0x069fff:S, 0x06a000-0x06afff:S, 0x06b000-0x06bfff:S, 0x06c000-0x06cfff:S, 0x06d000-0x06dfff:S, 0x06e000-0x06efff:S, 0x06f000-0x06ffff:S, 0x070000-0x070fff:S, 0x071000-0x071fff:S, 0x072000-0x072fff:S, 0x073000-0x073fff:S, 0x074000-0x074fff:S, 0x075000-0x075fff:S, 0x076000-0x076fff:S, 0x077000-0x077fff:S, 0x078000-0x078fff:S, 0x079000-0x079fff:S, 0x07a000-0x07afff:S, 0x07b000-0x07bfff:S, 0x07c000-0x07cfff:S, 0x07d000-0x07dfff:S, 0x07e000-0x07efff:S, 0x07f000-0x07ffff:S, 0x080000-0x080fff:W, 0x081000-0x081fff:W, 0x082000-0x082fff:W, 0x083000-0x083fff:W, 0x084000-0x084fff:W, 0x085000-0x085fff:W, 0x086000-0x086fff:W, 0x087000-0x087fff:W, 0x088000-0x088fff:W, 0x089000-0x089fff:W, 0x08a000-0x08afff:W, 0x08b000-0x08bfff:W, 0x08c000-0x08cfff:W, 0x08d000-0x08dfff:W, 0x08e000-0x08efff:W, 0x08f000-0x08ffff:W, 0x090000-0x090fff:W, 0x091000-0x091fff:W, 0x092000-0x092fff:W, 0x093000-0x093fff:W, 0x094000-0x094fff:W, 0x095000-0x095fff:W, 0x096000-0x096fff:W, 0x097000-0x097fff:W, 0x098000-0x098fff:W, 0x099000-0x099fff:W, 0x09a000-0x09afff:W, 0x09b000-0x09bfff:W, 0x09c000-0x09cfff:W, 0x09d000-0x09dfff:W, 0x09e000-0x09efff:W, 0x09f000-0x09ffff:W, 0x0a0000-0x0a0fff:W, 0x0a1000-0x0a1fff:W, 0x0a2000-0x0a2fff:W, 0x0a3000-0x0a3fff:W, 0x0a4000-0x0a4fff:W, 0x0a5000-0x0a5fff:W, 0x0a6000-0x0a6fff:W, 0x0a7000-0x0a7fff:W, 0x0a8000-0x0a8fff:W, 0x0a9000-0x0a9fff:W, 0x0aa000-0x0aafff:W, 0x0ab000-0x0abfff:W, 0x0ac000-0x0acfff:W, 0x0ad000-0x0adfff:W, 0x0ae000-0x0aefff:W, 0x0af000-0x0affff:W, 0x0b0000-0x0b0fff:W, 0x0b1000-0x0b1fff:W, 0x0b2000-0x0b2fff:W, 0x0b3000-0x0b3fff:W, 0x0b4000-0x0b4fff:W, 0x0b5000-0x0b5fff:W, 0x0b6000-0x0b6fff:W, 0x0b7000-0x0b7fff:W, 0x0b8000-0x0b8fff:W, 0x0b9000-0x0b9fff:W, 0x0ba000-0x0bafff:W, 0x0bb000-0x0bbfff:W, 0x0bc000-0x0bcfff:W, 0x0bd000-0x0bdfff:W, 0x0be000-0x0befff:W, 0x0bf000-0x0bffff:W, 0x0c0000-0x0c0fff:W, 0x0c1000-0x0c1fff:W, 0x0c2000-0x0c2fff:W, 0x0c3000-0x0c3fff:W, 0x0c4000-0x0c4fff:W, 0x0c5000-0x0c5fff:W, 0x0c6000-0x0c6fff:W, 0x0c7000-0x0c7fff:W, 0x0c8000-0x0c8fff:W, 0x0c9000-0x0c9fff:W, 0x0ca000-0x0cafff:W, 0x0cb000-0x0cbfff:W, 0x0cc000-0x0ccfff:W, 0x0cd000-0x0cdfff:W, 0x0ce000-0x0cefff:W, 0x0cf000-0x0cffff:W, 0x0d0000-0x0d0fff:W, 0x0d1000-0x0d1fff:W, 0x0d2000-0x0d2fff:W, 0x0d3000-0x0d3fff:W, 0x0d4000-0x0d4fff:W, 0x0d5000-0x0d5fff:W, 0x0d6000-0x0d6fff:W, 0x0d7000-0x0d7fff:W, 0x0d8000-0x0d8fff:W, 0x0d9000-0x0d9fff:W, 0x0da000-0x0dafff:W, 0x0db000-0x0dbfff:W, 0x0dc000-0x0dcfff:W, 0x0dd000-0x0ddfff:W, 0x0de000-0x0defff:W, 0x0df000-0x0dffff:W, 0x0e0000-0x0e0fff:W, 0x0e1000-0x0e1fff:W, 0x0e2000-0x0e2fff:W, 0x0e3000-0x0e3fff:W, 0x0e4000-0x0e4fff:W, 0x0e5000-0x0e5fff:W, 0x0e6000-0x0e6fff:W, 0x0e7000-0x0e7fff:W, 0x0e8000-0x0e8fff:W, 0x0e9000-0x0e9fff:W, 0x0ea000-0x0eafff:W, 0x0eb000-0x0ebfff:W, 0x0ec000-0x0ecfff:W, 0x0ed000-0x0edfff:W, 0x0ee000-0x0eefff:W, 0x0ef000-0x0effff:W, 0x0f0000-0x0f0fff:W, 0x0f1000-0x0f1fff:W, 0x0f2000-0x0f2fff:W, 0x0f3000-0x0f3fff:W, 0x0f4000-0x0f4fff:W, 0x0f5000-0x0f5fff:W, 0x0f6000-0x0f6fff:W, 0x0f7000-0x0f7fff:W, 0x0f8000-0x0f8fff:W, 0x0f9000-0x0f9fff:W, 0x0fa000-0x0fafff:W, 0x0fb000-0x0fbfff:W, 0x0fc000-0x0fcfff:W, 0x0fd000-0x0fdfff:W, 0x0fe000-0x0fefff:W, 0x0ff000-0x0fffff:E program_opcodes: preop=5006 optype=463b opmenu=05200302c79f0190 on-the-fly OPCODE (0x20) re-programmed, op-pos=2 W, 0x100000-0x100fff:EW, 0x101000-0x101fff:EW, 0x102000-0x102fff:EW, 0x103000-0x103fff:EW, 0x104000-0x104fff:EW, 0x105000-0x105fff:EW, 0x106000-0x106fff:EW, 0x107000-0x107fff:EW, 0x108000-0x108fff:EW, 0x109000-0x109fff:EW, 0x10a000-0x10afff:EW, 0x10b000-0x10bfff:Etimeout, ICH9_REG_SSFS=0x00002401 run OPCODE 0x20 failed spi_block_erase_20 failed during command execution at address 0x10b000 Looking at blockwise erase function 1... trying... 0x000000-0x00ffff:S, 0x010000-0x01ffff:S, 0x020000-0x02ffff:S, 0x030000-0x03ffff:S, 0x040000-0x04ffff:S, 0x050000-0x05ffff:S, 0x060000-0x06ffff:S, 0x070000-0x07ffff:S, 0x080000-0x08ffff:S, 0x090000-0x09ffff:S, 0x0a0000-0x0affff:S, 0x0b0000-0x0bffff:S, 0x0c0000-0x0cffff:S, 0x0d0000-0x0dffff:S, 0x0e0000-0x0effff:S, 0x0f0000-0x0fffff:S, 0x100000-0x10ffff:E program_opcodes: preop=5006 optype=463b opmenu=05520302c79f0190 on-the-fly OPCODE (0x52) re-programmed, op-pos=2 ERASE FAILED at 0x00100000! Expected=0xff, Read=0x11, failed byte count from 0x00100000-0x0010ffff: 0xeea9 ERASE FAILED! Looking at blockwise erase function 2... trying... 0x000000-0x00ffff:S, 0x010000-0x01ffff:S, 0x020000-0x02ffff:S, 0x030000-0x03ffff:S, 0x040000-0x04ffff:S, 0x050000-0x05ffff:S, 0x060000-0x06ffff:S, 0x070000-0x07ffff:S, 0x080000-0x08ffff:S, 0x090000-0x09ffff:S, 0x0a0000-0x0affff:S, 0x0b0000-0x0bffff:S, 0x0c0000-0x0cffff:S, 0x0d0000-0x0dffff:S, 0x0e0000-0x0effff:S, 0x0f0000-0x0fffff:S, 0x100000-0x10ffff:E program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 on-the-fly OPCODE (0xD8) re-programmed, op-pos=2 timeout, ICH9_REG_SSFS=0x00002401 run OPCODE 0xd8 failed spi_block_erase_d8 failed during command execution at address 0x100000 Error: SCIP never cleared! run OPCODE 0x03 failed Can't read anymore! FAILED! Uh oh. Erase/write failed. Checking if anything changed. Error: SCIP never cleared! run OPCODE 0x03 failed Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with FAILED: your board name in the subject line! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! Restoring PCI config space for 00:1f:0 reg 0xdc please help me ,thankyou very much! Best ! healthly

2 2

MCP61:flashrom -V SPI
by Rianav Antares 29 Apr '11

29 Apr '11

Hello, I hope you find this useful. This is after following the instructions given in flashrom -V on my mcp61P nforce430 msi k9n6pgm2 . Cheers. [root@verian ~]# flashrom -V flashrom v0.9.3-r1205 on Linux 2.6.38-ARCH (i686), built with libpci 3.1.7, GCC 4.5.2 20110127 (prerelease), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1443M loops per second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 1000 us, 10000 myus = 9993 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "MSI" DMI string system-product-name: "MS-7309" DMI string system-version: "1.0" DMI string baseboard-manufacturer: "MSI" DMI string baseboard-product-name: "MS-7309" DMI string baseboard-version: "1.0" DMI string chassis-type: "Desktop" Found chipset "NVIDIA MCP61", enabling flash write... chipset PCI ID is 10de:03e0, This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 Flash bus type is LPC Found SMBus device 10de:03eb at 00:01:1 MCP SPI BAR is at 0xd0000000 Strange. MCP SPI BAR is valid, but chipset apparently doesn't have SPI enabled. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: LPC. Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for AMIC A25L05PT, 64 KB: skipped. Probing for AMIC A25L05PU, 64 KB: skipped. Probing for AMIC A25L10PT, 128 KB: skipped. Probing for AMIC A25L10PU, 128 KB: skipped. Probing for AMIC A25L20PT, 256 KB: skipped. Probing for AMIC A25L20PU, 256 KB: skipped. Probing for AMIC A25L40PT, 512 KB: skipped. Probing for AMIC A25L40PU, 512 KB: skipped. Probing for AMIC A25L80P, 1024 KB: skipped. Probing for AMIC A25L16PT, 2048 KB: skipped. Probing for AMIC A25L16PU, 2048 KB: skipped. Probing for AMIC A25L512, 64 KB: skipped. Probing for AMIC A25L010, 128 KB: skipped. Probing for AMIC A25L020, 256 KB: skipped. Probing for AMIC A25L040, 512 KB: skipped. Probing for AMIC A25L080, 1024 KB: skipped. Probing for AMIC A25L016, 2048 KB: skipped. Probing for AMIC A25L032, 4096 KB: skipped. Probing for AMIC A25LQ032, 4096 KB: skipped. Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0x08, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT25DF021, 256 KB: skipped. Probing for Atmel AT25DF041A, 512 KB: skipped. Probing for Atmel AT25DF081, 1024 KB: skipped. Probing for Atmel AT25DF081A, 1024 KB: skipped. Probing for Atmel AT25DF161, 2048 KB: skipped. Probing for Atmel AT25DF321, 4096 KB: skipped. Probing for Atmel AT25DF321A, 4096 KB: skipped. Probing for Atmel AT25DF641, 8192 KB: skipped. Probing for Atmel AT25DQ161, 2048 KB: skipped. Probing for Atmel AT25F512B, 64 KB: skipped. Probing for Atmel AT25FS010, 128 KB: skipped. Probing for Atmel AT25FS040, 512 KB: skipped. Probing for Atmel AT26DF041, 512 KB: skipped. Probing for Atmel AT26DF081A, 1024 KB: skipped. Probing for Atmel AT26DF161, 2048 KB: skipped. Probing for Atmel AT26DF161A, 2048 KB: skipped. Probing for Atmel AT26F004, 512 KB: skipped. Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: skipped. Probing for Atmel AT45DB011D, 128 KB: skipped. Probing for Atmel AT45DB021D, 256 KB: skipped. Probing for Atmel AT45DB041D, 512 KB: skipped. Probing for Atmel AT45DB081D, 1024 KB: skipped. Probing for Atmel AT45DB161D, 2048 KB: skipped. Probing for Atmel AT45DB321C, 4224 KB: skipped. Probing for Atmel AT45DB321D, 4096 KB: skipped. Probing for Atmel AT45DB642D, 8192 KB: skipped. Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F020, 256 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for Bright BM29F040, 512 KB: skipped. Probing for EMST F49B002UA, 256 KB: skipped. Probing for EMST F25L008A, 1024 KB: skipped. Probing for Eon EN25B05, 64 KB: skipped. Probing for Eon EN25B05T, 64 KB: skipped. Probing for Eon EN25B10, 128 KB: skipped. Probing for Eon EN25B10T, 128 KB: skipped. Probing for Eon EN25B20, 256 KB: skipped. Probing for Eon EN25B20T, 256 KB: skipped. Probing for Eon EN25B40, 512 KB: skipped. Probing for Eon EN25B40T, 512 KB: skipped. Probing for Eon EN25B80, 1024 KB: skipped. Probing for Eon EN25B80T, 1024 KB: skipped. Probing for Eon EN25B16, 2048 KB: skipped. Probing for Eon EN25B16T, 2048 KB: skipped. Probing for Eon EN25B32, 4096 KB: skipped. Probing for Eon EN25B32T, 4096 KB: skipped. Probing for Eon EN25B64, 8192 KB: skipped. Probing for Eon EN25B64T, 8192 KB: skipped. Probing for Eon EN25D16, 2048 KB: skipped. Probing for Eon EN25F05, 64 KB: skipped. Probing for Eon EN25F10, 128 KB: skipped. Probing for Eon EN25F20, 256 KB: skipped. Probing for Eon EN25F40, 512 KB: skipped. Probing for Eon EN25F80, 1024 KB: skipped. Probing for Eon EN25F16, 2048 KB: skipped. Probing for Eon EN25F32, 4096 KB: skipped. Probing for Eon EN29F010, 128 KB: skipped. Probing for Eon EN29F002(A)(N)B, 256 KB: skipped. Probing for Eon EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Hyundai HY29F002T, 256 KB: skipped. Probing for Hyundai HY29F002B, 256 KB: skipped. Probing for Hyundai HY29F040A, 512 KB: skipped. Probing for Intel 28F001BN/BX-B, 128 KB: skipped. Probing for Intel 28F001BN/BX-T, 128 KB: skipped. Probing for Intel 28F002BC/BL/BV/BX-T, 256 KB: skipped. Probing for Intel 28F008S3/S5/SC, 512 KB: skipped. Probing for Intel 28F004B5/BE/BV/BX-B, 512 KB: skipped. Probing for Intel 28F004B5/BE/BV/BX-T, 512 KB: skipped. Probing for Intel 28F400BV/BX/CE/CV-B, 512 KB: skipped. Probing for Intel 28F400BV/BX/CE/CV-T, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: skipped. Probing for Intel 82802AC, 1024 KB: skipped. Probing for Macronix MX25L512, 64 KB: skipped. Probing for Macronix MX25L1005, 128 KB: skipped. Probing for Macronix MX25L2005, 256 KB: skipped. Probing for Macronix MX25L4005, 512 KB: skipped. Probing for Macronix MX25L8005, 1024 KB: skipped. Probing for Macronix MX25L1605, 2048 KB: skipped. Probing for Macronix MX25L1635D, 2048 KB: skipped. Probing for Macronix MX25L1635E, 2048 KB: skipped. Probing for Macronix MX25L3205, 4096 KB: skipped. Probing for Macronix MX25L3235D, 4096 KB: skipped. Probing for Macronix MX25L6405, 8192 KB: skipped. Probing for Macronix MX25L12805, 16384 KB: skipped. Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29F040, 512 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for MoselVitelic V29C51000B, 64 KB: skipped. Probing for MoselVitelic V29C51000T, 64 KB: skipped. Probing for MoselVitelic V29C51400B, 512 KB: skipped. Probing for MoselVitelic V29C51400T, 512 KB: skipped. Probing for MoselVitelic V29LC51000, 64 KB: skipped. Probing for MoselVitelic V29LC51001, 128 KB: skipped. Probing for MoselVitelic V29LC51002, 256 KB: skipped. Probing for Numonyx M25PE10, 128 KB: skipped. Probing for Numonyx M25PE20, 256 KB: skipped. Probing for Numonyx M25PE40, 512 KB: skipped. Probing for Numonyx M25PE80, 1024 KB: skipped. Probing for Numonyx M25PE16, 2048 KB: skipped. Probing for PMC Pm25LV010, 128 KB: skipped. Probing for PMC Pm25LV016B, 2048 KB: skipped. Probing for PMC Pm25LV020, 256 KB: skipped. Probing for PMC Pm25LV040, 512 KB: skipped. Probing for PMC Pm25LV080B, 1024 KB: skipped. Probing for PMC Pm25LV512, 64 KB: skipped. Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xd7, id2 0xde, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0x08, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 KB: skipped. Probing for Sharp LHF00L04, 1024 KB: skipped. Probing for Spansion S25FL008A, 1024 KB: skipped. Probing for Spansion S25FL016A, 2048 KB: skipped. Probing for SST SST25VF016B, 2048 KB: skipped. Probing for SST SST25VF032B, 4096 KB: skipped. Probing for SST SST25VF064C, 8192 KB: skipped. Probing for SST SST25VF040.REMS, 512 KB: skipped. Probing for SST SST25VF040B, 512 KB: skipped. Probing for SST SST25LF040A.RES, 512 KB: skipped. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Probing for SST SST25VF080B, 1024 KB: skipped. Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: skipped. Probing for SST SST49LF003A/B, 384 KB: skipped. Probing for SST SST49LF004A/B, 512 KB: skipped. Probing for SST SST49LF004C, 512 KB: skipped. Probing for SST SST49LF008A, 1024 KB: skipped. Probing for SST SST49LF008C, 1024 KB: skipped. Probing for SST SST49LF016C, 2048 KB: skipped. Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0xd7, id2 0xde, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0xd7, id2 0xde, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0x08, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0x08, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 KB: skipped. Probing for ST M25P05.RES, 64 KB: skipped. Probing for ST M25P10-A, 128 KB: skipped. Probing for ST M25P10.RES, 128 KB: skipped. Probing for ST M25P20, 256 KB: skipped. Probing for ST M25P40, 512 KB: skipped. Probing for ST M25P40-old, 512 KB: skipped. Probing for ST M25P80, 1024 KB: skipped. Probing for ST M25P16, 2048 KB: skipped. Probing for ST M25P32, 4096 KB: skipped. Probing for ST M25P64, 8192 KB: skipped. Probing for ST M25P128, 16384 KB: skipped. Probing for ST M25PX32, 4096 KB: skipped. Probing for ST M25PX64, 8192 KB: skipped. Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BB, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x08, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x08, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: skipped. Probing for ST M50FW016, 2048 KB: skipped. Probing for ST M50FW040, 512 KB: skipped. Probing for ST M50FW080, 1024 KB: skipped. Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: skipped. Probing for Winbond W25Q16, 2048 KB: skipped. Probing for Winbond W25Q32, 4096 KB: skipped. Probing for Winbond W25Q64, 8192 KB: skipped. Probing for Winbond W25x10, 128 KB: skipped. Probing for Winbond W25x20, 256 KB: skipped. Probing for Winbond W25x40, 512 KB: skipped. Probing for Winbond W25x80, 1024 KB: skipped. Probing for Winbond W25x16, 2048 KB: skipped. Probing for Winbond W25x32, 4096 KB: skipped. Probing for Winbond W25x64, 8192 KB: skipped. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped. Probing for Winbond W29C020(C)/W29C022, 256 KB: skipped. Probing for Winbond W29C040/P, 512 KB: skipped. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0x08, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040(F)B, 512 KB: probe_jedec_common: id1 0x08, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040(F)C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x08, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 KB: skipped. Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U/N, 256 KB: skipped. Probing for Winbond W49F020, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0xd7, id2 0xde, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 KB: skipped. Probing for Winbond W39V080FA, 1024 KB: skipped. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Probing for AMIC unknown AMIC SPI chip, 0 KB: skipped. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Probing for Eon unknown Eon SPI chip, 0 KB: skipped. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Probing for SST unknown SST SPI chip, 0 KB: skipped. Probing for ST unknown ST SPI chip, 0 KB: skipped. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. [root@verian ~]# lspci -nnvvvxxx 00:00.0 RAM memory [0500]: nVidia Corporation MCP61 Memory Controller [10de:03ea] (rev a1) Subsystem: nVidia Corporation Device [10de:cb84] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Capabilities: [44] HyperTransport: Slave or Primary Interface Command: BaseUnitID=0 UnitCnt=17 MastHost- DefDir- DUL- Link Control 0: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 0: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Link Control 1: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 1: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 1.03 Link Frequency 0: 400MHz Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 0: 200MHz+ 300MHz+ 400MHz+ 500MHz+ 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- Link Frequency 1: 200MHz Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 1: 200MHz- 300MHz- 400MHz- 500MHz- 600MHz- 800MHz- 1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend- Error Handling: PFlE+ OFlE+ PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE- PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE- Prefetchable memory behind bridge Upper: 00-00 Bus Number: 00 Capabilities: [dc] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 00: de 10 ea 03 06 00 b0 00 a1 00 00 05 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 de 10 84 cb 30: 00 00 00 00 44 00 00 00 00 00 00 00 00 00 00 00 40: de 10 84 cb 08 dc 20 02 20 00 11 11 d0 00 00 00 50: 23 02 7f 00 03 00 00 00 00 00 03 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 06 36 00 00 70: 44 44 44 00 d0 09 00 00 11 00 00 00 11 11 88 00 80: 23 99 88 00 fa 00 64 0d 03 00 00 00 7f 00 00 00 90: 70 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 01 01 01 01 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 08 00 01 a8 e0: 00 00 e0 fe 00 00 00 00 06 00 00 00 20 10 00 00 f0: f0 ff ff ff 00 00 00 00 00 00 00 00 00 00 00 00 00:01.0 ISA bridge [0601]: nVidia Corporation MCP61 LPC Bridge [10de:03e0] (rev a2) Subsystem: nVidia Corporation Device [10de:cb84] Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Region 0: I/O ports at 4f00 [size=256] 00: de 10 e0 03 0f 00 a0 00 a2 00 01 06 00 00 80 00 10: 01 4f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 de 10 84 cb 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: de 10 84 cb 00 00 ff fe fa 3e ff 00 fa 3e ff 00 50: fa 3e ff 00 00 5a 62 02 00 00 00 05 2f 00 fc 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 70: 10 00 ff ff c5 80 00 00 00 00 04 19 00 00 00 c0 80: 09 d0 00 10 08 12 00 00 ff 00 00 01 ff 00 00 00 90: ff 7f 00 00 00 00 00 00 21 65 08 74 b9 0c 00 d0 a0: 00 00 10 80 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 0a 7f 0a 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00:01.1 SMBus [0c05]: nVidia Corporation MCP61 SMBus [10de:03eb] (rev a2) Subsystem: Micro-Star International Co., Ltd. Device [1462:7309] Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin A routed to IRQ 11 Region 0: I/O ports at 4900 [size=64] Region 4: I/O ports at 4d00 [size=64] Region 5: I/O ports at 4e00 [size=64] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: nForce2_smbus Kernel modules: i2c-nforce2 00: de 10 eb 03 01 00 b0 00 a2 00 05 0c 00 00 80 00 10: 01 49 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 4d 00 00 01 4e 00 00 00 00 00 00 62 14 09 73 30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 01 00 00 40: 62 14 09 73 01 00 02 c0 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 01 40 00 00 01 44 00 00 01 48 00 00 00 10 d0 fe 70: 00 00 00 00 00 00 00 d0 00 00 fe fe 01 4c 00 00 80: 00 10 fe fe 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: d4 30 80 01 01 00 00 00 00 00 00 00 00 00 00 00 d0: 4c 00 40 01 10 00 00 00 05 00 00 00 00 00 00 00 e0: 88 10 04 00 00 40 02 07 80 22 04 20 41 44 44 11 f0: 02 ff 1e bf 01 00 00 80 10 00 00 00 00 00 00 00 00:01.2 RAM memory [0500]: nVidia Corporation MCP61 Memory Controller [10de:03f5] (rev a2) Subsystem: Micro-Star International Co., Ltd. Device [1462:7309] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: de 10 f5 03 00 04 a0 00 a2 00 00 05 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 62 14 09 73 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 10 02 80 10 10 00 10 10 50: 10 10 10 10 00 00 00 00 00 00 00 00 10 42 00 00 60: 0b 00 00 00 c0 1c 52 06 21 00 10 0a 00 00 63 00 70: 09 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 40 00 00 00 00 00 a0 18 00 00 90: 00 00 00 00 00 00 00 12 20 81 04 00 00 00 00 00 a0: 00 14 00 06 00 00 00 00 00 00 00 00 01 00 00 00 b0: 00 00 00 00 42 80 30 04 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:01.3 Co-processor [0b40]: nVidia Corporation MCP61 SMU [10de:03f4] (rev a2) Subsystem: Micro-Star International Co., Ltd. Device [1462:7309] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin B routed to IRQ 5 Region 0: Memory at d0000000 (32-bit, non-prefetchable) [size=512K] 00: de 10 f4 03 06 00 a0 00 a2 00 40 0b 00 00 80 00 10: 00 00 00 d0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 62 14 09 73 30: 00 00 00 00 00 00 00 00 00 00 00 00 05 02 03 01 40: 62 14 09 73 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 d0 00 00 00 00 00 00 00 00 80: 05 9c 80 01 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 08 00 02 a8 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:02.0 USB Controller [0c03]: nVidia Corporation MCP61 USB Controller [10de:03f1] (rev a3) (prog-if 10 [OHCI]) Subsystem: Micro-Star International Co., Ltd. Device [1462:7309] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 20 Region 0: Memory at dbf7f000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: ohci_hcd Kernel modules: ohci-hcd 00: de 10 f1 03 07 00 b0 00 a3 10 03 0c 00 00 80 00 10: 00 f0 f7 db 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 62 14 09 73 30: 00 00 00 00 44 00 00 00 00 00 00 00 07 01 03 01 40: 62 14 09 73 01 00 02 fe 00 00 00 00 00 00 00 00 50: 01 00 00 00 1d 47 40 00 10 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:02.1 USB Controller [0c03]: nVidia Corporation MCP61 USB Controller [10de:03f2] (rev a3) (prog-if 20 [EHCI]) Subsystem: Micro-Star International Co., Ltd. Device [1462:7309] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin B routed to IRQ 21 Region 0: Memory at dbf7ec00 (32-bit, non-prefetchable) [size=256] Capabilities: [44] Debug port: BAR=1 offset=0098 Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME+ Kernel driver in use: ehci_hcd Kernel modules: ehci-hcd 00: de 10 f2 03 06 00 b0 00 a3 20 03 0c 00 00 80 00 10: 00 ec f7 db 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 62 14 09 73 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 02 03 01 40: 62 14 09 73 0a 80 98 20 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 01 00 00 60 18 85 c3 13 0f 01 00 00 00 00 70: 00 00 08 00 00 10 20 80 89 3d b6 22 77 25 d4 00 80: 01 00 02 fe 00 80 00 00 00 00 00 00 15 16 00 00 90: 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 01 00 00 01 00 00 08 e0 00 00 00 00 00 00 00 00 b0: 00 11 22 33 44 00 00 00 ff 03 00 00 00 00 00 00 c0: 10 10 2d 0d 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00:04.0 PCI bridge [0604]: nVidia Corporation MCP61 PCI bridge [10de:03f3] (rev a1) (prog-if 01 [Subtractive decode]) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=64 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: fff00000-000fffff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr+ DiscTmrStat- DiscTmrSERREn- Capabilities: [b8] Subsystem: nVidia Corporation Device [10de:cb84] Capabilities: [8c] HyperTransport: MSI Mapping Enable- Fixed- Mapping Address Base: 00000000fee00000 00: de 10 f3 03 04 00 b0 00 a1 01 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 40 f0 00 80 22 20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 b8 00 00 00 00 00 00 00 00 00 02 02 40: 00 00 73 07 01 00 02 00 07 00 00 00 00 00 48 00 50: 00 00 00 00 00 00 00 00 ff 1f ff 1f 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 03 00 00 fa ff 00 00 00 00 00 00 08 00 00 a8 90: 00 00 e0 fe 00 00 00 00 00 00 00 00 00 00 00 00 a0: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 ff ff 00 00 0d 8c 00 00 de 10 84 cb c0: de 10 84 cb 03 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:05.0 Audio device [0403]: nVidia Corporation MCP61 High Definition Audio [10de:03f0] (rev a2) Subsystem: Micro-Star International Co., Ltd. Device [1462:7309] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (500ns min, 1250ns max) Interrupt: pin B routed to IRQ 23 Region 0: Memory at dbf78000 (32-bit, non-prefetchable) [size=16K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+ Address: 0000000000000000 Data: 0000 Masking: 00000000 Pending: 00000000 Capabilities: [6c] HyperTransport: MSI Mapping Enable- Fixed+ Kernel driver in use: oss_hdaudio 00: de 10 f0 03 06 00 b0 00 a2 00 03 04 00 00 80 00 10: 00 80 f7 db 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 62 14 09 73 30: 00 00 00 00 44 00 00 00 00 00 00 00 0b 02 02 05 40: 62 14 09 73 01 50 02 c0 00 00 00 00 01 01 0f 00 50: 05 6c 80 01 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 0f 00 00 00 08 00 02 a8 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 47 00 29 00 00 00 00 00 00 00:06.0 IDE interface [0101]: nVidia Corporation MCP61 IDE [10de:03ec] (rev a2) (prog-if 8a [Master SecP PriP]) Subsystem: nVidia Corporation Device [10de:cb84] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Region 0: [virtual] Memory at 000001f0 (32-bit, non-prefetchable) [size=8] Region 1: [virtual] Memory at 000003f0 (type 3, non-prefetchable) [size=1] Region 2: [virtual] Memory at 00000170 (32-bit, non-prefetchable) [size=8] Region 3: [virtual] Memory at 00000370 (type 3, non-prefetchable) [size=1] Region 4: I/O ports at fff0 [size=16] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: pata_amd Kernel modules: amd74xx, pata_amd 00: de 10 ec 03 05 00 b0 00 a2 8a 01 01 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: f1 ff 00 00 00 00 00 00 00 00 00 00 de 10 84 cb 30: 00 00 00 00 44 00 00 00 00 00 00 00 00 00 03 01 40: de 10 84 cb 01 00 02 00 00 00 00 00 00 00 00 00 50: 02 f0 00 00 00 00 00 00 99 99 99 99 aa 00 a8 a8 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 01 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00:07.0 Bridge [0680]: nVidia Corporation MCP61 Ethernet [10de:03ef] (rev a2) Subsystem: Micro-Star International Co., Ltd. Device [1462:7309] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (250ns min, 5000ns max) Interrupt: pin A routed to IRQ 43 Region 0: Memory at dbf7d000 (32-bit, non-prefetchable) [size=4K] Region 1: I/O ports at de00 [size=8] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable+ DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable+ Count=1/8 Maskable+ 64bit+ Address: 00000000fee0300c Data: 4179 Masking: 000000fe Pending: 00000000 Capabilities: [6c] HyperTransport: MSI Mapping Enable- Fixed+ Kernel driver in use: forcedeth Kernel modules: forcedeth 00: de 10 ef 03 07 04 b0 00 a2 00 80 06 00 00 00 00 10: 00 d0 f7 db 01 de 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 62 14 09 73 30: 00 00 00 00 44 00 00 00 00 00 00 00 05 01 01 14 40: 62 14 09 73 01 50 02 fe 00 01 00 00 08 00 00 20 50: 05 6c 87 01 0c 30 e0 fe 00 00 00 00 79 41 00 00 60: fe 00 00 00 00 00 00 00 ff 00 00 00 08 00 02 a8 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 42 01 00 00 00 00 00 00 00:08.0 IDE interface [0101]: nVidia Corporation MCP61 SATA Controller [10de:03f6] (rev a2) (prog-if 85 [Master SecO PriO]) Subsystem: Micro-Star International Co., Ltd. Device [1462:7309] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 (750ns min, 250ns max) Interrupt: pin A routed to IRQ 23 Region 0: I/O ports at dd80 [size=8] Region 1: I/O ports at dd00 [size=4] Region 2: I/O ports at dc00 [size=8] Region 3: I/O ports at db80 [size=4] Region 4: I/O ports at db00 [size=16] Region 5: Memory at dbf7c000 (32-bit, non-prefetchable) [size=4K] Capabilities: [44] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [b0] MSI: Enable- Count=1/4 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [cc] HyperTransport: MSI Mapping Enable- Fixed+ Kernel driver in use: sata_nv Kernel modules: sata_nv 00: de 10 f6 03 07 00 b0 00 a2 85 01 01 00 00 80 00 10: 81 dd 00 00 01 dd 00 00 01 dc 00 00 81 db 00 00 20: 01 db 00 00 00 c0 f7 db 00 00 00 00 62 14 09 73 30: 00 00 00 00 44 00 00 00 00 00 00 00 0a 01 03 01 40: 62 14 09 73 01 b0 02 00 00 00 00 00 00 00 00 00 50: 0f 68 08 00 00 00 00 00 00 20 00 20 44 20 00 20 60: 00 c6 00 c7 41 0c 00 00 00 0f 06 42 00 00 00 00 70: 2c 78 c4 40 01 10 00 00 01 10 00 00 20 00 20 81 80: 00 00 00 c0 00 f0 8f a9 00 00 08 80 00 50 9c 8f 90: 00 00 10 90 00 00 00 00 06 00 06 10 f6 03 01 01 a0: 08 00 00 0f 00 00 00 00 00 00 00 00 33 31 00 02 b0: 05 cc 84 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 0a 00 0a 00 08 00 02 a8 d0: 09 00 00 49 00 08 03 00 09 00 00 49 00 08 03 00 e0: 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 0c 00 00 00 00 00 00:09.0 PCI bridge [0604]: nVidia Corporation MCP61 PCI Express bridge [10de:03e8] (rev a2) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 I/O behind bridge: 0000e000-0000efff Memory behind bridge: dc000000-dfffffff Prefetchable memory behind bridge: 00000000c0000000-00000000cfffffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA+ MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: nVidia Corporation Device [10de:0000] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable+ Count=1/2 Maskable- 64bit+ Address: 00000000fee0300c Data: 4129 Capabilities: [60] HyperTransport: MSI Mapping Enable- Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x16, ASPM L0s L1, Latency L0 <512ns, L1 <4us ClockPM- Surprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x16, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #1, PowerLimit 75.000W; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=WRR32 Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Kernel driver in use: pcieport Kernel modules: shpchp 00: de 10 e8 03 07 04 10 00 a2 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 02 02 00 e1 e1 00 00 20: 00 dc f0 df 01 c0 f1 cf 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 1a 00 40: 0d 48 00 00 de 10 00 00 01 50 02 f8 00 00 00 00 50: 05 60 83 00 0c 30 e0 fe 00 00 00 00 29 41 00 00 60: 08 80 00 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 01 80 00 00 10 28 00 00 01 3d 11 00 90: 40 00 01 31 80 25 08 00 c0 01 48 01 08 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0b.0 PCI bridge [0604]: nVidia Corporation MCP61 PCI Express bridge [10de:03e9] (rev a2) (prog-if 00 [Normal decode]) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=03, subordinate=03, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: nVidia Corporation Device [10de:0000] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable+ Count=1/2 Maskable- 64bit+ Address: 00000000fee0300c Data: 4141 Capabilities: [60] HyperTransport: MSI Mapping Enable- Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <4us ClockPM- Surprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #2, PowerLimit 10.000W; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=WRR32 Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Kernel driver in use: pcieport Kernel modules: shpchp 00: de 10 e9 03 04 04 10 00 a2 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 03 03 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 40: 0d 48 00 00 de 10 00 00 01 50 02 f8 00 00 00 00 50: 05 60 83 00 0c 30 e0 fe 00 00 00 00 41 41 00 00 60: 08 80 00 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 01 80 00 00 10 28 00 00 11 3c 11 01 90: 00 00 11 10 00 05 10 00 c0 01 00 00 08 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0c.0 PCI bridge [0604]: nVidia Corporation MCP61 PCI Express bridge [10de:03e9] (rev a2) (prog-if 00 [Normal decode]) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=04, subordinate=04, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: nVidia Corporation Device [10de:0000] Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable+ Count=1/2 Maskable- 64bit+ Address: 00000000fee0300c Data: 4149 Capabilities: [60] HyperTransport: MSI Mapping Enable- Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [80] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #2, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <4us ClockPM- Surprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #3, PowerLimit 10.000W; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd On, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet- LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [100 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=WRR32 Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Kernel driver in use: pcieport Kernel modules: shpchp 00: de 10 e9 03 04 04 10 00 a2 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 04 04 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 40: 0d 48 00 00 de 10 00 00 01 50 02 f8 00 00 00 00 50: 05 60 83 00 0c 30 e0 fe 00 00 00 00 49 41 00 00 60: 08 80 00 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 10 00 41 01 01 80 00 00 10 28 00 00 11 3c 11 02 90: 00 00 11 10 00 05 18 00 c0 01 00 00 08 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor HyperTransport Configuration [1022:1200] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn+ ExtCTL- 64b- Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Revision ID: 3.00 Link Frequency: 400MHz Link Error: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz+ 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA+ UIDRD- ExtRS- UCnfE- 00: 22 10 00 12 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 01 02 04 00 01 02 04 00 01 02 04 00 01 02 04 00 50: 01 02 04 00 01 02 04 00 01 02 04 00 01 02 04 00 60: 00 00 01 00 e0 00 00 00 20 a8 4e 00 20 f8 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 00 01 21 20 20 11 11 60 02 f5 8f 13 00 00 00 90: 92 02 85 04 00 00 00 00 07 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.1 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor Address Map [1022:1201] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 01 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 03 00 00 00 00 00 bf 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 03 00 e0 00 80 ff ef 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 03 0a 00 00 00 0b 00 00 03 00 c0 00 00 0b fe 00 c0: 13 10 00 00 00 f0 ff 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 03 00 00 07 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.2 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor DRAM Controller [1022:1202] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 02 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 00 00 00 01 01 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: e0 3e 78 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 06 00 48 0d 00 00 00 00 80: 05 00 00 00 00 00 00 00 35 fb 7d 00 34 03 22 00 90: 10 00 01 00 0b 80 58 7f 07 03 00 80 00 00 00 00 a0: 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: f5 1d 95 69 e6 00 00 00 73 64 bb 94 94 90 8c 88 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 38 2b 81 62 50 a4 9e ea 1e 07 60 40 ef cd a4 60 e0: 3c 09 c5 82 42 a4 d1 40 34 86 89 9c 2f a5 2c aa f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.3 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor Miscellaneous Control [1022:1203] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [f0] Secure device <?> Kernel driver in use: k10temp Kernel modules: k10temp 00: 22 10 03 12 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 00 40: ff ff ff 3f 5c 00 b0 4a 00 00 00 00 00 00 00 00 50: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 04 00 24 34 00 00 00 30 52 80 01 00 70: 53 11 04 00 11 11 08 00 14 0c 20 00 14 09 09 00 80: 81 87 00 e6 e6 41 e6 01 08 00 00 00 00 40 58 42 90: 00 00 00 00 42 6c 00 00 30 07 15 90 00 00 00 00 a0: 00 09 02 90 80 18 68 22 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 24 0f 81 c8 16 10 22 03 26 53 27 00 e0: 00 00 00 00 30 13 00 1e 79 1f 07 00 00 00 00 00 f0: 0f 00 10 00 00 00 00 00 00 00 00 00 62 0f 10 00 00:18.4 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor Link Control [1022:1204] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 04 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02:00.0 VGA compatible controller [0300]: nVidia Corporation G96 [GeForce 9500 GT] [10de:0640] (rev a1) (prog-if 00 [VGA controller]) Subsystem: eVga.com. Corp. Device [3842:c958] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 19 Region 0: Memory at df000000 (32-bit, non-prefetchable) [size=16M] Region 1: Memory at c0000000 (64-bit, prefetchable) [size=256M] Region 3: Memory at dc000000 (64-bit, non-prefetchable) [size=32M] Region 5: I/O ports at ef80 [size=128] [virtual] Expansion ROM at def80000 [disabled] [size=512K] Capabilities: [60] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [68] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [78] Express (v2) Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <1us, L1 <4us ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x16, ASPM L0s L1, Latency L0 <1us, L1 <1us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x16, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [b4] Vendor Specific Information: Len=14 <?> Capabilities: [100 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Capabilities: [128 v1] Power Budgeting <?> Capabilities: [600 v1] Vendor Specific Information: ID=0001 Rev=1 Len=024 <?> Kernel driver in use: nvidia Kernel modules: nouveau, nvidiafb, nvidia 00: de 10 40 06 07 00 10 00 a1 00 00 03 00 00 00 00 10: 00 00 00 df 0c 00 00 c0 00 00 00 00 04 00 00 dc 20: 00 00 00 00 81 ef 00 00 00 00 00 00 42 38 58 c9 30: 00 00 00 00 60 00 00 00 00 00 00 00 0a 01 00 00 40: 42 38 58 c9 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 00 00 00 01 00 00 00 ce d6 23 00 00 00 00 00 60: 01 68 03 00 00 00 00 00 05 78 80 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 10 b4 02 00 20 85 00 00 80: 10 29 00 00 01 4d 00 00 48 00 01 11 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 a0: 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 b0: 00 00 00 00 09 00 14 01 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [root@verian ~]# lspci 00:00.0 RAM memory: nVidia Corporation MCP61 Memory Controller (rev a1) 00:01.0 ISA bridge: nVidia Corporation MCP61 LPC Bridge (rev a2) 00:01.1 SMBus: nVidia Corporation MCP61 SMBus (rev a2) 00:01.2 RAM memory: nVidia Corporation MCP61 Memory Controller (rev a2) 00:01.3 Co-processor: nVidia Corporation MCP61 SMU (rev a2) 00:02.0 USB Controller: nVidia Corporation MCP61 USB Controller (rev a3) 00:02.1 USB Controller: nVidia Corporation MCP61 USB Controller (rev a3) 00:04.0 PCI bridge: nVidia Corporation MCP61 PCI bridge (rev a1) 00:05.0 Audio device: nVidia Corporation MCP61 High Definition Audio (rev a2) 00:06.0 IDE interface: nVidia Corporation MCP61 IDE (rev a2) 00:07.0 Bridge: nVidia Corporation MCP61 Ethernet (rev a2) 00:08.0 IDE interface: nVidia Corporation MCP61 SATA Controller (rev a2) 00:09.0 PCI bridge: nVidia Corporation MCP61 PCI Express bridge (rev a2) 00:0b.0 PCI bridge: nVidia Corporation MCP61 PCI Express bridge (rev a2) 00:0c.0 PCI bridge: nVidia Corporation MCP61 PCI Express bridge (rev a2) 00:18.0 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor HyperTransport Configuration 00:18.1 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Address Map 00:18.2 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Miscellaneous Control 00:18.4 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Link Control 02:00.0 VGA compatible controller: nVidia Corporation G96 [GeForce 9500 GT] (rev a1) [root@verian ~]# -- Rianav Antares kerenskyy(a)myopera.com

1 0

Re: [flashrom] [PATCH] improve output in case run_opcode fails
by Michael Karcher 29 Apr '11

29 Apr '11

Am Samstag, den 30.04.2011, 01:30 +0200 schrieb Stefan Tauner: > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > + if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) || > + (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) { > + msg_pspew("The data was:\n"); > + int i; please don't declare variables after statements. > + for(i=0; i<count; i++){ > + msg_pspew("%3d: 0x%02x\n", i, data[i]); > + } > + } > } > > return result; Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> moved "int i" one line up and committed in r1291 Regards, Michael Karcher

1 0

[commit] r1291 - trunk
by repository service 29 Apr '11

29 Apr '11

Author: mkarcher Date: Sat Apr 30 01:53:09 2011 New Revision: 1291 URL: http://flashrom.org/trac/flashrom/changeset/1291 Log: improve output in case run_opcode fails Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Sat Apr 30 00:11:36 2011 (r1290) +++ trunk/ichspi.c Sat Apr 30 01:53:09 2011 (r1291) @@ -612,8 +612,7 @@ /* FIXME: make sure we do not needlessly cause transaction errors. */ temp16 = REGREAD16(ICH7_REG_SPIS); if (temp16 & SPIS_FCERR) { - msg_perr("Transaction error for opcode 0x%02x!\n", - op.opcode); + msg_perr("Transaction error!\n"); /* keep reserved bits */ temp16 &= SPIS_RESERVED_MASK; REGWRITE16(ICH7_REG_SPIS, temp16 | SPIS_FCERR); @@ -758,8 +757,7 @@ /* FIXME make sure we do not needlessly cause transaction errors. */ temp32 = REGREAD32(ICH9_REG_SSFS); if (temp32 & SSFS_FCERR) { - msg_perr("Transaction error for opcode 0x%02x!\n", - op.opcode); + msg_perr("Transaction error!\n"); /* keep reserved bits */ temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; /* Clear the transaction error. */ @@ -934,7 +932,24 @@ result = run_opcode(*opcode, addr, count, data); if (result) { - msg_pdbg("run OPCODE 0x%02x failed\n", opcode->opcode); + msg_pdbg("Running OPCODE 0x%02x failed ", opcode->opcode); + if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) || + (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS)) { + msg_pdbg("at address 0x%06x ", addr); + } + msg_pdbg("(payload length was %d).\n", count); + + /* Print out the data array if it contains data to write. + * Errors are detected before the received data is read back into + * the array so it won't make sense to print it then. */ + if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) || + (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) { + int i; + msg_pspew("The data was:\n"); + for(i=0; i<count; i++){ + msg_pspew("%3d: 0x%02x\n", i, data[i]); + } + } } return result;

1 0

[PATCH] improve output in case run_opcode fails
by Stefan Tauner 29 Apr '11

29 Apr '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 25 ++++++++++++++++++++----- 1 files changed, 20 insertions(+), 5 deletions(-) diff --git a/ichspi.c b/ichspi.c index 5c66ddd..f47783a 100644 --- a/ichspi.c +++ b/ichspi.c @@ -612,8 +612,7 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, /* FIXME: make sure we do not needlessly cause transaction errors. */ temp16 = REGREAD16(ICH7_REG_SPIS); if (temp16 & SPIS_FCERR) { - msg_perr("Transaction error for opcode 0x%02x!\n", - op.opcode); + msg_perr("Transaction error!\n"); /* keep reserved bits */ temp16 &= SPIS_RESERVED_MASK; REGWRITE16(ICH7_REG_SPIS, temp16 | SPIS_FCERR); @@ -758,8 +757,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, /* FIXME make sure we do not needlessly cause transaction errors. */ temp32 = REGREAD32(ICH9_REG_SSFS); if (temp32 & SSFS_FCERR) { - msg_perr("Transaction error for opcode 0x%02x!\n", - op.opcode); + msg_perr("Transaction error!\n"); /* keep reserved bits */ temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; /* Clear the transaction error. */ @@ -934,7 +932,24 @@ int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, result = run_opcode(*opcode, addr, count, data); if (result) { - msg_pdbg("run OPCODE 0x%02x failed\n", opcode->opcode); + msg_pdbg("Running OPCODE 0x%02x failed ", opcode->opcode); + if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) || + (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS)) { + msg_pdbg("at address 0x%06x ", addr); + } + msg_pdbg("(payload length was %d).\n", count); + + /* Print out the data array if it contains data to write. + * Errors are detected before the received data is read back into + * the array so it won't make sense to print it then. */ + if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) || + (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) { + msg_pspew("The data was:\n"); + int i; + for(i=0; i<count; i++){ + msg_pspew("%3d: 0x%02x\n", i, data[i]); + } + } } return result; -- 1.7.1

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Re: [flashrom] [PATCH 5/6] improve output in case run_opcode fails
by Stefan Tauner 29 Apr '11

29 Apr '11

On Fri, 1 Apr 2011 14:33:19 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > diff --git a/ichspi.c b/ichspi.c > index b24b6a0..0ad4f20 100644 > --- a/ichspi.c > +++ b/ichspi.c > ... > @@ -974,7 +973,19 @@ int ich_spi_send_command(unsigned int writecnt, > unsigned int readcnt, > result = run_opcode(*opcode, addr, count, data); > if (result) { > - msg_pdbg("run OPCODE 0x%02x failed\n", > opcode->opcode); > + msg_pdbg("run OPCODE 0x%02x failed at address > 0x%06x.\n", > + opcode->opcode, addr); > + /* Print out the data array if it contains data to > write. > + * Errors are detected before the received data is > read back into > + * the array so it won't make sense to print it > then. */ > + if (((opcode->spi_type == > SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) || > + (opcode->spi_type == > SPI_OPCODE_TYPE_WRITE_NO_ADDRESS))) { > + msg_pspew("The data was:\n"); > + uint8_t i; > + for(i=0; i<count; i++){ > + msg_pspew("%3d: 0x%02x\n", i, > data[i]); > + } > + } > } self-NAK :) uint8_t is too small and could result in an endless loop. oops. :( this should not happen normally, because devices supported by ichspi.c allow only 16B or 64B data lengths, but we could be called with something bigger i guess. how should this be solved? since "count" will get truncated implicitly when it is used as parameter for "run_opcode" we could do so explicitly before the loop. or an if around the loop checking for count<256. also i would like to include the count like so: "run OPCODE 0x%02x failed at address 0x%06x (length %d).\n" RFC :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 2

Here's the now (if) ready patch.
by Brandon Dowdy 29 Apr '11

29 Apr '11

Probably this patch is ready now. If not, then a few more problems to fix then.

1 0

Re: [flashrom] [PATCH] ichspi: Increase timeout to 60s for atomic operations
by Carl-Daniel Hailfinger 29 Apr '11

29 Apr '11

Am 29.04.2011 16:01 schrieb Michael Karcher: > Signed-off-by: Michael Karcher<flashrom(a)mkarcher.dialup.fu-berlin.de> > Thanks for the patch and for tracking this down and for writing a thorough analysis! Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Could you fix the whitespace before commit? > @@ -581,6 +588,7 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, > case 1: > /* Atomic command (preop+op) */ > temp16 |= SPIC_ACS; > + timeout = 100 * 1000* 60; /* 60 seconds */ > Should have a space after 1000 > break; > } > > @@ -720,6 +734,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, > case 1: > /* Atomic command (preop+op) */ > temp32 |= SSFC_ACS; > + timeout = 100 * 1000* 60; /* 60 seconds */ > Same here. > break; > } > > Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

[commit] r1290 - trunk
by repository service 29 Apr '11

29 Apr '11

Author: mkarcher Date: Sat Apr 30 00:11:36 2011 New Revision: 1290 URL: http://flashrom.org/trac/flashrom/changeset/1290 Log: ichspi: Increase timeout to 60s for atomic operations Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Wed Apr 27 16:34:08 2011 (r1289) +++ trunk/ichspi.c Sat Apr 30 00:11:36 2011 (r1290) @@ -572,7 +572,14 @@ } temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4; - /* Handle Atomic */ + timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ + /* Handle Atomic. Atomic commands include three steps: + - sending the preop (mainly EWSR or WREN) + - sending the main command + - waiting for the busy bit (WIP) to be cleared + This means the timeout must be sufficient for chip erase + of slow high-capacity chips. + */ switch (op.atomic) { case 2: /* Select second preop. */ @@ -581,6 +588,7 @@ case 1: /* Atomic command (preop+op) */ temp16 |= SPIC_ACS; + timeout = 100 * 1000 * 60; /* 60 seconds */ break; } @@ -591,7 +599,6 @@ REGWRITE16(ICH7_REG_SPIC, temp16); /* Wait for Cycle Done Status or Flash Cycle Error. */ - timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) && --timeout) { programmer_delay(10); @@ -711,7 +718,14 @@ } temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4); - /* Handle Atomic */ + timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ + /* Handle Atomic. Atomic commands include three steps: + - sending the preop (mainly EWSR or WREN) + - sending the main command + - waiting for the busy bit (WIP) to be cleared + This means the timeout must be sufficient for chip erase + of slow high-capacity chips. + */ switch (op.atomic) { case 2: /* Select second preop. */ @@ -720,6 +734,7 @@ case 1: /* Atomic command (preop+op) */ temp32 |= SSFC_ACS; + timeout = 100 * 1000 * 60; /* 60 seconds */ break; } @@ -730,7 +745,6 @@ REGWRITE32(ICH9_REG_SSFS, temp32); /* Wait for Cycle Done Status or Flash Cycle Error. */ - timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_CDS | SSFS_FCERR)) == 0) && --timeout) { programmer_delay(10);

1 0

Here's the properly fixed patch.
by Brandon Dowdy 29 Apr '11

29 Apr '11

Here is the properly and completely fixed patch.

1 0

Re: [flashrom] Problem H55M-S Foxconn
by Idwer Vollering 29 Apr '11

29 Apr '11

Forwarding his reply. 2011/4/29 Marcelo Sales Moreira <marcelo.sales(a)litecnologia.com.br>: > Good morning, > > I tested with version 0.9.3 and not work with the bios file that the > vendor sent me to work I had to update the bios file with custom bios / > upgrade software and then save with AFUDOS.EXE FlashROM, ai yes I could > replicate the bios saved for other boards. > > Attached is the original bios and bios saved with FlashROM Attached were: bios_save_flash.rom 4194304 bytes bios_logo.rom 1048576 bytes You can create a file that has the same size as "bios_save_flash.rom" / the chip size by doing this: cat bios_logo.rom bios_logo.rom bios_logo.rom bios_logo.rom >> bios_logo_4megabyte.rom We are also interested in the output of "flashrom -V -w bios_logo_4megabyte.rom" > > Att > Marcelo Moreira Sales > > > Em Qui, 2011-04-28 às 22:12 +0200, Idwer Vollering escreveu: >> 2011/4/28 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at>: >> > >> > >> > Begin forwarded message: >> > >> > Date: Thu, 28 Apr 2011 13:46:51 -0300 >> > From: Marcelo Sales Moreira <marcelo.sales(a)litecnologia.com.br> >> > To: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> >> > Subject: Re: [flashrom] Problem H55M-S Foxconn >> > >> > >> > Good afternoon, >> > >> > Attached is the output from-v FlashROM >> >> By looking at the output, I recommend to use version 0.9.3 or building >> the latest development code: >> http://www.flashrom.org/Downloads#Installation_from_source >> >> > >> > Att >> > Marcelo Moreira Sales >> > >> > >> > -- >> > Kind regards/Mit freundlichen Grüßen, Stefan Tauner >> > >> > _______________________________________________ >> > flashrom mailing list >> > flashrom(a)flashrom.org >> > http://www.flashrom.org/mailman/listinfo/flashrom >> > >> > >

1 0

[PATCH] ichspi: Increase timeout to 60s for atomic operations
by Michael Karcher 29 Apr '11

29 Apr '11

Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> --- ichspi.c | 22 ++++++++++++++++++---- 1 files changed, 18 insertions(+), 4 deletions(-) diff --git a/ichspi.c b/ichspi.c index ed92893..db5ec75 100644 --- a/ichspi.c +++ b/ichspi.c @@ -572,7 +572,14 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, } temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4; - /* Handle Atomic */ + timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ + /* Handle Atomic. Atomic commands include three steps: + - sending the preop (mainly EWSR or WREN) + - sending the main command + - waiting for the busy bit (WIP) to be cleared + This means the timeout must be sufficient for chip erase + of slow high-capacity chips. + */ switch (op.atomic) { case 2: /* Select second preop. */ @@ -581,6 +588,7 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, case 1: /* Atomic command (preop+op) */ temp16 |= SPIC_ACS; + timeout = 100 * 1000* 60; /* 60 seconds */ break; } @@ -591,7 +599,6 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, REGWRITE16(ICH7_REG_SPIC, temp16); /* Wait for Cycle Done Status or Flash Cycle Error. */ - timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) && --timeout) { programmer_delay(10); @@ -711,7 +718,14 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, } temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4); - /* Handle Atomic */ + timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ + /* Handle Atomic. Atomic commands include three steps: + - sending the preop (mainly EWSR or WREN) + - sending the main command + - waiting for the busy bit (WIP) to be cleared + This means the timeout must be sufficient for chip erase + of slow high-capacity chips. + */ switch (op.atomic) { case 2: /* Select second preop. */ @@ -720,6 +734,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, case 1: /* Atomic command (preop+op) */ temp32 |= SSFC_ACS; + timeout = 100 * 1000* 60; /* 60 seconds */ break; } @@ -730,7 +745,6 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, REGWRITE32(ICH9_REG_SSFS, temp32); /* Wait for Cycle Done Status or Flash Cycle Error. */ - timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_CDS | SSFS_FCERR)) == 0) && --timeout) { programmer_delay(10); -- 1.7.4.1

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reading BIOS setting using Flashrom
by ganesh.patwardhan＠wipro.com 28 Apr '11

28 Apr '11

Hi, Is it possible to read only BIOS setting and store in a file using Flashrom? Example :- say I want to read BIOS settings like Signature, boot order, Numlock setting etc... from Linux using Flashrom. Regards Ganesh Patwardhan Please do not print this email unless it is absolutely necessary. The information contained in this electronic message and any attachments to this message are intended for the exclusive use of the addressee(s) and may contain proprietary, confidential or privileged information. If you are not the intended recipient, you should not disseminate, distribute or copy this e-mail. Please notify the sender immediately and destroy all copies of this message and any attachments. WARNING: Computer viruses can be transmitted via email. The recipient should check this email and any attachments for the presence of viruses. The company accepts no liability for any damage caused by any virus transmitted by this email. www.wipro.com

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CHIPSET: Sun Fire x4100
by Stefan Reinauer 28 Apr '11

28 Apr '11

flashrom v0.9.3-r1283 on Linux 2.6.31.14-0.6-default (x86_64), built with libpci 3.1.3, GCC 4.4.1 [gcc-4_4-branch revision 150839], little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. No coreboot table found. Found chipset "NVIDIA CK804", enabling flash write... OK. WARNING: unexpected second chipset match: "NVIDIA CK804" ignoring, please report lspci and board URL to flashrom(a)flashrom.org with 'CHIPSET: your board name' in the subject line. This chipset supports the following protocols: Non-SPI. Found chip "ST M50FLW080A" (1024 KB, LPC,FWH) at physical address 0xfff00000. === This flash part has status UNTESTED for operations: WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! No operations were specified. ra:~ # lspci 00:00.0 Memory controller: nVidia Corporation CK804 Memory Controller (rev a4) 00:01.0 ISA bridge: nVidia Corporation CK804 ISA Bridge (rev f1) 00:01.1 SMBus: nVidia Corporation CK804 SMBus (rev a2) 00:02.0 USB Controller: nVidia Corporation CK804 USB Controller (rev a2) 00:02.1 USB Controller: nVidia Corporation CK804 USB Controller (rev a4) 00:06.0 IDE interface: nVidia Corporation CK804 IDE (rev f3) 00:09.0 PCI bridge: nVidia Corporation CK804 PCI Bridge (rev f2) 00:0a.0 Bridge: nVidia Corporation CK804 Ethernet Controller (rev f3) 00:0b.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev f3) 00:0c.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev f3) 00:0d.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev f3) 00:0e.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3) 00:18.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration 00:18.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map 00:18.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control 00:19.0 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration 00:19.1 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Address Map 00:19.2 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] DRAM Controller 00:19.3 Host bridge: Advanced Micro Devices [AMD] K8 [Athlon64/Opteron] Miscellaneous Control 01:03.0 VGA compatible controller: ATI Technologies Inc Rage XL (rev 27) 80:00.0 Memory controller: nVidia Corporation CK804 Memory Controller (rev a4) 80:01.0 Memory controller: nVidia Corporation CK804 Memory Controller (rev f1) 80:0a.0 Bridge: nVidia Corporation CK804 Ethernet Controller (rev f3) 80:0b.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev f3) 80:0c.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev f3) 80:0d.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev f3) 80:0e.0 PCI bridge: nVidia Corporation CK804 PCIE Bridge (rev a3) 80:10.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8132 PCI-X Bridge (rev 12) 80:10.1 PIC: Advanced Micro Devices [AMD] AMD-8132 PCI-X IOAPIC (rev 12) 80:11.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8132 PCI-X Bridge (rev 12) 80:11.1 PIC: Advanced Micro Devices [AMD] AMD-8132 PCI-X IOAPIC (rev 12) 86:01.0 Ethernet controller: Intel Corporation 82546EB Gigabit Ethernet Controller (Copper) (rev 03) 86:01.1 Ethernet controller: Intel Corporation 82546EB Gigabit Ethernet Controller (Copper) (rev 03) 86:02.0 SCSI storage controller: LSI Logic / Symbios Logic SAS1064 PCI-X Fusion-MPT SAS (rev 02)

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