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[commit] r1304 - trunk
by repository service 17 May '11

17 May '11

Author: stefanct Date: Wed May 18 03:31:10 2011 New Revision: 1304 URL: http://flashrom.org/trac/flashrom/changeset/1304 Log: Mark MX25L4005 tested for erase Signed-off-by: Raúl Soriano <GatoLoko(a)gmail.com> Acked-by: Idwer Vollering <vidwer(a)gmail.com> Modified: trunk/flashchips.c Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Wed May 18 03:31:03 2011 (r1303) +++ trunk/flashchips.c Wed May 18 03:31:10 2011 (r1304) @@ -3757,7 +3757,7 @@ .total_size = 512, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PR, + .tested = TEST_OK_PRE, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers =

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[commit] r1303 - trunk
by repository service 17 May '11

17 May '11

Author: stefanct Date: Wed May 18 03:31:03 2011 New Revision: 1303 URL: http://flashrom.org/trac/flashrom/changeset/1303 Log: Mark w25q80, w25q32, and w25q64 chips tested for write and erase Signed-off-by: David Hendricks <dhendrix(a)google.com> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Modified: trunk/flashchips.c Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Wed May 18 03:30:56 2011 (r1302) +++ trunk/flashchips.c Wed May 18 03:31:03 2011 (r1303) @@ -3793,7 +3793,7 @@ .total_size = 1024, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -7569,7 +7569,7 @@ .total_size = 512, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -7737,7 +7737,7 @@ .total_size = 128, .page_size = 128, .feature_bits = FEATURE_LONG_RESET, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 10, /* used datasheet for the W29C011A */ .block_erasers =

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[commit] r1302 - trunk
by repository service 17 May '11

17 May '11

Author: stefanct Date: Wed May 18 03:30:56 2011 New Revision: 1302 URL: http://flashrom.org/trac/flashrom/changeset/1302 Log: Remove filename parameter from chip_safety_check() Signed-off-by: David Hendricks <dhendrix(a)google.com> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Modified: trunk/flashrom.c Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Wed May 18 01:30:13 2011 (r1301) +++ trunk/flashrom.c Wed May 18 03:30:56 2011 (r1302) @@ -1772,7 +1772,7 @@ /* FIXME: This function signature needs to be improved once doit() has a better * function signature. */ -int chip_safety_check(struct flashchip *flash, int force, char *filename, int read_it, int write_it, int erase_it, int verify_it) +int chip_safety_check(struct flashchip *flash, int force, int read_it, int write_it, int erase_it, int verify_it) { if (!programmer_may_write && (write_it || erase_it)) { msg_perr("Write/erase is not working yet on your programmer in " @@ -1836,7 +1836,7 @@ int ret = 0; unsigned long size = flash->total_size * 1024; - if (chip_safety_check(flash, force, filename, read_it, write_it, erase_it, verify_it)) { + if (chip_safety_check(flash, force, read_it, write_it, erase_it, verify_it)) { msg_cerr("Aborting.\n"); ret = 1; goto out_nofree;

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[PATCH 1/1] Kill unused __FLASHROM_HAVE_OUTB__ define
by Peter Lemenkov 17 May '11

17 May '11

Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- hwaccess.h | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-) diff --git a/hwaccess.h b/hwaccess.h index 63a2bf2..d125890 100644 --- a/hwaccess.h +++ b/hwaccess.h @@ -163,8 +163,6 @@ cpu_to_be(64) #if NEED_PCI == 1 #if defined (__i386__) || defined (__x86_64__) -#define __FLASHROM_HAVE_OUTB__ 1 - /* for iopl and outb under Solaris */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) #include <strings.h> -- 1.7.2.3

2 1

[commit] r1301 - trunk
by repository service 17 May '11

17 May '11

Author: stefanct Date: Wed May 18 01:30:13 2011 New Revision: 1301 URL: http://flashrom.org/trac/flashrom/changeset/1301 Log: fix typo "not not" in board_enable.c Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Idwer Vollering <vidwer(a)gmail.com> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Tue May 17 15:31:55 2011 (r1300) +++ trunk/board_enable.c Wed May 18 01:30:13 2011 (r1301) @@ -2152,7 +2152,7 @@ if (!force_boardenable) { msg_pinfo("WARNING: Your mainboard is %s %s, but the mainboard-specific\n" - "code has not been tested, and thus will not not be executed by default.\n" + "code has not been tested, and thus will not be executed by default.\n" "Depending on your hardware environment, erasing, writing or even probing\n" "can fail without running the board specific code.\n\n" "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n"

1 0

[PATCH 5/5] introduce a global variable to save the maximum number of bytes in an SPI transaction supported by this programmer and use that to simplify code
by Stefan Tauner 17 May '11

17 May '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 45 +++++++++++++++++++++------------------------ 1 files changed, 21 insertions(+), 24 deletions(-) diff --git a/ichspi.c b/ichspi.c index aaf4df8..ab6af18 100644 --- a/ichspi.c +++ b/ichspi.c @@ -155,6 +155,9 @@ /* ICH SPI configuration lock-down. May be set during chipset enabling. */ static int ichspi_lock = 0; +/* Indicates maximum number of data bytes for each SPI transaction. */ +static int ichspi_maxdata = -1; + uint32_t ichspi_bbar = 0; static void *ich_spibar = NULL; @@ -911,37 +914,28 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, static int run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data) { + if (spi_programmer->type == SPI_CONTROLLER_NONE) { + msg_perr("%s: unsupported chipset\n", __func__); + return -1; + } + + if (datalength > ichspi_maxdata) { + msg_perr("%s: Internal command size error for " + "opcode 0x%02x, got datalength=%i, want <=%i\n", + __func__, op.opcode, datalength, ichspi_maxdata); + return SPI_INVALID_LENGTH; + } + switch (spi_programmer->type) { case SPI_CONTROLLER_VIA: - if (datalength > 16) { - msg_perr("%s: Internal command size error for " - "opcode 0x%02x, got datalength=%i, want <=16\n", - __func__, op.opcode, datalength); - return SPI_INVALID_LENGTH; - } - return ich7_run_opcode(op, offset, datalength, data, 16); case SPI_CONTROLLER_ICH7: - if (datalength > 64) { - msg_perr("%s: Internal command size error for " - "opcode 0x%02x, got datalength=%i, want <=16\n", - __func__, op.opcode, datalength); - return SPI_INVALID_LENGTH; - } - return ich7_run_opcode(op, offset, datalength, data, 64); + return ich7_run_opcode(op, offset, datalength, data, ichspi_maxdata); case SPI_CONTROLLER_ICH9: - if (datalength > 64) { - msg_perr("%s: Internal command size error for " - "opcode 0x%02x, got datalength=%i, want <=16\n", - __func__, op.opcode, datalength); - return SPI_INVALID_LENGTH; - } return ich9_run_opcode(op, offset, datalength, data); default: - msg_perr("%s: unsupported chipset\n", __func__); + /* If we ever get here, something really weird happened */ + return -1; } - - /* If we ever get here, something really weird happened */ - return -1; } static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, @@ -1206,6 +1200,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, break; } + ichspi_maxdata = 64; + /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */ msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", base, spibar_offset); @@ -1356,6 +1352,7 @@ int via_init_spi(struct pci_dev *dev) /* Not sure if it speaks all these bus protocols. */ buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; register_spi_programmer(&spi_programmer_via); + ichspi_maxdata = 16; msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2)); -- 1.7.1

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[PATCH 4/5] add macros and pretty printing for HSFS and HSFC
by Stefan Tauner 17 May '11

17 May '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++++++---------- 1 files changed, 62 insertions(+), 12 deletions(-) diff --git a/ichspi.c b/ichspi.c index f5d6bbc..aaf4df8 100644 --- a/ichspi.c +++ b/ichspi.c @@ -46,6 +46,37 @@ #define ICH9_REG_FADDR 0x08 /* 32 Bits */ #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ +#define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status Register */ +#define HSFS_FDONE_OFF 0 /* 0: Flash Cycle Done */ +#define HSFS_FDONE (0x1 << HSFS_FDONE_OFF) +#define HSFS_FCERR_OFF 1 /* 1: Flash Cycle Error */ +#define HSFS_FCERR (0x1 << HSFS_FCERR_OFF) +#define HSFS_AEL_OFF 2 /* 2: Access Error Log */ +#define HSFS_AEL (0x1 << HSFS_AEL_OFF) +#define HSFS_BERASE_OFF 3 /* 3-4: Block/Sector Erase Size */ +#define HSFS_BERASE (0x1 << HSFS_BERASE_OFF) +#define HSFS_SCIP_OFF 5 /* 5: SPI Cycle In Progress */ +#define HSFS_SCIP (0x1 << HSFS_SCIP_OFF) + /* 6-12: reserved */ +#define HSFS_FDOPSS_OFF 13 /* 13: Flash Descriptor Override Pin-Strap Status */ +#define HSFS_FDOPSS (0x1 << HSFS_FDOPSS_OFF) +#define HSFS_FDV_OFF 14 /* 14: Flash Descriptor Valid */ +#define HSFS_FDV (0x1 << HSFS_FDV_OFF) +#define HSFS_FLOCKDN_OFF 15 /* 15: Flash Configuration Lock-Down */ +#define HSFS_FLOCKDN (0x1 << HSFS_FLOCKDN_OFF) + +#define ICH9_REG_HSFC 0x06 /* 16 Bits Hardware Sequencing Flash Control Register */ +#define HSFC_FGO_OFF 0 /* 0: Flash Cycle Go */ +#define HSFC_FGO (0x1 << HSFC_FGO_OFF) +#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ +#define HSFC_FCYCLE (0x1 << HSFC_FCYCLE_OFF) + /* 3-7: reserved */ +#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ +#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF) + /* 14: reserved */ +#define HSFC_SME_OFF 15 /* 15: SPI SMI# Enable */ +#define HSFC_SME (0x1 << HSFC_SME_OFF) + #define ICH9_REG_SSFS 0x90 /* 08 Bits */ #define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */ #define SSFS_SCIP (0x1 << SSFS_SCIP_OFF) @@ -259,6 +290,28 @@ static void pretty_print_opcodes(OPCODES *ops) } #define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) +static void prettyprint_ich9_reg_hsfs(uint16_t reg_val) +{ + msg_pdbg("HSFS: "); + pprint_reg(HSFS, FDONE, reg_val, ", "); + pprint_reg(HSFS, FCERR, reg_val, ", "); + pprint_reg(HSFS, AEL, reg_val, ", "); + pprint_reg(HSFS, BERASE, reg_val, ", "); + pprint_reg(HSFS, SCIP, reg_val, ", "); + pprint_reg(HSFS, FDOPSS, reg_val, ", "); + pprint_reg(HSFS, FDV, reg_val, ", "); + pprint_reg(HSFS, FLOCKDN, reg_val, "\n"); +} + +static void prettyprint_ich9_reg_hsfc(uint16_t reg_val) +{ + msg_pdbg("HSFC: "); + pprint_reg(HSFC, FGO, reg_val, ", "); + pprint_reg(HSFC, FCYCLE, reg_val, ", "); + pprint_reg(HSFC, FDBC, reg_val, ", "); + pprint_reg(HSFC, SME, reg_val, "\n"); +} + static void prettyprint_ich9_reg_ssfs(uint32_t reg_val) { msg_pdbg("SSFS: "); @@ -1201,14 +1254,15 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, case SPI_CONTROLLER_ICH9: tmp2 = mmio_readw(ich_spibar + 4); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); - msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1)); - msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1); - msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1); - msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1); - msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3); - msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1); - msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1); - msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1); + prettyprint_ich9_reg_hsfs(tmp2); + if (tmp2 & (1 << 15)) { + msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); + ichspi_lock = 1; + } + + tmp2 = mmio_readw(ich_spibar + 6); + msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); + prettyprint_ich9_reg_hsfc(tmp2); tmp = mmio_readl(ich_spibar + 0x50); msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); @@ -1255,10 +1309,6 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, ichspi_bbar); msg_pdbg("0xB0: 0x%08x (FDOC)\n", mmio_readl(ich_spibar + 0xB0)); - if (tmp2 & (1 << 15)) { - msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); - ichspi_lock = 1; - } ich_init_opcodes(); break; default: -- 1.7.1

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[PATCH 3/5] add pretty printing functions for SSFS+SSFC and the OPCODE struct and use them
by Stefan Tauner 17 May '11

17 May '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 50 ++++++++++++++++++++++++++++++++++++++++++++------ 1 files changed, 44 insertions(+), 6 deletions(-) diff --git a/ichspi.c b/ichspi.c index 67c4efb..f5d6bbc 100644 --- a/ichspi.c +++ b/ichspi.c @@ -242,6 +242,44 @@ static OPCODE POSSIBLE_OPCODES[] = { static OPCODES O_EXISTING = {}; +/* pretty printing functions */ +static void pretty_print_opcodes(OPCODES *ops) +{ + if(ops == NULL) + return; + + msg_pdbg("preop0=0x%02x, preop1=0x%02x\n", ops->preop[0], ops->preop[1]); + + OPCODE oc; + uint8_t i; + for (i = 0; i < 8; i++) { + oc = ops->opcode[i]; + msg_pdbg("op[%d]=0x%02x, %d, %d\n", i, oc.opcode, oc.spi_type, oc.atomic); + } +} + +#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) +static void prettyprint_ich9_reg_ssfs(uint32_t reg_val) +{ + msg_pdbg("SSFS: "); + pprint_reg(SSFS, SCIP, reg_val, ", "); + pprint_reg(SSFS, FDONE, reg_val, ", "); + pprint_reg(SSFS, FCERR, reg_val, ", "); + pprint_reg(SSFS, AEL, reg_val, "\n"); +} + +static void prettyprint_ich9_reg_ssfc(uint32_t reg_val) +{ + msg_pdbg("SSFC: "); + pprint_reg(SSFC, SCGO, reg_val, ", "); + pprint_reg(SSFC, ACS, reg_val, ", "); + pprint_reg(SSFC, SPOP, reg_val, ", "); + pprint_reg(SSFC, COP, reg_val, ", "); + pprint_reg(SSFC, DBC, reg_val, ", "); + pprint_reg(SSFC, SME, reg_val, ", "); + pprint_reg(SSFC, SCF, reg_val, "\n"); +} + static uint8_t lookup_spi_type(uint8_t opcode) { int a; @@ -518,6 +556,7 @@ static int ich_init_opcodes(void) } else { curopcodes = curopcodes_done; msg_pdbg("done\n"); + pretty_print_opcodes(curopcodes); return 0; } } @@ -792,6 +831,8 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, temp32 = REGREAD32(ICH9_REG_SSFS); if (temp32 & SSFS_FCERR) { msg_perr("Transaction error!\n"); + prettyprint_ich9_reg_ssfs(temp32); + prettyprint_ich9_reg_ssfc(temp32); /* keep reserved bits */ temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; /* Clear the transaction error. */ @@ -1193,16 +1234,13 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, tmp = mmio_readl(ich_spibar + 0x90); msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff); - msg_pdbg("AEL %i, ", (tmp >> 4) & 1); - msg_pdbg("FCERR %i, ", (tmp >> 3) & 1); - msg_pdbg("FDONE %i, ", (tmp >> 2) & 1); - msg_pdbg("SCIP %i\n", (tmp >> 0) & 1); + prettyprint_ich9_reg_ssfs(tmp); if (tmp & (1 << 3)) { msg_pdbg("Clearing SSFS.FCERR\n"); mmio_writeb(1 << 3, ich_spibar + 0x90); } - tmp >>= 8; - msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp); + msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp >> 8); + prettyprint_ich9_reg_ssfc(tmp); msg_pdbg("0x94: 0x%04x (PREOP)\n", mmio_readw(ich_spibar + 0x94)); -- 1.7.1

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[PATCH 2/5] improve macros for SSFS and SSFC bits
by Stefan Tauner 17 May '11

17 May '11

- introduce offset macros and use them to (re)define the existing mask macros - add comments - rename SSFS_CDS to SSFS_FDONE (abbr. used in datasheet not in SSFS but HSFS) - use those for refactoring and magic number elemination. - following patch uses them for pretty printing Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 48 ++++++++++++++++++++++++++++++------------------ 1 files changed, 30 insertions(+), 18 deletions(-) diff --git a/ichspi.c b/ichspi.c index 0569d33..67c4efb 100644 --- a/ichspi.c +++ b/ichspi.c @@ -47,23 +47,35 @@ #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ #define ICH9_REG_SSFS 0x90 /* 08 Bits */ -#define SSFS_SCIP 0x00000001 -#define SSFS_CDS 0x00000004 -#define SSFS_FCERR 0x00000008 -#define SSFS_AEL 0x00000010 +#define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */ +#define SSFS_SCIP (0x1 << SSFS_SCIP_OFF) +#define SSFS_FDONE_OFF 2 /* Cycle Done Status */ +#define SSFS_FDONE (0x1 << SSFS_FDONE_OFF) +#define SSFS_FCERR_OFF 3 /* Flash Cycle Error */ +#define SSFS_FCERR (0x1 << SSFS_FCERR_OFF) +#define SSFS_AEL_OFF 4 /* Access Error Log */ +#define SSFS_AEL (0x1 << SSFS_AEL_OFF) #define SSFS_RESERVED_MASK 0x000000e2 #define ICH9_REG_SSFC 0x91 /* 24 Bits */ -#define SSFC_SCGO 0x00000200 -#define SSFC_ACS 0x00000400 -#define SSFC_SPOP 0x00000800 -#define SSFC_COP 0x00001000 -#define SSFC_DBC 0x00010000 -#define SSFC_DS 0x00400000 -#define SSFC_SME 0x00800000 -#define SSFC_SCF 0x01000000 -#define SSFC_SCF_20MHZ 0x00000000 -#define SSFC_SCF_33MHZ 0x01000000 +#define SSFC_SCGO_OFF (1 + 8) /* 1: SPI Cycle Go */ +#define SSFC_SCGO (0x1 << SSFC_SCGO_OFF) +#define SSFC_ACS_OFF (2 + 8) /* 2: Atomic Cycle Sequence */ +#define SSFC_ACS (0x1 << SSFC_ACS_OFF) +#define SSFC_SPOP_OFF (3 + 8) /* 3: Sequence Prefix Opcode Pointer */ +#define SSFC_SPOP (0x1 << SSFC_SPOP_OFF) +#define SSFC_COP_OFF (4 + 8) /* 4-6: Cycle Opcode Pointer */ +#define SSFC_COP (0x7 << SSFC_COP_OFF) +#define SSFC_DBC_OFF (8 + 8) /* 8-13: Data Byte Count */ +#define SSFC_DBC (0x3f << SSFC_DBC_OFF) +#define SSFC_DS_OFF (14 + 8) /* 14: Data Cycle */ +#define SSFC_DS (0x1 << SSFC_DS_OFF) +#define SSFC_SME_OFF (15 + 8) /* 15: SPI SMI# Enable */ +#define SSFC_SME (0x1 << SSFC_SME_OFF) +#define SSFC_SCF_OFF (16 + 8) /* 16-18: SPI Cycle Frequency */ +#define SSFC_SCF (0x7 << SSFC_SCF_OFF) +#define SSFC_SCF_20MHZ 0x00000000 +#define SSFC_SCF_33MHZ 0x01000000 /* We combine SSFS and SSFC to one 32-bit word, * therefore SSFC bits are off by 8. * The following bits are reserved SSFC: 23-19,7,0; SSFS: 5-7. */ @@ -708,8 +720,8 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, temp32 = REGREAD32(ICH9_REG_SSFS); /* Keep reserved bits only */ temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; - /* clear error status registers */ - temp32 |= (SSFS_CDS + SSFS_FCERR); + /* Clear cycle done and cycle error status registers */ + temp32 |= (SSFS_FDONE + SSFS_FCERR); REGWRITE32(ICH9_REG_SSFS, temp32); /* Use 20 MHz */ @@ -719,7 +731,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, if (datalength != 0) { uint32_t datatemp; temp32 |= SSFC_DS; - datatemp = ((uint32_t) ((datalength - 1) & 0x3f)) << (8 + 8); + datatemp = (uint32_t) (((datalength - 1) << SSFC_DBC_OFF) & SSFC_DBC); temp32 |= datatemp; } @@ -766,7 +778,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, REGWRITE32(ICH9_REG_SSFS, temp32); /* Wait for Cycle Done Status or Flash Cycle Error. */ - while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_CDS | SSFS_FCERR)) == 0) && + while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_FDONE | SSFS_FCERR)) == 0) && --timeout) { programmer_delay(10); } -- 1.7.1

1 0

[PATCH 1/5] whitespace fixes (space to tabs mostly) and (additional) comments
by Stefan Tauner 17 May '11

17 May '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 54 +++++++++++++++++++++++++++++------------------------- 1 files changed, 29 insertions(+), 25 deletions(-) diff --git a/ichspi.c b/ichspi.c index ddd14d3..0569d33 100644 --- a/ichspi.c +++ b/ichspi.c @@ -43,17 +43,17 @@ #include "spi.h" /* ICH9 controller register definition */ -#define ICH9_REG_FADDR 0x08 /* 32 Bits */ -#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ +#define ICH9_REG_FADDR 0x08 /* 32 Bits */ +#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ -#define ICH9_REG_SSFS 0x90 /* 08 Bits */ +#define ICH9_REG_SSFS 0x90 /* 08 Bits */ #define SSFS_SCIP 0x00000001 #define SSFS_CDS 0x00000004 #define SSFS_FCERR 0x00000008 #define SSFS_AEL 0x00000010 #define SSFS_RESERVED_MASK 0x000000e2 -#define ICH9_REG_SSFC 0x91 /* 24 Bits */ +#define ICH9_REG_SSFC 0x91 /* 24 Bits */ #define SSFC_SCGO 0x00000200 #define SSFC_ACS 0x00000400 #define SSFC_SPOP 0x00000800 @@ -64,20 +64,23 @@ #define SSFC_SCF 0x01000000 #define SSFC_SCF_20MHZ 0x00000000 #define SSFC_SCF_33MHZ 0x01000000 +/* We combine SSFS and SSFC to one 32-bit word, + * therefore SSFC bits are off by 8. + * The following bits are reserved SSFC: 23-19,7,0; SSFS: 5-7. */ #define SSFC_RESERVED_MASK 0xf8008100 -#define ICH9_REG_PREOP 0x94 /* 16 Bits */ -#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */ -#define ICH9_REG_OPMENU 0x98 /* 64 Bits */ +#define ICH9_REG_PREOP 0x94 /* 16 Bits */ +#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */ +#define ICH9_REG_OPMENU 0x98 /* 64 Bits */ // ICH9R SPI commands -#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0 -#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1 -#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2 -#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3 +#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0 +#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1 +#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2 +#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3 // ICH7 registers -#define ICH7_REG_SPIS 0x00 /* 16 Bits */ +#define ICH7_REG_SPIS 0x00 /* 16 Bits */ #define SPIS_SCIP 0x0001 #define SPIS_GRANT 0x0002 #define SPIS_CDS 0x0004 @@ -94,17 +97,17 @@ bit 7 is used with fast read and one shot controls CS de-assert? */ -#define ICH7_REG_SPIC 0x02 /* 16 Bits */ -#define SPIC_SCGO 0x0002 -#define SPIC_ACS 0x0004 -#define SPIC_SPOP 0x0008 -#define SPIC_DS 0x4000 +#define ICH7_REG_SPIC 0x02 /* 16 Bits */ +#define SPIC_SCGO 0x0002 +#define SPIC_ACS 0x0004 +#define SPIC_SPOP 0x0008 +#define SPIC_DS 0x4000 -#define ICH7_REG_SPIA 0x04 /* 32 Bits */ -#define ICH7_REG_SPID0 0x08 /* 64 Bytes */ -#define ICH7_REG_PREOP 0x54 /* 16 Bits */ -#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */ -#define ICH7_REG_OPMENU 0x58 /* 64 Bits */ +#define ICH7_REG_SPIA 0x04 /* 32 Bits */ +#define ICH7_REG_SPID0 0x08 /* 64 Bytes */ +#define ICH7_REG_PREOP 0x54 /* 16 Bits */ +#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */ +#define ICH7_REG_OPMENU 0x58 /* 64 Bits */ /* ICH SPI configuration lock-down. May be set during chipset enabling. */ static int ichspi_lock = 0; @@ -597,7 +600,7 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, - waiting for the busy bit (WIP) to be cleared This means the timeout must be sufficient for chip erase of slow high-capacity chips. - */ + */ switch (op.atomic) { case 2: /* Select second preop. */ @@ -703,7 +706,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, /* Assemble SSFS + SSFC */ temp32 = REGREAD32(ICH9_REG_SSFS); - /* keep reserved bits */ + /* Keep reserved bits only */ temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; /* clear error status registers */ temp32 |= (SSFS_CDS + SSFS_FCERR); @@ -712,6 +715,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, /* Use 20 MHz */ temp32 |= SSFC_SCF_20MHZ; + /* Set data byte count (DBC) and data cycle bit (DS) */ if (datalength != 0) { uint32_t datatemp; temp32 |= SSFC_DS; @@ -742,7 +746,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, - waiting for the busy bit (WIP) to be cleared This means the timeout must be sufficient for chip erase of slow high-capacity chips. - */ + */ switch (op.atomic) { case 2: /* Select second preop. */ -- 1.7.1

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[PATCH 0/5] ichspi patches 2.0
by Stefan Tauner 17 May '11

17 May '11

I have revised my first patch set which does nothing fancy but improves the output of ichspi mostly. I combined 1/6 and 2/6 to this one's 1/5 because they are tiny anyway. 1/6 did not receive an ack yet, but since it's trivial i'll self-ack 1/5 if no one objects. 2/5 now uses the offsets to define the bit masks as suggested by stefan reinauer. 3/5 (4/6) and 5/5 (6/6) were already acked (via irc) iirc. the latter has been changed due to r1299 (kill central list of SPI programmers). 5/6 is already committed. 4/5 introduces new macros and pretty printing for the hardware sequencing registers. Stefan Tauner (5): whitespace fixes (space to tabs mostly) and (additional) comments improve macros for SSFS and SSFC bits add pretty printing functions for SSFS+SSFC and the OPCODE struct and use them add macros and pretty printing for HSFS and HSFC introduce a global variable to save the maximum number of bytes in an SPI transaction supported by this programmer and use that to simplify code ichspi.c | 273 ++++++++++++++++++++++++++++++++++++++++++-------------------- 1 files changed, 187 insertions(+), 86 deletions(-)

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erase failed: ASUS A8AE-LE
by Kris King 17 May '11

17 May '11

Thank you for helping, even if there is no fix, or my mobo dies waiting. This is exactly why I joined the linux community. Incase this is helpful this is the failure in progress... falserunes@TITANIUM:~$ cd bios falserunes@TITANIUM:~/bios$ sudo flashrom -w 315.rom [sudo] password for falserunes: flashrom v0.9.3-r1291 on Linux 2.6.35-28-generic (x86_64), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... delay loop is unreliable, trying to continue OK. Found chipset "ATI SB400", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Found chip "PMC Pm49FL004" (512 KB, LPC,FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Erasing and writing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x25, failed byte count from 0x00000000-0x00000fff: 0xfed ERASE FAILED! ERASE FAILED at 0x00000000! Expected=0xff, Read=0x25, failed byte count from 0x00000000-0x0000ffff: 0xfee8 ERASE FAILED! ERASE FAILED at 0x00000000! Expected=0xff, Read=0x25, failed byte count from 0x00000000-0x0007ffff: 0x590c1 ERASE FAILED! Done. Verifying flash... VERIFY FAILED at 0x00000000! Expected=0x24, Read=0x25, failed byte count from 0x00000000-0x0007ffff: 0x51472 Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with FAILED: your board name in the subject line! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! falserunes@TITANIUM:~/bios$

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[commit] r1300 - trunk
by repository service 17 May '11

17 May '11

Author: stefanct Date: Tue May 17 15:31:55 2011 New Revision: 1300 URL: http://flashrom.org/trac/flashrom/changeset/1300 Log: add board enable for Asus A8AE-LE (HP OEM) Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Wed May 11 19:07:07 2011 (r1299) +++ trunk/board_enable.c Tue May 17 15:31:55 2011 (r1300) @@ -1081,6 +1081,35 @@ } /* + * Suited for: + * - Asus A8AE-LE (Codename AmberineM; used in Compaq Presario 061) + * Datasheet(s) used: + * - AMD document 43009 "AMD SB700/710/750 Register Reference Guide" rev. 1.00 + */ +static int amd_sbxxx_gpio9_raise(void) +{ + struct pci_dev *dev; + uint32_t reg; + + dev = pci_dev_find(0x1002, 0x4372); /* AMD SMBus Controller */ + if (!dev) { + msg_perr("\nERROR: AMD SMBus Controller (0x4372) not found.\n"); + return -1; + } + + reg = pci_read_long(dev, 0xA8); /* GPIO_12_to_4_Cntrl CI_Reg: A8h-ABh */ + /* enable output (0: enable, 1: tristate): + GPIO9 output enable is at bit 5 in 0xA9 */ + reg &= ~((uint32_t)1<<(8+5)); + /* raise: + GPIO9 output register is at bit 5 in 0xA8 */ + reg |= (1<<5); + pci_write_long(dev, 0xA8, reg); + + return 0; +} + +/* * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}. */ static int intel_piix4_gpo_set(unsigned int gpo, int raise) @@ -1924,6 +1953,7 @@ {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V8X", 0, OK, it8703f_gpio51_raise}, {0x1106, 0x3099, 0x1043, 0x807F, 0x1106, 0x3147, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V333", 0, OK, it8703f_gpio51_raise}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, P3, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise}, + {0x1002, 0x4372, 0x103c, 0x2a26, 0x1002, 0x4377, 0x103c, 0x2a26, NULL, NULL, NULL, P3, "ASUS", "A8AE-LE", 0, OK, amd_sbxxx_gpio9_raise}, {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, P3, "ASUS", "A8Jm", 0, NT, intel_ich_gpio34_raise}, {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI2L", NULL, NULL, P3, "ASUS", "A8N-LA (Nagami-GL8E)", 0, OK, nvidia_mcp_gpio0_raise}, {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, P3, "ASUS", "A8N", 0, NT, board_shuttle_fn25}, /* TODO: This should probably be A8N-SLI Deluxe, see http://www.coreboot.org/pipermail/flashrom/2009-November/000878.html. */

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Re: [flashrom] [coreboot] BIOS Protection Guidelines from NIST
by Paul Menzel 17 May '11

17 May '11

Am Dienstag, den 17.05.2011, 12:59 +0400 schrieb Антон Кочков: > April 2011: > > http://csrc.nist.gov/publications/nistpubs/800-147/NIST-SP800-147-April2011… Thank you for the URL. coreboot is not even mentioned. Searching for »source« or »closed« did not turn anything up either, so I guess having access to the source code is not mentioned as an essential way of protection. I guess you guys (adding flashrom to CC) will have more comments. Will you post them in your answers? Maybe we can contact the authors of this article too. Thanks, Paul

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Set DST bit in RTC clock?
by Peter Daum 17 May '11

17 May '11

Hi, this is admittedly a little off-topic but I with all the BIOS-experts here, I hope there might be somebody who knows about this: Is there any way to modify the daylight savings time bit (see http://www.plasma-online.de/textual/download/misc/cmos_registers.html) of the "realtime" clock of a i386 machine running linux? "nvramtool" won't touch the 1st 14 bytes of the CMOS. I tried changing "hwclock" but this uses the kernel rtc driver which obviously also does not allow to change the DST setting. (This is of course useless for Linux - I need it in connection with problems involving some well-known system from Redmond ...) Any ideas? Regards, Peter

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[PATCH] Add lock printing for AMD8111 chipset
by Joshua Roys 16 May '11

16 May '11

Hello, This is for csugah from IRC. http://paste.flashrom.org/view.php?id=570 http://paste.flashrom.org/view.php?id=571 http://paste.flashrom.org/view.php?id=572 http://paste.flashrom.org/view.php?id=573 The attached patch should help diagnose your board. Also, csugah, try this patch to fix the segv you were seeing: http://patchwork.coreboot.org/patch/2878/ Add lock printing for the AMD8111. Signed-off-by: Joshua Roys <roysjosh(a)gmail.com> Joshua Roys

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VIA VT6421A LPC programmer
by XVilka Haos of System 16 May '11

16 May '11

This board contain Winbond W39V040BPZ chip http://paste.flashrom.org/view.php?id=569 Best regards, XVilka.

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XW9400 upgrade
by Nigel R 15 May '11

15 May '11

Sorry if this has been gone through before but... I've been put off by the various problems I've read about updating the BIOS on my XW9400 motherboard to support quad core processors. There seem to be various problems ( mac addresses going awol ) and things that need to be done ( connecting jumpers etc. ) which have made me think it isn't worth it. But - I've decided I want to give it a go... My understanding is that I need to short out a jumper on the board - I think I know which points I have to bridge - but does anyone have a picture - just to make me feel sure I'm not going to blow the entire board up :-/ I have the latest version of flashrom - the process I think I need to go through is ... I've used sudo flashrom -r biosbackup.rom -m hp:xw9400 to copy the current image. I'm assuming I have to use sudo flashrom -m hp:xw9400 -w 7D6_0403.bin to flash it with the 4.03 image off the HP web site. I'm assuming that with the write enable, this will update the boot block - but will this also remove the MAC addresses - or is that some other problem people have had? Thanks for any help. Nigel

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My USB+AVR-based flasher (w/ serprog protocol fw) gets spi support and a little webpage
by Urja Rannikko 15 May '11

15 May '11

Hi, I didnt want to mix this randomness into my patch mail, so I'm sending two. I set up a simple web page for serving all the files related to this little project of mine: http://urjaman.dyndns.info/usbavrprog/ . You might be able to see that there is a reason for why I dont normally do web design stuff ;), but it gets this stuff out. (FYI: This webserver is going to be down starting 2011/05/21, hopefully ending before end of 2011/06.) Also, I've written code for it and for flashrom to support SPI protocol over serprog, so I will be sending a patch to flashrom next. -- Urja Rannikko aka urjaman

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jidacmos
by Taylor Thomson Wisbeck 13 May '11

13 May '11

Hi, Someone can send me the executable "jidacmos.exe". Thanks Taylor

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fail update bios
by Abashev Danila 12 May '11

12 May '11

Hello! I have EPoX EP-8RDAEI. I I can not update bios. Details in the attached files. Restored the bios from a previously created backup. The system reboots normally.

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Re: [flashrom] Erase faild
by Stefan Reinauer 12 May '11

12 May '11

* Marco Runge <Marco_Runge(a)raykiel.com> [110512 14:46]: > I am a Software Engineer from Raytheon Ansch tz Germany and wanted to use > flashrom to update the bios of our embedded bord form emerson. Unfortuneately > s.th. must have gone wrong. First write of the bios was fine but after reboot I > got a crisis report that the two flash banks are corrupt. I could boot from > thumb drive anyway and wanted to write the backup copy but got the following > error message: > > Erase failed at 0x00000010! Expected=0xff, Read=0x5a, failed byte count from > 0x00000000 - 0x0000ffff: 0xd092. > > We are using the following board: http://www.emersonnetworkpower.com/en-US/ > Products/EmbeddedComputing/CompactPCI/Pages/EmbCompCPCI7203.aspx > > Chipset: Intel Ibex Peak > Found chipset: Atmel AT25DF641 8192Kb SPI at 0xff800000 > > I hope you can help Please post the full log (possibly with --verbose) Also, does the image in flash match what you previously read from the chip? In that case it's most likely that the flash is write protected Stefan

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Erase faild
by Marco Runge 12 May '11

12 May '11

Hi, I am a Software Engineer from Raytheon Anschütz Germany and wanted to use flashrom to update the bios of our embedded bord form emerson. Unfortuneately s.th. must have gone wrong. First write of the bios was fine but after reboot I got a crisis report that the two flash banks are corrupt. I could boot from thumb drive anyway and wanted to write the backup copy but got the following error message: Erase failed at 0x00000010! Expected=0xff, Read=0x5a, failed byte count from 0x00000000 - 0x0000ffff: 0xd092. We are using the following board: http://www.emersonnetworkpower.com/en-US/Products/EmbeddedComputing/Compact… Chipset: Intel Ibex Peak Found chipset: Atmel AT25DF641 8192Kb SPI at 0xff800000 I hope you can help Best regards Marco Runge Marco Runge Software Engineer EDA BAD Raytheon Anschuetz GmbH +49 431 3019 646 office +49 431 3019 291 fax Marco_Runge(a)raykiel.com Zeyestrasse 16 - 24 D-24106 Kiel Germany www.raytheon-anschuetz.com Raytheon Anschuetz GmbH Sitz der Gesellschaft: Kiel Registergericht: Amtsgericht Kiel HRB 4086 Geschaeftsfuehrer: Dr. Lueder Hogrefe Vorsitzender des Aufsichtsrats: Patrick K. Peppe Diese Nachricht enthaelt vertrauliche oder rechtlich geschuetzte Informationen. Wenn Sie nicht der beabsichtigte Empfaenger sind, informieren Sie bitte sofort den Absender und loeschen Sie diese Nachricht. Das unbefugte Kopieren dieser Nachricht oder die unbefugte Weitergabe der enthaltenen Informationen ist nicht gestattet. The information contained in this message is confidential or protected by law. If you are not the intended recipient, please contact the sender and delete this message. Any unauthorized copying of this message or unauthorized distribution of the information contained herein is prohibited.

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Re: [flashrom] [PATCH 1/3] Factor out SPI write/read chunking wrappers.
by Carl-Daniel Hailfinger 11 May '11

11 May '11

Hi Michael, thanks for your patch! Am 05.05.2011 03:04 schrieb Michael Karcher: > diff --git a/dummyflasher.c b/dummyflasher.c > index d818a84..b6e67db 100644 > --- a/dummyflasher.c > +++ b/dummyflasher.c > @@ -507,12 +507,6 @@ int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, > return 0; > } > > -int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > -{ > - /* Maximum read length is unlimited, use 64kB. */ > - return spi_read_chunked(flash, buf, start, len, 64 * 1024); > -} > - > int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > { > return spi_write_chunked(flash, buf, start, len, > Any reason you didn't kill dummy_write_256()? If you kill it, please remove it from programmer.h and adjust SPI_CONTROLLER_DUMMY in spi.c accordingly. Thanks. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH 3/3] kill central list of SPI programmers
by Carl-Daniel Hailfinger 11 May '11

11 May '11

Am 05.05.2011 03:04 schrieb Michael Karcher: > Remove the array spi_programmer, replace it by dynamic registration > instead. Also initially start with no busses supported, and switch to > the default non-SPI only for the internal programmer. > > Signed-off-by: Michael Karcher<flashrom(a)mkarcher.dialup.fu-berlin.de> > Thanks for your patch! I have a few minor nitpicks and design questions, but the code changes seem to be bug-free, so you get an Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Your patch is very readable and got me thinking about future directions of that code, especially multiple registrations... so take the review with a grain of salt. > diff --git a/dummyflasher.c b/dummyflasher.c > index c4c9c4e..fdaa5f2 100644 > --- a/dummyflasher.c > +++ b/dummyflasher.c > @@ -339,7 +339,7 @@ static int emulate_spi_chip_response(unsigned int writecnt, unsigned int readcnt > } > #endif > > -int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, > +static int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > int i; > @@ -375,12 +375,22 @@ int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, > return 0; > } > > -int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > +static int dummy_spi_write_256(struct flashchip *flash, uint8_t *buf, int start, int len) > { > return spi_write_chunked(flash, buf, start, len, > spi_write_256_chunksize); > } > > +static const struct spi_programmer spi_programmer_dummyflasher = { > + .type = SPI_CONTROLLER_DUMMY, > + .max_data_read = MAX_DATA_READ_UNLIMITED, > + .max_data_write = MAX_DATA_UNSPECIFIED, > 256 instead? > + .command = dummy_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = default_spi_read, > + .write_256 = dummy_spi_write_256, > Same comment as for patch 1 of the series. AFAICS dummy_spi_write_256 should be replaced by the default one. > +}; > + > int dummy_init(void) > { > char *bustext = NULL; > Please fix the whitespace (spaces instead of tabs) in it87spi.c and dummyflasher.c. Apparently a newline is missing at the end of spi.c. > diff --git a/bitbang_spi.c b/bitbang_spi.c > index be30944..ca28434 100644 > --- a/bitbang_spi.c > +++ b/bitbang_spi.c > @@ -81,7 +81,7 @@ static uint8_t bitbang_spi_readwrite_byte(uint8_t val) > return ret; > } > > -int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, > +static int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, > const unsigned char *writearr, unsigned char *readarr) > { > int i; > @@ -106,6 +106,16 @@ int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, > return 0; > } > > +static const struct spi_programmer spi_programmer_bitbang = { > Can you make this one non-const to allow changing .type? > + .type = SPI_CONTROLLER_BITBANG, > And leave type empty, to be filled by bitbang_spi_init()? > + .max_data_read = MAX_DATA_READ_UNLIMITED, > + .max_data_write = MAX_DATA_WRITE_UNLIMITED, > + .command = bitbang_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = default_spi_read, > + .write_256 = default_spi_write_256, > +}; > + > int bitbang_spi_init(const struct bitbang_spi_master *master, int halfperiod) > Could you extend this function signature to have an additional enum spi_controller parameter? If each bitbang-using programmer calls bitbang_spi_init(spi_controller, master, halfperiod) we can keep the spi_controller enums unchanged for now which would help us keep things consistent (for example, ichspi.c uses 3 different spi_controller enums for the same functions). > { > /* BITBANG_SPI_INVALID is 0, so if someone forgot to initialize ->type, > Insert in this function: spi_programmer_bitbang.type=spi_controller; > diff --git a/programmer.h b/programmer.h > index fefb9cd..53a50f6 100644 > --- a/programmer.h > +++ b/programmer.h > @@ -527,7 +518,6 @@ enum spi_controller { > SPI_CONTROLLER_SB600, > SPI_CONTROLLER_VIA, > SPI_CONTROLLER_WBSIO, > - SPI_CONTROLLER_MCP6X_BITBANG, > #endif > #endif > #if CONFIG_FT2232_SPI == 1 > @@ -542,16 +532,9 @@ enum spi_controller { > #if CONFIG_DEDIPROG == 1 > SPI_CONTROLLER_DEDIPROG, > #endif > -#if CONFIG_RAYER_SPI == 1 > - SPI_CONTROLLER_RAYER, > -#endif > -#if CONFIG_NICINTEL_SPI == 1 > - SPI_CONTROLLER_NICINTEL, > -#endif > -#if CONFIG_OGP_SPI == 1 > - SPI_CONTROLLER_OGP, > +#if CONFIG_OGP_SPI == 1 || CONFIG_NICINTEL_SPI == 1 || CONFIG_RAYER_SPI == 1 || (CONFIG_INTERNAL == 1&& (defined(__i386__) || defined(__x86_64__))) > + SPI_CONTROLLER_BITBANG, > #endif > - SPI_CONTROLLER_INVALID /* This must always be the last entry. */ > }; > extern const int spi_programmer_count; > If you use enum spi_controller as parameter for bitbang_spi_init(), we don't need an extra SPI_CONTROLLER_BITBANG and can keep the programmer-specific ones. The calls to bitbang_spi_init() in mcp6x_spi.c, nicintel_spi.c, ogp_spi.c and rayer_spi.c would need to be adjusted as well. I plan to add a union private_data{} to struct spi_programmer to allow storing stuff like struct bitbang_spi_master, avoiding the need for programmer-internal static configuration variables. Regards, Carl-Daniel -- http://www.hailfinger.org/

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