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[PATCH 4/7] use the max_data_read field of the new spi_programmer struct to simplify run_opcode.
by Stefan Tauner 23 May '11

23 May '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 41 +++++++++++++++++------------------------ 1 files changed, 17 insertions(+), 24 deletions(-) diff --git a/ichspi.c b/ichspi.c index 6152fe1..eb9cc7e 100644 --- a/ichspi.c +++ b/ichspi.c @@ -913,37 +913,30 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, static int run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data) { + uint8_t maxlength = spi_programmer->max_data_read; + + if (spi_programmer->type == SPI_CONTROLLER_NONE) { + msg_perr("%s: unsupported chipset\n", __func__); + return -1; + } + + if (datalength > maxlength) { + msg_perr("%s: Internal command size error for " + "opcode 0x%02x, got datalength=%i, want <=%i\n", + __func__, op.opcode, datalength, maxlength); + return SPI_INVALID_LENGTH; + } + switch (spi_programmer->type) { case SPI_CONTROLLER_VIA: - if (datalength > 16) { - msg_perr("%s: Internal command size error for " - "opcode 0x%02x, got datalength=%i, want <=16\n", - __func__, op.opcode, datalength); - return SPI_INVALID_LENGTH; - } - return ich7_run_opcode(op, offset, datalength, data, 16); case SPI_CONTROLLER_ICH7: - if (datalength > 64) { - msg_perr("%s: Internal command size error for " - "opcode 0x%02x, got datalength=%i, want <=16\n", - __func__, op.opcode, datalength); - return SPI_INVALID_LENGTH; - } - return ich7_run_opcode(op, offset, datalength, data, 64); + return ich7_run_opcode(op, offset, datalength, data, maxlength); case SPI_CONTROLLER_ICH9: - if (datalength > 64) { - msg_perr("%s: Internal command size error for " - "opcode 0x%02x, got datalength=%i, want <=16\n", - __func__, op.opcode, datalength); - return SPI_INVALID_LENGTH; - } return ich9_run_opcode(op, offset, datalength, data); default: - msg_perr("%s: unsupported chipset\n", __func__); + /* If we ever get here, something really weird happened */ + return -1; } - - /* If we ever get here, something really weird happened */ - return -1; } static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, -- 1.7.1

1 0

[PATCH 3/7] add macros and pretty printing for HSFS and HSFC
by Stefan Tauner 23 May '11

23 May '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++++++---------- 1 files changed, 62 insertions(+), 12 deletions(-) diff --git a/ichspi.c b/ichspi.c index 2788aec..6152fe1 100644 --- a/ichspi.c +++ b/ichspi.c @@ -43,6 +43,37 @@ #include "spi.h" /* ICH9 controller register definition */ +#define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ +#define HSFS_FDONE_OFF 0 /* 0: Flash Cycle Done */ +#define HSFS_FDONE (0x1 << HSFS_FDONE_OFF) +#define HSFS_FCERR_OFF 1 /* 1: Flash Cycle Error */ +#define HSFS_FCERR (0x1 << HSFS_FCERR_OFF) +#define HSFS_AEL_OFF 2 /* 2: Access Error Log */ +#define HSFS_AEL (0x1 << HSFS_AEL_OFF) +#define HSFS_BERASE_OFF 3 /* 3-4: Block/Sector Erase Size */ +#define HSFS_BERASE (0x1 << HSFS_BERASE_OFF) +#define HSFS_SCIP_OFF 5 /* 5: SPI Cycle In Progress */ +#define HSFS_SCIP (0x1 << HSFS_SCIP_OFF) + /* 6-12: reserved */ +#define HSFS_FDOPSS_OFF 13 /* 13: Flash Descriptor Override Pin-Strap Status */ +#define HSFS_FDOPSS (0x1 << HSFS_FDOPSS_OFF) +#define HSFS_FDV_OFF 14 /* 14: Flash Descriptor Valid */ +#define HSFS_FDV (0x1 << HSFS_FDV_OFF) +#define HSFS_FLOCKDN_OFF 15 /* 15: Flash Configuration Lock-Down */ +#define HSFS_FLOCKDN (0x1 << HSFS_FLOCKDN_OFF) + +#define ICH9_REG_HSFC 0x06 /* 16 Bits Hardware Sequencing Flash Control */ +#define HSFC_FGO_OFF 0 /* 0: Flash Cycle Go */ +#define HSFC_FGO (0x1 << HSFC_FGO_OFF) +#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ +#define HSFC_FCYCLE (0x1 << HSFC_FCYCLE_OFF) + /* 3-7: reserved */ +#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ +#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF) + /* 14: reserved */ +#define HSFC_SME_OFF 15 /* 15: SPI SMI# Enable */ +#define HSFC_SME (0x1 << HSFC_SME_OFF) + #define ICH9_REG_FADDR 0x08 /* 32 Bits */ #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ @@ -260,6 +291,28 @@ static void pretty_print_opcodes(OPCODES *ops) } #define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) +static void prettyprint_ich9_reg_hsfs(uint16_t reg_val) +{ + msg_pdbg("HSFS: "); + pprint_reg(HSFS, FDONE, reg_val, ", "); + pprint_reg(HSFS, FCERR, reg_val, ", "); + pprint_reg(HSFS, AEL, reg_val, ", "); + pprint_reg(HSFS, BERASE, reg_val, ", "); + pprint_reg(HSFS, SCIP, reg_val, ", "); + pprint_reg(HSFS, FDOPSS, reg_val, ", "); + pprint_reg(HSFS, FDV, reg_val, ", "); + pprint_reg(HSFS, FLOCKDN, reg_val, "\n"); +} + +static void prettyprint_ich9_reg_hsfc(uint16_t reg_val) +{ + msg_pdbg("HSFC: "); + pprint_reg(HSFC, FGO, reg_val, ", "); + pprint_reg(HSFC, FCYCLE, reg_val, ", "); + pprint_reg(HSFC, FDBC, reg_val, ", "); + pprint_reg(HSFC, SME, reg_val, "\n"); +} + static void prettyprint_ich9_reg_ssfs(uint32_t reg_val) { msg_pdbg("SSFS: "); @@ -1203,14 +1256,15 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, case SPI_CONTROLLER_ICH9: tmp2 = mmio_readw(ich_spibar + 4); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); - msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1)); - msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1); - msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1); - msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1); - msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3); - msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1); - msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1); - msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1); + prettyprint_ich9_reg_hsfs(tmp2); + if (tmp2 & (1 << 15)) { + msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); + ichspi_lock = 1; + } + + tmp2 = mmio_readw(ich_spibar + 6); + msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); + prettyprint_ich9_reg_hsfc(tmp2); tmp = mmio_readl(ich_spibar + 0x50); msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); @@ -1257,10 +1311,6 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, ichspi_bbar); msg_pdbg("0xB0: 0x%08x (FDOC)\n", mmio_readl(ich_spibar + 0xB0)); - if (tmp2 & (1 << 15)) { - msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); - ichspi_lock = 1; - } ich_init_opcodes(); break; default: -- 1.7.1

1 0

[PATCH 2/7] add pretty printing functions for SSFS+SSFC and the OPCODE struct and use them
by Stefan Tauner 23 May '11

23 May '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 51 +++++++++++++++++++++++++++++++++++++++++++++------ 1 files changed, 45 insertions(+), 6 deletions(-) diff --git a/ichspi.c b/ichspi.c index 1cfdf48..2788aec 100644 --- a/ichspi.c +++ b/ichspi.c @@ -243,6 +243,44 @@ static OPCODE POSSIBLE_OPCODES[] = { static OPCODES O_EXISTING = {}; +/* pretty printing functions */ +static void pretty_print_opcodes(OPCODES *ops) +{ + if(ops == NULL) + return; + + msg_pdbg("preop0=0x%02x, preop1=0x%02x\n", ops->preop[0], ops->preop[1]); + + OPCODE oc; + uint8_t i; + for (i = 0; i < 8; i++) { + oc = ops->opcode[i]; + msg_pdbg("op[%d]=0x%02x, %d, %d\n", i, oc.opcode, oc.spi_type, oc.atomic); + } +} + +#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) +static void prettyprint_ich9_reg_ssfs(uint32_t reg_val) +{ + msg_pdbg("SSFS: "); + pprint_reg(SSFS, SCIP, reg_val, ", "); + pprint_reg(SSFS, FDONE, reg_val, ", "); + pprint_reg(SSFS, FCERR, reg_val, ", "); + pprint_reg(SSFS, AEL, reg_val, "\n"); +} + +static void prettyprint_ich9_reg_ssfc(uint32_t reg_val) +{ + msg_pdbg("SSFC: "); + pprint_reg(SSFC, SCGO, reg_val, ", "); + pprint_reg(SSFC, ACS, reg_val, ", "); + pprint_reg(SSFC, SPOP, reg_val, ", "); + pprint_reg(SSFC, COP, reg_val, ", "); + pprint_reg(SSFC, DBC, reg_val, ", "); + pprint_reg(SSFC, SME, reg_val, ", "); + pprint_reg(SSFC, SCF, reg_val, "\n"); +} + static uint8_t lookup_spi_type(uint8_t opcode) { int a; @@ -519,6 +557,8 @@ static int ich_init_opcodes(void) } else { curopcodes = curopcodes_done; msg_pdbg("done\n"); + pretty_print_opcodes(curopcodes); + msg_pdbg("\n"); return 0; } } @@ -793,6 +833,8 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, temp32 = REGREAD32(ICH9_REG_SSFS); if (temp32 & SSFS_FCERR) { msg_perr("Transaction error!\n"); + prettyprint_ich9_reg_ssfs(temp32); + prettyprint_ich9_reg_ssfc(temp32); /* keep reserved bits */ temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; /* Clear the transaction error. */ @@ -1194,16 +1236,13 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, tmp = mmio_readl(ich_spibar + 0x90); msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff); - msg_pdbg("AEL %i, ", (tmp >> 4) & 1); - msg_pdbg("FCERR %i, ", (tmp >> 3) & 1); - msg_pdbg("FDONE %i, ", (tmp >> 2) & 1); - msg_pdbg("SCIP %i\n", (tmp >> 0) & 1); + prettyprint_ich9_reg_ssfs(tmp); if (tmp & (1 << 3)) { msg_pdbg("Clearing SSFS.FCERR\n"); mmio_writeb(1 << 3, ich_spibar + 0x90); } - tmp >>= 8; - msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp); + msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp >> 8); + prettyprint_ich9_reg_ssfc(tmp); msg_pdbg("0x94: 0x%04x (PREOP)\n", mmio_readw(ich_spibar + 0x94)); -- 1.7.1

1 0

[PATCH 1/7] improve macros for SSFS and SSFC bits
by Stefan Tauner 23 May '11

23 May '11

- introduce offset macros and use them to (re)define the existing mask macros - add comments - rename SSFS_CDS to SSFS_FDONE (abbr. used in datasheet not in SSFS but HSFS) - use those for refactoring and magic number elemination. - following patch uses them for pretty printing Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 48 ++++++++++++++++++++++++++++++------------------ 1 files changed, 30 insertions(+), 18 deletions(-) diff --git a/ichspi.c b/ichspi.c index 6370fb6..1cfdf48 100644 --- a/ichspi.c +++ b/ichspi.c @@ -47,24 +47,36 @@ #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ #define ICH9_REG_SSFS 0x90 /* 08 Bits */ -#define SSFS_SCIP 0x00000001 -#define SSFS_CDS 0x00000004 -#define SSFS_FCERR 0x00000008 -#define SSFS_AEL 0x00000010 +#define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */ +#define SSFS_SCIP (0x1 << SSFS_SCIP_OFF) +#define SSFS_FDONE_OFF 2 /* Cycle Done Status */ +#define SSFS_FDONE (0x1 << SSFS_FDONE_OFF) +#define SSFS_FCERR_OFF 3 /* Flash Cycle Error */ +#define SSFS_FCERR (0x1 << SSFS_FCERR_OFF) +#define SSFS_AEL_OFF 4 /* Access Error Log */ +#define SSFS_AEL (0x1 << SSFS_AEL_OFF) /* The following bits are reserved in SSFS: 1,5-7. */ #define SSFS_RESERVED_MASK 0x000000e2 #define ICH9_REG_SSFC 0x91 /* 24 Bits */ -#define SSFC_SCGO 0x00000200 -#define SSFC_ACS 0x00000400 -#define SSFC_SPOP 0x00000800 -#define SSFC_COP 0x00001000 -#define SSFC_DBC 0x00010000 -#define SSFC_DS 0x00400000 -#define SSFC_SME 0x00800000 -#define SSFC_SCF 0x01000000 -#define SSFC_SCF_20MHZ 0x00000000 -#define SSFC_SCF_33MHZ 0x01000000 +#define SSFC_SCGO_OFF (1 + 8) /* 1: SPI Cycle Go */ +#define SSFC_SCGO (0x1 << SSFC_SCGO_OFF) +#define SSFC_ACS_OFF (2 + 8) /* 2: Atomic Cycle Sequence */ +#define SSFC_ACS (0x1 << SSFC_ACS_OFF) +#define SSFC_SPOP_OFF (3 + 8) /* 3: Sequence Prefix Opcode Pointer */ +#define SSFC_SPOP (0x1 << SSFC_SPOP_OFF) +#define SSFC_COP_OFF (4 + 8) /* 4-6: Cycle Opcode Pointer */ +#define SSFC_COP (0x7 << SSFC_COP_OFF) +#define SSFC_DBC_OFF (8 + 8) /* 8-13: Data Byte Count */ +#define SSFC_DBC (0x3f << SSFC_DBC_OFF) +#define SSFC_DS_OFF (14 + 8) /* 14: Data Cycle */ +#define SSFC_DS (0x1 << SSFC_DS_OFF) +#define SSFC_SME_OFF (15 + 8) /* 15: SPI SMI# Enable */ +#define SSFC_SME (0x1 << SSFC_SME_OFF) +#define SSFC_SCF_OFF (16 + 8) /* 16-18: SPI Cycle Frequency */ +#define SSFC_SCF (0x7 << SSFC_SCF_OFF) +#define SSFC_SCF_20MHZ 0x00000000 +#define SSFC_SCF_33MHZ 0x01000000 /* We combine SSFS and SSFC to one 32-bit word, * therefore SSFC bits are off by 8. * The following bits are reserved in SSFC: 23-19,7,0. */ @@ -709,8 +721,8 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, temp32 = REGREAD32(ICH9_REG_SSFS); /* Keep reserved bits only */ temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; - /* clear error status registers */ - temp32 |= (SSFS_CDS + SSFS_FCERR); + /* Clear cycle done and cycle error status registers */ + temp32 |= (SSFS_FDONE + SSFS_FCERR); REGWRITE32(ICH9_REG_SSFS, temp32); /* Use 20 MHz */ @@ -720,7 +732,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, if (datalength != 0) { uint32_t datatemp; temp32 |= SSFC_DS; - datatemp = ((uint32_t) ((datalength - 1) & 0x3f)) << (8 + 8); + datatemp = (uint32_t) (((datalength - 1) << SSFC_DBC_OFF) & SSFC_DBC); temp32 |= datatemp; } @@ -767,7 +779,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, REGWRITE32(ICH9_REG_SSFS, temp32); /* Wait for Cycle Done Status or Flash Cycle Error. */ - while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_CDS | SSFS_FCERR)) == 0) && + while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_FDONE | SSFS_FCERR)) == 0) && --timeout) { programmer_delay(10); } -- 1.7.1

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[PATCH 0/7] ichspi patches 3.0
by Stefan Tauner 23 May '11

23 May '11

a few corrections and 3 new patches :) Stefan Tauner (7): improve macros for SSFS and SSFC bits add pretty printing functions for SSFS+SSFC and the OPCODE struct and use them add macros and pretty printing for HSFS and HSFC use the max_data_read field of the new spi_programmer struct to simplify run_opcode. warn if SMM BIOS Write Protection is detected in BIOS_CNTL add missing ICH9 register macros and use them to eliminate magic numbers add ICH/PCH flash descriptor decoding Makefile | 2 +- chipset_enable.c | 12 +- ich_descriptors.c | 415 ++++++++++++++++++++++ ich_descriptors.h | 406 +++++++++++++++++++++ ichspi.c | 279 ++++++++++----- util/ich_descriptors_tool/Makefile | 42 +++ util/ich_descriptors_tool/TODO | 5 + util/ich_descriptors_tool/ich_descriptors_tool.c | 226 ++++++++++++ 8 files changed, 1302 insertions(+), 85 deletions(-) create mode 100644 ich_descriptors.c create mode 100644 ich_descriptors.h create mode 100644 util/ich_descriptors_tool/Makefile create mode 100644 util/ich_descriptors_tool/TODO create mode 100644 util/ich_descriptors_tool/ich_descriptors_tool.c

1 0

Gigabyte P55A-UD4 works.
by Björn Augustsson 22 May '11

22 May '11

Hello folks! Just writing in to let you know that the Gigabyte P55A-UD4 seems to work fine. I say seems, because when I re-read the image back with "-r" afterwards, it doesn't exactly match the original file I wrote. Same size, but bsdiff generates a 3297 byte binary diff file (In some format...) between them. OTOH, the system boots fine, says it'd the right version (I updated from version F11 to F15, which is the latest.) I've attached the three files your docs asks for (output, lspci, superiotool) Ideas? /August. -- Wrong on most accounts. const Foo *foo; and Foo const *foo; mean the same: foo being a pointer to const Foo. const Foo const *foo; would mean the same but is illegal (double const). You are confusing this with Foo * const foo; and const Foo * const foo; respectively. -David Kastrup, comp.os.linux.development.system

2 3

Winbond W25Q128 - in Intel ICH10
by Rheneus 22 May '11

22 May '11

Hi, I could not use flashrom 0.9.3 -r1205 to detect Winbond W25Q128 to program BIOS. Attached the read log Just by adding WINBOND_NEX_W25Q128 0x4018 in flashchips.c for W25Q128, similar to W25Q64 throws run Opcode 0x3 error for read. Could you please give some suggestions. -Antony # ./flashrom -Vr ./read.bios flashrom v0.9.3-r1205 on NetBSD 5.1_STABLE (i386), built with libpci 3.1.3, GCC 4.1.3 20080704 prerelease (NetBSD nb2 20081120), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 153M loops per second, 10 myus = 10 us, 100 myus = 102 us, 1000 myus = 1026 us, 10000 myus = 10213 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. sh: dmidecode: not found dmidecode execution unsucessfull - continuing without DMI info Found chipset "Intel 3420", enabling flash write... chipset PCI ID is 8086:3b14, 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x4 0x7fffffff/0x7fffffff FWH IDSEL: 0x5 0x7fffffff/0x7fffffff FWH IDSEL: 0x6 0x7fffffff/0x7fffffff FWH IDSEL: 0x7 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x8 Root Complex Register Block address = 0xfed1c000 GCS = 0xc40: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x3 (LPC) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0x6008 (HSFS) FLOCKDN 0, FDV 1, FDOPSS 1, SCIP 0, BERASE 1, AEL 0, FCERR 0, FDONE 0 0x50: 0x0000ffff (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff 0x54: 0x00000000 (FREG0: Flash Descriptor) 0x00000000-0x00000fff is read-write 0x58: 0x07ff0400 (FREG1: BIOS) 0x00400000-0x007fffff is read-write 0x5C: 0x03ff0003 (FREG2: Management Engine) 0x00003000-0x003fffff is read-write 0x60: 0x00020001 (FREG3: Gigabit Ethernet) 0x00001000-0x00002fff is read-write 0x64: 0x00000fff (FREG4: Platform Data) 0x00fff000-0x00000fff is read-write 0x74: 0x00000000 (PR0) 0x78: 0x00000000 (PR1) 0x7C: 0x00000000 (PR2) 0x80: 0x00000000 (PR3) 0x84: 0x00000000 (PR4) 0x90: 0xf8414004 (SSFS, SSFC) 0x94: 0x5006 (PREOP) 0x96: 0x462b (OPTYPE) 0x98: 0x05ab0302 (OPMENU) 0x9C: 0xc79f0190 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xB0: 0x00001000 (FDOC) Programming OPCODES... program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 done SPI Read Configuration: prefetching enabled, caching enabled, OK. This chipset supports the following protocols: FWH,SPI. Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for AMIC A25L05PT, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for AMIC A25L05PU, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for AMIC A25L10PT, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for AMIC A25L10PU, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for AMIC A25L20PT, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for AMIC A25L20PU, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for AMIC A25L40PT, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for AMIC A25L40PU, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for AMIC A25L80P, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for AMIC A25L16PT, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for AMIC A25L16PU, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for AMIC A25L512, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for AMIC A25L010, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for AMIC A25L020, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for AMIC A25L040, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for AMIC A25L080, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for AMIC A25L016, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for AMIC A25L032, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for AMIC A25LQ032, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: skipped. Probing for Atmel AT25DF021, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Atmel AT25DF041A, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Atmel AT25DF081, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Atmel AT25DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Atmel AT25DF161, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Atmel AT25DF321A, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Atmel AT25DF641, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Atmel AT25DQ161, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Atmel AT25F512B, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Atmel AT25FS010, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Atmel AT25FS040, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Atmel AT26DF041, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Atmel AT26DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Atmel AT26DF161, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Atmel AT26DF161A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Atmel AT26F004, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Atmel AT45DB011D, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Atmel AT45DB021D, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Atmel AT45DB041D, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Atmel AT45DB081D, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Atmel AT45DB161D, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Atmel AT45DB321C, 4224 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Atmel AT45DB321D, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Atmel AT45DB642D, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F020, 256 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for Bright BM29F040, 512 KB: skipped. Probing for EMST F49B002UA, 256 KB: skipped. Probing for EMST F25L008A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Eon EN25B05, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Eon EN25B05T, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Eon EN25B10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Eon EN25B10T, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Eon EN25B20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Eon EN25B20T, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Eon EN25B40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Eon EN25B40T, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Eon EN25B80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Eon EN25B80T, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Eon EN25B16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Eon EN25B16T, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Eon EN25B32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Eon EN25B32T, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Eon EN25B64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Eon EN25B64T, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Eon EN25D16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Eon EN25F05, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Eon EN25F10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Eon EN25F20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Eon EN25F40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Eon EN25F80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Eon EN25F16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Eon EN25F32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Eon EN29F010, 128 KB: skipped. Probing for Eon EN29F002(A)(N)B, 256 KB: skipped. Probing for Eon EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Hyundai HY29F002T, 256 KB: skipped. Probing for Hyundai HY29F002B, 256 KB: skipped. Probing for Hyundai HY29F040A, 512 KB: skipped. Probing for Intel 28F001BN/BX-B, 128 KB: skipped. Probing for Intel 28F001BN/BX-T, 128 KB: skipped. Probing for Intel 28F002BC/BL/BV/BX-T, 256 KB: skipped. Probing for Intel 28F008S3/S5/SC, 512 KB: skipped. Probing for Intel 28F004B5/BE/BV/BX-B, 512 KB: skipped. Probing for Intel 28F004B5/BE/BV/BX-T, 512 KB: skipped. Probing for Intel 28F400BV/BX/CE/CV-B, 512 KB: skipped. Probing for Intel 28F400BV/BX/CE/CV-T, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Macronix MX25L1005, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Macronix MX25L2005, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Macronix MX25L4005, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Macronix MX25L1635D, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Macronix MX25L1635E, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Macronix MX25L3205, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Macronix MX25L3235D, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Macronix MX25L6405, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Macronix MX25L12805, 16384 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29F040, 512 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for MoselVitelic V29C51000B, 64 KB: skipped. Probing for MoselVitelic V29C51000T, 64 KB: skipped. Probing for MoselVitelic V29C51400B, 512 KB: skipped. Probing for MoselVitelic V29C51400T, 512 KB: skipped. Probing for MoselVitelic V29LC51000, 64 KB: skipped. Probing for MoselVitelic V29LC51001, 128 KB: skipped. Probing for MoselVitelic V29LC51002, 256 KB: skipped. Probing for Numonyx M25PE10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Numonyx M25PE20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Numonyx M25PE40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Numonyx M25PE80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Numonyx M25PE16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for PMC Pm25LV010, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for PMC Pm25LV016B, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for PMC Pm25LV020, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for PMC Pm25LV040, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for PMC Pm25LV080B, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for PMC Pm25LV512, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL004A, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Spansion S25FL008A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Spansion S25FL016A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Spansion S25FL032A, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Spansion S25FL064A, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for SST SST25VF010.REMS, 128 KB: probe_spi_rems: id1 0xef, id2 0x17 Probing for SST SST25VF016B, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for SST SST25VF032B, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for SST SST25VF064C, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for SST SST25VF040.REMS, 512 KB: probe_spi_rems: id1 0xef, id2 0x17 Probing for SST SST25VF040B, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for SST SST25LF040A.RES, 512 KB: program_opcodes: preop=5006 optype=462b opmenu=05ab0302c79f0190 on-the-fly OPCODE (0xAB) re-programmed, op-pos=2 probe_spi_res2: id1 0x17, id2 0x17 Probing for SST SST25VF040B.REMS, 512 KB: probe_spi_rems: id1 0xef, id2 0x17 Probing for SST SST25VF080B, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0x4e, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 KB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 KB: skipped. Probing for SST SST49LF020A, 256 KB: skipped. Probing for SST SST49LF040, 512 KB: skipped. Probing for SST SST49LF040B, 512 KB: skipped. Probing for SST SST49LF080A, 1024 KB: skipped. Probing for SST SST49LF160C, 2048 KB: skipped. Probing for ST M25P05-A, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for ST M25P05.RES, 64 KB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for ST M25P10.RES, 128 KB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for ST M25P40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for ST M25P40-old, 512 KB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for ST M25P16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for ST M25P32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for ST M25P64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for ST M25P128, 16384 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for ST M25PX32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for ST M25PX64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BB, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 KB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Winbond W25Q16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Winbond W25Q32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Winbond W25Q64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Winbond W25x10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Winbond W25x20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Winbond W25x40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Winbond W25x80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Winbond W25x16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Winbond W25x32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Winbond W25x64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped. Probing for Winbond W29C020(C)/W29C022, 256 KB: skipped. Probing for Winbond W29C040/P, 512 KB: skipped. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: skipped. Probing for Winbond W39V040B, 512 KB: skipped. Probing for Winbond W39V040C, 512 KB: skipped. Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 KB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 KB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 KB: skipped. Probing for Winbond W49F002U/N, 256 KB: skipped. Probing for Winbond W49F020, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: skipped. Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 KB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for AMIC unknown AMIC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Atmel unknown Atmel SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Eon unknown Eon SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Macronix unknown Macronix SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for PMC unknown PMC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for SST unknown SST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for ST unknown ST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Sanyo unknown Sanyo SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Probing for Generic unknown SPI chip (RDID), 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x4018 Found chip "Generic unknown SPI chip (RDID)" (0 KB, SPI) at physical address 0x0. Probing for Generic unknown SPI chip (REMS), 0 KB: probe_spi_rems: id1 0xef, id2 0x17 === This flash part has status NOT WORKING for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Read is not working on this chip. Aborting. Restoring PCI config space for 00:1f:0 reg 0xdc

3 7

flashrom -V
by vap vap 21 May '11

21 May '11

My chipset is not supported. Thanks.

1 0

[PATCH] add (untested) board enable for GA-K8NS Pro-939
by Stefan Tauner 20 May '11

20 May '11

this was done for a russian nick-named "general-beck" on irc. he has disappeared before testing the patch. iirc: michael dug up the right gpio; idwer and me figured the pci ids out and i put everything together in a hurry. please correct me if i am wrong :) general beck: could you test this patch? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

3 2

Re: [flashrom] [PATCH] eliminate magic numbers indicating maximum column sizes in print_supported_chipsets and print_supported_boards_helper
by Uwe Hermann 20 May '11

20 May '11

On Thu, May 19, 2011 at 02:44:19AM +0200, Stefan Tauner wrote: > without this the magic numbers need to be kept in sync with the maximum length of the > strings printed in the corresponding column. if not an overflow and a nasty ' '-storm occurs > on executing flashrom -L. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> I only did a quick code review, but the output looks good. Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

1 0

Re: [flashrom] [PATCH 5/5] introduce a global variable to save the maximum number of bytes in an SPI transaction supported by this programmer and use that to simplify code
by Stefan Tauner 19 May '11

19 May '11

On Wed, 18 May 2011 00:31:52 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: parts of this are superseded by the "kill central list of SPI programmers"-patch, namely the declaration of and writes to the global value. the new max_data_read/write fields of the spi_programmer struct can be used instead to simplify the code. (which one should i use in the case that part is even wanted by you?) > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > ichspi.c | 45 +++++++++++++++++++++------------------------ > 1 files changed, 21 insertions(+), 24 deletions(-) > > diff --git a/ichspi.c b/ichspi.c > index aaf4df8..ab6af18 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -155,6 +155,9 @@ > /* ICH SPI configuration lock-down. May be set during chipset enabling. */ > static int ichspi_lock = 0; > > +/* Indicates maximum number of data bytes for each SPI transaction. */ > +static int ichspi_maxdata = -1; > + > uint32_t ichspi_bbar = 0; > > static void *ich_spibar = NULL; > @@ -911,37 +914,28 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, > static int run_opcode(OPCODE op, uint32_t offset, > uint8_t datalength, uint8_t * data) > { > + if (spi_programmer->type == SPI_CONTROLLER_NONE) { > + msg_perr("%s: unsupported chipset\n", __func__); > + return -1; > + } > + > + if (datalength > ichspi_maxdata) { > + msg_perr("%s: Internal command size error for " > + "opcode 0x%02x, got datalength=%i, want <=%i\n", > + __func__, op.opcode, datalength, ichspi_maxdata); > + return SPI_INVALID_LENGTH; > + } > + > switch (spi_programmer->type) { > case SPI_CONTROLLER_VIA: > - if (datalength > 16) { > - msg_perr("%s: Internal command size error for " > - "opcode 0x%02x, got datalength=%i, want <=16\n", > - __func__, op.opcode, datalength); > - return SPI_INVALID_LENGTH; > - } > - return ich7_run_opcode(op, offset, datalength, data, 16); > case SPI_CONTROLLER_ICH7: > - if (datalength > 64) { > - msg_perr("%s: Internal command size error for " > - "opcode 0x%02x, got datalength=%i, want <=16\n", > - __func__, op.opcode, datalength); > - return SPI_INVALID_LENGTH; > - } > - return ich7_run_opcode(op, offset, datalength, data, 64); > + return ich7_run_opcode(op, offset, datalength, data, ichspi_maxdata); > case SPI_CONTROLLER_ICH9: > - if (datalength > 64) { > - msg_perr("%s: Internal command size error for " > - "opcode 0x%02x, got datalength=%i, want <=16\n", > - __func__, op.opcode, datalength); > - return SPI_INVALID_LENGTH; > - } > return ich9_run_opcode(op, offset, datalength, data); > default: > - msg_perr("%s: unsupported chipset\n", __func__); > + /* If we ever get here, something really weird happened */ > + return -1; > } > - > - /* If we ever get here, something really weird happened */ > - return -1; > } > > static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, > @@ -1206,6 +1200,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > break; > } > > + ichspi_maxdata = 64; > + > /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */ > msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", base, spibar_offset); > > @@ -1356,6 +1352,7 @@ int via_init_spi(struct pci_dev *dev) > /* Not sure if it speaks all these bus protocols. */ > buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; > register_spi_programmer(&spi_programmer_via); > + ichspi_maxdata = 16; > > msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); > msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2)); > -- > 1.7.1 > -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

Re: [flashrom] [PATCH 4/8] Add support for Atmel's AT25F series of SPI flash chips. This includes a new probing method (probe_spi_rdid_at25f), block erase method (spi_block_erase_62), spi_prettyprint_status_register_at25f and spi_disable_blockprotect_at25f.
by Carl-Daniel Hailfinger 19 May '11

19 May '11

Hi Stefan, thanks for your patch. As you found out, we do have a few architectural changes in locking ahead of us, and the best we can do until then is to print the decoded status register (.printlock) and unlock the whole chip (.unlock). The longterm goal is to abuse .printlock (probably renamed to .detectlock) to gather locking info for some flashrom internal data structure, and to abuse .unlock (probably renamed to .changelock) to lock and unlock regions of the flash chip. A generic lockprinting function will then simply display user-readable output for the data stored internally once .printlock has run. You might think that writing printlock functions is a waste of time considering the long-term design plans, but they actually make it a lot easier to write a proper detectlock and changelock routine, I'd even say that a conversion to detectlock/changelock becomes straightforward if you already have readable code for lock interpretation. Comments on the patch are inline. Am 15.03.2011 16:29 schrieb Stefan Tauner: > Signed-off-by: Stefan Tauner<stefan.tauner(a)student.tuwien.ac.at> > > diff --git a/chipdrivers.h b/chipdrivers.h > index dc46fe1..09dd751 100644 > --- a/chipdrivers.h > +++ b/chipdrivers.h > @@ -27,6 +27,7 @@ > > /* spi.c, should probably be in spi_chip.c */ > int probe_spi_rdid(struct flashchip *flash); > +int probe_spi_rdid_at25f(struct flashchip *flash); > That name is a bit unfortunate, it's not really related to the command we know as RDID. That said, the vendor datasheet IIRC mentions the name RDID, so naming is not totally obvious. A name like probe_spi_at25f might be less misleading. Then again, my original naming choice for the command definitions in spi.h has the same problem. Thoughts? > int probe_spi_rdid4(struct flashchip *flash); > int probe_spi_rems(struct flashchip *flash); > int probe_spi_res1(struct flashchip *flash); > @@ -37,6 +38,7 @@ int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int > int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen); > int spi_block_erase_d7(struct flashchip *flash, unsigned int addr, unsigned int blocklen); > int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen); > +int spi_block_erase_62(struct flashchip *flash, unsigned int addr, unsigned int blocklen); > int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int blocklen); > int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen); > int spi_chip_write_1(struct flashchip *flash, uint8_t *buf, int start, int len); > @@ -45,12 +47,14 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); > uint8_t spi_read_status_register(void); > int spi_prettyprint_status_register_at25df(struct flashchip *flash); > int spi_prettyprint_status_register_at25df_sec(struct flashchip *flash); > +int spi_prettyprint_status_register_at25f(struct flashchip *flash); > AFAICS that hunk depends on an earlier patch of yours. > int spi_prettyprint_status_register_at25f512b(struct flashchip *flash); > int spi_prettyprint_status_register_at25fs010(struct flashchip *flash); > int spi_prettyprint_status_register_at25fs040(struct flashchip *flash); > int spi_disable_blockprotect(struct flashchip *flash); > int spi_disable_blockprotect_at25df(struct flashchip *flash); > int spi_disable_blockprotect_at25df_sec(struct flashchip *flash); > +int spi_disable_blockprotect_at25f(struct flashchip *flash); > int spi_disable_blockprotect_at25fs010(struct flashchip *flash); > int spi_disable_blockprotect_at25fs040(struct flashchip *flash); > int spi_byte_program(int addr, uint8_t databyte); > diff --git a/flashchips.c b/flashchips.c > index 29a4da0..7cb7d39 100644 > --- a/flashchips.c > +++ b/flashchips.c > @@ -1583,6 +1583,63 @@ struct flashchip flashchips[] = { > > { > .vendor = "Atmel", > + .name = "AT25F512", > + .bustype = CHIP_BUSTYPE_SPI, > + .manufacture_id = ATMEL_ID, > + .model_id = ATMEL_AT25F512, > + .total_size = 64, > + .page_size = 256, > This may be correct, but it looks odd... does AT25F512 really have a bigger page_size for writes than AT25F512A? > + .feature_bits = FEATURE_WRSR_WREN, > + .tested = TEST_UNTESTED, > + .probe = probe_spi_rdid_at25f, > + .probe_timing = TIMING_ZERO, > + .block_erasers = > + { > + { > + .eraseblocks = { {32 * 1024, 2} }, > + .block_erase = spi_block_erase_52, > + }, { > + .eraseblocks = { {64 * 1024, 1} }, > + .block_erase = spi_block_erase_62, > + } > + }, > + .printlock = spi_prettyprint_status_register_at25f, > + .unlock = spi_disable_blockprotect_at25f, > + .write = spi_chip_write_256, > + .read = spi_chip_read, > + }, > + > + { > + .vendor = "Atmel", > + .name = "AT25F512A", > + .bustype = CHIP_BUSTYPE_SPI, > + .manufacture_id = ATMEL_ID, > + .model_id = ATMEL_AT25F512A, > + .total_size = 64, > + .page_size = 128, > + .feature_bits = FEATURE_WRSR_WREN, > + .tested = TEST_UNTESTED, > + .probe = probe_spi_rdid_at25f, > + .probe_timing = TIMING_ZERO, > + .block_erasers = > + { > + { > + .eraseblocks = { {32 * 1024, 2} }, > + .block_erase = spi_block_erase_52, > + }, { > + .eraseblocks = { {64 * 1024, 1} }, > + .block_erase = spi_block_erase_62, > + } > + }, > + .printlock = spi_prettyprint_status_register_at25f, > + /* Not correct to use this one, because the BP1 bit is N/A. */ > + .unlock = spi_disable_blockprotect_at25f, > + .write = spi_chip_write_256, > + .read = spi_chip_read, > + }, > + > + { > + .vendor = "Atmel", > .name = "AT25F512B", > .bustype = CHIP_BUSTYPE_SPI, > .manufacture_id = ATMEL_ID, > @@ -1622,6 +1679,36 @@ struct flashchip flashchips[] = { > > { > .vendor = "Atmel", > + /* The A suffix indicates 33MHz instead of 20MHz clock rate. > + * All other properties seem to be the same.*/ > + .name = "AT25F1024(A)", > + .bustype = CHIP_BUSTYPE_SPI, > + .manufacture_id = ATMEL_ID, > + .model_id = ATMEL_AT25F1024, > + .total_size = 128, > + .page_size = 256, > + .feature_bits = FEATURE_WRSR_WREN, > + .tested = TEST_OK_PREW, > + .probe = probe_spi_rdid_at25f, > + .probe_timing = TIMING_ZERO, > + .block_erasers = > + { > + { > + .eraseblocks = { {32 * 1024, 4} }, > + .block_erase = spi_block_erase_52, > + }, { > + .eraseblocks = { {128 * 1024, 1} }, > + .block_erase = spi_block_erase_62, > + } > + }, > + .printlock = spi_prettyprint_status_register_at25f, > + .unlock = spi_disable_blockprotect_at25f, > + .write = spi_chip_write_256, > + .read = spi_chip_read, > + }, > + > + { > + .vendor = "Atmel", > .name = "AT25FS010", > .bustype = CHIP_BUSTYPE_SPI, > .manufacture_id = ATMEL_ID, > diff --git a/flashchips.h b/flashchips.h > index 3b2b94f..9b08d25 100644 > --- a/flashchips.h > +++ b/flashchips.h > @@ -134,13 +134,11 @@ > #define ATMEL_AT25DF321A 0x4701 > #define ATMEL_AT25DF641 0x4800 > #define ATMEL_AT25DQ161 0x8600 > -#define ATMEL_AT25F512 /* No device ID found in datasheet. Vendor ID > - * can be read with AT25F512A_RDID */ > -#define ATMEL_AT25F512A 0x65 /* Needs AT25F512A_RDID */ > +#define ATMEL_AT25F512 0x65 /* guessed, no device ID in datasheet. > + * Vendor ID can be read with AT25F_RDID */ > +#define ATMEL_AT25F512A 0x65 /* Needs AT25F_RDID */ > #define ATMEL_AT25F512B 0x6500 > -#define ATMEL_AT25F1024 /* No device ID found in datasheet. Vendor ID > - * can be read with AT25F512A_RDID */ > -#define ATMEL_AT25F1024A 0x60 /* Needs AT25F512A_RDID */ > +#define ATMEL_AT25F1024 0x60 /* Needs AT25F_RDID */ > That's a bit odd. You merge AT25F1024 and AT25F1024A into one definition, but you keep AT25F512 and AT25F512A separate. > #define ATMEL_AT25FS010 0x6601 > #define ATMEL_AT25FS040 0x6604 > #define ATMEL_AT26DF041 0x4400 > diff --git a/spi.h b/spi.h > index b908603..a5c3406 100644 > --- a/spi.h > +++ b/spi.h > @@ -30,10 +30,11 @@ > /* INSIZE may be 0x04 for some chips*/ > #define JEDEC_RDID_INSIZE 0x03 > > -/* AT25F512A has bit 3 as don't care bit in commands */ > -#define AT25F512A_RDID 0x15 /* 0x15 or 0x1d */ > -#define AT25F512A_RDID_OUTSIZE 0x01 > -#define AT25F512A_RDID_INSIZE 0x02 > +/* Some Atmel AT25F* models have bit 3 as don't care bit in commands */ > +/* 0x15 or 0x1d */ > +#define AT25F_RDID 0x15 > +#define AT25F_RDID_OUTSIZE 0x01 > +#define AT25F_RDID_INSIZE 0x02 > See the naming discussion near the beginning of my mail. > > /* Read Electronic Manufacturer Signature */ > #define JEDEC_REMS 0x90 > @@ -61,6 +62,11 @@ > #define JEDEC_CE_60_OUTSIZE 0x01 > #define JEDEC_CE_60_INSIZE 0x00 > > +/* Chip Erase 0x62 is supported by Atmel AT25F chips. */ > +#define JEDEC_CE_62 0x62 > +#define JEDEC_CE_62_OUTSIZE 0x01 > +#define JEDEC_CE_62_INSIZE 0x00 > + > /* Chip Erase 0xc7 is supported by SST/ST/EON/Macronix chips. */ > #define JEDEC_CE_C7 0xc7 > #define JEDEC_CE_C7_OUTSIZE 0x01 > diff --git a/spi25.c b/spi25.c > index c4cd6b2..38037f1 100644 > --- a/spi25.c > +++ b/spi25.c > @@ -141,7 +141,11 @@ static int probe_spi_rdid_generic(struct flashchip *flash, int bytes_in, unsigne > } > } else { > id1 = readarr[0]; > - id2 = (readarr[1]<< 8) | readarr[2]; > + /* Special case for AT25F chips. */ > + if (bytes_in == 2) > + id2 = readarr[1]; > + else > + id2 = (readarr[1]<< 8) | readarr[2]; > Could you make AT25F probing a totally separate function which does not reuse probe_spi_rdid_generic? And move it to at25.c white you're at it? > } > > msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2); > @@ -173,6 +177,11 @@ int probe_spi_rdid(struct flashchip *flash) > return probe_spi_rdid_generic(flash, JEDEC_RDID_INSIZE, JEDEC_RDID); > } > > +int probe_spi_rdid_at25f(struct flashchip *flash) > +{ > + return probe_spi_rdid_generic(flash, AT25F_RDID_INSIZE, AT25F_RDID); > See above. > +} > + > int probe_spi_rdid4(struct flashchip *flash) > { > /* Some SPI controllers do not support commands with writecnt=1 and > @@ -394,6 +403,32 @@ int spi_prettyprint_status_register_at25df_sec(struct flashchip *flash) > return spi_prettyprint_status_register_at25df(flash); > } > > +int spi_prettyprint_status_register_at25f(struct flashchip *flash) > +{ > + uint8_t status; > + > + status = spi_read_status_register(); > + msg_cdbg("Chip status register is %02x\n", status); > + > + msg_cdbg("Chip status register: Status Register Write Protect (WPEN) " > + "is %sset\n", (status& (1<< 7)) ? "" : "not "); > + /* The following 3 bits are undefined in AT25F512(A), AT25F1024(A): > + msg_cdbg("Chip status register: Bit 6 is " > + "%sset\n", (status& (1<< 6)) ? "" : "not "); > + msg_cdbg("Chip status register: Bit 5 is " > + "%sset\n", (status& (1<< 5)) ? "" : "not "); > + msg_cdbg("Chip status register: Bit 4 is " > + "%sset\n", (status& (1<< 4)) ? "" : "not "); > + */ > + /* This is undefined for AT25F512A; will be refactored soonish anyway */ > + msg_cdbg("Chip status register: Block Protect 1 (BP1) is %sset\n", > + (status& (1<< 3)) ? "" : "not "); > + msg_cdbg("Chip status register: Block Protect 0 (BP0) is %sset\n", > + (status& (1<< 2)) ? "" : "not "); > + spi_prettyprint_status_register_welwip(status); > + return 0; > +} > Status printing should already be handled just fine with the current code, could you please cross-check that? > + > int spi_prettyprint_status_register_at25f512b(struct flashchip *flash) > { > uint8_t status; > @@ -592,6 +627,46 @@ int spi_chip_erase_60(struct flashchip *flash) > return 0; > } > > +int spi_chip_erase_62(struct flashchip *flash) > +{ > + int result; > + struct spi_command cmds[] = { > + { > + .writecnt = JEDEC_WREN_OUTSIZE, > + .writearr = (const unsigned char[]){ JEDEC_WREN }, > + .readcnt = 0, > + .readarr = NULL, > + }, { > + .writecnt = JEDEC_CE_62_OUTSIZE, > + .writearr = (const unsigned char[]){ JEDEC_CE_62 }, > + .readcnt = 0, > + .readarr = NULL, > + }, { > + .writecnt = 0, > + .writearr = NULL, > + .readcnt = 0, > + .readarr = NULL, > + }}; > + > + result = spi_send_multicommand(cmds); > + if (result) { > + msg_cerr("%s failed during command execution\n", > + __func__); > + return result; > + } > + /* Wait until the Write-In-Progress bit is cleared. > + * This usually takes 2-5 s, so wait in 100 ms steps. > + */ > + /* FIXME: We assume spi_read_status_register will never fail. */ > + while (spi_read_status_register()& JEDEC_RDSR_BIT_WIP) > + programmer_delay(100 * 1000); > + if (check_erased_range(flash, 0, flash->total_size * 1024)) { > + msg_cerr("ERASE FAILED!\n"); > + return -1; > + } > + return 0; > +} > + > int spi_chip_erase_c7(struct flashchip *flash) > { > int result; > @@ -826,6 +901,16 @@ int spi_block_erase_60(struct flashchip *flash, unsigned int addr, unsigned int > return spi_chip_erase_60(flash); > } > > +int spi_block_erase_62(struct flashchip *flash, unsigned int addr, unsigned int blocklen) > +{ > + if ((addr != 0) || (blocklen != flash->total_size * 1024)) { > + msg_cerr("%s called with incorrect arguments\n", > + __func__); > + return -1; > + } > + return spi_chip_erase_62(flash); > +} > Should *_erase_62 be moved to at25.c or is it generic enogh to live in spi25.c? > + > int spi_block_erase_c7(struct flashchip *flash, unsigned int addr, unsigned int blocklen) > { > if ((addr != 0) || (blocklen != flash->total_size * 1024)) { > @@ -1076,6 +1161,57 @@ int spi_disable_blockprotect(struct flashchip *flash) > return 0; > } > > +int spi_disable_blockprotect_at25f(struct flashchip *flash) > +{ > + uint8_t status; > + int result; > + > + status = spi_read_status_register(); > + /* If block protection is disabled (BP0 and BP1 are 0), stop here. */ > + if ((status& (3<< 2)) == 0) > + return 0; > + > + msg_cdbg("Some block protection in effect, disabling\n"); > + if (status& (1<< 7)) { > + msg_cdbg("Need to disable Write Protect Enable (WPEN)\n"); > + /* The following is used in spi_disable_blockprotect_at25df > + * to check the state of the hardware lock pin. This is not > + * possible with this chip, so we have to try. > + if ((status& (1<< 4)) == 0) { > + msg_cerr("WP# pin is active, disabling " > + "write protection is impossible.\n"); > + return 1; > + } > + */ > + /* All bits except bit 7 (WPEN) are readonly. If the WP pin is > + * low, WPEN is readonly and this will fail. */ > + result = spi_write_status_register(flash, status& ~(1<< 7)); > + if (result) { > + msg_cerr("spi_write_status_register failed\n"); > + return result; > + } > + status = spi_read_status_register(); > + if (status& (1<< 7)) { > + msg_cerr("WP# pin is probably active, disabling " > + "write protection is impossible.\n"); > + return 1; > + } > + > + } > + /* Global unprotect. Make sure to mask WPEN as well. */ > + result = spi_write_status_register(flash, status& ~0x8c); > + if (result) { > + msg_cerr("spi_write_status_register failed\n"); > + return result; > + } > + status = spi_read_status_register(); > + if ((status& (3<< 2)) != 0) { > + msg_cerr("Block protection could not be disabled!\n"); > + return 1; > + } > + return 0; > +} > The function above should be in at25.c. > + > int spi_disable_blockprotect_at25df(struct flashchip *flash) > { > uint8_t status; > Feel free to only respond to my comments without posting a new patch if you think some of my comments are not applicable. Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

Re: [flashrom] [PATCH 4/5] add macros and pretty printing for HSFS and HSFC
by Stefan Tauner 19 May '11

19 May '11

HSFS (0x04) and HSFC (0x06) should be placed before FADDR (0x08) and FDATA0 (0x10). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

[PATCH] Lock printing for AMIC A25* and Atmel AT25*
by Carl-Daniel Hailfinger 19 May '11

19 May '11

Add lock printing for AMIC A25L05PT, A25L05PU, A25L10PT, A25L10PU, A25L20PT, A25L20PU, A25L40PT, A25L40PU, A25L80P, A25L16PT, A25L16PU, A25L512, A25L010, A25L020, A25L040, A25L080, A25L016, A25L032, A25LQ032. Add lock printing for Atmel AT26DF081A, AT26DF161, AT26DF161A, AT26DF321. Move Atmel AT25*/AT26* lock related functions from spi25.c to at25.c. That code was originally committed in r1115, but chip specific functions shouldn't live in the generic spi25.c. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_prettyprint_statusreg_a25_at25/a25.c =================================================================== --- flashrom-spi_prettyprint_statusreg_a25_at25/a25.c (Revision 0) +++ flashrom-spi_prettyprint_statusreg_a25_at25/a25.c (Revision 0) @@ -0,0 +1,103 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2010 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "flash.h" +#include "chipdrivers.h" +#include "spi.h" + +/* Prettyprint the status register. Works for AMIC A25L series. */ + +int spi_prettyprint_status_register_amic_a25l05p(struct flashchip *flash) +{ + uint8_t status; + + status = spi_read_status_register(); + msg_cdbg("Chip status register is %02x\n", status); + + msg_cdbg("Chip status register: Status Register Write Disable " + "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); + spi_prettyprint_status_register_bit(status, 6); + spi_prettyprint_status_register_bit(status, 5); + spi_prettyprint_status_register_bit(status, 4); + spi_prettyprint_status_register_bp3210(status, 1); + spi_prettyprint_status_register_welwip(status); + return 0; +} + +int spi_prettyprint_status_register_amic_a25l40p(struct flashchip *flash) +{ + uint8_t status; + + status = spi_read_status_register(); + msg_cdbg("Chip status register is %02x\n", status); + + msg_cdbg("Chip status register: Status Register Write Disable " + "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); + spi_prettyprint_status_register_bit(status, 6); + spi_prettyprint_status_register_bit(status, 5); + spi_prettyprint_status_register_bp3210(status, 2); + spi_prettyprint_status_register_welwip(status); + return 0; +} + +int spi_prettyprint_status_register_amic_a25l032(struct flashchip *flash) +{ + uint8_t status; + + status = spi_read_status_register(); + msg_cdbg("Chip status register is %02x\n", status); + + msg_cdbg("Chip status register: Status Register Write Disable " + "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); + msg_cdbg("Chip status register: Sector Protect Size (SEC) " + "is %i KB\n", (status & (1 << 6)) ? 4 : 64); + msg_cdbg("Chip status register: Top/Bottom (TB) " + "is %s\n", (status & (1 << 5)) ? "bottom" : "top"); + spi_prettyprint_status_register_bp3210(status, 2); + spi_prettyprint_status_register_welwip(status); + msg_cdbg("Chip status register 2 is NOT decoded!\n"); + return 0; +} + +int spi_prettyprint_status_register_amic_a25lq032(struct flashchip *flash) +{ + uint8_t status; + + status = spi_read_status_register(); + msg_cdbg("Chip status register is %02x\n", status); + + msg_cdbg("Chip status register: Status Register Write Disable " + "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); + msg_cdbg("Chip status register: Sector Protect Size (SEC) " + "is %i KB\n", (status & (1 << 6)) ? 4 : 64); + msg_cdbg("Chip status register: Top/Bottom (TB) " + "is %s\n", (status & (1 << 5)) ? "bottom" : "top"); + spi_prettyprint_status_register_bp3210(status, 2); + spi_prettyprint_status_register_welwip(status); + msg_cdbg("Chip status register 2 is NOT decoded!\n"); + return 0; +} + +/* FIXME: spi_disable_blockprotect is incorrect but works fine for chips using + * spi_prettyprint_status_register_amic_a25l05p or + * spi_prettyprint_status_register_amic_a25l40p. + * FIXME: spi_disable_blockprotect is incorrect and will fail randomly for chips + * using spi_prettyprint_status_register_amic_a25l032 or + * spi_prettyprint_status_register_amic_a25lq032. + */ Index: flashrom-spi_prettyprint_statusreg_a25_at25/Makefile =================================================================== --- flashrom-spi_prettyprint_statusreg_a25_at25/Makefile (Revision 1245) +++ flashrom-spi_prettyprint_statusreg_a25_at25/Makefile (Arbeitskopie) @@ -84,7 +84,8 @@ CHIP_OBJS = jedec.o stm50flw0x0x.o w39.o w29ee011.o \ sst28sf040.o m29f400bt.o 82802ab.o pm49fl00x.o \ - sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o sharplhf00l04.o + sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o sharplhf00l04.o \ + a25.o at25.o LIB_OBJS = layout.o Index: flashrom-spi_prettyprint_statusreg_a25_at25/at25.c =================================================================== --- flashrom-spi_prettyprint_statusreg_a25_at25/at25.c (Revision 0) +++ flashrom-spi_prettyprint_statusreg_a25_at25/at25.c (Revision 0) @@ -0,0 +1,287 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2010 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "flash.h" +#include "chipdrivers.h" +#include "spi.h" + +/* Prettyprint the status register. Works for Atmel A25/A26 series. */ + +static void spi_prettyprint_status_register_atmel_at25_srpl(uint8_t status) +{ + msg_cdbg("Chip status register: Sector Protection Register Lock (SRPL) " + "is %sset\n", (status & (1 << 7)) ? "" : "not "); +} + +static void spi_prettyprint_status_register_atmel_at25_epewpp(uint8_t status) +{ + msg_cdbg("Chip status register: Erase/Program Error (EPE) " + "is %sset\n", (status & (1 << 5)) ? "" : "not "); + msg_cdbg("Chip status register: WP# pin (WPP) " + "is %sasserted\n", (status & (1 << 4)) ? "not " : ""); +} + +static void spi_prettyprint_status_register_atmel_at25_swp(uint8_t status) +{ + msg_cdbg("Chip status register: Software Protection Status (SWP): "); + switch (status & (3 << 2)) { + case 0x0 << 2: + msg_cdbg("no sectors are protected\n"); + break; + case 0x1 << 2: + msg_cdbg("some sectors are protected\n"); + /* FIXME: Read individual Sector Protection Registers. */ + break; + case 0x3 << 2: + msg_cdbg("all sectors are protected\n"); + break; + default: + msg_cdbg("reserved for future use\n"); + break; + } +} + +int spi_prettyprint_status_register_at25df(struct flashchip *flash) +{ + uint8_t status; + + status = spi_read_status_register(); + msg_cdbg("Chip status register is %02x\n", status); + + spi_prettyprint_status_register_atmel_at25_srpl(status); + spi_prettyprint_status_register_bit(status, 6); + spi_prettyprint_status_register_atmel_at25_epewpp(status); + spi_prettyprint_status_register_atmel_at25_swp(status); + spi_prettyprint_status_register_welwip(status); + return 0; +} + +int spi_prettyprint_status_register_at25df_sec(struct flashchip *flash) +{ + /* FIXME: We should check the security lockdown. */ + msg_cdbg("Ignoring security lockdown (if present)\n"); + msg_cdbg("Ignoring status register byte 2\n"); + return spi_prettyprint_status_register_at25df(flash); +} + +int spi_prettyprint_status_register_at25f(struct flashchip *flash) +{ + uint8_t status; + + status = spi_read_status_register(); + msg_cdbg("Chip status register is %02x\n", status); + + spi_prettyprint_status_register_atmel_at25_srpl(status); + spi_prettyprint_status_register_bit(status, 6); + spi_prettyprint_status_register_atmel_at25_epewpp(status); + spi_prettyprint_status_register_bit(status, 3); + msg_cdbg("Chip status register: Block Protect 0 (BP0) is " + "%sset, %s sectors are protected\n", + (status & (1 << 2)) ? "" : "not ", + (status & (1 << 2)) ? "all" : "no"); + spi_prettyprint_status_register_welwip(status); + return 0; +} + +int spi_prettyprint_status_register_at25fs010(struct flashchip *flash) +{ + uint8_t status; + + status = spi_read_status_register(); + msg_cdbg("Chip status register is %02x\n", status); + + msg_cdbg("Chip status register: Status Register Write Protect (WPEN) " + "is %sset\n", (status & (1 << 7)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 6 / Block Protect 4 (BP4) is " + "%sset\n", (status & (1 << 6)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) is " + "%sset\n", (status & (1 << 5)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 4 is " + "%sset\n", (status & (1 << 4)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) is " + "%sset\n", (status & (1 << 3)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) is " + "%sset\n", (status & (1 << 2)) ? "" : "not "); + /* FIXME: Pretty-print detailed sector protection status. */ + spi_prettyprint_status_register_welwip(status); + return 0; +} + +int spi_prettyprint_status_register_at25fs040(struct flashchip *flash) +{ + uint8_t status; + + status = spi_read_status_register(); + msg_cdbg("Chip status register is %02x\n", status); + + msg_cdbg("Chip status register: Status Register Write Protect (WPEN) " + "is %sset\n", (status & (1 << 7)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 6 / Block Protect 4 (BP4) is " + "%sset\n", (status & (1 << 6)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) is " + "%sset\n", (status & (1 << 5)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 4 / Block Protect 2 (BP2) is " + "%sset\n", (status & (1 << 4)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) is " + "%sset\n", (status & (1 << 3)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) is " + "%sset\n", (status & (1 << 2)) ? "" : "not "); + /* FIXME: Pretty-print detailed sector protection status. */ + spi_prettyprint_status_register_welwip(status); + return 0; +} + +int spi_prettyprint_status_register_atmel_at26df081a(struct flashchip *flash) +{ + uint8_t status; + + status = spi_read_status_register(); + msg_cdbg("Chip status register is %02x\n", status); + + spi_prettyprint_status_register_atmel_at25_srpl(status); + msg_cdbg("Chip status register: Sequential Program Mode Status (SPM) " + "is %sset\n", (status & (1 << 6)) ? "" : "not "); + spi_prettyprint_status_register_atmel_at25_epewpp(status); + spi_prettyprint_status_register_atmel_at25_swp(status); + spi_prettyprint_status_register_welwip(status); + return 0; +} + +int spi_disable_blockprotect_at25df(struct flashchip *flash) +{ + uint8_t status; + int result; + + status = spi_read_status_register(); + /* If block protection is disabled, stop here. */ + if ((status & (3 << 2)) == 0) + return 0; + + msg_cdbg("Some block protection in effect, disabling\n"); + if (status & (1 << 7)) { + msg_cdbg("Need to disable Sector Protection Register Lock\n"); + if ((status & (1 << 4)) == 0) { + msg_cerr("WP# pin is active, disabling " + "write protection is impossible.\n"); + return 1; + } + /* All bits except bit 7 (SPRL) are readonly. */ + result = spi_write_status_register(flash, status & ~(1 << 7)); + if (result) { + msg_cerr("spi_write_status_register failed\n"); + return result; + } + + } + /* Global unprotect. Make sure to mask SPRL as well. */ + result = spi_write_status_register(flash, status & ~0xbc); + if (result) { + msg_cerr("spi_write_status_register failed\n"); + return result; + } + status = spi_read_status_register(); + if ((status & (3 << 2)) != 0) { + msg_cerr("Block protection could not be disabled!\n"); + return 1; + } + return 0; +} + +int spi_disable_blockprotect_at25df_sec(struct flashchip *flash) +{ + /* FIXME: We should check the security lockdown. */ + msg_cinfo("Ignoring security lockdown (if present)\n"); + return spi_disable_blockprotect_at25df(flash); +} + +int spi_disable_blockprotect_at25f(struct flashchip *flash) +{ + /* spi_disable_blockprotect_at25df is not really the right way to do + * this, but the side effects of said function work here as well. + */ + return spi_disable_blockprotect_at25df(flash); +} + +int spi_disable_blockprotect_at25fs010(struct flashchip *flash) +{ + uint8_t status; + int result; + + status = spi_read_status_register(); + /* If block protection is disabled, stop here. */ + if ((status & 0x6c) == 0) + return 0; + + msg_cdbg("Some block protection in effect, disabling\n"); + if (status & (1 << 7)) { + msg_cdbg("Need to disable Status Register Write Protect\n"); + /* Clear bit 7 (WPEN). */ + result = spi_write_status_register(flash, status & ~(1 << 7)); + if (result) { + msg_cerr("spi_write_status_register failed\n"); + return result; + } + } + /* Global unprotect. Make sure to mask WPEN as well. */ + result = spi_write_status_register(flash, status & ~0xec); + if (result) { + msg_cerr("spi_write_status_register failed\n"); + return result; + } + status = spi_read_status_register(); + if ((status & 0x6c) != 0) { + msg_cerr("Block protection could not be disabled!\n"); + return 1; + } + return 0; +} + +int spi_disable_blockprotect_at25fs040(struct flashchip *flash) +{ + uint8_t status; + int result; + + status = spi_read_status_register(); + /* If block protection is disabled, stop here. */ + if ((status & 0x7c) == 0) + return 0; + + msg_cdbg("Some block protection in effect, disabling\n"); + if (status & (1 << 7)) { + msg_cdbg("Need to disable Status Register Write Protect\n"); + /* Clear bit 7 (WPEN). */ + result = spi_write_status_register(flash, status & ~(1 << 7)); + if (result) { + msg_cerr("spi_write_status_register failed\n"); + return result; + } + } + /* Global unprotect. Make sure to mask WPEN as well. */ + result = spi_write_status_register(flash, status & ~0xfc); + if (result) { + msg_cerr("spi_write_status_register failed\n"); + return result; + } + status = spi_read_status_register(); + if ((status & 0x7c) != 0) { + msg_cerr("Block protection could not be disabled!\n"); + return 1; + } + return 0; +} Index: flashrom-spi_prettyprint_statusreg_a25_at25/spi25.c =================================================================== --- flashrom-spi_prettyprint_statusreg_a25_at25/spi25.c (Revision 1245) +++ flashrom-spi_prettyprint_statusreg_a25_at25/spi25.c (Arbeitskopie) @@ -29,8 +29,6 @@ #include "programmer.h" #include "spi.h" -void spi_prettyprint_status_register(struct flashchip *flash); - static int spi_rdid(unsigned char *readarr, int bytes) { const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID }; @@ -312,7 +310,7 @@ } /* Prettyprint the status register. Common definitions. */ -static void spi_prettyprint_status_register_welwip(uint8_t status) +void spi_prettyprint_status_register_welwip(uint8_t status) { msg_cdbg("Chip status register: Write Enable Latch (WEL) is " "%sset\n", (status & (1 << 1)) ? "" : "not "); @@ -321,144 +319,38 @@ } /* Prettyprint the status register. Common definitions. */ -static void spi_prettyprint_status_register_common(uint8_t status) +void spi_prettyprint_status_register_bp3210(uint8_t status, int bp) { - msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) is " - "%sset\n", (status & (1 << 5)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 4 / Block Protect 2 (BP2) is " - "%sset\n", (status & (1 << 4)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) is " - "%sset\n", (status & (1 << 3)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) is " - "%sset\n", (status & (1 << 2)) ? "" : "not "); - spi_prettyprint_status_register_welwip(status); -} - -/* Prettyprint the status register. Works for - * AMIC A25L series - */ -void spi_prettyprint_status_register_amic_a25l(uint8_t status) -{ - msg_cdbg("Chip status register: Status Register Write Disable " - "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); - spi_prettyprint_status_register_common(status); -} - -/* Prettyprint the status register. Common definitions. */ -static void spi_prettyprint_status_register_at25_srplepewpp(uint8_t status) -{ - msg_cdbg("Chip status register: Sector Protection Register Lock (SRPL) " - "is %sset\n", (status & (1 << 7)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 6 " - "is %sset\n", (status & (1 << 6)) ? "" : "not "); - msg_cdbg("Chip status register: Erase/Program Error (EPE) " - "is %sset\n", (status & (1 << 5)) ? "" : "not "); - msg_cdbg("Chip status register: WP# pin (WPP) " - "is %sactive\n", (status & (1 << 4)) ? "not " : ""); -} - -int spi_prettyprint_status_register_at25df(struct flashchip *flash) -{ - uint8_t status; - - status = spi_read_status_register(); - msg_cdbg("Chip status register is %02x\n", status); - - spi_prettyprint_status_register_at25_srplepewpp(status); - msg_cdbg("Chip status register: Software Protection Status (SWP): "); - switch (status & (3 << 2)) { - case 0x0 << 2: - msg_cdbg("no sectors are protected\n"); - break; - case 0x1 << 2: - msg_cdbg("some sectors are protected\n"); - /* FIXME: Read individual Sector Protection Registers. */ - break; - case 0x3 << 2: - msg_cdbg("all sectors are protected\n"); - break; - default: - msg_cdbg("reserved for future use\n"); - break; + switch (bp) { + /* Fall through. */ + case 3: + msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) " + "is %sset\n", (status & (1 << 5)) ? "" : "not "); + case 2: + msg_cdbg("Chip status register: Bit 4 / Block Protect 2 (BP2) " + "is %sset\n", (status & (1 << 4)) ? "" : "not "); + case 1: + msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) " + "is %sset\n", (status & (1 << 3)) ? "" : "not "); + case 0: + msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) " + "is %sset\n", (status & (1 << 2)) ? "" : "not "); } - spi_prettyprint_status_register_welwip(status); - return 0; } -int spi_prettyprint_status_register_at25df_sec(struct flashchip *flash) +/* Prettyprint the status register. Unnamed bits. */ +void spi_prettyprint_status_register_bit(uint8_t status, int bit) { - /* FIXME: We should check the security lockdown. */ - msg_cdbg("Ignoring security lockdown (if present)\n"); - msg_cdbg("Ignoring status register byte 2\n"); - return spi_prettyprint_status_register_at25df(flash); + msg_cdbg("Chip status register: Bit %i " + "is %sset\n", bit, (status & (1 << bit)) ? "" : "not "); } -int spi_prettyprint_status_register_at25f(struct flashchip *flash) +static void spi_prettyprint_status_register_common(uint8_t status) { - uint8_t status; - - status = spi_read_status_register(); - msg_cdbg("Chip status register is %02x\n", status); - - spi_prettyprint_status_register_at25_srplepewpp(status); - msg_cdbg("Chip status register: Bit 3 " - "is %sset\n", (status & (1 << 3)) ? "" : "not "); - msg_cdbg("Chip status register: Block Protect 0 (BP0) is " - "%sset, %s sectors are protected\n", - (status & (1 << 2)) ? "" : "not ", - (status & (1 << 2)) ? "all" : "no"); + spi_prettyprint_status_register_bp3210(status, 3); spi_prettyprint_status_register_welwip(status); - return 0; } -int spi_prettyprint_status_register_at25fs010(struct flashchip *flash) -{ - uint8_t status; - - status = spi_read_status_register(); - msg_cdbg("Chip status register is %02x\n", status); - - msg_cdbg("Chip status register: Status Register Write Protect (WPEN) " - "is %sset\n", (status & (1 << 7)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 6 / Block Protect 4 (BP4) is " - "%sset\n", (status & (1 << 6)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) is " - "%sset\n", (status & (1 << 5)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 4 is " - "%sset\n", (status & (1 << 4)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) is " - "%sset\n", (status & (1 << 3)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) is " - "%sset\n", (status & (1 << 2)) ? "" : "not "); - /* FIXME: Pretty-print detailed sector protection status. */ - spi_prettyprint_status_register_welwip(status); - return 0; -} - -int spi_prettyprint_status_register_at25fs040(struct flashchip *flash) -{ - uint8_t status; - - status = spi_read_status_register(); - msg_cdbg("Chip status register is %02x\n", status); - - msg_cdbg("Chip status register: Status Register Write Protect (WPEN) " - "is %sset\n", (status & (1 << 7)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 6 / Block Protect 4 (BP4) is " - "%sset\n", (status & (1 << 6)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) is " - "%sset\n", (status & (1 << 5)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 4 / Block Protect 2 (BP2) is " - "%sset\n", (status & (1 << 4)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) is " - "%sset\n", (status & (1 << 3)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) is " - "%sset\n", (status & (1 << 2)) ? "" : "not "); - /* FIXME: Pretty-print detailed sector protection status. */ - spi_prettyprint_status_register_welwip(status); - return 0; -} - /* Prettyprint the status register. Works for * ST M25P series * MX MX25L series @@ -514,17 +406,13 @@ bpt[(status & 0x1c) >> 2]); } -void spi_prettyprint_status_register(struct flashchip *flash) +int spi_prettyprint_status_register(struct flashchip *flash) { uint8_t status; status = spi_read_status_register(); msg_cdbg("Chip status register is %02x\n", status); switch (flash->manufacture_id) { - case AMIC_ID: - if ((flash->model_id & 0xff00) == 0x2000) - spi_prettyprint_status_register_amic_a25l(status); - break; case ST_ID: if (((flash->model_id & 0xff00) == 0x2000) || ((flash->model_id & 0xff00) == 0x2500)) @@ -549,6 +437,7 @@ } break; } + return 0; } int spi_chip_erase_60(struct flashchip *flash) @@ -949,7 +838,7 @@ return 0; } -static int spi_write_status_register(struct flashchip *flash, int status) +int spi_write_status_register(struct flashchip *flash, int status) { int ret = 1; @@ -1075,128 +964,6 @@ return 0; } -int spi_disable_blockprotect_at25df(struct flashchip *flash) -{ - uint8_t status; - int result; - - status = spi_read_status_register(); - /* If block protection is disabled, stop here. */ - if ((status & (3 << 2)) == 0) - return 0; - - msg_cdbg("Some block protection in effect, disabling\n"); - if (status & (1 << 7)) { - msg_cdbg("Need to disable Sector Protection Register Lock\n"); - if ((status & (1 << 4)) == 0) { - msg_cerr("WP# pin is active, disabling " - "write protection is impossible.\n"); - return 1; - } - /* All bits except bit 7 (SPRL) are readonly. */ - result = spi_write_status_register(flash, status & ~(1 << 7)); - if (result) { - msg_cerr("spi_write_status_register failed\n"); - return result; - } - - } - /* Global unprotect. Make sure to mask SPRL as well. */ - result = spi_write_status_register(flash, status & ~0xbc); - if (result) { - msg_cerr("spi_write_status_register failed\n"); - return result; - } - status = spi_read_status_register(); - if ((status & (3 << 2)) != 0) { - msg_cerr("Block protection could not be disabled!\n"); - return 1; - } - return 0; -} - -int spi_disable_blockprotect_at25df_sec(struct flashchip *flash) -{ - /* FIXME: We should check the security lockdown. */ - msg_cinfo("Ignoring security lockdown (if present)\n"); - return spi_disable_blockprotect_at25df(flash); -} - -int spi_disable_blockprotect_at25f(struct flashchip *flash) -{ - /* spi_disable_blockprotect_at25df is not really the right way to do - * this, but the side effects of said function work here as well. - */ - return spi_disable_blockprotect_at25df(flash); -} - -int spi_disable_blockprotect_at25fs010(struct flashchip *flash) -{ - uint8_t status; - int result; - - status = spi_read_status_register(); - /* If block protection is disabled, stop here. */ - if ((status & 0x6c) == 0) - return 0; - - msg_cdbg("Some block protection in effect, disabling\n"); - if (status & (1 << 7)) { - msg_cdbg("Need to disable Status Register Write Protect\n"); - /* Clear bit 7 (WPEN). */ - result = spi_write_status_register(flash, status & ~(1 << 7)); - if (result) { - msg_cerr("spi_write_status_register failed\n"); - return result; - } - } - /* Global unprotect. Make sure to mask WPEN as well. */ - result = spi_write_status_register(flash, status & ~0xec); - if (result) { - msg_cerr("spi_write_status_register failed\n"); - return result; - } - status = spi_read_status_register(); - if ((status & 0x6c) != 0) { - msg_cerr("Block protection could not be disabled!\n"); - return 1; - } - return 0; -} -int spi_disable_blockprotect_at25fs040(struct flashchip *flash) -{ - uint8_t status; - int result; - - status = spi_read_status_register(); - /* If block protection is disabled, stop here. */ - if ((status & 0x7c) == 0) - return 0; - - msg_cdbg("Some block protection in effect, disabling\n"); - if (status & (1 << 7)) { - msg_cdbg("Need to disable Status Register Write Protect\n"); - /* Clear bit 7 (WPEN). */ - result = spi_write_status_register(flash, status & ~(1 << 7)); - if (result) { - msg_cerr("spi_write_status_register failed\n"); - return result; - } - } - /* Global unprotect. Make sure to mask WPEN as well. */ - result = spi_write_status_register(flash, status & ~0xfc); - if (result) { - msg_cerr("spi_write_status_register failed\n"); - return result; - } - status = spi_read_status_register(); - if ((status & 0x7c) != 0) { - msg_cerr("Block protection could not be disabled!\n"); - return 1; - } - return 0; -} - int spi_nbyte_read(int address, uint8_t *bytes, int len) { const unsigned char cmd[JEDEC_READ_OUTSIZE] = { Index: flashrom-spi_prettyprint_statusreg_a25_at25/flashchips.c =================================================================== --- flashrom-spi_prettyprint_statusreg_a25_at25/flashchips.c (Revision 1245) +++ flashrom-spi_prettyprint_statusreg_a25_at25/flashchips.c (Arbeitskopie) @@ -300,6 +300,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l05p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -331,6 +332,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l05p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -363,6 +365,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l05p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -395,6 +398,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l05p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -427,6 +431,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l05p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -459,6 +464,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l05p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -496,6 +502,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -528,6 +535,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -560,6 +568,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -595,6 +604,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -630,6 +640,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -660,6 +671,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -690,6 +702,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -720,6 +733,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -750,6 +764,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -780,6 +795,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -810,6 +826,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -846,6 +863,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l032, .unlock = NULL, /* Two status reg bytes (read with 0x35 and 0x05) */ .write = spi_chip_write_256, .read = spi_chip_read, @@ -882,6 +900,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25lq032, .unlock = NULL, /* Two status reg bytes (read with 0x35 and 0x05) */ .write = spi_chip_write_256, .read = spi_chip_read, @@ -1499,6 +1518,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_atmel_at26df081a, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1534,6 +1554,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_at25df, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1569,6 +1590,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_atmel_at26df081a, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1586,6 +1608,7 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, + .printlock = spi_prettyprint_status_register_atmel_at26df081a, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, Index: flashrom-spi_prettyprint_statusreg_a25_at25/chipdrivers.h =================================================================== --- flashrom-spi_prettyprint_statusreg_a25_at25/chipdrivers.h (Revision 1245) +++ flashrom-spi_prettyprint_statusreg_a25_at25/chipdrivers.h (Arbeitskopie) @@ -43,23 +43,37 @@ int spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); uint8_t spi_read_status_register(void); +int spi_write_status_register(struct flashchip *flash, int status); +void spi_prettyprint_status_register_bit(uint8_t status, int bit); +void spi_prettyprint_status_register_bp3210(uint8_t status, int bp); +void spi_prettyprint_status_register_welwip(uint8_t status); +int spi_prettyprint_status_register(struct flashchip *flash); +int spi_disable_blockprotect(struct flashchip *flash); +int spi_byte_program(int addr, uint8_t databyte); +int spi_nbyte_program(int addr, uint8_t *bytes, int len); +int spi_nbyte_read(int addr, uint8_t *bytes, int len); +int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); +int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); +int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len); + +/* a25.c */ +int spi_prettyprint_status_register_amic_a25l05p(struct flashchip *flash); +int spi_prettyprint_status_register_amic_a25l40p(struct flashchip *flash); +int spi_prettyprint_status_register_amic_a25l032(struct flashchip *flash); +int spi_prettyprint_status_register_amic_a25lq032(struct flashchip *flash); + +/* at25.c */ int spi_prettyprint_status_register_at25df(struct flashchip *flash); int spi_prettyprint_status_register_at25df_sec(struct flashchip *flash); int spi_prettyprint_status_register_at25f(struct flashchip *flash); int spi_prettyprint_status_register_at25fs010(struct flashchip *flash); int spi_prettyprint_status_register_at25fs040(struct flashchip *flash); -int spi_disable_blockprotect(struct flashchip *flash); +int spi_prettyprint_status_register_atmel_at26df081a(struct flashchip *flash); int spi_disable_blockprotect_at25df(struct flashchip *flash); int spi_disable_blockprotect_at25df_sec(struct flashchip *flash); int spi_disable_blockprotect_at25f(struct flashchip *flash); int spi_disable_blockprotect_at25fs010(struct flashchip *flash); int spi_disable_blockprotect_at25fs040(struct flashchip *flash); -int spi_byte_program(int addr, uint8_t databyte); -int spi_nbyte_program(int addr, uint8_t *bytes, int len); -int spi_nbyte_read(int addr, uint8_t *bytes, int len); -int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); -int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); -int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len); /* 82802ab.c */ uint8_t wait_82802ab(struct flashchip *flash); -- http://www.hailfinger.org/

2 7

GSOC 2011
by Stefan Tauner 19 May '11

19 May '11

hello since no one on irc even replied with "go away intel nazi!!11", i have to propose my idea here ;) i tried to get flashrom to work on my two main computers[1], but they don't work because of the EC/Intel's management engine (ME). i don't know for sure how the vendor tools do the flashing, but i presume that they talk to the ME via HECI to coordinate the process. There _was_ an attempt to get basic HECI and QST (intel quiet system technology) into the kernel to allow temperature readings etc. Intel abandoned it in 2009 [2]. my (project) idea is to try to reverse engineer some vendor tools to see how they work and try to reproduce it in flashrom to eventually support ME enabled motherboards in flashrom. i dunno how big the impact would be, but i guess this would allow even many laptops to be supported? what do you think about this idea and its feasibility? any volunteers for mentoring? :) 1: http://patchwork.coreboot.org/patch/2798/ 2: http://driverdev.linuxdriverproject.org/pipermail/devel/2009-September/0024… also i have some questions about the "official" ideas: UI: - With TUI do you mean (something like) ncurses? - the "current" code is [3]? i have not looked into it yet. - has it to use qt and/or that code (i like java *hide* and have a bit of gdk experience)? recovery stuff: guess it would be mandatory to have a working coreboot setup with real hardware for that? bitbanging support: this would also require available hardware. would i have to buy that myself? can it be borrowed from someone? these projects would probably profit from my open workbench logic analyzer... the infrastructure things sound a bit boring, but from what i saw in the source some refactoring would (also) improve the codebase somewhat. ;) so the infrastructure-related projects may be even the most valuable contribution for longterm goals. ok that was not really a question, sorry. if there are other ideas i would love to hear them (soon). thanks! 3: http://gitorious.org/flashrom/flashrom-gui/commits/master -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

3 6

Re: [flashrom] [PATCH 1/5] whitespace fixes (space to tabs mostly) and (additional) comments
by Stefan Tauner 18 May '11

18 May '11

revised, self-acked and committed in r1317 -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

Re: [flashrom] [PATCH] whitespace, documentation and other small stuff
by Stefan Tauner 18 May '11

18 May '11

self-acked and committed in r1317 -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

[commit] r1317 - in trunk: . util
by repository service 18 May '11

18 May '11

Author: stefanct Date: Thu May 19 04:58:17 2011 New Revision: 1317 URL: http://flashrom.org/trac/flashrom/changeset/1317 Log: whitespace, documentation and other small stuff this patch combines three previously posted patches in a revised form. one is even stolen from Stefan Reinauer (remove umlauts from man page). Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> some parts are Acked-by: Carl-Daniel Hailfinger<c-d.hailfinger.devel.2006(a)gmx.net> the rest is Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/chipset_enable.c trunk/drkaiser.c trunk/flash.h trunk/flashchips.h trunk/flashrom.8 trunk/flashrom.c trunk/ichspi.c trunk/print.c trunk/print_wiki.c trunk/util/flashrom_partial_write_test.sh trunk/wbsio_spi.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Thu May 19 02:06:06 2011 (r1316) +++ trunk/chipset_enable.c Thu May 19 04:58:17 2011 (r1317) @@ -558,8 +558,8 @@ #define CS5530_ENABLE_SA20 (1 << 6) buses_supported = CHIP_BUSTYPE_PARALLEL; - /* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and - * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB. + /* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and + * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB. * FIXME: Should we really touch the low mapping below 1 MB? Flashrom * ignores that region completely. * Make the configured ROM areas writable. Modified: trunk/drkaiser.c ============================================================================== --- trunk/drkaiser.c Thu May 19 02:06:06 2011 (r1316) +++ trunk/drkaiser.c Thu May 19 04:58:17 2011 (r1317) @@ -49,7 +49,7 @@ rpci_write_word(pcidev_dev, PCI_MAGIC_DRKAISER_ADDR, PCI_MAGIC_DRKAISER_VALUE); - /* Map 128KB flash memory window. */ + /* Map 128kB flash memory window. */ drkaiser_bar = physmap("Dr. Kaiser PC-Waechter flash memory", addr, 128 * 1024); Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Thu May 19 02:06:06 2011 (r1316) +++ trunk/flash.h Thu May 19 04:58:17 2011 (r1317) @@ -107,7 +107,9 @@ uint32_t manufacture_id; uint32_t model_id; + /* Total chip size in kilobytes */ int total_size; + /* Chip page size in bytes */ int page_size; int feature_bits; @@ -125,6 +127,9 @@ /* * Erase blocks and associated erase function. Any chip erase function * is stored as chip-sized virtual block together with said function. + * The first one that fits will be chosen. There is currently no way to + * influence that behaviour. For testing just comment out the other + * elements or set the function pointer to NULL. */ struct block_eraser { struct eraseblock{ Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Thu May 19 02:06:06 2011 (r1316) +++ trunk/flashchips.h Thu May 19 04:58:17 2011 (r1317) @@ -145,9 +145,9 @@ #define ATMEL_AT25FS040 0x6604 #define ATMEL_AT26DF041 0x4400 #define ATMEL_AT26DF081 0x4500 /* guessed, no datasheet available */ -#define ATMEL_AT26DF081A 0x4501 +#define ATMEL_AT26DF081A 0x4501 #define ATMEL_AT26DF161 0x4600 -#define ATMEL_AT26DF161A 0x4601 +#define ATMEL_AT26DF161A 0x4601 #define ATMEL_AT26DF321 0x4700 /* Same as 25DF321 */ #define ATMEL_AT26F004 0x0400 #define ATMEL_AT29C040A 0xA4 Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Thu May 19 02:06:06 2011 (r1316) +++ trunk/flashrom.8 Thu May 19 04:58:17 2011 (r1317) @@ -564,7 +564,7 @@ .br Joe Bao .br -Jörg Fischer +Joerg Fischer .br Joshua Roys .br Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Thu May 19 02:06:06 2011 (r1316) +++ trunk/flashrom.c Thu May 19 04:58:17 2011 (r1317) @@ -1140,7 +1140,7 @@ for (flash = flashchips + startchip; flash && flash->name; flash++) { if (chip_to_probe && strcmp(flash->name, chip_to_probe) != 0) continue; - msg_gdbg("Probing for %s %s, %d KB: ", + msg_gdbg("Probing for %s %s, %d kB: ", flash->vendor, flash->name, flash->total_size); if (!flash->probe && !force) { msg_gdbg("failed! flashrom has no probe function for " @@ -1201,7 +1201,7 @@ #endif snprintf(location, sizeof(location), "on %s", programmer_table[programmer].name); - msg_cinfo("%s chip \"%s %s\" (%d KB, %s) %s.\n", + msg_cinfo("%s chip \"%s %s\" (%d kB, %s) %s.\n", force ? "Assuming" : "Found", flash->vendor, flash->name, flash->total_size, flashbuses_to_text(flash->bustype), location); Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Thu May 19 02:06:06 2011 (r1316) +++ trunk/ichspi.c Thu May 19 04:58:17 2011 (r1317) @@ -43,17 +43,18 @@ #include "spi.h" /* ICH9 controller register definition */ -#define ICH9_REG_FADDR 0x08 /* 32 Bits */ -#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ +#define ICH9_REG_FADDR 0x08 /* 32 Bits */ +#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ -#define ICH9_REG_SSFS 0x90 /* 08 Bits */ +#define ICH9_REG_SSFS 0x90 /* 08 Bits */ #define SSFS_SCIP 0x00000001 #define SSFS_CDS 0x00000004 #define SSFS_FCERR 0x00000008 #define SSFS_AEL 0x00000010 +/* The following bits are reserved in SSFS: 1,5-7. */ #define SSFS_RESERVED_MASK 0x000000e2 -#define ICH9_REG_SSFC 0x91 /* 24 Bits */ +#define ICH9_REG_SSFC 0x91 /* 24 Bits */ #define SSFC_SCGO 0x00000200 #define SSFC_ACS 0x00000400 #define SSFC_SPOP 0x00000800 @@ -64,20 +65,23 @@ #define SSFC_SCF 0x01000000 #define SSFC_SCF_20MHZ 0x00000000 #define SSFC_SCF_33MHZ 0x01000000 +/* We combine SSFS and SSFC to one 32-bit word, + * therefore SSFC bits are off by 8. + * The following bits are reserved in SSFC: 23-19,7,0. */ #define SSFC_RESERVED_MASK 0xf8008100 -#define ICH9_REG_PREOP 0x94 /* 16 Bits */ -#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */ -#define ICH9_REG_OPMENU 0x98 /* 64 Bits */ +#define ICH9_REG_PREOP 0x94 /* 16 Bits */ +#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */ +#define ICH9_REG_OPMENU 0x98 /* 64 Bits */ // ICH9R SPI commands -#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0 -#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1 -#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2 -#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3 +#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0 +#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1 +#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2 +#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3 // ICH7 registers -#define ICH7_REG_SPIS 0x00 /* 16 Bits */ +#define ICH7_REG_SPIS 0x00 /* 16 Bits */ #define SPIS_SCIP 0x0001 #define SPIS_GRANT 0x0002 #define SPIS_CDS 0x0004 @@ -94,17 +98,17 @@ bit 7 is used with fast read and one shot controls CS de-assert? */ -#define ICH7_REG_SPIC 0x02 /* 16 Bits */ -#define SPIC_SCGO 0x0002 -#define SPIC_ACS 0x0004 -#define SPIC_SPOP 0x0008 -#define SPIC_DS 0x4000 - -#define ICH7_REG_SPIA 0x04 /* 32 Bits */ -#define ICH7_REG_SPID0 0x08 /* 64 Bytes */ -#define ICH7_REG_PREOP 0x54 /* 16 Bits */ -#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */ -#define ICH7_REG_OPMENU 0x58 /* 64 Bits */ +#define ICH7_REG_SPIC 0x02 /* 16 Bits */ +#define SPIC_SCGO 0x0002 +#define SPIC_ACS 0x0004 +#define SPIC_SPOP 0x0008 +#define SPIC_DS 0x4000 + +#define ICH7_REG_SPIA 0x04 /* 32 Bits */ +#define ICH7_REG_SPID0 0x08 /* 64 Bytes */ +#define ICH7_REG_PREOP 0x54 /* 16 Bits */ +#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */ +#define ICH7_REG_OPMENU 0x58 /* 64 Bits */ /* ICH SPI configuration lock-down. May be set during chipset enabling. */ static int ichspi_lock = 0; @@ -597,7 +601,7 @@ - waiting for the busy bit (WIP) to be cleared This means the timeout must be sufficient for chip erase of slow high-capacity chips. - */ + */ switch (op.atomic) { case 2: /* Select second preop. */ @@ -703,7 +707,7 @@ /* Assemble SSFS + SSFC */ temp32 = REGREAD32(ICH9_REG_SSFS); - /* keep reserved bits */ + /* Keep reserved bits only */ temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; /* clear error status registers */ temp32 |= (SSFS_CDS + SSFS_FCERR); @@ -712,6 +716,7 @@ /* Use 20 MHz */ temp32 |= SSFC_SCF_20MHZ; + /* Set data byte count (DBC) and data cycle bit (DS) */ if (datalength != 0) { uint32_t datatemp; temp32 |= SSFC_DS; @@ -742,7 +747,7 @@ - waiting for the busy bit (WIP) to be cleared This means the timeout must be sufficient for chip erase of slow high-capacity chips. - */ + */ switch (op.atomic) { case 2: /* Select second preop. */ Modified: trunk/print.c ============================================================================== --- trunk/print.c Thu May 19 02:06:06 2011 (r1316) +++ trunk/print.c Thu May 19 04:58:17 2011 (r1317) @@ -100,7 +100,7 @@ for (i = strlen("Device"); i < maxchiplen; i++) printf(" "); - printf("Tested Known Size/KB: Type:\n"); + printf("Tested Known Size/kB: Type:\n"); for (i = 0; i < okcol; i++) printf(" "); printf("OK Broken\n\n"); Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Thu May 19 02:06:06 2011 (r1316) +++ trunk/print_wiki.c Thu May 19 04:58:17 2011 (r1317) @@ -59,7 +59,7 @@ static const char chip_th[] = "{| border=\"0\" style=\"font-size: smaller\" \ valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ -! align=\"left\" | Device\n! align=\"left\" | Size / KB\n\ +! align=\"left\" | Device\n! align=\"left\" | Size / kB\n\ ! align=\"left\" | Type\n! align=\"left\" colspan=\"4\" | Status\n\n\ |- bgcolor=\"#6699ff\"\n| colspan=\"4\" |  \n\ | Probe\n| Read\n| Erase\n| Write\n\n"; Modified: trunk/util/flashrom_partial_write_test.sh ============================================================================== --- trunk/util/flashrom_partial_write_test.sh Thu May 19 02:06:06 2011 (r1316) +++ trunk/util/flashrom_partial_write_test.sh Thu May 19 04:58:17 2011 (r1317) @@ -18,8 +18,8 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # # This script attempts to test Flashrom partial write capability by writing -# patterns of 0xff and 0x00 bytes to the lowest 128KB of flash. 128KB is chosen -# since 64KB is usually the largest possible block size, so we will try to +# patterns of 0xff and 0x00 bytes to the lowest 128kB of flash. 128kB is chosen +# since 64kB is usually the largest possible block size, so we will try to # cover at least two blocks with this test. EXIT_SUCCESS=0 @@ -197,7 +197,7 @@ # 2. The old content must be restored at unspecified offsets. # 3. The new content must be written at specified offsets. # -# Note: The last chunk of 0xff bytes is only 2K as to avoid overrunning a 128KB +# Note: The last chunk of 0xff bytes is only 2k as to avoid overrunning a 128kB # test image. # echo " Modified: trunk/wbsio_spi.c ============================================================================== --- trunk/wbsio_spi.c Thu May 19 02:06:06 2011 (r1316) +++ trunk/wbsio_spi.c Thu May 19 04:58:17 2011 (r1317) @@ -84,7 +84,7 @@ register_spi_programmer(&spi_programmer_wbsio); msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " - "1024 KB!\n", __func__); + "1024 kB!\n", __func__); max_rom_decode.spi = 1024 * 1024; return 0;

1 0

[PATCH] eliminate magic numbers indicating maximum column sizes in print_supported_chipsets and print_supported_boards_helper
by Stefan Tauner 18 May '11

18 May '11

without this the magic numbers need to be kept in sync with the maximum length of the strings printed in the corresponding column. if not an overflow and a nasty ' '-storm occurs on executing flashrom -L. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- print.c | 101 +++++++++++++++++++++++++++++++++++++++------------------ programmer.h | 8 ++-- 2 files changed, 73 insertions(+), 36 deletions(-) diff --git a/print.c b/print.c index 3760cc4..c21aef6 100644 --- a/print.c +++ b/print.c @@ -22,6 +22,7 @@ #include <stdio.h> #include <string.h> #include <stdlib.h> +#include <assert.h> #include "flash.h" #include "flashchips.h" #include "programmer.h" @@ -77,9 +78,11 @@ static int digits(int n) static void print_supported_chips(void) { int okcol = 0, pos = 0, i, chipcount = 0; - int maxchiplen = 0, maxvendorlen = 0; + int maxvendorlen = strlen("Vendor") + 1; + int maxchiplen = strlen("Device") + 1; const struct flashchip *f; + assert(flashchips != NULL); for (f = flashchips; f->name != NULL; f++) { /* Ignore "unknown XXXX SPI chip" entries. */ if (!strncmp(f->name, "unknown", 7)) @@ -158,63 +161,97 @@ static void print_supported_chips(void) #if CONFIG_INTERNAL == 1 static void print_supported_chipsets(void) { - int i, j, chipsetcount = 0; + int i, chipsetcount = 0; const struct penable *c = chipset_enables; + int maxvendorlen = strlen("Vendor") + 1; + int maxchipsetlen = strlen("Chipset") + 1; - for (i = 0; c[i].vendor_name != NULL; i++) + assert(chipset_enables != NULL); + for (c = chipset_enables; c->vendor_name != NULL; c++) { chipsetcount++; + maxvendorlen = max(maxvendorlen, strlen(c->vendor_name)); + maxchipsetlen = max(maxchipsetlen, strlen(c->device_name)); + } + maxvendorlen++; + maxchipsetlen++; + + printf("\nSupported chipsets (total: %d):\n\n", chipsetcount); + + printf("Vendor"); + for (i = strlen("Vendor"); i < maxvendorlen; i++) + printf(" "); + + printf("Chipset"); + for (i = strlen("Chipset"); i < maxchipsetlen; i++) + printf(" "); - printf("\nSupported chipsets (total: %d):\n\nVendor: " - "Chipset: PCI IDs:\n\n", chipsetcount); + printf("PCI IDs State\n\n"); - for (i = 0; c[i].vendor_name != NULL; i++) { - printf("%s", c[i].vendor_name); - for (j = 0; j < 25 - strlen(c[i].vendor_name); j++) + for (c = chipset_enables; c->vendor_name != NULL; c++) { + printf("%s", c->vendor_name); + for (i = 0; i < maxvendorlen - strlen(c->vendor_name); i++) printf(" "); - printf("%s", c[i].device_name); - for (j = 0; j < 25 - strlen(c[i].device_name); j++) + printf("%s", c->device_name); + for (i = 0; i < maxchipsetlen - strlen(c->device_name); i++) printf(" "); - printf("%04x:%04x%s\n", c[i].vendor_id, c[i].device_id, - (c[i].status == OK) ? "" : " (untested)"); + printf("%04x:%04x%s\n", c->vendor_id, c->device_id, + (c->status == OK) ? "" : " (untested)"); } } static void print_supported_boards_helper(const struct board_info *boards, const char *devicetype) { - int i, j, boardcount_good = 0, boardcount_bad = 0; - const struct board_pciid_enable *b = board_pciid_enables; - - for (i = 0; boards[i].vendor != NULL; i++) { - if (boards[i].working) + int i, boardcount_good = 0, boardcount_bad = 0; + const struct board_pciid_enable *e = board_pciid_enables; + const struct board_info *b = boards; + int maxvendorlen = strlen("Vendor") + 1; + int maxboardlen = strlen("Board") + 1; + + assert(boards != NULL); + for (b = boards; b->vendor != NULL; b++) { + maxvendorlen = max(maxvendorlen, strlen(b->vendor)); + maxboardlen = max(maxboardlen, strlen(b->name)); + if (b->working) boardcount_good++; else boardcount_bad++; } + maxvendorlen++; + maxboardlen++; + + printf("\nKnown %s (good: %d, bad: %d):\n\n", + devicetype, boardcount_good, boardcount_bad); + + printf("Vendor"); + for (i = strlen("Vendor"); i < maxvendorlen; i++) + printf(" "); + + printf("Board"); + for (i = strlen("Board"); i < maxboardlen; i++) + printf(" "); - printf("\nKnown %s (good: %d, bad: %d):" - "\n\nVendor: Board: " - "Status: Required option:" - "\n\n", devicetype, boardcount_good, boardcount_bad); + printf("Status Required option\n\n"); - for (i = 0; boards[i].vendor != NULL; i++) { - printf("%s", boards[i].vendor); - for (j = 0; j < 25 - strlen(boards[i].vendor); j++) + assert(board_pciid_enables != NULL); + for (b = boards; b->vendor != NULL; b++) { + printf("%s", b->vendor); + for (i = 0; i < maxvendorlen - strlen(b->vendor); i++) printf(" "); - printf("%s", boards[i].name); - for (j = 0; j < 28 - strlen(boards[i].name); j++) + printf("%s", b->name); + for (i = 0; i < maxboardlen - strlen(b->name); i++) printf(" "); - printf((boards[i].working) ? "OK " : "BAD "); + printf((b->working) ? "OK " : "BAD "); - for (j = 0; b[j].vendor_name != NULL; j++) { - if (strcmp(b[j].vendor_name, boards[i].vendor) - || strcmp(b[j].board_name, boards[i].name)) + for (e = board_pciid_enables; e->vendor_name != NULL; e++) { + if (strcmp(e->vendor_name, b->vendor) + || strcmp(e->board_name, b->name)) continue; - if (b[j].lb_vendor == NULL) + if (e->lb_vendor == NULL) printf("(autodetected)"); else - printf("-m %s:%s", b[j].lb_vendor, - b[j].lb_part); + printf("-m %s:%s", e->lb_vendor, + e->lb_part); } printf("\n"); } diff --git a/programmer.h b/programmer.h index b68aa88..e1147f1 100644 --- a/programmer.h +++ b/programmer.h @@ -145,7 +145,7 @@ struct bitbang_spi_master { struct penable { uint16_t vendor_id; uint16_t device_id; - int status; + int status; /* OK=0 and NT=1 are defines only. Beware! */ const char *vendor_name; const char *device_name; int (*doit) (struct pci_dev *dev, const char *name); @@ -174,10 +174,10 @@ struct board_pciid_enable { uint16_t second_card_vendor; uint16_t second_card_device; - /* Pattern to match DMI entries */ + /* Pattern to match DMI entries. May be NULL. */ const char *dmi_pattern; - /* The vendor / part name from the coreboot table. */ + /* The vendor / part name from the coreboot table. May be NULL. */ const char *lb_vendor; const char *lb_part; @@ -188,7 +188,7 @@ struct board_pciid_enable { int max_rom_decode_parallel; int status; - int (*enable) (void); + int (*enable) (void); /* May be NULL. */ }; extern const struct board_pciid_enable board_pciid_enables[]; -- 1.7.1

1 0

[commit] r1316 - trunk
by repository service 18 May '11

18 May '11

Author: hailfinger Date: Thu May 19 02:06:06 2011 New Revision: 1316 URL: http://flashrom.org/trac/flashrom/changeset/1316 Log: Add lock printing for AMIC A25L05PT, A25L05PU, A25L10PT, A25L10PU, A25L20PT, A25L20PU, A25L40PT, A25L40PU, A25L80P, A25L16PT, A25L16PU, A25L512, A25L010, A25L020, A25L040, A25L080, A25L016, A25L032, A25LQ032 to a25.c. Add lock printing for Atmel AT26DF081A, AT26DF161, AT26DF161A, AT26DF321. Move Atmel AT25*/AT26* lock related functions originally added in r1115 from spi25.c to at25.c. For SPI chips the lock printing was handled by one common function, but sharing a common function which only is a big switch() statement doesn't make sense, especially if we can define lock printing functions per flash chip anyway. The printlock function pointer in struct flashchip is used to print status register and locking information, and serves as replacement for implicit status register and lock printing during probe. That code will later be changed to store locking info in a machine- accessible data structure so flashrom can handle locked regions correctly. Signed-off-by: Carl-Daniel Hailfinger<c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Added: trunk/a25.c trunk/at25.c Modified: trunk/Makefile trunk/chipdrivers.h trunk/flashchips.c trunk/spi25.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Wed May 18 13:28:47 2011 (r1315) +++ trunk/Makefile Thu May 19 02:06:06 2011 (r1316) @@ -119,7 +119,8 @@ CHIP_OBJS = jedec.o stm50flw0x0x.o w39.o w29ee011.o \ sst28sf040.o m29f400bt.o 82802ab.o pm49fl00x.o \ - sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o sharplhf00l04.o + sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o sharplhf00l04.o \ + a25.o at25.o LIB_OBJS = layout.o Added: trunk/a25.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/a25.c Thu May 19 02:06:06 2011 (r1316) @@ -0,0 +1,104 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2010 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "flash.h" +#include "chipdrivers.h" +#include "spi.h" + +/* Prettyprint the status register. Works for AMIC A25L series. */ + +int spi_prettyprint_status_register_amic_a25l05p(struct flashchip *flash) +{ + uint8_t status; + + status = spi_read_status_register(); + msg_cdbg("Chip status register is %02x\n", status); + + msg_cdbg("Chip status register: Status Register Write Disable " + "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); + spi_prettyprint_status_register_bit(status, 6); + spi_prettyprint_status_register_bit(status, 5); + spi_prettyprint_status_register_bit(status, 4); + spi_prettyprint_status_register_bp3210(status, 1); + spi_prettyprint_status_register_welwip(status); + return 0; +} + +int spi_prettyprint_status_register_amic_a25l40p(struct flashchip *flash) +{ + uint8_t status; + + status = spi_read_status_register(); + msg_cdbg("Chip status register is %02x\n", status); + + msg_cdbg("Chip status register: Status Register Write Disable " + "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); + spi_prettyprint_status_register_bit(status, 6); + spi_prettyprint_status_register_bit(status, 5); + spi_prettyprint_status_register_bp3210(status, 2); + spi_prettyprint_status_register_welwip(status); + return 0; +} + +int spi_prettyprint_status_register_amic_a25l032(struct flashchip *flash) +{ + uint8_t status; + + status = spi_read_status_register(); + msg_cdbg("Chip status register is %02x\n", status); + + msg_cdbg("Chip status register: Status Register Write Disable " + "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); + msg_cdbg("Chip status register: Sector Protect Size (SEC) " + "is %i KB\n", (status & (1 << 6)) ? 4 : 64); + msg_cdbg("Chip status register: Top/Bottom (TB) " + "is %s\n", (status & (1 << 5)) ? "bottom" : "top"); + spi_prettyprint_status_register_bp3210(status, 2); + spi_prettyprint_status_register_welwip(status); + msg_cdbg("Chip status register 2 is NOT decoded!\n"); + return 0; +} + +int spi_prettyprint_status_register_amic_a25lq032(struct flashchip *flash) +{ + uint8_t status; + + status = spi_read_status_register(); + msg_cdbg("Chip status register is %02x\n", status); + + msg_cdbg("Chip status register: Status Register Write Disable " + "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); + msg_cdbg("Chip status register: Sector Protect Size (SEC) " + "is %i KB\n", (status & (1 << 6)) ? 4 : 64); + msg_cdbg("Chip status register: Top/Bottom (TB) " + "is %s\n", (status & (1 << 5)) ? "bottom" : "top"); + spi_prettyprint_status_register_bp3210(status, 2); + spi_prettyprint_status_register_welwip(status); + msg_cdbg("Chip status register 2 is NOT decoded!\n"); + return 0; +} + +/* FIXME: spi_disable_blockprotect is incorrect but works fine for chips using + * spi_prettyprint_status_register_amic_a25l05p or + * spi_prettyprint_status_register_amic_a25l40p. + * FIXME: spi_disable_blockprotect is incorrect and will fail for chips using + * spi_prettyprint_status_register_amic_a25l032 or + * spi_prettyprint_status_register_amic_a25lq032 if those have locks controlled + * by the second status register. + */ Added: trunk/at25.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/at25.c Thu May 19 02:06:06 2011 (r1316) @@ -0,0 +1,287 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2010 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "flash.h" +#include "chipdrivers.h" +#include "spi.h" + +/* Prettyprint the status register. Works for Atmel A25/A26 series. */ + +static void spi_prettyprint_status_register_atmel_at25_srpl(uint8_t status) +{ + msg_cdbg("Chip status register: Sector Protection Register Lock (SRPL) " + "is %sset\n", (status & (1 << 7)) ? "" : "not "); +} + +static void spi_prettyprint_status_register_atmel_at25_epewpp(uint8_t status) +{ + msg_cdbg("Chip status register: Erase/Program Error (EPE) " + "is %sset\n", (status & (1 << 5)) ? "" : "not "); + msg_cdbg("Chip status register: WP# pin (WPP) " + "is %sasserted\n", (status & (1 << 4)) ? "not " : ""); +} + +static void spi_prettyprint_status_register_atmel_at25_swp(uint8_t status) +{ + msg_cdbg("Chip status register: Software Protection Status (SWP): "); + switch (status & (3 << 2)) { + case 0x0 << 2: + msg_cdbg("no sectors are protected\n"); + break; + case 0x1 << 2: + msg_cdbg("some sectors are protected\n"); + /* FIXME: Read individual Sector Protection Registers. */ + break; + case 0x3 << 2: + msg_cdbg("all sectors are protected\n"); + break; + default: + msg_cdbg("reserved for future use\n"); + break; + } +} + +int spi_prettyprint_status_register_at25df(struct flashchip *flash) +{ + uint8_t status; + + status = spi_read_status_register(); + msg_cdbg("Chip status register is %02x\n", status); + + spi_prettyprint_status_register_atmel_at25_srpl(status); + spi_prettyprint_status_register_bit(status, 6); + spi_prettyprint_status_register_atmel_at25_epewpp(status); + spi_prettyprint_status_register_atmel_at25_swp(status); + spi_prettyprint_status_register_welwip(status); + return 0; +} + +int spi_prettyprint_status_register_at25df_sec(struct flashchip *flash) +{ + /* FIXME: We should check the security lockdown. */ + msg_cdbg("Ignoring security lockdown (if present)\n"); + msg_cdbg("Ignoring status register byte 2\n"); + return spi_prettyprint_status_register_at25df(flash); +} + +int spi_prettyprint_status_register_at25f(struct flashchip *flash) +{ + uint8_t status; + + status = spi_read_status_register(); + msg_cdbg("Chip status register is %02x\n", status); + + spi_prettyprint_status_register_atmel_at25_srpl(status); + spi_prettyprint_status_register_bit(status, 6); + spi_prettyprint_status_register_atmel_at25_epewpp(status); + spi_prettyprint_status_register_bit(status, 3); + msg_cdbg("Chip status register: Block Protect 0 (BP0) is " + "%sset, %s sectors are protected\n", + (status & (1 << 2)) ? "" : "not ", + (status & (1 << 2)) ? "all" : "no"); + spi_prettyprint_status_register_welwip(status); + return 0; +} + +int spi_prettyprint_status_register_at25fs010(struct flashchip *flash) +{ + uint8_t status; + + status = spi_read_status_register(); + msg_cdbg("Chip status register is %02x\n", status); + + msg_cdbg("Chip status register: Status Register Write Protect (WPEN) " + "is %sset\n", (status & (1 << 7)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 6 / Block Protect 4 (BP4) is " + "%sset\n", (status & (1 << 6)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) is " + "%sset\n", (status & (1 << 5)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 4 is " + "%sset\n", (status & (1 << 4)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) is " + "%sset\n", (status & (1 << 3)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) is " + "%sset\n", (status & (1 << 2)) ? "" : "not "); + /* FIXME: Pretty-print detailed sector protection status. */ + spi_prettyprint_status_register_welwip(status); + return 0; +} + +int spi_prettyprint_status_register_at25fs040(struct flashchip *flash) +{ + uint8_t status; + + status = spi_read_status_register(); + msg_cdbg("Chip status register is %02x\n", status); + + msg_cdbg("Chip status register: Status Register Write Protect (WPEN) " + "is %sset\n", (status & (1 << 7)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 6 / Block Protect 4 (BP4) is " + "%sset\n", (status & (1 << 6)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) is " + "%sset\n", (status & (1 << 5)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 4 / Block Protect 2 (BP2) is " + "%sset\n", (status & (1 << 4)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) is " + "%sset\n", (status & (1 << 3)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) is " + "%sset\n", (status & (1 << 2)) ? "" : "not "); + /* FIXME: Pretty-print detailed sector protection status. */ + spi_prettyprint_status_register_welwip(status); + return 0; +} + +int spi_prettyprint_status_register_atmel_at26df081a(struct flashchip *flash) +{ + uint8_t status; + + status = spi_read_status_register(); + msg_cdbg("Chip status register is %02x\n", status); + + spi_prettyprint_status_register_atmel_at25_srpl(status); + msg_cdbg("Chip status register: Sequential Program Mode Status (SPM) " + "is %sset\n", (status & (1 << 6)) ? "" : "not "); + spi_prettyprint_status_register_atmel_at25_epewpp(status); + spi_prettyprint_status_register_atmel_at25_swp(status); + spi_prettyprint_status_register_welwip(status); + return 0; +} + +int spi_disable_blockprotect_at25df(struct flashchip *flash) +{ + uint8_t status; + int result; + + status = spi_read_status_register(); + /* If block protection is disabled, stop here. */ + if ((status & (3 << 2)) == 0) + return 0; + + msg_cdbg("Some block protection in effect, disabling\n"); + if (status & (1 << 7)) { + msg_cdbg("Need to disable Sector Protection Register Lock\n"); + if ((status & (1 << 4)) == 0) { + msg_cerr("WP# pin is active, disabling " + "write protection is impossible.\n"); + return 1; + } + /* All bits except bit 7 (SPRL) are readonly. */ + result = spi_write_status_register(flash, status & ~(1 << 7)); + if (result) { + msg_cerr("spi_write_status_register failed\n"); + return result; + } + + } + /* Global unprotect. Make sure to mask SPRL as well. */ + result = spi_write_status_register(flash, status & ~0xbc); + if (result) { + msg_cerr("spi_write_status_register failed\n"); + return result; + } + status = spi_read_status_register(); + if ((status & (3 << 2)) != 0) { + msg_cerr("Block protection could not be disabled!\n"); + return 1; + } + return 0; +} + +int spi_disable_blockprotect_at25df_sec(struct flashchip *flash) +{ + /* FIXME: We should check the security lockdown. */ + msg_cinfo("Ignoring security lockdown (if present)\n"); + return spi_disable_blockprotect_at25df(flash); +} + +int spi_disable_blockprotect_at25f(struct flashchip *flash) +{ + /* spi_disable_blockprotect_at25df is not really the right way to do + * this, but the side effects of said function work here as well. + */ + return spi_disable_blockprotect_at25df(flash); +} + +int spi_disable_blockprotect_at25fs010(struct flashchip *flash) +{ + uint8_t status; + int result; + + status = spi_read_status_register(); + /* If block protection is disabled, stop here. */ + if ((status & 0x6c) == 0) + return 0; + + msg_cdbg("Some block protection in effect, disabling\n"); + if (status & (1 << 7)) { + msg_cdbg("Need to disable Status Register Write Protect\n"); + /* Clear bit 7 (WPEN). */ + result = spi_write_status_register(flash, status & ~(1 << 7)); + if (result) { + msg_cerr("spi_write_status_register failed\n"); + return result; + } + } + /* Global unprotect. Make sure to mask WPEN as well. */ + result = spi_write_status_register(flash, status & ~0xec); + if (result) { + msg_cerr("spi_write_status_register failed\n"); + return result; + } + status = spi_read_status_register(); + if ((status & 0x6c) != 0) { + msg_cerr("Block protection could not be disabled!\n"); + return 1; + } + return 0; +} + +int spi_disable_blockprotect_at25fs040(struct flashchip *flash) +{ + uint8_t status; + int result; + + status = spi_read_status_register(); + /* If block protection is disabled, stop here. */ + if ((status & 0x7c) == 0) + return 0; + + msg_cdbg("Some block protection in effect, disabling\n"); + if (status & (1 << 7)) { + msg_cdbg("Need to disable Status Register Write Protect\n"); + /* Clear bit 7 (WPEN). */ + result = spi_write_status_register(flash, status & ~(1 << 7)); + if (result) { + msg_cerr("spi_write_status_register failed\n"); + return result; + } + } + /* Global unprotect. Make sure to mask WPEN as well. */ + result = spi_write_status_register(flash, status & ~0xfc); + if (result) { + msg_cerr("spi_write_status_register failed\n"); + return result; + } + status = spi_read_status_register(); + if ((status & 0x7c) != 0) { + msg_cerr("Block protection could not be disabled!\n"); + return 1; + } + return 0; +} Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Wed May 18 13:28:47 2011 (r1315) +++ trunk/chipdrivers.h Thu May 19 02:06:06 2011 (r1316) @@ -43,23 +43,37 @@ int spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); uint8_t spi_read_status_register(void); +int spi_write_status_register(struct flashchip *flash, int status); +void spi_prettyprint_status_register_bit(uint8_t status, int bit); +void spi_prettyprint_status_register_bp3210(uint8_t status, int bp); +void spi_prettyprint_status_register_welwip(uint8_t status); +int spi_prettyprint_status_register(struct flashchip *flash); +int spi_disable_blockprotect(struct flashchip *flash); +int spi_byte_program(int addr, uint8_t databyte); +int spi_nbyte_program(int addr, uint8_t *bytes, int len); +int spi_nbyte_read(int addr, uint8_t *bytes, int len); +int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); +int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); +int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len); + +/* a25.c */ +int spi_prettyprint_status_register_amic_a25l05p(struct flashchip *flash); +int spi_prettyprint_status_register_amic_a25l40p(struct flashchip *flash); +int spi_prettyprint_status_register_amic_a25l032(struct flashchip *flash); +int spi_prettyprint_status_register_amic_a25lq032(struct flashchip *flash); + +/* at25.c */ int spi_prettyprint_status_register_at25df(struct flashchip *flash); int spi_prettyprint_status_register_at25df_sec(struct flashchip *flash); int spi_prettyprint_status_register_at25f(struct flashchip *flash); int spi_prettyprint_status_register_at25fs010(struct flashchip *flash); int spi_prettyprint_status_register_at25fs040(struct flashchip *flash); -int spi_disable_blockprotect(struct flashchip *flash); +int spi_prettyprint_status_register_atmel_at26df081a(struct flashchip *flash); int spi_disable_blockprotect_at25df(struct flashchip *flash); int spi_disable_blockprotect_at25df_sec(struct flashchip *flash); int spi_disable_blockprotect_at25f(struct flashchip *flash); int spi_disable_blockprotect_at25fs010(struct flashchip *flash); int spi_disable_blockprotect_at25fs040(struct flashchip *flash); -int spi_byte_program(int addr, uint8_t databyte); -int spi_nbyte_program(int addr, uint8_t *bytes, int len); -int spi_nbyte_read(int addr, uint8_t *bytes, int len); -int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); -int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); -int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len); /* 82802ab.c */ uint8_t wait_82802ab(struct flashchip *flash); Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Wed May 18 13:28:47 2011 (r1315) +++ trunk/flashchips.c Thu May 19 02:06:06 2011 (r1316) @@ -546,6 +546,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l05p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -577,6 +578,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l05p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -609,6 +611,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l05p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -641,6 +644,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l05p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -673,6 +677,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l05p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -705,6 +710,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l05p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -742,6 +748,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -774,6 +781,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -806,6 +814,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -841,6 +850,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -876,6 +886,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -906,6 +917,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -936,6 +948,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -966,6 +979,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -996,6 +1010,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1026,6 +1041,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1056,6 +1072,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1092,6 +1109,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l032, .unlock = NULL, /* Two status reg bytes (read with 0x35 and 0x05) */ .write = spi_chip_write_256, .read = spi_chip_read, @@ -1128,6 +1146,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25lq032, .unlock = NULL, /* Two status reg bytes (read with 0x35 and 0x05) */ .write = spi_chip_write_256, .read = spi_chip_read, @@ -1746,6 +1765,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_atmel_at26df081a, .unlock = spi_disable_blockprotect_at25df, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1781,6 +1801,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_at25df, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1816,6 +1837,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_atmel_at26df081a, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1833,6 +1855,7 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, + .printlock = spi_prettyprint_status_register_atmel_at26df081a, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, Modified: trunk/spi25.c ============================================================================== --- trunk/spi25.c Wed May 18 13:28:47 2011 (r1315) +++ trunk/spi25.c Thu May 19 02:06:06 2011 (r1316) @@ -29,8 +29,6 @@ #include "programmer.h" #include "spi.h" -void spi_prettyprint_status_register(struct flashchip *flash); - static int spi_rdid(unsigned char *readarr, int bytes) { static const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID }; @@ -312,7 +310,7 @@ } /* Prettyprint the status register. Common definitions. */ -static void spi_prettyprint_status_register_welwip(uint8_t status) +void spi_prettyprint_status_register_welwip(uint8_t status) { msg_cdbg("Chip status register: Write Enable Latch (WEL) is " "%sset\n", (status & (1 << 1)) ? "" : "not "); @@ -321,142 +319,36 @@ } /* Prettyprint the status register. Common definitions. */ -static void spi_prettyprint_status_register_common(uint8_t status) -{ - msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) is " - "%sset\n", (status & (1 << 5)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 4 / Block Protect 2 (BP2) is " - "%sset\n", (status & (1 << 4)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) is " - "%sset\n", (status & (1 << 3)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) is " - "%sset\n", (status & (1 << 2)) ? "" : "not "); - spi_prettyprint_status_register_welwip(status); -} - -/* Prettyprint the status register. Works for - * AMIC A25L series - */ -void spi_prettyprint_status_register_amic_a25l(uint8_t status) -{ - msg_cdbg("Chip status register: Status Register Write Disable " - "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); - spi_prettyprint_status_register_common(status); -} - -/* Prettyprint the status register. Common definitions. */ -static void spi_prettyprint_status_register_at25_srplepewpp(uint8_t status) -{ - msg_cdbg("Chip status register: Sector Protection Register Lock (SRPL) " - "is %sset\n", (status & (1 << 7)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 6 " - "is %sset\n", (status & (1 << 6)) ? "" : "not "); - msg_cdbg("Chip status register: Erase/Program Error (EPE) " - "is %sset\n", (status & (1 << 5)) ? "" : "not "); - msg_cdbg("Chip status register: WP# pin (WPP) " - "is %sactive\n", (status & (1 << 4)) ? "not " : ""); -} - -int spi_prettyprint_status_register_at25df(struct flashchip *flash) +void spi_prettyprint_status_register_bp3210(uint8_t status, int bp) { - uint8_t status; - - status = spi_read_status_register(); - msg_cdbg("Chip status register is %02x\n", status); - - spi_prettyprint_status_register_at25_srplepewpp(status); - msg_cdbg("Chip status register: Software Protection Status (SWP): "); - switch (status & (3 << 2)) { - case 0x0 << 2: - msg_cdbg("no sectors are protected\n"); - break; - case 0x1 << 2: - msg_cdbg("some sectors are protected\n"); - /* FIXME: Read individual Sector Protection Registers. */ - break; - case 0x3 << 2: - msg_cdbg("all sectors are protected\n"); - break; - default: - msg_cdbg("reserved for future use\n"); - break; + switch (bp) { + /* Fall through. */ + case 3: + msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) " + "is %sset\n", (status & (1 << 5)) ? "" : "not "); + case 2: + msg_cdbg("Chip status register: Bit 4 / Block Protect 2 (BP2) " + "is %sset\n", (status & (1 << 4)) ? "" : "not "); + case 1: + msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) " + "is %sset\n", (status & (1 << 3)) ? "" : "not "); + case 0: + msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) " + "is %sset\n", (status & (1 << 2)) ? "" : "not "); } - spi_prettyprint_status_register_welwip(status); - return 0; } -int spi_prettyprint_status_register_at25df_sec(struct flashchip *flash) +/* Prettyprint the status register. Unnamed bits. */ +void spi_prettyprint_status_register_bit(uint8_t status, int bit) { - /* FIXME: We should check the security lockdown. */ - msg_cdbg("Ignoring security lockdown (if present)\n"); - msg_cdbg("Ignoring status register byte 2\n"); - return spi_prettyprint_status_register_at25df(flash); + msg_cdbg("Chip status register: Bit %i " + "is %sset\n", bit, (status & (1 << bit)) ? "" : "not "); } -int spi_prettyprint_status_register_at25f(struct flashchip *flash) -{ - uint8_t status; - - status = spi_read_status_register(); - msg_cdbg("Chip status register is %02x\n", status); - - spi_prettyprint_status_register_at25_srplepewpp(status); - msg_cdbg("Chip status register: Bit 3 " - "is %sset\n", (status & (1 << 3)) ? "" : "not "); - msg_cdbg("Chip status register: Block Protect 0 (BP0) is " - "%sset, %s sectors are protected\n", - (status & (1 << 2)) ? "" : "not ", - (status & (1 << 2)) ? "all" : "no"); - spi_prettyprint_status_register_welwip(status); - return 0; -} - -int spi_prettyprint_status_register_at25fs010(struct flashchip *flash) +static void spi_prettyprint_status_register_common(uint8_t status) { - uint8_t status; - - status = spi_read_status_register(); - msg_cdbg("Chip status register is %02x\n", status); - - msg_cdbg("Chip status register: Status Register Write Protect (WPEN) " - "is %sset\n", (status & (1 << 7)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 6 / Block Protect 4 (BP4) is " - "%sset\n", (status & (1 << 6)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) is " - "%sset\n", (status & (1 << 5)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 4 is " - "%sset\n", (status & (1 << 4)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) is " - "%sset\n", (status & (1 << 3)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) is " - "%sset\n", (status & (1 << 2)) ? "" : "not "); - /* FIXME: Pretty-print detailed sector protection status. */ + spi_prettyprint_status_register_bp3210(status, 3); spi_prettyprint_status_register_welwip(status); - return 0; -} - -int spi_prettyprint_status_register_at25fs040(struct flashchip *flash) -{ - uint8_t status; - - status = spi_read_status_register(); - msg_cdbg("Chip status register is %02x\n", status); - - msg_cdbg("Chip status register: Status Register Write Protect (WPEN) " - "is %sset\n", (status & (1 << 7)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 6 / Block Protect 4 (BP4) is " - "%sset\n", (status & (1 << 6)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) is " - "%sset\n", (status & (1 << 5)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 4 / Block Protect 2 (BP2) is " - "%sset\n", (status & (1 << 4)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) is " - "%sset\n", (status & (1 << 3)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) is " - "%sset\n", (status & (1 << 2)) ? "" : "not "); - /* FIXME: Pretty-print detailed sector protection status. */ - spi_prettyprint_status_register_welwip(status); - return 0; } /* Prettyprint the status register. Works for @@ -514,17 +406,13 @@ bpt[(status & 0x1c) >> 2]); } -void spi_prettyprint_status_register(struct flashchip *flash) +int spi_prettyprint_status_register(struct flashchip *flash) { uint8_t status; status = spi_read_status_register(); msg_cdbg("Chip status register is %02x\n", status); switch (flash->manufacture_id) { - case AMIC_ID: - if ((flash->model_id & 0xff00) == 0x2000) - spi_prettyprint_status_register_amic_a25l(status); - break; case ST_ID: if (((flash->model_id & 0xff00) == 0x2000) || ((flash->model_id & 0xff00) == 0x2500)) @@ -549,6 +437,7 @@ } break; } + return 0; } int spi_chip_erase_60(struct flashchip *flash) @@ -949,7 +838,7 @@ return 0; } -static int spi_write_status_register(struct flashchip *flash, int status) +int spi_write_status_register(struct flashchip *flash, int status) { int ret = 1; @@ -1072,128 +961,6 @@ msg_cerr("Block protection could not be disabled!\n"); return 1; } - return 0; -} - -int spi_disable_blockprotect_at25df(struct flashchip *flash) -{ - uint8_t status; - int result; - - status = spi_read_status_register(); - /* If block protection is disabled, stop here. */ - if ((status & (3 << 2)) == 0) - return 0; - - msg_cdbg("Some block protection in effect, disabling\n"); - if (status & (1 << 7)) { - msg_cdbg("Need to disable Sector Protection Register Lock\n"); - if ((status & (1 << 4)) == 0) { - msg_cerr("WP# pin is active, disabling " - "write protection is impossible.\n"); - return 1; - } - /* All bits except bit 7 (SPRL) are readonly. */ - result = spi_write_status_register(flash, status & ~(1 << 7)); - if (result) { - msg_cerr("spi_write_status_register failed\n"); - return result; - } - - } - /* Global unprotect. Make sure to mask SPRL as well. */ - result = spi_write_status_register(flash, status & ~0xbc); - if (result) { - msg_cerr("spi_write_status_register failed\n"); - return result; - } - status = spi_read_status_register(); - if ((status & (3 << 2)) != 0) { - msg_cerr("Block protection could not be disabled!\n"); - return 1; - } - return 0; -} - -int spi_disable_blockprotect_at25df_sec(struct flashchip *flash) -{ - /* FIXME: We should check the security lockdown. */ - msg_cinfo("Ignoring security lockdown (if present)\n"); - return spi_disable_blockprotect_at25df(flash); -} - -int spi_disable_blockprotect_at25f(struct flashchip *flash) -{ - /* spi_disable_blockprotect_at25df is not really the right way to do - * this, but the side effects of said function work here as well. - */ - return spi_disable_blockprotect_at25df(flash); -} - -int spi_disable_blockprotect_at25fs010(struct flashchip *flash) -{ - uint8_t status; - int result; - - status = spi_read_status_register(); - /* If block protection is disabled, stop here. */ - if ((status & 0x6c) == 0) - return 0; - - msg_cdbg("Some block protection in effect, disabling\n"); - if (status & (1 << 7)) { - msg_cdbg("Need to disable Status Register Write Protect\n"); - /* Clear bit 7 (WPEN). */ - result = spi_write_status_register(flash, status & ~(1 << 7)); - if (result) { - msg_cerr("spi_write_status_register failed\n"); - return result; - } - } - /* Global unprotect. Make sure to mask WPEN as well. */ - result = spi_write_status_register(flash, status & ~0xec); - if (result) { - msg_cerr("spi_write_status_register failed\n"); - return result; - } - status = spi_read_status_register(); - if ((status & 0x6c) != 0) { - msg_cerr("Block protection could not be disabled!\n"); - return 1; - } - return 0; -} -int spi_disable_blockprotect_at25fs040(struct flashchip *flash) -{ - uint8_t status; - int result; - - status = spi_read_status_register(); - /* If block protection is disabled, stop here. */ - if ((status & 0x7c) == 0) - return 0; - - msg_cdbg("Some block protection in effect, disabling\n"); - if (status & (1 << 7)) { - msg_cdbg("Need to disable Status Register Write Protect\n"); - /* Clear bit 7 (WPEN). */ - result = spi_write_status_register(flash, status & ~(1 << 7)); - if (result) { - msg_cerr("spi_write_status_register failed\n"); - return result; - } - } - /* Global unprotect. Make sure to mask WPEN as well. */ - result = spi_write_status_register(flash, status & ~0xfc); - if (result) { - msg_cerr("spi_write_status_register failed\n"); - return result; - } - status = spi_read_status_register(); - if ((status & 0x7c) != 0) { - msg_cerr("Block protection could not be disabled!\n"); - return 1; - } return 0; }

1 0

ST M25P32
by Ferenc Cserepkei 18 May '11

18 May '11

Hi, These are the results of flashrom v0.9.3 (svn checked out friday) on HP compaq nw8440 running Ubuntu 10.10, AMD64, DediProg SF100 USB flasher is used. Regards: Ferenc

2 1

working: MSI 870-C45 (MS-7599)
by Kjell Braden 18 May '11

18 May '11

Hi, I've a new mainboard: MSI 870-C45 (MS-7599). Everything (reading, writing, verifying) works fine. Cheers, -- Kjell

2 1

Test Results: ST M50FW080 on Pentium-M+ICH4-M Mainboard
by bruce＠anagrams.biz 18 May '11

18 May '11

Hi, Flashrom v0.9.3-r1299 will erase and write the ST M50FW080. I am using a proprietary mainboard with Pentium-M, ICH4-M, and an H8 EC which doesn't get in the way. It's very similar to a middle-aged laptop. Given the nature of the Intel ICH chips, I would expect any ICH4-based system to behave the same, but I haven't tried it. flashrom output files are attached. -- Bruce Stofer 76a75ab1897e7b4dd7d50747ea3d1121 flashrom-E.out =============================================================================== begin 664 flashrom-E.out M9FQA<VAR;VT(a)=C`N.2XS+7(Q,C`U(&]N($QI;G5X(#(N-BXS,BXR,"YP<RTQ M,#`T,C(M<W1J=61E+6UE<FQI;B`H:38X-BDL(&)U:6QT('=I=&@@;&EB<&-I M(#,N,"XP+"!'0T,@-"XS+C,L(&QI='1L92!E;F1I86X*9FQA<VAR;VT@:7,@ M9G)E92!S;V9T=V%R92P@9V5T('1H92!S;W5R8V4@8V]D92!A="!H='1P.B\O M=W=W+F9L87-H<F]M+F]R9PH*0V%L:6)R871I;F<@9&5L87D@;&]O<"XN+B!/ M4R!T:6UE<B!R97-O;'5T:6]N(&ES(#4@=7-E8W,L(#DW-4T@;&]O<',@<&5R M('-E8V]N9"P@,3`@;7EU<R`](#$T('5S+"`Q,#`@;7EU<R`](#$Q-2!U<RP@ M,3`P,"!M>75S(#T(a),3`Y.2!U<RP@,3`P,#`@;7EU<R`](#$P,C(W('5S+"`R M,"!M>75S(#T@,C<@=7,L($]++@I);FET:6%L:7II;F<@:6YT97)N86P@<')O M9W)A;6UE<@I.;R!C;W)E8F]O="!T86)L92!F;W5N9"X*9&UI9&5C;V1E(&5X M96-U=&EO;B!U;G-U8V5S<V9U;&P@+2!C;VYT:6YU:6YG('=I=&AO=70@1$U) M(&EN9F\*1F]U;F0@8VAI<'-E="`B26YT96P@24-(-"U-(BP@96YA8FQI;F<@ M9FQA<V@@=W)I=&4N+BX@8VAI<'-E="!00TD@240@:7,@.#`X-CHR-&-C+"`* M0DE/4R!,;V-K($5N86)L93H@9&ES86)L960L($))3U,@5W)I=&4@16YA8FQE M.B!E;F%B;&5D+"!"24]37T-.5$P@:7,@,'@Q"D]++@I4:&ES(&-H:7!S970@ M<W5P<&]R=',@=&AE(&9O;&QO=VEN9R!P<F]T;V-O;',Z($972"X*4')O8FEN M9R!F;W(@04U$($%M,CE&,#$P02]"+"`Q,C@@2T(Z('-K:7!P960N"E!R;V)I M;F<@9F]R($%-1"!!;3(Y1C`P,BA.*4)"+"`R-38@2T(Z('-K:7!P960N"E!R M;V)I;F<@9F]R($%-1"!!;3(Y1C`P,BA.*4)4+"`R-38@2T(Z('-K:7!P960N M"E!R;V)I;F<@9F]R($%-1"!!;3(Y1C`Q-D0L(#(P-#@@2T(Z('-K:7!P960N M"E!R;V)I;F<@9F]R($%-1"!!;3(Y1C`T,$(L(#4Q,B!+0CH@<VMI<'!E9"X* M4')O8FEN9R!F;W(@04U$($%M,CE&,#@P0BP@,3`R-"!+0CH@<VMI<'!E9"X* M4')O8FEN9R!F;W(@04U$($%M,CE,5C`T,$(L(#4Q,B!+0CH@<VMI<'!E9"X* M4')O8FEN9R!F;W(@04U$($%M,CE,5C`X,4(L(#$P,C0@2T(Z('-K:7!P960N M"E!R;V)I;F<@9F]R($%-24,@03(U3#`U4%0L(#8T($M".B!S:VEP<&5D+@I0 M<F]B:6YG(&9O<B!!34E#($$R-4PP-5!5+"`V-"!+0CH@<VMI<'!E9"X*4')O M8FEN9R!F;W(@04U)0R!!,C5,,3!05"P@,3(X($M".B!S:VEP<&5D+@I0<F]B M:6YG(&9O<B!!34E#($$R-4PQ,%!5+"`Q,C@@2T(Z('-K:7!P960N"E!R;V)I M;F<@9F]R($%-24,@03(U3#(P4%0L(#(U-B!+0CH@<VMI<'!E9"X*4')O8FEN M9R!F;W(@04U)0R!!,C5,,C!052P@,C4V($M".B!S:VEP<&5D+@I0<F]B:6YG M(&9O<B!!34E#($$R-4PT,%!4+"`U,3(@2T(Z('-K:7!P960N"E!R;V)I;F<@ M9F]R($%-24,@03(U3#0P4%4L(#4Q,B!+0CH@<VMI<'!E9"X*4')O8FEN9R!F M;W((a)04U)0R!!,C5,.#!0+"`Q,#(T($M".B!S:VEP<&5D+@I0<F]B:6YG(&9O M<B!!34E#($$R-4PQ-E!4+"`R,#0X($M".B!S:VEP<&5D+@I0<F]B:6YG(&9O M<B!!34E#($$R-4PQ-E!5+"`R,#0X($M".B!S:VEP<&5D+@I0<F]B:6YG(&9O M<B!!34E#($$R-4PU,3(L(#8T($M".B!S:VEP<&5D+@I0<F]B:6YG(&9O<B!! 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[RFC] usb flashing protocol (was: cheapish and free usb spi flashing device)
by Stefan Tauner 18 May '11

18 May '11

hey! peter and i have started to discuss and lay out the details of a native usb flashing protocol. the WIP document can be found at http://titanpad.com/x8M9ZvNeMN we need to design abstract representations of a few things like erase blocks, instruction sequences for various operations etc. some of which are (probably) already implemented in flashrom in one form or another while others might be useful to have in there and have been discussed or at least thought through already by someone. so feel free to contribute please. ;) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[PATCH] Enable Write for SST25VF080B
by John Schmerge 18 May '11

18 May '11

The attached patch enables write support for the SST25VF080B chip. This was enabled in 0.9.3 and changed to 'PRE' since the 0.9.3 snapshot. Also attached is a log of 'flashrom -wV' showing proper operation on this chipset. This patch has been tested on a large deployment of computers (on the order of thousands of machines). Let me know if there is anything else that I need to provide to have this get commited. Thanks, John Signed-off-by: John Schmerge <jschmerge(a)gmail.com>

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