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[PATCH 04/11] use the max_data_read field of the new spi_programmer struct to simplify run_opcode.
by Stefan Tauner 27 May '11

27 May '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 41 +++++++++++++++++------------------------ 1 files changed, 17 insertions(+), 24 deletions(-) diff --git a/ichspi.c b/ichspi.c index 12727d1..dff6f32 100644 --- a/ichspi.c +++ b/ichspi.c @@ -913,37 +913,30 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, static int run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data) { + uint8_t maxlength = spi_programmer->max_data_read; + + if (spi_programmer->type == SPI_CONTROLLER_NONE) { + msg_perr("%s: unsupported chipset\n", __func__); + return -1; + } + + if (datalength > maxlength) { + msg_perr("%s: Internal command size error for " + "opcode 0x%02x, got datalength=%i, want <=%i\n", + __func__, op.opcode, datalength, maxlength); + return SPI_INVALID_LENGTH; + } + switch (spi_programmer->type) { case SPI_CONTROLLER_VIA: - if (datalength > 16) { - msg_perr("%s: Internal command size error for " - "opcode 0x%02x, got datalength=%i, want <=16\n", - __func__, op.opcode, datalength); - return SPI_INVALID_LENGTH; - } - return ich7_run_opcode(op, offset, datalength, data, 16); case SPI_CONTROLLER_ICH7: - if (datalength > 64) { - msg_perr("%s: Internal command size error for " - "opcode 0x%02x, got datalength=%i, want <=16\n", - __func__, op.opcode, datalength); - return SPI_INVALID_LENGTH; - } - return ich7_run_opcode(op, offset, datalength, data, 64); + return ich7_run_opcode(op, offset, datalength, data, maxlength); case SPI_CONTROLLER_ICH9: - if (datalength > 64) { - msg_perr("%s: Internal command size error for " - "opcode 0x%02x, got datalength=%i, want <=16\n", - __func__, op.opcode, datalength); - return SPI_INVALID_LENGTH; - } return ich9_run_opcode(op, offset, datalength, data); default: - msg_perr("%s: unsupported chipset\n", __func__); + /* If we ever get here, something really weird happened */ + return -1; } - - /* If we ever get here, something really weird happened */ - return -1; } static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, -- 1.7.1

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[PATCH 03/11] add macros and pretty printing for HSFS and HSFC
by Stefan Tauner 27 May '11

27 May '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++++++---------- 1 files changed, 62 insertions(+), 12 deletions(-) diff --git a/ichspi.c b/ichspi.c index 7e4a363..12727d1 100644 --- a/ichspi.c +++ b/ichspi.c @@ -43,6 +43,37 @@ #include "spi.h" /* ICH9 controller register definition */ +#define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ +#define HSFS_FDONE_OFF 0 /* 0: Flash Cycle Done */ +#define HSFS_FDONE (0x1 << HSFS_FDONE_OFF) +#define HSFS_FCERR_OFF 1 /* 1: Flash Cycle Error */ +#define HSFS_FCERR (0x1 << HSFS_FCERR_OFF) +#define HSFS_AEL_OFF 2 /* 2: Access Error Log */ +#define HSFS_AEL (0x1 << HSFS_AEL_OFF) +#define HSFS_BERASE_OFF 3 /* 3-4: Block/Sector Erase Size */ +#define HSFS_BERASE (0x1 << HSFS_BERASE_OFF) +#define HSFS_SCIP_OFF 5 /* 5: SPI Cycle In Progress */ +#define HSFS_SCIP (0x1 << HSFS_SCIP_OFF) + /* 6-12: reserved */ +#define HSFS_FDOPSS_OFF 13 /* 13: Flash Descriptor Override Pin-Strap Status */ +#define HSFS_FDOPSS (0x1 << HSFS_FDOPSS_OFF) +#define HSFS_FDV_OFF 14 /* 14: Flash Descriptor Valid */ +#define HSFS_FDV (0x1 << HSFS_FDV_OFF) +#define HSFS_FLOCKDN_OFF 15 /* 15: Flash Configuration Lock-Down */ +#define HSFS_FLOCKDN (0x1 << HSFS_FLOCKDN_OFF) + +#define ICH9_REG_HSFC 0x06 /* 16 Bits Hardware Sequencing Flash Control */ +#define HSFC_FGO_OFF 0 /* 0: Flash Cycle Go */ +#define HSFC_FGO (0x1 << HSFC_FGO_OFF) +#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ +#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) + /* 3-7: reserved */ +#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ +#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF) + /* 14: reserved */ +#define HSFC_SME_OFF 15 /* 15: SPI SMI# Enable */ +#define HSFC_SME (0x1 << HSFC_SME_OFF) + #define ICH9_REG_FADDR 0x08 /* 32 Bits */ #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ @@ -260,6 +291,28 @@ static void pretty_print_opcodes(OPCODES *ops) } #define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) +static void prettyprint_ich9_reg_hsfs(uint16_t reg_val) +{ + msg_pdbg("HSFS: "); + pprint_reg(HSFS, FDONE, reg_val, ", "); + pprint_reg(HSFS, FCERR, reg_val, ", "); + pprint_reg(HSFS, AEL, reg_val, ", "); + pprint_reg(HSFS, BERASE, reg_val, ", "); + pprint_reg(HSFS, SCIP, reg_val, ", "); + pprint_reg(HSFS, FDOPSS, reg_val, ", "); + pprint_reg(HSFS, FDV, reg_val, ", "); + pprint_reg(HSFS, FLOCKDN, reg_val, "\n"); +} + +static void prettyprint_ich9_reg_hsfc(uint16_t reg_val) +{ + msg_pdbg("HSFC: "); + pprint_reg(HSFC, FGO, reg_val, ", "); + pprint_reg(HSFC, FCYCLE, reg_val, ", "); + pprint_reg(HSFC, FDBC, reg_val, ", "); + pprint_reg(HSFC, SME, reg_val, "\n"); +} + static void prettyprint_ich9_reg_ssfs(uint32_t reg_val) { msg_pdbg("SSFS: "); @@ -1204,14 +1257,15 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, case SPI_CONTROLLER_ICH9: tmp2 = mmio_readw(ich_spibar + 4); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); - msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1)); - msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1); - msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1); - msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1); - msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3); - msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1); - msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1); - msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1); + prettyprint_ich9_reg_hsfs(tmp2); + if (tmp2 & (1 << 15)) { + msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); + ichspi_lock = 1; + } + + tmp2 = mmio_readw(ich_spibar + 6); + msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); + prettyprint_ich9_reg_hsfc(tmp2); tmp = mmio_readl(ich_spibar + 0x50); msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); @@ -1258,10 +1312,6 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, ichspi_bbar); msg_pdbg("0xB0: 0x%08x (FDOC)\n", mmio_readl(ich_spibar + 0xB0)); - if (tmp2 & (1 << 15)) { - msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); - ichspi_lock = 1; - } ich_init_opcodes(); break; default: -- 1.7.1

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[PATCH 02/11] add pretty printing functions for SSFS+SSFC and the OPCODE struct and use them
by Stefan Tauner 27 May '11

27 May '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 51 +++++++++++++++++++++++++++++++++++++++++++++------ 1 files changed, 45 insertions(+), 6 deletions(-) diff --git a/ichspi.c b/ichspi.c index 676b93a..7e4a363 100644 --- a/ichspi.c +++ b/ichspi.c @@ -243,6 +243,44 @@ static OPCODE POSSIBLE_OPCODES[] = { static OPCODES O_EXISTING = {}; +/* pretty printing functions */ +static void pretty_print_opcodes(OPCODES *ops) +{ + if(ops == NULL) + return; + + msg_pdbg("preop0=0x%02x, preop1=0x%02x\n", ops->preop[0], ops->preop[1]); + + OPCODE oc; + uint8_t i; + for (i = 0; i < 8; i++) { + oc = ops->opcode[i]; + msg_pdbg("op[%d]=0x%02x, %d, %d\n", i, oc.opcode, oc.spi_type, oc.atomic); + } +} + +#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) +static void prettyprint_ich9_reg_ssfs(uint32_t reg_val) +{ + msg_pdbg("SSFS: "); + pprint_reg(SSFS, SCIP, reg_val, ", "); + pprint_reg(SSFS, FDONE, reg_val, ", "); + pprint_reg(SSFS, FCERR, reg_val, ", "); + pprint_reg(SSFS, AEL, reg_val, "\n"); +} + +static void prettyprint_ich9_reg_ssfc(uint32_t reg_val) +{ + msg_pdbg("SSFC: "); + pprint_reg(SSFC, SCGO, reg_val, ", "); + pprint_reg(SSFC, ACS, reg_val, ", "); + pprint_reg(SSFC, SPOP, reg_val, ", "); + pprint_reg(SSFC, COP, reg_val, ", "); + pprint_reg(SSFC, DBC, reg_val, ", "); + pprint_reg(SSFC, SME, reg_val, ", "); + pprint_reg(SSFC, SCF, reg_val, "\n"); +} + static uint8_t lookup_spi_type(uint8_t opcode) { int a; @@ -519,6 +557,8 @@ static int ich_init_opcodes(void) } else { curopcodes = curopcodes_done; msg_pdbg("done\n"); + pretty_print_opcodes(curopcodes); + msg_pdbg("\n"); return 0; } } @@ -793,6 +833,8 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, temp32 = REGREAD32(ICH9_REG_SSFS); if (temp32 & SSFS_FCERR) { msg_perr("Transaction error!\n"); + prettyprint_ich9_reg_ssfs(temp32); + prettyprint_ich9_reg_ssfc(temp32); /* keep reserved bits */ temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; /* Clear the transaction error. */ @@ -1195,16 +1237,13 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, tmp = mmio_readl(ich_spibar + 0x90); msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff); - msg_pdbg("AEL %i, ", (tmp >> 4) & 1); - msg_pdbg("FCERR %i, ", (tmp >> 3) & 1); - msg_pdbg("FDONE %i, ", (tmp >> 2) & 1); - msg_pdbg("SCIP %i\n", (tmp >> 0) & 1); + prettyprint_ich9_reg_ssfs(tmp); if (tmp & (1 << 3)) { msg_pdbg("Clearing SSFS.FCERR\n"); mmio_writeb(1 << 3, ich_spibar + 0x90); } - tmp >>= 8; - msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp); + msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp >> 8); + prettyprint_ich9_reg_ssfc(tmp); msg_pdbg("0x94: 0x%04x (PREOP)\n", mmio_readw(ich_spibar + 0x94)); -- 1.7.1

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[PATCH 01/11] improve macros for SSFS and SSFC bits
by Stefan Tauner 27 May '11

27 May '11

- introduce offset macros and use them to (re)define the existing mask macros - add comments - rename SSFS_CDS to SSFS_FDONE (abbr. used in datasheet not in SSFS but HSFS) - use those for refactoring and magic number elemination. - following patch uses them for pretty printing Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 48 ++++++++++++++++++++++++++++++------------------ 1 files changed, 30 insertions(+), 18 deletions(-) diff --git a/ichspi.c b/ichspi.c index 299cbf3..676b93a 100644 --- a/ichspi.c +++ b/ichspi.c @@ -47,24 +47,36 @@ #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ #define ICH9_REG_SSFS 0x90 /* 08 Bits */ -#define SSFS_SCIP 0x00000001 -#define SSFS_CDS 0x00000004 -#define SSFS_FCERR 0x00000008 -#define SSFS_AEL 0x00000010 +#define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */ +#define SSFS_SCIP (0x1 << SSFS_SCIP_OFF) +#define SSFS_FDONE_OFF 2 /* Cycle Done Status */ +#define SSFS_FDONE (0x1 << SSFS_FDONE_OFF) +#define SSFS_FCERR_OFF 3 /* Flash Cycle Error */ +#define SSFS_FCERR (0x1 << SSFS_FCERR_OFF) +#define SSFS_AEL_OFF 4 /* Access Error Log */ +#define SSFS_AEL (0x1 << SSFS_AEL_OFF) /* The following bits are reserved in SSFS: 1,5-7. */ #define SSFS_RESERVED_MASK 0x000000e2 #define ICH9_REG_SSFC 0x91 /* 24 Bits */ -#define SSFC_SCGO 0x00000200 -#define SSFC_ACS 0x00000400 -#define SSFC_SPOP 0x00000800 -#define SSFC_COP 0x00001000 -#define SSFC_DBC 0x00010000 -#define SSFC_DS 0x00400000 -#define SSFC_SME 0x00800000 -#define SSFC_SCF 0x01000000 -#define SSFC_SCF_20MHZ 0x00000000 -#define SSFC_SCF_33MHZ 0x01000000 +#define SSFC_SCGO_OFF (1 + 8) /* 1: SPI Cycle Go */ +#define SSFC_SCGO (0x1 << SSFC_SCGO_OFF) +#define SSFC_ACS_OFF (2 + 8) /* 2: Atomic Cycle Sequence */ +#define SSFC_ACS (0x1 << SSFC_ACS_OFF) +#define SSFC_SPOP_OFF (3 + 8) /* 3: Sequence Prefix Opcode Pointer */ +#define SSFC_SPOP (0x1 << SSFC_SPOP_OFF) +#define SSFC_COP_OFF (4 + 8) /* 4-6: Cycle Opcode Pointer */ +#define SSFC_COP (0x7 << SSFC_COP_OFF) +#define SSFC_DBC_OFF (8 + 8) /* 8-13: Data Byte Count */ +#define SSFC_DBC (0x3f << SSFC_DBC_OFF) +#define SSFC_DS_OFF (14 + 8) /* 14: Data Cycle */ +#define SSFC_DS (0x1 << SSFC_DS_OFF) +#define SSFC_SME_OFF (15 + 8) /* 15: SPI SMI# Enable */ +#define SSFC_SME (0x1 << SSFC_SME_OFF) +#define SSFC_SCF_OFF (16 + 8) /* 16-18: SPI Cycle Frequency */ +#define SSFC_SCF (0x7 << SSFC_SCF_OFF) +#define SSFC_SCF_20MHZ 0x00000000 +#define SSFC_SCF_33MHZ 0x01000000 /* We combine SSFS and SSFC to one 32-bit word, * therefore SSFC bits are off by 8. * The following bits are reserved in SSFC: 23-19,7,0. */ @@ -709,8 +721,8 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, temp32 = REGREAD32(ICH9_REG_SSFS); /* Keep reserved bits only */ temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; - /* clear error status registers */ - temp32 |= (SSFS_CDS + SSFS_FCERR); + /* Clear cycle done and cycle error status registers */ + temp32 |= (SSFS_FDONE + SSFS_FCERR); REGWRITE32(ICH9_REG_SSFS, temp32); /* Use 20 MHz */ @@ -720,7 +732,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, if (datalength != 0) { uint32_t datatemp; temp32 |= SSFC_DS; - datatemp = ((uint32_t) ((datalength - 1) & 0x3f)) << (8 + 8); + datatemp = (uint32_t) (((datalength - 1) << SSFC_DBC_OFF) & SSFC_DBC); temp32 |= datatemp; } @@ -767,7 +779,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, REGWRITE32(ICH9_REG_SSFS, temp32); /* Wait for Cycle Done Status or Flash Cycle Error. */ - while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_CDS | SSFS_FCERR)) == 0) && + while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_FDONE | SSFS_FCERR)) == 0) && --timeout) { programmer_delay(10); } -- 1.7.1

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[PATCH 00/11] ichspi patches 4.0 (includes draft version of hw sequencing support)
by Stefan Tauner 27 May '11

27 May '11

hardware sequencing is almost complete (as in fully implemented, but not tested). we still need a solution for the const flashchips elements. besides hwseq there are also a few other new improvements and fixes of old patches. Stefan Tauner (11): improve macros for SSFS and SSFC bits add pretty printing functions for SSFS+SSFC and the OPCODE struct and use them add macros and pretty printing for HSFS and HSFC use the max_data_read field of the new spi_programmer struct to simplify run_opcode. warn if SMM BIOS Write Protection is detected in BIOS_CNTL add missing ICH9 register macros and use them to eliminate magic numbers add ICH/PCH flash descriptor decoding simplify ich_set_bbar add macros and pretty printing for "Host Lower Vendor Specific Component Capabilities" registers add FPB (Flash Partition Boundary) macros and init printing add support for Intel Hardware Sequencing Makefile | 2 +- chipdrivers.h | 6 + chipset_enable.c | 11 +- flashchips.c | 40 ++- ich_descriptors.c | 451 +++++++++++++++ ich_descriptors.h | 408 ++++++++++++++ ichspi.c | 646 ++++++++++++++++++---- programmer.h | 1 + util/ich_descriptors_tool/Makefile | 42 ++ util/ich_descriptors_tool/TODO | 5 + util/ich_descriptors_tool/ich_descriptors_tool.c | 226 ++++++++ 11 files changed, 1719 insertions(+), 119 deletions(-) create mode 100644 ich_descriptors.c create mode 100644 ich_descriptors.h create mode 100644 util/ich_descriptors_tool/Makefile create mode 100644 util/ich_descriptors_tool/TODO create mode 100644 util/ich_descriptors_tool/ich_descriptors_tool.c

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[commit] r1321 - trunk
by repository service 27 May '11

27 May '11

Author: stefanct Date: Sat May 28 04:37:14 2011 New Revision: 1321 URL: http://flashrom.org/trac/flashrom/changeset/1321 Log: small fixes - missing spaces in code and output - improved documentation/naming/output - missing line breaks in spi probing functions Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/flash.h trunk/flashrom.c trunk/ichspi.c trunk/print.c trunk/spi25.c Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Thu May 26 16:28:51 2011 (r1320) +++ trunk/flash.h Sat May 28 04:37:14 2011 (r1321) @@ -136,6 +136,8 @@ unsigned int size; /* Eraseblock size */ unsigned int count; /* Number of contiguous blocks with that size */ } eraseblocks[NUM_ERASEREGIONS]; + /* a block_erase function should try to erase one block of size + * 'blocklen' at address 'blockaddr' and return 0 on success. */ int (*block_erase) (struct flashchip *flash, unsigned int blockaddr, unsigned int blocklen); } block_erasers[NUM_ERASEFUNCTIONS]; Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Thu May 26 16:28:51 2011 (r1320) +++ trunk/flashrom.c Sat May 28 04:37:14 2011 (r1321) @@ -1312,7 +1312,7 @@ goto out_free; } - ret = write_buf_to_file(buf, flash->total_size * 1024, filename); + ret = write_buf_to_file(buf, size, filename); out_free: free(buf); msg_cinfo("%s.\n", ret ? "FAILED" : "done"); @@ -1489,13 +1489,13 @@ if (!eraser.block_erase && eraser.eraseblocks[0].count) { if (log) msg_cdbg("eraseblock layout is known, but matching " - "block erase function is not implemented. "); + "block erase function is not implemented. "); return 1; } if (eraser.block_erase && !eraser.eraseblocks[0].count) { if (log) msg_cdbg("block erase function found, but " - "eraseblock layout is not defined. "); + "eraseblock layout is not defined. "); return 1; } return 0; Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Thu May 26 16:28:51 2011 (r1320) +++ trunk/ichspi.c Sat May 28 04:37:14 2011 (r1321) @@ -159,9 +159,9 @@ return mmio_readb(ich_spibar + X); } -#define REGWRITE32(X,Y) mmio_writel(Y, ich_spibar+X) -#define REGWRITE16(X,Y) mmio_writew(Y, ich_spibar+X) -#define REGWRITE8(X,Y) mmio_writeb(Y, ich_spibar+X) +#define REGWRITE32(off,val) mmio_writel(val, ich_spibar+off) +#define REGWRITE16(off,val) mmio_writew(val, ich_spibar+off) +#define REGWRITE8(off,val) mmio_writeb(val, ich_spibar+off) /* Common SPI functions */ static int find_opcode(OPCODES *op, uint8_t opcode); @@ -856,7 +856,8 @@ if (!ichspi_lock) opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt); if (opcode_index == -1) { - msg_pdbg("Invalid OPCODE 0x%02x\n", cmd); + msg_pdbg("Invalid OPCODE 0x%02x, will not execute.\n", + cmd); return SPI_INVALID_OPCODE; } } Modified: trunk/print.c ============================================================================== --- trunk/print.c Thu May 26 16:28:51 2011 (r1320) +++ trunk/print.c Sat May 28 04:37:14 2011 (r1321) @@ -43,18 +43,18 @@ ret = strcat_realloc(ret, "Non-SPI,"); } else { if (bustype & CHIP_BUSTYPE_PARALLEL) - ret = strcat_realloc(ret, "Parallel,"); + ret = strcat_realloc(ret, "Parallel, "); if (bustype & CHIP_BUSTYPE_LPC) - ret = strcat_realloc(ret, "LPC,"); + ret = strcat_realloc(ret, "LPC, "); if (bustype & CHIP_BUSTYPE_FWH) - ret = strcat_realloc(ret, "FWH,"); + ret = strcat_realloc(ret, "FWH, "); if (bustype & CHIP_BUSTYPE_SPI) - ret = strcat_realloc(ret, "SPI,"); + ret = strcat_realloc(ret, "SPI, "); if (bustype == CHIP_BUSTYPE_NONE) - ret = strcat_realloc(ret, "None,"); + ret = strcat_realloc(ret, "None, "); } /* Kill last comma. */ - ret[strlen(ret) - 1] = '\0'; + ret[strlen(ret) - 2] = '\0'; ret = realloc(ret, strlen(ret) + 1); return ret; } Modified: trunk/spi25.c ============================================================================== --- trunk/spi25.c Thu May 26 16:28:51 2011 (r1320) +++ trunk/spi25.c Sat May 28 04:37:14 2011 (r1321) @@ -119,8 +119,10 @@ uint32_t id1; uint32_t id2; - if (spi_rdid(readarr, bytes)) + if (spi_rdid(readarr, bytes)) { + msg_cdbg("\n"); return 0; + } if (!oddparity(readarr[0])) msg_cdbg("RDID byte 0 parity violation. "); @@ -198,8 +200,10 @@ unsigned char readarr[JEDEC_REMS_INSIZE]; uint32_t id1, id2; - if (spi_rems(readarr)) + if (spi_rems(readarr)) { + msg_cdbg("\n"); return 0; + } id1 = readarr[0]; id2 = readarr[1]; @@ -254,15 +258,19 @@ return 0; } - if (spi_res(readarr, 1)) + if (spi_res(readarr, 1)) { + msg_cdbg("\n"); return 0; + } id2 = readarr[0]; msg_cdbg("%s: id 0x%x\n", __func__, id2); - if (id2 != flash->model_id) + if (id2 != flash->model_id) { + msg_cdbg("\n"); return 0; + } /* Print the status register to tell the * user about possible write protection. @@ -276,8 +284,10 @@ unsigned char readarr[2]; uint32_t id1, id2; - if (spi_res(readarr, 2)) + if (spi_res(readarr, 2)) { + msg_cdbg("\n"); return 0; + } id1 = readarr[0]; id2 = readarr[1];

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Hardware Sequencing for ichspi.c
by Stefan Tauner 27 May '11

27 May '11

Hello list! i am researching hardware sequencing at the moment and i am thinking about how it should be implemented and integrated. == INTRODUCTION == newer intel chipsets allow two modes of operation when talking to spi flashes: software and hw sequencing. in sw sequencing the software needs to provide the spi opcodes (or use the predefined ones if applicable) in a table that it can later invoke. to do so the id of the opcode, data lengths and data content is written to some ich registers and a bit is flipped to trigger the execution. the opcodes can be reprogrammed by the software at any time (which allows pretty much everything - as long as there is no locking/protection activated, but that's another story). sw sequencing is already fully supported by flashrom. in hw sequencing the list of opcodes is fixed (with the exception of the erase command). this does of course only work if the flash chip adheres to strict specifications which are documented in the datasheets (erase sector size, write enable procedures/status register semantics etc). if ME or GbE firmware should be supported then the restrictions are even more severe (and HW seq is required for those features). another requirement for hw seq is that the flash must contain a valid descriptor section. in that data structure the layout of the flash contents it described among other things. this way the ME and the GbE processors can find their firmware at startup (my guess). the descriptors also define the locking of the flash regions we had so much trouble in the past. it is also possible to use more than one flash chip to store bios and firmware information with descriptors. this is transparent to the software when using hw seq (and sw seq is not able to speak to the second chip/toggle the second CS at all afaics). == DETAILS == requirements for hw seq (besides the reqs for sw seq like unlocked regions and the properties mentioned in "SPI Based BIOS Requirements" in the data sheets etc.): - a compatible flash device as defined in "Hardware Sequencing Requirements" in intel's ICH/PCH datasheets. that is not easy to check right now, but we probably do not care anyway (or is anyone interested in using ICHs as general purpose flashing devices? actually this would be possible with the second chip select and hardware sequencing... :). - HSFS.FDV=1 i.e. a valid flash descriptor signature is found at the bottom of the flash (some steppings seem to have an offset of 0x10, but that's not our problem when we are using HSFS.FDV). limitations of hw seq: - only read, write and erase operations can be committed. this has lots of implications for an integration into flashrom; see IMPLEMENTATION. other interesting bits: - there is support for shadowing two flash chips into one contiguous address space. the use of multiple flash chips can be checked in flash descriptor bit FLMAP0.NC. there is limited support for chips with different attributes: different sizes are no problem (defined in fd FCBA). other attributes can be assigned to two parts of the SPI address space by the lower and upper VSCC (Host Lower/Upper Vendor Specific Component Capabilities Register). the border between them is defined by register FPB.FPBA. this can be used for flash chips that differ for example in the erase opcode. NB: this also allows the use of a single flash chip with different erase granularities in different address spaces. the two attribute registers (LVSCC and UVSCC) can be locked independently from each other and from the FLOCKDN bit. - there is a table of jedec ids and the (erase/write (enable)) abilities of associated flash chips in the flash descriptor (unreachable via ICH/PCH registers). the ability words have the same semantic as the VSCC mentioned above. quoting the (confidential) ibex peak SPI programming guide AN: "The Intel® ME VSCC Table defines how the Intel® ME will communicate with the installed SPI flash. This table is defined in the descriptor and is the responsibility of who puts together the NVM image. LVSCC and/or UVSCC registers are defined in memory space and must be set by BIOS. This table must define every flash part that is intended to be used." == IMPLEMENTATION == the very simple access model of hw seq is too simple for flashrom, or put in another way: flashrom is too sophisticated to integrate hw seq easily. in hw seq the target device is not a single flashchip from the flashchips table, but a contiguous address space which we can access by just setting an address, filling in the data (like in sw seq) and then committing the command by setting the read/write or erase mode and the go-flag in HSFC. i have identified the following problems and am asking for possible solutions: - "dynamic" target device. we dont have one single flash chip, but only certain attributes available (total size, erase block sizes for currently up to two address spaces). there are many combinations of flash chips that could be wired up on boards. theoretically we could define them all and use a customized probe function to "detect" them, but that's of course(?) not the way to go. the main problem here is the constant flashrom array. an alternative may be a const array of pointers to (mostly const) flashchips, where one of them is a non-const generic ich hw seq device with a custom probe function that sets the important fields of that chip. dunno if that would work (i.e. compile to mostly text section data). maybe we could probably live with a const generic device anyway, because we can read the flash size anytime via the ich registers. but there are problems with the generic flashrom methods: e.g. they check for matching file and flash sizes. - different programmer function semantics. there are no opcodes to deal with, so the existing spi functions in ichspi.c are not really useful. i think the best way would be to add a new programmer for this. since we only allow one spi programmer atm(?), the registering of the programmer in ich_init_spi would have to be changed. how would we want to specify if hw seq should be used? there is no way to get command line arguments in there (yet). another way would be to deduce that just from the register contents: - if the opcodes are locked and dont contain enough opcodes to succeed, use hw seq. this is probably not so easy to check, so it would be easier to just do the following: - if the opcodes are locked down, use hw seq - also if there are (>=) 2 flash components, we have to use hw seq. - another way may be to use sw seq and retry with sw seq when we fail, but that's also complicated and i would love to avoid that at least for the near future. i may have missed a thing or a dozen, but please dont shoot me my brain is already wounded from digging through all that information ;) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 1

Intel SandyBridge serie 6 chipsets support
by Mohammed-Amine.Rebai＠bull.net 27 May '11

27 May '11

Dear Flahsrom representant, I am a Bios engineer at BULL, a major european server and supercomputer company «www.bull.com » . First of all, I would like to thank you for the great job you are doing, we use your utility a lot. I would like to know if you are planning to support the Bios SPI flash flashing on the Intel SandyBridge architecture, especially the Intel 6 series chipset/C200/Patsburg platform controller hub? Thanks in advance for your answer. Best regards +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | Amine REBAI | BIOS engineer | Bull SAS, Architect of an Open World(TM) | BP 68 - Rue Jean Jaures - 78340 Les Clayes sous Bois (France) | Email : MOHAMMED-AMINE.REBAI(a)BULL.NET | Tel : +33 (0)1 30 80 31 38 | | R&D/Server_Design_Development - http://www.bull.com/hpc | - http://www.bull.com/novascale | | Ce message contient des informations confidentielles, couvertes par | le secret professionnel ou réservées exclusivement à leur destinataire. | Toute lecture, utilisation, diffusion ou divulgation sans autorisation | expresse est rigoureusement interdite. | Si vous n'en êtes pas le destinataire, merci de prendre contact avec | l'expéditeur et de détruire ce message. | | This e-mail contains material that is confidential for the sole use of | the intended recipient. Any review, reliance or distribution by others | or forwarding without express permission is strictly prohibited. | If you are not the intended recipient, please contact the sender and | delete all copies. +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

1 0

Requested Verbose Output
by Lee Daugherty 26 May '11

26 May '11

This is the output of the BIOS found on the MSI MS-7309.

1 0

[commit] r1320 - trunk
by repository service 26 May '11

26 May '11

Author: stefanct Date: Thu May 26 16:28:51 2011 New Revision: 1320 URL: http://flashrom.org/trac/flashrom/changeset/1320 Log: add a bunch of new/tested motherboards, board enables and flash chips tested motherboards: - MSI MS-7599 (870-C45) http://www.flashrom.org/pipermail/flashrom/2011-May/006420.html - Gigabyte GA-P55A-UD4 (rev 1.0) http://www.flashrom.org/pipermail/flashrom/2011-May/006415.html - Supermicro X8DTU-F http://www.flashrom.org/pipermail/flashrom/2011-May/006329.html - Supermicro X8STi http://www.flashrom.org/pipermail/flashrom/2011-May/006436.html tested board enable: - abit NF-M2 nView success report (without a log though): http://www.flashrom.org/pipermail/flashrom/2011-April/006167.html tested flash chips: - ST M50FW080 (+EW) http://www.flashrom.org/pipermail/flashrom/2011-May/006409.html - ST M25P32 (+EW) http://www.flashrom.org/pipermail/flashrom/2011-May/006398.html - Winbond W25x64 (+P) http://www.flashrom.org/pipermail/flashrom/2011-March/006012.html - Winbond W39V040FA (+W) http://www.flashrom.org/pipermail/flashrom/2010-December/005642.html new flash chip - Winbond W25Q128 http://www.flashrom.org/pipermail/flashrom/2011-April/006309.html W25Q128 is: Signed-off-by: Antony Rheneus <rheneus.paul(a)gmail.com> everything else is: Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/flashchips.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Thu May 26 15:30:51 2011 (r1319) +++ trunk/board_enable.c Thu May 26 16:28:51 2011 (r1320) @@ -1959,7 +1959,7 @@ {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, P3, "abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, P3, "abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower}, {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, P3, "abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise}, - {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0240, 0x10de, 0x0222, NULL, NULL, NULL, P3, "abit", "NF-M2 nView", 0, NT, nvidia_mcp_gpio4_lower}, + {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0240, 0x10de, 0x0222, NULL, NULL, NULL, P3, "abit", "NF-M2 nView", 0, OK, nvidia_mcp_gpio4_lower}, {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, "(VA6)$", NULL, NULL, P3, "abit", "VA6", 0, OK, via_apollo_gpo4_lower}, {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", P3, "abit", "VT6X4", 0, OK, via_apollo_gpo4_lower}, {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, P3, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Thu May 26 15:30:51 2011 (r1319) +++ trunk/flashchips.c Thu May 26 16:28:51 2011 (r1320) @@ -6467,7 +6467,7 @@ .model_id = ST_M25P32, .total_size = 4096, .page_size = 256, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -7064,7 +7064,7 @@ .total_size = 1024, .page_size = 64 * 1024, .feature_bits = FEATURE_REGISTERMAP, - .tested = TEST_OK_PR, + .tested = TEST_OK_PREW, .probe = probe_82802ab, .probe_timing = TIMING_IGNORED, /* routine don't use probe_timing (82802ab.c) */ .block_erasers = @@ -7525,6 +7525,42 @@ { .vendor = "Winbond", + .name = "W25Q128", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q128, + .total_size = 16384, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PROBE, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "Winbond", .name = "W25x10", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = WINBOND_NEX_ID, @@ -7724,7 +7760,7 @@ .total_size = 8192, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PROBE, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = @@ -7963,9 +7999,9 @@ .total_size = 512, .page_size = 64 * 1024, .feature_bits = FEATURE_REGISTERMAP | FEATURE_EITHER_RESET, - .tested = TEST_OK_PRE, + .tested = TEST_OK_PREW, .probe = probe_jedec, - .probe_timing = 10, + .probe_timing = 10, .block_erasers = { { Modified: trunk/print.c ============================================================================== --- trunk/print.c Thu May 26 15:30:51 2011 (r1319) +++ trunk/print.c Thu May 26 16:28:51 2011 (r1320) @@ -535,6 +535,7 @@ B("GIGABYTE", "GA-MA790FX-DQ6", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2690", NULL), B("GIGABYTE", "GA-MA790GP-DS4H", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2887", NULL), B("GIGABYTE", "GA-MA790XT-UD4P (rev. 1.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3010", NULL), + B("GIGABYTE", "GA-P55A-UD4 (rev. 1.0 (and 2.0?))", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3436", NULL), B("HP", "e-Vectra P2706T", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Home.jsp?lang=en&cc=us&pro…", NULL), B("HP", "ProLiant DL145 G3", 1, "http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c008…", NULL), B("HP", "ProLiant DL165 G6", 1, "http://h10010.www1.hp.com/wwpc/us/en/sm/WF05a/15351-15351-3328412-241644-33…", NULL), @@ -587,6 +588,7 @@ B("MSI", "MS-7368 (K9AG Neo2-Digital)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1241", NULL), B("MSI", "MS-7376 (K9A2 Platinum)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1332", NULL), B("MSI", "MS-7596 (785GM-E51)", 1, "http://eu.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1866", NULL), + B("MSI", "MS-7599 (870-C45)", 1, "http://www.msi.com/product/mb/870-C45.html", NULL), B("MSI", "MS-7640 (890FXA-GD70)",1, "http://www.msi.com/product/mb/890FXA-GD70.html", "Reported by \"Linux User #330250\" http://flashrom.org/pipermail/flashrom/2011-March/006072.html"), B("MSI", "MS-7642 (890GXM-G65)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=2012", NULL), B("NEC", "PowerMate 2000", 1, "http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/", NULL), @@ -617,6 +619,8 @@ B("Supermicro", "H8QC8", 1, "http://www.supermicro.com/Aplus/motherboard/Opteron/nforce/H8QC8.cfm", NULL), B("Supermicro", "X8DTH-6F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTH-6F.cfm", NULL), B("Supermicro", "X8DTT-F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTT-F.cfm", NULL), + B("Supermicro", "X8DTU-F", 1, "http://www.supermicro.com/products/motherboard/QPI/5500/X8DTU-F.cfm", NULL), + B("Supermicro", "X8STi", 1, "http://www.supermicro.com/products/motherboard/Xeon3000/X58/X8STi.cfm", NULL), B("T-Online", "S-100", 1, "http://wiki.freifunk-hannover.de/T-Online_S_100", NULL), B("Tekram", "P6Pro-A5", 1, "http://www.motherboard.cz/mb/tekram/P6Pro-A5.htm", NULL), B("Termtek", "TK-3370 (Rev:2.5B)", 1, NULL, NULL),

1 0

[PATCH] ichspi: fix unused FREG detection
by Joshua Roys 26 May '11

26 May '11

Hello, This patch will fix incorrect output from my original patch: 0x64: 0x00000fff (FREG4: Platform Data) 0x00fff000-0x00000fff is locked Signed-off-by: Joshua Roys <roysjosh(a)gmail.com> Thanks, Josh

2 3

[commit] r1319 - trunk
by repository service 26 May '11

26 May '11

Author: stefanct Date: Thu May 26 15:30:51 2011 New Revision: 1319 URL: http://flashrom.org/trac/flashrom/changeset/1319 Log: ichspi: fix detection of unused regions Signed-off-by: Joshua Roys <roysjosh(a)gmail.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Thu May 26 03:35:19 2011 (r1318) +++ trunk/ichspi.c Thu May 26 15:30:51 2011 (r1319) @@ -1045,7 +1045,7 @@ base = ICH_FREG_BASE(freg); limit = ICH_FREG_LIMIT(freg); - if (base == 0x1fff && limit == 0) { + if (base > limit) { /* this FREG is disabled */ msg_pdbg("%s region is unused.\n", region_names[i]); return;

1 0

flashrom -v
by Matthew Legitt 26 May '11

26 May '11

flashrom v0.9.3-r1205 on Linux 2.6.18-238.9.1.el5 (x86_64), built with libpci 3.1.7, GCC 4.1.2 20080704 (Red Hat 4.1.2-50), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 790M loops per second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 1037 us, 10000 myus = 9973 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Acer" DMI string system-product-name: "Aspire R1600" DMI string system-version: " " DMI string baseboard-manufacturer: "Acer" DMI string baseboard-product-name: "FMCP7A-ION" DMI string baseboard-version: " " DMI string chassis-type: "Desktop" Found chipset "NVIDIA MCP79", enabling flash write... chipset PCI ID is 10de:0aad, This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Flash bus type is SPI Found SMBus device 10de:0aa2 at 00:03:2 MCP SPI BAR is at 0xfae80000 SPI control is 0xc052, req=0, gnt=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: SPI. Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for AMIC A25L05PT, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L05PU, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PT, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PU, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PT, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PU, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PT, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PU, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L80P, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PT, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PU, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L020, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L080, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L016, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L032, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25LQ032, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: skipped. Probing for Atmel AT25DF021, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF041A, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321A, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF641, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DQ161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25F512B, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF041, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26F004, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB011D, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB021D, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB041D, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB081D, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB161D, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321C, 4224 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321D, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB642D, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F020, 256 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for Bright BM29F040, 512 KB: skipped. Probing for EMST F49B002UA, 256 KB: skipped. Probing for EMST F25L008A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05T, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10T, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20T, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40T, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80T, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16T, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32T, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64T, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25D16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F05, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN29F010, 128 KB: skipped. Probing for Eon EN29F002(A)(N)B, 256 KB: skipped. Probing for Eon EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Hyundai HY29F002T, 256 KB: skipped. Probing for Hyundai HY29F002B, 256 KB: skipped. Probing for Hyundai HY29F040A, 512 KB: skipped. Probing for Intel 28F001BN/BX-B, 128 KB: skipped. Probing for Intel 28F001BN/BX-T, 128 KB: skipped. Probing for Intel 28F002BC/BL/BV/BX-T, 256 KB: skipped. Probing for Intel 28F008S3/S5/SC, 512 KB: skipped. Probing for Intel 28F004B5/BE/BV/BX-B, 512 KB: skipped. Probing for Intel 28F004B5/BE/BV/BX-T, 512 KB: skipped. Probing for Intel 28F400BV/BX/CE/CV-B, 512 KB: skipped. Probing for Intel 28F400BV/BX/CE/CV-T, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: skipped. Probing for Intel 82802AC, 1024 KB: skipped. Probing for Macronix MX25L512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1005, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L2005, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L4005, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found chip "Macronix MX25L8005" (1024 KB, SPI) at physical address 0xfff00000. Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635D, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635E, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3205, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3235D, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L6405, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L12805, 16384 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29F040, 512 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for MoselVitelic V29C51000B, 64 KB: skipped. Probing for MoselVitelic V29C51000T, 64 KB: skipped. Probing for MoselVitelic V29C51400B, 512 KB: skipped. Probing for MoselVitelic V29C51400T, 512 KB: skipped. Probing for MoselVitelic V29LC51000, 64 KB: skipped. Probing for MoselVitelic V29LC51001, 128 KB: skipped. Probing for MoselVitelic V29LC51002, 256 KB: skipped. Probing for Numonyx M25PE10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV010, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV016B, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV020, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV040, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV080B, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV512, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: skipped. Probing for PMC Pm49FL004, 512 KB: skipped. Probing for Sanyo LF25FW203A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sharp LHF00L04, 1024 KB: skipped. Probing for Spansion S25FL008A, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL016A, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF016B, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF032B, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF064C, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF040.REMS, 512 KB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF040B, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25LF040A.RES, 512 KB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25VF040B.REMS, 512 KB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF080B, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: skipped. Probing for SST SST49LF003A/B, 384 KB: skipped. Probing for SST SST49LF004A/B, 512 KB: skipped. Probing for SST SST49LF004C, 512 KB: skipped. Probing for SST SST49LF008A, 1024 KB: skipped. Probing for SST SST49LF008C, 1024 KB: skipped. Probing for SST SST49LF016C, 2048 KB: skipped. Probing for SST SST49LF020, 256 KB: skipped. Probing for SST SST49LF020A, 256 KB: skipped. Probing for SST SST49LF040, 512 KB: skipped. Probing for SST SST49LF040B, 512 KB: skipped. Probing for SST SST49LF080A, 1024 KB: skipped. Probing for SST SST49LF160C, 2048 KB: skipped. Probing for ST M25P05-A, 64 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P05.RES, 64 KB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P10.RES, 128 KB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40-old, 512 KB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P128, 16384 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BB, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: skipped. Probing for ST M50FLW040B, 512 KB: skipped. Probing for ST M50FLW080A, 1024 KB: skipped. Probing for ST M50FLW080B, 1024 KB: skipped. Probing for ST M50FW002, 256 KB: skipped. Probing for ST M50FW016, 2048 KB: skipped. Probing for ST M50FW040, 512 KB: skipped. Probing for ST M50FW080, 1024 KB: skipped. Probing for ST M50LPW116, 2048 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x10, 128 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x20, 256 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x40, 512 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x80, 1024 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x16, 2048 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x32, 4096 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25x64, 8192 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped. Probing for Winbond W29C020(C)/W29C022, 256 KB: skipped. Probing for Winbond W29C040/P, 512 KB: skipped. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: skipped. Probing for Winbond W39V040(F)B, 512 KB: skipped. Probing for Winbond W39V040(F)C, 512 KB: skipped. Probing for Winbond W39V040FA, 512 KB: skipped. Probing for Winbond W39V080A, 1024 KB: skipped. Probing for Winbond W49F002U/N, 256 KB: skipped. Probing for Winbond W49F020, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: skipped. Probing for Winbond W49V002FA, 256 KB: skipped. Probing for Winbond W39V080FA, 1024 KB: skipped. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Probing for AMIC unknown AMIC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel unknown Atmel SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon unknown Eon SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix unknown Macronix SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC unknown PMC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST unknown SST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST unknown ST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sanyo unknown Sanyo SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (RDID), 0 KB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (REMS), 0 KB: probe_spi_rems: id1 0xc2, id2 0x13 No operations were specified. If I discombobulate the matter replicator attached to the proton-magnetic accelerator while the neutrino anti-matter graviton at Warp 9, synthesizes the synergy of the combined spectral waves and the space-time-continuum monitor reaches critical mass while the boson particles are firing and gravity reversal generators are at peak speed, will this disintegrate the black hole particle shield and make my data invisible?

1 0

Re: [flashrom] [PATCH] eliminate magic numbers indicating maximum column sizes in print_supported_chipsets and print_supported_boards_helper
by Carl-Daniel Hailfinger 25 May '11

25 May '11

Am 24.05.2011 02:21 schrieb Stefan Tauner: > without this the magic numbers need to be kept in sync with the maximum length of the > strings printed in the corresponding column. if not an overflow and a nasty ' '-storm occurs > on executing flashrom -L. > > Signed-off-by: Stefan Tauner<stefan.tauner(a)student.tuwien.ac.at> > --- > > after a short discussion with carldani i have removed the assert stuff and > do some inferior array checking in selfcheck. IMHO assert should be avoided because it is the equivalent of crashing (no cleanup, no graceful error handling). Assert is OK if memory corruption or a similar problem has been detected and you just want to abort as quickly as possible without any cleanup to inimize further damage. > we only have _extern_ > references to the tables to sizeof does not work. we could add a "getter" > for the sizes of the array or bring the tables into view to improve this... > but i dont think it's worth it. > > flashrom.c | 22 +++++++++++++ > print.c | 96 ++++++++++++++++++++++++++++++++++++++------------------- > programmer.h | 8 ++-- > 3 files changed, 90 insertions(+), 36 deletions(-) > > diff --git a/flashrom.c b/flashrom.c > index 46c9ecd..821d745 100644 > --- a/flashrom.c > +++ b/flashrom.c > @@ -1709,6 +1709,28 @@ int selfcheck(void) > msg_gerr("Programmer table miscompilation!\n"); > ret = 1; > } > + /* It would be favorable if we could also check for correct terminaion > + * of the follwing arrays, but we don't know their size in here... */ > + if (flashchips == NULL || flashchips[0].vendor == NULL) { > + msg_gerr("Flashchips table miscompilation!\n"); > + ret = 1; > + } > The code below is internal-only. Please make sure it still compiles with # make CONFIG_INTERNAL=no That usually means wrapping in #if CONFIG_INTERNAL == 1 > + if (chipset_enables == NULL || chipset_enables[0].vendor_name == NULL) { > + msg_gerr("Chipset enables table miscompilation!\n"); > + ret = 1; > + } > chipset_enables[0].vendor_name==NULL is a valid case if someone wants to run a minimal flashrom on a machine which does not need a chipset enable. > + if (board_pciid_enables == NULL || board_pciid_enables[0].vendor_name == NULL) { > + msg_gerr("Board enables table miscompilation!\n"); > + ret = 1; > + } > board_pciid_enables[0].vendor_name == NULL is a valid case for minimal flashrom on a board which does not need a board enable. > + if (boards_known == NULL || boards_known[0].vendor == NULL) { > + msg_gerr("Known boards table miscompilation!\n"); > + ret = 1; > + } > Same here if someone does not care about --list-supported output at all (e.g. in embedded usage). > + if (laptops_known == NULL || laptops_known[0].vendor == NULL) { > + msg_gerr("Known laptops table miscompilation!\n"); > + ret = 1; > + } > Dito. The tests for NULL pointers of chipset_enables etc. make a lot of sense, but the size checks only make sense if you know the array size from elsewhere and if you want to check that the array size matches the size an array walker (loop until ->somemember==NULL) would see. That means the selfcheck function would have to live in the same file as the array or you use another global variable which holds sizeof(array). Put #endif here. > for (flash = flashchips; flash&& flash->name; flash++) > if (selfcheck_eraseblocks(flash)) > ret = 1; > diff --git a/print.c b/print.c > index e84a417..b0f8247 100644 > --- a/print.c > +++ b/print.c > @@ -77,7 +77,8 @@ static int digits(int n) > static void print_supported_chips(void) > { > int okcol = 0, pos = 0, i, chipcount = 0; > - int maxchiplen = 0, maxvendorlen = 0; > + int maxvendorlen = strlen("Vendor") + 1; > + int maxchiplen = strlen("Device") + 1; > const struct flashchip *f; > > for (f = flashchips; f->name != NULL; f++) { > @@ -158,63 +159,94 @@ static void print_supported_chips(void) > #if CONFIG_INTERNAL == 1 > static void print_supported_chipsets(void) > { > - int i, j, chipsetcount = 0; > + int i, chipsetcount = 0; > const struct penable *c = chipset_enables; > + int maxvendorlen = strlen("Vendor") + 1; > + int maxchipsetlen = strlen("Chipset") + 1; > > - for (i = 0; c[i].vendor_name != NULL; i++) > + for (c = chipset_enables; c->vendor_name != NULL; c++) { > chipsetcount++; > + maxvendorlen = max(maxvendorlen, strlen(c->vendor_name)); > + maxchipsetlen = max(maxchipsetlen, strlen(c->device_name)); > + } > + maxvendorlen++; > + maxchipsetlen++; > + > + printf("\nSupported chipsets (total: %d):\n\n", chipsetcount); > Not your fault, but I think the \n at the beginning here is really ugly. It should live in the caller. > + > + printf("Vendor"); > + for (i = strlen("Vendor"); i< maxvendorlen; i++) > + printf(" "); > + > + printf("Chipset"); > + for (i = strlen("Chipset"); i< maxchipsetlen; i++) > + printf(" "); > > - printf("\nSupported chipsets (total: %d):\n\nVendor: " > - "Chipset: PCI IDs:\n\n", chipsetcount); > + printf("PCI IDs State\n\n"); > > - for (i = 0; c[i].vendor_name != NULL; i++) { > - printf("%s", c[i].vendor_name); > - for (j = 0; j< 25 - strlen(c[i].vendor_name); j++) > + for (c = chipset_enables; c->vendor_name != NULL; c++) { > + printf("%s", c->vendor_name); > + for (i = 0; i< maxvendorlen - strlen(c->vendor_name); i++) > printf(" "); > - printf("%s", c[i].device_name); > - for (j = 0; j< 25 - strlen(c[i].device_name); j++) > + printf("%s", c->device_name); > + for (i = 0; i< maxchipsetlen - strlen(c->device_name); i++) > printf(" "); > - printf("%04x:%04x%s\n", c[i].vendor_id, c[i].device_id, > - (c[i].status == OK) ? "" : " (untested)"); > + printf("%04x:%04x%s\n", c->vendor_id, c->device_id, > + (c->status == OK) ? "" : " (untested)"); > } > } > > static void print_supported_boards_helper(const struct board_info *boards, > const char *devicetype) > { > - int i, j, boardcount_good = 0, boardcount_bad = 0; > - const struct board_pciid_enable *b = board_pciid_enables; > - > - for (i = 0; boards[i].vendor != NULL; i++) { > - if (boards[i].working) > + int i, boardcount_good = 0, boardcount_bad = 0; > + const struct board_pciid_enable *e = board_pciid_enables; > + const struct board_info *b = boards; > + int maxvendorlen = strlen("Vendor") + 1; > + int maxboardlen = strlen("Board") + 1; > + > + for (b = boards; b->vendor != NULL; b++) { > + maxvendorlen = max(maxvendorlen, strlen(b->vendor)); > + maxboardlen = max(maxboardlen, strlen(b->name)); > + if (b->working) > boardcount_good++; > else > boardcount_bad++; > } > + maxvendorlen++; > + maxboardlen++; > + > + printf("\nKnown %s (good: %d, bad: %d):\n\n", > + devicetype, boardcount_good, boardcount_bad); > Not your fault, but I think the \n at the beginning here is really ugly. It should live in the caller. > + > + printf("Vendor"); > + for (i = strlen("Vendor"); i< maxvendorlen; i++) > + printf(" "); > + > + printf("Board"); > + for (i = strlen("Board"); i< maxboardlen; i++) > + printf(" "); > > - printf("\nKnown %s (good: %d, bad: %d):" > - "\n\nVendor: Board: " > - "Status: Required option:" > - "\n\n", devicetype, boardcount_good, boardcount_bad); > + printf("Status Required option\n\n"); > > - for (i = 0; boards[i].vendor != NULL; i++) { > - printf("%s", boards[i].vendor); > - for (j = 0; j< 25 - strlen(boards[i].vendor); j++) > + for (b = boards; b->vendor != NULL; b++) { > + printf("%s", b->vendor); > + for (i = 0; i< maxvendorlen - strlen(b->vendor); i++) > printf(" "); > - printf("%s", boards[i].name); > - for (j = 0; j< 28 - strlen(boards[i].name); j++) > + printf("%s", b->name); > + for (i = 0; i< maxboardlen - strlen(b->name); i++) > printf(" "); > - printf((boards[i].working) ? "OK " : "BAD "); > + printf((b->working) ? "OK " : "BAD "); > > - for (j = 0; b[j].vendor_name != NULL; j++) { > - if (strcmp(b[j].vendor_name, boards[i].vendor) > - || strcmp(b[j].board_name, boards[i].name)) > + for (e = board_pciid_enables; e->vendor_name != NULL; e++) { > + if (strcmp(e->vendor_name, b->vendor) > + || strcmp(e->board_name, b->name)) > continue; > - if (b[j].lb_vendor == NULL) > + if (e->lb_vendor == NULL) > printf("(autodetected)"); > else > - printf("-m %s:%s", b[j].lb_vendor, > - b[j].lb_part); > + printf("-m %s:%s", e->lb_vendor, > + e->lb_part); > } > printf("\n"); > } > diff --git a/programmer.h b/programmer.h > index b68aa88..e1147f1 100644 > --- a/programmer.h > +++ b/programmer.h > @@ -145,7 +145,7 @@ struct bitbang_spi_master { > struct penable { > uint16_t vendor_id; > uint16_t device_id; > - int status; > + int status; /* OK=0 and NT=1 are defines only. Beware! */ > Do we want an enum instead? > const char *vendor_name; > const char *device_name; > int (*doit) (struct pci_dev *dev, const char *name); > @@ -174,10 +174,10 @@ struct board_pciid_enable { > uint16_t second_card_vendor; > uint16_t second_card_device; > > - /* Pattern to match DMI entries */ > + /* Pattern to match DMI entries. May be NULL. */ > const char *dmi_pattern; > > - /* The vendor / part name from the coreboot table. */ > + /* The vendor / part name from the coreboot table. May be NULL. */ > const char *lb_vendor; > const char *lb_part; > > @@ -188,7 +188,7 @@ struct board_pciid_enable { > > int max_rom_decode_parallel; > int status; > - int (*enable) (void); > + int (*enable) (void); /* May be NULL. */ > }; > > extern const struct board_pciid_enable board_pciid_enables[]; > Looks good otherwise. Regards, Carl-Daniel -- http://www.hailfinger.org/

2 3

[commit] r1318 - trunk
by repository service 25 May '11

25 May '11

Author: stefanct Date: Thu May 26 03:35:19 2011 New Revision: 1318 URL: http://flashrom.org/trac/flashrom/changeset/1318 Log: eliminate magic numbers indicating maximum column sizes in print_supported_chipsets and print_supported_boards_helper without this the magic numbers need to be kept in sync with the maximum length of the strings printed in the corresponding column. if not, an overflow and a nasty ' '-storm occur on executing flashrom -L. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashrom.c trunk/print.c trunk/programmer.h Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Thu May 19 04:58:17 2011 (r1317) +++ trunk/flashrom.c Thu May 26 03:35:19 2011 (r1318) @@ -1709,9 +1709,37 @@ msg_gerr("Programmer table miscompilation!\n"); ret = 1; } + /* It would be favorable if we could also check for correct terminaion + * of the follwing arrays, but we don't know their size in here... + * For 'flashchips' we check the first element to be non-null. In the + * other cases there exist use cases where the first element can be + * null. */ + if (flashchips == NULL || flashchips[0].vendor == NULL) { + msg_gerr("Flashchips table miscompilation!\n"); + ret = 1; + } for (flash = flashchips; flash && flash->name; flash++) if (selfcheck_eraseblocks(flash)) ret = 1; + +#if CONFIG_INTERNAL == 1 + if (chipset_enables == NULL) { + msg_gerr("Chipset enables table does not exist!\n"); + ret = 1; + } + if (board_pciid_enables == NULL) { + msg_gerr("Board enables table does not exist!\n"); + ret = 1; + } + if (boards_known == NULL) { + msg_gerr("Known boards table does not exist!\n"); + ret = 1; + } + if (laptops_known == NULL) { + msg_gerr("Known laptops table does not exist!\n"); + ret = 1; + } +#endif // CONFIG_INTERNAL == 1 return ret; } Modified: trunk/print.c ============================================================================== --- trunk/print.c Thu May 19 04:58:17 2011 (r1317) +++ trunk/print.c Thu May 26 03:35:19 2011 (r1318) @@ -77,7 +77,8 @@ static void print_supported_chips(void) { int okcol = 0, pos = 0, i, chipcount = 0; - int maxchiplen = 0, maxvendorlen = 0; + int maxvendorlen = strlen("Vendor") + 1; + int maxchiplen = strlen("Device") + 1; const struct flashchip *f; for (f = flashchips; f->name != NULL; f++) { @@ -92,7 +93,7 @@ maxchiplen++; okcol = maxvendorlen + maxchiplen; - printf("\nSupported flash chips (total: %d):\n\n", chipcount); + printf("Supported flash chips (total: %d):\n\n", chipcount); printf("Vendor"); for (i = strlen("Vendor"); i < maxvendorlen; i++) printf(" "); @@ -158,63 +159,94 @@ #if CONFIG_INTERNAL == 1 static void print_supported_chipsets(void) { - int i, j, chipsetcount = 0; + int i, chipsetcount = 0; const struct penable *c = chipset_enables; + int maxvendorlen = strlen("Vendor") + 1; + int maxchipsetlen = strlen("Chipset") + 1; - for (i = 0; c[i].vendor_name != NULL; i++) + for (c = chipset_enables; c->vendor_name != NULL; c++) { chipsetcount++; + maxvendorlen = max(maxvendorlen, strlen(c->vendor_name)); + maxchipsetlen = max(maxchipsetlen, strlen(c->device_name)); + } + maxvendorlen++; + maxchipsetlen++; + + printf("Supported chipsets (total: %d):\n\n", chipsetcount); - printf("\nSupported chipsets (total: %d):\n\nVendor: " - "Chipset: PCI IDs:\n\n", chipsetcount); + printf("Vendor"); + for (i = strlen("Vendor"); i < maxvendorlen; i++) + printf(" "); - for (i = 0; c[i].vendor_name != NULL; i++) { - printf("%s", c[i].vendor_name); - for (j = 0; j < 25 - strlen(c[i].vendor_name); j++) + printf("Chipset"); + for (i = strlen("Chipset"); i < maxchipsetlen; i++) + printf(" "); + + printf("PCI IDs State\n\n"); + + for (c = chipset_enables; c->vendor_name != NULL; c++) { + printf("%s", c->vendor_name); + for (i = 0; i < maxvendorlen - strlen(c->vendor_name); i++) printf(" "); - printf("%s", c[i].device_name); - for (j = 0; j < 25 - strlen(c[i].device_name); j++) + printf("%s", c->device_name); + for (i = 0; i < maxchipsetlen - strlen(c->device_name); i++) printf(" "); - printf("%04x:%04x%s\n", c[i].vendor_id, c[i].device_id, - (c[i].status == OK) ? "" : " (untested)"); + printf("%04x:%04x%s\n", c->vendor_id, c->device_id, + (c->status == OK) ? "" : " (untested)"); } } static void print_supported_boards_helper(const struct board_info *boards, const char *devicetype) { - int i, j, boardcount_good = 0, boardcount_bad = 0; - const struct board_pciid_enable *b = board_pciid_enables; - - for (i = 0; boards[i].vendor != NULL; i++) { - if (boards[i].working) + int i, boardcount_good = 0, boardcount_bad = 0; + const struct board_pciid_enable *e = board_pciid_enables; + const struct board_info *b = boards; + int maxvendorlen = strlen("Vendor") + 1; + int maxboardlen = strlen("Board") + 1; + + for (b = boards; b->vendor != NULL; b++) { + maxvendorlen = max(maxvendorlen, strlen(b->vendor)); + maxboardlen = max(maxboardlen, strlen(b->name)); + if (b->working) boardcount_good++; else boardcount_bad++; } + maxvendorlen++; + maxboardlen++; + + printf("Known %s (good: %d, bad: %d):\n\n", + devicetype, boardcount_good, boardcount_bad); + + printf("Vendor"); + for (i = strlen("Vendor"); i < maxvendorlen; i++) + printf(" "); + + printf("Board"); + for (i = strlen("Board"); i < maxboardlen; i++) + printf(" "); + + printf("Status Required option\n\n"); + + for (b = boards; b->vendor != NULL; b++) { + printf("%s", b->vendor); + for (i = 0; i < maxvendorlen - strlen(b->vendor); i++) + printf(" "); + printf("%s", b->name); + for (i = 0; i < maxboardlen - strlen(b->name); i++) + printf(" "); + printf((b->working) ? "OK " : "BAD "); - printf("\nKnown %s (good: %d, bad: %d):" - "\n\nVendor: Board: " - "Status: Required option:" - "\n\n", devicetype, boardcount_good, boardcount_bad); - - for (i = 0; boards[i].vendor != NULL; i++) { - printf("%s", boards[i].vendor); - for (j = 0; j < 25 - strlen(boards[i].vendor); j++) - printf(" "); - printf("%s", boards[i].name); - for (j = 0; j < 28 - strlen(boards[i].name); j++) - printf(" "); - printf((boards[i].working) ? "OK " : "BAD "); - - for (j = 0; b[j].vendor_name != NULL; j++) { - if (strcmp(b[j].vendor_name, boards[i].vendor) - || strcmp(b[j].board_name, boards[i].name)) + for (e = board_pciid_enables; e->vendor_name != NULL; e++) { + if (strcmp(e->vendor_name, b->vendor) + || strcmp(e->board_name, b->name)) continue; - if (b[j].lb_vendor == NULL) + if (e->lb_vendor == NULL) printf("(autodetected)"); else - printf("-m %s:%s", b[j].lb_vendor, - b[j].lb_part); + printf("-m %s:%s", e->lb_vendor, + e->lb_part); } printf("\n"); } @@ -228,10 +260,12 @@ printf("\nSupported programmers:\n"); list_programmers_linebreak(0, 80, 0); #if CONFIG_INTERNAL == 1 - printf("\nSupported devices for the %s programmer:\n", + printf("\nSupported devices for the %s programmer:\n\n", programmer_table[PROGRAMMER_INTERNAL].name); print_supported_chipsets(); + printf("\n"); print_supported_boards_helper(boards_known, "boards"); + printf("\n"); print_supported_boards_helper(laptops_known, "laptops"); #endif #if CONFIG_DUMMY == 1 Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Thu May 19 04:58:17 2011 (r1317) +++ trunk/programmer.h Thu May 26 03:35:19 2011 (r1318) @@ -145,7 +145,7 @@ struct penable { uint16_t vendor_id; uint16_t device_id; - int status; + int status; /* OK=0 and NT=1 are defines only. Beware! */ const char *vendor_name; const char *device_name; int (*doit) (struct pci_dev *dev, const char *name); @@ -174,10 +174,10 @@ uint16_t second_card_vendor; uint16_t second_card_device; - /* Pattern to match DMI entries */ + /* Pattern to match DMI entries. May be NULL. */ const char *dmi_pattern; - /* The vendor / part name from the coreboot table. */ + /* The vendor / part name from the coreboot table. May be NULL. */ const char *lb_vendor; const char *lb_part; @@ -188,7 +188,7 @@ int max_rom_decode_parallel; int status; - int (*enable) (void); + int (*enable) (void); /* May be NULL. */ }; extern const struct board_pciid_enable board_pciid_enables[];

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Re: [flashrom] [PATCH 1/6] whitespace (space to tabs mostly)
by Carl-Daniel Hailfinger 25 May '11

25 May '11

Am 01.04.2011 14:33 schrieb Stefan Tauner: > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Assuming that you looked at diff -w and found no code differences, this is Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH 6/7] add missing ICH9 register macros and use them to eliminate magic numbers
by Stefan Tauner 25 May '11

25 May '11

On Tue, 24 May 2011 01:23:13 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > + if (ichspi_bbar) { > msg_pdbg("Reserved bits in BBAR not zero: 0x%04x", > ichspi_bbar); > ichspi_bbar |= minaddr; dunno why the closing } was lost here. must have been a mistake when i reordered my patches with cherry-pick and did not compile test again. :/ did i mention that i hate line limits? the correct hunk(s) should look like this: diff --git a/ichspi.c b/ichspi.c index b7b8cbd..03bc162 100644 @@ -556,9 +556,10 @@ void ich_set_bbar(uint32_t minaddr) case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: ichspi_bbar = mmio_readl(ich_spibar + 0x50) & ~BBAR_MASK; - if (ichspi_bbar) + if (ichspi_bbar) { msg_pdbg("Reserved bits in BBAR not zero: 0x%04x", ichspi_bbar); + } ichspi_bbar |= minaddr; rmmio_writel(ichspi_bbar, ich_spibar + 0x50); ichspi_bbar = mmio_readl(ich_spibar + 0x50); @@ -570,9 +571,10 @@ void ich_set_bbar(uint32_t minaddr) break; case SPI_CONTROLLER_ICH9: ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR) & ~BBAR_MASK; - if (ichspi_bbar) + if (ichspi_bbar) { msg_pdbg("Reserved bits in BBAR not zero: 0x%04x", ichspi_bbar); + } ichspi_bbar |= minaddr; rmmio_writel(ichspi_bbar, ich_spibar + ICH9_REG_BBAR); ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

MSI Big Bang Xpower
by Vinh Le 25 May '11

25 May '11

I have an MSI Big Bang Xpower motherboard with openSUSE 11.2 GNU/Linux as the main OS. I'd like to use flashrom to install a newer version of the BIOS. I installed and executed flashrom from 11.2: ----- flashrom v0.9.1-r710 No coreboot table found. Found chipset "Intel ICH10R", enabling flash write... OK. This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... OK. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically. ----- From this, I checked for the supported hardware on flashrom.org and didn't see the MSI Big Bang Xpower. I'm sending the results of flashrom -V and lspci --nnvvxxx in hopes of having this motherboard supported. (openSUSE 11.2 doesn't seem to have superiotool.) Thanks! ----- flashrom v0.9.1-r710 No coreboot table found. Found chipset "Intel ICH10R", enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled BIOS Lock Enable: enabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x3 Root Complex Register Block address = 0xfed1c000 GCS = 0x461: BIOS Interface Lock-Down: enabled, BOOT BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0x0008 (HSFS) FLOCKDN 0, FDV 0, FDOPSS 0, SCIP 0, BERASE 1, AEL 0, FCERR 0, FDONE 0 0x50: 0x0000ffff (FRAP) BMWAG 0, BMRAG 0, BRWA 255, BRRA 255 0x54: 0x00001fff (FREG0) 0x58: 0x00001fff (FREG1) 0x5C: 0x00001fff (FREG2) 0x60: 0x00001fff (FREG3) 0x64: 0x00001fff (FREG4) 0x74: 0x00000000 (PR0) 0x78: 0x00000000 (PR1) 0x7C: 0x00000000 (PR2) 0x80: 0x00000000 (PR3) 0x84: 0x00000000 (PR4) 0x90: 0x00426004 (SSFS, SSFC) 0x94: 0x0006 (PREOP) 0x96: 0x463b (OPTYPE) 0x98: 0x05d80302 (OPMENU) 0x9C: 0xc79f0190 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xB0: 0x00000000 (FDOC) Programming OPCODES... program_opcodes: preop=0006 optype=463b opmenu=05d80302c79f0190 done SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... 1128M loops per second, 100 myus = 199 us. OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F016D, 2048 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F040B, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29F080B, 1024 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29LV040B, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for AMD Am29LV081B, 1024 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for ASD AE49F2008, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Atmel AT25DF021, 256 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF041A, 512 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF081, 1024 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF161, 2048 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF321, 4096 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF321A, 4096 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25DF641, 8192 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25F512B, 64 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25FS010, 128 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT25FS040, 512 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF041, 512 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF081A, 1024 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF161, 2048 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26DF161A, 2048 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT26F004, 512 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT29C512, 64 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Atmel AT29C010A, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Atmel AT29C020, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Atmel AT29C040A, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Atmel AT45CS1282, 16896 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB011D, 128 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB021D, 256 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB041D, 512 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB081D, 1024 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB161D, 2048 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB321C, 4224 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB321D, 4096 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT45DB642D, 8192 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Atmel AT49BV512, 64 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N), 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for AMIC A25L40P, 512 KB: RDID returned 0xef 0x40 0x16 0x00. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for AMIC A29002B, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for AMIC A29002T, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for AMIC A29040B, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for AMIC A49LF040A, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for EMST F49B002UA, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Eon EN25B05, 64 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B10, 128 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B20, 256 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B40, 512 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B80, 1024 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B16, 2048 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B32, 4096 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25B64, 8192 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25D16, 2048 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F05, 64 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F10, 128 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F20, 256 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F40, 512 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F80, 1024 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F16, 2048 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Eon EN25F32, 4096 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Macronix MX25L512, 64 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1005, 128 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L2005, 256 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L4005, 512 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L8005, 1024 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1605, 2048 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L1635D, 2048 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L3205, 4096 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L3235D, 4096 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L6405, 8192 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX25L12805, 16384 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Numonyx M25PE10, 128 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE20, 256 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE40, 256 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE80, 1024 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Numonyx M25PE16, 2048 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV010, 128 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV016B, 2048 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV020, 256 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV040, 512 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV080B, 1024 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm25LV512, 64 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for PMC Pm29F0002T, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for PMC Pm29F0002B, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for PMC Pm49FL002, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xc7, id2 0x85, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0xff, id2 0xff Probing for Spansion S25FL016A, 2048 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF016B, 2048 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF032B, 4096 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF040B, 512 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST25VF040.REMS, 512 KB: REMS returned ef 15. probe_spi_rems: id1 0xef, id2 0x15 Probing for SST SST25VF040B.REMS, 512 KB: REMS returned ef 15. probe_spi_rems: id1 0xef, id2 0x15 Probing for SST SST25VF080B, 1024 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for SST SST28SF040A, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST29EE010, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST29LE010, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST29EE020A, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST29LE020, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF010A, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF020A, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39SF040, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF512, 64 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF010, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF020, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF040, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST39VF080, 1024 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SST SST49LF002A/B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xc7, id2 0x85, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF008A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF020, 256 KB: probe_jedec: id1 0xc7, id2 0x85, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0xc7, id2 0x85, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for ST M25P05-A, 64 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P05.RES, 64 KB: RDID returned 0xef 0x40 0x16. Probing for ST M25P10-A, 128 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P10.RES, 128 KB: RDID returned 0xef 0x40 0x16. Probing for ST M25P20, 256 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P40, 512 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P40-old, 512 KB: RDID returned 0xef 0x40 0x16. Probing for ST M25P80, 1024 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P16, 2048 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P32, 4096 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P64, 8192 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M25P128, 16384 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for ST M29F002B, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29F040B, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29F400BT, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29W010B, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M29W040B, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for ST M50FLW040A, 512 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FLW040B, 512 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FLW080A, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FLW080B, 1024 KB: probe_stm50flw0x0x: id1 0xff, id2 0xff Probing for ST M50FW002, 256 KB: probe_49lfxxxc: id1 0xc7, id2 0x85 Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50LPW116, 2048 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W25x10, 128 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25x20, 256 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25x40, 512 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25x80, 1024 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W25x16, 2048 KB: RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Probing for Winbond W29C011, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W29C020C, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W29C040P, 512 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W29EE011, 128 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 KB: probe_w39v040c: id1 0xff, id2 0xff, id1 parity violation Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: skipped. Host bus type LPC,FWH,SPI and chip bus type Parallel are incompatible. Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0xc7, id2 0x85, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xc7, id2 0x85, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 KB: probe_winbond_fwhub: id1 0xff, id2 0xff Probing for Winbond W39V080FA (dual mode), 512 KB: probe_winbond_fwhub: id1 0xff, id2 0xff Probing for Atmel unknown Atmel SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Not unmapping zero size at (nil) Probing for EON unknown EON SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Not unmapping zero size at (nil) Probing for Macronix unknown Macronix SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Not unmapping zero size at (nil) Probing for PMC unknown PMC SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Not unmapping zero size at (nil) Probing for SST unknown SST SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Not unmapping zero size at (nil) Probing for ST unknown ST SPI chip, 0 KB: Not mapping flash chip, zero size at 0x00000000. RDID returned 0xef 0x40 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x4016 Not unmapping zero size at (nil) No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically. ----- ----- 00:00.0 Host bridge [0600]: Intel Corporation X58 I/O Hub to ESI Port [8086:3405] (rev 13) Subsystem: Micro-Star International Co., Ltd. Device [1462:7666] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [60] MSI: Enable- Count=1/2 Maskable+ 64bit- Address: 00000000 Data: 0000 Masking: 00000000 Pending: 00000000 Capabilities: [90] Express (v2) Root Port (Slot-), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s L1, Latency L0 <512ns, L1 <64us ClockPM- Surprise+ LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range BCD, TimeoutDis+ ARIFwd+ DevCtl2: Completion Timeout: 260ms to 900ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [e0] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- Capabilities: [150] Access Control Services ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans- ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- Capabilities: [160] Vendor Specific Information <?> 00: 86 80 05 34 00 00 10 00 13 00 00 06 40 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 62 14 66 76 30: 00 00 00 00 60 00 00 00 00 00 00 00 ff 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 00 d1 fe 00 00 00 00 00 00 00 00 00 00 00 00 60: 05 90 02 01 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 10 e0 42 00 20 80 00 00 00 00 00 00 41 3c 3b 00 a0: 00 00 41 30 00 00 00 00 c0 07 00 01 00 00 00 00 b0: 00 00 00 00 3e 00 00 00 09 00 00 00 00 00 00 00 c0: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 01 00 03 c8 08 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:01.0 PCI bridge [0604]: Intel Corporation 5520/5500/X58 I/O Hub PCI Express Root Port 1 [8086:3408] (rev 13) (prog-if 00 [Normal decode]) Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 256 bytes Bus: primary=00, secondary=0f, subordinate=0f, sec-latency=0 Memory behind bridge: fbe00000-fbefffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: Micro-Star International Co., Ltd. Device [1462:7666] Capabilities: [60] MSI: Enable+ Count=1/2 Maskable+ 64bit- Address: feeff00c Data: 4169 Masking: 00000002 Pending: 00000000 Capabilities: [90] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x16, ASPM unknown, Latency L0 <512ns, L1 <4us ClockPM- Surprise+ LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 31, PowerLimit 10.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd Off, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range BCD, TimeoutDis+ ARIFwd+ DevCtl2: Completion Timeout: 260ms to 900ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [e0] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- Capabilities: [150] Access Control Services ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans- ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- Capabilities: [160] Vendor Specific Information <?> Kernel driver in use: pcieport-driver 00: 86 80 08 34 06 05 10 00 13 00 04 06 40 00 01 00 10: 00 00 00 00 00 00 00 00 00 0f 0f 00 f0 00 00 20 20: e0 fb e0 fb f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 40: 0d 60 00 00 62 14 66 76 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 05 90 03 01 0c f0 ef fe 69 41 00 00 02 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 10 e0 42 01 21 80 00 00 0f 00 00 00 02 31 39 00 a0: 40 00 12 70 00 05 88 01 c0 03 48 01 00 00 01 00 b0: 00 00 00 00 3e 00 00 00 09 00 00 00 00 00 00 00 c0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 01 00 03 c8 08 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:02.0 PCI bridge [0604]: Intel Corporation 5520/5500/X58 I/O Hub PCI Express Root Port 2 [8086:3409] (rev 13) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 256 bytes Bus: primary=00, secondary=0e, subordinate=0e, sec-latency=0 I/O behind bridge: 0000e000-0000efff Memory behind bridge: fbd00000-fbdfffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: Intel Corporation Device [8086:0000] Capabilities: [60] MSI: Enable+ Count=1/2 Maskable+ 64bit- Address: feeff00c Data: 4171 Masking: 00000002 Pending: 00000000 Capabilities: [90] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x2, ASPM L0s L1, Latency L0 <512ns, L1 <64us ClockPM- Surprise+ LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 32, PowerLimit 10.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd Off, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range BCD, TimeoutDis+ ARIFwd+ DevCtl2: Completion Timeout: 260ms to 900ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [e0] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- Capabilities: [150] Access Control Services ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans- ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- Kernel driver in use: pcieport-driver 00: 86 80 09 34 07 05 10 00 13 00 04 06 40 00 01 00 10: 00 00 00 00 00 00 00 00 00 0e 0e 00 e0 e0 00 00 20: d0 fb d0 fb f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 40: 0d 60 00 00 86 80 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 05 90 03 01 0c f0 ef fe 71 41 00 00 02 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 10 e0 42 01 21 80 00 00 0f 00 00 00 22 3c 3b 00 a0: 40 00 12 70 00 05 90 01 c0 03 48 01 00 00 01 00 b0: 00 00 00 00 3e 00 00 00 09 00 00 00 00 00 00 00 c0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 01 00 03 c8 08 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:03.0 PCI bridge [0604]: Intel Corporation 5520/5500/X58 I/O Hub PCI Express Root Port 3 [8086:340a] (rev 13) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 256 bytes Bus: primary=00, secondary=0d, subordinate=0d, sec-latency=0 I/O behind bridge: 0000d000-0000dfff Memory behind bridge: f9f00000-fbcfffff Prefetchable memory behind bridge: 00000000ce000000-00000000dfffffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA+ MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: Micro-Star International Co., Ltd. Device [1462:7666] Capabilities: [60] MSI: Enable+ Count=1/2 Maskable+ 64bit- Address: feeff00c Data: 4179 Masking: 00000002 Pending: 00000000 Capabilities: [90] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x16, ASPM unknown, Latency L0 <512ns, L1 <4us ClockPM- Surprise+ LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x16, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 33, PowerLimit 75.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd Off, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range BCD, TimeoutDis+ ARIFwd+ DevCtl2: Completion Timeout: 260ms to 900ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [e0] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- Capabilities: [150] Access Control Services ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans- ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- Capabilities: [160] Vendor Specific Information <?> Kernel driver in use: pcieport-driver 00: 86 80 0a 34 07 05 10 00 13 00 04 06 40 00 01 00 10: 00 00 00 00 00 00 00 00 00 0d 0d 00 d0 d0 00 00 20: f0 f9 c0 fb 01 ce f1 df 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 1a 00 40: 0d 60 00 00 62 14 66 76 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 05 90 03 01 0c f0 ef fe 79 41 00 00 02 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 10 e0 42 01 21 80 00 00 0f 00 00 00 02 31 39 00 a0: 40 00 02 71 80 25 98 01 c0 03 48 01 00 00 01 00 b0: 00 00 00 00 3e 00 00 00 09 00 00 00 00 00 00 00 c0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 01 00 03 c8 08 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:04.0 PCI bridge [0604]: Intel Corporation 5520/X58 I/O Hub PCI Express Root Port 4 [8086:340b] (rev 13) (prog-if 00 [Normal decode]) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 256 bytes Bus: primary=00, secondary=0c, subordinate=0c, sec-latency=0 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: Intel Corporation Device [8086:0000] Capabilities: [60] MSI: Enable+ Count=1/2 Maskable+ 64bit- Address: feeff00c Data: 4189 Masking: 00000002 Pending: 00000000 Capabilities: [90] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x4, ASPM L0s L1, Latency L0 <512ns, L1 <4us ClockPM- Surprise+ LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 34, PowerLimit 25.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd Off, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet+ LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range BCD, TimeoutDis+ ARIFwd+ DevCtl2: Completion Timeout: 260ms to 900ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [e0] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- Capabilities: [150] Access Control Services ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans- ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- Kernel driver in use: pcieport-driver 00: 86 80 0b 34 04 05 10 00 13 00 04 06 40 00 01 00 10: 00 00 00 00 00 00 00 00 00 0c 0c 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 40: 0d 60 00 00 86 80 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 05 90 03 01 0c f0 ef fe 89 41 00 00 02 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 10 e0 42 01 21 80 00 00 0f 00 00 00 42 3c 39 00 a0: 00 00 02 10 80 0c a0 01 c0 03 08 00 00 00 01 00 b0: 00 00 00 00 3e 00 00 00 09 00 00 00 00 00 00 00 c0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 01 00 03 c8 08 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:05.0 PCI bridge [0604]: Intel Corporation 5520/X58 I/O Hub PCI Express Root Port 5 [8086:340c] (rev 13) (prog-if 00 [Normal decode]) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 256 bytes Bus: primary=00, secondary=0b, subordinate=0b, sec-latency=0 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: Intel Corporation Device [8086:0000] Capabilities: [60] MSI: Enable+ Count=1/2 Maskable+ 64bit- Address: feeff00c Data: 4191 Masking: 00000002 Pending: 00000000 Capabilities: [90] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x4, ASPM L0s L1, Latency L0 <512ns, L1 <4us ClockPM- Surprise+ LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 35, PowerLimit 25.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd Off, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet+ LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range BCD, TimeoutDis+ ARIFwd+ DevCtl2: Completion Timeout: 260ms to 900ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [e0] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- Capabilities: [150] Access Control Services ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans- ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- Kernel driver in use: pcieport-driver 00: 86 80 0c 34 04 05 10 00 13 00 04 06 40 00 01 00 10: 00 00 00 00 00 00 00 00 00 0b 0b 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 40: 0d 60 00 00 86 80 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 05 90 03 01 0c f0 ef fe 91 41 00 00 02 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 10 e0 42 01 21 80 00 00 0f 00 00 00 42 3c 39 00 a0: 00 00 02 10 80 0c a8 01 c0 03 08 00 00 00 01 00 b0: 00 00 00 00 3e 00 00 00 09 00 00 00 00 00 00 00 c0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 01 00 03 c8 08 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:06.0 PCI bridge [0604]: Intel Corporation 5520/X58 I/O Hub PCI Express Root Port 6 [8086:340d] (rev 13) (prog-if 00 [Normal decode]) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 256 bytes Bus: primary=00, secondary=0a, subordinate=0a, sec-latency=0 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: Intel Corporation Device [8086:0000] Capabilities: [60] MSI: Enable+ Count=1/2 Maskable+ 64bit- Address: feeff00c Data: 4199 Masking: 00000002 Pending: 00000000 Capabilities: [90] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x4, ASPM L0s L1, Latency L0 <512ns, L1 <4us ClockPM- Surprise+ LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 36, PowerLimit 25.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd Off, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet+ LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range BCD, TimeoutDis+ ARIFwd+ DevCtl2: Completion Timeout: 260ms to 900ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [e0] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- Capabilities: [150] Access Control Services ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans- ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- Kernel driver in use: pcieport-driver 00: 86 80 0d 34 04 05 10 00 13 00 04 06 40 00 01 00 10: 00 00 00 00 00 00 00 00 00 0a 0a 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 40: 0d 60 00 00 86 80 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 05 90 03 01 0c f0 ef fe 99 41 00 00 02 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 10 e0 42 01 21 80 00 00 0f 00 00 00 42 3c 39 00 a0: 00 00 02 10 80 0c b0 01 c0 03 08 00 00 00 01 00 b0: 00 00 00 00 3e 00 00 00 09 00 00 00 00 00 00 00 c0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 01 00 03 c8 08 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:07.0 PCI bridge [0604]: Intel Corporation 5520/5500/X58 I/O Hub PCI Express Root Port 7 [8086:340e] (rev 13) (prog-if 00 [Normal decode]) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 256 bytes Bus: primary=00, secondary=09, subordinate=09, sec-latency=0 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: Micro-Star International Co., Ltd. Device [1462:7666] Capabilities: [60] MSI: Enable+ Count=1/2 Maskable+ 64bit- Address: feeff00c Data: 41a1 Masking: 00000002 Pending: 00000000 Capabilities: [90] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x16, ASPM unknown, Latency L0 <512ns, L1 <4us ClockPM- Surprise+ LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 37, PowerLimit 25.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd Off, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet+ LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range BCD, TimeoutDis+ ARIFwd+ DevCtl2: Completion Timeout: 260ms to 900ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [e0] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- Capabilities: [150] Access Control Services ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans- ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- Capabilities: [160] Vendor Specific Information <?> Kernel driver in use: pcieport-driver 00: 86 80 0e 34 04 05 10 00 13 00 04 06 40 00 01 00 10: 00 00 00 00 00 00 00 00 00 09 09 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 40: 0d 60 00 00 62 14 66 76 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 05 90 03 01 0c f0 ef fe a1 41 00 00 02 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 10 e0 42 01 21 80 00 00 0f 00 00 00 02 31 39 00 a0: 00 00 01 10 80 0c b8 01 c0 03 08 00 00 00 01 00 b0: 00 00 00 00 3e 00 00 00 09 00 00 00 00 00 00 00 c0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 01 00 03 c8 08 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:08.0 PCI bridge [0604]: Intel Corporation 5520/5500/X58 I/O Hub PCI Express Root Port 8 [8086:340f] (rev 13) (prog-if 00 [Normal decode]) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 256 bytes Bus: primary=00, secondary=08, subordinate=08, sec-latency=0 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: Intel Corporation Device [8086:0000] Capabilities: [60] MSI: Enable+ Count=1/2 Maskable+ 64bit- Address: feeff00c Data: 41a9 Masking: 00000002 Pending: 00000000 Capabilities: [90] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x4, ASPM L0s L1, Latency L0 <512ns, L1 <4us ClockPM- Surprise+ LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 38, PowerLimit 25.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd Off, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet+ LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range BCD, TimeoutDis+ ARIFwd+ DevCtl2: Completion Timeout: 260ms to 900ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [e0] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- Capabilities: [150] Access Control Services ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans- ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- Kernel driver in use: pcieport-driver 00: 86 80 0f 34 04 05 10 00 13 00 04 06 40 00 01 00 10: 00 00 00 00 00 00 00 00 00 08 08 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 40: 0d 60 00 00 86 80 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 05 90 03 01 0c f0 ef fe a9 41 00 00 02 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 10 e0 42 01 21 80 00 00 0f 00 00 00 42 3c 39 00 a0: 00 00 01 10 80 0c c0 01 c0 03 08 00 00 00 01 00 b0: 00 00 00 00 3e 00 00 00 09 00 00 00 00 00 00 00 c0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 01 00 03 c8 08 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:09.0 PCI bridge [0604]: Intel Corporation 5520/5500/X58 I/O Hub PCI Express Root Port 9 [8086:3410] (rev 13) (prog-if 00 [Normal decode]) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 256 bytes Bus: primary=00, secondary=07, subordinate=07, sec-latency=0 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: Intel Corporation Device [8086:0000] Capabilities: [60] MSI: Enable+ Count=1/2 Maskable+ 64bit- Address: feeff00c Data: 41b1 Masking: 00000002 Pending: 00000000 Capabilities: [90] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x4, ASPM L0s L1, Latency L0 <512ns, L1 <4us ClockPM- Surprise+ LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 39, PowerLimit 25.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd Off, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet+ LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range BCD, TimeoutDis+ ARIFwd+ DevCtl2: Completion Timeout: 260ms to 900ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [e0] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- Capabilities: [150] Access Control Services ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans- ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- Kernel driver in use: pcieport-driver 00: 86 80 10 34 04 05 10 00 13 00 04 06 40 00 01 00 10: 00 00 00 00 00 00 00 00 00 07 07 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 40: 0d 60 00 00 86 80 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 05 90 03 01 0c f0 ef fe b1 41 00 00 02 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 10 e0 42 01 21 80 00 00 0f 00 00 00 42 3c 39 00 a0: 00 00 01 10 80 0c c8 01 c0 03 08 00 00 00 01 00 b0: 00 00 00 00 3e 00 00 00 09 00 00 00 00 00 00 00 c0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 01 00 03 c8 08 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0a.0 PCI bridge [0604]: Intel Corporation 5520/5500/X58 I/O Hub PCI Express Root Port 10 [8086:3411] (rev 13) (prog-if 00 [Normal decode]) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 256 bytes Bus: primary=00, secondary=06, subordinate=06, sec-latency=0 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Subsystem: Intel Corporation Device [8086:0000] Capabilities: [60] MSI: Enable+ Count=1/2 Maskable+ 64bit- Address: feeff00c Data: 41b9 Masking: 00000002 Pending: 00000000 Capabilities: [90] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x4, ASPM L0s L1, Latency L0 <512ns, L1 <4us ClockPM- Surprise+ LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surpise- Slot # 3a, PowerLimit 25.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Off, PwrInd Off, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- Changed: MRL- PresDet+ LinkState- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Range BCD, TimeoutDis+ ARIFwd+ DevCtl2: Completion Timeout: 260ms to 900ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [e0] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- Capabilities: [150] Access Control Services ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans- ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- Kernel driver in use: pcieport-driver 00: 86 80 11 34 04 05 10 00 13 00 04 06 40 00 01 00 10: 00 00 00 00 00 00 00 00 00 06 06 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 40: 0d 60 00 00 86 80 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 05 90 03 01 0c f0 ef fe b9 41 00 00 02 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 10 e0 42 01 21 80 00 00 0f 00 00 00 42 3c 39 00 a0: 00 00 01 10 80 0c d0 01 c0 03 08 00 00 00 01 00 b0: 00 00 00 00 3e 00 00 00 09 00 00 00 00 00 00 00 c0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 01 00 03 c8 08 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.0 PIC [0800]: Intel Corporation 5520/5500/X58 I/O Hub System Management Registers [8086:342e] (rev 13) (prog-if 00 [8259]) Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [40] Express (v2) Root Complex Integrated Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed unknown, Width x0, ASPM L0s, Latency L0 unlimited, L1 unlimited ClockPM- Surprise+ LLActRep+ BwNot+ LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed unknown, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB 00: 86 80 2e 34 00 00 10 00 13 00 00 08 40 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 40: 10 00 92 00 00 80 00 00 00 00 00 00 00 f4 3b 00 50: 00 00 00 10 00 00 00 00 c0 07 00 00 00 00 01 00 60: 00 00 00 00 00 80 00 00 00 00 00 00 00 f4 3b 00 70: 00 00 00 10 00 00 00 00 c0 07 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 ff ff ff ff 07 00 90: 00 00 00 00 00 00 00 00 48 10 04 00 34 6c 03 00 a0: 00 00 00 00 00 00 00 00 09 00 80 cb 00 00 00 00 b0: 00 00 ff ff ff ff 07 00 00 00 00 00 00 00 00 00 c0: 00 00 ff ff ff ff 07 00 00 00 00 00 00 00 00 00 d0: 00 00 00 c8 00 00 00 b0 01 00 00 00 00 00 00 fc e0: ff ff ff ff 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 e8 ff 3f 00 00 00 00 c4 7f 00 00 00 00 00 00 00:14.1 PIC [0800]: Intel Corporation 5520/5500/X58 I/O Hub GPIO and Scratch Pad Registers [8086:3422] (rev 13) (prog-if 00 [8259]) Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [40] Express (v2) Root Complex Integrated Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed unknown, Width x0, ASPM L0s, Latency L0 unlimited, L1 unlimited ClockPM- Surprise+ LLActRep+ BwNot+ LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed unknown, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB 00: 86 80 22 34 00 00 10 00 13 00 00 08 40 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 40: 10 00 92 00 00 80 00 00 00 00 00 00 00 f4 3b 00 50: 00 00 00 10 00 00 00 00 c0 07 00 00 00 00 01 00 60: 00 00 00 00 00 80 00 00 00 00 00 00 00 f4 3b 00 70: 00 00 00 10 00 00 00 00 c0 07 00 00 80 15 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 bf a0: 00 00 00 00 00 00 00 02 00 00 84 01 00 00 00 00 b0: fa 36 01 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 47 2d 00 00 d0: 04 00 04 00 00 04 00 00 00 00 00 00 80 15 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 bf 00:14.2 PIC [0800]: Intel Corporation 5520/5500/X58 I/O Hub Control Status and RAS Registers [8086:3423] (rev 13) (prog-if 00 [8259]) Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [40] Express (v2) Root Complex Integrated Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed unknown, Width x0, ASPM L0s, Latency L0 unlimited, L1 unlimited ClockPM- Surprise+ LLActRep+ BwNot+ LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed unknown, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB 00: 86 80 23 34 00 00 10 00 13 00 00 08 40 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 40: 10 00 92 00 00 80 00 00 00 00 00 00 00 f4 3b 00 50: 00 00 00 10 00 00 00 00 c0 07 00 00 00 00 01 00 60: 00 00 00 00 00 80 00 00 00 00 00 00 00 f4 3b 00 70: 00 00 00 10 00 00 00 00 c0 07 00 00 00 00 00 00 80: a4 80 a0 02 50 01 aa aa a8 00 00 00 65 15 00 00 90: 00 00 00 00 24 00 00 00 04 08 00 00 22 05 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 00 00 00 00 00 00 00 00 00 00 00 00 42 00 00 d0: 00 00 00 00 00 08 08 92 9d 00 bf 35 00 00 10 00 e0: 40 58 05 00 db 01 00 00 ff 07 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.3 PIC [0800]: Intel Corporation 5520/5500/X58 I/O Hub Throttle Registers [8086:3438] (rev 13) (prog-if 00 [8259]) Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 86 80 38 34 00 00 00 00 13 00 00 08 40 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 0b 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 0b 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 0b 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 dc 00 00 00 a8 00 00 00 00 00 b4 00 c8 00 f0: 00 00 00 7f 00 00 00 00 40 0d d3 07 00 00 00 00 00:1a.0 USB Controller [0c03]: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #4 [8086:3a37] (prog-if 00 [UHCI]) Subsystem: Micro-Star International Co., Ltd. Device [1462:7666] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 16 Region 4: I/O ports at 7080 [size=32] Capabilities: [50] PCI Advanced Features AFCap: TP+ FLR+ AFCtrl: FLR- AFStatus: TP- Kernel driver in use: uhci_hcd 00: 86 80 37 3a 05 00 90 02 00 00 03 0c 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 81 70 00 00 00 00 00 00 00 00 00 00 62 14 66 76 30: 00 00 00 00 50 00 00 00 00 00 00 00 03 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 13 00 06 03 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 01 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 00:1a.1 USB Controller [0c03]: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #5 [8086:3a38] (prog-if 00 [UHCI]) Subsystem: Micro-Star International Co., Ltd. Device [1462:7666] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 21 Region 4: I/O ports at 7400 [size=32] Capabilities: [50] PCI Advanced Features AFCap: TP+ FLR+ AFCtrl: FLR- AFStatus: TP- Kernel driver in use: uhci_hcd 00: 86 80 38 3a 05 00 90 02 00 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 74 00 00 00 00 00 00 00 00 00 00 62 14 66 76 30: 00 00 00 00 50 00 00 00 00 00 00 00 06 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 13 00 06 03 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 01 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 00:1a.2 USB Controller [0c03]: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #6 [8086:3a39] (prog-if 00 [UHCI]) Subsystem: Micro-Star International Co., Ltd. Device [1462:7666] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin D routed to IRQ 19 Region 4: I/O ports at 7480 [size=32] Capabilities: [50] PCI Advanced Features AFCap: TP+ FLR+ AFCtrl: FLR- AFStatus: TP- Kernel driver in use: uhci_hcd 00: 86 80 39 3a 05 00 90 02 00 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 81 74 00 00 00 00 00 00 00 00 00 00 62 14 66 76 30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 04 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 13 00 06 03 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 01 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 00:1a.7 USB Controller [0c03]: Intel Corporation 82801JI (ICH10 Family) USB2 EHCI Controller #2 [8086:3a3c] (prog-if 20 [EHCI]) Subsystem: Micro-Star International Co., Ltd. Device [1462:7666] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin C routed to IRQ 18 Region 0: Memory at f9af6000 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Debug port: BAR=1 offset=00a0 Capabilities: [98] PCI Advanced Features AFCap: TP+ FLR+ AFCtrl: FLR- AFStatus: TP- Kernel driver in use: ehci_hcd 00: 86 80 3c 3a 06 00 90 02 00 20 03 0c 00 00 00 00 10: 00 60 af f9 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 62 14 66 76 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 03 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 c2 c9 00 00 00 00 0a 98 a0 20 00 00 00 00 60: 20 20 ff 01 00 00 00 00 01 00 00 00 00 00 08 80 70: 00 00 cf 0f 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 13 00 06 03 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 aa ff 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 88 85 40 00 86 0f 04 00 0a 17 02 20 00:1b.0 Audio device [0403]: Intel Corporation 82801JI (ICH10 Family) HD Audio Controller [8086:3a3e] Subsystem: Micro-Star International Co., Ltd. Device [1462:4132] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 256 bytes Interrupt: pin A routed to IRQ 22 Region 0: Memory at f9af8000 (64-bit, non-prefetchable) [size=16K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=55mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [60] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [70] Express (v1) Root Complex Integrated Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE- FLReset+ DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #0, Speed unknown, Width x0, ASPM unknown, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed unknown, Width x0, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- Capabilities: [100] Virtual Channel <?> Capabilities: [130] Root Complex Link <?> Kernel driver in use: HDA Intel 00: 86 80 3e 3a 06 00 10 00 00 00 03 04 40 00 00 00 10: 04 80 af f9 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 62 14 32 41 30: 00 00 00 00 50 00 00 00 00 00 00 00 04 01 00 00 40: 01 00 00 07 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 60 42 c8 00 00 00 00 00 00 00 00 00 00 00 00 60: 05 70 80 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 10 00 91 00 00 00 00 10 00 08 10 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 04 00 01 00 00 00 00 31 00 a3 02 00 00 00 00 d0: 61 00 a3 02 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 00:1c.0 PCI bridge [0604]: Intel Corporation 82801JI (ICH10 Family) PCI Express Port 1 [8086:3a40] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 256 bytes Bus: primary=00, secondary=05, subordinate=05, sec-latency=0 I/O behind bridge: 0000c000-0000cfff Memory behind bridge: f9e00000-f9efffff Prefetchable memory behind bridge: 00000000f8f00000-00000000f8ffffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us ClockPM- Surprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surpise+ Slot # 20, PowerLimit 10.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: feeff00c Data: 41c1 Capabilities: [90] Subsystem: Micro-Star International Co., Ltd. Device [1462:4132] Capabilities: [a0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100] Virtual Channel <?> Capabilities: [180] Root Complex Link <?> Kernel driver in use: pcieport-driver 00: 86 80 40 3a 07 05 10 00 00 00 04 06 40 00 81 00 10: 00 00 00 00 00 00 00 00 00 05 05 00 c0 c0 00 00 20: e0 f9 e0 f9 f1 f8 f1 f8 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 05 01 02 00 40: 10 80 41 01 00 80 00 00 00 00 10 00 11 2c 11 01 50: 40 00 11 30 60 05 00 01 00 00 48 01 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 90 01 00 0c f0 ef fe c1 41 00 00 00 00 00 00 90: 0d a0 00 00 62 14 32 41 00 00 00 00 00 00 00 00 a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 11 08 00 00 00 00 e0: 00 0f c7 00 06 07 08 00 30 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 00:1c.1 PCI bridge [0604]: Intel Corporation 82801JI (ICH10 Family) PCI Express Port 2 [8086:3a42] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 256 bytes Bus: primary=00, secondary=04, subordinate=04, sec-latency=0 I/O behind bridge: 0000b000-0000bfff Memory behind bridge: f9d00000-f9dfffff Prefetchable memory behind bridge: 00000000f8e00000-00000000f8efffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #2, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us ClockPM- Surprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surpise+ Slot # 21, PowerLimit 10.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: feeff00c Data: 41c9 Capabilities: [90] Subsystem: Micro-Star International Co., Ltd. Device [1462:4132] Capabilities: [a0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100] Virtual Channel <?> Capabilities: [180] Root Complex Link <?> Kernel driver in use: pcieport-driver 00: 86 80 42 3a 07 05 10 00 00 00 04 06 40 00 81 00 10: 00 00 00 00 00 00 00 00 00 04 04 00 b0 b0 00 00 20: d0 f9 d0 f9 e1 f8 e1 f8 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 03 02 02 00 40: 10 80 41 01 00 80 00 00 00 00 10 00 11 2c 11 02 50: 40 00 11 30 60 05 08 01 00 00 48 01 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 90 01 00 0c f0 ef fe c9 41 00 00 00 00 00 00 90: 0d a0 00 00 62 14 32 41 00 00 00 00 00 00 00 00 a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 11 08 00 00 00 00 e0: 00 0f c7 00 06 07 08 00 30 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 00:1c.2 PCI bridge [0604]: Intel Corporation 82801JI (ICH10 Family) PCI Express Port 3 [8086:3a44] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 256 bytes Bus: primary=00, secondary=03, subordinate=03, sec-latency=0 I/O behind bridge: 0000a000-0000afff Memory behind bridge: f9c00000-f9cfffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #3, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <1us, L1 <4us ClockPM- Surprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surpise+ Slot # 22, PowerLimit 10.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: feeff00c Data: 41d1 Capabilities: [90] Subsystem: Micro-Star International Co., Ltd. Device [1462:4132] Capabilities: [a0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100] Virtual Channel <?> Capabilities: [180] Root Complex Link <?> Kernel driver in use: pcieport-driver 00: 86 80 44 3a 07 05 10 00 00 00 04 06 40 00 81 00 10: 00 00 00 00 00 00 00 00 00 03 03 00 a0 a0 00 00 20: c0 f9 c0 f9 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 03 02 00 40: 10 80 41 01 00 80 00 00 00 00 10 00 11 4c 11 03 50: 00 00 11 30 60 05 10 01 00 00 48 01 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 90 01 00 0c f0 ef fe d1 41 00 00 00 00 00 00 90: 0d a0 00 00 62 14 32 41 00 00 00 00 00 00 00 00 a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 11 08 00 00 00 00 e0: 00 0f c7 00 06 07 08 00 30 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 00:1c.3 PCI bridge [0604]: Intel Corporation 82801JI (ICH10 Family) PCI Express Port 4 [8086:3a46] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 256 bytes Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 I/O behind bridge: 00009000-00009fff Memory behind bridge: f9b00000-f9bfffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- LnkCap: Port #4, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us ClockPM- Surprise- LLActRep+ BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surpise+ Slot # 23, PowerLimit 10.000000; Interlock- NoCompl- SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: feeff00c Data: 41d9 Capabilities: [90] Subsystem: Micro-Star International Co., Ltd. Device [1462:4132] Capabilities: [a0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [100] Virtual Channel <?> Capabilities: [180] Root Complex Link <?> Kernel driver in use: pcieport-driver 00: 86 80 46 3a 07 05 10 00 00 00 04 06 40 00 81 00 10: 00 00 00 00 00 00 00 00 00 02 02 00 90 90 00 00 20: b0 f9 b0 f9 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 04 02 00 40: 10 80 41 01 00 80 00 00 00 00 10 00 11 2c 11 04 50: 40 00 11 30 60 05 18 01 00 00 48 01 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 90 01 00 0c f0 ef fe d9 41 00 00 00 00 00 00 90: 0d a0 00 00 62 14 32 41 00 00 00 00 00 00 00 00 a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 11 08 00 00 00 00 e0: 00 0f c7 00 06 07 08 00 30 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 00:1d.0 USB Controller [0c03]: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #1 [8086:3a34] (prog-if 00 [UHCI]) Subsystem: Micro-Star International Co., Ltd. Device [1462:7666] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 23 Region 4: I/O ports at 7800 [size=32] Capabilities: [50] PCI Advanced Features AFCap: TP+ FLR+ AFCtrl: FLR- AFStatus: TP- Kernel driver in use: uhci_hcd 00: 86 80 34 3a 05 00 90 02 00 00 03 0c 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 78 00 00 00 00 00 00 00 00 00 00 62 14 66 76 30: 00 00 00 00 50 00 00 00 00 00 00 00 07 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 13 00 06 03 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 01 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 00:1d.1 USB Controller [0c03]: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #2 [8086:3a35] (prog-if 00 [UHCI]) Subsystem: Micro-Star International Co., Ltd. Device [1462:7666] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 19 Region 4: I/O ports at 7880 [size=32] Capabilities: [50] PCI Advanced Features AFCap: TP+ FLR+ AFCtrl: FLR- AFStatus: TP- Kernel driver in use: uhci_hcd 00: 86 80 35 3a 05 00 90 02 00 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 81 78 00 00 00 00 00 00 00 00 00 00 62 14 66 76 30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 13 00 06 03 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 01 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 00:1d.2 USB Controller [0c03]: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #3 [8086:3a36] (prog-if 00 [UHCI]) Subsystem: Micro-Star International Co., Ltd. Device [1462:7666] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin C routed to IRQ 18 Region 4: I/O ports at 7c00 [size=32] Capabilities: [50] PCI Advanced Features AFCap: TP+ FLR+ AFCtrl: FLR- AFStatus: TP- Kernel driver in use: uhci_hcd 00: 86 80 36 3a 05 00 90 02 00 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 7c 00 00 00 00 00 00 00 00 00 00 62 14 66 76 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 03 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 13 00 06 03 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 01 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 00:1d.7 USB Controller [0c03]: Intel Corporation 82801JI (ICH10 Family) USB2 EHCI Controller #1 [8086:3a3a] (prog-if 20 [EHCI]) Subsystem: Micro-Star International Co., Ltd. Device [1462:7666] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 23 Region 0: Memory at f9afc000 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Debug port: BAR=1 offset=00a0 Capabilities: [98] PCI Advanced Features AFCap: TP+ FLR+ AFCtrl: FLR- AFStatus: TP- Kernel driver in use: ehci_hcd 00: 86 80 3a 3a 06 00 90 02 00 20 03 0c 00 00 00 00 10: 00 c0 af f9 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 62 14 66 76 30: 00 00 00 00 50 00 00 00 00 00 00 00 07 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 c2 c9 00 00 00 00 0a 98 a0 20 00 00 00 00 60: 20 20 ff 01 00 00 00 00 01 00 00 00 00 00 08 80 70: 00 00 df 0f 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 13 00 06 03 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 aa ff 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 88 85 40 00 86 0f 04 00 0a 17 02 20 00:1e.0 PCI bridge [0604]: Intel Corporation 82801 PCI Bridge [8086:244e] (rev 90) (prog-if 01 [Subtractive decode]) Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=32 Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Subsystem: Micro-Star International Co., Ltd. Device [1462:7666] 00: 86 80 4e 24 04 01 10 00 90 01 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 20 f0 00 80 22 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 02 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 12 00 00 50: 0d 00 00 00 62 14 66 76 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 00:1f.0 ISA bridge [0601]: Intel Corporation 82801JIR (ICH10R) LPC Interface Controller [8086:3a16] Subsystem: Micro-Star International Co., Ltd. Device [1462:7666] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Capabilities: [e0] Vendor Specific Information <?> 00: 86 80 16 3a 07 00 10 02 00 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 62 14 66 76 30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 40: 01 08 00 00 80 00 00 00 01 05 00 00 10 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 83 85 8b 8a d0 00 00 00 80 86 84 87 f8 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 0f 34 01 0a fc 00 01 0a 14 00 01 47 fc 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 74 06 00 00 39 00 00 00 13 00 00 00 00 03 00 c0 b0: 00 00 f0 00 00 00 00 00 00 00 00 08 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 33 22 11 00 67 45 00 00 c0 ff 00 00 03 00 00 00 e0: 09 00 0c 10 01 00 c4 02 64 02 00 00 00 00 00 00 f0: 01 c0 d1 fe 00 00 00 00 86 0f 04 00 00 00 00 00 00:1f.2 IDE interface [0101]: Intel Corporation 82801JI (ICH10 Family) 4 port SATA IDE Controller [8086:3a20] (prog-if 8a [Master SecP PriP]) Subsystem: Micro-Star International Co., Ltd. Device [1462:7666] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 19 Region 0: I/O ports at 01f0 [size=8] Region 1: I/O ports at 03f4 [size=1] Region 2: I/O ports at 0170 [size=8] Region 3: I/O ports at 0374 [size=1] Region 4: I/O ports at ff90 [size=16] Region 5: I/O ports at ffa0 [size=16] Capabilities: [70] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [b0] PCI Advanced Features AFCap: TP+ FLR+ AFCtrl: FLR- AFStatus: TP- Kernel driver in use: ata_piix 00: 86 80 20 3a 05 00 b0 02 00 8a 01 01 00 00 00 00 10: 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 20: 91 ff 00 00 a1 ff 00 00 00 00 00 00 62 14 66 76 30: 00 00 00 00 70 00 00 00 00 00 00 00 00 02 00 00 40: 73 e3 00 80 0b 00 00 00 03 00 11 00 00 00 00 00 50: 00 00 00 00 30 30 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 01 b0 03 00 08 00 00 00 00 00 00 00 00 00 00 00 80: 05 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 0f 85 93 01 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 13 00 06 03 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 07 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 00:1f.3 SMBus [0c05]: Intel Corporation 82801JI (ICH10 Family) SMBus Controller [8086:3a30] Subsystem: Micro-Star International Co., Ltd. Device [1462:7666] Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin C routed to IRQ 18 Region 0: Memory at f9afe000 (64-bit, non-prefetchable) [size=256] Region 4: I/O ports at 0400 [size=32] Kernel driver in use: i801_smbus 00: 86 80 30 3a 03 00 80 02 00 00 05 0c 00 00 00 00 10: 04 e0 af f9 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 04 00 00 00 00 00 00 00 00 00 00 62 14 66 76 30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 03 00 00 40: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 02 04 04 00 f0 00 08 08 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 00:1f.5 IDE interface [0101]: Intel Corporation 82801JI (ICH10 Family) 2 port SATA IDE Controller [8086:3a26] (prog-if 85 [Master SecO PriO]) Subsystem: Micro-Star International Co., Ltd. Device [1462:7666] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 19 Region 0: I/O ports at 8c00 [size=8] Region 1: I/O ports at 8880 [size=4] Region 2: I/O ports at 8800 [size=8] Region 3: I/O ports at 8480 [size=4] Region 4: I/O ports at 8400 [size=16] Region 5: I/O ports at 8080 [size=16] Capabilities: [70] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [b0] PCI Advanced Features AFCap: TP+ FLR+ AFCtrl: FLR- AFStatus: TP- Kernel driver in use: ata_piix 00: 86 80 26 3a 07 00 b0 02 00 85 01 01 00 00 00 00 10: 01 8c 00 00 81 88 00 00 01 88 00 00 81 84 00 00 20: 01 84 00 00 81 80 00 00 00 00 00 00 62 14 66 76 30: 00 00 00 00 70 00 00 00 00 00 00 00 0a 02 00 00 40: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 01 b0 03 00 08 00 00 00 00 00 00 00 00 00 00 00 80: 05 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 13 00 06 03 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 02:00.0 SATA controller [0106]: JMicron Technology Corp. JMB362/JMB363 AHCI Controller [197b:2363] (rev 03) (prog-if 01 [AHCI 1.0]) Subsystem: Micro-Star International Co., Ltd. Device [1462:7666] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 256 bytes Interrupt: pin A routed to IRQ 19 Region 5: Memory at f9bfe000 (32-bit, non-prefetchable) [size=8K] Capabilities: [68] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] Express (v1) Legacy Endpoint, MSI 01 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend- LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s, Latency L0 unlimited, L1 unlimited ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- Kernel driver in use: ahci 00: 7b 19 63 23 07 00 10 00 03 01 06 01 40 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 e0 bf f9 00 00 00 00 62 14 66 76 30: 00 00 00 00 68 00 00 00 00 00 00 00 0a 01 00 00 40: b7 a1 c2 00 08 08 ff e0 20 00 00 20 00 00 00 00 50: 10 00 11 02 00 00 00 00 00 20 08 00 11 f4 03 01 60: 00 00 11 10 00 00 00 00 01 50 02 40 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 a0 01 0a 00 14 aa 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 c0: c3 8b 38 00 03 45 02 00 53 00 00 00 0f 80 a7 00 d0: 18 00 00 80 01 00 00 10 00 00 eb 00 00 00 00 01 e0: 00 00 00 00 00 00 00 00 18 35 9c c2 01 88 00 84 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02:00.1 IDE interface [0101]: JMicron Technology Corp. JMB362/JMB363 AHCI Controller [197b:2363] (rev 03) (prog-if 85 [Master SecO PriO]) Subsystem: Micro-Star International Co., Ltd. Device [1462:7666] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 16 Region 0: I/O ports at 9c00 [size=8] Region 1: I/O ports at 9880 [size=4] Region 2: I/O ports at 9800 [size=8] Region 3: I/O ports at 9480 [size=4] Region 4: I/O ports at 9400 [size=16] Capabilities: [68] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: pata_jmicron 00: 7b 19 63 23 05 00 10 00 03 85 01 01 00 00 00 00 10: 01 9c 00 00 81 98 00 00 01 98 00 00 81 94 00 00 20: 01 94 00 00 00 00 00 00 00 00 00 00 62 14 66 76 30: 00 00 00 00 68 00 00 00 00 00 00 00 00 02 00 00 40: b7 a1 c2 00 08 08 ff e0 20 00 00 20 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 00 02 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 a0 01 0a 00 14 aa 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 c0: c3 8b 38 00 03 45 02 00 53 00 00 00 0f 80 a7 00 d0: 18 00 00 80 01 00 00 10 00 00 eb 00 00 00 00 01 e0: 00 00 00 00 00 00 00 00 18 35 9c c2 01 88 00 84 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03:00.0 FireWire (IEEE 1394) [0c00]: VIA Technologies, Inc. Device [1106:3403] (rev 01) (prog-if 10 [OHCI]) Subsystem: Micro-Star International Co., Ltd. Device [1462:666d] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 256 bytes Interrupt: pin A routed to IRQ 18 Region 0: Memory at f9cff800 (64-bit, non-prefetchable) [size=2K] Region 2: I/O ports at a800 [size=256] Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2+ AuxCurrent=0mA PME(D0-,D1-,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [80] MSI: Enable- Count=1/1 Maskable+ 64bit+ Address: 0000000000000000 Data: 0000 Masking: 00000000 Pending: 00000000 Capabilities: [98] Express (v1) Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <1us, L1 <64us ClockPM+ Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- Capabilities: [100] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 14, GenCap+ CGenEn- ChkCap+ ChkEn- Capabilities: [130] Device Serial Number 00-10-dc-ff-ff-b4-aa-98 Kernel driver in use: ohci1394 00: 06 11 03 34 07 00 10 00 01 10 00 0c 40 00 00 00 10: 04 f8 cf f9 00 00 00 00 01 a8 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 62 14 6d 66 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 80 03 e4 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 02 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 05 98 80 01 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 10 00 01 00 00 80 28 00 a0: 00 20 19 00 11 4c 07 00 00 00 11 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 04:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168] (rev 03) Subsystem: Micro-Star International Co., Ltd. Device [1462:7666] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 256 bytes Interrupt: pin A routed to IRQ 40 Region 0: I/O ports at b800 [size=256] Region 2: Memory at f8eff000 (64-bit, prefetchable) [size=4K] Region 4: Memory at f8ef8000 (64-bit, prefetchable) [size=16K] Expansion ROM at f9de0000 [disabled] [size=128K] Capabilities: [40] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+ Address: 00000000feeff00c Data: 4152 Capabilities: [70] Express (v2) Endpoint, MSI 01 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 4096 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <64us ClockPM+ Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [ac] MSI-X: Enable- Count=4 Masked- Vector table: BAR=4 offset=00000000 PBA: BAR=4 offset=00000800 Capabilities: [cc] Vital Product Data Unknown small resource type 00, will not decode more. Capabilities: [100] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn- Capabilities: [140] Virtual Channel <?> Capabilities: [160] Device Serial Number 21-00-00-00-68-4c-e0-00 Kernel driver in use: r8169 00: ec 10 68 81 07 04 10 00 03 00 00 02 40 00 00 00 10: 01 b8 00 00 00 00 00 00 0c f0 ef f8 00 00 00 00 20: 0c 80 ef f8 00 00 00 00 00 00 00 00 62 14 66 76 30: 00 00 de f9 40 00 00 00 00 00 00 00 05 01 00 00 40: 01 50 c3 ff 08 00 00 00 00 00 00 00 00 00 00 00 50: 05 70 81 00 0c f0 ef fe 00 00 00 00 52 41 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 10 ac 02 02 c1 8c 28 00 10 50 19 00 11 3c 07 00 80: 40 00 11 10 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 11 cc 03 00 b0: 04 00 00 00 04 08 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 80 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 05:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168] (rev 03) Subsystem: Micro-Star International Co., Ltd. Device [1462:7666] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 256 bytes Interrupt: pin A routed to IRQ 39 Region 0: I/O ports at c800 [size=256] Region 2: Memory at f8fff000 (64-bit, prefetchable) [size=4K] Region 4: Memory at f8ff8000 (64-bit, prefetchable) [size=16K] Expansion ROM at f9ee0000 [disabled] [size=128K] Capabilities: [40] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+ Address: 00000000feeff00c Data: 414a Capabilities: [70] Express (v2) Endpoint, MSI 01 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 4096 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <64us ClockPM+ Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [ac] MSI-X: Enable- Count=4 Masked- Vector table: BAR=4 offset=00000000 PBA: BAR=4 offset=00000800 Capabilities: [cc] Vital Product Data Unknown small resource type 00, will not decode more. Capabilities: [100] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn- Capabilities: [140] Virtual Channel <?> Capabilities: [160] Device Serial Number 22-00-00-00-68-4c-e0-00 Kernel driver in use: r8169 00: ec 10 68 81 07 04 10 00 03 00 00 02 40 00 00 00 10: 01 c8 00 00 00 00 00 00 0c f0 ff f8 00 00 00 00 20: 0c 80 ff f8 00 00 00 00 00 00 00 00 62 14 66 76 30: 00 00 ee f9 40 00 00 00 00 00 00 00 03 01 00 00 40: 01 50 c3 ff 08 00 00 00 00 00 00 00 00 00 00 00 50: 05 70 81 00 0c f0 ef fe 00 00 00 00 4a 41 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 10 ac 02 02 c1 8c 28 00 10 50 19 00 11 3c 07 00 80: 40 00 11 10 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 11 cc 03 00 b0: 04 00 00 00 04 08 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 03 00 00 80 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0d:00.0 VGA compatible controller [0300]: nVidia Corporation Device [10de:0ca3] (rev a2) (prog-if 00 [VGA controller]) Subsystem: eVga.com. Corp. Device [3842:1246] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 16 Region 0: Memory at fa000000 (32-bit, non-prefetchable) [size=16M] Region 1: Memory at d0000000 (64-bit, prefetchable) [size=256M] Region 3: Memory at ce000000 (64-bit, prefetchable) [size=32M] Region 5: I/O ports at dc00 [size=128] [virtual] Expansion ROM at f9f80000 [disabled] [size=512K] Capabilities: [60] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [68] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [78] Express (v2) Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 <64us ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x16, ASPM L0s L1, Latency L0 <256ns, L1 <4us ClockPM+ Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x16, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [b4] Vendor Specific Information <?> Capabilities: [100] Virtual Channel <?> Capabilities: [128] Power Budgeting <?> Capabilities: [600] Vendor Specific Information <?> Kernel driver in use: nvidia 00: de 10 a3 0c 07 00 10 00 a2 00 00 03 00 00 80 00 10: 00 00 00 fa 0c 00 00 d0 00 00 00 00 0c 00 00 ce 20: 00 00 00 00 01 dc 00 00 00 00 00 00 42 38 46 12 30: 00 00 00 00 60 00 00 00 00 00 00 00 03 01 00 00 40: 42 38 46 12 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 00 00 00 01 00 00 00 ce d6 23 00 00 00 00 00 60: 01 68 03 00 08 00 00 00 05 78 80 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 10 b4 02 00 e0 8d 2c 01 80: 10 29 00 00 02 2d 05 00 48 01 02 11 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 a0: 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 b0: 00 00 00 00 09 00 14 01 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0d:00.1 Audio device [0403]: nVidia Corporation Device [10de:0be4] (rev a1) Subsystem: eVga.com. Corp. Device [3842:1246] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 256 bytes Interrupt: pin B routed to IRQ 5 Region 0: Memory at fbcfc000 (32-bit, non-prefetchable) [size=16K] Capabilities: [60] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [68] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [78] Express (v2) Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <4us, L1 <64us ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x16, ASPM L0s L1, Latency L0 <256ns, L1 <1us ClockPM+ Surprise- LLActRep- BwNot- LnkCtl: ASPM L0s L1 Enabled; RCB 128 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x16, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB 00: de 10 e4 0b 06 00 10 00 a1 00 03 04 40 00 80 00 10: 00 c0 cf fb 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 42 38 46 12 30: 00 00 00 00 60 00 00 00 00 00 00 00 05 02 00 00 40: 42 38 46 12 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 ce d6 23 00 00 00 00 00 60: 01 68 03 00 08 00 00 00 05 78 80 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 10 00 02 00 a0 8d 2c 01 80: 10 29 01 00 02 2d 04 00 4b 01 02 11 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 10 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0e:00.0 SATA controller [0106]: Device [1b4b:9123] (rev 10) (prog-if 01 [AHCI 1.0]) Subsystem: Micro-Star International Co., Ltd. Device [1462:7666] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 38 Region 0: I/O ports at ec00 [size=8] Region 1: I/O ports at e880 [size=4] Region 2: I/O ports at e800 [size=8] Region 3: I/O ports at e480 [size=4] Region 4: I/O ports at e400 [size=16] Region 5: Memory at fbdff800 (32-bit, non-prefetchable) [size=2K] Expansion ROM at fbde0000 [disabled] [size=64K] Capabilities: [40] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: feeff00c Data: 41e1 Capabilities: [70] Express (v2) Legacy Endpoint, MSI 00 DevCap: MaxPayload 512 bytes, PhantFunc 0, Latency L0s <1us, L1 <8us ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend- LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <64us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [100] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- Kernel driver in use: ahci 00: 4b 1b 23 91 07 04 10 00 10 01 06 01 00 00 00 00 10: 01 ec 00 00 81 e8 00 00 01 e8 00 00 81 e4 00 00 20: 01 e4 00 00 00 f8 df fb 00 00 00 00 62 14 66 76 30: 00 00 de fb 40 00 00 00 00 00 00 00 03 01 00 00 40: 01 50 03 40 00 00 00 00 00 00 00 00 00 00 00 00 50: 05 70 01 00 0c f0 ef fe e1 41 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 10 00 12 00 02 87 28 00 10 20 09 00 12 3c 03 00 80: 40 00 12 10 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 a0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0f:00.0 USB Controller [0c03]: NEC Corporation Device [1033:0194] (rev 03) (prog-if 30) Subsystem: Micro-Star International Co., Ltd. Device [1462:7666] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 256 bytes Interrupt: pin A routed to IRQ 16 Region 0: Memory at fbefe000 (64-bit, non-prefetchable) [size=8K] Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [70] MSI: Enable- Count=1/8 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [90] MSI-X: Enable- Count=8 Masked- Vector table: BAR=0 offset=00001000 PBA: BAR=0 offset=00001080 Capabilities: [a0] Express (v2) Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend- LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <4us, L1 unlimited ClockPM+ Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [100] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- Capabilities: [140] Device Serial Number ff-ff-ff-ff-ff-ff-ff-ff Capabilities: [150] #18 Kernel driver in use: xhci_hcd 00: 33 10 94 01 06 00 10 00 03 30 03 0c 40 00 00 00 10: 04 e0 ef fb 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 62 14 66 76 30: 00 00 00 00 50 00 00 00 00 00 00 00 03 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 70 c3 c9 08 00 00 00 00 00 00 00 00 00 00 00 60: 30 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 05 90 86 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 11 a0 07 00 00 10 00 00 80 10 00 00 00 00 00 00 a0: 10 00 02 00 c0 8f 00 00 00 28 19 00 12 ec 07 00 b0: 40 01 12 10 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 10 08 00 00 00 00 00 00 00 00 00 00 d0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: fc 1f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 08 14 60 00 00 00 00 00 00 00 00 00 00 00 00 00 -----

2 6

Motherboard
by Cristiano Pimentel 24 May '11

24 May '11

Hello, Flashrom accepts the mainboard Intel D510MO??? It works with the D510MO?

1 0

Fwd: [patch] VT6421A LPC programmer
by Антон Кочков 24 May '11

24 May '11

Best regards, Anton Kochkov. ---------- Forwarded message ---------- From: Антон Кочков <anton.kochkov(a)gmail.com> Date: 2011/5/24 Subject: Re: [flashrom] [patch] VT6421A LPC programmer To: "Jonathan A. Kollasch" <jakllsch(a)kollasch.net> This patch not working on most VT6421A. May be we need check for flash access before writing/reading chip? flash_access_control(PCI_dev via_device) { count = 0; while (c<300) { access_mode = pci_read_byte(via_device, 0x68); if (access_mode & (1<<6)) == (1<<6) { return access_granted; } else { delay(0xA); } c++; } return access_restricted; } Best regards, Anton Kochkov. On Tue, Jan 4, 2011 at 06:23, Jonathan A. Kollasch <jakllsch(a)kollasch.net> wrote: > Add VIA VT6421A LPC programmer driver. > > Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom >

1 0

Re: [flashrom] [patch] VT6421A LPC programmer
by Антон Кочков 24 May '11

24 May '11

Sorry, forgot this: Looks like it need for: pci_dword_write(via_device, 0x30, 0xFFFFFFFF); some delay; pci_dword_write(via_device, 0x30, 0); before any access to 0x6x registers to VIA device Best regards, Anton Kochkov. 2011/5/24 Антон Кочков <anton.kochkov(a)gmail.com>: > This patch not working on most VT6421A. > > May be we need check for flash access before writing/reading chip? > > flash_access_control(PCI_dev via_device) > { > count = 0; > while (c<300) { > access_mode = pci_read_byte(via_device, 0x68); > if (access_mode & (1<<6)) == (1<<6) { > return access_granted; > } else { > delay(0xA); > } > c++; > } > return access_restricted; > } > > Best regards, > Anton Kochkov. > > > > > On Tue, Jan 4, 2011 at 06:23, Jonathan A. Kollasch > <jakllsch(a)kollasch.net> wrote: >> Add VIA VT6421A LPC programmer driver. >> >> Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> >> >> _______________________________________________ >> flashrom mailing list >> flashrom(a)flashrom.org >> http://www.flashrom.org/mailman/listinfo/flashrom >> >

1 0

[PATCH] eliminate magic numbers indicating maximum column sizes in print_supported_chipsets and print_supported_boards_helper
by Stefan Tauner 23 May '11

23 May '11

without this the magic numbers need to be kept in sync with the maximum length of the strings printed in the corresponding column. if not an overflow and a nasty ' '-storm occurs on executing flashrom -L. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- after a short discussion with carldani i have removed the assert stuff and do some inferior array checking in selfcheck. we only have _extern_ references to the tables to sizeof does not work. we could add a "getter" for the sizes of the array or bring the tables into view to improve this... but i dont think it's worth it. flashrom.c | 22 +++++++++++++ print.c | 96 ++++++++++++++++++++++++++++++++++++++------------------- programmer.h | 8 ++-- 3 files changed, 90 insertions(+), 36 deletions(-) diff --git a/flashrom.c b/flashrom.c index 46c9ecd..821d745 100644 --- a/flashrom.c +++ b/flashrom.c @@ -1709,6 +1709,28 @@ int selfcheck(void) msg_gerr("Programmer table miscompilation!\n"); ret = 1; } + /* It would be favorable if we could also check for correct terminaion + * of the follwing arrays, but we don't know their size in here... */ + if (flashchips == NULL || flashchips[0].vendor == NULL) { + msg_gerr("Flashchips table miscompilation!\n"); + ret = 1; + } + if (chipset_enables == NULL || chipset_enables[0].vendor_name == NULL) { + msg_gerr("Chipset enables table miscompilation!\n"); + ret = 1; + } + if (board_pciid_enables == NULL || board_pciid_enables[0].vendor_name == NULL) { + msg_gerr("Board enables table miscompilation!\n"); + ret = 1; + } + if (boards_known == NULL || boards_known[0].vendor == NULL) { + msg_gerr("Known boards table miscompilation!\n"); + ret = 1; + } + if (laptops_known == NULL || laptops_known[0].vendor == NULL) { + msg_gerr("Known laptops table miscompilation!\n"); + ret = 1; + } for (flash = flashchips; flash && flash->name; flash++) if (selfcheck_eraseblocks(flash)) ret = 1; diff --git a/print.c b/print.c index e84a417..b0f8247 100644 --- a/print.c +++ b/print.c @@ -77,7 +77,8 @@ static int digits(int n) static void print_supported_chips(void) { int okcol = 0, pos = 0, i, chipcount = 0; - int maxchiplen = 0, maxvendorlen = 0; + int maxvendorlen = strlen("Vendor") + 1; + int maxchiplen = strlen("Device") + 1; const struct flashchip *f; for (f = flashchips; f->name != NULL; f++) { @@ -158,63 +159,94 @@ static void print_supported_chips(void) #if CONFIG_INTERNAL == 1 static void print_supported_chipsets(void) { - int i, j, chipsetcount = 0; + int i, chipsetcount = 0; const struct penable *c = chipset_enables; + int maxvendorlen = strlen("Vendor") + 1; + int maxchipsetlen = strlen("Chipset") + 1; - for (i = 0; c[i].vendor_name != NULL; i++) + for (c = chipset_enables; c->vendor_name != NULL; c++) { chipsetcount++; + maxvendorlen = max(maxvendorlen, strlen(c->vendor_name)); + maxchipsetlen = max(maxchipsetlen, strlen(c->device_name)); + } + maxvendorlen++; + maxchipsetlen++; + + printf("\nSupported chipsets (total: %d):\n\n", chipsetcount); + + printf("Vendor"); + for (i = strlen("Vendor"); i < maxvendorlen; i++) + printf(" "); + + printf("Chipset"); + for (i = strlen("Chipset"); i < maxchipsetlen; i++) + printf(" "); - printf("\nSupported chipsets (total: %d):\n\nVendor: " - "Chipset: PCI IDs:\n\n", chipsetcount); + printf("PCI IDs State\n\n"); - for (i = 0; c[i].vendor_name != NULL; i++) { - printf("%s", c[i].vendor_name); - for (j = 0; j < 25 - strlen(c[i].vendor_name); j++) + for (c = chipset_enables; c->vendor_name != NULL; c++) { + printf("%s", c->vendor_name); + for (i = 0; i < maxvendorlen - strlen(c->vendor_name); i++) printf(" "); - printf("%s", c[i].device_name); - for (j = 0; j < 25 - strlen(c[i].device_name); j++) + printf("%s", c->device_name); + for (i = 0; i < maxchipsetlen - strlen(c->device_name); i++) printf(" "); - printf("%04x:%04x%s\n", c[i].vendor_id, c[i].device_id, - (c[i].status == OK) ? "" : " (untested)"); + printf("%04x:%04x%s\n", c->vendor_id, c->device_id, + (c->status == OK) ? "" : " (untested)"); } } static void print_supported_boards_helper(const struct board_info *boards, const char *devicetype) { - int i, j, boardcount_good = 0, boardcount_bad = 0; - const struct board_pciid_enable *b = board_pciid_enables; - - for (i = 0; boards[i].vendor != NULL; i++) { - if (boards[i].working) + int i, boardcount_good = 0, boardcount_bad = 0; + const struct board_pciid_enable *e = board_pciid_enables; + const struct board_info *b = boards; + int maxvendorlen = strlen("Vendor") + 1; + int maxboardlen = strlen("Board") + 1; + + for (b = boards; b->vendor != NULL; b++) { + maxvendorlen = max(maxvendorlen, strlen(b->vendor)); + maxboardlen = max(maxboardlen, strlen(b->name)); + if (b->working) boardcount_good++; else boardcount_bad++; } + maxvendorlen++; + maxboardlen++; + + printf("\nKnown %s (good: %d, bad: %d):\n\n", + devicetype, boardcount_good, boardcount_bad); + + printf("Vendor"); + for (i = strlen("Vendor"); i < maxvendorlen; i++) + printf(" "); + + printf("Board"); + for (i = strlen("Board"); i < maxboardlen; i++) + printf(" "); - printf("\nKnown %s (good: %d, bad: %d):" - "\n\nVendor: Board: " - "Status: Required option:" - "\n\n", devicetype, boardcount_good, boardcount_bad); + printf("Status Required option\n\n"); - for (i = 0; boards[i].vendor != NULL; i++) { - printf("%s", boards[i].vendor); - for (j = 0; j < 25 - strlen(boards[i].vendor); j++) + for (b = boards; b->vendor != NULL; b++) { + printf("%s", b->vendor); + for (i = 0; i < maxvendorlen - strlen(b->vendor); i++) printf(" "); - printf("%s", boards[i].name); - for (j = 0; j < 28 - strlen(boards[i].name); j++) + printf("%s", b->name); + for (i = 0; i < maxboardlen - strlen(b->name); i++) printf(" "); - printf((boards[i].working) ? "OK " : "BAD "); + printf((b->working) ? "OK " : "BAD "); - for (j = 0; b[j].vendor_name != NULL; j++) { - if (strcmp(b[j].vendor_name, boards[i].vendor) - || strcmp(b[j].board_name, boards[i].name)) + for (e = board_pciid_enables; e->vendor_name != NULL; e++) { + if (strcmp(e->vendor_name, b->vendor) + || strcmp(e->board_name, b->name)) continue; - if (b[j].lb_vendor == NULL) + if (e->lb_vendor == NULL) printf("(autodetected)"); else - printf("-m %s:%s", b[j].lb_vendor, - b[j].lb_part); + printf("-m %s:%s", e->lb_vendor, + e->lb_part); } printf("\n"); } diff --git a/programmer.h b/programmer.h index b68aa88..e1147f1 100644 --- a/programmer.h +++ b/programmer.h @@ -145,7 +145,7 @@ struct bitbang_spi_master { struct penable { uint16_t vendor_id; uint16_t device_id; - int status; + int status; /* OK=0 and NT=1 are defines only. Beware! */ const char *vendor_name; const char *device_name; int (*doit) (struct pci_dev *dev, const char *name); @@ -174,10 +174,10 @@ struct board_pciid_enable { uint16_t second_card_vendor; uint16_t second_card_device; - /* Pattern to match DMI entries */ + /* Pattern to match DMI entries. May be NULL. */ const char *dmi_pattern; - /* The vendor / part name from the coreboot table. */ + /* The vendor / part name from the coreboot table. May be NULL. */ const char *lb_vendor; const char *lb_part; @@ -188,7 +188,7 @@ struct board_pciid_enable { int max_rom_decode_parallel; int status; - int (*enable) (void); + int (*enable) (void); /* May be NULL. */ }; extern const struct board_pciid_enable board_pciid_enables[]; -- 1.7.1

1 0

[PATCH 7/7] add ICH/PCH flash descriptor decoding
by Stefan Tauner 23 May '11

23 May '11

based on the work of Matthias 'mazzoo' Wenzel this patch adds... - pretty printing of those ICH/PCH flash descriptors that are cached/mapped by the chipset (and which are therefore reachable via FDOC/FDOD registers) and - a new tool to the util directory that is able to decode all flash descriptors stored in a flash dump file. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- Makefile | 2 +- ich_descriptors.c | 415 ++++++++++++++++++++++ ich_descriptors.h | 406 +++++++++++++++++++++ ichspi.c | 12 +- util/ich_descriptors_tool/Makefile | 42 +++ util/ich_descriptors_tool/TODO | 5 + util/ich_descriptors_tool/ich_descriptors_tool.c | 226 ++++++++++++ 7 files changed, 1105 insertions(+), 3 deletions(-) create mode 100644 ich_descriptors.c create mode 100644 ich_descriptors.h create mode 100644 util/ich_descriptors_tool/Makefile create mode 100644 util/ich_descriptors_tool/TODO create mode 100644 util/ich_descriptors_tool/ich_descriptors_tool.c diff --git a/Makefile b/Makefile index 6e6e2de..b61031f 100644 --- a/Makefile +++ b/Makefile @@ -223,7 +223,7 @@ ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o # FIXME: The PROGRAMMER_OBJS below should only be included on x86. -PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o ich_descriptors.o sb600spi.o wbsio_spi.o mcp6x_spi.o NEED_PCI := yes endif diff --git a/ich_descriptors.c b/ich_descriptors.c new file mode 100644 index 0000000..9ae153b --- /dev/null +++ b/ich_descriptors.c @@ -0,0 +1,415 @@ +/* This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * authors: + * (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * (c) 2011 Stefan Tauner + */ + +#include "ich_descriptors.h" + +#if defined(__i386__) || defined(__x86_64__) + +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP + +#define DESCRIPTOR_MODE_MAGIC 0x0ff0a55a +#define msg_pdbg printf +#include <stdio.h> + +struct flash_strap fisba; +struct flash_upper_map flumap; + +#else + +#include "flash.h" /* for msg_* */ + +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP + +struct flash_descriptor fdbar; +struct flash_component fcba; +struct flash_region frba; +struct flash_master fmba; + +uint32_t getFCBA() +{ + return (fdbar.FLMAP0 << 4) & 0x00000ff0; +} + +uint32_t getFRBA() +{ + return (fdbar.FLMAP0 >> 12) & 0x00000ff0; +} + +uint32_t getFMBA() +{ + return (fdbar.FLMAP1 << 4) & 0x00000ff0; +} + +uint32_t getFMSBA() +{ + return (fdbar.FLMAP2 << 4) & 0x00000ff0; +} + +uint32_t getFLREG_limit(uint32_t flreg) +{ + return (flreg >> 4) & 0x01fff000; +} + +uint32_t getFLREG_base(uint32_t flreg) +{ + return (flreg << 12) & 0x01fff000; +} + +uint32_t getFISBA() +{ + return (fdbar.FLMAP1 >> 12) & 0x00000ff0; +} + +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP +uint32_t getVTBA() +{ + return (flumap.FLUMAP1 << 4) & 0x0ff0; +} +#endif + +const struct flash_descriptor_addresses desc_addr = { + .FCBA = getFCBA, + .FRBA = getFRBA, + .FMBA = getFMBA, + .FMSBA = getFMSBA, + .FISBA = getFISBA, + .FLREG_limit = getFLREG_limit, + .FLREG_base = getFLREG_base, +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP + .VTBA = getVTBA, +#endif +}; + +void pretty_print_ich_descriptors() +{ + pretty_print_ich_descriptor_map(); + pretty_print_ich_descriptor_component(); + pretty_print_ich_descriptor_region(); + pretty_print_ich_descriptor_master(); +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP + pretty_print_ich_descriptor_upper_map(); + /* FIXME: detect chipset correctly */ + pretty_print_ich_descriptor_straps(CHIPSET_SERIES_5_IBEX_PEAK); +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP + msg_pdbg("\n"); +} + +void pretty_print_ich_descriptor_map(void) +{ + msg_pdbg("=== FDBAR ===\n"); + msg_pdbg("FLVALSIG 0x%8.8x\n", fdbar.FLVALSIG); + msg_pdbg("FLMAP0 0x%8.8x\n", fdbar.FLMAP0 ); + msg_pdbg("FLMAP1 0x%8.8x\n", fdbar.FLMAP1 ); + msg_pdbg("FLMAP2 0x%8.8x\n", fdbar.FLMAP2 ); + msg_pdbg("\n"); + msg_pdbg("--- FDBAR details ---\n"); + msg_pdbg("0x%2.2x NR Number of Regions\n", fdbar.NR ); + msg_pdbg("0x%8.8x FRBA Flash Region Base Address\n", desc_addr.FRBA() ); + msg_pdbg("0x%2.2x NC Number of Components\n", fdbar.NC ); + msg_pdbg("0x%8.8x FCBA Flash Component Base Address\n", desc_addr.FCBA() ); + msg_pdbg("\n"); + msg_pdbg("0x%2.2x ISL ICH Strap Length\n", fdbar.ISL ); + msg_pdbg("0x%8.8x FISBA Flash ICH Strap Base Address\n", desc_addr.FISBA()); + msg_pdbg("0x%2.2x NM Number of Masters\n", fdbar.NM ); + msg_pdbg("0x%8.8x FMBA Flash Master Base Address\n", desc_addr.FMBA() ); + msg_pdbg("\n"); + msg_pdbg("0x%2.2x MSL MCH Strap Length\n", fdbar.MSL ); + msg_pdbg("0x%8.8x FMSBA Flash MCH Strap Base Address\n", desc_addr.FMSBA()); +} + +void pretty_print_ich_descriptor_component(void) +{ + char * str_freq[8] = { + "20 MHz", /* 000 */ + "33 MHz", /* 001 */ + "reserved/illegal", /* 010 */ + "reserved/illegal", /* 011 */ + "50 MHz", /* 100 */ + "reserved/illegal", /* 101 */ + "reserved/illegal", /* 110 */ + "reserved/illegal" /* 111 */ + }; + char * str_mem[8] = { + "512kB", + "1 MB", + "2 MB", + "4 MB", + "8 MB", + "16 MB", + "undocumented/illegal", + "reserved/illegal" + }; + + msg_pdbg("\n"); + msg_pdbg("=== FCBA ===\n"); + msg_pdbg("FLCOMP 0x%8.8x\n", fcba.FLCOMP); + msg_pdbg("FLILL 0x%8.8x\n", fcba.FLILL ); + msg_pdbg("\n"); + msg_pdbg("--- FCBA details ---\n"); + msg_pdbg("0x%2.2x freq_read_id %s\n", + fcba.freq_read_id , str_freq[fcba.freq_read_id ]); + msg_pdbg("0x%2.2x freq_write %s\n", + fcba.freq_write , str_freq[fcba.freq_write ]); + msg_pdbg("0x%2.2x freq_fastread %s\n", + fcba.freq_fastread, str_freq[fcba.freq_fastread]); + msg_pdbg("0x%2.2x fastread %ssupported\n", + fcba.fastread, fcba.fastread ? "" : "not "); + msg_pdbg("0x%2.2x freq_read %s\n", + fcba.freq_read, str_freq[fcba.freq_read ]); + msg_pdbg("0x%2.2x comp 1 density %s\n", + fcba.comp1_density, str_mem[fcba.comp1_density]); + if (fdbar.NC) + msg_pdbg("0x%2.2x comp 2 density %s\n", + fcba.comp2_density, str_mem[fcba.comp2_density]); + else + msg_pdbg("0x%2.2x comp 2 density is not used (NC=0)\n", + fcba.comp2_density); + msg_pdbg("\n"); + msg_pdbg("0x%2.2x invalid instr 0\n", fcba.invalid_instr0); + msg_pdbg("0x%2.2x invalid instr 1\n", fcba.invalid_instr1); + msg_pdbg("0x%2.2x invalid instr 2\n", fcba.invalid_instr2); + msg_pdbg("0x%2.2x invalid instr 3\n", fcba.invalid_instr3); +} + +void pretty_print_ich_descriptor_region(void) +{ + msg_pdbg("\n"); + msg_pdbg("=== FRBA ===\n"); + msg_pdbg("FLREG0 0x%8.8x\n", frba.FLREG0); + msg_pdbg("FLREG1 0x%8.8x\n", frba.FLREG1); + msg_pdbg("FLREG2 0x%8.8x\n", frba.FLREG2); + msg_pdbg("FLREG3 0x%8.8x\n", frba.FLREG3); + msg_pdbg("\n"); + msg_pdbg("--- FRBA details ---\n"); + msg_pdbg("0x%8.8x region 0 limit (descr)\n", desc_addr.FLREG_limit(frba.FLREG0)); + msg_pdbg("0x%8.8x region 0 base (descr)\n", desc_addr.FLREG_base(frba.FLREG0)); + msg_pdbg("0x%8.8x region 1 limit ( BIOS)\n", desc_addr.FLREG_limit(frba.FLREG1)); + msg_pdbg("0x%8.8x region 1 base ( BIOS)\n", desc_addr.FLREG_base(frba.FLREG1)); + msg_pdbg("0x%8.8x region 2 limit ( ME )\n", desc_addr.FLREG_limit(frba.FLREG2)); + msg_pdbg("0x%8.8x region 2 base ( ME )\n", desc_addr.FLREG_base(frba.FLREG2)); + msg_pdbg("0x%8.8x region 3 limit ( GbE )\n", desc_addr.FLREG_limit(frba.FLREG3)); + msg_pdbg("0x%8.8x region 3 base ( GbE )\n", desc_addr.FLREG_base(frba.FLREG3)); +} + +void pretty_print_ich_descriptor_master(void) +{ + msg_pdbg("\n"); + msg_pdbg("=== FMBA ===\n"); + msg_pdbg("FLMSTR1 0x%8.8x\n", fmba.FLMSTR1); + msg_pdbg("FLMSTR2 0x%8.8x\n", fmba.FLMSTR2); + msg_pdbg("FLMSTR3 0x%8.8x\n", fmba.FLMSTR3); + + msg_pdbg("\n"); + msg_pdbg("--- FMBA details ---\n"); + msg_pdbg("BIOS can %s write GbE\n", fmba.BIOS_GbE_write ? " " : "NOT"); + msg_pdbg("BIOS can %s write ME\n", fmba.BIOS_ME_write ? " " : "NOT"); + msg_pdbg("BIOS can %s write BIOS\n", fmba.BIOS_BIOS_write ? " " : "NOT"); + msg_pdbg("BIOS can %s write descr\n", fmba.BIOS_descr_write ? " " : "NOT"); + msg_pdbg("BIOS can %s read GbE\n", fmba.BIOS_GbE_read ? " " : "NOT"); + msg_pdbg("BIOS can %s read ME\n", fmba.BIOS_ME_read ? " " : "NOT"); + msg_pdbg("BIOS can %s read BIOS\n", fmba.BIOS_BIOS_read ? " " : "NOT"); + msg_pdbg("BIOS can %s read descr\n", fmba.BIOS_descr_read ? " " : "NOT"); + msg_pdbg("ME can %s write GbE\n", fmba.ME_GbE_write ? " " : "NOT"); + msg_pdbg("ME can %s write ME\n", fmba.ME_ME_write ? " " : "NOT"); + msg_pdbg("ME can %s write BIOS\n", fmba.ME_BIOS_write ? " " : "NOT"); + msg_pdbg("ME can %s write descr\n", fmba.ME_descr_write ? " " : "NOT"); + msg_pdbg("ME can %s read GbE\n", fmba.ME_GbE_read ? " " : "NOT"); + msg_pdbg("ME can %s read ME\n", fmba.ME_ME_read ? " " : "NOT"); + msg_pdbg("ME can %s read BIOS\n", fmba.ME_BIOS_read ? " " : "NOT"); + msg_pdbg("ME can %s read descr\n", fmba.ME_descr_read ? " " : "NOT"); + msg_pdbg("GbE can %s write GbE\n", fmba.GbE_GbE_write ? " " : "NOT"); + msg_pdbg("GbE can %s write ME\n", fmba.GbE_ME_write ? " " : "NOT"); + msg_pdbg("GbE can %s write BIOS\n", fmba.GbE_BIOS_write ? " " : "NOT"); + msg_pdbg("GbE can %s write descr\n", fmba.GbE_descr_write ? " " : "NOT"); + msg_pdbg("GbE can %s read GbE\n", fmba.GbE_GbE_read ? " " : "NOT"); + msg_pdbg("GbE can %s read ME\n", fmba.GbE_ME_read ? " " : "NOT"); + msg_pdbg("GbE can %s read BIOS\n", fmba.GbE_BIOS_read ? " " : "NOT"); + msg_pdbg("GbE can %s read descr\n", fmba.GbE_descr_read ? " " : "NOT"); +} + +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP +void pretty_print_ich_descriptor_straps_ich8(void) +{ + char * str_GPIO12[4] = { + "GPIO12", + "LAN PHY Power Control Function (Native Output)", + " GLAN_DOCK# (Native Input)", + "invalid configuration", + }; + + msg_pdbg("\n"); + msg_pdbg("=== FISBA ===\n"); + msg_pdbg("STRP0 0x%8.8x\n", fisba.ich8.STRP0); + + msg_pdbg("\n"); + msg_pdbg("--- FISBA details ---\n"); + msg_pdbg("ME SMBus addr2 0x%2.2x\n", fisba.ich8.ASD2); + msg_pdbg("ME SMBus addr1 0x%2.2x\n", fisba.ich8.ASD); + msg_pdbg("ME SMBus Controller is connected to %s\n", fisba.ich8.MESM2SEL ? "SMLink pins" : "SMBus pins"); + msg_pdbg("SPI CS1 is used for %s\n", fisba.ich8.SPICS1_LANPHYPC_SEL ? "LAN PHY Power Control Function" : "SPI Chip Select"); + msg_pdbg("GPIO12_SEL is used as %s\n", str_GPIO12[fisba.ich8.GPIO12_SEL]); + msg_pdbg("PCIe Port 6 is used for %s\n", fisba.ich8.GLAN_PCIE_SEL ? "integrated GLAN" : "PCI Express"); + msg_pdbg("Intel AMT SMBus Controller 1 is connected to %s\n", fisba.ich8.BMCMODE ? "SMLink" : "SMBus"); + msg_pdbg("TCO slave is on %s. Intel AMT SMBus Controller 1 is %sabled\n", + fisba.ich8.TCOMODE ? "SMBus" : "SMLink", fisba.ich8.TCOMODE ? "en" : "dis"); + msg_pdbg("ME A is %sabled\n", fisba.ich8.ME_DISABLE ? "dis" : "en"); + + msg_pdbg("\n"); + msg_pdbg("=== FMSBA ===\n"); + msg_pdbg("STRP1 0x%8.8x\n", fisba.ich8.STRP1); + + msg_pdbg("\n"); + msg_pdbg("--- FMSBA details ---\n"); + msg_pdbg("ME B is %sabled\n", fisba.ich8.ME_disable_B ? "dis" : "en"); +} + +void pretty_print_ich_descriptor_straps_ibex(void) +{ + int i; + msg_pdbg("\n"); + msg_pdbg("=== FPSBA ===\n"); + for(i = 0; i <= 15; i++) + msg_pdbg("STRP%-2d = 0x%8.8x\n", i, fisba.ibex.STRPs[i]); +} + +void pretty_print_ich_descriptor_straps(enum chipset cs) +{ + switch (cs) { + case CHIPSET_ICH8: + pretty_print_ich_descriptor_straps_ich8(); + break; + case CHIPSET_SERIES_5_IBEX_PEAK: + pretty_print_ich_descriptor_straps_ibex(); + break; + default: + break; + } +} +void pretty_print_ich_descriptor_upper_map(void) +{ + int i; + msg_pdbg("\n"); + msg_pdbg("=== FLUMAP ===\n"); + msg_pdbg("FLUMAP1 0x%8.8x\n", flumap.FLUMAP1); + + msg_pdbg("\n"); + msg_pdbg("--- FLUMAP details ---\n"); + msg_pdbg("VTL 0x%8.8x\n", flumap.VTL); + msg_pdbg("VTBA 0x%8.8x\n", desc_addr.VTBA()); + msg_pdbg("\n"); + + for (i=0; i < flumap.VTL/2; i++) + { + msg_pdbg(" JID%d = 0x%8.8x\n", i, flumap.vscc_table[i].JID ); + msg_pdbg(" VSCC%d = 0x%8.8x\n", i, flumap.vscc_table[i].VSCC); + } +} + +int read_ich_descriptors_from_dump(uint32_t *dump) +{ + int i; + uint8_t pch_bug_offset = 0; + if (dump[0] != DESCRIPTOR_MODE_MAGIC) { + if (dump[4] == DESCRIPTOR_MODE_MAGIC) + pch_bug_offset = 4; + else + return -1; + } + + /* map */ + fdbar.FLVALSIG = dump[0 + pch_bug_offset]; + fdbar.FLMAP0 = dump[1 + pch_bug_offset]; + fdbar.FLMAP1 = dump[2 + pch_bug_offset]; + fdbar.FLMAP2 = dump[3 + pch_bug_offset]; + + /* component */ + fcba.FLCOMP = dump[(desc_addr.FCBA() >> 2) + 0]; + fcba.FLILL = dump[(desc_addr.FCBA() >> 2) + 1]; + fcba.FLPB = dump[(desc_addr.FCBA() >> 2) + 2]; + + /* region */ + frba.FLREG0 = dump[(desc_addr.FRBA() >> 2) + 0]; + frba.FLREG1 = dump[(desc_addr.FRBA() >> 2) + 1]; + frba.FLREG2 = dump[(desc_addr.FRBA() >> 2) + 2]; + frba.FLREG3 = dump[(desc_addr.FRBA() >> 2) + 3]; + + /* master */ + fmba.FLMSTR1 = dump[(desc_addr.FMBA() >> 2) + 0]; + fmba.FLMSTR2 = dump[(desc_addr.FMBA() >> 2) + 1]; + fmba.FLMSTR3 = dump[(desc_addr.FMBA() >> 2) + 2]; + + /* upper map */ + flumap.FLUMAP1 = dump[(0x0efc >> 2) + 0]; + + for (i=0; i < flumap.VTL; i++) + { + flumap.vscc_table[i].JID = dump[(desc_addr.VTBA() >> 2) + i * 2 + 0]; + flumap.vscc_table[i].VSCC = dump[(desc_addr.VTBA() >> 2) + i * 2 + 1]; + } + /* straps */ + /* FIXME: detect chipset correctly */ + switch (CHIPSET_SERIES_5_IBEX_PEAK) { + case CHIPSET_ICH8: + fisba.ich8.STRP0 = dump[(desc_addr.FISBA() >> 2) + 0]; + fisba.ich8.STRP1 = dump[(desc_addr.FMSBA() >> 2) + 0]; + break; + case CHIPSET_SERIES_5_IBEX_PEAK: + for(i = 0; i <= 15; i++) + fisba.ibex.STRPs[i] = dump[(desc_addr.FISBA() >> 2) + i]; + break; + default: + break; + } + + return 0; +} +#else // ICH_DESCRIPTORS_FROM_MMAP_DUMP + +static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) +{ + uint32_t control = 0; + control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS; + control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI; + *(volatile uint32_t *) (spibar + ICH9_REG_FDOC) = control; + return *(volatile uint32_t *)(spibar + ICH9_REG_FDOD); +} + +void read_ich_descriptors_from_fdo(void *spibar) +{ + msg_pdbg("Reading flash descriptors " + "mapped by the chipset via FDOC/FDOD..."); + /* descriptor map section */ + fdbar.FLVALSIG = read_descriptor_reg(0, 0, spibar); + fdbar.FLMAP0 = read_descriptor_reg(0, 1, spibar); + fdbar.FLMAP1 = read_descriptor_reg(0, 2, spibar); + fdbar.FLMAP2 = read_descriptor_reg(0, 3, spibar); + + /* component section */ + fcba.FLCOMP = read_descriptor_reg(1, 0, spibar); + fcba.FLILL = read_descriptor_reg(1, 1, spibar); + fcba.FLPB = read_descriptor_reg(1, 2, spibar); + + /* region section */ + frba.FLREG0 = read_descriptor_reg(2, 0, spibar); + frba.FLREG1 = read_descriptor_reg(2, 1, spibar); + frba.FLREG2 = read_descriptor_reg(2, 2, spibar); + frba.FLREG3 = read_descriptor_reg(2, 3, spibar); + + /* master section */ + fmba.FLMSTR1 = read_descriptor_reg(3, 0, spibar); + fmba.FLMSTR2 = read_descriptor_reg(3, 1, spibar); + fmba.FLMSTR3 = read_descriptor_reg(3, 2, spibar); + + /* strap section and upper map */ + /* impossible via FDOC/FDOD(?) */ + msg_pdbg(" done\n"); +} + +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP +#endif // defined(__i386__) || defined(__x86_64__) diff --git a/ich_descriptors.h b/ich_descriptors.h new file mode 100644 index 0000000..96dd724 --- /dev/null +++ b/ich_descriptors.h @@ -0,0 +1,406 @@ +/* This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * authors: + * (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * (c) 2011 Stefan Tauner + */ + +#include <stdint.h> + +#if defined(__i386__) || defined(__x86_64__) +#ifndef __ICH_DESCRIPTORS_H__ +#define __ICH_DESCRIPTORS_H__ 1 + +/* should probably be in ichspi.h */ +#define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */ +#define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Select */ +#define FDOC_FDSI (0x3f << FDOC_FDSI_OFF) +#define FDOC_FDSS_OFF 12 /* 12-14: Flash Descriptor Section Select */ +#define FDOC_FDSS (0x3 << FDOC_FDSS_OFF) +#define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */ + +enum chipset { + CHIPSET_ICH8, + CHIPSET_ICH9, + CHIPSET_ICH10, + CHIPSET_SERIES_5_IBEX_PEAK, + CHIPSET_SERIES_6_COUGAR_POINT, + CHIPSET_SERIES_7_PANTHER_POINT +}; + +struct flash_descriptor_addresses { + uint32_t (*FCBA)(void); + uint32_t (*FRBA)(void); + uint32_t (*FMBA)(void); + uint32_t (*FMSBA)(void); + uint32_t (*FLREG_limit)(uint32_t flreg); + uint32_t (*FLREG_base)(uint32_t flreg); + uint32_t (*FISBA)(void); +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP + uint32_t (*VTBA)(void); +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP +}; + +struct flash_descriptor { + uint32_t FLVALSIG; /* 0x00 */ + union { /* 0x04 */ + uint32_t FLMAP0; + struct { + uint8_t FCBA :8; + uint8_t NC :2; + unsigned :6; + uint8_t FRBA :8; + uint8_t NR :3; + unsigned :5; + }; + }; + union { /* 0x08 */ + uint32_t FLMAP1; + struct { + uint8_t FMBA :8; + uint8_t NM :3; + unsigned :5; + union { + uint8_t FISBA :8; + uint8_t FPSBA :8; + }; + uint8_t ISL :8; + }; + }; + union { /* 0x0c */ + uint32_t FLMAP2; + struct { + uint8_t FMSBA :8; + uint8_t MSL :8; + unsigned :16; + }; + }; +}; + +struct flash_component { + union { /* 0x00 */ + uint32_t FLCOMP; + struct { + uint8_t comp1_density :3; + uint8_t comp2_density :3; + unsigned :11; + uint8_t freq_read :3; + uint8_t fastread :1; + uint8_t freq_fastread :3; + uint8_t freq_write :3; + uint8_t freq_read_id :3; + unsigned :2; + }; + }; + union { /* 0x04 */ + uint32_t FLILL; + struct { + uint8_t invalid_instr0; + uint8_t invalid_instr1; + uint8_t invalid_instr2; + uint8_t invalid_instr3; + }; + }; + union { /* 0x08 */ + uint32_t FLPB; + struct { + uint16_t FPBA :13; + unsigned :19; + }; + }; +}; + +struct flash_region { + + union { + uint32_t FLREG0; /* Flash Descriptor */ + struct { + uint16_t reg0_base :13; + unsigned :3; + uint16_t reg0_limit :13; + unsigned :3; + }; + }; + union { + uint32_t FLREG1; /* BIOS */ + struct { + uint16_t reg1_base :13; + unsigned :3; + uint16_t reg1_limit :13; + unsigned :3; + }; + }; + union { + uint32_t FLREG2; /* ME */ + struct { + uint16_t reg2_base :13; + unsigned :3; + uint16_t reg2_limit :13; + unsigned :3; + }; + }; + union { + uint32_t FLREG3; /* GbE */ + struct { + uint16_t reg3_base :13; + unsigned :3; + uint16_t reg3_limit :13; + unsigned :3; + }; + }; +} frba; + +struct flash_master { + union { + uint32_t FLMSTR1; + struct { + uint16_t BIOS_req_ID :16; + uint8_t BIOS_descr_read :1; + uint8_t BIOS_BIOS_read :1; + uint8_t BIOS_ME_read :1; + uint8_t BIOS_GbE_read :1; + uint8_t BIOS_plat_read :1; + unsigned :3; + uint8_t BIOS_descr_write :1; + uint8_t BIOS_BIOS_write :1; + uint8_t BIOS_ME_write :1; + uint8_t BIOS_GbE_write :1; + uint8_t BIOS_plat_write :1; + unsigned :3; + }; + }; + union { + uint32_t FLMSTR2; + struct { + uint16_t ME_req_ID :16; + uint8_t ME_descr_read :1; + uint8_t ME_BIOS_read :1; + uint8_t ME_ME_read :1; + uint8_t ME_GbE_read :1; + uint8_t ME_plat_read :1; + unsigned :3; + uint8_t ME_descr_write :1; + uint8_t ME_BIOS_write :1; + uint8_t ME_ME_write :1; + uint8_t ME_GbE_write :1; + uint8_t ME_plat_write :1; + unsigned :3; + }; + }; + union { + uint32_t FLMSTR3; + struct { + uint16_t GbE_req_ID :16; + uint8_t GbE_descr_read :1; + uint8_t GbE_BIOS_read :1; + uint8_t GbE_ME_read :1; + uint8_t GbE_GbE_read :1; + uint8_t GbE_plat_read :1; + unsigned :3; + uint8_t GbE_descr_write :1; + uint8_t GbE_BIOS_write :1; + uint8_t GbE_ME_write :1; + uint8_t GbE_GbE_write :1; + uint8_t GbE_plat_write :1; + unsigned :3; + }; + }; +}; + +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP +struct flash_strap { + union { + struct { + union { + uint32_t STRP0; + struct { + uint8_t ME_DISABLE :1; + unsigned :6; + uint8_t TCOMODE :1; + uint8_t ASD :7; + uint8_t BMCMODE :1; + unsigned :3; + uint8_t GLAN_PCIE_SEL :1; + uint8_t GPIO12_SEL :2; + uint8_t SPICS1_LANPHYPC_SEL :1; + uint8_t MESM2SEL :1; + unsigned :1; + uint8_t ASD2 :7; + }; + }; + union { + uint32_t STRP1; + struct { + uint8_t ME_disable_B :1; + unsigned :31; + }; + }; + }ich8; + union { + uint32_t STRPs[15]; + struct { + union { + uint32_t STRP0; + struct { + unsigned :1; + uint8_t cs_ss2 :1; + unsigned :5; + uint8_t SMB_EN :1; + uint8_t SML0_EN :1; + uint8_t SML1_EN :1; + uint8_t SML1FRQ :2; + uint8_t SMB0FRQ :2; + uint8_t SML0FRQ :2; + unsigned :4; + uint8_t LANPHYPC_GP12_SEL :1; + uint8_t cs_ss1 :1; + unsigned :2; + uint8_t DMI_REQID_DIS :1; + unsigned :4; + uint8_t BBBS :2; + unsigned :1; + }; + }; + union { + uint32_t STRP1; + struct { + }; + }; + union { + uint32_t STRP2; + struct { + }; + }; + union { + uint32_t STRP3; + struct { + }; + }; + union { + uint32_t STRP4; + struct { + }; + }; + union { + uint32_t STRP5; + struct { + }; + }; + union { + uint32_t STRP6; + struct { + }; + }; + union { + uint32_t STRP7; + struct { + }; + }; + union { + uint32_t STRP8; + struct { + }; + }; + union { + uint32_t STRP9; + struct { + }; + }; + union { + uint32_t STRP10; + struct { + }; + }; + union { + uint32_t STRP11; + struct { + }; + }; + union { + uint32_t STRP12; + struct { + }; + }; + union { + uint32_t STRP13; + struct { + }; + }; + union { + uint32_t STRP14; + struct { + }; + }; + union { + uint32_t STRP15; + struct { + }; + }; + }; + }ibex; + }; +}; + +struct flash_upper_map { + union { + uint32_t FLUMAP1; + struct { + uint8_t VTBA :8; + uint8_t VTL :8; + unsigned :16; + }; + }; + struct { + union { + uint32_t JID; + struct { + uint8_t vid :8; + uint8_t cid0 :8; + uint8_t cid1 :8; + unsigned :8; + }; + }; + union { + uint32_t VSCC; + struct { + uint8_t ubes :2; + uint8_t uwg :1; + uint8_t uwsr :1; + uint8_t uwews :1; + unsigned :3; + uint8_t ueo :8; + uint8_t lbes :2; + uint8_t lwg :1; + uint8_t lwsr :1; + uint8_t lwews :1; + unsigned :3; + uint16_t leo :16; + }; + }; + }vscc_table[128]; +}; +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP + +void pretty_print_ich_descriptors(void); + +void pretty_print_ich_descriptor_map(void); +void pretty_print_ich_descriptor_component(void); +void pretty_print_ich_descriptor_region(void); +void pretty_print_ich_descriptor_master(void); + +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP + +void pretty_print_ich_descriptor_upper_map(void); +void pretty_print_ich_descriptor_straps(enum chipset cs); +int read_ich_descriptors_from_dump(uint32_t *dump); + +#else // ICH_DESCRIPTORS_FROM_MMAP_DUMP + +void read_ich_descriptors_from_fdo(void *spibar); + +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP + +#endif // __ICH_DESCRIPTORS_H__ +#endif // defined(__i386__) || defined(__x86_64__) diff --git a/ichspi.c b/ichspi.c index df44373..23ceeff 100644 --- a/ichspi.c +++ b/ichspi.c @@ -6,6 +6,7 @@ * Copyright (C) 2008 Dominik Geyer <dominik.geyer(a)kontron.com> * Copyright (C) 2008 coresystems GmbH <info(a)coresystems.de> * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger + * Copyright (C) 2011 Stefan Tauner * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -41,6 +42,7 @@ #include "chipdrivers.h" #include "programmer.h" #include "spi.h" +#include "ich_descriptors.h" /* ICH9 controller register definition */ #define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ @@ -1194,6 +1196,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, uint8_t old, new; uint16_t spibar_offset, tmp2; uint32_t tmp; + int ichspi_desc = 0; switch (ich_generation) { case 7: @@ -1265,6 +1268,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } + if (tmp2 & HSFS_FDV) + ichspi_desc = 1; tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); @@ -1313,8 +1318,11 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); msg_pdbg("0xA0: 0x%08x (BBAR)\n", ichspi_bbar); - msg_pdbg("0xB0: 0x%08x (FDOC)\n", - mmio_readl(ich_spibar + ICH9_REG_FDOC)); + msg_pdbg("\n"); + if (ichspi_desc) { + read_ich_descriptors_from_fdo(ich_spibar); + pretty_print_ich_descriptors(); + } ich_init_opcodes(); break; default: diff --git a/util/ich_descriptors_tool/Makefile b/util/ich_descriptors_tool/Makefile new file mode 100644 index 0000000..9b1d096 --- /dev/null +++ b/util/ich_descriptors_tool/Makefile @@ -0,0 +1,42 @@ +CC ?= gcc + +PROGRAM=ich_descriptors_tool +EXTRAINCDIRS = ../../ . +DEPPATH = .dep +OBJATH = .obj +SHAREDSRC = ich_descriptors.c +SHAREDSRCDIR = ../.. + +SRC = $(wildcard *.c) + +CFLAGS=-Wall +CFLAGS += -MMD -MP -MF $(DEPPATH)/$((a)F).d +# enables functions that populate the descriptor structs from plain dump arrays +CFLAGS += -D ICH_DESCRIPTORS_FROM_MMAP_DUMP +CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) + +OBJ = $(OBJATH)/$(SRC:%.c=%.o) + +SHAREDOBJ = $(OBJATH)/$(notdir $(SHAREDSRC:%.c=%.o)) + +all:$(PROGRAM) + +$(OBJ): $(OBJATH)/%.o : %.c + $(CC) $(CFLAGS) -o $@ -c $< + +# this enables us to NOT share object files with flashrom, +# which would lead to unexpected results otherwise (w/o running make clean) +$(SHAREDOBJ): $(OBJATH)/%.o : $(SHAREDSRCDIR)/%.c + $(CC) $(CFLAGS) -o $@ -c $< + +$(PROGRAM): $(OBJ) $(SHAREDOBJ) + $(CC) -o $(PROGRAM) $(OBJ) $(SHAREDOBJ) + +clean: + rm -f $(PROGRAM) + rm -rf $(DEPPATH) $(OBJATH) + +# Include the dependency files. +-include $(shell mkdir -p $(DEPPATH) $(OBJATH) 2>/dev/null) $(wildcard $(DEPPATH)/*) + +.PHONY: all clean \ No newline at end of file diff --git a/util/ich_descriptors_tool/TODO b/util/ich_descriptors_tool/TODO new file mode 100644 index 0000000..e3933ee --- /dev/null +++ b/util/ich_descriptors_tool/TODO @@ -0,0 +1,5 @@ +- reverse the path, as in assemble a descriptormode image from various + blobs (BIOS, GbE, ME, OEM) and a description (xml? custom config? + sane defaults and cmd-line switches?) +- dump 256 OEM bytes +- handle descriptors of various chipsets correctly \ No newline at end of file diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c new file mode 100644 index 0000000..8ce7677 --- /dev/null +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -0,0 +1,226 @@ +/* + * dump information and binaries from BIOS images that are in descriptor mode/soft-strap + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * authors: + * (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * (c) 2011 Stefan Tauner + * + * */ +#include <stdio.h> +#include <stdint.h> +#include <stdlib.h> +#include <sys/mman.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <fcntl.h> +#include <unistd.h> +#include <string.h> +#include <errno.h> +#include "flash.h" +#include "ich_descriptors.h" + +extern struct flash_descriptor fdbar; +extern struct flash_component fcba; +extern struct flash_region frba; +extern struct flash_master fmba; +extern struct flash_strap fisba; +extern struct flash_upper_map flumap; +extern struct flash_descriptor_addresses desc_addr; + +static int f; /* file descriptor to flash file */ +static int fs; /* file size */ +static uint32_t *fm; /* mmap'd file */ + +void dump_file_descriptor(char * fn) +{ + char * n = malloc(strlen(fn) + 11); + snprintf(n, strlen(fn) + 11, "%s.descr.bin", fn); + printf("\n"); + printf("+++ dumping %s ... ", n); + int fh = open(n, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); + free(n); + if (fh < 0) + { + printf("ERROR: couldn't open(%s): %s\n", n, strerror(errno)); + exit(1); + } + + int ret; + ret = write(fh, &fm[frba.reg0_base >> 2], frba.reg0_limit); + if (ret != frba.reg0_limit) + { + printf("FAILED.\n"); + exit(1); + } + + printf("done.\n"); + + close(fh); +} + +void dump_file_BIOS(char * fn) +{ + char * n = malloc(strlen(fn) + 10); + snprintf(n, strlen(fn) + 10, "%s.BIOS.bin", fn); + printf("\n"); + printf("+++ dumping %s ... ", n); + int fh = open(n, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); + free(n); + if (fh < 0) + { + printf("ERROR: couldn't open(%s): %s\n", n, strerror(errno)); + exit(1); + } + + int ret; + ret = write(fh, &fm[frba.reg1_base >> 2], frba.reg1_limit); + if (ret != frba.reg1_limit) + { + printf("FAILED.\n"); + exit(1); + } + + printf("done.\n"); + + close(fh); +} + +void dump_file_ME(char * fn) +{ + char * n = malloc(strlen(fn) + 8); + snprintf(n, strlen(fn) + 8, "%s.ME.bin", fn); + printf("\n"); + printf("+++ dumping %s ... ", n); + int fh = open(n, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); + free(n); + if (fh < 0) + { + printf("ERROR: couldn't open(%s): %s\n", n, strerror(errno)); + exit(1); + } + + int ret; + ret = write(fh, &fm[frba.reg2_base >> 2], frba.reg2_limit); + if (ret != frba.reg2_limit) + { + printf("FAILED.\n"); + exit(1); + } + + printf("done.\n"); + + close(fh); +} + +void dump_file_GbE(char * fn) +{ + char * n = malloc(strlen(fn) + 9); + snprintf(n, strlen(fn) + 9, "%s.GbE.bin", fn); + printf("\n"); + printf("+++ dumping %s ... ", n); + int fh = open(n, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); + free(n); + if (fh < 0) + { + printf("ERROR: couldn't open(%s): %s\n", n, strerror(errno)); + exit(1); + } + + int ret; + ret = write(fh, &fm[frba.reg3_base >> 2], frba.reg3_limit); + if (ret != frba.reg3_limit) + { + printf("FAILED.\n"); + exit(1); + } + + printf("done.\n"); + uint8_t * pMAC = (uint8_t *) &fm[frba.reg3_base >> 2]; + printf("the MAC-address might be: %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", + pMAC[0], + pMAC[1], + pMAC[2], + pMAC[3], + pMAC[4], + pMAC[5] + ); + + close(fh); +} + +void dump_files(char * n) +{ + printf("=== dumping section files ===\n"); + if (frba.reg0_limit) + dump_file_descriptor(n); + if (frba.reg1_limit) + dump_file_BIOS(n); + if (frba.reg2_limit) + dump_file_ME(n); + if (frba.reg3_limit) + dump_file_GbE(n); +} + +void usage(char ** argv, char* error) +{ + printf("%s\n", error); + printf("\n"); + printf("usage: '%s <bios image file> [-d]'\n", argv[0]); + printf("\n"); + printf("\twhere <bios image file> isn't actually a BIOS image, but the SPI flash\n"); + printf("\tcontents of the SPI connected to your intel chipset.\n"); + printf("\tIn case that image is really in descriptor mode (a.k.a soft-strap)\n"); + printf("\t%s will pretty print all relevant information.\n", argv[0]); + printf("\tIf '-d' is specified as the second parameter some sections such as\n"); + printf("\tthe real BIOS image as seen by the CPU or a GbE blob that is\n"); + printf("\trequired to initialize your ICH GbE are also dumped to files.\n"); + exit(1); +} + +int main(int argc, char **argv) +{ + if (argc < 2) + usage(argv, "Need at least one parameter"); + f = open(argv[1], O_RDONLY); + if (f < 0) + usage(argv, "No such file"); + if (argc >= 3 && (strcmp("-d", argv[2]) == 0)) + usage(argv, "Bogus second argument"); + + fs = lseek(f, 0, SEEK_END); + if (fs < 0) + usage(argv, "Seeking to the end of the file failed"); + + fm = mmap(NULL, fs, PROT_READ, MAP_PRIVATE, f, 0); + if (fm == (void *) -1) + { + /* fallback for stupid OSes like cygwin */ + int ret; + fm = malloc(fs); + if (!fm) + usage(argv, "Could not allocate memory"); + lseek(f, 0, SEEK_SET); + ret = read(f, fm, fs); + if (ret != fs) + usage(argv, "Seeking to the end of the file failed"); + } + printf("flash image is %d [0x%x] bytes\n", fs, fs); + close(f); + + if(read_ich_descriptors_from_dump(fm)){ + printf("not in descriptor mode\n"); + exit(1); + } + + pretty_print_ich_descriptors(); + + if (argc >= 3) + dump_files(argv[1]); + + return 0; +} + -- 1.7.1

1 0

[PATCH 6/7] add missing ICH9 register macros and use them to eliminate magic numbers
by Stefan Tauner 23 May '11

23 May '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 59 +++++++++++++++++++++++++++++++++++------------------------ 1 files changed, 35 insertions(+), 24 deletions(-) diff --git a/ichspi.c b/ichspi.c index eb9cc7e..df44373 100644 --- a/ichspi.c +++ b/ichspi.c @@ -77,6 +77,15 @@ #define ICH9_REG_FADDR 0x08 /* 32 Bits */ #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ +#define ICH9_REG_FRAP 0x50 /* 32 Bytes Flash Region Access Permissions */ +#define ICH9_REG_FREG0 0x54 /* 32 Bytes Flash Region 0 */ + +#define ICH9_REG_PR0 0x74 /* 32 Bytes Protected Range 0 */ +#define ICH9_REG_PR1 0x78 /* 32 Bytes Protected Range 1 */ +#define ICH9_REG_PR2 0x7c /* 32 Bytes Protected Range 2 */ +#define ICH9_REG_PR3 0x80 /* 32 Bytes Protected Range 3 */ +#define ICH9_REG_PR4 0x84 /* 32 Bytes Protected Range 4 */ + #define ICH9_REG_SSFS 0x90 /* 08 Bits */ #define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */ #define SSFS_SCIP (0x1 << SSFS_SCIP_OFF) @@ -117,6 +126,9 @@ #define ICH9_REG_OPTYPE 0x96 /* 16 Bits */ #define ICH9_REG_OPMENU 0x98 /* 64 Bits */ +#define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */ +#define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */ + // ICH9R SPI commands #define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0 #define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1 @@ -537,7 +549,6 @@ static int program_opcodes(OPCODES *op, int enable_undo) */ void ich_set_bbar(uint32_t minaddr) { -#define BBAR_MASK 0x00ffff00 minaddr &= BBAR_MASK; switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: @@ -556,13 +567,13 @@ void ich_set_bbar(uint32_t minaddr) msg_perr("Setting BBAR failed!\n"); break; case SPI_CONTROLLER_ICH9: - ichspi_bbar = mmio_readl(ich_spibar + 0xA0) & ~BBAR_MASK; - if (ichspi_bbar) + ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR) & ~BBAR_MASK; + if (ichspi_bbar) { msg_pdbg("Reserved bits in BBAR not zero: 0x%04x", ichspi_bbar); ichspi_bbar |= minaddr; - rmmio_writel(ichspi_bbar, ich_spibar + 0xA0); - ichspi_bbar = mmio_readl(ich_spibar + 0xA0); + rmmio_writel(ichspi_bbar, ich_spibar + ICH9_REG_BBAR); + ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); /* We don't have any option except complaining. And if the write * failed, the restore will fail as well, so no problem there. */ @@ -1137,7 +1148,7 @@ static void do_ich9_spi_frap(uint32_t frap, int i) uint32_t base, limit; int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) | (((ICH_BRRA(frap) >> i) & 1) << 0); - int offset = 0x54 + i * 4; + int offset = ICH9_REG_FREG0 + i * 4; uint32_t freg = mmio_readl(ich_spibar + offset); msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n", @@ -1247,19 +1258,19 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, ich_init_opcodes(); break; case SPI_CONTROLLER_ICH9: - tmp2 = mmio_readw(ich_spibar + 4); + tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); prettyprint_ich9_reg_hsfs(tmp2); - if (tmp2 & (1 << 15)) { + if (tmp2 & HSFS_FLOCKDN) { msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } - tmp2 = mmio_readw(ich_spibar + 6); + tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); prettyprint_ich9_reg_hsfc(tmp2); - tmp = mmio_readl(ich_spibar + 0x50); + tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP); msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); @@ -1271,39 +1282,39 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, do_ich9_spi_frap(tmp, i); msg_pdbg("0x74: 0x%08x (PR0)\n", - mmio_readl(ich_spibar + 0x74)); + mmio_readl(ich_spibar + ICH9_REG_PR0)); msg_pdbg("0x78: 0x%08x (PR1)\n", - mmio_readl(ich_spibar + 0x78)); + mmio_readl(ich_spibar + ICH9_REG_PR1)); msg_pdbg("0x7C: 0x%08x (PR2)\n", - mmio_readl(ich_spibar + 0x7C)); + mmio_readl(ich_spibar + ICH9_REG_PR2)); msg_pdbg("0x80: 0x%08x (PR3)\n", - mmio_readl(ich_spibar + 0x80)); + mmio_readl(ich_spibar + ICH9_REG_PR3)); msg_pdbg("0x84: 0x%08x (PR4)\n", - mmio_readl(ich_spibar + 0x84)); + mmio_readl(ich_spibar + ICH9_REG_PR4)); - tmp = mmio_readl(ich_spibar + 0x90); + tmp = mmio_readl(ich_spibar + ICH9_REG_SSFS); msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff); prettyprint_ich9_reg_ssfs(tmp); - if (tmp & (1 << 3)) { + if (tmp & SSFS_FCERR) { msg_pdbg("Clearing SSFS.FCERR\n"); - mmio_writeb(1 << 3, ich_spibar + 0x90); + mmio_writeb(SSFS_FCERR, ich_spibar + ICH9_REG_SSFS); } msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp >> 8); prettyprint_ich9_reg_ssfc(tmp); msg_pdbg("0x94: 0x%04x (PREOP)\n", - mmio_readw(ich_spibar + 0x94)); + mmio_readw(ich_spibar + ICH9_REG_PREOP)); msg_pdbg("0x96: 0x%04x (OPTYPE)\n", - mmio_readw(ich_spibar + 0x96)); + mmio_readw(ich_spibar + ICH9_REG_OPTYPE)); msg_pdbg("0x98: 0x%08x (OPMENU)\n", - mmio_readl(ich_spibar + 0x98)); + mmio_readl(ich_spibar + ICH9_REG_OPMENU)); msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", - mmio_readl(ich_spibar + 0x9C)); - ichspi_bbar = mmio_readl(ich_spibar + 0xA0); + mmio_readl(ich_spibar + ICH9_REG_OPTYPE + 4)); + ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); msg_pdbg("0xA0: 0x%08x (BBAR)\n", ichspi_bbar); msg_pdbg("0xB0: 0x%08x (FDOC)\n", - mmio_readl(ich_spibar + 0xB0)); + mmio_readl(ich_spibar + ICH9_REG_FDOC)); ich_init_opcodes(); break; default: -- 1.7.1

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[PATCH 5/7] warn if SMM BIOS Write Protection is detected in BIOS_CNTL
by Stefan Tauner 23 May '11

23 May '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipset_enable.c | 12 +++++++++++- 1 files changed, 11 insertions(+), 1 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index 83b49ad..339c6bb 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -264,8 +264,18 @@ static int enable_flash_ich(struct pci_dev *dev, const char *name, (old & (1 << 0)) ? "en" : "dis"); msg_pdbg("BIOS_CNTL is 0x%x\n", old); - new = old | 1; + /* + * Quote from the 6 Series datasheet: + * "5: SMM BIOS Write Protect Disable (SMM_BWP) + * 1 = BIOS region SMM protection is enabled. + * The BIOS Region is not writable unless all processors are in SMM." + * In earlier chipsets this bit is reserved. */ + if (old & (5 << 1)) { + msg_pinfo("WARNING: BIOS region SMM protection is enabled!\n"); + return -1; + } + new = old | 1; if (new == old) return 0; -- 1.7.1

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