- flashrom - mail.coreboot.org

hi
by garrraaahyyy＠gmail.com 31 May '11

31 May '11

hey, you'll never see another opportunity like this http://g.msn.com.br/BR9/1369.0?http://cnbc7.com/news

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asus p4p800 error while flashing
by Yura I 31 May '11

31 May '11

Hi. I got an error while flashing asus p4p800 motherboard on ubuntu 10.04: $ sudo flashrom -w P4C800-ASUS-Entry-1021.005 flashrom v0.9.1-r946 No coreboot table found. Found chipset "Intel ICH5/ICH5R", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash chip... ERASE FAILED at 0x00000ae8! Expected=0xff, Read=0x44, failed byte count from 0x00000000-0x00000fff: 0x4fb ERASE FAILED! ERASE FAILED at 0x00000ae8! Expected=0xff, Read=0x44, failed byte count from 0x00000000-0x0000ffff: 0xf419 ERASE FAILED! FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! Old bios is saved. Computer isnt rebooted. Can you help me? Yuri

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Re: [flashrom] asus p4p800 error while flashing
by Paul Menzel 31 May '11

31 May '11

Dear Yuri, please always reply to the list and use interleaved quoting style [3]. I put your address into CC not being sure if you are following the list. Am Dienstag, den 31.05.2011, 13:22 +0400 schrieb Yura I: > Thaks for answer. I have compiled the latest version from snv. And got > still same error: Strange. > $ sudo flashrom -w P4P81019.rom > flashrom v0.9.3-r1322 on Linux 2.6.32-32-generic-pae (i686), built with > libpci 3.0.0, GCC 4.4.3, little endian > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > Found chipset "Intel ICH5/ICH5R", enabling flash write... OK. > This chipset supports the following protocols: FWH. > WARNING: Your mainboard is ASUS P4P800, but the mainboard-specific > code has not been tested, and thus will not be executed by default. > Depending on your hardware environment, erasing, writing or even probing > can fail without running the board specific code. > > Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection > "internal programmer") for details. > Found chip "SST SST49LF004A/B" (512 kB, FWH) at physical address 0xfff80000. > Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. > Erasing and writing flash chip... ERASE FAILED at 0x00000ae8! > Expected=0xff, Read=0x44, failed byte count from 0x00000000-0x00000fff: > 0x4fb > ERASE FAILED! > ERASE FAILED at 0x00000ae8! Expected=0xff, Read=0x44, failed byte count > from 0x00000000-0x0000ffff: 0xf419 > ERASE FAILED! > Ошибка сегментирования > > Last translated message is "Segmentation fault". It should definitely not segfault. But this is where my knowledge stops and I have no time to look into this. You should definitely join the IRC channel. I do not know how scared you are but probably nothing fatal happened since no write was allowed or took place. But you should wait for the experts to tell you what to do. Thanks, Paul [3] http://en.opensuse.org/openSUSE:Mailing_list_netiquette

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Re: [flashrom] Intel SandyBridge serie 6 chipsets support
by Stefan Tauner 31 May '11

31 May '11

On Mon, 30 May 2011 13:57:21 +0200 Mohammed-Amine.Rebai(a)bull.net wrote: > Hallo Stefan, hello! > Wir könnten eigentlich deutsch sprechen ;). we could, but it would upset those nasty dutch people and all those who cant make any sense out of german even more ;) i tricked your client to reply not directly to me but to the mailing list with a special header in my email so that everyone else can read your replies too (and answer them). that is because often people (new to mailing lists or just unwary) just reply to the sender and not to the list as well (you did so too in your reply to idwer). usually there is a button or menu entry to "reply to all" which also includes previously "cc:"-tagged addresses in your reply. hth > Ja, unsere Kunden benützen auch flashrom. Wir haben usere EFI shell > flashing tool, aber die Kunden benützen das Linux Shell am liebsten, > besonders wenn du viele Clusters/Servers flashen muss. understandable :) > Aber mein Problem ist vor diesen Sachen. « chipset_flash_enable » findet > nicht das PCH: > « This chipset supports the following protocols: Non-SPI. WARNING: > No chipset found. Flash detection will most likely fail. » > > und das PCH device_id (Vendor ID:0x8086, Device ID:0x244e ) existiert > nicht in das «chipset_enables » stuct. ( mein PCH heisst Patsburg oder > C200 chipset ). ah ok i was not aware that those are missing. my laptop is based on ibex peak/QS57 and i have not checked if the newer ones are actually there. i will put that on my todo list. > Wenn ich « enable_flash_ich10 » Funktion nötige, es funkioniert auch > nicht. > Maximum FWH chip size: 0x0 bytes BIOS Lock Enable: > disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 tried to set 0xdc > to 0x1 on ICH10 failed (WARNING ONLY) Root Complex Register Block > address = 0x0 Error accessing ICH RCRB, 0x4000 bytes at 0x00000000 > /dev/mem mmap failed: Resource temporarily unavailable ok that certainly does not look right. could you please send us a full log of the output of flashrom -VV with the added pci id please? > Ich werde vielleicht eine neue funktion schreiben ;). that would of course be very appreciated. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Intel SandyBridge serie 6 chipsets support
by Idwer Vollering 30 May '11

30 May '11

2011/5/30 <Mohammed-Amine.Rebai(a)bull.net>: > Dear Mr Vollering, > > I am sorry for the language mixing, I was not aware that other people than > my replier ( Stefan Tauner ) would receive my answer. That is the difference between replying and replying to all recipients ;) > Due to his informal answer ( smiles etc ) I tried to answer back the same way. > > As a Bios engineer, as far as I know, we only use your software to flash the > Bios in some cases where we are under Linux. Our usual way to flash our > machines is a Bios Integrated utility under EFI Shell. > > Thanks again for your help and for the nice job you are doing. Thanks. The build you're offering (flashrom-bin-x86_64-20081003.tar) looks outdated though, it is from 2008 and targets 64-bit hardware only. Is that on purpose, e.g. you exclusively sell 64-bit hardware? > > Best Regards > Amine Rebai > > > > > > > > De : Idwer Vollering <vidwer(a)gmail.com> > A : Mohammed-Amine.Rebai(a)bull.net > Cc : flashrom(a)flashrom.org > Date : 30/05/2011 15:15 > Objet : Re: [flashrom] Intel SandyBridge serie 6 chipsets support > ________________________________ > > > 2011/5/30 <Mohammed-Amine.Rebai(a)bull.net>: >> Hallo Stefan, >> >> Wir könnten eigentlich deutsch sprechen ;). >> >> Ja, unsere Kunden benützen auch flashrom. Wir haben usere EFI shell >> flashing >> tool, aber die Kunden benützen das Linux Shell am liebsten, besonders wenn >> du viele Clusters/Servers flashen muss. >> >> Stimmt, das SPI interface in « Intel Chipset Serie 6 » ist fast wie die >> vorausgegangen. Es gibt ME protection und special « unlocking sequence » >> mit >> special opcodes. >> >> Aber mein Problem ist vor diesen Sachen. « chipset_flash_enable » findet >> nicht das PCH: >> « This chipset supports the following protocols: Non-SPI. >> WARNING: No chipset found. Flash detection will most likely fail. » >> >> und das PCH device_id (Vendor ID:0x8086, Device ID:0x244e ) existiert >> nicht >> in das «chipset_enables » stuct. ( mein PCH heisst Patsburg oder C200 >> chipset ). >> >> Wenn ich « enable_flash_ich10 » Funktion nötige, es funkioniert auch >> nicht. >> Maximum FWH chip size: 0x0 bytes BIOS Lock Enable: >> disabled, >> BIOS Write Enable: disabled, BIOS_CNTL is 0x0 tried to set 0xdc to >> 0x1 on ICH10 failed (WARNING ONLY) Root Complex Register Block >> address = 0x0 Error accessing ICH RCRB, 0x4000 bytes at 0x00000000 >> /dev/mem mmap failed: Resource temporarily unavailableIch werde >> vielleicht eine neue funktion schreiben ;). >> Vielen Dank. >> >> Mit freundlichen Grüßen >> Amine Rebai > > It is not very "freundlich" (friendly) to write a reply in an other > language than English, given the fact that your first message was > written in English. > > Also, the download named flashrom-bin-x86_64-20081003.tar [1] is > behind a 'paywall' / customer login. There is no trace of "flashrom is > GPL software" at that website, where can anyone download, if there are > any, your patches? > > Thanks, > Idwer > > [1] > http://support.bull.com/ols/product/platforms/hw-extremcomp/bullx-R/dl/tool… > >> >> >> >> >> De : Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> >> A : Mohammed-Amine.Rebai(a)bull.net >> Cc : flashrom(a)flashrom.org >> Date : 27/05/2011 20:02 >> Objet : Re: [flashrom] Intel SandyBridge serie 6 chipsets support >> ________________________________ >> >> >> On Fri, 27 May 2011 14:58:57 +0200 >> Mohammed-Amine.Rebai(a)bull.net wrote: >> >>> Dear Flahsrom representant, >> hello! >> >>> I am a Bios engineer at BULL, a major european server and supercomputer >>> company «www.bull.com » . >>> >>> First of all, I would like to thank you for the great job you are doing, >>> we use your utility a lot. >> nice to hear that, thank you. is it offered to your customers too? >> >>> I would like to know if you are planning to support the Bios SPI flash >>> flashing on the Intel SandyBridge architecture, especially the Intel 6 >>> series chipset/C200/Patsburg platform controller hub? >> >> the spi interface of the 6 series chipset is very similar to the >> previous ones and as long as there is no locking in place (i am talking >> about PR0-PR4 and related "security" stuff) it may already work, have >> you tried it? >> >> in case of locking in place (that might be a requirement in nowadays >> chipsets due to the requirement of using the ME) flashrom would not >> work yet. i am working on this problem within the scope of my google >> summer of code project which should be completed by the end of summer. >> dont hold your breath though please ;) >> >> -- >> Kind regards/Mit freundlichen Grüßen, Stefan Tauner >> >> >> _______________________________________________ >> flashrom mailing list >> flashrom(a)flashrom.org >> http://www.flashrom.org/mailman/listinfo/flashrom >> > >

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Re: [flashrom] Intel SandyBridge serie 6 chipsets support
by Idwer Vollering 30 May '11

30 May '11

2011/5/30 <Mohammed-Amine.Rebai(a)bull.net>: > Hallo Stefan, > > Wir könnten eigentlich deutsch sprechen ;). > > Ja, unsere Kunden benützen auch flashrom. Wir haben usere EFI shell flashing > tool, aber die Kunden benützen das Linux Shell am liebsten, besonders wenn > du viele Clusters/Servers flashen muss. > > Stimmt, das SPI interface in « Intel Chipset Serie 6 » ist fast wie die > vorausgegangen. Es gibt ME protection und special « unlocking sequence » mit > special opcodes. > > Aber mein Problem ist vor diesen Sachen. « chipset_flash_enable » findet > nicht das PCH: > « This chipset supports the following protocols: Non-SPI. > WARNING: No chipset found. Flash detection will most likely fail. » > > und das PCH device_id (Vendor ID:0x8086, Device ID:0x244e ) existiert nicht > in das «chipset_enables » stuct. ( mein PCH heisst Patsburg oder C200 > chipset ). > > Wenn ich « enable_flash_ich10 » Funktion nötige, es funkioniert auch nicht. > Maximum FWH chip size: 0x0 bytes BIOS Lock Enable: disabled, > BIOS Write Enable: disabled, BIOS_CNTL is 0x0 tried to set 0xdc to > 0x1 on ICH10 failed (WARNING ONLY) Root Complex Register Block > address = 0x0 Error accessing ICH RCRB, 0x4000 bytes at 0x00000000 > /dev/mem mmap failed: Resource temporarily unavailableIch werde > vielleicht eine neue funktion schreiben ;). > Vielen Dank. > > Mit freundlichen Grüßen > Amine Rebai It is not very "freundlich" (friendly) to write a reply in an other language than English, given the fact that your first message was written in English. Also, the download named flashrom-bin-x86_64-20081003.tar [1] is behind a 'paywall' / customer login. There is no trace of "flashrom is GPL software" at that website, where can anyone download, if there are any, your patches? Thanks, Idwer [1] http://support.bull.com/ols/product/platforms/hw-extremcomp/bullx-R/dl/tool… > > > > > De : Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > A : Mohammed-Amine.Rebai(a)bull.net > Cc : flashrom(a)flashrom.org > Date : 27/05/2011 20:02 > Objet : Re: [flashrom] Intel SandyBridge serie 6 chipsets support > ________________________________ > > > On Fri, 27 May 2011 14:58:57 +0200 > Mohammed-Amine.Rebai(a)bull.net wrote: > >> Dear Flahsrom representant, > hello! > >> I am a Bios engineer at BULL, a major european server and supercomputer >> company «www.bull.com » . >> >> First of all, I would like to thank you for the great job you are doing, >> we use your utility a lot. > nice to hear that, thank you. is it offered to your customers too? > >> I would like to know if you are planning to support the Bios SPI flash >> flashing on the Intel SandyBridge architecture, especially the Intel 6 >> series chipset/C200/Patsburg platform controller hub? > > the spi interface of the 6 series chipset is very similar to the > previous ones and as long as there is no locking in place (i am talking > about PR0-PR4 and related "security" stuff) it may already work, have > you tried it? > > in case of locking in place (that might be a requirement in nowadays > chipsets due to the requirement of using the ME) flashrom would not > work yet. i am working on this problem within the scope of my google > summer of code project which should be completed by the end of summer. > dont hold your breath though please ;) > > -- > Kind regards/Mit freundlichen Grüßen, Stefan Tauner > > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom >

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Success: MSI G31TM-P21 (MS-7529)
by Peter Lemenkov 30 May '11

30 May '11

Hello. I just successfully reflashed one MSI board. work ~/7529v46: sudo flashrom -w A7529IMS.460 flashrom v0.9.3-r1299 on Linux 2.6.38.6-27.fc15.x86_64 (x86_64), built with libpci 3.1.7, GCC 4.6.0 20110428 (Red Hat 4.6.0-6), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "Intel ICH7/ICH7R", enabling flash write... OK. This chipset supports the following protocols: SPI. Found chip "Winbond W25Q80" (1024 KB, SPI) at physical address 0xfff00000. Flash image seems to be a legacy BIOS. Disabling checks. Erasing and writing flash chip... Done. Verifying flash... VERIFIED. work ~/7529v46: http://msi.com/product/mb/G31TM-P21.html -- With best regards, Peter Lemenkov.

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[PATCH] Macronix MX25L6445E
by Wagner, Helge (GE Intelligent Platforms) 30 May '11

30 May '11

Hi, i have tried to reprogram a Macronix MX25L6445E flash chip. This worked, but gave me an error message: ERASE FAILED at 0x0001107f! Expected=0xff, Read=0x00, failed byte count from 0x00010000-0x0001ffff: 0x9c15 ERASE FAILED! Looking deeper into the datasheet, i saw that the MX25L6445E has the same ID as the MX25L6405, but with (at least) one difference: The MX25L6405 has a block size of 64KByte for erase function 20h, while the MX25L6445E is using 4KByte sector size for the same erase function 20h. As a result the spi_block_erase_20() will fail for the MX25L6445E (while the spi_block_erase_d8() which is used then will succeed). I have now re-ordered the erase functions for the MX25L6405/MX25L6445E: spi_block_erase_d8 - first spi_block_erase_60 - second spi_block_erase_c7 - third spi_block_erase_20 - last So if one of the d8/60/c7 erase functions are successfull, the spi_block_erase_20 will never be called. To be sure that the spi_block_erase_20 works for both the MX25L6405 and the MX25L6445E, we could change the block erase size from 64K to 4K. This should work even for the MX25L6405, but with the side effect of the erase taking longer than needed. Any comments? Please find my patches included. Signed-off-by: Helge Wagner <Helge.Wagner(a)ge.com> Regards, Helge Helge Wagner Software Engineer GE Intelligent Platforms

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Re: [flashrom] Intel SandyBridge serie 6 chipsets support
by Stefan Tauner 30 May '11

30 May '11

On Fri, 27 May 2011 14:58:57 +0200 Mohammed-Amine.Rebai(a)bull.net wrote: > Dear Flahsrom representant, hello! > I am a Bios engineer at BULL, a major european server and supercomputer > company «www.bull.com » . > > First of all, I would like to thank you for the great job you are doing, > we use your utility a lot. nice to hear that, thank you. is it offered to your customers too? > I would like to know if you are planning to support the Bios SPI flash > flashing on the Intel SandyBridge architecture, especially the Intel 6 > series chipset/C200/Patsburg platform controller hub? the spi interface of the 6 series chipset is very similar to the previous ones and as long as there is no locking in place (i am talking about PR0-PR4 and related "security" stuff) it may already work, have you tried it? in case of locking in place (that might be a requirement in nowadays chipsets due to the requirement of using the ME) flashrom would not work yet. i am working on this problem within the scope of my google summer of code project which should be completed by the end of summer. dont hold your breath though please ;) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] SST25VF064C on GE Intelligent Platforms CR12/VR12/EC12 board family
by Stefan Tauner 29 May '11

29 May '11

On Sat, 28 May 2011 17:50:28 +0200 "Wagner, Helge (GE Intelligent Platforms)" <Helge.Wagner(a)ge.com> wrote: > the SST25VF064C is still marked as untested for WRITE in r1320. hello thanks for your report! i have marked the SST49LF020 as fully supported and will commit it later. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH 00/11] ichspi patches 4.0 - logs showing the new output
by Stefan Tauner 29 May '11

29 May '11

the two logs appended show the differences in the output between current head (r1322) and after all of these have been applied. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH 01/11] improve macros for SSFS and SSFC bits
by Carl-Daniel Hailfinger 28 May '11

28 May '11

Am 28.05.2011 05:38 schrieb Stefan Tauner: > - introduce offset macros and use them to (re)define the existing mask macros > - add comments > - rename SSFS_CDS to SSFS_FDONE (abbr. used in datasheet not in SSFS but HSFS) > - use those for refactoring and magic number elemination. > - following patch uses them for pretty printing > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > ichspi.c | 48 ++++++++++++++++++++++++++++++------------------ > 1 files changed, 30 insertions(+), 18 deletions(-) > > diff --git a/ichspi.c b/ichspi.c > index 299cbf3..676b93a 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -47,24 +47,36 @@ > #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ > > #define ICH9_REG_SSFS 0x90 /* 08 Bits */ > -#define SSFS_SCIP 0x00000001 > -#define SSFS_CDS 0x00000004 > -#define SSFS_FCERR 0x00000008 > -#define SSFS_AEL 0x00000010 > +#define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */ > +#define SSFS_SCIP (0x1 << SSFS_SCIP_OFF) > This is probably a philosophical question, but should we use #define SSFS_SCIP (0x1 << 0) instead and skip definition of all *_OFF #defines? I don't have a good answer, so I'm hoping you can tell me which one is better. > +#define SSFS_FDONE_OFF 2 /* Cycle Done Status */ > +#define SSFS_FDONE (0x1 << SSFS_FDONE_OFF) > +#define SSFS_FCERR_OFF 3 /* Flash Cycle Error */ > +#define SSFS_FCERR (0x1 << SSFS_FCERR_OFF) > +#define SSFS_AEL_OFF 4 /* Access Error Log */ > +#define SSFS_AEL (0x1 << SSFS_AEL_OFF) > /* The following bits are reserved in SSFS: 1,5-7. */ > #define SSFS_RESERVED_MASK 0x000000e2 > > #define ICH9_REG_SSFC 0x91 /* 24 Bits */ > -#define SSFC_SCGO 0x00000200 > -#define SSFC_ACS 0x00000400 > -#define SSFC_SPOP 0x00000800 > -#define SSFC_COP 0x00001000 > -#define SSFC_DBC 0x00010000 > -#define SSFC_DS 0x00400000 > -#define SSFC_SME 0x00800000 > -#define SSFC_SCF 0x01000000 > -#define SSFC_SCF_20MHZ 0x00000000 > -#define SSFC_SCF_33MHZ 0x01000000 > +#define SSFC_SCGO_OFF (1 + 8) /* 1: SPI Cycle Go */ > +#define SSFC_SCGO (0x1 << SSFC_SCGO_OFF) > +#define SSFC_ACS_OFF (2 + 8) /* 2: Atomic Cycle Sequence */ > +#define SSFC_ACS (0x1 << SSFC_ACS_OFF) > +#define SSFC_SPOP_OFF (3 + 8) /* 3: Sequence Prefix Opcode Pointer */ > +#define SSFC_SPOP (0x1 << SSFC_SPOP_OFF) > +#define SSFC_COP_OFF (4 + 8) /* 4-6: Cycle Opcode Pointer */ > +#define SSFC_COP (0x7 << SSFC_COP_OFF) > +#define SSFC_DBC_OFF (8 + 8) /* 8-13: Data Byte Count */ > +#define SSFC_DBC (0x3f << SSFC_DBC_OFF) > +#define SSFC_DS_OFF (14 + 8) /* 14: Data Cycle */ > +#define SSFC_DS (0x1 << SSFC_DS_OFF) > +#define SSFC_SME_OFF (15 + 8) /* 15: SPI SMI# Enable */ > +#define SSFC_SME (0x1 << SSFC_SME_OFF) > +#define SSFC_SCF_OFF (16 + 8) /* 16-18: SPI Cycle Frequency */ > +#define SSFC_SCF (0x7 << SSFC_SCF_OFF) > +#define SSFC_SCF_20MHZ 0x00000000 > +#define SSFC_SCF_33MHZ 0x01000000 > /* We combine SSFS and SSFC to one 32-bit word, > * therefore SSFC bits are off by 8. > * The following bits are reserved in SSFC: 23-19,7,0. */ > @@ -709,8 +721,8 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, > temp32 = REGREAD32(ICH9_REG_SSFS); > /* Keep reserved bits only */ > temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; > - /* clear error status registers */ > - temp32 |= (SSFS_CDS + SSFS_FCERR); > + /* Clear cycle done and cycle error status registers */ > + temp32 |= (SSFS_FDONE + SSFS_FCERR); > Odd. Did we really have + instead of | here? That looks wrong (yes, technically it is correct, but still, it suggests that the values are numeric instead of individual bits). Now that you're touching that code, could you fix it to use | instead? And please fix an earlier occurence of temp16 |= (SPIS_CDS + SPIS_FCERR) as well. Thanks! > REGWRITE32(ICH9_REG_SSFS, temp32); > > /* Use 20 MHz */ > @@ -720,7 +732,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, > if (datalength != 0) { > uint32_t datatemp; > temp32 |= SSFC_DS; > - datatemp = ((uint32_t) ((datalength - 1) & 0x3f)) << (8 + 8); > + datatemp = (uint32_t) (((datalength - 1) << SSFC_DBC_OFF) & SSFC_DBC); > Are you really 100% sure that integer promotion rules allow that? datalength is uint8_t, and shifting it directly by 8 bits or more may result in undefined behaviour. Need to check that with a C guru. > temp32 |= datatemp; > } > > Rest looks good. Once the _OFF stuff is decided and once we are 100% sure that the integer promotion rules are applied correctly, this is Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH 06/11] add missing ICH9 register macros and use them to eliminate magic numbers
by Carl-Daniel Hailfinger 28 May '11

28 May '11

Am 28.05.2011 05:38 schrieb Stefan Tauner: > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > ichspi.c | 63 ++++++++++++++++++++++++++++++++++++------------------------- > 1 files changed, 37 insertions(+), 26 deletions(-) > > diff --git a/ichspi.c b/ichspi.c > index dff6f32..584cab4 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -77,6 +77,15 @@ > #define ICH9_REG_FADDR 0x08 /* 32 Bits */ > #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ > > +#define ICH9_REG_FRAP 0x50 /* 32 Bytes Flash Region Access Permissions */ > +#define ICH9_REG_FREG0 0x54 /* 32 Bytes Flash Region 0 */ > + > +#define ICH9_REG_PR0 0x74 /* 32 Bytes Protected Range 0 */ > +#define ICH9_REG_PR1 0x78 /* 32 Bytes Protected Range 1 */ > +#define ICH9_REG_PR2 0x7c /* 32 Bytes Protected Range 2 */ > +#define ICH9_REG_PR3 0x80 /* 32 Bytes Protected Range 3 */ > +#define ICH9_REG_PR4 0x84 /* 32 Bytes Protected Range 4 */ > + > #define ICH9_REG_SSFS 0x90 /* 08 Bits */ > #define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */ > #define SSFS_SCIP (0x1 << SSFS_SCIP_OFF) > @@ -117,6 +126,9 @@ > #define ICH9_REG_OPTYPE 0x96 /* 16 Bits */ > #define ICH9_REG_OPMENU 0x98 /* 64 Bits */ > > +#define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */ > +#define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */ > + > // ICH9R SPI commands > #define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0 > #define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1 > @@ -537,15 +549,15 @@ static int program_opcodes(OPCODES *op, int enable_undo) > */ > void ich_set_bbar(uint32_t minaddr) > { > -#define BBAR_MASK 0x00ffff00 > minaddr &= BBAR_MASK; > switch (spi_programmer->type) { > case SPI_CONTROLLER_ICH7: > case SPI_CONTROLLER_VIA: > ichspi_bbar = mmio_readl(ich_spibar + 0x50) & ~BBAR_MASK; > - if (ichspi_bbar) > + if (ichspi_bbar) { > msg_pdbg("Reserved bits in BBAR not zero: 0x%04x", > ichspi_bbar); > + } > Was that hunk intentional? We usually avoid {} for single-command if blocks. > ichspi_bbar |= minaddr; > rmmio_writel(ichspi_bbar, ich_spibar + 0x50); > ichspi_bbar = mmio_readl(ich_spibar + 0x50); > @@ -556,13 +568,14 @@ void ich_set_bbar(uint32_t minaddr) > msg_perr("Setting BBAR failed!\n"); > break; > case SPI_CONTROLLER_ICH9: > - ichspi_bbar = mmio_readl(ich_spibar + 0xA0) & ~BBAR_MASK; > - if (ichspi_bbar) > + ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR) & ~BBAR_MASK; > + if (ichspi_bbar) { > msg_pdbg("Reserved bits in BBAR not zero: 0x%04x", > ichspi_bbar); > + } > Same here. > ichspi_bbar |= minaddr; > - rmmio_writel(ichspi_bbar, ich_spibar + 0xA0); > - ichspi_bbar = mmio_readl(ich_spibar + 0xA0); > + rmmio_writel(ichspi_bbar, ich_spibar + ICH9_REG_BBAR); > + ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); > /* We don't have any option except complaining. And if the write > * failed, the restore will fail as well, so no problem there. > */ > @@ -1138,7 +1151,7 @@ static void do_ich9_spi_frap(uint32_t frap, int i) > uint32_t base, limit; > int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) | > (((ICH_BRRA(frap) >> i) & 1) << 0); > - int offset = 0x54 + i * 4; > + int offset = ICH9_REG_FREG0 + i * 4; > uint32_t freg = mmio_readl(ich_spibar + offset); > > msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n", > @@ -1248,19 +1261,19 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > ich_init_opcodes(); > break; > case SPI_CONTROLLER_ICH9: > - tmp2 = mmio_readw(ich_spibar + 4); > + tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); > msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); > prettyprint_ich9_reg_hsfs(tmp2); > - if (tmp2 & (1 << 15)) { > + if (tmp2 & HSFS_FLOCKDN) { > msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); > ichspi_lock = 1; > } > > - tmp2 = mmio_readw(ich_spibar + 6); > + tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); > msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); > prettyprint_ich9_reg_hsfc(tmp2); > > - tmp = mmio_readl(ich_spibar + 0x50); > + tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP); > msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); > msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); > msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); > @@ -1272,39 +1285,37 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > do_ich9_spi_frap(tmp, i); > > msg_pdbg("0x74: 0x%08x (PR0)\n", > - mmio_readl(ich_spibar + 0x74)); > + mmio_readl(ich_spibar + ICH9_REG_PR0)); > msg_pdbg("0x78: 0x%08x (PR1)\n", > - mmio_readl(ich_spibar + 0x78)); > + mmio_readl(ich_spibar + ICH9_REG_PR1)); > msg_pdbg("0x7C: 0x%08x (PR2)\n", > - mmio_readl(ich_spibar + 0x7C)); > + mmio_readl(ich_spibar + ICH9_REG_PR2)); > msg_pdbg("0x80: 0x%08x (PR3)\n", > - mmio_readl(ich_spibar + 0x80)); > + mmio_readl(ich_spibar + ICH9_REG_PR3)); > msg_pdbg("0x84: 0x%08x (PR4)\n", > - mmio_readl(ich_spibar + 0x84)); > + mmio_readl(ich_spibar + ICH9_REG_PR4)); > > - tmp = mmio_readl(ich_spibar + 0x90); > + tmp = mmio_readl(ich_spibar + ICH9_REG_SSFS); > msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff); > prettyprint_ich9_reg_ssfs(tmp); > - if (tmp & (1 << 3)) { > + if (tmp & SSFS_FCERR) { > msg_pdbg("Clearing SSFS.FCERR\n"); > - mmio_writeb(1 << 3, ich_spibar + 0x90); > + mmio_writeb(SSFS_FCERR, ich_spibar + ICH9_REG_SSFS); > } > msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp >> 8); > prettyprint_ich9_reg_ssfc(tmp); > > msg_pdbg("0x94: 0x%04x (PREOP)\n", > - mmio_readw(ich_spibar + 0x94)); > + mmio_readw(ich_spibar + ICH9_REG_PREOP)); > msg_pdbg("0x96: 0x%04x (OPTYPE)\n", > - mmio_readw(ich_spibar + 0x96)); > + mmio_readw(ich_spibar + ICH9_REG_OPTYPE)); > msg_pdbg("0x98: 0x%08x (OPMENU)\n", > - mmio_readl(ich_spibar + 0x98)); > + mmio_readl(ich_spibar + ICH9_REG_OPMENU)); > msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", > - mmio_readl(ich_spibar + 0x9C)); > - ichspi_bbar = mmio_readl(ich_spibar + 0xA0); > + mmio_readl(ich_spibar + ICH9_REG_OPMENU + 4)); > + ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); > msg_pdbg("0xA0: 0x%08x (BBAR)\n", > ichspi_bbar); > - msg_pdbg("0xB0: 0x%08x (FDOC)\n", > - mmio_readl(ich_spibar + 0xB0)); > Why did FDOC disappear? > ich_init_opcodes(); > break; > default: > Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH 04/11] use the max_data_read field of the new spi_programmer struct to simplify run_opcode.
by Carl-Daniel Hailfinger 28 May '11

28 May '11

Am 28.05.2011 05:38 schrieb Stefan Tauner: > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Nice simplification! Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH 03/11] add macros and pretty printing for HSFS and HSFC
by Carl-Daniel Hailfinger 28 May '11

28 May '11

Am 28.05.2011 05:38 schrieb Stefan Tauner: > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Same *_OFF comment as for patch 1/11, and please supply new flashrom verbose output if possible so I can take a look and make sure I didn't miss anything obvious in the review. Apart from that, the patch is OK. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Please commit once *_OFF is sorted out. Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH 02/11] add pretty printing functions for SSFS+SSFC and the OPCODE struct and use them
by Carl-Daniel Hailfinger 28 May '11

28 May '11

Am 28.05.2011 05:38 schrieb Stefan Tauner: > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Looks good so far. Can you please send a snippet of the old and the new output on the same hardware? I'd like to see the differences. Thanks! Regards, Carl-Daniel -- http://www.hailfinger.org/

1 0

[commit] r1322 - trunk
by repository service 28 May '11

28 May '11

Author: stefanct Date: Sun May 29 00:59:05 2011 New Revision: 1322 URL: http://flashrom.org/trac/flashrom/changeset/1322 Log: tiny fix for a small fix there was one line break added too much in the previous commit, sorry. the probing functions need to output at least one '\n' for satisfactory output. that means even in error cases they have to do that. OTOH they should not output a sequence of "\n\n" because it would distort the verbose probing output with empty lines. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/spi25.c Modified: trunk/spi25.c ============================================================================== --- trunk/spi25.c Sat May 28 04:37:14 2011 (r1321) +++ trunk/spi25.c Sun May 29 00:59:05 2011 (r1322) @@ -267,10 +267,8 @@ msg_cdbg("%s: id 0x%x\n", __func__, id2); - if (id2 != flash->model_id) { - msg_cdbg("\n"); + if (id2 != flash->model_id) return 0; - } /* Print the status register to tell the * user about possible write protection.

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SST25VF064C on GE Intelligent Platforms CR12/VR12/EC12 board family
by Wagner, Helge (GE Intelligent Platforms) 28 May '11

28 May '11

Hi, the SST25VF064C is still marked as untested for WRITE in r1320. I have tested it on our CR12/VR12/EC12 board family and found it fully working (see attached logs). Regards, Helge Helge Wagner Software Engineer GE Intelligent Platforms

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[PATCH 11/11] add support for Intel Hardware Sequencing
by Stefan Tauner 27 May '11

27 May '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipdrivers.h | 6 ++ flashchips.c | 40 ++++++++- ichspi.c | 280 ++++++++++++++++++++++++++++++++++++++++++++++++++++++-- programmer.h | 1 + 4 files changed, 316 insertions(+), 11 deletions(-) diff --git a/chipdrivers.h b/chipdrivers.h index 92ddbea..f97e2ad 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -84,6 +84,12 @@ void print_status_82802ab(uint8_t status); int unlock_82802ab(struct flashchip *flash); int unlock_28f004s5(struct flashchip *flash); +/* ichspi.c */ +int ich_hwseq_probe(struct flashchip *flash); +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int start, int len); +int ich_hwseq_block_erase(struct flashchip *flash, unsigned int addr, unsigned int blocklen); +int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); + /* jedec.c */ uint8_t oddparity(uint8_t val); void toggle_ready_jedec(chipaddr dst); diff --git a/flashchips.c b/flashchips.c index a1e3441..42391cd 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8273,7 +8273,44 @@ const struct flashchip flashchips[] = { .write = write_jedec_1, .read = read_memmapped, }, - +#if defined(__i386__) || defined(__x86_64__) + { + .vendor = "Intel", + .name = "Hardware Sequencing", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = INTEL_ID, + .model_id = GENERIC_DEVICE_ID, + .total_size = 4, + .page_size = 256, + .tested = TEST_OK_PR, + .probe = ich_hwseq_probe, + .block_erasers = + { + { + .eraseblocks = { {256, 4 * 4} }, + .block_erase = ich_hwseq_block_erase, + //}, { + //{ + //.eraseblocks = { {256, CHIPSIZE * 4} }, + //.block_erase = ich_hwseq_block_erase, + //}, { + //{ + //.eraseblocks = { {4 * 1024, CHIPSIZE / 4} }, + //.block_erase = ich_hwseq_block_erase, + //}, { + //{ + //.eraseblocks = { {8 * 1024, CHIPSIZE / 8} }, + //.block_erase = ich_hwseq_block_erase, + //}, { + //{ + //.eraseblocks = { {64 * 1024, CHIPSIZE / 64} }, + //.block_erase = ich_hwseq_block_erase, + } + }, + .write = ich_hwseq_write_256, + .read = ich_hwseq_read, + }, +#endif // defined(__i386__) || defined(__x86_64__) { .vendor = "AMIC", .name = "unknown AMIC SPI chip", @@ -8406,6 +8443,7 @@ const struct flashchip flashchips[] = { .probe = probe_spi_rdid, .write = NULL, }, + { .vendor = "Generic", .name = "unknown SPI chip (REMS)", diff --git a/ichspi.c b/ichspi.c index 5bba0ab..8cdcb5c 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1099,6 +1099,240 @@ static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, return result; } +uint32_t ich_hwseq_get_erase_block_size(void) +{ + uint8_t enc_berase = (REGREAD16(ICH9_REG_HSFS) & HSFS_BERASE) >> + HSFS_BERASE_OFF; + const uint32_t dec_berase[4] = { + 256, + 4 * 1024, + 8 * 1024, + 64 * 1024 + }; + return dec_berase[enc_berase]; +} + +int ich_hwseq_probe(struct flashchip *flash) +{ + extern struct flash_descriptor fdbar; + msg_cdbg("Prerequisites for Intel Hardware Sequencing are "); + if (spi_programmer->type == SPI_CONTROLLER_ICH_HWSEQ) { + msg_cdbg("met.\n"); + msg_cdbg("Found %d attached SPI flash chips with a " + "combined density of %d kB.\n", fdbar.NC + 1, + (getFCBA_component_density(0) + + getFCBA_component_density(1)) / 1024); + return 1; + } else { + msg_cdbg("not met.\n"); + return 0; + } +} + +static int ich_hwseq_send_command(unsigned int writecnt, + unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + msg_pdbg("skipped. Intel Hardware Sequencing does not support sending " + "arbitrary commands."); + return -1; +} + +int ich_hwseq_block_erase(struct flashchip *flash, + unsigned int addr, + unsigned int len) +{ + uint32_t erase_block; + uint32_t hsfc; + uint32_t hsfs; + uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */ + + REGWRITE32(ICH9_REG_FADDR, (addr & 0x00FFFFFF)); + erase_block = ich_hwseq_get_erase_block_size(); + if (strcmp(flash->name, "Hardware Sequencing") != 0) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode\n", flash->name); + return -1; + } + + if (len != erase_block) { + msg_cerr("Erase block size for address 0x%06x is %d B, " + "but requested erase block size is %d B. " + "Not erasing anything.\n", + addr, + erase_block, + len); + return -1; + } + + if (addr % erase_block != 0) { + msg_cerr("Erase address 0x%06x is not aligned to the erase " + "block boundary (any multiple of %d). " + "Not erasing anything.\n", + addr, + erase_block); + return -1; + } + + msg_pdbg("erasing %d bytes starting at 0x%06x\n", len, addr); + + hsfc = REGREAD16(ICH9_REG_HSFC); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc = (0x11 << HSFC_FCYCLE_OFF); /* set erase operation */ + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + /* Wait for Cycle Done Status or Flash Cycle Error. */ + while (((REGREAD16(ICH9_REG_HSFS) & + (HSFS_FDONE | HSFS_FCERR)) == 0) && + --timeout) { + programmer_delay(10); + } + if (!timeout) { + msg_perr("timeout, ICH9_REG_HSFS=0x%04x\n", + REGREAD16(ICH9_REG_HSFS)); + return 1; + } + + hsfs = REGREAD16(ICH9_REG_HSFS); + REGWRITE16(ICH9_REG_HSFS, hsfs); /* clear all error bits */ + if (hsfs & HSFS_FCERR) { + msg_perr("Transaction error between offset 0x%06x and 0x%06x + " + "%d (= 0x%06x)!\n", + addr, addr, len, addr+len); + prettyprint_ich9_reg_hsfs(hsfs); + prettyprint_ich9_reg_hsfc(hsfs); + return 1; + } + return 0; +} + +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int addr, int len) +{ + uint32_t *buf32 = (uint32_t *)buf; + uint16_t hsfc = REGREAD16(ICH9_REG_HSFC); + uint16_t hsfs; + uint16_t timeout = 100 * 60; + int i; + + if (strcmp(flash->name, "Hardware Sequencing") != 0) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode\n", flash->name); + return -1; + } + + if (len % 4 != 0) { + msg_perr("Read size has to be a multiple of 4 in hardware" + "sequencing mode\n"); + return -1; + } + + msg_pdbg("reading %d bytes starting at 0x%06x\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + for (i = 0; i < len; i += 4) { + REGWRITE32(ICH9_REG_FADDR, (addr & 0x00FFFFFF)); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* set read operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + hsfc |= (3 << HSFC_FDBC_OFF); /* set byte count to 3+1 */ + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + /* Wait for Cycle Done Status or Flash Cycle Error. */ + while (((REGREAD16(ICH9_REG_HSFS) & + (HSFS_FDONE | HSFS_FCERR)) == 0) && + --timeout) { + programmer_delay(10); + } + if (!timeout) { + msg_perr("timeout, ICH9_REG_HSFS=0x%04x\n", + REGREAD16(ICH9_REG_HSFS)); + return 1; + } + + hsfs = REGREAD16(ICH9_REG_HSFS); + REGWRITE16(ICH9_REG_HSFS, hsfs); /* clear all error bits */ + if (hsfs & HSFS_FCERR) { + msg_perr("Transaction error between offset 0x%06x and " + "0x%06x + %d (= 0x%06x)!\n", + addr, addr, 4, addr + 4); + prettyprint_ich9_reg_hsfs(hsfs); + prettyprint_ich9_reg_hsfc(hsfs); + return 1; + } + + *buf32++ = REGREAD32(ICH9_REG_FDATA0); + addr += 4; + } + return 0; +} + +int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, int addr, int len) +{ + uint32_t *buf32 = (uint32_t *)buf; + uint16_t hsfc = REGREAD16(ICH9_REG_HSFC); + uint16_t hsfs; + uint16_t timeout = 100 * 60; + int i; + if (strcmp(flash->name, "Hardware Sequencing") != 0) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode\n", flash->name); + return -1; + } + + if ((len % 4 != 0)) { + msg_perr("Write size has to be a multiple of 4 in hardware " + "sequencing mode\n"); + return -1; + } + + msg_pdbg("writing %d bytes starting at 0x%06x\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + for (i = 0; i < len; i += 4) { + REGWRITE32(ICH9_REG_FADDR, (addr & 0x00FFFFFF)); + REGWRITE32(ICH9_REG_FDATA0, *buf32++); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc = (0x10 << HSFC_FCYCLE_OFF); /* set write operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + hsfc |= (3 << HSFC_FDBC_OFF); /* set byte count to 3+1 */ + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + /* Wait for Cycle Done Status or Flash Cycle Error. */ + while (((REGREAD16(ICH9_REG_HSFS) & + (HSFS_FDONE | HSFS_FCERR)) == 0) && + --timeout) { + programmer_delay(10); + } + if (!timeout) { + msg_perr("timeout, ICH9_REG_HSFS=0x%04x\n", + REGREAD16(ICH9_REG_HSFS)); + return 1; + } + + hsfs = REGREAD16(ICH9_REG_HSFS); + REGWRITE16(ICH9_REG_HSFS, hsfs); /* clear all error bits */ + if (hsfs & HSFS_FCERR) { + msg_perr("Transaction error between offset 0x%06x and " + "0x%06x + %d (= 0x%06x)!\n", + addr, addr, 4, addr + 4); + prettyprint_ich9_reg_hsfs(hsfs); + prettyprint_ich9_reg_hsfc(hsfs); + return 1; + } + addr += 4; + } + return 0; +} + static int ich_spi_send_multicommand(struct spi_command *cmds) { int ret = 0; @@ -1217,6 +1451,16 @@ static const struct spi_programmer spi_programmer_ich9 = { .write_256 = default_spi_write_256, }; +static const struct spi_programmer spi_programmer_ich_hwseq = { + .type = SPI_CONTROLLER_ICH_HWSEQ, + .max_data_read = 64, + .max_data_write = 64, + .command = ich_hwseq_send_command, + .multicommand = default_spi_send_multicommand, + .read = ich_hwseq_read, + .write_256 = ich_hwseq_write_256, +}; + int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, int ich_generation) { @@ -1225,20 +1469,21 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, uint16_t spibar_offset, tmp2; uint32_t tmp; int ichspi_desc = 0; + /* used for hw sequencing detection */ + extern struct flash_descriptor fdbar; + uint32_t size_low; + uint32_t size_high; switch (ich_generation) { case 7: - register_spi_programmer(&spi_programmer_ich7); spibar_offset = 0x3020; break; case 8: - register_spi_programmer(&spi_programmer_ich9); spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ - register_spi_programmer(&spi_programmer_ich9); spibar_offset = 0x3800; break; } @@ -1249,8 +1494,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, /* Assign Virtual Address */ ich_spibar = rcrb + spibar_offset; - switch (spi_programmer->type) { - case SPI_CONTROLLER_ICH7: + switch (ich_generation) { + case 7: msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", @@ -1286,9 +1531,13 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } + register_spi_programmer(&spi_programmer_ich7); ich_init_opcodes(); break; - case SPI_CONTROLLER_ICH9: + case 8: + case 9: + case 10: + default: /* Future version might behave the same */ tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); prettyprint_ich9_reg_hsfs(tmp2); @@ -1365,10 +1614,21 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, read_ich_descriptors_from_fdo(ich_spibar); pretty_print_ich_descriptors(); } - ich_init_opcodes(); - break; - default: - /* Nothing */ + + /* Fetch erase block sizes for addresses below and above FPBA + * and check if erase blocks are equal for all addresses. */ + REGWRITE32(ICH9_REG_FADDR, (0 & 0x00FFFFFF)); + size_low = ich_hwseq_get_erase_block_size(); + REGWRITE32(ICH9_REG_FADDR, + (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) & 0x00FFFFFF); + size_high = ich_hwseq_get_erase_block_size(); + + if ((ichspi_lock || fdbar.NC != 0) && (size_low == size_high)) + register_spi_programmer(&spi_programmer_ich_hwseq); + else { + register_spi_programmer(&spi_programmer_ich9); + ich_init_opcodes(); + } break; } diff --git a/programmer.h b/programmer.h index e1147f1..8ccaf0b 100644 --- a/programmer.h +++ b/programmer.h @@ -538,6 +538,7 @@ enum spi_controller { #if defined(__i386__) || defined(__x86_64__) SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, + SPI_CONTROLLER_ICH_HWSEQ, SPI_CONTROLLER_IT85XX, SPI_CONTROLLER_IT87XX, SPI_CONTROLLER_SB600, -- 1.7.1

1 0

[PATCH 10/11] add FPB (Flash Partition Boundary) macros and init printing
by Stefan Tauner 27 May '11

27 May '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/ichspi.c b/ichspi.c index c8d8432..5bba0ab 100644 --- a/ichspi.c +++ b/ichspi.c @@ -150,6 +150,10 @@ #define VSCC_VCL (0x1 << VSCC_VCL_OFF) /* 24-31: reserved */ +#define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */ +#define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */ +#define FPB_FPBA (0x1FFF << FPB_FPBA_OFF) + // ICH9R SPI commands #define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0 #define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1 @@ -1353,6 +1357,9 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pdbg("UVSCC: "); prettyprint_ich9_reg_vscc(tmp); + tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); + msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + msg_pdbg("\n"); if (ichspi_desc) { read_ich_descriptors_from_fdo(ich_spibar); -- 1.7.1

1 0

[PATCH 09/11] add macros and pretty printing for "Host Lower Vendor Specific Component Capabilities" registers
by Stefan Tauner 27 May '11

27 May '11

there are two of them: lower and upper. they are only useful for hardware sequencing and indicate properties of the respective flash chip/address space. the VSCC registers describe the properties of the address space lower and equal or above than FPBA. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 41 +++++++++++++++++++++++++++++++++++++++++ 1 files changed, 41 insertions(+), 0 deletions(-) diff --git a/ichspi.c b/ichspi.c index fd983ce..c8d8432 100644 --- a/ichspi.c +++ b/ichspi.c @@ -131,6 +131,25 @@ #define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */ #define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */ +#define ICH9_REG_LVSCC 0xC4 /* 32 Bits Host Lower Vendor Specific Component Capabilities */ +#define ICH9_REG_UVSCC 0xC8 /* 32 Bits Host Upper Vendor Specific Component Capabilities */ +/* Field locations and semantics for LVSCC and UVSCC are equal therefore they + * share the same macros. */ +#define VSCC_EBS_OFF 0 /* 0-1: Block/Sector Erase Size */ +#define VSCC_EBS (0x3 << VSCC_EBS_OFF) +#define VSCC_WG_OFF 2 /* 2: Write Granularity */ +#define VSCC_WG (0x1 << VSCC_WG_OFF) +#define VSCC_WSR_OFF 3 /* 3: Write Status Required */ +#define VSCC_WSR (0x1 << VSCC_WSR_OFF) +#define VSCC_WEWS_OFF 4 /* 4: Write Enable on Write Status */ +#define VSCC_WEWS (0x1 << VSCC_WEWS_OFF) + /* 5-7: reserved */ +#define VSCC_EO_OFF 8 /* 8-15: Erase Opcode */ +#define VSCC_EO (0xff << VSCC_EO_OFF) +#define VSCC_VCL_OFF 23 /* 23: Vendor Component Lock */ +#define VSCC_VCL (0x1 << VSCC_VCL_OFF) + /* 24-31: reserved */ + // ICH9R SPI commands #define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0 #define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1 @@ -305,6 +324,7 @@ static void pretty_print_opcodes(OPCODES *ops) } #define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) +#define pprint_reg_hex(reg, bit, val, sep) msg_pdbg("%s=0x%x" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) static void prettyprint_ich9_reg_hsfs(uint16_t reg_val) { msg_pdbg("HSFS: "); @@ -348,6 +368,16 @@ static void prettyprint_ich9_reg_ssfc(uint32_t reg_val) pprint_reg(SSFC, SCF, reg_val, "\n"); } +static void prettyprint_ich9_reg_vscc(uint32_t reg_val) +{ + pprint_reg_hex(VSCC, EBS, reg_val, ", "); + pprint_reg(VSCC, WG, reg_val, ", "); + pprint_reg(VSCC, WSR, reg_val, ", "); + pprint_reg(VSCC, WEWS, reg_val, ", "); + pprint_reg_hex(VSCC, EO, reg_val, ", "); + pprint_reg(VSCC, VCL, reg_val, "\n"); +} + static uint8_t lookup_spi_type(uint8_t opcode) { int a; @@ -1312,6 +1342,17 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); msg_pdbg("0xA0: 0x%08x (BBAR)\n", ichspi_bbar); + + tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); + msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); + msg_pdbg("LVSCC: "); + prettyprint_ich9_reg_vscc(tmp); + + tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); + msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); + msg_pdbg("UVSCC: "); + prettyprint_ich9_reg_vscc(tmp); + msg_pdbg("\n"); if (ichspi_desc) { read_ich_descriptors_from_fdo(ich_spibar); -- 1.7.1

1 0

[PATCH 08/11] simplify ich_set_bbar
by Stefan Tauner 27 May '11

27 May '11

~10 lines less, documenting better what the differences are (i.e. offset of BBAR only). Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 49 ++++++++++++++++++++----------------------------- 1 files changed, 20 insertions(+), 29 deletions(-) diff --git a/ichspi.c b/ichspi.c index d8df898..fd983ce 100644 --- a/ichspi.c +++ b/ichspi.c @@ -549,45 +549,36 @@ static int program_opcodes(OPCODES *op, int enable_undo) * Try to set BBAR (BIOS Base Address Register), but read back the value in case * it didn't stick. */ -void ich_set_bbar(uint32_t minaddr) +void ich_set_bbar(uint32_t min_addr) { - minaddr &= BBAR_MASK; + void *bbar_addr; switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: - ichspi_bbar = mmio_readl(ich_spibar + 0x50) & ~BBAR_MASK; - if (ichspi_bbar) { - msg_pdbg("Reserved bits in BBAR not zero: 0x%04x", - ichspi_bbar); - } - ichspi_bbar |= minaddr; - rmmio_writel(ichspi_bbar, ich_spibar + 0x50); - ichspi_bbar = mmio_readl(ich_spibar + 0x50); - /* We don't have any option except complaining. And if the write - * failed, the restore will fail as well, so no problem there. - */ - if (ichspi_bbar != minaddr) - msg_perr("Setting BBAR failed!\n"); + bbar_addr = ich_spibar + 0x50; break; case SPI_CONTROLLER_ICH9: - ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR) & ~BBAR_MASK; - if (ichspi_bbar) { - msg_pdbg("Reserved bits in BBAR not zero: 0x%04x", - ichspi_bbar); - } - ichspi_bbar |= minaddr; - rmmio_writel(ichspi_bbar, ich_spibar + ICH9_REG_BBAR); - ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); - /* We don't have any option except complaining. And if the write - * failed, the restore will fail as well, so no problem there. - */ - if (ichspi_bbar != minaddr) - msg_perr("Setting BBAR failed!\n"); + bbar_addr = ich_spibar + ICH9_REG_BBAR; break; default: msg_perr("Unknown chipset for BBAR setting!\n"); - break; + return; + } + if (ichspi_bbar) { + msg_pdbg("Reserved bits in BBAR not zero: 0x%04x", + ichspi_bbar); } + + min_addr &= BBAR_MASK; + ichspi_bbar |= min_addr; + rmmio_writel(ichspi_bbar, bbar_addr); + ichspi_bbar = mmio_readl(bbar_addr); + + /* We don't have any option except complaining. And if the write + * failed, the restore will fail as well, so no problem there. + */ + if (ichspi_bbar != min_addr) + msg_perr("Setting BBAR failed!\n"); } /* This function generates OPCODES from or programs OPCODES to ICH according to -- 1.7.1

1 0

[PATCH 07/11] add ICH/PCH flash descriptor decoding
by Stefan Tauner 27 May '11

27 May '11

based on the work of Matthias 'mazzoo' Wenzel this patch adds... - pretty printing of those ICH/PCH flash descriptors that are cached/mapped by the chipset (and which are therefore reachable via FDOC/FDOD registers) and - a new tool to the util directory that is able to decode all flash descriptors stored in a flash dump file. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- Makefile | 2 +- ich_descriptors.c | 451 ++++++++++++++++++++++ ich_descriptors.h | 408 +++++++++++++++++++ ichspi.c | 10 + util/ich_descriptors_tool/Makefile | 42 ++ util/ich_descriptors_tool/TODO | 5 + util/ich_descriptors_tool/ich_descriptors_tool.c | 226 +++++++++++ 7 files changed, 1143 insertions(+), 1 deletions(-) create mode 100644 ich_descriptors.c create mode 100644 ich_descriptors.h create mode 100644 util/ich_descriptors_tool/Makefile create mode 100644 util/ich_descriptors_tool/TODO create mode 100644 util/ich_descriptors_tool/ich_descriptors_tool.c diff --git a/Makefile b/Makefile index 6e6e2de..b61031f 100644 --- a/Makefile +++ b/Makefile @@ -223,7 +223,7 @@ ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o # FIXME: The PROGRAMMER_OBJS below should only be included on x86. -PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o ich_descriptors.o sb600spi.o wbsio_spi.o mcp6x_spi.o NEED_PCI := yes endif diff --git a/ich_descriptors.c b/ich_descriptors.c new file mode 100644 index 0000000..d20cb6d --- /dev/null +++ b/ich_descriptors.c @@ -0,0 +1,451 @@ +/* This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * authors: + * (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * (c) 2011 Stefan Tauner + */ + +#include "ich_descriptors.h" + +#if defined(__i386__) || defined(__x86_64__) + +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP + +#define DESCRIPTOR_MODE_MAGIC 0x0ff0a55a +#define msg_pdbg printf +#include <stdio.h> + +struct flash_strap fisba; +struct flash_upper_map flumap; + +#else + +#include "flash.h" /* for msg_* */ + +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP + +struct flash_descriptor fdbar = { 0 }; +struct flash_component fcba = { {0} }; +struct flash_region frba = { {0} }; +struct flash_master fmba = { {0} }; + +uint32_t getFCBA() +{ + return (fdbar.FLMAP0 << 4) & 0x00000ff0; +} + +uint32_t getFRBA() +{ + return (fdbar.FLMAP0 >> 12) & 0x00000ff0; +} + +uint32_t getFMBA() +{ + return (fdbar.FLMAP1 << 4) & 0x00000ff0; +} + +uint32_t getFMSBA() +{ + return (fdbar.FLMAP2 << 4) & 0x00000ff0; +} + +uint32_t getFLREG_limit(uint32_t flreg) +{ + return (flreg >> 4) & 0x01fff000; +} + +uint32_t getFLREG_base(uint32_t flreg) +{ + return (flreg << 12) & 0x01fff000; +} + +uint32_t getFISBA() +{ + return (fdbar.FLMAP1 >> 12) & 0x00000ff0; +} + +/** Returns the integer representation of the component density with index +comp in bytes or -1 on failure. */ +int getFCBA_component_density(uint8_t comp) +{ + uint8_t size_enc; + const int dec_mem[6] = { + 512 * 1024, + 1 * 1024 * 1024, + 2 * 1024 * 1024, + 4 * 1024 * 1024, + 8 * 1024 * 1024, + 16 * 1024 * 1024, + }; + + switch(comp) { + case 0: + size_enc = fcba.comp1_density; + break; + case 1: + size_enc = fcba.comp2_density; + break; + default: + msg_perr("Only component index 0 or 1 are supported yet.\n"); + return -1; + } + if (size_enc > 5) { + msg_perr("Density of component with index %d illegal or " + "unsupported. Encoded density is 0x%x.\n", + comp, + size_enc); + return -1; + } + return dec_mem[size_enc]; +} + +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP +uint32_t getVTBA() +{ + return (flumap.FLUMAP1 << 4) & 0x0ff0; +} +#endif + +const struct flash_descriptor_addresses desc_addr = { + .FCBA = getFCBA, + .FRBA = getFRBA, + .FMBA = getFMBA, + .FMSBA = getFMSBA, + .FISBA = getFISBA, + .FLREG_limit = getFLREG_limit, + .FLREG_base = getFLREG_base, +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP + .VTBA = getVTBA, +#endif +}; + +void pretty_print_ich_descriptors() +{ + pretty_print_ich_descriptor_map(); + pretty_print_ich_descriptor_component(); + pretty_print_ich_descriptor_region(); + pretty_print_ich_descriptor_master(); +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP + pretty_print_ich_descriptor_upper_map(); + /* FIXME: detect chipset correctly */ + pretty_print_ich_descriptor_straps(CHIPSET_SERIES_5_IBEX_PEAK); +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP + msg_pdbg("\n"); +} + +void pretty_print_ich_descriptor_map(void) +{ + msg_pdbg("=== FDBAR ===\n"); + msg_pdbg("FLVALSIG 0x%8.8x\n", fdbar.FLVALSIG); + msg_pdbg("FLMAP0 0x%8.8x\n", fdbar.FLMAP0 ); + msg_pdbg("FLMAP1 0x%8.8x\n", fdbar.FLMAP1 ); + msg_pdbg("FLMAP2 0x%8.8x\n", fdbar.FLMAP2 ); + msg_pdbg("\n"); + msg_pdbg("--- FDBAR details ---\n"); + msg_pdbg("0x%2.2x NR Number of Regions\n", fdbar.NR ); + msg_pdbg("0x%8.8x FRBA Flash Region Base Address\n", desc_addr.FRBA() ); + msg_pdbg("0x%2.2x NC Number of Components\n", fdbar.NC ); + msg_pdbg("0x%8.8x FCBA Flash Component Base Address\n", desc_addr.FCBA() ); + msg_pdbg("\n"); + msg_pdbg("0x%2.2x ISL ICH Strap Length\n", fdbar.ISL ); + msg_pdbg("0x%8.8x FISBA Flash ICH Strap Base Address\n", desc_addr.FISBA()); + msg_pdbg("0x%2.2x NM Number of Masters\n", fdbar.NM ); + msg_pdbg("0x%8.8x FMBA Flash Master Base Address\n", desc_addr.FMBA() ); + msg_pdbg("\n"); + msg_pdbg("0x%2.2x MSL MCH Strap Length\n", fdbar.MSL ); + msg_pdbg("0x%8.8x FMSBA Flash MCH Strap Base Address\n", desc_addr.FMSBA()); +} + +void pretty_print_ich_descriptor_component(void) +{ + const char * str_freq[8] = { + "20 MHz", /* 000 */ + "33 MHz", /* 001 */ + "reserved/illegal", /* 010 */ + "reserved/illegal", /* 011 */ + "50 MHz", /* 100 */ + "reserved/illegal", /* 101 */ + "reserved/illegal", /* 110 */ + "reserved/illegal" /* 111 */ + }; + const char * str_mem[8] = { + "512kB", + "1 MB", + "2 MB", + "4 MB", + "8 MB", + "16 MB", + "undocumented/illegal", + "reserved/illegal" + }; + + msg_pdbg("\n"); + msg_pdbg("=== FCBA ===\n"); + msg_pdbg("FLCOMP 0x%8.8x\n", fcba.FLCOMP); + msg_pdbg("FLILL 0x%8.8x\n", fcba.FLILL ); + msg_pdbg("\n"); + msg_pdbg("--- FCBA details ---\n"); + msg_pdbg("0x%2.2x freq_read_id %s\n", + fcba.freq_read_id , str_freq[fcba.freq_read_id ]); + msg_pdbg("0x%2.2x freq_write %s\n", + fcba.freq_write , str_freq[fcba.freq_write ]); + msg_pdbg("0x%2.2x freq_fastread %s\n", + fcba.freq_fastread, str_freq[fcba.freq_fastread]); + msg_pdbg("0x%2.2x fastread %ssupported\n", + fcba.fastread, fcba.fastread ? "" : "not "); + msg_pdbg("0x%2.2x freq_read %s\n", + fcba.freq_read, str_freq[fcba.freq_read ]); + msg_pdbg("0x%2.2x comp 1 density %s\n", + fcba.comp1_density, str_mem[fcba.comp1_density]); + if (fdbar.NC) + msg_pdbg("0x%2.2x comp 2 density %s\n", + fcba.comp2_density, str_mem[fcba.comp2_density]); + else + msg_pdbg("0x%2.2x comp 2 is not used (FLMAP0.NC=0)\n", + fcba.comp2_density); + msg_pdbg("\n"); + msg_pdbg("0x%2.2x invalid instr 0\n", fcba.invalid_instr0); + msg_pdbg("0x%2.2x invalid instr 1\n", fcba.invalid_instr1); + msg_pdbg("0x%2.2x invalid instr 2\n", fcba.invalid_instr2); + msg_pdbg("0x%2.2x invalid instr 3\n", fcba.invalid_instr3); +} + +void pretty_print_ich_descriptor_region(void) +{ + msg_pdbg("\n"); + msg_pdbg("=== FRBA ===\n"); + msg_pdbg("FLREG0 0x%8.8x\n", frba.FLREG0); + msg_pdbg("FLREG1 0x%8.8x\n", frba.FLREG1); + msg_pdbg("FLREG2 0x%8.8x\n", frba.FLREG2); + msg_pdbg("FLREG3 0x%8.8x\n", frba.FLREG3); + msg_pdbg("\n"); + msg_pdbg("--- FRBA details ---\n"); + msg_pdbg("0x%8.8x region 0 limit (descr)\n", desc_addr.FLREG_limit(frba.FLREG0)); + msg_pdbg("0x%8.8x region 0 base (descr)\n", desc_addr.FLREG_base(frba.FLREG0)); + msg_pdbg("0x%8.8x region 1 limit ( BIOS)\n", desc_addr.FLREG_limit(frba.FLREG1)); + msg_pdbg("0x%8.8x region 1 base ( BIOS)\n", desc_addr.FLREG_base(frba.FLREG1)); + msg_pdbg("0x%8.8x region 2 limit ( ME )\n", desc_addr.FLREG_limit(frba.FLREG2)); + msg_pdbg("0x%8.8x region 2 base ( ME )\n", desc_addr.FLREG_base(frba.FLREG2)); + msg_pdbg("0x%8.8x region 3 limit ( GbE )\n", desc_addr.FLREG_limit(frba.FLREG3)); + msg_pdbg("0x%8.8x region 3 base ( GbE )\n", desc_addr.FLREG_base(frba.FLREG3)); +} + +void pretty_print_ich_descriptor_master(void) +{ + msg_pdbg("\n"); + msg_pdbg("=== FMBA ===\n"); + msg_pdbg("FLMSTR1 0x%8.8x\n", fmba.FLMSTR1); + msg_pdbg("FLMSTR2 0x%8.8x\n", fmba.FLMSTR2); + msg_pdbg("FLMSTR3 0x%8.8x\n", fmba.FLMSTR3); + + msg_pdbg("\n"); + msg_pdbg("--- FMBA details ---\n"); + msg_pdbg("BIOS can %s write GbE\n", fmba.BIOS_GbE_write ? " " : "NOT"); + msg_pdbg("BIOS can %s write ME\n", fmba.BIOS_ME_write ? " " : "NOT"); + msg_pdbg("BIOS can %s write BIOS\n", fmba.BIOS_BIOS_write ? " " : "NOT"); + msg_pdbg("BIOS can %s write descr\n", fmba.BIOS_descr_write ? " " : "NOT"); + msg_pdbg("BIOS can %s read GbE\n", fmba.BIOS_GbE_read ? " " : "NOT"); + msg_pdbg("BIOS can %s read ME\n", fmba.BIOS_ME_read ? " " : "NOT"); + msg_pdbg("BIOS can %s read BIOS\n", fmba.BIOS_BIOS_read ? " " : "NOT"); + msg_pdbg("BIOS can %s read descr\n", fmba.BIOS_descr_read ? " " : "NOT"); + msg_pdbg("ME can %s write GbE\n", fmba.ME_GbE_write ? " " : "NOT"); + msg_pdbg("ME can %s write ME\n", fmba.ME_ME_write ? " " : "NOT"); + msg_pdbg("ME can %s write BIOS\n", fmba.ME_BIOS_write ? " " : "NOT"); + msg_pdbg("ME can %s write descr\n", fmba.ME_descr_write ? " " : "NOT"); + msg_pdbg("ME can %s read GbE\n", fmba.ME_GbE_read ? " " : "NOT"); + msg_pdbg("ME can %s read ME\n", fmba.ME_ME_read ? " " : "NOT"); + msg_pdbg("ME can %s read BIOS\n", fmba.ME_BIOS_read ? " " : "NOT"); + msg_pdbg("ME can %s read descr\n", fmba.ME_descr_read ? " " : "NOT"); + msg_pdbg("GbE can %s write GbE\n", fmba.GbE_GbE_write ? " " : "NOT"); + msg_pdbg("GbE can %s write ME\n", fmba.GbE_ME_write ? " " : "NOT"); + msg_pdbg("GbE can %s write BIOS\n", fmba.GbE_BIOS_write ? " " : "NOT"); + msg_pdbg("GbE can %s write descr\n", fmba.GbE_descr_write ? " " : "NOT"); + msg_pdbg("GbE can %s read GbE\n", fmba.GbE_GbE_read ? " " : "NOT"); + msg_pdbg("GbE can %s read ME\n", fmba.GbE_ME_read ? " " : "NOT"); + msg_pdbg("GbE can %s read BIOS\n", fmba.GbE_BIOS_read ? " " : "NOT"); + msg_pdbg("GbE can %s read descr\n", fmba.GbE_descr_read ? " " : "NOT"); +} + +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP +void pretty_print_ich_descriptor_straps_ich8(void) +{ + const char * str_GPIO12[4] = { + "GPIO12", + "LAN PHY Power Control Function (Native Output)", + " GLAN_DOCK# (Native Input)", + "invalid configuration", + }; + + msg_pdbg("\n"); + msg_pdbg("=== FISBA ===\n"); + msg_pdbg("STRP0 0x%8.8x\n", fisba.ich8.STRP0); + + msg_pdbg("\n"); + msg_pdbg("--- FISBA details ---\n"); + msg_pdbg("ME SMBus addr2 0x%2.2x\n", fisba.ich8.ASD2); + msg_pdbg("ME SMBus addr1 0x%2.2x\n", fisba.ich8.ASD); + msg_pdbg("ME SMBus Controller is connected to %s\n", fisba.ich8.MESM2SEL ? "SMLink pins" : "SMBus pins"); + msg_pdbg("SPI CS1 is used for %s\n", fisba.ich8.SPICS1_LANPHYPC_SEL ? "LAN PHY Power Control Function" : "SPI Chip Select"); + msg_pdbg("GPIO12_SEL is used as %s\n", str_GPIO12[fisba.ich8.GPIO12_SEL]); + msg_pdbg("PCIe Port 6 is used for %s\n", fisba.ich8.GLAN_PCIE_SEL ? "integrated GLAN" : "PCI Express"); + msg_pdbg("Intel AMT SMBus Controller 1 is connected to %s\n", fisba.ich8.BMCMODE ? "SMLink" : "SMBus"); + msg_pdbg("TCO slave is on %s. Intel AMT SMBus Controller 1 is %sabled\n", + fisba.ich8.TCOMODE ? "SMBus" : "SMLink", fisba.ich8.TCOMODE ? "en" : "dis"); + msg_pdbg("ME A is %sabled\n", fisba.ich8.ME_DISABLE ? "dis" : "en"); + + msg_pdbg("\n"); + msg_pdbg("=== FMSBA ===\n"); + msg_pdbg("STRP1 0x%8.8x\n", fisba.ich8.STRP1); + + msg_pdbg("\n"); + msg_pdbg("--- FMSBA details ---\n"); + msg_pdbg("ME B is %sabled\n", fisba.ich8.ME_disable_B ? "dis" : "en"); +} + +void pretty_print_ich_descriptor_straps_ibex(void) +{ + int i; + msg_pdbg("\n"); + msg_pdbg("=== FPSBA ===\n"); + for(i = 0; i <= 15; i++) + msg_pdbg("STRP%-2d = 0x%8.8x\n", i, fisba.ibex.STRPs[i]); +} + +void pretty_print_ich_descriptor_straps(enum chipset cs) +{ + switch (cs) { + case CHIPSET_ICH8: + pretty_print_ich_descriptor_straps_ich8(); + break; + case CHIPSET_SERIES_5_IBEX_PEAK: + pretty_print_ich_descriptor_straps_ibex(); + break; + default: + break; + } +} + +void pretty_print_ich_descriptor_upper_map(void) +{ + int i; + msg_pdbg("\n"); + msg_pdbg("=== FLUMAP ===\n"); + msg_pdbg("FLUMAP1 0x%8.8x\n", flumap.FLUMAP1); + + msg_pdbg("\n"); + msg_pdbg("--- FLUMAP details ---\n"); + msg_pdbg("VTL 0x%8.8x\n", flumap.VTL); + msg_pdbg("VTBA 0x%8.8x\n", desc_addr.VTBA()); + msg_pdbg("\n"); + + for (i=0; i < flumap.VTL/2; i++) + { + msg_pdbg(" JID%d = 0x%8.8x\n", i, flumap.vscc_table[i].JID ); + msg_pdbg(" VSCC%d = 0x%8.8x\n", i, flumap.vscc_table[i].VSCC); + } +} + +int read_ich_descriptors_from_dump(uint32_t *dump) +{ + int i; + uint8_t pch_bug_offset = 0; + if (dump[0] != DESCRIPTOR_MODE_MAGIC) { + if (dump[4] == DESCRIPTOR_MODE_MAGIC) + pch_bug_offset = 4; + else + return -1; + } + + /* map */ + fdbar.FLVALSIG = dump[0 + pch_bug_offset]; + fdbar.FLMAP0 = dump[1 + pch_bug_offset]; + fdbar.FLMAP1 = dump[2 + pch_bug_offset]; + fdbar.FLMAP2 = dump[3 + pch_bug_offset]; + + /* component */ + fcba.FLCOMP = dump[(desc_addr.FCBA() >> 2) + 0]; + fcba.FLILL = dump[(desc_addr.FCBA() >> 2) + 1]; + fcba.FLPB = dump[(desc_addr.FCBA() >> 2) + 2]; + + /* region */ + frba.FLREG0 = dump[(desc_addr.FRBA() >> 2) + 0]; + frba.FLREG1 = dump[(desc_addr.FRBA() >> 2) + 1]; + frba.FLREG2 = dump[(desc_addr.FRBA() >> 2) + 2]; + frba.FLREG3 = dump[(desc_addr.FRBA() >> 2) + 3]; + + /* master */ + fmba.FLMSTR1 = dump[(desc_addr.FMBA() >> 2) + 0]; + fmba.FLMSTR2 = dump[(desc_addr.FMBA() >> 2) + 1]; + fmba.FLMSTR3 = dump[(desc_addr.FMBA() >> 2) + 2]; + + /* upper map */ + flumap.FLUMAP1 = dump[(0x0efc >> 2) + 0]; + + for (i=0; i < flumap.VTL; i++) + { + flumap.vscc_table[i].JID = dump[(desc_addr.VTBA() >> 2) + i * 2 + 0]; + flumap.vscc_table[i].VSCC = dump[(desc_addr.VTBA() >> 2) + i * 2 + 1]; + } + /* straps */ + /* FIXME: detect chipset correctly */ + switch (CHIPSET_SERIES_5_IBEX_PEAK) { + case CHIPSET_ICH8: + fisba.ich8.STRP0 = dump[(desc_addr.FISBA() >> 2) + 0]; + fisba.ich8.STRP1 = dump[(desc_addr.FMSBA() >> 2) + 0]; + break; + case CHIPSET_SERIES_5_IBEX_PEAK: + for(i = 0; i <= 15; i++) + fisba.ibex.STRPs[i] = dump[(desc_addr.FISBA() >> 2) + i]; + break; + default: + break; + } + + return 0; +} +#else // ICH_DESCRIPTORS_FROM_MMAP_DUMP + +static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) +{ + uint32_t control = 0; + control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS; + control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI; + *(volatile uint32_t *) (spibar + ICH9_REG_FDOC) = control; + return *(volatile uint32_t *)(spibar + ICH9_REG_FDOD); +} + +void read_ich_descriptors_from_fdo(void *spibar) +{ + msg_pdbg("Reading flash descriptors " + "mapped by the chipset via FDOC/FDOD..."); + /* descriptor map section */ + fdbar.FLVALSIG = read_descriptor_reg(0, 0, spibar); + fdbar.FLMAP0 = read_descriptor_reg(0, 1, spibar); + fdbar.FLMAP1 = read_descriptor_reg(0, 2, spibar); + fdbar.FLMAP2 = read_descriptor_reg(0, 3, spibar); + + /* component section */ + fcba.FLCOMP = read_descriptor_reg(1, 0, spibar); + fcba.FLILL = read_descriptor_reg(1, 1, spibar); + fcba.FLPB = read_descriptor_reg(1, 2, spibar); + + /* region section */ + frba.FLREG0 = read_descriptor_reg(2, 0, spibar); + frba.FLREG1 = read_descriptor_reg(2, 1, spibar); + frba.FLREG2 = read_descriptor_reg(2, 2, spibar); + frba.FLREG3 = read_descriptor_reg(2, 3, spibar); + + /* master section */ + fmba.FLMSTR1 = read_descriptor_reg(3, 0, spibar); + fmba.FLMSTR2 = read_descriptor_reg(3, 1, spibar); + fmba.FLMSTR3 = read_descriptor_reg(3, 2, spibar); + + /* strap section and upper map */ + /* impossible via FDOC/FDOD(?) */ + msg_pdbg(" done\n"); +} + +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP +#endif // defined(__i386__) || defined(__x86_64__) diff --git a/ich_descriptors.h b/ich_descriptors.h new file mode 100644 index 0000000..af9d0ba --- /dev/null +++ b/ich_descriptors.h @@ -0,0 +1,408 @@ +/* This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * authors: + * (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * (c) 2011 Stefan Tauner + */ + +#include <stdint.h> + +#if defined(__i386__) || defined(__x86_64__) +#ifndef __ICH_DESCRIPTORS_H__ +#define __ICH_DESCRIPTORS_H__ 1 + +/* should probably be in ichspi.h */ +#define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */ +#define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Select */ +#define FDOC_FDSI (0x3f << FDOC_FDSI_OFF) +#define FDOC_FDSS_OFF 12 /* 12-14: Flash Descriptor Section Select */ +#define FDOC_FDSS (0x3 << FDOC_FDSS_OFF) +#define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */ + +enum chipset { + CHIPSET_ICH8, + CHIPSET_ICH9, + CHIPSET_ICH10, + CHIPSET_SERIES_5_IBEX_PEAK, + CHIPSET_SERIES_6_COUGAR_POINT, + CHIPSET_SERIES_7_PANTHER_POINT +}; + +struct flash_descriptor_addresses { + uint32_t (*FCBA)(void); + uint32_t (*FRBA)(void); + uint32_t (*FMBA)(void); + uint32_t (*FMSBA)(void); + uint32_t (*FLREG_limit)(uint32_t flreg); + uint32_t (*FLREG_base)(uint32_t flreg); + uint32_t (*FISBA)(void); +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP + uint32_t (*VTBA)(void); +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP +}; + +struct flash_descriptor { + uint32_t FLVALSIG; /* 0x00 */ + union { /* 0x04 */ + uint32_t FLMAP0; + struct { + uint8_t FCBA :8; + uint8_t NC :2; + unsigned :6; + uint8_t FRBA :8; + uint8_t NR :3; + unsigned :5; + }; + }; + union { /* 0x08 */ + uint32_t FLMAP1; + struct { + uint8_t FMBA :8; + uint8_t NM :3; + unsigned :5; + union { + uint8_t FISBA :8; + uint8_t FPSBA :8; + }; + uint8_t ISL :8; + }; + }; + union { /* 0x0c */ + uint32_t FLMAP2; + struct { + uint8_t FMSBA :8; + uint8_t MSL :8; + unsigned :16; + }; + }; +}; + +struct flash_component { + union { /* 0x00 */ + uint32_t FLCOMP; + struct { + uint8_t comp1_density :3; + uint8_t comp2_density :3; + unsigned :11; + uint8_t freq_read :3; + uint8_t fastread :1; + uint8_t freq_fastread :3; + uint8_t freq_write :3; + uint8_t freq_read_id :3; + unsigned :2; + }; + }; + union { /* 0x04 */ + uint32_t FLILL; + struct { + uint8_t invalid_instr0; + uint8_t invalid_instr1; + uint8_t invalid_instr2; + uint8_t invalid_instr3; + }; + }; + union { /* 0x08 */ + uint32_t FLPB; + struct { + uint16_t FPBA :13; + unsigned :19; + }; + }; +}; + +struct flash_region { + + union { + uint32_t FLREG0; /* Flash Descriptor */ + struct { + uint16_t reg0_base :13; + unsigned :3; + uint16_t reg0_limit :13; + unsigned :3; + }; + }; + union { + uint32_t FLREG1; /* BIOS */ + struct { + uint16_t reg1_base :13; + unsigned :3; + uint16_t reg1_limit :13; + unsigned :3; + }; + }; + union { + uint32_t FLREG2; /* ME */ + struct { + uint16_t reg2_base :13; + unsigned :3; + uint16_t reg2_limit :13; + unsigned :3; + }; + }; + union { + uint32_t FLREG3; /* GbE */ + struct { + uint16_t reg3_base :13; + unsigned :3; + uint16_t reg3_limit :13; + unsigned :3; + }; + }; +} frba; + +struct flash_master { + union { + uint32_t FLMSTR1; + struct { + uint16_t BIOS_req_ID :16; + uint8_t BIOS_descr_read :1; + uint8_t BIOS_BIOS_read :1; + uint8_t BIOS_ME_read :1; + uint8_t BIOS_GbE_read :1; + uint8_t BIOS_plat_read :1; + unsigned :3; + uint8_t BIOS_descr_write :1; + uint8_t BIOS_BIOS_write :1; + uint8_t BIOS_ME_write :1; + uint8_t BIOS_GbE_write :1; + uint8_t BIOS_plat_write :1; + unsigned :3; + }; + }; + union { + uint32_t FLMSTR2; + struct { + uint16_t ME_req_ID :16; + uint8_t ME_descr_read :1; + uint8_t ME_BIOS_read :1; + uint8_t ME_ME_read :1; + uint8_t ME_GbE_read :1; + uint8_t ME_plat_read :1; + unsigned :3; + uint8_t ME_descr_write :1; + uint8_t ME_BIOS_write :1; + uint8_t ME_ME_write :1; + uint8_t ME_GbE_write :1; + uint8_t ME_plat_write :1; + unsigned :3; + }; + }; + union { + uint32_t FLMSTR3; + struct { + uint16_t GbE_req_ID :16; + uint8_t GbE_descr_read :1; + uint8_t GbE_BIOS_read :1; + uint8_t GbE_ME_read :1; + uint8_t GbE_GbE_read :1; + uint8_t GbE_plat_read :1; + unsigned :3; + uint8_t GbE_descr_write :1; + uint8_t GbE_BIOS_write :1; + uint8_t GbE_ME_write :1; + uint8_t GbE_GbE_write :1; + uint8_t GbE_plat_write :1; + unsigned :3; + }; + }; +}; + +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP +struct flash_strap { + union { + struct { + union { + uint32_t STRP0; + struct { + uint8_t ME_DISABLE :1; + unsigned :6; + uint8_t TCOMODE :1; + uint8_t ASD :7; + uint8_t BMCMODE :1; + unsigned :3; + uint8_t GLAN_PCIE_SEL :1; + uint8_t GPIO12_SEL :2; + uint8_t SPICS1_LANPHYPC_SEL :1; + uint8_t MESM2SEL :1; + unsigned :1; + uint8_t ASD2 :7; + }; + }; + union { + uint32_t STRP1; + struct { + uint8_t ME_disable_B :1; + unsigned :31; + }; + }; + }ich8; + union { + uint32_t STRPs[15]; + struct { + union { + uint32_t STRP0; + struct { + unsigned :1; + uint8_t cs_ss2 :1; + unsigned :5; + uint8_t SMB_EN :1; + uint8_t SML0_EN :1; + uint8_t SML1_EN :1; + uint8_t SML1FRQ :2; + uint8_t SMB0FRQ :2; + uint8_t SML0FRQ :2; + unsigned :4; + uint8_t LANPHYPC_GP12_SEL :1; + uint8_t cs_ss1 :1; + unsigned :2; + uint8_t DMI_REQID_DIS :1; + unsigned :4; + uint8_t BBBS :2; + unsigned :1; + }; + }; + union { + uint32_t STRP1; + struct { + }; + }; + union { + uint32_t STRP2; + struct { + }; + }; + union { + uint32_t STRP3; + struct { + }; + }; + union { + uint32_t STRP4; + struct { + }; + }; + union { + uint32_t STRP5; + struct { + }; + }; + union { + uint32_t STRP6; + struct { + }; + }; + union { + uint32_t STRP7; + struct { + }; + }; + union { + uint32_t STRP8; + struct { + }; + }; + union { + uint32_t STRP9; + struct { + }; + }; + union { + uint32_t STRP10; + struct { + }; + }; + union { + uint32_t STRP11; + struct { + }; + }; + union { + uint32_t STRP12; + struct { + }; + }; + union { + uint32_t STRP13; + struct { + }; + }; + union { + uint32_t STRP14; + struct { + }; + }; + union { + uint32_t STRP15; + struct { + }; + }; + }; + }ibex; + }; +}; + +struct flash_upper_map { + union { + uint32_t FLUMAP1; + struct { + uint8_t VTBA :8; + uint8_t VTL :8; + unsigned :16; + }; + }; + struct { + union { + uint32_t JID; + struct { + uint8_t vid :8; + uint8_t cid0 :8; + uint8_t cid1 :8; + unsigned :8; + }; + }; + union { + uint32_t VSCC; + struct { + uint8_t ubes :2; + uint8_t uwg :1; + uint8_t uwsr :1; + uint8_t uwews :1; + unsigned :3; + uint8_t ueo :8; + uint8_t lbes :2; + uint8_t lwg :1; + uint8_t lwsr :1; + uint8_t lwews :1; + unsigned :3; + uint16_t leo :16; + }; + }; + }vscc_table[128]; +}; +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP + +void pretty_print_ich_descriptors(void); + +void pretty_print_ich_descriptor_map(void); +void pretty_print_ich_descriptor_component(void); +void pretty_print_ich_descriptor_region(void); +void pretty_print_ich_descriptor_master(void); + +int getFCBA_component_density(uint8_t comp); + +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP + +void pretty_print_ich_descriptor_upper_map(void); +void pretty_print_ich_descriptor_straps(enum chipset cs); +int read_ich_descriptors_from_dump(uint32_t *dump); + +#else // ICH_DESCRIPTORS_FROM_MMAP_DUMP + +void read_ich_descriptors_from_fdo(void *spibar); + +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP + +#endif // __ICH_DESCRIPTORS_H__ +#endif // defined(__i386__) || defined(__x86_64__) diff --git a/ichspi.c b/ichspi.c index 584cab4..d8df898 100644 --- a/ichspi.c +++ b/ichspi.c @@ -6,6 +6,7 @@ * Copyright (C) 2008 Dominik Geyer <dominik.geyer(a)kontron.com> * Copyright (C) 2008 coresystems GmbH <info(a)coresystems.de> * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger + * Copyright (C) 2011 Stefan Tauner * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -41,6 +42,7 @@ #include "chipdrivers.h" #include "programmer.h" #include "spi.h" +#include "ich_descriptors.h" /* ICH9 controller register definition */ #define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ @@ -1197,6 +1199,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, uint8_t old, new; uint16_t spibar_offset, tmp2; uint32_t tmp; + int ichspi_desc = 0; switch (ich_generation) { case 7: @@ -1268,6 +1271,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } + if (tmp2 & HSFS_FDV) + ichspi_desc = 1; tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); @@ -1316,6 +1321,11 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); msg_pdbg("0xA0: 0x%08x (BBAR)\n", ichspi_bbar); + msg_pdbg("\n"); + if (ichspi_desc) { + read_ich_descriptors_from_fdo(ich_spibar); + pretty_print_ich_descriptors(); + } ich_init_opcodes(); break; default: diff --git a/util/ich_descriptors_tool/Makefile b/util/ich_descriptors_tool/Makefile new file mode 100644 index 0000000..9b1d096 --- /dev/null +++ b/util/ich_descriptors_tool/Makefile @@ -0,0 +1,42 @@ +CC ?= gcc + +PROGRAM=ich_descriptors_tool +EXTRAINCDIRS = ../../ . +DEPPATH = .dep +OBJATH = .obj +SHAREDSRC = ich_descriptors.c +SHAREDSRCDIR = ../.. + +SRC = $(wildcard *.c) + +CFLAGS=-Wall +CFLAGS += -MMD -MP -MF $(DEPPATH)/$((a)F).d +# enables functions that populate the descriptor structs from plain dump arrays +CFLAGS += -D ICH_DESCRIPTORS_FROM_MMAP_DUMP +CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) + +OBJ = $(OBJATH)/$(SRC:%.c=%.o) + +SHAREDOBJ = $(OBJATH)/$(notdir $(SHAREDSRC:%.c=%.o)) + +all:$(PROGRAM) + +$(OBJ): $(OBJATH)/%.o : %.c + $(CC) $(CFLAGS) -o $@ -c $< + +# this enables us to NOT share object files with flashrom, +# which would lead to unexpected results otherwise (w/o running make clean) +$(SHAREDOBJ): $(OBJATH)/%.o : $(SHAREDSRCDIR)/%.c + $(CC) $(CFLAGS) -o $@ -c $< + +$(PROGRAM): $(OBJ) $(SHAREDOBJ) + $(CC) -o $(PROGRAM) $(OBJ) $(SHAREDOBJ) + +clean: + rm -f $(PROGRAM) + rm -rf $(DEPPATH) $(OBJATH) + +# Include the dependency files. +-include $(shell mkdir -p $(DEPPATH) $(OBJATH) 2>/dev/null) $(wildcard $(DEPPATH)/*) + +.PHONY: all clean \ No newline at end of file diff --git a/util/ich_descriptors_tool/TODO b/util/ich_descriptors_tool/TODO new file mode 100644 index 0000000..e3933ee --- /dev/null +++ b/util/ich_descriptors_tool/TODO @@ -0,0 +1,5 @@ +- reverse the path, as in assemble a descriptormode image from various + blobs (BIOS, GbE, ME, OEM) and a description (xml? custom config? + sane defaults and cmd-line switches?) +- dump 256 OEM bytes +- handle descriptors of various chipsets correctly \ No newline at end of file diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c new file mode 100644 index 0000000..8ce7677 --- /dev/null +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -0,0 +1,226 @@ +/* + * dump information and binaries from BIOS images that are in descriptor mode/soft-strap + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * authors: + * (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * (c) 2011 Stefan Tauner + * + * */ +#include <stdio.h> +#include <stdint.h> +#include <stdlib.h> +#include <sys/mman.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <fcntl.h> +#include <unistd.h> +#include <string.h> +#include <errno.h> +#include "flash.h" +#include "ich_descriptors.h" + +extern struct flash_descriptor fdbar; +extern struct flash_component fcba; +extern struct flash_region frba; +extern struct flash_master fmba; +extern struct flash_strap fisba; +extern struct flash_upper_map flumap; +extern struct flash_descriptor_addresses desc_addr; + +static int f; /* file descriptor to flash file */ +static int fs; /* file size */ +static uint32_t *fm; /* mmap'd file */ + +void dump_file_descriptor(char * fn) +{ + char * n = malloc(strlen(fn) + 11); + snprintf(n, strlen(fn) + 11, "%s.descr.bin", fn); + printf("\n"); + printf("+++ dumping %s ... ", n); + int fh = open(n, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); + free(n); + if (fh < 0) + { + printf("ERROR: couldn't open(%s): %s\n", n, strerror(errno)); + exit(1); + } + + int ret; + ret = write(fh, &fm[frba.reg0_base >> 2], frba.reg0_limit); + if (ret != frba.reg0_limit) + { + printf("FAILED.\n"); + exit(1); + } + + printf("done.\n"); + + close(fh); +} + +void dump_file_BIOS(char * fn) +{ + char * n = malloc(strlen(fn) + 10); + snprintf(n, strlen(fn) + 10, "%s.BIOS.bin", fn); + printf("\n"); + printf("+++ dumping %s ... ", n); + int fh = open(n, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); + free(n); + if (fh < 0) + { + printf("ERROR: couldn't open(%s): %s\n", n, strerror(errno)); + exit(1); + } + + int ret; + ret = write(fh, &fm[frba.reg1_base >> 2], frba.reg1_limit); + if (ret != frba.reg1_limit) + { + printf("FAILED.\n"); + exit(1); + } + + printf("done.\n"); + + close(fh); +} + +void dump_file_ME(char * fn) +{ + char * n = malloc(strlen(fn) + 8); + snprintf(n, strlen(fn) + 8, "%s.ME.bin", fn); + printf("\n"); + printf("+++ dumping %s ... ", n); + int fh = open(n, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); + free(n); + if (fh < 0) + { + printf("ERROR: couldn't open(%s): %s\n", n, strerror(errno)); + exit(1); + } + + int ret; + ret = write(fh, &fm[frba.reg2_base >> 2], frba.reg2_limit); + if (ret != frba.reg2_limit) + { + printf("FAILED.\n"); + exit(1); + } + + printf("done.\n"); + + close(fh); +} + +void dump_file_GbE(char * fn) +{ + char * n = malloc(strlen(fn) + 9); + snprintf(n, strlen(fn) + 9, "%s.GbE.bin", fn); + printf("\n"); + printf("+++ dumping %s ... ", n); + int fh = open(n, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); + free(n); + if (fh < 0) + { + printf("ERROR: couldn't open(%s): %s\n", n, strerror(errno)); + exit(1); + } + + int ret; + ret = write(fh, &fm[frba.reg3_base >> 2], frba.reg3_limit); + if (ret != frba.reg3_limit) + { + printf("FAILED.\n"); + exit(1); + } + + printf("done.\n"); + uint8_t * pMAC = (uint8_t *) &fm[frba.reg3_base >> 2]; + printf("the MAC-address might be: %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", + pMAC[0], + pMAC[1], + pMAC[2], + pMAC[3], + pMAC[4], + pMAC[5] + ); + + close(fh); +} + +void dump_files(char * n) +{ + printf("=== dumping section files ===\n"); + if (frba.reg0_limit) + dump_file_descriptor(n); + if (frba.reg1_limit) + dump_file_BIOS(n); + if (frba.reg2_limit) + dump_file_ME(n); + if (frba.reg3_limit) + dump_file_GbE(n); +} + +void usage(char ** argv, char* error) +{ + printf("%s\n", error); + printf("\n"); + printf("usage: '%s <bios image file> [-d]'\n", argv[0]); + printf("\n"); + printf("\twhere <bios image file> isn't actually a BIOS image, but the SPI flash\n"); + printf("\tcontents of the SPI connected to your intel chipset.\n"); + printf("\tIn case that image is really in descriptor mode (a.k.a soft-strap)\n"); + printf("\t%s will pretty print all relevant information.\n", argv[0]); + printf("\tIf '-d' is specified as the second parameter some sections such as\n"); + printf("\tthe real BIOS image as seen by the CPU or a GbE blob that is\n"); + printf("\trequired to initialize your ICH GbE are also dumped to files.\n"); + exit(1); +} + +int main(int argc, char **argv) +{ + if (argc < 2) + usage(argv, "Need at least one parameter"); + f = open(argv[1], O_RDONLY); + if (f < 0) + usage(argv, "No such file"); + if (argc >= 3 && (strcmp("-d", argv[2]) == 0)) + usage(argv, "Bogus second argument"); + + fs = lseek(f, 0, SEEK_END); + if (fs < 0) + usage(argv, "Seeking to the end of the file failed"); + + fm = mmap(NULL, fs, PROT_READ, MAP_PRIVATE, f, 0); + if (fm == (void *) -1) + { + /* fallback for stupid OSes like cygwin */ + int ret; + fm = malloc(fs); + if (!fm) + usage(argv, "Could not allocate memory"); + lseek(f, 0, SEEK_SET); + ret = read(f, fm, fs); + if (ret != fs) + usage(argv, "Seeking to the end of the file failed"); + } + printf("flash image is %d [0x%x] bytes\n", fs, fs); + close(f); + + if(read_ich_descriptors_from_dump(fm)){ + printf("not in descriptor mode\n"); + exit(1); + } + + pretty_print_ich_descriptors(); + + if (argc >= 3) + dump_files(argv[1]); + + return 0; +} + -- 1.7.1

1 0

[PATCH 06/11] add missing ICH9 register macros and use them to eliminate magic numbers
by Stefan Tauner 27 May '11

27 May '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 63 ++++++++++++++++++++++++++++++++++++------------------------- 1 files changed, 37 insertions(+), 26 deletions(-) diff --git a/ichspi.c b/ichspi.c index dff6f32..584cab4 100644 --- a/ichspi.c +++ b/ichspi.c @@ -77,6 +77,15 @@ #define ICH9_REG_FADDR 0x08 /* 32 Bits */ #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ +#define ICH9_REG_FRAP 0x50 /* 32 Bytes Flash Region Access Permissions */ +#define ICH9_REG_FREG0 0x54 /* 32 Bytes Flash Region 0 */ + +#define ICH9_REG_PR0 0x74 /* 32 Bytes Protected Range 0 */ +#define ICH9_REG_PR1 0x78 /* 32 Bytes Protected Range 1 */ +#define ICH9_REG_PR2 0x7c /* 32 Bytes Protected Range 2 */ +#define ICH9_REG_PR3 0x80 /* 32 Bytes Protected Range 3 */ +#define ICH9_REG_PR4 0x84 /* 32 Bytes Protected Range 4 */ + #define ICH9_REG_SSFS 0x90 /* 08 Bits */ #define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */ #define SSFS_SCIP (0x1 << SSFS_SCIP_OFF) @@ -117,6 +126,9 @@ #define ICH9_REG_OPTYPE 0x96 /* 16 Bits */ #define ICH9_REG_OPMENU 0x98 /* 64 Bits */ +#define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */ +#define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */ + // ICH9R SPI commands #define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0 #define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1 @@ -537,15 +549,15 @@ static int program_opcodes(OPCODES *op, int enable_undo) */ void ich_set_bbar(uint32_t minaddr) { -#define BBAR_MASK 0x00ffff00 minaddr &= BBAR_MASK; switch (spi_programmer->type) { case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_VIA: ichspi_bbar = mmio_readl(ich_spibar + 0x50) & ~BBAR_MASK; - if (ichspi_bbar) + if (ichspi_bbar) { msg_pdbg("Reserved bits in BBAR not zero: 0x%04x", ichspi_bbar); + } ichspi_bbar |= minaddr; rmmio_writel(ichspi_bbar, ich_spibar + 0x50); ichspi_bbar = mmio_readl(ich_spibar + 0x50); @@ -556,13 +568,14 @@ void ich_set_bbar(uint32_t minaddr) msg_perr("Setting BBAR failed!\n"); break; case SPI_CONTROLLER_ICH9: - ichspi_bbar = mmio_readl(ich_spibar + 0xA0) & ~BBAR_MASK; - if (ichspi_bbar) + ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR) & ~BBAR_MASK; + if (ichspi_bbar) { msg_pdbg("Reserved bits in BBAR not zero: 0x%04x", ichspi_bbar); + } ichspi_bbar |= minaddr; - rmmio_writel(ichspi_bbar, ich_spibar + 0xA0); - ichspi_bbar = mmio_readl(ich_spibar + 0xA0); + rmmio_writel(ichspi_bbar, ich_spibar + ICH9_REG_BBAR); + ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); /* We don't have any option except complaining. And if the write * failed, the restore will fail as well, so no problem there. */ @@ -1138,7 +1151,7 @@ static void do_ich9_spi_frap(uint32_t frap, int i) uint32_t base, limit; int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) | (((ICH_BRRA(frap) >> i) & 1) << 0); - int offset = 0x54 + i * 4; + int offset = ICH9_REG_FREG0 + i * 4; uint32_t freg = mmio_readl(ich_spibar + offset); msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n", @@ -1248,19 +1261,19 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, ich_init_opcodes(); break; case SPI_CONTROLLER_ICH9: - tmp2 = mmio_readw(ich_spibar + 4); + tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); prettyprint_ich9_reg_hsfs(tmp2); - if (tmp2 & (1 << 15)) { + if (tmp2 & HSFS_FLOCKDN) { msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } - tmp2 = mmio_readw(ich_spibar + 6); + tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); prettyprint_ich9_reg_hsfc(tmp2); - tmp = mmio_readl(ich_spibar + 0x50); + tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP); msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); @@ -1272,39 +1285,37 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, do_ich9_spi_frap(tmp, i); msg_pdbg("0x74: 0x%08x (PR0)\n", - mmio_readl(ich_spibar + 0x74)); + mmio_readl(ich_spibar + ICH9_REG_PR0)); msg_pdbg("0x78: 0x%08x (PR1)\n", - mmio_readl(ich_spibar + 0x78)); + mmio_readl(ich_spibar + ICH9_REG_PR1)); msg_pdbg("0x7C: 0x%08x (PR2)\n", - mmio_readl(ich_spibar + 0x7C)); + mmio_readl(ich_spibar + ICH9_REG_PR2)); msg_pdbg("0x80: 0x%08x (PR3)\n", - mmio_readl(ich_spibar + 0x80)); + mmio_readl(ich_spibar + ICH9_REG_PR3)); msg_pdbg("0x84: 0x%08x (PR4)\n", - mmio_readl(ich_spibar + 0x84)); + mmio_readl(ich_spibar + ICH9_REG_PR4)); - tmp = mmio_readl(ich_spibar + 0x90); + tmp = mmio_readl(ich_spibar + ICH9_REG_SSFS); msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff); prettyprint_ich9_reg_ssfs(tmp); - if (tmp & (1 << 3)) { + if (tmp & SSFS_FCERR) { msg_pdbg("Clearing SSFS.FCERR\n"); - mmio_writeb(1 << 3, ich_spibar + 0x90); + mmio_writeb(SSFS_FCERR, ich_spibar + ICH9_REG_SSFS); } msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp >> 8); prettyprint_ich9_reg_ssfc(tmp); msg_pdbg("0x94: 0x%04x (PREOP)\n", - mmio_readw(ich_spibar + 0x94)); + mmio_readw(ich_spibar + ICH9_REG_PREOP)); msg_pdbg("0x96: 0x%04x (OPTYPE)\n", - mmio_readw(ich_spibar + 0x96)); + mmio_readw(ich_spibar + ICH9_REG_OPTYPE)); msg_pdbg("0x98: 0x%08x (OPMENU)\n", - mmio_readl(ich_spibar + 0x98)); + mmio_readl(ich_spibar + ICH9_REG_OPMENU)); msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", - mmio_readl(ich_spibar + 0x9C)); - ichspi_bbar = mmio_readl(ich_spibar + 0xA0); + mmio_readl(ich_spibar + ICH9_REG_OPMENU + 4)); + ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); msg_pdbg("0xA0: 0x%08x (BBAR)\n", ichspi_bbar); - msg_pdbg("0xB0: 0x%08x (FDOC)\n", - mmio_readl(ich_spibar + 0xB0)); ich_init_opcodes(); break; default: -- 1.7.1

1 0

[PATCH 05/11] warn if SMM BIOS Write Protection is detected in BIOS_CNTL
by Stefan Tauner 27 May '11

27 May '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipset_enable.c | 11 ++++++++++- 1 files changed, 10 insertions(+), 1 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index 83b49ad..1f6f74c 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -264,8 +264,17 @@ static int enable_flash_ich(struct pci_dev *dev, const char *name, (old & (1 << 0)) ? "en" : "dis"); msg_pdbg("BIOS_CNTL is 0x%x\n", old); - new = old | 1; + /* + * Quote from the 6 Series datasheet: + * "5: SMM BIOS Write Protect Disable (SMM_BWP) + * 1 = BIOS region SMM protection is enabled. + * The BIOS Region is not writable unless all processors are in SMM." + * In earlier chipsets this bit is reserved. */ + if (old & (1 << 5)) { + msg_pinfo("WARNING: BIOS region SMM protection is enabled!\n"); + } + new = old | 1; if (new == old) return 0; -- 1.7.1

1 0

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