- flashrom - mail.coreboot.org

Re: [flashrom] [PATCH] dummyflasher.c: add an "content" parameter to select initialization data
by Stefan Tauner 21 Jul '11

21 Jul '11

On Fri, 22 Jul 2011 00:08:41 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > previously the dummies were initialized to be empty (all ones), which makes > writes skip erasing altogether. with this patch the default is to fill it with random > bytes instead. > additionally one can decide other options with the "content" parameter: > content=ones - old behavior > content=random - new default > content=zeros - filled with 0x00 > content=increment - filled with i++ sorry, fixed commit log looks like: dummyflasher.c: add a "content" parameter to select initialization data previously the dummies were initialized to be empty (all ones), which makes write operations skip erasing altogether. with this patch the default is to fill it with random bytes instead. additionally one can decide other options with the "content" parameter: content=ones - old behavior content=random - new default content=zeros - filled with 0x00 content=increment - filled with i++ i am tired. gn8 -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH] dummyflasher.c: add an "empty" parameter and initialize with random bytes by default
by Uwe Hermann 21 Jul '11

21 Jul '11

On Thu, Jul 21, 2011 at 05:54:46PM +0200, Stefan Tauner wrote: > previously the dummies were initialized to be empty (all ones), which makes writes skip > erasing altogether. with this patch the default is to fill it with random bytes instead and the > old behavior can be enforced with stating "empty=yes" on the command line. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> I'd make the programmer options a bit more generic to allow for other content easily and consistently: -p dummy:content=ff -p dummy:content=00 -p dummy:content=random -p dummy:content=incrementing etc. The default should be documented in the manpage. > + empty = extract_programmer_param("empty"); > + if (empty != NULL) { > + if (strstr(empty, "yes")) Why not strcasecmp() here? Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[commit] r1380 - trunk
by repository service 21 Jul '11

21 Jul '11

Author: hailfinger Date: Thu Jul 21 23:21:04 2011 New Revision: 1380 URL: http://flashrom.org/trac/flashrom/changeset/1380 Log: Fix out-of-bounds access if all erase functions fail. Fix detection of unchanged chip contents on erase failure. Return error if no usable erase functions exist. Thanks to Stefan Tauner for spotting the last problem. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/flashrom.c Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Thu Jul 21 21:59:34 2011 (r1379) +++ trunk/flashrom.c Thu Jul 21 23:21:04 2011 (r1380) @@ -1507,7 +1507,7 @@ int erase_and_write_flash(struct flashchip *flash, uint8_t *oldcontents, uint8_t *newcontents) { - int k, ret = 0; + int k, ret = 1; uint8_t *curcontents; unsigned long size = flash->total_size * 1024; unsigned int usable_erasefunctions = count_usable_erasers(flash); @@ -1522,8 +1522,12 @@ memcpy(curcontents, oldcontents, size); for (k = 0; k < NUM_ERASEFUNCTIONS; k++) { + if (!usable_erasefunctions) { + msg_cdbg("No usable erase functions left.\n"); + break; + } msg_cdbg("Looking at blockwise erase function %i... ", k); - if (check_block_eraser(flash, k, 1) && usable_erasefunctions) { + if (check_block_eraser(flash, k, 1)) { msg_cdbg("Looking for another erase function.\n"); continue; } @@ -1535,10 +1539,8 @@ if (!ret) break; /* Write/erase failed, so try to find out what the current chip - * contents are. If no usable erase functions remain, we could - * abort the loop instead of continuing, the effect is the same. - * The only difference is whether the reason for other unusable - * functions is printed or not. If in doubt, verbosity wins. + * contents are. If no usable erase functions remain, we can + * skip this: the next iteration will break immediately anyway. */ if (!usable_erasefunctions) continue;

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Re: [flashrom] [PATCH] chipset_enable.c: add a message in the case the chipset enable is untested
by Paul Menzel 21 Jul '11

21 Jul '11

Am Donnerstag, den 21.07.2011, 14:23 +0200 schrieb Stefan Tauner: > old output: > Calibrating delay loop... OK. > Found chipset "Intel QS57", enabling flash write... OK. > This chipset supports the following protocols: FWH, SPI. > > new non-verbose output for tested chipsets: > Calibrating delay loop... OK. > Found chipset "Intel QS57". Enabling flash write... OK. > This chipset supports the following protocols: FWH, SPI. > > new non-verbose output for untested chipsets: > Found chipset "Intel QS57". > This chipset is marked as untested. If you are using an up-to-date version > of flashrom please email a report to flashrom(a)flashrom.org including a > verbose (-V) log. Thank you! A similar message should be shown somewhere else. I would put more information in it. This chipset is marked as untested. If you are using an up-to-date version of flashrom <http://flashrom.org/Downloads> please email a report to flashrom(a)flashrom.org with the subject (variable with the name (here Intel QS57) including a verbose (-V) log. Thank you! Do we have preferences if the log should be pasted or attached? > Enabling flash write... OK. > This chipset supports the following protocols: FWH, SPI. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > chipset_enable.c | 19 ++++++++++++++----- > 1 files changed, 14 insertions(+), 5 deletions(-) […] Thanks, Paul

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Re: [flashrom] [PATCH] chipset_enable.c: add a message in the case the chipset enable is untested
by Uwe Hermann 21 Jul '11

21 Jul '11

On Thu, Jul 21, 2011 at 02:23:05PM +0200, Stefan Tauner wrote: > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> > + msg_pinfo("Found chipset \"%s %s\"", > + chipset_enables[i].vendor_name, > + chipset_enables[i].device_name); > + msg_pdbg("with PCI ID %04x:%04x", > chipset_enables[i].vendor_id, > chipset_enables[i].device_id); I'd print the IDs unconditionally, not only with -V, but that's for another patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[commit] r1379 - trunk
by repository service 21 Jul '11

21 Jul '11

Author: stefanct Date: Thu Jul 21 21:59:34 2011 New Revision: 1379 URL: http://flashrom.org/trac/flashrom/changeset/1379 Log: chipset_enable.c: add a message for untested chipset enables old output: Calibrating delay loop... OK. Found chipset "Intel QS57", enabling flash write... OK. This chipset supports the following protocols: FWH, SPI. new non-verbose output for tested chipsets: Calibrating delay loop... OK. Found chipset "Intel QS57". Enabling flash write... OK. This chipset supports the following protocols: FWH, SPI. new non-verbose output for untested chipsets: Found chipset "Intel QS57". This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... OK. This chipset supports the following protocols: FWH, SPI. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/chipset_enable.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Thu Jul 21 21:52:00 2011 (r1378) +++ trunk/chipset_enable.c Thu Jul 21 21:59:34 2011 (r1379) @@ -1226,13 +1226,22 @@ chipset_enables[i].device_name); continue; } - msg_pinfo("Found chipset \"%s %s\", enabling flash write... ", - chipset_enables[i].vendor_name, - chipset_enables[i].device_name); - msg_pdbg("chipset PCI ID is %04x:%04x, ", + msg_pinfo("Found chipset \"%s %s\"", + chipset_enables[i].vendor_name, + chipset_enables[i].device_name); + msg_pdbg("with PCI ID %04x:%04x", chipset_enables[i].vendor_id, chipset_enables[i].device_id); + msg_pinfo(". "); + if (chipset_enables[i].status == NT) { + msg_pinfo("\nThis chipset is marked as untested. If " + "you are using an up-to-date version\nof " + "flashrom please email a report to " + "flashrom(a)flashrom.org including a\nverbose " + "(-V) log. Thank you!\n"); + } + msg_pinfo("Enabling flash write... "); ret = chipset_enables[i].doit(dev, chipset_enables[i].device_name); if (ret == NOT_DONE_YET) {

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Re: [flashrom] [PATCH] flashrom.8: explain read accesses as part of the write operation
by Uwe Hermann 21 Jul '11

21 Jul '11

On Thu, Jul 21, 2011 at 01:06:29PM +0200, Stefan Tauner wrote: > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Lookѕ good, also did a quick check against the code. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[commit] r1378 - trunk
by repository service 21 Jul '11

21 Jul '11

Author: stefanct Date: Thu Jul 21 21:52:00 2011 New Revision: 1378 URL: http://flashrom.org/trac/flashrom/changeset/1378 Log: flashrom.8: explain read accesses as part of the write operation Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/flashrom.8 Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Thu Jul 21 11:18:18 2011 (r1377) +++ trunk/flashrom.8 Thu Jul 21 21:52:00 2011 (r1378) @@ -45,6 +45,13 @@ into flash ROM. This will first automatically .B erase the chip, then write to it. +.sp +In the process the chip is also read several times. First an in-memory backup +is made for disaster recovery and to be able to skip regions that are +already equal to the image file. This copy is updated along with the write +operation. In case of erase errors it is even re-read completely. After +writing has finished and if verification is enabled, the whole flash chip is +read out and compared with the input image. .TP .B "\-n, \-\-noverify" Skip the automatic verification of flash ROM contents after writing. Using this @@ -541,7 +548,7 @@ backup. This is caused by the embedded controller (EC) present in many laptops, which interacts badly with any flash attempts. This is a hardware limitation and flashrom will attempt to detect it and abort immediately for safety reasons. -.SH LICENCE +.SH LICENSE .B flashrom is covered by the GNU General Public License (GPL), version 2. Some files are additionally available under the GPL (version 2, or any later version). @@ -623,6 +630,6 @@ .br All authors can be reached via email at <flashrom(a)flashrom.org>. .PP -This manual page was written by Uwe Hermann <uwe(a)hermann-uwe.de> -and Carl-Daniel Hailfinger. +This manual page was written by Uwe Hermann <uwe(a)hermann-uwe.de>, +Carl-Daniel Hailfinger and others. It is licensed under the terms of the GNU GPL (version 2 or later).

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[commit] r1369 - trunk
by repository service 21 Jul '11

21 Jul '11

Author: stefanct Date: Wed Jul 13 00:01:44 2011 New Revision: 1369 URL: http://flashrom.org/trac/flashrom/changeset/1369 Log: update motherboard URLs in print.c Signed-off-by: Benjamin Bellec <b.bellec(a)gmail.com> with small changes: Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/print.c Modified: trunk/print.c ============================================================================== --- trunk/print.c Sat Jul 9 21:46:53 2011 (r1368) +++ trunk/print.c Wed Jul 13 00:01:44 2011 (r1369) @@ -376,15 +376,15 @@ const struct board_info boards_known[] = { #if defined(__i386__) || defined(__x86_64__) B("A-Trend", "ATC-6220", 1, "http://www.motherboard.cz/mb/atrend/atc6220.htm", NULL), - B("abit", "AN-M2", 1, "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?DEFTITLE=…", NULL), + B("abit", "AN-M2", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=…", NULL), B("abit", "AX8", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=…", NULL), B("abit", "BM6", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NA…", NULL), - B("abit", "Fatal1ty F-I90HD", 1, "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?pMODEL_NA…", NULL), + B("abit", "Fatal1ty F-I90HD", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NA…", NULL), B("abit", "IC7", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NA…", NULL), B("abit", "IP35", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=LG…", NULL), - B("abit", "IP35 Pro", 1, "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?fMTYPE=LG…", NULL), + B("abit", "IP35 Pro", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=LG…", NULL), B("abit", "IS-10", 0, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?pMODEL_NA…", "Reported by deejkuba(a)aol.com to flashrom(a)coreboot.org, no public archive. Missing board enable and/or M50FW040 unlocking. May work now."), - B("abit", "KN8 Ultra", 1, "http://www.abit.com.tw/page/de/motherboard/motherboard_detail.php?DEFTITLE=…", NULL), + B("abit", "KN8 Ultra", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?DEFTITLE=…", NULL), B("abit", "NF-M2 nView", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=So…", NULL), B("abit", "NF7-S", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=So…", NULL), B("abit", "VA6", 1, "http://www.abit.com.tw/page/en/motherboard/motherboard_detail.php?fMTYPE=Sl…", NULL), @@ -399,16 +399,16 @@ B("ASI", "MB-5BLMP", 1, "http://www.hojerteknik.com/winnet.htm", "Used in the IGEL WinNET III thin client."), B("ASRock", "775i65G", 1, "http://www.asrock.com/mb/overview.asp?Model=775i65G", NULL), B("ASRock", "890GX Extreme3", 1, "http://www.asrock.com/mb/overview.asp?Model=890GX%20Extreme3", NULL), - B("ASRock", "939A785GMH/128M", 1, "http://www.asrock.com/mb/overview.asp?Model=939A785GMH/128M&s=939", NULL), + B("ASRock", "939A785GMH/128M", 1, "http://www.asrock.com/mb/overview.asp?Model=939A785GMH/128M", NULL), B("ASRock", "A330GC", 1, "http://www.asrock.com/mb/overview.asp?Model=A330GC", NULL), - B("ASRock", "A770CrossFire", 1, "http://www.asrock.com/mb/overview.asp?Model=A770CrossFire&s=AM2%%2b", NULL), + B("ASRock", "A770CrossFire", 1, "http://www.asrock.com/mb/overview.asp?Model=A770CrossFire", NULL), B("ASRock", "ALiveNF6G-DVI", 1, "http://www.asrock.com/mb/overview.asp?Model=ALiveNF6G-DVI", NULL), B("ASRock", "K7S41", 1, "http://www.asrock.com/mb/overview.asp?Model=K7S41", NULL), B("ASRock", "K7S41GX", 1, "http://www.asrock.com/mb/overview.asp?Model=K7S41GX", NULL), - B("ASRock", "K7VT4A+", 0, "http://www.asrock.com/mb/overview.asp?Model=K7VT4A%%2b&s=", "No chip found, probably due to flash translation. http://www.flashrom.org/pipermail/flashrom/2009-August/000393.html"), + B("ASRock", "K7VT4A+", 0, "http://www.asrock.com/mb/overview.asp?Model=K7VT4A%2b", "No chip found, probably due to flash translation. http://www.flashrom.org/pipermail/flashrom/2009-August/000393.html"), B("ASRock", "K8S8X", 1, "http://www.asrock.com/mb/overview.asp?Model=K8S8X", NULL), - B("ASRock", "M3A790GXH/128M", 1, "http://www.asrock.com/MB/overview.asp?Model=M3A790GXH/128M", NULL), - B("ASRock", "P4i65GV", 1, NULL, NULL), + B("ASRock", "M3A790GXH/128M", 1, "http://www.asrock.com/mb/overview.asp?Model=M3A790GXH/128M", NULL), + B("ASRock", "P4i65GV", 1, "http://www.asrock.com/mb/overview.asp?Model=P4i65GV", NULL), B("ASUS", "A7N8X Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=wAsRYm41KTp78MFC", NULL), B("ASUS", "A7N8X-E Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=TmQtPJv4jIxmL9C2", NULL), B("ASUS", "A7V133", 1, "ftp://ftp.asus.com.tw/pub/ASUS/mb/socka/kt133a/a7v133/", NULL), @@ -525,9 +525,9 @@ B("GIGABYTE", "GA-6IEM", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1379", NULL), B("GIGABYTE", "GA-6VXE7+", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2410", NULL), B("GIGABYTE", "GA-6ZMA", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1541", NULL), - B("GIGABYTE", "GA-MA785GMT-UD2H", 1, "http://www.gigabyte.de/Products/Motherboard/Products_Overview.aspx?ProductI…", NULL), - B("GIGABYTE", "GA-770TA-UD3", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3272#ov", NULL), - B("GIGABYTE", "GA-7DXR", 1, "http://www.gigabyte.de/Products/Motherboard/Products_Spec.aspx?ProductID=13…", NULL), + B("GIGABYTE", "GA-MA785GMT-UD2H (rev. 1.0)", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3156", NULL), + B("GIGABYTE", "GA-770TA-UD3", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=3272", NULL), + B("GIGABYTE", "GA-7DXR", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1302", NULL), B("GIGABYTE", "GA-7VT600", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1666", NULL), B("GIGABYTE", "GA-7ZM", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1366", "Works fine if you remove jumper JP9 on the board and disable the flash protection BIOS option."), B("GIGABYTE", "GA-8IP775", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1830", NULL), @@ -579,43 +579,43 @@ B("Lanner", "EM-8510C", 1, NULL, NULL), B("Lex", "CV700A", 1, "http://www.lex.com.tw/product/CV700A-spec.htm", NULL), B("Mitac", "6513WU", 1, "http://web.archive.org/web/20050313054828/http://www.mitac.com/micweb/produ…", NULL), - B("MSI", "MS-6153", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=336", NULL), + B("MSI", "MS-6153", 1, "http://www.msi.com/product/mb/MS-6153.html", NULL), B("MSI", "MS-6156", 1, "http://uk.ts.fujitsu.com/rl/servicesupport/techsupport/boards/Motherboards/…", NULL), - B("MSI", "MS-6163 (MS-6163 Pro)",1, "http://www.msi.com/index.php?func=proddesc&prod_no=340", NULL), - B("MSI", "MS-6178", 0, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=343", "Immediately powers off if you try to hot-plug the chip. However, this does '''not''' happen if you use coreboot. Owned by Uwe Hermann <uwe(a)hermann-uwe.de>."), - B("MSI", "MS-6330 (K7T Turbo)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=327", NULL), - B("MSI", "MS-6391 (845 Pro4)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=293", NULL), - B("MSI", "MS-6561 (745 Ultra)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=274", NULL), + B("MSI", "MS-6163 (MS-6163 Pro)",1, "http://www.msi.com/product/mb/MS-6163-Pro.html", NULL), + B("MSI", "MS-6178", 0, "http://www.msi.com/product/mb/MS-6178.html", "Immediately powers off if you try to hot-plug the chip. However, this does '''not''' happen if you use coreboot. Owned by Uwe Hermann <uwe(a)hermann-uwe.de>."), + B("MSI", "MS-6330 (K7T Turbo)", 1, "http://www.msi.com/product/mb/K7T-Turbo.html", NULL), + B("MSI", "MS-6391 (845 Pro4)", 1, "http://www.msi.com/product/mb/845-Pro4.html", NULL), + B("MSI", "MS-6561 (745 Ultra)", 1, "http://www.msi.com/product/mb/745-Ultra.html", NULL), B("MSI", "MS-6566 (845 Ultra-C)",1, "http://www.msi.com/product/mb/845-Ultra-C.html", NULL), - B("MSI", "MS-6570 (K7N2)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=519", NULL), + B("MSI", "MS-6570 (K7N2)", 1, "http://www.msi.com/product/mb/K7N2.html", NULL), B("MSI", "MS-6577 (Xenon)", 1, "http://h10025.www1.hp.com/ewfrf/wc/document?product=90390&lc=en&cc=us&dlc=e…", "This is an OEM board from HP, the HP name is Xenon."), - B("MSI", "MS-6590 (KT4 Ultra)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=502", NULL), - B("MSI", "MS-6702E (K8T Neo2-F)",1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=588", NULL), - B("MSI", "MS-6712 (KT4V)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=505", NULL), - B("MSI", "MS-6787 (P4MAM-V/P4MAM-L)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=577", NULL), - B("MSI", "MS-7005 (651M-L)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=559", NULL), - B("MSI", "MS-7025 (K8N Neo2 Platinum)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=587", NULL), + B("MSI", "MS-6590 (KT4 Ultra)", 1, "http://www.msi.com/product/mb/KT4-Ultra.html", NULL), + B("MSI", "MS-6702E (K8T Neo2-F)",1, "http://www.msi.com/product/mb/K8T-Neo2-F--FIR.html", NULL), + B("MSI", "MS-6712 (KT4V)", 1, "http://www.msi.com/product/mb/KT4V---KT4V-L--v1-0-.html", NULL), + B("MSI", "MS-6787 (P4MAM-V/P4MAM-L)", 1, "http://www.msi.com/service/search/?kw=6787&type=product", NULL), + B("MSI", "MS-7005 (651M-L)", 1, "http://www.msi.com/product/mb/651M-L.html", NULL), + B("MSI", "MS-7025 (K8N Neo2 Platinum)", 1, "http://www.msi.com/product/mb/K8N-Neo2-Platinum.html", NULL), B("MSI", "MS-7046", 1, "http://www.heimir.de/ms7046/", NULL), - B("MSI", "MS-7061 (KM4M-V/KM4AM-V)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=594", NULL), + B("MSI", "MS-7061 (KM3M-V/KM4M-V/KM4AM-V)", 1, "http://www.msi.com/service/search/?kw=7061&type=product", NULL), B("MSI", "MS-7065", 1, "http://browse.geekbench.ca/geekbench2/view/53114", NULL), - B("MSI", "MS-7135 (K8N Neo3)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=170", NULL), + B("MSI", "MS-7135 (K8N Neo3)", 1, "http://www.msi.com/product/mb/K8N-Neo3.html", NULL), B("MSI", "MS-7168 (Orion)", 1, "http://support.packardbell.co.uk/uk/item/index.php?i=spec_orion&pi=platform…", NULL), - B("MSI", "MS-7207 (K8NGM2-L)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=224", NULL), - B("MSI", "MS-7211 (PM8M3-V)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=234", NULL), - B("MSI", "MS-7236 (945PL Neo3)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1173", NULL), - B("MSI", "MS-7253 (K9VGM-V)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=260", NULL), - B("MSI", "MS-7255 (P4M890M)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1082", NULL), - B("MSI", "MS-7260 (K9N Neo)", 0, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=255", "Interestingly flashrom does not work when the vendor BIOS is booted, but it ''does'' work flawlessly when the machine is booted with coreboot. Owned by Uwe Hermann <uwe(a)hermann-uwe.de>."), - B("MSI", "MS-7312 (K9MM-V)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1104", NULL), - B("MSI", "MS-7345 (P35 Neo2-FIR)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1261", NULL), - B("MSI", "MS-7368 (K9AG Neo2-Digital)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1241", NULL), - B("MSI", "MS-7376 (K9A2 Platinum)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1332", NULL), + B("MSI", "MS-7207 (K8NGM2-L)", 1, "http://www.msi.com/product/mb/K8NGM2-FID--IL--L.html", NULL), + B("MSI", "MS-7211 (PM8M3-V)", 1, "http://www.msi.com/product/mb/PM8M3-V.html", NULL), + B("MSI", "MS-7236 (945PL Neo3)", 1, "http://www.msi.com/product/mb/945PL-Neo3.html", NULL), + B("MSI", "MS-7253 (K9VGM-V)", 1, "http://www.msi.com/product/mb/K9VGM-V.html", NULL), + B("MSI", "MS-7255 (P4M890M)", 1, "http://www.msi.com/product/mb/P4M890M-L-IL.html", NULL), + B("MSI", "MS-7260 (K9N Neo PCB 1.0)", 0, "http://www.msi.com/product/mb/K9N-Neo--PCB-1-0-.html", "Interestingly flashrom does not work when the vendor BIOS is booted, but it ''does'' work flawlessly when the machine is booted with coreboot. Owned by Uwe Hermann <uwe(a)hermann-uwe.de>."), + B("MSI", "MS-7312 (K9MM-V)", 1, "http://www.msi.com/product/mb/K9MM-V.html", NULL), + B("MSI", "MS-7345 (P35 Neo2-FIR)", 1, "http://www.msi.com/product/mb/P35-Neo2-FR---FIR.html", NULL), + B("MSI", "MS-7368 (K9AG Neo2-Digital)", 1, "http://www.msi.com/product/mb/K9AG-Neo2-Digital.html", NULL), + B("MSI", "MS-7376 (K9A2 Platinum V1)", 1, "http://www.msi.com/product/mb/K9A2-Platinum.html", NULL), B("MSI", "MS-7529 (G31M3-L(S) V2)", 1, "http://www.msi.com/product/mb/G31M3-L-V2---G31M3-LS-V2.html", NULL), - B("MSI", "MS-7529 (G31TM-P21)", 1, "http://msi.com/product/mb/G31TM-P21.html", NULL), - B("MSI", "MS-7596 (785GM-E51)", 1, "http://eu.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=1866", NULL), + B("MSI", "MS-7529 (G31TM-P21)", 1, "http://www.msi.com/product/mb/G31TM-P21.html", NULL), + B("MSI", "MS-7596 (785GM-E51)", 1, "http://www.msi.com/product/mb/785GM-E51.html", NULL), B("MSI", "MS-7599 (870-C45)", 1, "http://www.msi.com/product/mb/870-C45.html", NULL), - B("MSI", "MS-7640 (890FXA-GD70)",1, "http://www.msi.com/product/mb/890FXA-GD70.html", "Reported by \"Linux User #330250\" http://flashrom.org/pipermail/flashrom/2011-March/006072.html"), - B("MSI", "MS-7642 (890GXM-G65)", 1, "http://www.msi.com/index.php?func=proddesc&maincat_no=1&prod_no=2012", NULL), + B("MSI", "MS-7640 (890FXA-GD70)",1, "http://www.msi.com/product/mb/890FXA-GD70.html", NULL), + B("MSI", "MS-7642 (890GXM-G65)", 1, "http://www.msi.com/product/mb/890GXM-G65.html", NULL), B("MSI", "MS-7698 (E350IA-E45)", 1, "http://www.msi.com/product/mb/E350IA-E45.html", NULL), B("NEC", "PowerMate 2000", 1, "http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/", NULL), B("Nokia", "IP530", 1, NULL, NULL),

3 2

[commit] r1375 - trunk
by repository service 21 Jul '11

21 Jul '11

Author: stefanct Date: Tue Jul 19 10:50:18 2011 New Revision: 1375 URL: http://flashrom.org/trac/flashrom/changeset/1375 Log: annotate additional flashchips with voltage ranges also fix a few others and remove the one for Intel 28F002BC/BL/BV/BX-T because we need to investigate it further. Signed-off-by: Steven Zakulec <spzakulec(a)gmail.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/flashchips.c Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Tue Jul 19 09:58:06 2011 (r1374) +++ trunk/flashchips.c Tue Jul 19 10:50:18 2011 (r1375) @@ -113,7 +113,7 @@ }, .write = write_jedec_1, .read = read_memmapped, - .voltage = {4750, 5250}, /* -55 speed is +-5%, all others +-10% */ + .voltage = {4750, 5250}, /* 4.75-5.25V for type -55, others 4.5-5.5V */ }, { @@ -145,6 +145,7 @@ }, .write = write_jedec_1, .read = read_memmapped, + .voltage = {4750, 5250}, /* 4.75-5.25V for type -55, others 4.5-5.5V */ }, { @@ -256,6 +257,7 @@ }, .write = write_jedec_1, .read = read_memmapped, + .voltage = {3000, 3600}, /* 3.0-3.6V for type -45R, others 2.7-3.6V */ }, { @@ -286,6 +288,7 @@ }, .write = write_jedec_1, .read = read_memmapped, + .voltage = {3000, 3600}, /* 3.0-3.6V for type -45R, others 2.7-3.6V */ }, { @@ -317,6 +320,7 @@ }, .write = write_jedec_1, .read = read_memmapped, + .voltage = {3000, 3600}, /* 3.0-3.6V for type -55, others 2.7-3.6V */ }, { @@ -348,6 +352,7 @@ }, .write = write_jedec_1, .read = read_memmapped, + .voltage = {3000, 3600}, /* 3.0-3.6V for type -55, others 2.7-3.6V */ }, { @@ -379,6 +384,7 @@ }, .write = write_jedec_1, .read = read_memmapped, + .voltage = {2700, 3600}, }, { @@ -410,6 +416,7 @@ }, .write = write_jedec_1, .read = read_memmapped, + .voltage = {2700, 3600}, }, { @@ -441,6 +448,7 @@ }, .write = write_jedec_1, .read = read_memmapped, + .voltage = {3000, 3600} /* 3.0-3.6V for type -70R, others 2.7-3.6V */ }, { @@ -472,6 +480,7 @@ }, .write = write_jedec_1, .read = read_memmapped, + .voltage = {3000, 3600} /* 3.0-3.6V for type -70R, others 2.7-3.6V */ }, { @@ -498,7 +507,7 @@ }, .write = write_jedec_1, .read = read_memmapped, - .voltage = {2700, 3600}, + .voltage = {3000, 3600}, /* 3.0-3.6V for type -60R, others 2.7-3.6V*/ }, { @@ -525,7 +534,7 @@ }, .write = write_jedec_1, .read = read_memmapped, - .voltage = {2700, 3600}, + .voltage = {3000, 3600}, /* 3.0-3.6V for type -70R, others 2.7-3.6V */ }, { @@ -591,6 +600,7 @@ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, + .voltage = {2700, 3600}, }, { @@ -1332,7 +1342,7 @@ .unlock = spi_disable_blockprotect_at25df, .write = spi_chip_write_256, .read = spi_chip_read, - .voltage = {2300, 3600}, /* Datasheet says 2.3-3.6V or 2.7-3.6V */ + .voltage = {2700, 3600}, /* 2.3-3.6V & 2.7-3.6V models available */ }, { @@ -1370,7 +1380,7 @@ .unlock = spi_disable_blockprotect_at25df, .write = spi_chip_write_256, .read = spi_chip_read, - .voltage = {2300, 3600}, /* Datasheet says 2.3-3.6V or 2.7-3.6V */ + .voltage = {2700, 3600}, /* 2.3-3.6V & 2.7-3.6V models available */ }, { @@ -1446,6 +1456,7 @@ .unlock = spi_disable_blockprotect_at25df_sec, .write = spi_chip_write_256, .read = spi_chip_read, + .voltage = {2700, 3600}, }, { @@ -1773,7 +1784,7 @@ }, .write = NULL /* Incompatible Page write */, .read = spi_chip_read, - .voltage = {2700, 3600}, /* Datasheet says 3.0-3.6 V or 2.7-3.6 V */ + .voltage = {2700, 3600}, /* 3.0-3.6V for higher speed, 2.7-3.6V normal */ }, { @@ -2098,7 +2109,7 @@ .probe_timing = TIMING_ZERO, .write = NULL, .read = NULL, - .voltage = {2500, 3600}, /* Datasheet says 2.5-3.6 V or 2.7-3.6 V */ + .voltage = {2500, 3600}, /* 2.5-3.6V & 2.7-3.6V models available */ }, { @@ -2114,7 +2125,7 @@ .probe_timing = TIMING_ZERO, .write = NULL, .read = NULL, - .voltage = {2500, 3600}, /* Datasheet says 2.5-3.6 V or 2.7-3.6 V */ + .voltage = {2700, 3600}, /* 2.5-3.6V & 2.7-3.6V models available */ }, { @@ -2130,7 +2141,7 @@ .probe_timing = TIMING_ZERO, .write = NULL, .read = NULL, - .voltage = {2500, 3600}, /* Datasheet says 2.5-3.6 V or 2.7-3.6 V */ + .voltage = {2700, 3600}, /* 2.5-3.6V & 2.7-3.6V models available */ }, { @@ -2317,6 +2328,7 @@ }, .write = write_jedec_1, .read = read_memmapped, + .voltage = {4500, 5500}, }, { @@ -3378,7 +3390,7 @@ }, .write = write_m29f400bt, .read = read_memmapped, - .voltage = {4750, 5250}, /* 5.0V +-5% for -55 model, +-10% for rest */ + .voltage = {4750, 5250}, /* 4.75-5.25V for type -55, others 4.5-5.5V */ }, { @@ -3410,7 +3422,7 @@ }, .write = write_m29f400bt, .read = read_memmapped, - .voltage = {4750, 5250}, /* 5.0V +-5% for -55 model, +-10% for rest */ + .voltage = {4750, 5250}, /* 4.75-5.25V for type -55, others 4.5-5.5V */ }, { @@ -3442,7 +3454,7 @@ }, .write = write_jedec_1, .read = read_memmapped, - .voltage = {4750, 5250}, /* 5.0V +-5% for -45 model, +-10% for rest */ + .voltage = {4750, 5250}, /* 4.75-5.25V for type -45, others 4.5-5.5V */ }, { @@ -3474,7 +3486,7 @@ }, .write = write_jedec_1, .read = read_memmapped, - .voltage = {4750, 5250}, /* 5.0V +-5% for -45 model, +-10% for rest */ + .voltage = {4750, 5250}, /* 4.75-5.25V for type -45, others 4.5-5.5V */ }, { @@ -3501,6 +3513,7 @@ }, .write = write_jedec_1, .read = read_memmapped, + .voltage = {4500, 5500}, }, { @@ -3582,7 +3595,6 @@ }, .write = write_82802ab, .read = read_memmapped, - .voltage = {4500, 5500}, /* 5.0V +-10% read, 12V fast program & erase- +-5% standard, +-10% option */ }, { @@ -4052,6 +4064,7 @@ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, + .voltage = {2700, 3600}, }, { @@ -4344,6 +4357,7 @@ }, .write = write_jedec_1, .read = read_memmapped, + .voltage = {4500, 5500}, }, { @@ -4775,6 +4789,7 @@ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, + .voltage = {2700, 3600}, }, { @@ -4900,6 +4915,7 @@ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, + .voltage = {2700, 3600}, }, { @@ -5201,6 +5217,7 @@ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, + .voltage = {2700, 3600}, }, { @@ -5281,6 +5298,7 @@ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, + .voltage = {2700, 3600}, }, { @@ -5307,6 +5325,7 @@ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, + .voltage = {2700, 3600}, }, { @@ -5336,6 +5355,7 @@ .unlock = spi_disable_blockprotect, .write = spi_chip_write_1, .read = spi_chip_read, + .voltage = {2700, 3600}, }, { @@ -5473,6 +5493,7 @@ .unlock = spi_disable_blockprotect, .write = spi_chip_write_1, .read = spi_chip_read, + .voltage = {2700, 3600}, }, { @@ -5538,6 +5559,7 @@ .unlock = spi_disable_blockprotect, .write = spi_chip_write_1, .read = spi_chip_read, + .voltage = {3000, 3600}, }, { @@ -5573,6 +5595,7 @@ .unlock = spi_disable_blockprotect, .write = spi_chip_write_1, .read = spi_chip_read, + .voltage = {2700, 3600}, }, { @@ -6780,6 +6803,7 @@ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, + .voltage = {2700, 3600}, }, { @@ -6840,7 +6864,7 @@ }, .write = write_jedec_1, .read = read_memmapped, - .voltage = {4750, 5250}, /* Datasheet says some are only 4.75-5.25 V */ + .voltage = {4750, 5250}, /* 4.75-5.25V for type -X, others 4.5-5.5V */ }, { @@ -6872,7 +6896,7 @@ }, .write = write_jedec_1, .read = read_memmapped, - .voltage = {4750, 5250}, /* Datasheet says some are only 4.75-5.25 V */ + .voltage = {4750, 5250}, /* 4.75-5.25V for type -X, others 4.5-5.5V */ }, { @@ -8131,6 +8155,7 @@ .printlock = printlock_w39l040, .write = write_jedec_1, .read = read_memmapped, + .voltage = {3000, 3600}, }, { @@ -8275,6 +8300,7 @@ .unlock = unlock_w39v040fb, .write = write_jedec_1, .read = read_memmapped, + .voltage = {3000, 3600}, /* Also has 12V fast program */ }, { @@ -8302,6 +8328,7 @@ .printlock = printlock_w39v040fc, .write = write_jedec_1, .read = read_memmapped, + .voltage = {3000, 3600}, /* Also has 12V fast program */ }, { @@ -8478,7 +8505,7 @@ .unlock = unlock_w39v080fa, .write = write_jedec_1, .read = read_memmapped, - .voltage = {3000, 3600}, /* 12 V fast program mode */ + .voltage = {3000, 3600}, /* Also has 12V fast program */ }, { @@ -8506,6 +8533,7 @@ .printlock = printlock_w39v080fa_dual, .write = write_jedec_1, .read = read_memmapped, + .voltage = {3000, 3600}, /* Also has 12V fast program */ }, {

2 1

[PATCH] ft2232_spi: Improve error handling, remove exit() calls
by Uwe Hermann 21 Jul '11

21 Jul '11

See patch. This is just a first step, there is certainly room for further improving the error handling (error #defines such as FL_ERR_MALLOC, consistent and documented return codes, and more). Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

2 2

[PATCH] dummyflasher.c: add an "empty" parameter and initialize with random bytes by default
by Stefan Tauner 21 Jul '11

21 Jul '11

previously the dummies were initialized to be empty (all ones), which makes writes skip erasing altogether. with this patch the default is to fill it with random bytes instead and the old behavior can be enforced with stating "empty=yes" on the command line. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- dummyflasher.c | 22 ++++++++++++++++++++-- 1 files changed, 20 insertions(+), 2 deletions(-) diff --git a/dummyflasher.c b/dummyflasher.c index fca228c..b463ea4 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -94,6 +94,8 @@ int dummy_init(void) { char *bustext = NULL; char *tmp = NULL; + char *empty; + int e = 0; #if EMULATE_CHIP struct stat image_stat; #endif @@ -128,6 +130,13 @@ int dummy_init(void) msg_pdbg("Support for all flash bus types disabled.\n"); free(bustext); + empty = extract_programmer_param("empty"); + if (empty != NULL) { + if (strstr(empty, "yes")) + e = 1; + free(empty); + } + tmp = extract_programmer_param("spi_write_256_chunksize"); if (tmp) { spi_write_256_chunksize = atoi(tmp); @@ -198,8 +207,17 @@ int dummy_init(void) return 1; } - msg_pdbg("Filling fake flash chip with 0xff, size %i\n", emu_chip_size); - memset(flashchip_contents, 0xff, emu_chip_size); + msg_pdbg("Filling fake flash chip containing %i bytes with ", + emu_chip_size); + if (e) { + msg_pdbg("0xff.\n"); + memset(flashchip_contents, 0xff, emu_chip_size); + } else { + msg_pdbg("random data.\n"); + unsigned int i; + for (i = 0; i < emu_chip_size; i++) + flashchip_contents[i] = rand(); + } emu_persistent_image = extract_programmer_param("image"); if (!emu_persistent_image) { -- 1.7.1

1 0

Re: [flashrom] [PATCH] flashrom.8: explain read accesses as part of the write operation
by Paul Menzel 21 Jul '11

21 Jul '11

Dear Stefan, Am Donnerstag, den 21.07.2011, 13:06 +0200 schrieb Stefan Tauner: > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > flashrom.8 | 13 +++++++++---- > 1 files changed, 9 insertions(+), 4 deletions(-) > > diff --git a/flashrom.8 b/flashrom.8 > index 5b11f6e..3b7ad40 100644 > --- a/flashrom.8 > +++ b/flashrom.8 > @@ -44,7 +44,12 @@ Write > .B <file> > into flash ROM. This will first automatically > .B erase > -the chip, then write to it. > +the chip, then write to it. The chip is also read several times: first an I would make a full stop after »times« and begin a new sentence. > +in-memory backup is made for disaster recovery and to be able to skip regions > +that are already equal to the image file. This copy is updated after each erase > +block (in case of errors it is even re-read completely). After writing has … block. (In case of ….) > +finished and if verification is enabled, the whole flash is read out and the whole flash ROM/chip I do not know if there are guidelines for referring to the chip. > +compared with the input image. > .TP > .B "\-n, \-\-noverify" > Skip the automatic verification of flash ROM contents after writing. Using this > @@ -541,7 +546,7 @@ unusable unless you can desolder the flash chip and have a full flash chip > backup. This is caused by the embedded controller (EC) present in many laptops, > which interacts badly with any flash attempts. This is a hardware limitation > and flashrom will attempt to detect it and abort immediately for safety reasons. > -.SH LICENCE > +.SH LICENSE Please commit that separately next time right ahead as trivial. > .B flashrom > is covered by the GNU General Public License (GPL), version 2. Some files are > additionally available under the GPL (version 2, or any later version). > @@ -623,6 +628,6 @@ some others, please see the flashrom svn changelog for details. > .br > All authors can be reached via email at <flashrom(a)flashrom.org>. > .PP > -This manual page was written by Uwe Hermann <uwe(a)hermann-uwe.de> > -and Carl-Daniel Hailfinger. > +This manual page was written by Uwe Hermann <uwe(a)hermann-uwe.de>, > +Carl-Daniel Hailfinger and others. > It is licensed under the terms of the GNU GPL (version 2 or later). Acked-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Thanks, Paul

2 2

[PATCH] chipset_enable.c: add a message in the case the chipset enable is untested
by Stefan Tauner 21 Jul '11

21 Jul '11

old output: Calibrating delay loop... OK. Found chipset "Intel QS57", enabling flash write... OK. This chipset supports the following protocols: FWH, SPI. new non-verbose output for tested chipsets: Calibrating delay loop... OK. Found chipset "Intel QS57". Enabling flash write... OK. This chipset supports the following protocols: FWH, SPI. new non-verbose output for untested chipsets: Found chipset "Intel QS57". This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... OK. This chipset supports the following protocols: FWH, SPI. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipset_enable.c | 19 ++++++++++++++----- 1 files changed, 14 insertions(+), 5 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index c8aed07..ecb020c 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1226,13 +1226,22 @@ int chipset_flash_enable(void) chipset_enables[i].device_name); continue; } - msg_pinfo("Found chipset \"%s %s\", enabling flash write... ", - chipset_enables[i].vendor_name, - chipset_enables[i].device_name); - msg_pdbg("chipset PCI ID is %04x:%04x, ", + msg_pinfo("Found chipset \"%s %s\"", + chipset_enables[i].vendor_name, + chipset_enables[i].device_name); + msg_pdbg("with PCI ID %04x:%04x", chipset_enables[i].vendor_id, chipset_enables[i].device_id); - + msg_pinfo(". "); + + if (chipset_enables[i].status == NT) { + msg_pinfo("\nThis chipset is marked as untested. If " + "you are using an up-to-date version\nof " + "flashrom please email a report to " + "flashrom(a)flashrom.org including a\nverbose " + "(-V) log. Thank you!\n"); + } + msg_pinfo("Enabling flash write... "); ret = chipset_enables[i].doit(dev, chipset_enables[i].device_name); if (ret == NOT_DONE_YET) { -- 1.7.1

1 0

Re: [flashrom] REPORT: Writing support OK (SST SST39SF020A)
by Stefan Tauner 21 Jul '11

21 Jul '11

On Sun, 17 Jul 2011 11:15:31 -0300 Marcos Felipe Rasia de Mello <marcosfrm(a)gmail.com> wrote: > We can add ASUS P4S533-X to the supported board list. true, i have added it and will commit it later. thanks for pointing that out. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 1

[PATCH] flashrom.8: explain read accesses as part of the write operation
by Stefan Tauner 21 Jul '11

21 Jul '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flashrom.8 | 13 +++++++++---- 1 files changed, 9 insertions(+), 4 deletions(-) diff --git a/flashrom.8 b/flashrom.8 index 5b11f6e..3b7ad40 100644 --- a/flashrom.8 +++ b/flashrom.8 @@ -44,7 +44,12 @@ Write .B <file> into flash ROM. This will first automatically .B erase -the chip, then write to it. +the chip, then write to it. The chip is also read several times: first an +in-memory backup is made for disaster recovery and to be able to skip regions +that are already equal to the image file. This copy is updated after each erase +block (in case of errors it is even re-read completely). After writing has +finished and if verification is enabled, the whole flash is read out and +compared with the input image. .TP .B "\-n, \-\-noverify" Skip the automatic verification of flash ROM contents after writing. Using this @@ -541,7 +546,7 @@ unusable unless you can desolder the flash chip and have a full flash chip backup. This is caused by the embedded controller (EC) present in many laptops, which interacts badly with any flash attempts. This is a hardware limitation and flashrom will attempt to detect it and abort immediately for safety reasons. -.SH LICENCE +.SH LICENSE .B flashrom is covered by the GNU General Public License (GPL), version 2. Some files are additionally available under the GPL (version 2, or any later version). @@ -623,6 +628,6 @@ some others, please see the flashrom svn changelog for details. .br All authors can be reached via email at <flashrom(a)flashrom.org>. .PP -This manual page was written by Uwe Hermann <uwe(a)hermann-uwe.de> -and Carl-Daniel Hailfinger. +This manual page was written by Uwe Hermann <uwe(a)hermann-uwe.de>, +Carl-Daniel Hailfinger and others. It is licensed under the terms of the GNU GPL (version 2 or later). -- 1.7.1

1 0

Re: [flashrom] [PATCH 5/4] ichspi 7.2 - ichspi: improve prettyprint_opcodes
by Stefan Tauner 21 Jul '11

21 Jul '11

before: […] Reading OPCODES... done preop0=0x06, preop1=0x50 op[0]=0x02, 3, 0 op[1]=0x03, 2, 0 op[2]=0x20, 3, 0 op[3]=0x05, 0, 0 op[4]=0x9f, 0, 1 op[5]=0x20, 1, 2 op[6]=0x01, 1, 0 op[7]=0x06, 0, 0 SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: FWH, SPI. […] after: […] Reading OPCODES... done OP Type Pre-OP op[0]: 0x02, write w/ addr, none op[1]: 0x03, read w/ addr, none op[2]: 0x20, write w/ addr, none op[3]: 0x05, read w/o addr, none op[4]: 0x9f, read w/o addr, none op[5]: 0x20, write w/o addr, 1 op[6]: 0x01, write w/o addr, 2 op[7]: 0x06, read w/o addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x50 SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: FWH, SPI. […] i could also print the preops directly in the preop column instead of using that redirection. but i think as debug output it is better to know the index of the two preops too. side note: does it make sense to create an opcode -> string decoder for flashrom-wide usage in user output (in spi25.c)? an erase opcode -> function pointer decoder is used in sfdp, that could also be generalized like that. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

[commit] r1377 - trunk
by repository service 21 Jul '11

21 Jul '11

Author: uwe Date: Thu Jul 21 11:18:18 2011 New Revision: 1377 URL: http://flashrom.org/trac/flashrom/changeset/1377 Log: ft2232_spi: Improve error handling, remove exit() calls. In order to make the ft2232_spi code more usable in libflashrom (e.g. from frontends/GUIs) there must not be any exit() calls in the code, as that would also terminate the frontend. Thus, replace all exit() calls with proper error handling code by returning a _unique_ negative error number, so that the frontend (and/or user/developer) can also know a bit more exactly _which_ error occured, not only _that_ an error occured. Also, call ftdi_usb_close() before returning due to errors. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Tadas Slotkus <devtadas(a)gmail.com> Modified: trunk/ft2232_spi.c Modified: trunk/ft2232_spi.c ============================================================================== --- trunk/ft2232_spi.c Wed Jul 20 18:34:18 2011 (r1376) +++ trunk/ft2232_spi.c Thu Jul 21 11:18:18 2011 (r1377) @@ -150,9 +150,10 @@ .write_256 = default_spi_write_256, }; +/* Returns 0 upon success, a negative number upon errors. */ int ft2232_spi_init(void) { - int f; + int f, ret = 0; struct ftdi_context *ftdic = &ftdic_context; unsigned char buf[512]; int ft2232_vid = FTDI_VID; @@ -195,7 +196,7 @@ } else { msg_perr("Error: Invalid device type specified.\n"); free(arg); - return 1; + return -1; } } free(arg); @@ -211,7 +212,7 @@ default: msg_perr("Error: Invalid port/interface specified.\n"); free(arg); - return 1; + return -2; } } free(arg); @@ -223,7 +224,7 @@ if (ftdi_init(ftdic) < 0) { msg_perr("ftdi_init failed\n"); - return EXIT_FAILURE; // TODO + return -3; } f = ftdi_usb_open(ftdic, ft2232_vid, ft2232_type); @@ -231,7 +232,7 @@ if (f < 0 && f != -5) { msg_perr("Unable to open FTDI device: %d (%s)\n", f, ftdi_get_error_string(ftdic)); - exit(-1); // TODO + return -4; } if (ftdic->type != TYPE_2232H && ftdic->type != TYPE_4232H) { @@ -264,8 +265,10 @@ if (clock_5x) { msg_pdbg("Disable divide-by-5 front stage\n"); buf[0] = 0x8a; /* Disable divide-by-5. */ - if (send_buf(ftdic, buf, 1)) - return -1; + if (send_buf(ftdic, buf, 1)) { + ret = -5; + goto ftdi_err; + } mpsse_clk = 60.0; } else { mpsse_clk = 12.0; @@ -276,8 +279,10 @@ /* valueL/valueH are (desired_divisor - 1) */ buf[1] = (DIVIDE_BY - 1) & 0xff; buf[2] = ((DIVIDE_BY - 1) >> 8) & 0xff; - if (send_buf(ftdic, buf, 3)) - return -1; + if (send_buf(ftdic, buf, 3)) { + ret = -6; + goto ftdi_err; + } msg_pdbg("MPSSE clock: %f MHz divisor: %d " "SPI clock: %f MHz\n", @@ -287,23 +292,36 @@ /* Disconnect TDI/DO to TDO/DI for loopback. */ msg_pdbg("No loopback of TDI/DO TDO/DI\n"); buf[0] = 0x85; - if (send_buf(ftdic, buf, 1)) - return -1; + if (send_buf(ftdic, buf, 1)) { + ret = -7; + goto ftdi_err; + } msg_pdbg("Set data bits\n"); buf[0] = SET_BITS_LOW; buf[1] = cs_bits; buf[2] = pindir; - if (send_buf(ftdic, buf, 3)) - return -1; + if (send_buf(ftdic, buf, 3)) { + ret = -8; + goto ftdi_err; + } // msg_pdbg("\nft2232 chosen\n"); register_spi_programmer(&spi_programmer_ft2232); return 0; + +ftdi_err: + if ((f = ftdi_usb_close(ftdic)) < 0) { + msg_perr("Unable to close FTDI device: %d (%s)\n", f, + ftdi_get_error_string(ftdic)); + } + + return ret; } +/* Returns 0 upon success, a negative number upon errors. */ static int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { @@ -324,7 +342,8 @@ buf = realloc(buf, bufsize); if (!buf) { msg_perr("Out of memory!\n"); - exit(1); + /* TODO: What to do with buf? */ + return SPI_GENERIC_ERROR; } oldbufsize = bufsize; }

1 0

[PATCH 4/4] ichspi.c: add support for Intel Hardware Sequencing
by Stefan Tauner 20 Jul '11

20 Jul '11

todo: - revise hwseq activation: when should hwseq be used, when swseq? in the current version i have added a programmer parameter to tell flashrom when one wants to use hwseq _if it is available_ (i.e. descriptor valid), example: flashrom -p internal:laptop=force_I_want_a_brick,hwseq=yes -VV this needs to be documented in the man page if it gets merged like that. - commit message (is a link to my blog post a good idea (additionally)?) - revise (levels of) prints - revise timeout values (for optimal performance) - build upon the upcoming opaque interface framework instead Tested-by: David Hendricks <dhendrix(a)google.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipdrivers.h | 6 + flashchips.c | 23 ++++- flashchips.h | 2 + ich_descriptors.c | 35 ++++++ ich_descriptors.h | 1 + ichspi.c | 351 +++++++++++++++++++++++++++++++++++++++++++++++++++-- programmer.h | 1 + 7 files changed, 406 insertions(+), 13 deletions(-) diff --git a/chipdrivers.h b/chipdrivers.h index 92ddbea..f97e2ad 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -84,6 +84,12 @@ void print_status_82802ab(uint8_t status); int unlock_82802ab(struct flashchip *flash); int unlock_28f004s5(struct flashchip *flash); +/* ichspi.c */ +int ich_hwseq_probe(struct flashchip *flash); +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int start, int len); +int ich_hwseq_block_erase(struct flashchip *flash, unsigned int addr, unsigned int blocklen); +int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); + /* jedec.c */ uint8_t oddparity(uint8_t val); void toggle_ready_jedec(chipaddr dst); diff --git a/flashchips.c b/flashchips.c index 7cfd5a7..cec18c9 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8535,7 +8535,27 @@ const struct flashchip flashchips[] = { .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program */ }, - +#if defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) + { + .vendor = "Intel", + .name = "Hardware Sequencing", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = INTEL_ID, + .model_id = INTEL_HWSEQ, + .total_size = 0, + .page_size = 256, + .tested = TEST_OK_PREW, + .probe = ich_hwseq_probe, + .block_erasers = + { + { /* erase blocks will be set by the probing function */ + .block_erase = ich_hwseq_block_erase, + } + }, + .write = ich_hwseq_write_256, + .read = ich_hwseq_read, + }, +#endif // defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) { .vendor = "AMIC", .name = "unknown AMIC SPI chip", @@ -8668,6 +8688,7 @@ const struct flashchip flashchips[] = { .probe = probe_spi_rdid, .write = NULL, }, + { .vendor = "Generic", .name = "unknown SPI chip (REMS)", diff --git a/flashchips.h b/flashchips.h index 3b2b94f..6b8d574 100644 --- a/flashchips.h +++ b/flashchips.h @@ -340,6 +340,8 @@ #define SHARP_LH28F008SA 0xA2 /* Sharp chip, Intel Vendor ID */ #define SHARP_LH28F008SC 0xA6 /* Sharp chip, Intel Vendor ID */ +#define INTEL_HWSEQ 0xFFFE /* dummy ID for hardware sequencing */ + #define ISSI_ID 0xD5 /* ISSI Integrated Silicon Solutions */ /* diff --git a/ich_descriptors.c b/ich_descriptors.c index db1e11c..6a14580 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -600,6 +600,41 @@ int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, enum #else // ICH_DESCRIPTORS_FROM_DUMP +/** Returns the integer representation of the component density with index +idx in bytes or 0 if a correct size can not be determined. */ +int getFCBA_component_density(uint8_t idx, const struct flash_descriptors *desc) +{ + uint8_t size_enc; + const int dec_mem[6] = { + 512 * 1024, + 1 * 1024 * 1024, + 2 * 1024 * 1024, + 4 * 1024 * 1024, + 8 * 1024 * 1024, + 16 * 1024 * 1024, + }; + + switch(idx) { + case 0: + size_enc = desc->component.comp1_density; + break; + case 1: + if (desc->content.NC == 0) + return 0; + size_enc = desc->component.comp2_density; + break; + default: + msg_perr("Only component index 0 or 1 are supported yet.\n"); + return 0; + } + if (size_enc > 5) { + msg_perr("Density of component with index %d is invalid. " + "Encoded density is 0x%x.\n", idx, size_enc); + return 0; + } + return dec_mem[size_enc]; +} + static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) { uint32_t control = 0; diff --git a/ich_descriptors.h b/ich_descriptors.h index a90897c..6dd4bdf 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -468,6 +468,7 @@ int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, enum #else // ICH_DESCRIPTORS_FROM_DUMP void read_ich_descriptors_via_fdo(void *spibar, struct flash_descriptors *desc); +int getFCBA_component_density(uint8_t idx, const struct flash_descriptors *desc); #endif // ICH_DESCRIPTORS_FROM_DUMP #endif // __ICH_DESCRIPTORS_H__ diff --git a/ichspi.c b/ichspi.c index b5ee23a..283dcf7 100644 --- a/ichspi.c +++ b/ichspi.c @@ -23,10 +23,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if defined(__i386__) || defined(__x86_64__) +#if defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) #include <string.h> +#include <stdlib.h> #include "flash.h" +#include "flashchips.h" #include "chipdrivers.h" #include "programmer.h" #include "spi.h" @@ -1073,6 +1075,298 @@ static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, return result; } +static struct hwseq { + uint32_t size_comp0; + uint32_t size_comp1; +} hwseq; + +static void ich_hwseq_set_addr(uint32_t addr) +{ + uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF; + REGWRITE32(ICH9_REG_FADDR, (addr & 0x01FFFFFF) | addr_old); +} + +/* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes + * of the block containing this address. */ +static uint32_t ich_hwseq_get_erase_block_size(unsigned int addr) +{ + uint8_t enc_berase; + const uint32_t dec_berase[4] = { + 256, + 4 * 1024, + 8 * 1024, + 64 * 1024 + }; + + ich_hwseq_set_addr(addr); + enc_berase = (REGREAD16(ICH9_REG_HSFS) & HSFS_BERASE) >> + HSFS_BERASE_OFF; + return dec_berase[enc_berase]; +} + +/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 10 us intervals. + Resets all error flags in HSFS. + Returns 0 if the cycle completes successfully without errors within + timeout us, 1 on errors. */ +static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, + unsigned int len) +{ + uint16_t hsfs; + uint32_t addr; + + while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) & + (HSFS_FDONE | HSFS_FCERR)) == 0) && + --timeout) { + programmer_delay(10); + } + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + if (!timeout) { + addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; + msg_perr("Timeout error between offset 0x%08x and " + "0x%08x + %d (=0x%08x)!\n", + addr, addr, len - 1, addr + len - 1); + prettyprint_ich9_reg_hsfs(hsfs); + prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); + return 1; + } + + if (hsfs & HSFS_FCERR) { + addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; + msg_perr("Transaction error between offset 0x%08x and " + "0x%08x (=0x%08x + %d)!\n", + addr, addr + len - 1, addr, len - 1); + prettyprint_ich9_reg_hsfs(hsfs); + prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); + return 1; + } + return 0; +} + +int ich_hwseq_probe(struct flashchip *flash) +{ + uint32_t total_size, boundary; + uint32_t erase_size_low, size_low, erase_size_high, size_high; + struct block_eraser *eraser; + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_cerr("This chip (%s) is not supported in hardware" + "sequencing mode and should never have been probed.\n", + flash->name); + msg_cerr("%s: Please report a bug at flashrom(a)flashrom.org\n", + __func__); + return 0; + } + + msg_cdbg("Prerequisites for Intel Hardware Sequencing are "); + if (spi_programmer->type != SPI_CONTROLLER_ICH_HWSEQ) { + msg_cdbg("not met.\n"); + return 0; + } + msg_cdbg("met.\n"); + + total_size = hwseq.size_comp0 + hwseq.size_comp1; + msg_cdbg("Found %d attached SPI flash chip", + (hwseq.size_comp1 != 0) ? 2 : 1); + if (hwseq.size_comp1 != 0) + msg_cdbg("s with a combined"); + else + msg_cdbg(" with a"); + msg_cdbg(" density of %d kB.\n", total_size / 1024); + flash->total_size = total_size / 1024; + + eraser = &(flash->block_erasers[0]); + boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12; + size_high = total_size - boundary; + erase_size_high = ich_hwseq_get_erase_block_size(boundary); + + if (boundary == 0) { + msg_cdbg("There is only one partition containing the whole " + "address space (0x%06x - 0x%06x).\n", 0, size_high-1); + eraser->eraseblocks[0].size = erase_size_high; + eraser->eraseblocks[0].count = size_high / erase_size_high; + msg_cdbg("There are %d erase blocks with %d B each.\n", + size_high / erase_size_high, erase_size_high); + } else { + msg_cdbg("The flash address space (0x%06x - 0x%06x) is divided " + "at address 0x%06x in two partitions.\n", + 0, size_high-1, boundary); + size_low = total_size - size_high; + erase_size_low = ich_hwseq_get_erase_block_size(0); + + eraser->eraseblocks[0].size = erase_size_low; + eraser->eraseblocks[0].count = size_low / erase_size_low; + msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n", + 0, size_low-1); + msg_cdbg("In that range are %d erase blocks with %d B each.\n", + size_low / erase_size_low, erase_size_low); + + eraser->eraseblocks[1].size = erase_size_high; + eraser->eraseblocks[1].count = size_high / erase_size_high; + msg_cdbg("The second partition ranges from 0x%06x to 0x%06x.\n", + boundary, size_high-1); + msg_cdbg("In that range are %d erase blocks with %d B each.\n", + size_high / erase_size_high, erase_size_high); + } + return 1; +} + +static int ich_hwseq_send_command(unsigned int writecnt, + unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + msg_pdbg("skipped. Intel Hardware Sequencing does not support sending " + "arbitrary commands."); + return -1; +} + +int ich_hwseq_block_erase(struct flashchip *flash, + unsigned int addr, + unsigned int len) +{ + uint32_t erase_block; + uint16_t hsfc; + uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */ + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode\n", flash->name); + return -1; + } + + erase_block = ich_hwseq_get_erase_block_size(addr); + if (len != erase_block) { + msg_cerr("Erase block size for address 0x%06x is %d B, " + "but requested erase block size is %d B. " + "Not erasing anything.\n", addr, erase_block, len); + return -1; + } + + /* Although the hardware supports this (it would erase the whole block + * containing the address) we play safe here. */ + if (addr % erase_block != 0) { + msg_cerr("Erase address 0x%06x is not aligned to the erase " + "block boundary (any multiple of %d). " + "Not erasing anything.\n", addr, erase_block); + return -1; + } + + if (addr + len > flash->total_size * 1024) { + msg_perr("Request to erase some inaccessible memory address(es)" + " (addr=0x%x, len=%d). " + "Not erasing anything.\n", addr, len); + return -1; + } + + msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr); + + /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ + hsfc |= HSFC_FGO; /* start */ + msg_pdbg("HSFC used for block erasing: "); + prettyprint_ich9_reg_hsfc(hsfc); + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, len)) + return -1; + return 0; +} + +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int addr, int len) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode.\n", flash->name); + return -1; + } + + if (addr < 0 || addr + len > flash->total_size * 1024) { + msg_perr("Request to read from an inaccessible memory address " + "(addr=0x%x, len=%d).\n", addr, len); + return -1; + } + + msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + while (len > 0) { + block_len = min(len, spi_programmer->max_data_read); + ich_hwseq_set_addr(addr); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* set read operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + return 1; + ich_read_data(buf, block_len, ICH9_REG_FDATA0); + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} + +int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, int addr, int len) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode\n", flash->name); + return -1; + } + + if (addr < 0 || addr + len > flash->total_size * 1024) { + msg_perr("Request to write to an inaccessible memory address " + "(addr=0x%x, len=%d).\n", addr, len); + return -1; + } + + msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + while (len > 0) { + ich_hwseq_set_addr(addr); + block_len = min(len, spi_programmer->max_data_write); + ich_fill_data(buf, block_len, ICH9_REG_FDATA0); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + return -1; + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} + static int ich_spi_send_multicommand(struct spi_command *cmds) { int ret = 0; @@ -1187,6 +1481,16 @@ static const struct spi_programmer spi_programmer_ich9 = { .write_256 = default_spi_write_256, }; +static const struct spi_programmer spi_programmer_ich_hwseq = { + .type = SPI_CONTROLLER_ICH_HWSEQ, + .max_data_read = 64, + .max_data_write = 64, + .command = ich_hwseq_send_command, + .multicommand = default_spi_send_multicommand, + .read = ich_hwseq_read, + .write_256 = ich_hwseq_write_256, +}; + int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, int ich_generation) { @@ -1194,21 +1498,21 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, uint8_t old, new; uint16_t spibar_offset, tmp2; uint32_t tmp; + char *arg; int ichspi_desc = 0; + int hwseq_en = 0; + struct flash_descriptors desc = {{ 0 }}; switch (ich_generation) { case 7: - register_spi_programmer(&spi_programmer_ich7); spibar_offset = 0x3020; break; case 8: - register_spi_programmer(&spi_programmer_ich9); spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ - register_spi_programmer(&spi_programmer_ich9); spibar_offset = 0x3800; break; } @@ -1219,8 +1523,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, /* Assign Virtual Address */ ich_spibar = rcrb + spibar_offset; - switch (spi_programmer->type) { - case SPI_CONTROLLER_ICH7: + switch (ich_generation) { + case 7: msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", @@ -1256,9 +1560,21 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } + register_spi_programmer(&spi_programmer_ich7); ich_init_opcodes(); break; - case SPI_CONTROLLER_ICH9: + case 8: + case 9: + case 10: + default: /* Future version might behave the same */ + arg = extract_programmer_param("hwseq"); + if (arg && !strcmp(arg, "yes")) + hwseq_en = 1; + else if (arg && !strlen(arg)) + msg_pinfo("Missing argument for hwseq.\n"); + else if (arg) + msg_pinfo("Unknown argument for hwseq: %s\n", arg); + free(arg); tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); prettyprint_ich9_reg_hsfs(tmp2); @@ -1334,14 +1650,25 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pdbg("\n"); if (ichspi_desc) { - struct flash_descriptors desc = {{ 0 }}; read_ich_descriptors_via_fdo(ich_spibar, &desc); prettyprint_ich_descriptors(CHIPSET_UNKNOWN, &desc); + /* If the descriptor is valid and indicates multiple + * flash devices we need to use hwseq to be able to + * access the second flash device. + */ + if (desc.content.NC != 0) + hwseq_en = 1; + } else + hwseq_en = 0; /* disable it even if the user said yes */ + + if (hwseq_en > 0) { + hwseq.size_comp0 = getFCBA_component_density(0, &desc); + hwseq.size_comp1 = getFCBA_component_density(1, &desc); + register_spi_programmer(&spi_programmer_ich_hwseq); + } else { + register_spi_programmer(&spi_programmer_ich9); + ich_init_opcodes(); } - ich_init_opcodes(); - break; - default: - /* Nothing */ break; } diff --git a/programmer.h b/programmer.h index 6a28dbe..6e316d1 100644 --- a/programmer.h +++ b/programmer.h @@ -517,6 +517,7 @@ enum spi_controller { #if defined(__i386__) || defined(__x86_64__) SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, + SPI_CONTROLLER_ICH_HWSEQ, SPI_CONTROLLER_IT85XX, SPI_CONTROLLER_IT87XX, SPI_CONTROLLER_SB600, -- 1.7.1

1 0

[PATCH 3/4] add ich_descriptor_tool to decode all flash descriptors stored in a flash dump file
by Stefan Tauner 20 Jul '11

20 Jul '11

additionally to what is available via FDOC/FDOD this allows to access: - the softstraps which are used to configure the chipset by flash content without the need for BIOS routines. on ICH8 it is possible to read those with FDOC/FDOC too, but this was removed in later chipsets. - the ME VSCC (Vendor Specific Component Capabilities) table simply put, this is an SPI chip database used by the ME to figure out the flash's capabilities Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ich_descriptors.c | 399 ++++++++++++++++++++++ ich_descriptors.h | 210 ++++++++++++ util/ich_descriptors_tool/Makefile | 42 +++ util/ich_descriptors_tool/TODO | 6 + util/ich_descriptors_tool/ich_descriptors_tool.c | 225 ++++++++++++ 5 files changed, 882 insertions(+), 0 deletions(-) create mode 100644 util/ich_descriptors_tool/Makefile create mode 100644 util/ich_descriptors_tool/TODO create mode 100644 util/ich_descriptors_tool/ich_descriptors_tool.c diff --git a/ich_descriptors.c b/ich_descriptors.c index cf77601..db1e11c 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -22,8 +22,32 @@ #if defined(__i386__) || defined(__x86_64__) #include "ich_descriptors.h" + +#ifdef ICH_DESCRIPTORS_FROM_DUMP + +#include <stdio.h> +#define msg_pdbg printf +#define msg_pspew printf +#define DESCRIPTOR_MODE_SIGNATURE 0x0ff0a55a +/* The upper map is located in the word before the 256B-long OEM section at the + * end of the 4kB-long flash descriptor. + */ +#define UPPER_MAP_OFFSET (4096 - 256 - 4) +#define getVTBA(flumap) (((flumap)->FLUMAP1 << 4) & 0x00000ff0) + +#ifndef min +#define min(a, b) (a < b) ? a : b +#endif +#ifndef max +#define max(a, b) (a > b) ? a : b +#endif + +#else // ICH_DESCRIPTORS_FROM_DUMP + #include "flash.h" /* for msg_* */ +#endif // ICH_DESCRIPTORS_FROM_DUMP + #define getFCBA(cont) (((cont)->FLMAP0 << 4) & 0x00000ff0) #define getFRBA(cont) (((cont)->FLMAP0 >> 12) & 0x00000ff0) #define getFMBA(cont) (((cont)->FLMAP1 << 4) & 0x00000ff0) @@ -36,6 +60,12 @@ void prettyprint_ich_descriptors(enum chipset cs, const struct flash_descriptors prettyprint_ich_descriptor_component(desc); prettyprint_ich_descriptor_region(&desc->region); prettyprint_ich_descriptor_master(&desc->master); +#ifdef ICH_DESCRIPTORS_FROM_DUMP + if (cs >= CHIPSET_ICH8) { + prettyprint_ich_descriptor_upper_map(&desc->upper); + prettyprint_ich_descriptor_straps(cs, desc); + } +#endif // ICH_DESCRIPTORS_FROM_DUMP } void prettyprint_ich_descriptor_content(const struct flash_content *cont) @@ -202,6 +232,374 @@ void prettyprint_ich9_reg_vscc(uint32_t reg_val) pprint_reg(VSCC, VCL, reg_val, "\n"); } +#ifdef ICH_DESCRIPTORS_FROM_DUMP + +void prettyprint_ich_descriptor_straps_ich8(const struct flash_descriptors *desc) +{ + const char * const str_GPIO12[4] = { + "GPIO12", + "LAN PHY Power Control Function (Native Output)", + "GLAN_DOCK# (Native Input)", + "invalid configuration", + }; + + + msg_pdbg2("--- MCH details ---\n"); + msg_pdbg2("ME B is %sabled.\n", desc->north.ich8.MDB ? "dis" : "en"); + msg_pdbg2("\n"); + + msg_pdbg2("--- ICH details ---\n"); + msg_pdbg2("ME SMBus Address 1: 0x%02x\n", desc->south.ich8.ASD); + msg_pdbg2("ME SMBus Address 2: 0x%02x\n", desc->south.ich8.ASD2); + msg_pdbg2("ME SMBus Controller is connected to the %s.\n", + desc->south.ich8.MESM2SEL ? "SMLink pins" : "SMBus pins"); + msg_pdbg2("SPI CS1 is used for %s.\n", + desc->south.ich8.SPICS1_LANPHYPC_SEL ? + "LAN PHY Power Control Function" : + "SPI Chip Select"); + msg_pdbg2("GPIO12 Select is used as %s.\n", + str_GPIO12[desc->south.ich8.GPIO12_SEL]); + msg_pdbg2("PCIe Port 6 is used for %s.\n", + desc->south.ich8.GLAN_PCIE_SEL ? "integrated LAN" : "PCI Express"); + msg_pdbg2("%sn BMC Mode: " + "Intel AMT SMBus Controller 1 is connected to %s.\n", + desc->south.ich8.BMCMODE ? "I" : "Not i", + desc->south.ich8.BMCMODE ? "SMLink" : "SMBus"); + msg_pdbg2("TCO is in %s Mode.\n", + desc->south.ich8.TCOMODE ? "Advanced TCO" : "Legacy/Compatible"); + msg_pdbg2("ME A is %sabled.\n", + desc->south.ich8.ME_DISABLE ? "dis" : "en"); + msg_pdbg2("\n"); +} + +static void prettyprint_ich_descriptor_straps_ibex_pciecs(uint8_t conf, uint8_t off) +{ + msg_pdbg2("PCI Express Port Configuration Strap %d: ", off+1); + + off *= 4; + switch(conf){ + case 0: + msg_pdbg2("4x1 Ports %d-%d (x1)", 1+off, 4+off); + break; + case 1: + msg_pdbg2("1x2, 2x1 Port %d (x2), Port %d (disabled), " + "Ports %d, %d (x1)", 1+off, 2+off, 3+off, 4+off); + break; + case 2: + msg_pdbg2("2x2 Port %d (x2), Port %d (x2), Ports " + "%d, %d (disabled)", 1+off, 3+off, 2+off, 4+off); + break; + case 3: + msg_pdbg2("1x4 Port %d (x4), Ports %d-%d (disabled)", + 1+off, 2+off, 4+off); + break; + } + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_straps_ibex(const struct flash_south_strap *s) +{ + const uint8_t const dec_t209min[4] = { + 100, + 50, + 5, + 1 + }; + + msg_pdbg2("--- PCH ---\n"); + + /* PCHSTRP1 */ + msg_pdbg2("Chipset configuration Softstrap 2: %d\n", s->ibex.cs_ss2); + msg_pdbg2("Intel ME SMBus Select is %sabled.\n", + s->ibex.SMB_EN ? "en" : "dis"); + msg_pdbg2("SMLink0 segment is %sabled.\n", + s->ibex.SML0_EN ? "en" : "dis"); + msg_pdbg2("SMLink1 segment is %sabled.\n", + s->ibex.SML1_EN ? "en" : "dis"); + msg_pdbg2("SMLink1 Frequency: %s\n", + (s->ibex.SML1FRQ == 1) ? "100 kHz" : "reserved"); + msg_pdbg2("Intel ME SMBus Frequency: %s\n", + (s->ibex.SMB0FRQ == 1) ? "100 kHz" : "reserved"); + msg_pdbg2("SMLink0 Frequency: %s\n", + (s->ibex.SML0FRQ == 1) ? "100 kHz" : "reserved"); + msg_pdbg2("GPIO12 is used as %s.\n", s->ibex.LANPHYPC_GP12_SEL ? + "LAN_PHY_PWR_CTRL" : "general purpose output"); + + /* PCHSTRP2 */ + msg_pdbg2("Chipset configuration Softstrap 3: 0x%x\n", s->ibex.cs_ss3); + + /* PCHSTRP3 */ + msg_pdbg2("ME SMBus ASD address is %sabled.\n", + s->ibex.MESMASDEN ? "en" : "dis"); + msg_pdbg2("ME SMBus Controller ASD Target address: 0x%02x\n", + s->ibex.MESMASDA); + msg_pdbg2("ME SMBus I2C address is %sabled.\n", + s->ibex.MESMI2CEN ? "en" : "dis"); + msg_pdbg2("ME SMBus I2C target address: 0x%02x\n", + s->ibex.MESMI2CA); + + /* PCHSTRP4 */ + /* PCHSTRP5 */ + msg_pdbg2("Intel PHY is %s.\n", + (s->ibex.PHYCON == 2) ? "connected" : + (s->ibex.PHYCON == 0) ? "disconnected" : "reserved"); + msg_pdbg2("GbE MAC SMBus address is %sabled.\n", + s->ibex.GBEMAC_SMBUS_ADDR_EN ? "en" : "dis"); + msg_pdbg2("GbE MAC SMBus address: 0x%02x\n", + s->ibex.GBEMAC_SMBUS_ADDR); + msg_pdbg2("GbE PHY SMBus address: 0x%02x\n", + s->ibex.GBEPHY_SMBUS_ADDR); + + /* PCHSTRP6 */ + /* PCHSTRP7 */ + msg_pdbg2("Intel ME SMBus Subsystem Vendor ID: 0x%04x\n", + s->ibex.MESMA2UDID_VENDOR); + msg_pdbg2("Intel ME SMBus Subsystem Device ID: 0x%04x\n", + s->ibex.MESMA2UDID_VENDOR); + + /* PCHSTRP8 */ + /* PCHSTRP9 */ + prettyprint_ich_descriptor_straps_ibex_pciecs(s->ibex.PCIEPCS1, 0); + prettyprint_ich_descriptor_straps_ibex_pciecs(s->ibex.PCIEPCS1, 1); + msg_pdbg2("PCIe Lane Reversal 1: PCIe Lanes 0-3 are %sreserved.\n", + s->ibex.PCIELR1 ? "" : "not "); + msg_pdbg2("PCIe Lane Reversal 2: PCIe Lanes 4-7 are %sreserved.\n", + s->ibex.PCIELR2 ? "" : "not "); + msg_pdbg2("DMI Lane Reversal: DMI Lanes 0-3 are %sreserved.\n", + s->ibex.DMILR ? "" : "not "); + msg_pdbg2("Default PHY PCIe Port is %d.\n", s->ibex.PHY_PCIEPORTSEL+1); + msg_pdbg2("Integrated MAC/PHY communication over PCIe is %sabled.\n", + s->ibex.PHY_PCIE_EN ? "en" : "dis"); + + /* PCHSTRP10 */ + msg_pdbg2("Management Engine will boot from %sflash.\n", + s->ibex.ME_BOOT_FLASH ? "" : "ROM, then "); + msg_pdbg2("Chipset configuration Softstrap 5: %d\n", s->ibex.cs_ss5); + msg_pdbg2("Virtualization Engine Enable 1 is %sabled.\n", + s->ibex.VE_EN ? "en" : "dis"); + msg_pdbg2("ME Memory-attached Debug Display Device is %sabled.\n", + s->ibex.MMDDE ? "en" : "dis"); + msg_pdbg2("ME Memory-attached Debug Display Device address: 0x%02x\n", + s->ibex.MMADDR); + msg_pdbg2("Chipset configuration Softstrap 7: %d\n", s->ibex.cs_ss7); + msg_pdbg2("Integrated Clocking Configuration is %d.\n", + (s->ibex.ICC_SEL == 7) ? 0 : s->ibex.ICC_SEL); + msg_pdbg2("PCH Signal CL_RST1# does %sassert when Intel ME performs a " + "reset.\n", s->ibex.MER_CL1 ? "" : "not "); + + /* PCHSTRP11 */ + msg_pdbg2("SMLink1 GP Address is %sabled.\n", + s->ibex.SML1GPAEN ? "en" : "dis"); + msg_pdbg2("SMLink1 controller General Purpose Target address: 0x%02x\n", + s->ibex.SML1GPA); + msg_pdbg2("SMLink1 I2C Target address is %sabled.\n", + s->ibex.SML1I2CAEN ? "en" : "dis"); + msg_pdbg2("SMLink1 I2C Target address: 0x%02x\n", + s->ibex.SML1I2CA); + + /* PCHSTRP12 */ + /* PCHSTRP13 */ + /* PCHSTRP14 */ + msg_pdbg2("Virtualization Engine Enable 2 is %sabled.\n", + s->ibex.VE_EN2 ? "en" : "dis"); + msg_pdbg2("Virtualization Engine will boot from %sflash.\n", + s->ibex.VE_BOOT_FLASH ? "" : "ROM, then "); + msg_pdbg2("Braidwood SSD functionality is %sabled.\n", + s->ibex.BW_SSD ? "en" : "dis"); + msg_pdbg2("Braidwood NVMHCI functionality is %sabled.\n", + s->ibex.NVMHCI_EN ? "en" : "dis"); + + /* PCHSTRP15 */ + msg_pdbg2("Chipset configuration Softstrap 6: %d\n", s->ibex.cs_ss6); + msg_pdbg2("Integrated wired LAN Solution is %sabled.\n", + s->ibex.IWL_EN ? "en" : "dis"); + msg_pdbg2("t209 min Timing: %d ms\n", + dec_t209min[s->ibex.t209min]); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_straps(enum chipset cs, const struct flash_descriptors *desc) +{ + unsigned int i, max; + msg_pdbg1("=== Softstraps ===\n"); + + if (sizeof(desc->north.STRPs) / 4 + 1 < desc->content.MSL) { + max = sizeof(desc->north.STRPs) / 4 + 1; + msg_pdbg1("MSL (%u) is greater than the current maximum of %u " + "entries.\n", desc->content.MSL, max + 1); + msg_pdbg1("Only the first %u entries will be printed.\n", max); + } else + max = desc->content.MSL; + + msg_pdbg1("--- North/MCH/PROC (%d entries) ---\n", max); + for(i = 0; i < max; i++) + msg_pdbg1("STRP%-2d = 0x%08x\n", i, desc->north.STRPs[i]); + msg_pdbg1("\n"); + + if (sizeof(desc->south.STRPs) / 4 < desc->content.ISL) { + max = sizeof(desc->south.STRPs) / 4; + msg_pdbg1("ISL (%u) is greater than the current maximum of %u " + "entries.\n", desc->content.ISL, max); + msg_pdbg1("Only the first %u entries will be printed.\n", max); + } else + max = desc->content.ISL; + + msg_pdbg1("--- South/ICH/PCH (%d entries) ---\n", max); + for(i = 0; i < max; i++) + msg_pdbg1("STRP%-2d = 0x%08x\n", i, desc->south.STRPs[i]); + msg_pdbg1("\n"); + + switch (cs) { + case CHIPSET_ICH8: + if (sizeof(desc->north.ich8) / 4 != desc->content.MSL) + msg_pdbg2("Detailed North/MCH/PROC information is " + "probably not reliable, printing anyway.\n"); + if (sizeof(desc->south.ich8) / 4 != desc->content.ISL) + msg_pdbg2("Detailed South/ICH/PCH information is " + "probably not reliable, printing anyway.\n"); + prettyprint_ich_descriptor_straps_ich8(desc); + break; + case CHIPSET_5_SERIES_IBEX_PEAK: + /* PCH straps only. PROCSTRPs are unknown. */ + if (sizeof(desc->south.ibex) / 4 != desc->content.ISL) + msg_pdbg2("Detailed South/ICH/PCH information is " + "probably not reliable, printing anyway.\n"); + prettyprint_ich_descriptor_straps_ibex(&desc->south); + break; + case CHIPSET_UNKNOWN: + break; + default: + msg_pdbg2("The meaning of the descriptor straps are unknown " + "yet.\n\n"); + break; + } +} + +void prettyprint_rdid(uint32_t reg_val) +{ + uint8_t mid = reg_val & 0xFF; + uint16_t did = ((reg_val >> 16) & 0xFF) | (reg_val & 0xFF00); + msg_pdbg2("Manufacturer ID 0x%02x, Device ID 0x%04x\n", mid, did); +} + +void prettyprint_ich_descriptor_upper_map(const struct flash_upper_map *umap) +{ + int i; + msg_pdbg1("=== Upper Map Section ===\n"); + msg_pdbg1("FLUMAP1 0x%08x\n", umap->FLUMAP1); + msg_pdbg1("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2("VTL (length) = %d\n", umap->VTL); + msg_pdbg2("VTBA (base address) = 0x%6.6x\n", getVTBA(umap)); + msg_pdbg2("\n"); + + msg_pdbg2("VSCC Table: %d entries\n", umap->VTL/2); + for (i = 0; i < umap->VTL/2; i++) + { + uint32_t jid = umap->vscc_table[i].JID; + uint32_t vscc = umap->vscc_table[i].VSCC; + msg_pdbg2(" JID%d = 0x%08x\n", i, jid); + msg_pdbg2(" VSCC%d = 0x%08x\n", i, vscc); + msg_pdbg2(" "); /* indention */ + prettyprint_rdid(jid); + msg_pdbg2(" "); /* indention */ + prettyprint_ich9_reg_vscc(vscc); + } + msg_pdbg2("\n"); +} + +/* len is the length of dump in bytes */ +int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, enum chipset cs, struct flash_descriptors *desc) +{ + unsigned int i, max; + uint8_t pch_bug_offset = 0; + + if (dump == NULL || desc == NULL) + return RET_PARAM; + + if (dump[0] != DESCRIPTOR_MODE_SIGNATURE) { + if (dump[4] == DESCRIPTOR_MODE_SIGNATURE) + pch_bug_offset = 4; + else { + return RET_ERR;} + } + + /* map */ + if (len < (4 + pch_bug_offset) * 4 - 1) + return RET_OOB; + desc->content.FLVALSIG = dump[0 + pch_bug_offset]; + desc->content.FLMAP0 = dump[1 + pch_bug_offset]; + desc->content.FLMAP1 = dump[2 + pch_bug_offset]; + desc->content.FLMAP2 = dump[3 + pch_bug_offset]; + + /* component */ + if (len < (getFCBA(&desc->content) + 3 * 4 - 1)) + return RET_OOB; + desc->component.FLCOMP = dump[(getFCBA(&desc->content) >> 2) + 0]; + desc->component.FLILL = dump[(getFCBA(&desc->content) >> 2) + 1]; + desc->component.FLPB = dump[(getFCBA(&desc->content) >> 2) + 2]; + + /* region */ + if (len < (getFRBA(&desc->content) + 5 * 4 - 1)) + return RET_OOB; + desc->region.FLREGs[0] = dump[(getFRBA(&desc->content) >> 2) + 0]; + desc->region.FLREGs[1] = dump[(getFRBA(&desc->content) >> 2) + 1]; + desc->region.FLREGs[2] = dump[(getFRBA(&desc->content) >> 2) + 2]; + desc->region.FLREGs[3] = dump[(getFRBA(&desc->content) >> 2) + 3]; + desc->region.FLREGs[4] = dump[(getFRBA(&desc->content) >> 2) + 4]; + + /* master */ + if (len < (getFMBA(&desc->content) + 3 * 4 - 1)) + return RET_OOB; + desc->master.FLMSTR1 = dump[(getFMBA(&desc->content) >> 2) + 0]; + desc->master.FLMSTR2 = dump[(getFMBA(&desc->content) >> 2) + 1]; + desc->master.FLMSTR3 = dump[(getFMBA(&desc->content) >> 2) + 2]; + + /* upper map */ + desc->upper.FLUMAP1 = dump[(UPPER_MAP_OFFSET >> 2) + 0]; + + /* VTL is 8 bits long. Quote from the Ibex Peak SPI programming guide: + * "Identifies the 1s based number of DWORDS contained in the VSCC + * Table. Each SPI component entry in the table is 2 DWORDS long." So + * the maximum of 255 gives us 127.5 SPI components(!?) 8 bytes each. A + * check ensures that the maximum offset actually accessed is available. + */ + if (len < (getVTBA(&desc->upper) + (desc->upper.VTL / 2 * 8) - 1)) + return RET_OOB; + + for (i = 0; i < desc->upper.VTL/2; i++) { + desc->upper.vscc_table[i].JID = + dump[(getVTBA(&desc->upper) >> 2) + i * 2 + 0]; + desc->upper.vscc_table[i].VSCC = + dump[(getVTBA(&desc->upper) >> 2) + i * 2 + 1]; + } + + /* MCH/PROC (aka. North) straps */ + if (len < getFMSBA(&desc->content) + desc->content.MSL * 4) + return RET_OOB; + + /* limit the range to be written */ + max = min(sizeof(desc->north.STRPs) / 4, desc->content.MSL); + for (i = 0; i < max; i++) + desc->north.STRPs[i] = + dump[(getFMSBA(&desc->content) >> 2) + i]; + + /* ICH/PCH (aka. South) straps */ + if (len < getFISBA(&desc->content) + desc->content.ISL * 4) + return RET_OOB; + + /* limit the range to be written */ + max = min(sizeof(desc->south.STRPs) / 4, desc->content.ISL); + for (i = 0; i < max; i++) + desc->south.STRPs[i] = + dump[(getFISBA(&desc->content) >> 2) + i]; + + return RET_OK; +} + +#else // ICH_DESCRIPTORS_FROM_DUMP + static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) { uint32_t control = 0; @@ -244,4 +642,5 @@ void read_ich_descriptors_via_fdo(void *spibar, struct flash_descriptors *desc) msg_pdbg1(" done\n"); } +#endif // ICH_DESCRIPTORS_FROM_DUMP #endif // defined(__i386__) || defined(__x86_64__) diff --git a/ich_descriptors.h b/ich_descriptors.h index f248394..a90897c 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -29,6 +29,12 @@ #define msg_pdbg1 msg_pdbg #define msg_pdbg2 msg_pspew +#define RET_OK 0 +#define RET_ERR -1 +#define RET_WARN -2 +#define RET_PARAM -3 +#define RET_OOB -4 + #define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */ /* 0-1: reserved */ #define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */ @@ -244,11 +250,206 @@ struct flash_master { }; }; +#ifdef ICH_DESCRIPTORS_FROM_DUMP +struct flash_north_strap { + union { + uint32_t STRPs[1]; /* current maximum: ich8 */ + struct { /* ich8 */ + struct { /* STRP2 (in the datasheet) */ + uint32_t MDB :1; + uint32_t :31; + }; + } ich8; + }; +}; + +struct flash_south_strap { + union { + uint32_t STRPs[16]; /* current maximum: ibex peak */ + struct { /* ich8 */ + struct { /* STRP1 */ + uint32_t ME_DISABLE :1; + uint32_t :6; + uint32_t TCOMODE :1; + uint32_t ASD :7; + uint32_t BMCMODE :1; + uint32_t :3; + uint32_t GLAN_PCIE_SEL :1; + uint32_t GPIO12_SEL :2; + uint32_t SPICS1_LANPHYPC_SEL :1; + uint32_t MESM2SEL :1; + uint32_t :1; + uint32_t ASD2 :7; + }; + } ich8; + struct { /* ibex peak */ + struct { /* STRP0 */ + uint32_t :1; + uint32_t cs_ss2 :1; + uint32_t :5; + uint32_t SMB_EN :1; + uint32_t SML0_EN :1; + uint32_t SML1_EN :1; + uint32_t SML1FRQ :2; + uint32_t SMB0FRQ :2; + uint32_t SML0FRQ :2; + uint32_t :4; + uint32_t LANPHYPC_GP12_SEL :1; + uint32_t cs_ss1 :1; + uint32_t :2; + uint32_t DMI_REQID_DIS :1; + uint32_t :4; + uint32_t BBBS :2; + uint32_t :1; + }; + struct { /* STRP1 */ + uint32_t cs_ss3 :4; + uint32_t :28; + }; + struct { /* STRP2 */ + uint32_t :8; + uint32_t MESMASDEN :1; + uint32_t MESMASDA :7; + uint32_t :8; + uint32_t MESMI2CEN :1; + uint32_t MESMI2CA :7; + }; + struct { /* STRP3 */ + uint32_t :32; + }; + struct { /* STRP4 */ + uint32_t PHYCON :2; + uint32_t :6; + uint32_t GBEMAC_SMBUS_ADDR_EN :1; + uint32_t GBEMAC_SMBUS_ADDR :7; + uint32_t :1; + uint32_t GBEPHY_SMBUS_ADDR :7; + uint32_t :8; + }; + struct { /* STRP5 */ + uint32_t :32; + }; + struct { /* STRP6 */ + uint32_t :32; + }; + struct { /* STRP7 */ + uint32_t MESMA2UDID_VENDOR :16; + uint32_t MESMA2UDID_DEVICE :16; + }; + struct { /* STRP8 */ + uint32_t :32; + }; + struct { /* STRP9 */ + uint32_t PCIEPCS1 :2; + uint32_t PCIEPCS2 :2; + uint32_t PCIELR1 :1; + uint32_t PCIELR2 :1; + uint32_t DMILR :1; + uint32_t :1; + uint32_t PHY_PCIEPORTSEL :3; + uint32_t PHY_PCIE_EN :1; + uint32_t :20; + }; + struct { /* STRP10 */ + uint32_t :1; + uint32_t ME_BOOT_FLASH :1; + uint32_t cs_ss5 :1; + uint32_t VE_EN :1; + uint32_t :4; + uint32_t MMDDE :1; + uint32_t MMADDR :7; + uint32_t cs_ss7 :1; + uint32_t :1; + uint32_t ICC_SEL :3; + uint32_t MER_CL1 :1; + uint32_t :10; + }; + struct { /* STRP11 */ + uint32_t SML1GPAEN :1; + uint32_t SML1GPA :7; + uint32_t :10; + uint32_t SML1I2CAEN :1; + uint32_t SML1I2CA :7; + }; + struct { /* STRP12 */ + uint32_t :32; + }; + struct { /* STRP13 */ + uint32_t :32; + }; + struct { /* STRP14 */ + uint32_t :8; + uint32_t VE_EN2 :1; + uint32_t :5; + uint32_t VE_BOOT_FLASH :1; + uint32_t :1; + uint32_t BW_SSD :1; + uint32_t NVMHCI_EN :1; + uint32_t :14; + }; + struct { /* STRP15 */ + uint32_t :3; + uint32_t cs_ss6 :2; + uint32_t :1; + uint32_t IWL_EN :1; + uint32_t :1; + uint32_t t209min :2; + uint32_t :22; + }; + }ibex; + }; +}; + +struct flash_upper_map { + union { + uint32_t FLUMAP1; + struct { + uint32_t VTBA :8; + uint32_t VTL :8; + uint32_t :16; + }; + }; + struct { + union { + uint32_t JID; + struct { + uint32_t vid :8; + uint32_t cid0 :8; + uint32_t cid1 :8; + uint32_t :8; + }; + }; + union { + uint32_t VSCC; + struct { + uint32_t ubes :2; + uint32_t uwg :1; + uint32_t uwsr :1; + uint32_t uwews :1; + uint32_t :3; + uint32_t ueo :8; + uint32_t lbes :2; + uint32_t lwg :1; + uint32_t lwsr :1; + uint32_t lwews :1; + uint32_t :3; + uint32_t leo :16; + }; + }; + } vscc_table[128]; +}; +#endif // ICH_DESCRIPTORS_FROM_DUMP + struct flash_descriptors { struct flash_content content; struct flash_component component; struct flash_region region; struct flash_master master; +#ifdef ICH_DESCRIPTORS_FROM_DUMP + struct flash_north_strap north; + struct flash_south_strap south; + struct flash_upper_map upper; +#endif // ICH_DESCRIPTORS_FROM_DUMP }; void prettyprint_ich_descriptors(enum chipset, const struct flash_descriptors *desc); @@ -258,7 +459,16 @@ void prettyprint_ich_descriptor_component(const struct flash_descriptors *desc); void prettyprint_ich_descriptor_region(const struct flash_region *region); void prettyprint_ich_descriptor_master(const struct flash_master *master); +#ifdef ICH_DESCRIPTORS_FROM_DUMP + +void prettyprint_ich_descriptor_upper_map(const struct flash_upper_map *umap); +void prettyprint_ich_descriptor_straps(enum chipset cs, const struct flash_descriptors *desc); +int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, enum chipset cs, struct flash_descriptors *desc); + +#else // ICH_DESCRIPTORS_FROM_DUMP + void read_ich_descriptors_via_fdo(void *spibar, struct flash_descriptors *desc); +#endif // ICH_DESCRIPTORS_FROM_DUMP #endif // __ICH_DESCRIPTORS_H__ #endif // defined(__i386__) || defined(__x86_64__) diff --git a/util/ich_descriptors_tool/Makefile b/util/ich_descriptors_tool/Makefile new file mode 100644 index 0000000..0d79c6b --- /dev/null +++ b/util/ich_descriptors_tool/Makefile @@ -0,0 +1,42 @@ +CC ?= gcc + +PROGRAM=ich_descriptors_tool +EXTRAINCDIRS = ../../ . +DEPPATH = .dep +OBJATH = .obj +SHAREDSRC = ich_descriptors.c +SHAREDSRCDIR = ../.. + +SRC = $(wildcard *.c) + +CFLAGS=-Wall +CFLAGS += -MMD -MP -MF $(DEPPATH)/$((a)F).d +# enables functions that populate the descriptor structs from plain binary dumps +CFLAGS += -D ICH_DESCRIPTORS_FROM_DUMP +CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) + +OBJ = $(OBJATH)/$(SRC:%.c=%.o) + +SHAREDOBJ = $(OBJATH)/$(notdir $(SHAREDSRC:%.c=%.o)) + +all:$(PROGRAM) + +$(OBJ): $(OBJATH)/%.o : %.c + $(CC) $(CFLAGS) -o $@ -c $< + +# this enables us to share source files without simultaneously sharing .o files +# with flashrom, which would lead to unexpected results (w/o running make clean) +$(SHAREDOBJ): $(OBJATH)/%.o : $(SHAREDSRCDIR)/%.c + $(CC) $(CFLAGS) -o $@ -c $< + +$(PROGRAM): $(OBJ) $(SHAREDOBJ) + $(CC) -o $(PROGRAM) $(OBJ) $(SHAREDOBJ) + +clean: + rm -f $(PROGRAM) + rm -rf $(DEPPATH) $(OBJATH) + +# Include the dependency files. +-include $(shell mkdir -p $(DEPPATH) $(OBJATH) 2>/dev/null) $(wildcard $(DEPPATH)/*) + +.PHONY: all clean diff --git a/util/ich_descriptors_tool/TODO b/util/ich_descriptors_tool/TODO new file mode 100644 index 0000000..03701bf --- /dev/null +++ b/util/ich_descriptors_tool/TODO @@ -0,0 +1,6 @@ +- reverse the path, as in assemble a descriptormode image from various + blobs (BIOS, GbE, ME, OEM) and a description (xml? custom config? + sane defaults and cmd-line switches?) +- dump 256 OEM bytes +- handle descriptors of various chipsets correctly +- little endian only diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c new file mode 100644 index 0000000..10f14fb --- /dev/null +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -0,0 +1,225 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (C) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * dump information and binaries from BIOS images that are in descriptor mode + */ +#include <stdio.h> +#include <stdint.h> +#include <stdlib.h> +#include <sys/mman.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <fcntl.h> +#include <unistd.h> +#include <string.h> +#include <errno.h> +#include "ich_descriptors.h" + +static void dump_file(const char *basename, const uint32_t *dump, unsigned int len, struct flash_region *reg, unsigned int i) +{ + int ret; + char *fn; + const char *reg_name; + uint32_t file_len; + const char *const region_names[5] = { + "Descriptor", "BIOS", "ME", "GbE", "Platform" + }; + uint32_t base = ICH_FREG_BASE(reg->FLREGs[i]); + uint32_t limit = ICH_FREG_LIMIT(reg->FLREGs[i]); + + reg_name = region_names[i]; + if (base > limit) { + printf("The %s region is unused and thus not dumped.\n", + reg_name); + return; + } + + limit = limit | 0x0fff; + file_len = limit + 1 - base; + if (base + file_len > len) { + printf("The %s region is spanning 0x%08x-0x%08x, but it is " + "not (fully) included in the image (0-0x%08x), thus not " + "dumped.\n", reg_name, base, limit, len - 1); + return; + } + + fn = malloc(strlen(basename) + strlen(reg_name) + strlen(".bin") + 2); + if (!fn) { + fprintf(stderr, "Out of memory!\n"); + exit(1); + } + snprintf(fn, strlen(basename) + strlen(reg_name) + strlen(".bin") + 2, + "%s.%s.bin", basename, reg_name); + printf("Dumping %u bytes of the %s region from 0x%08x-0x%08x to %s... ", + file_len, region_names[i], base, limit, fn); + int fh = open(fn, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); + free(fn); + if (fh < 0) { + fprintf(stderr, + "ERROR: couldn't open(%s): %s\n", fn, strerror(errno)); + exit(1); + } + + ret = write(fh, &dump[base >> 2], file_len); + if (ret != file_len) { + fprintf(stderr, "FAILED.\n"); + exit(1); + } + + printf("done.\n"); + close(fh); +} + +void dump_files(const char *n, const uint32_t *buf, unsigned int len, struct flash_region *reg) +{ + unsigned int i; + printf("=== Dumping region files ===\n"); + for (i = 0; i < 5; i++) + dump_file(n, buf, len, reg, i); + printf("\n"); +} + +static void usage(char *argv[], char *error) +{ + if (error != NULL) { + fprintf(stderr, "%s\n", error); + } + printf("usage: '%s -f <image file name> [-c <chipset name>] [-d]'\n\n" +"where <image file name> points to an image of the contents of the SPI flash.\n" +"In case that image is really in descriptor mode %s\n" +"will pretty print some of the contained information.\n" +"To also print the data stored in the descriptor strap you have to indicate\n" +"the chipset series with the '-c' parameter and one of the possible arguments:\n" +"\t- \"ich8\",\n" +"\t- \"ich9\",\n" +"\t- \"ich10\",\n" +"\t- \"5\" or \"ibex\" for Intel's 5 series chipsets,\n" +"\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n" +"\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n" +"If '-d' is specified some regions such as the BIOS image as seen by the CPU or\n" +"the GbE blob that is required to initialize the GbE are also dumped to files.\n", + argv[0], argv[0]); + exit(1); +} + +int main(int argc, char *argv[]) +{ + int fd; /* file descriptor to flash file */ + unsigned int len; /* file/buffer size in bytes */ + uint32_t *buf; /* mmap'd file */ + + int opt; + int ret; + int dump = 0; + const char *fn = NULL; + const char *csn = NULL; + enum chipset cs = CHIPSET_UNKNOWN; + struct flash_descriptors desc = {{ 0 }}; + + while ((opt = getopt(argc, argv, "df:c:")) != -1) { + switch (opt) { + case 'd': + dump = 1; + break; + case 'f': + fn = optarg; + break; + case 'c': + csn = optarg; + break; + default: /* '?' */ + usage(argv, NULL); + } + } + if (fn == NULL) + usage(argv, + "Need a file name of a descriptor image to read from."); + + fd = open(fn, O_RDONLY); + if (fd < 0) + usage(argv, "No such file"); + len = lseek(fd, 0, SEEK_END); + if (len < 0) + usage(argv, "Seeking to the end of the file failed"); + + buf = mmap(NULL, len, PROT_READ, MAP_PRIVATE, fd, 0); + if (buf == (void *) -1) { + /* fallback for stupid OSes like cygwin */ + int ret; + buf = malloc(len); + if (!buf) + usage(argv, "Could not allocate memory"); + lseek(fd, 0, SEEK_SET); + ret = read(fd, buf, len); + if (ret != len) + usage(argv, "Seeking to the end of the file failed"); + } + printf("The flash image has a size of %d [0x%x] bytes.\n", len, len); + close(fd); + + if (csn != NULL) { + if (strcmp(csn, "ich8") == 0) + cs = CHIPSET_ICH8; + else if (strcmp(csn, "ich9") == 0) + cs = CHIPSET_ICH9; + else if (strcmp(csn, "ich10") == 0) + cs = CHIPSET_ICH10; + else if ((strcmp(csn, "5") == 0) || + (strcmp(csn, "ibex") == 0)) + cs = CHIPSET_5_SERIES_IBEX_PEAK; + else if ((strcmp(csn, "6") == 0) || + (strcmp(csn, "cougar") == 0)) + cs = CHIPSET_6_SERIES_COUGAR_POINT; + else if ((strcmp(csn, "7") == 0) || + (strcmp(csn, "panther") == 0)) + cs = CHIPSET_7_SERIES_PANTHER_POINT; + } + + ret = read_ich_descriptors_from_dump(buf, len, cs, &desc); + switch (ret) { + case RET_OK: + break; + case RET_ERR: + printf("Image not in descriptor mode.\n"); + exit(1); + case RET_OOB: + printf("Tried to access a location out of bounds of the image. " + "- Corrupt image?\n"); + exit(1); + default: + printf("Unhandled return value at %s:%u, please report this.\n", + __FILE__, __LINE__); + exit(1); + } + + prettyprint_ich_descriptors(cs, &desc); + + //uint8_t *pMAC = (uint8_t *) &buf[r->reg3_base >> 2]; + //printf("The MAC-address might be: %02x:%02x:%02x:%02x:%02x:%02x\n", + //pMAC[0], pMAC[1], pMAC[2], pMAC[3], pMAC[4], pMAC[5]); + + if (dump == 1) + dump_files(fn, buf, len, &desc.region); + + return 0; +} + -- 1.7.1

1 0

[PATCH 2/4] add ICH/PCH flash descriptor decoding via FDOC/FDOD
by Stefan Tauner 20 Jul '11

20 Jul '11

based on the work of Matthias 'mazzoo' Wenzel this patch adds pretty printing of those ICH/PCH flash descriptors that are cached/mapped by the chipset (and which are therefore reachable via FDOC/FDOD registers). this includes the following: - content descriptor: describes the image and some generic properties (number of regions, offset of regions, PCH/ICH and MCH/PROC strap offsets and lengths) - component descriptor: identify the different SPI Flash Components and their capabilities. - region descriptor similarly to a partition table this describes the different regions - master descriptor defines access rights of the individual regions this is only a part of the data included in the descriptor. other information can be retreived from a complete binary dump of the descriptor image only. this patch also adds macros and pretty printing for "Vendor Specific Component Capabilities" registers: there are two of them: lower and upper. they describe the properties of the address space divided by FPBA (which allows to use multiple flash chips or partitions with different properties). the properties of flash chips supported by the ME are stored in the same format in a descriptor table. a later patch will uses them outside of ichspi.c which is also the reason why the prettyprinting function and the register bit macros are not defined in ichspi.c but ich_descriptors.h. TODO: - file naming and partitioning was not discussed. we may want a ichspi.h. and/or rename ichspi.c to ich_spi.c or similar... - straps of ich8 (only) could be printed at runtime via FDOC/FDOD. worth it? no, imo. but reading out the descriptor region manually and parsing it with the following patch may be useful? Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- Makefile | 3 +- ich_descriptors.c | 247 +++++++++++++++++++++++++++++++++++++++++++++++++ ich_descriptors.h | 264 +++++++++++++++++++++++++++++++++++++++++++++++++++++ ichspi.c | 39 ++++++-- 4 files changed, 544 insertions(+), 9 deletions(-) create mode 100644 ich_descriptors.c create mode 100644 ich_descriptors.h diff --git a/Makefile b/Makefile index a35df06..7f73452 100644 --- a/Makefile +++ b/Makefile @@ -308,7 +308,8 @@ ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o ifeq ($(ARCH),"x86") -PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += it87spi.o it85spi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += ichspi.o ich_descriptors.o else endif NEED_PCI := yes diff --git a/ich_descriptors.c b/ich_descriptors.c new file mode 100644 index 0000000..cf77601 --- /dev/null +++ b/ich_descriptors.c @@ -0,0 +1,247 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (c) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if defined(__i386__) || defined(__x86_64__) + +#include "ich_descriptors.h" +#include "flash.h" /* for msg_* */ + +#define getFCBA(cont) (((cont)->FLMAP0 << 4) & 0x00000ff0) +#define getFRBA(cont) (((cont)->FLMAP0 >> 12) & 0x00000ff0) +#define getFMBA(cont) (((cont)->FLMAP1 << 4) & 0x00000ff0) +#define getFISBA(cont) (((cont)->FLMAP1 >> 12) & 0x00000ff0) +#define getFMSBA(cont) (((cont)->FLMAP2 << 4) & 0x00000ff0) + +void prettyprint_ich_descriptors(enum chipset cs, const struct flash_descriptors *desc) +{ + prettyprint_ich_descriptor_content(&desc->content); + prettyprint_ich_descriptor_component(desc); + prettyprint_ich_descriptor_region(&desc->region); + prettyprint_ich_descriptor_master(&desc->master); +} + +void prettyprint_ich_descriptor_content(const struct flash_content *cont) +{ + msg_pdbg1("=== Content Section ===\n"); + msg_pdbg1("FLVALSIG 0x%08x\n", cont->FLVALSIG); + msg_pdbg1("FLMAP0 0x%08x\n", cont->FLMAP0); + msg_pdbg1("FLMAP1 0x%08x\n", cont->FLMAP1); + msg_pdbg1("FLMAP2 0x%08x\n", cont->FLMAP2); + msg_pdbg1("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2("NR (Number of Regions): %5d\n", + cont->NR + 1); + msg_pdbg2("FRBA (Flash Region Base Address): 0x%03x\n", + getFRBA(cont)); + msg_pdbg2("NC (Number of Components): %5d\n", + cont->NC + 1); + msg_pdbg2("FCBA (Flash Component Base Address): 0x%03x\n", + getFCBA(cont)); + msg_pdbg2("ISL (ICH/PCH Strap Length): %5d\n", + cont->ISL); + msg_pdbg2("FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x%03x\n", + getFISBA(cont)); + msg_pdbg2("NM (Number of Masters): %5d\n", + cont->NM + 1); + msg_pdbg2("FMBA (Flash Master Base Address): 0x%03x\n", + getFMBA(cont)); + msg_pdbg2("MSL/PSL (MCH/PROC Strap Length): %5d\n", + cont->MSL); + msg_pdbg2("FMSBA (Flash MCH/PROC Strap Base Address): 0x%03x\n", + getFMSBA(cont)); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_component(const struct flash_descriptors *desc) +{ + const char * const str_freq[8] = { + "20 MHz", /* 000 */ + "33 MHz", /* 001 */ + "reserved", /* 010 */ + "reserved", /* 011 */ + "50 MHz", /* 100 */ + "reserved", /* 101 */ + "reserved", /* 110 */ + "reserved" /* 111 */ + }; + const char * const str_mem[8] = { + "512 kB", /* 000 */ + " 1 MB", /* 001 */ + " 2 MB", /* 010 */ + " 4 MB", /* 011 */ + " 8 MB", /* 100 */ + " 16 MB", /* 101 */ + "reserved", /* 110 */ + "reserved", /* 111 */ + }; + + msg_pdbg1("=== Component Section ===\n"); + msg_pdbg1("FLCOMP 0x%08x\n", desc->component.FLCOMP); + msg_pdbg1("FLILL 0x%08x\n", desc->component.FLILL ); + msg_pdbg1("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2("Component 1 density: %s\n", + str_mem[desc->component.comp1_density]); + if (desc->content.NC) + msg_pdbg2("Component 2 density: %s\n", + str_mem[desc->component.comp2_density]); + else + msg_pdbg2("Component 2 is not used.\n"); + msg_pdbg2("Read Clock Frequency: %s\n", + str_freq[desc->component.freq_read]); + msg_pdbg2("Read ID and Status Clock Freq.: %s\n", + str_freq[desc->component.freq_read_id]); + msg_pdbg2("Write and Erase Clock Freq.: %s\n", + str_freq[desc->component.freq_write]); + msg_pdbg2("Fast Read is %ssupported.\n", + desc->component.fastread ? "" : "not "); + if (desc->component.fastread) + msg_pdbg2("Fast Read Clock Frequency: %s\n", + str_freq[desc->component.freq_fastread]); + if (desc->component.FLILL == 0) + msg_pdbg2("No forbidden opcodes.\n"); + else { + msg_pdbg2("Invalid instruction 0: 0x%02x\n", + desc->component.invalid_instr0); + msg_pdbg2("Invalid instruction 1: 0x%02x\n", + desc->component.invalid_instr1); + msg_pdbg2("Invalid instruction 2: 0x%02x\n", + desc->component.invalid_instr2); + msg_pdbg2("Invalid instruction 3: 0x%02x\n", + desc->component.invalid_instr3); + } + msg_pdbg2("\n"); +} + +static void pprint_freg(const struct flash_region *reg, uint32_t i) +{ + const char *const region_names[5] = { + "Descr.", "BIOS", "ME", "GbE", "Platf." + }; + uint32_t base = ICH_FREG_BASE(reg->FLREGs[i]); + uint32_t limit = ICH_FREG_LIMIT(reg->FLREGs[i]); + msg_pdbg2("Region %d (%-6s) ", i, region_names[i]); + if (base > limit) + msg_pdbg2("is unused.\n"); + else + msg_pdbg2("0x%08x - 0x%08x\n", base, limit | 0x0fff); +} + +void prettyprint_ich_descriptor_region(const struct flash_region *reg) +{ + uint8_t i; + msg_pdbg1("=== Region Section ===\n"); + for (i = 0; i < 5; i++) + msg_pdbg1("FLREG%d 0x%08x\n", i, reg->FLREGs[i]); + msg_pdbg1("\n"); + + msg_pdbg2("--- Details ---\n"); + for (i = 0; i < 5; i++) + pprint_freg(reg, i); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_master(const struct flash_master *mstr) +{ + msg_pdbg1("=== Master Section ===\n"); + msg_pdbg1("FLMSTR1 0x%08x\n", mstr->FLMSTR1); + msg_pdbg1("FLMSTR2 0x%08x\n", mstr->FLMSTR2); + msg_pdbg1("FLMSTR3 0x%08x\n", mstr->FLMSTR3); + msg_pdbg1("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2(" Descr. BIOS ME GbE Platf.\n"); + msg_pdbg2("BIOS %c%c %c%c %c%c %c%c %c%c\n", + (mstr->BIOS_descr_r) ?'r':' ', (mstr->BIOS_descr_w) ?'w':' ', + (mstr->BIOS_BIOS_r) ?'r':' ', (mstr->BIOS_BIOS_w) ?'w':' ', + (mstr->BIOS_ME_r) ?'r':' ', (mstr->BIOS_ME_w) ?'w':' ', + (mstr->BIOS_GbE_r) ?'r':' ', (mstr->BIOS_GbE_w) ?'w':' ', + (mstr->BIOS_plat_r) ?'r':' ', (mstr->BIOS_plat_w) ?'w':' '); + msg_pdbg2("ME %c%c %c%c %c%c %c%c %c%c\n", + (mstr->ME_descr_r) ?'r':' ', (mstr->ME_descr_w) ?'w':' ', + (mstr->ME_BIOS_r) ?'r':' ', (mstr->ME_BIOS_w) ?'w':' ', + (mstr->ME_ME_r) ?'r':' ', (mstr->ME_ME_w) ?'w':' ', + (mstr->ME_GbE_r) ?'r':' ', (mstr->ME_GbE_w) ?'w':' ', + (mstr->ME_plat_r) ?'r':' ', (mstr->ME_plat_w) ?'w':' '); + msg_pdbg2("GbE %c%c %c%c %c%c %c%c %c%c\n", + (mstr->GbE_descr_r) ?'r':' ', (mstr->GbE_descr_w) ?'w':' ', + (mstr->GbE_BIOS_r) ?'r':' ', (mstr->GbE_BIOS_w) ?'w':' ', + (mstr->GbE_ME_r) ?'r':' ', (mstr->GbE_ME_w) ?'w':' ', + (mstr->GbE_GbE_r) ?'r':' ', (mstr->GbE_GbE_w) ?'w':' ', + (mstr->GbE_plat_r) ?'r':' ', (mstr->GbE_plat_w) ?'w':' '); + msg_pdbg2("\n"); +} + +void prettyprint_ich9_reg_vscc(uint32_t reg_val) +{ + pprint_reg_hex(VSCC, BES, reg_val, ", "); + pprint_reg(VSCC, WG, reg_val, ", "); + pprint_reg(VSCC, WSR, reg_val, ", "); + pprint_reg(VSCC, WEWS, reg_val, ", "); + pprint_reg_hex(VSCC, EO, reg_val, ", "); + pprint_reg(VSCC, VCL, reg_val, "\n"); +} + +static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) +{ + uint32_t control = 0; + control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS; + control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI; + *(volatile uint32_t *) (spibar + ICH9_REG_FDOC) = control; + return *(volatile uint32_t *)(spibar + ICH9_REG_FDOD); +} + +void read_ich_descriptors_via_fdo(void *spibar, struct flash_descriptors *desc) +{ + msg_pdbg1("Reading flash descriptors " + "mapped by the chipset via FDOC/FDOD..."); + /* content section */ + desc->content.FLVALSIG = read_descriptor_reg(0, 0, spibar); + desc->content.FLMAP0 = read_descriptor_reg(0, 1, spibar); + desc->content.FLMAP1 = read_descriptor_reg(0, 2, spibar); + desc->content.FLMAP2 = read_descriptor_reg(0, 3, spibar); + + /* component section */ + desc->component.FLCOMP = read_descriptor_reg(1, 0, spibar); + desc->component.FLILL = read_descriptor_reg(1, 1, spibar); + desc->component.FLPB = read_descriptor_reg(1, 2, spibar); + + /* region section */ + desc->region.FLREGs[0] = read_descriptor_reg(2, 0, spibar); + desc->region.FLREGs[1] = read_descriptor_reg(2, 1, spibar); + desc->region.FLREGs[2] = read_descriptor_reg(2, 2, spibar); + desc->region.FLREGs[3] = read_descriptor_reg(2, 3, spibar); + desc->region.FLREGs[4] = read_descriptor_reg(2, 4, spibar); + + /* master section */ + desc->master.FLMSTR1 = read_descriptor_reg(3, 0, spibar); + desc->master.FLMSTR2 = read_descriptor_reg(3, 1, spibar); + desc->master.FLMSTR3 = read_descriptor_reg(3, 2, spibar); + + /* Accessing the strap section via FDOC/D is only possible on ICH8 and + * reading the upper map is impossible on all chipsets, so don't bother. + */ + + msg_pdbg1(" done\n"); +} +#endif // defined(__i386__) || defined(__x86_64__) diff --git a/ich_descriptors.h b/ich_descriptors.h new file mode 100644 index 0000000..f248394 --- /dev/null +++ b/ich_descriptors.h @@ -0,0 +1,264 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (c) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if defined(__i386__) || defined(__x86_64__) +#ifndef __ICH_DESCRIPTORS_H__ +#define __ICH_DESCRIPTORS_H__ 1 + +#include <stdint.h> + +/* most of the following should probably be in a new file named ichspi.h */ +#define msg_pdbg1 msg_pdbg +#define msg_pdbg2 msg_pspew + +#define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */ + /* 0-1: reserved */ +#define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */ +#define FDOC_FDSI (0x3f << FDOC_FDSI_OFF) +#define FDOC_FDSS_OFF 12 /* 12-14: Flash Descriptor Section Select */ +#define FDOC_FDSS (0x3 << FDOC_FDSS_OFF) + /* 15-31: reserved */ + +#define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */ + +/* Field locations and semantics for LVSCC, UVSCC and related words in the flash + * descriptor are equal therefore they all share the same macros below. */ +#define VSCC_BES_OFF 0 /* 0-1: Block/Sector Erase Size */ +#define VSCC_BES (0x3 << VSCC_BES_OFF) +#define VSCC_WG_OFF 2 /* 2: Write Granularity */ +#define VSCC_WG (0x1 << VSCC_WG_OFF) +#define VSCC_WSR_OFF 3 /* 3: Write Status Required */ +#define VSCC_WSR (0x1 << VSCC_WSR_OFF) +#define VSCC_WEWS_OFF 4 /* 4: Write Enable on Write Status */ +#define VSCC_WEWS (0x1 << VSCC_WEWS_OFF) + /* 5-7: reserved */ +#define VSCC_EO_OFF 8 /* 8-15: Erase Opcode */ +#define VSCC_EO (0xff << VSCC_EO_OFF) + /* 16-22: reserved */ +#define VSCC_VCL_OFF 23 /* 23: Vendor Component Lock */ +#define VSCC_VCL (0x1 << VSCC_VCL_OFF) + /* 24-31: reserved */ + +#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) +#define pprint_reg_hex(reg, bit, val, sep) msg_pdbg("%s=0x%x" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) +void prettyprint_ich9_reg_vscc(uint32_t reg_val); + +#define ICH_FREG_BASE(flreg) ((flreg << 12) & 0x01fff000) +#define ICH_FREG_LIMIT(flreg) ((flreg >> 4) & 0x01fff000) + +/* Used to select the right descriptor printing function. + * Currently only ICH8 and Ibex Peak are supported. + */ +enum chipset { + CHIPSET_UNKNOWN, + CHIPSET_ICH7 = 7, + CHIPSET_ICH8, + CHIPSET_ICH9, + CHIPSET_ICH10, + CHIPSET_5_SERIES_IBEX_PEAK, + CHIPSET_6_SERIES_COUGAR_POINT, + CHIPSET_7_SERIES_PANTHER_POINT +}; + +struct flash_content { + uint32_t FLVALSIG; /* 0x00 */ + union { /* 0x04 */ + uint32_t FLMAP0; + struct { + uint32_t FCBA :8; + uint32_t NC :2; + uint32_t :6; + uint32_t FRBA :8; + uint32_t NR :3; + uint32_t :5; + }; + }; + union { /* 0x08 */ + uint32_t FLMAP1; + struct { + uint32_t FMBA :8; + uint32_t NM :3; + uint32_t :5; + uint32_t FISBA :8; + uint32_t ISL :8; + }; + }; + union { /* 0x0c */ + uint32_t FLMAP2; + struct { + uint32_t FMSBA :8; + uint32_t MSL :8; + uint32_t :16; + }; + }; +}; + +struct flash_component { + union { /* 0x00 */ + uint32_t FLCOMP; + struct { + uint32_t comp1_density :3; + uint32_t comp2_density :3; + uint32_t :11; + uint32_t freq_read :3; + uint32_t fastread :1; + uint32_t freq_fastread :3; + uint32_t freq_write :3; + uint32_t freq_read_id :3; + uint32_t :2; + }; + }; + union { /* 0x04 */ + uint32_t FLILL; + struct { + uint32_t invalid_instr0; + uint32_t invalid_instr1; + uint32_t invalid_instr2; + uint32_t invalid_instr3; + }; + }; + union { /* 0x08 */ + uint32_t FLPB; + struct { + uint32_t FPBA :13; + uint32_t :19; + }; + }; +}; + +struct flash_region { + union { + uint32_t FLREGs[5]; + struct { + /* FLREG0 Flash Descriptor */ + struct { + uint32_t reg0_base :13; + uint32_t :3; + uint32_t reg0_limit :13; + uint32_t :3; + }; + /* FLREG1 BIOS */ + struct { + uint32_t reg1_base :13; + uint32_t :3; + uint32_t reg1_limit :13; + uint32_t :3; + }; + /* FLREG2 ME */ + struct { + uint32_t reg2_base :13; + uint32_t :3; + uint32_t reg2_limit :13; + uint32_t :3; + }; + /* FLREG3 GbE */ + struct { + uint32_t reg3_base :13; + uint32_t :3; + uint32_t reg3_limit :13; + uint32_t :3; + }; + /* FLREG4 Platform */ + struct { + uint32_t reg4_base :13; + uint32_t :3; + uint32_t reg4_limit :13; + uint32_t :3; + }; + }; + }; +}; + +struct flash_master { + union { + uint32_t FLMSTR1; + struct { + uint32_t BIOS_req_ID :16; + uint32_t BIOS_descr_r :1; + uint32_t BIOS_BIOS_r :1; + uint32_t BIOS_ME_r :1; + uint32_t BIOS_GbE_r :1; + uint32_t BIOS_plat_r :1; + uint32_t :3; + uint32_t BIOS_descr_w :1; + uint32_t BIOS_BIOS_w :1; + uint32_t BIOS_ME_w :1; + uint32_t BIOS_GbE_w :1; + uint32_t BIOS_plat_w :1; + uint32_t :3; + }; + }; + union { + uint32_t FLMSTR2; + struct { + uint32_t ME_req_ID :16; + uint32_t ME_descr_r :1; + uint32_t ME_BIOS_r :1; + uint32_t ME_ME_r :1; + uint32_t ME_GbE_r :1; + uint32_t ME_plat_r :1; + uint32_t :3; + uint32_t ME_descr_w :1; + uint32_t ME_BIOS_w :1; + uint32_t ME_ME_w :1; + uint32_t ME_GbE_w :1; + uint32_t ME_plat_w :1; + uint32_t :3; + }; + }; + union { + uint32_t FLMSTR3; + struct { + uint32_t GbE_req_ID :16; + uint32_t GbE_descr_r :1; + uint32_t GbE_BIOS_r :1; + uint32_t GbE_ME_r :1; + uint32_t GbE_GbE_r :1; + uint32_t GbE_plat_r :1; + uint32_t :3; + uint32_t GbE_descr_w :1; + uint32_t GbE_BIOS_w :1; + uint32_t GbE_ME_w :1; + uint32_t GbE_GbE_w :1; + uint32_t GbE_plat_w :1; + uint32_t :3; + }; + }; +}; + +struct flash_descriptors { + struct flash_content content; + struct flash_component component; + struct flash_region region; + struct flash_master master; +}; + +void prettyprint_ich_descriptors(enum chipset, const struct flash_descriptors *desc); + +void prettyprint_ich_descriptor_content(const struct flash_content *content); +void prettyprint_ich_descriptor_component(const struct flash_descriptors *desc); +void prettyprint_ich_descriptor_region(const struct flash_region *region); +void prettyprint_ich_descriptor_master(const struct flash_master *master); + +void read_ich_descriptors_via_fdo(void *spibar, struct flash_descriptors *desc); + +#endif // __ICH_DESCRIPTORS_H__ +#endif // defined(__i386__) || defined(__x86_64__) diff --git a/ichspi.c b/ichspi.c index 2480fa5..b5ee23a 100644 --- a/ichspi.c +++ b/ichspi.c @@ -30,6 +30,7 @@ #include "chipdrivers.h" #include "programmer.h" #include "spi.h" +#include "ich_descriptors.h" /* ICH9 controller register definition */ #define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ @@ -120,6 +121,14 @@ #define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */ #define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */ +#define ICH9_REG_LVSCC 0xC4 /* 32 Bits Host Lower Vendor Specific Component Capabilities */ +#define ICH9_REG_UVSCC 0xC8 /* 32 Bits Host Upper Vendor Specific Component Capabilities */ +/* The individual fields of the VSCC registers are defined in the file + * ich_descriptors.h. The reason is that the same fields are also used in the + * flash descriptors to define the properties of the different flash chips + * supported by the BIOS image. These descriptors are also the source for the + * registers above. */ + #define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */ #define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */ #define FPB_FPBA (0x1FFF << FPB_FPBA_OFF) @@ -302,8 +311,6 @@ static void prettyprint_opcodes(OPCODES *ops) } } -#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) - static void prettyprint_ich9_reg_hsfs(uint16_t reg_val) { msg_pdbg("HSFS: "); @@ -1130,9 +1137,6 @@ static int ich_spi_send_multicommand(struct spi_command *cmds) #define ICH_BRWA(x) ((x >> 8) & 0xff) #define ICH_BRRA(x) ((x >> 0) & 0xff) -#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff) -#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff) - static void do_ich9_spi_frap(uint32_t frap, int i) { static const char *const access_names[4] = { @@ -1159,9 +1163,8 @@ static void do_ich9_spi_frap(uint32_t frap, int i) return; } - msg_pdbg("0x%08x-0x%08x is %s\n", - (base << 12), (limit << 12) | 0x0fff, - access_names[rwperms]); + msg_pdbg("0x%08x-0x%08x is %s\n", base, (limit | 0x0fff), + access_names[rwperms]); } static const struct spi_programmer spi_programmer_ich7 = { @@ -1191,6 +1194,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, uint8_t old, new; uint16_t spibar_offset, tmp2; uint32_t tmp; + int ichspi_desc = 0; switch (ich_generation) { case 7: @@ -1262,6 +1266,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } + if (tmp2 & HSFS_FDV) + ichspi_desc = 1; tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); @@ -1312,9 +1318,26 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); msg_pdbg("0xA0: 0x%08x (BBAR)\n", ichspi_bbar); + + tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); + msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); + msg_pdbg("LVSCC: "); + prettyprint_ich9_reg_vscc(tmp); + + tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); + msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); + msg_pdbg("UVSCC: "); + prettyprint_ich9_reg_vscc(tmp); + tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + msg_pdbg("\n"); + if (ichspi_desc) { + struct flash_descriptors desc = {{ 0 }}; + read_ich_descriptors_via_fdo(ich_spibar, &desc); + prettyprint_ich_descriptors(CHIPSET_UNKNOWN, &desc); + } ich_init_opcodes(); break; default: -- 1.7.1

1 0

[PATCH 1/4] ichspi.c: refactor filling and reading the fdata/spid registers
by Stefan Tauner 20 Jul '11

20 Jul '11

- add ich_fill_data to fill the chipset registers from an array - add ich_read_data to copy the data from the chipset register into an array - replace the existing code with calls to those functions - minor cosmetic changes Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> --- ichspi.c | 135 ++++++++++++++++++++++++++------------------------------------ 1 files changed, 57 insertions(+), 78 deletions(-) diff --git a/ichspi.c b/ichspi.c index 99c4613..2480fa5 100644 --- a/ichspi.c +++ b/ichspi.c @@ -6,6 +6,7 @@ * Copyright (C) 2008 Dominik Geyer <dominik.geyer(a)kontron.com> * Copyright (C) 2008 coresystems GmbH <info(a)coresystems.de> * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger + * Copyright (C) 2011 Stefan Tauner * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,18 +23,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* - * This module is designed for supporting the devices - * ST M25P40 - * ST M25P80 - * ST M25P16 - * ST M25P32 already tested - * ST M25P64 - * AT 25DF321 already tested - * ... and many more SPI flash devices - * - */ - #if defined(__i386__) || defined(__x86_64__) #include <string.h> @@ -293,7 +282,7 @@ static OPCODE POSSIBLE_OPCODES[] = { static OPCODES O_EXISTING = {}; /* pretty printing functions */ -static void pretty_print_opcodes(OPCODES *ops) +static void prettyprint_opcodes(OPCODES *ops) { if(ops == NULL) return; @@ -592,6 +581,51 @@ static void ich_set_bbar(uint32_t min_addr) msg_perr("Setting BBAR failed!\n"); } +/* Read len bytes from the fdata/spid register into the data array. + * + * Note that using len > spi_programmer->max_data_read will return garbage or + * may even crash. + */ + static void ich_read_data(uint8_t *data, int len, int reg0_off) + { + int i; + uint32_t temp32 = 0; + + for (i = 0; i < len; i++) { + if ((i % 4) == 0) + temp32 = REGREAD32(reg0_off + i); + + data[i] = (temp32 >> ((i % 4) * 8)) & 0xff; + } +} + +/* Fill len bytes from the data array into the fdata/spid registers. + * + * Note that using len > spi_programmer->max_data_write will trash the registers + * following the data registers. + */ +static void ich_fill_data(const uint8_t *data, int len, int reg0_off) +{ + uint32_t temp32 = 0; + int i; + + if (len <= 0) + return; + + for (i = 0; i < len; i++) { + if ((i % 4) == 0) + temp32 = 0; + + temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8); + + if ((i % 4) == 3) /* 32 bits are full, write them to regs. */ + REGWRITE32(reg0_off + (i - (i % 4)), temp32); + } + i--; + if ((i % 4) != 3) /* Write remaining data to regs. */ + REGWRITE32(reg0_off + (i - (i % 4)), temp32); +} + /* This function generates OPCODES from or programs OPCODES to ICH according to * the chipset's SPI configuration lock. * @@ -627,7 +661,7 @@ static int ich_init_opcodes(void) } else { curopcodes = curopcodes_done; msg_pdbg("done\n"); - pretty_print_opcodes(curopcodes); + prettyprint_opcodes(curopcodes); msg_pdbg("\n"); return 0; } @@ -638,9 +672,8 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, { int write_cmd = 0; int timeout; - uint32_t temp32 = 0; + uint32_t temp32; uint16_t temp16; - uint32_t a; uint64_t opmenu; int opcode_index; @@ -664,26 +697,8 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF) | temp32); /* Program data into SPID0 to N */ - if (write_cmd && (datalength != 0)) { - temp32 = 0; - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = 0; - } - - temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8); - - if ((a % 4) == 3) { - REGWRITE32(ICH7_REG_SPID0 + (a - (a % 4)), - temp32); - } - } - if (((a - 1) % 4) != 3) { - REGWRITE32(ICH7_REG_SPID0 + - ((a - 1) - ((a - 1) % 4)), temp32); - } - - } + if (write_cmd && (datalength != 0)) + ich_fill_data(data, datalength, ICH7_REG_SPID0); /* Assemble SPIS */ temp16 = REGREAD16(ICH7_REG_SPIS); @@ -764,17 +779,8 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, return 1; } - if ((!write_cmd) && (datalength != 0)) { - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = REGREAD32(ICH7_REG_SPID0 + (a)); - } - - data[a] = - (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) - >> ((a % 4) * 8); - } - } + if ((!write_cmd) && (datalength != 0)) + ich_read_data(data, datalength, ICH7_REG_SPID0); return 0; } @@ -785,7 +791,6 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, int write_cmd = 0; int timeout; uint32_t temp32; - uint32_t a; uint64_t opmenu; int opcode_index; @@ -810,25 +815,8 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32); /* Program data into FDATA0 to N */ - if (write_cmd && (datalength != 0)) { - temp32 = 0; - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = 0; - } - - temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8); - - if ((a % 4) == 3) { - REGWRITE32(ICH9_REG_FDATA0 + (a - (a % 4)), - temp32); - } - } - if (((a - 1) % 4) != 3) { - REGWRITE32(ICH9_REG_FDATA0 + - ((a - 1) - ((a - 1) % 4)), temp32); - } - } + if (write_cmd && (datalength != 0)) + ich_fill_data(data, datalength, ICH9_REG_FDATA0); /* Assemble SSFS + SSFC */ temp32 = REGREAD32(ICH9_REG_SSFS); @@ -916,17 +904,8 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, return 1; } - if ((!write_cmd) && (datalength != 0)) { - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = REGREAD32(ICH9_REG_FDATA0 + (a)); - } - - data[a] = - (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) - >> ((a % 4) * 8); - } - } + if ((!write_cmd) && (datalength != 0)) + ich_read_data(data, datalength, ICH9_REG_FDATA0); return 0; } -- 1.7.1

1 0

[PATCH 0/4] ichspi 7.2
by Stefan Tauner 20 Jul '11

20 Jul '11

1/4 unchanged, still needs testing. i have worked on 2/4 and 3/4 quite a bit. they check the input from the image data when using it to calculate the offset for read accesses. a few structs were reorganised where i saw fit... a few bugs were squished too in the process. hwseq itself (4/4) has a small change which allows the user to select hwseq, see commit log for details. Stefan Tauner (4): ichspi.c: refactor filling and reading the fdata/spid registers add ICH/PCH flash descriptor decoding via FDOC/FDOD add ich_descriptor_tool to decode all flash descriptors stored in a flash dump file ichspi.c: add support for Intel Hardware Sequencing Makefile | 3 +- chipdrivers.h | 6 + flashchips.c | 23 +- flashchips.h | 2 + ich_descriptors.c | 681 ++++++++++++++++++++++ ich_descriptors.h | 475 +++++++++++++++ ichspi.c | 523 ++++++++++++++--- programmer.h | 1 + util/ich_descriptors_tool/Makefile | 42 ++ util/ich_descriptors_tool/TODO | 6 + util/ich_descriptors_tool/ich_descriptors_tool.c | 225 +++++++ 11 files changed, 1888 insertions(+), 99 deletions(-) create mode 100644 ich_descriptors.c create mode 100644 ich_descriptors.h create mode 100644 util/ich_descriptors_tool/Makefile create mode 100644 util/ich_descriptors_tool/TODO create mode 100644 util/ich_descriptors_tool/ich_descriptors_tool.c

1 0

Re: [flashrom] [PATCH 07/12] add ICH/PCH flash descriptor decoding
by Carl-Daniel Hailfinger 20 Jul '11

20 Jul '11

Am 08.06.2011 04:55 schrieb Stefan Tauner: > based on the work of Matthias 'mazzoo' Wenzel this patch adds... > - pretty printing of those ICH/PCH flash descriptors that are cached/mapped by the chipset > (and which are therefore reachable via FDOC/FDOD registers) and > - a new tool to the util directory that is able to decode all flash descriptors stored in a flash > dump file. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > A slightly more verbose explanation would be nice. That said, I'll comment anyway so you have something to work with. > diff --git a/Makefile b/Makefile > index 6e6e2de..b61031f 100644 > --- a/Makefile > +++ b/Makefile > @@ -223,7 +223,7 @@ ifeq ($(CONFIG_INTERNAL), yes) > FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' > PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o > # FIXME: The PROGRAMMER_OBJS below should only be included on x86. > -PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o > +PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o ich_descriptors.o sb600spi.o wbsio_spi.o mcp6x_spi.o > Maybe break this into multiple lines. > NEED_PCI := yes > endif > > diff --git a/ich_descriptors.c b/ich_descriptors.c > new file mode 100644 > index 0000000..0b03624 > --- /dev/null > +++ b/ich_descriptors.c > @@ -0,0 +1,453 @@ > +/* This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * authors: > + * (c) 2010 Matthias Wenzel <bios at mazzoo dot de> > + * (c) 2011 Stefan Tauner > Please use the same format as in other files, i.e. don't only use "(c)" but also add the word "Copyright". Rumor has it that even the order of "(c)" vs. "Copyright" is important for US law. No idea if that is true, but it can't hurt to do the same as everyone else. > + */ > + > +#include "ich_descriptors.h" > + > +#if defined(__i386__) || defined(__x86_64__) > + > +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP > + > +#define DESCRIPTOR_MODE_MAGIC 0x0ff0a55a > +#define msg_pdbg printf > +#include <stdio.h> > + > +struct flash_strap fisba; > +struct flash_upper_map flumap; > + > +#else > + > +#include "flash.h" /* for msg_* */ > + > +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP > + > +struct flash_descriptor fdbar = { 0 }; > +struct flash_component fcba = { {0} }; > +struct flash_region frba = { {0} }; > +struct flash_master fmba = { {0} }; > + > +uint32_t getFCBA() > Please use foo(void) for function declarations/definitions if no parameters are used. Same comment applies for all other functions of the same type. > +{ > + return (fdbar.FLMAP0 << 4) & 0x00000ff0; > +} > + > +uint32_t getFRBA() > +{ > + return (fdbar.FLMAP0 >> 12) & 0x00000ff0; > +} > + > +uint32_t getFMBA() > +{ > + return (fdbar.FLMAP1 << 4) & 0x00000ff0; > +} > + > +uint32_t getFMSBA() > +{ > + return (fdbar.FLMAP2 << 4) & 0x00000ff0; > +} > + > +uint32_t getFLREG_limit(uint32_t flreg) > +{ > + return (flreg >> 4) & 0x01fff000; > +} > + > +uint32_t getFLREG_base(uint32_t flreg) > +{ > + return (flreg << 12) & 0x01fff000; > +} > + > +uint32_t getFISBA() > +{ > + return (fdbar.FLMAP1 >> 12) & 0x00000ff0; > +} > + > +/** Returns the integer representation of the component density with index > +comp in bytes or 0 if a correct size can not be determined. */ > +int getFCBA_component_density(uint8_t comp) > +{ > + uint8_t size_enc; > + const int dec_mem[6] = { > + 512 * 1024, > + 1 * 1024 * 1024, > + 2 * 1024 * 1024, > + 4 * 1024 * 1024, > + 8 * 1024 * 1024, > + 16 * 1024 * 1024, > + }; > + > + switch(comp) { > + case 0: > + size_enc = fcba.comp1_density; > + break; > + case 1: > + if (fdbar.NC == 0) > + return 0; > + size_enc = fcba.comp2_density; > + break; > + default: > + msg_perr("Only component index 0 or 1 are supported yet.\n"); > + return 0; > + } > + if (size_enc > 5) { > + msg_perr("Density of component with index %d illegal or " > Please replace "illegal" with "invalid" everywhere. > + "unsupported. Encoded density is 0x%x.\n", > + comp, > Please kill this line break. > + size_enc); > + return 0; > + } > + return dec_mem[size_enc]; > +} > + > +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP > +uint32_t getVTBA() > +{ > + return (flumap.FLUMAP1 << 4) & 0x0ff0; > +} > +#endif > + > +const struct flash_descriptor_addresses desc_addr = { > + .FCBA = getFCBA, > + .FRBA = getFRBA, > + .FMBA = getFMBA, > + .FMSBA = getFMSBA, > + .FISBA = getFISBA, > + .FLREG_limit = getFLREG_limit, > + .FLREG_base = getFLREG_base, > +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP > + .VTBA = getVTBA, > +#endif > +}; > + > +void pretty_print_ich_descriptors() > +{ > + pretty_print_ich_descriptor_map(); > + pretty_print_ich_descriptor_component(); > + pretty_print_ich_descriptor_region(); > + pretty_print_ich_descriptor_master(); > +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP > + pretty_print_ich_descriptor_upper_map(); > + /* FIXME: detect chipset correctly */ > + pretty_print_ich_descriptor_straps(CHIPSET_SERIES_5_IBEX_PEAK); > +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP > + msg_pdbg("\n"); > +} > + > +void pretty_print_ich_descriptor_map(void) > +{ > + msg_pdbg("=== FDBAR ===\n"); > + msg_pdbg("FLVALSIG 0x%8.8x\n", fdbar.FLVALSIG); > + msg_pdbg("FLMAP0 0x%8.8x\n", fdbar.FLMAP0 ); > + msg_pdbg("FLMAP1 0x%8.8x\n", fdbar.FLMAP1 ); > + msg_pdbg("FLMAP2 0x%8.8x\n", fdbar.FLMAP2 ); > + msg_pdbg("\n"); > + msg_pdbg("--- FDBAR details ---\n"); > + msg_pdbg("0x%2.2x NR Number of Regions\n", fdbar.NR ); > + msg_pdbg("0x%8.8x FRBA Flash Region Base Address\n", desc_addr.FRBA() ); > + msg_pdbg("0x%2.2x NC Number of Components\n", fdbar.NC ); > + msg_pdbg("0x%8.8x FCBA Flash Component Base Address\n", desc_addr.FCBA() ); > + msg_pdbg("\n"); > + msg_pdbg("0x%2.2x ISL ICH Strap Length\n", fdbar.ISL ); > + msg_pdbg("0x%8.8x FISBA Flash ICH Strap Base Address\n", desc_addr.FISBA()); > + msg_pdbg("0x%2.2x NM Number of Masters\n", fdbar.NM ); > + msg_pdbg("0x%8.8x FMBA Flash Master Base Address\n", desc_addr.FMBA() ); > + msg_pdbg("\n"); > + msg_pdbg("0x%2.2x MSL MCH Strap Length\n", fdbar.MSL ); > + msg_pdbg("0x%8.8x FMSBA Flash MCH Strap Base Address\n", desc_addr.FMSBA()); > +} > + > +void pretty_print_ich_descriptor_component(void) > +{ > + const char * str_freq[8] = { > const char * const str_freq[8] = { > + "20 MHz", /* 000 */ > + "33 MHz", /* 001 */ > + "reserved/illegal", /* 010 */ > + "reserved/illegal", /* 011 */ > + "50 MHz", /* 100 */ > + "reserved/illegal", /* 101 */ > + "reserved/illegal", /* 110 */ > + "reserved/illegal" /* 111 */ > + }; > + const char * str_mem[8] = { > Same here. > + "512kB", > + "1 MB", > + "2 MB", > + "4 MB", > + "8 MB", > + "16 MB", > + "undocumented/illegal", > + "reserved/illegal" > + }; > + > + msg_pdbg("\n"); > + msg_pdbg("=== FCBA ===\n"); > + msg_pdbg("FLCOMP 0x%8.8x\n", fcba.FLCOMP); > + msg_pdbg("FLILL 0x%8.8x\n", fcba.FLILL ); > + msg_pdbg("\n"); > + msg_pdbg("--- FCBA details ---\n"); > + msg_pdbg("0x%2.2x freq_read_id %s\n", > + fcba.freq_read_id , str_freq[fcba.freq_read_id ]); > Out-of-bounds access if fcba.freq_read_id>=8 > + msg_pdbg("0x%2.2x freq_write %s\n", > + fcba.freq_write , str_freq[fcba.freq_write ]); > Same problem here. > + msg_pdbg("0x%2.2x freq_fastread %s\n", > + fcba.freq_fastread, str_freq[fcba.freq_fastread]); > And here. > + msg_pdbg("0x%2.2x fastread %ssupported\n", > + fcba.fastread, fcba.fastread ? "" : "not "); > + msg_pdbg("0x%2.2x freq_read %s\n", > + fcba.freq_read, str_freq[fcba.freq_read ]); > And here. > + msg_pdbg("0x%2.2x comp 1 density %s\n", > + fcba.comp1_density, str_mem[fcba.comp1_density]); > And here. > + if (fdbar.NC) > + msg_pdbg("0x%2.2x comp 2 density %s\n", > + fcba.comp2_density, str_mem[fcba.comp2_density]); > And here. > + else > + msg_pdbg("0x%2.2x comp 2 is not used (FLMAP0.NC=0)\n", > + fcba.comp2_density); > + msg_pdbg("\n"); > + msg_pdbg("0x%2.2x invalid instr 0\n", fcba.invalid_instr0); > + msg_pdbg("0x%2.2x invalid instr 1\n", fcba.invalid_instr1); > + msg_pdbg("0x%2.2x invalid instr 2\n", fcba.invalid_instr2); > + msg_pdbg("0x%2.2x invalid instr 3\n", fcba.invalid_instr3); > +} > + > +void pretty_print_ich_descriptor_region(void) > +{ > + msg_pdbg("\n"); > + msg_pdbg("=== FRBA ===\n"); > + msg_pdbg("FLREG0 0x%8.8x\n", frba.FLREG0); > + msg_pdbg("FLREG1 0x%8.8x\n", frba.FLREG1); > + msg_pdbg("FLREG2 0x%8.8x\n", frba.FLREG2); > + msg_pdbg("FLREG3 0x%8.8x\n", frba.FLREG3); > + msg_pdbg("\n"); > + msg_pdbg("--- FRBA details ---\n"); > + msg_pdbg("0x%8.8x region 0 limit (descr)\n", desc_addr.FLREG_limit(frba.FLREG0)); > + msg_pdbg("0x%8.8x region 0 base (descr)\n", desc_addr.FLREG_base(frba.FLREG0)); > + msg_pdbg("0x%8.8x region 1 limit ( BIOS)\n", desc_addr.FLREG_limit(frba.FLREG1)); > + msg_pdbg("0x%8.8x region 1 base ( BIOS)\n", desc_addr.FLREG_base(frba.FLREG1)); > + msg_pdbg("0x%8.8x region 2 limit ( ME )\n", desc_addr.FLREG_limit(frba.FLREG2)); > + msg_pdbg("0x%8.8x region 2 base ( ME )\n", desc_addr.FLREG_base(frba.FLREG2)); > + msg_pdbg("0x%8.8x region 3 limit ( GbE )\n", desc_addr.FLREG_limit(frba.FLREG3)); > + msg_pdbg("0x%8.8x region 3 base ( GbE )\n", desc_addr.FLREG_base(frba.FLREG3)); > +} > + > +void pretty_print_ich_descriptor_master(void) > +{ > + msg_pdbg("\n"); > + msg_pdbg("=== FMBA ===\n"); > + msg_pdbg("FLMSTR1 0x%8.8x\n", fmba.FLMSTR1); > + msg_pdbg("FLMSTR2 0x%8.8x\n", fmba.FLMSTR2); > + msg_pdbg("FLMSTR3 0x%8.8x\n", fmba.FLMSTR3); > + > + msg_pdbg("\n"); > + msg_pdbg("--- FMBA details ---\n"); > + msg_pdbg("BIOS can %s write GbE\n", fmba.BIOS_GbE_write ? " " : "NOT"); > + msg_pdbg("BIOS can %s write ME\n", fmba.BIOS_ME_write ? " " : "NOT"); > + msg_pdbg("BIOS can %s write BIOS\n", fmba.BIOS_BIOS_write ? " " : "NOT"); > + msg_pdbg("BIOS can %s write descr\n", fmba.BIOS_descr_write ? " " : "NOT"); > + msg_pdbg("BIOS can %s read GbE\n", fmba.BIOS_GbE_read ? " " : "NOT"); > + msg_pdbg("BIOS can %s read ME\n", fmba.BIOS_ME_read ? " " : "NOT"); > + msg_pdbg("BIOS can %s read BIOS\n", fmba.BIOS_BIOS_read ? " " : "NOT"); > + msg_pdbg("BIOS can %s read descr\n", fmba.BIOS_descr_read ? " " : "NOT"); > + msg_pdbg("ME can %s write GbE\n", fmba.ME_GbE_write ? " " : "NOT"); > + msg_pdbg("ME can %s write ME\n", fmba.ME_ME_write ? " " : "NOT"); > + msg_pdbg("ME can %s write BIOS\n", fmba.ME_BIOS_write ? " " : "NOT"); > + msg_pdbg("ME can %s write descr\n", fmba.ME_descr_write ? " " : "NOT"); > + msg_pdbg("ME can %s read GbE\n", fmba.ME_GbE_read ? " " : "NOT"); > + msg_pdbg("ME can %s read ME\n", fmba.ME_ME_read ? " " : "NOT"); > + msg_pdbg("ME can %s read BIOS\n", fmba.ME_BIOS_read ? " " : "NOT"); > + msg_pdbg("ME can %s read descr\n", fmba.ME_descr_read ? " " : "NOT"); > + msg_pdbg("GbE can %s write GbE\n", fmba.GbE_GbE_write ? " " : "NOT"); > + msg_pdbg("GbE can %s write ME\n", fmba.GbE_ME_write ? " " : "NOT"); > + msg_pdbg("GbE can %s write BIOS\n", fmba.GbE_BIOS_write ? " " : "NOT"); > + msg_pdbg("GbE can %s write descr\n", fmba.GbE_descr_write ? " " : "NOT"); > + msg_pdbg("GbE can %s read GbE\n", fmba.GbE_GbE_read ? " " : "NOT"); > + msg_pdbg("GbE can %s read ME\n", fmba.GbE_ME_read ? " " : "NOT"); > + msg_pdbg("GbE can %s read BIOS\n", fmba.GbE_BIOS_read ? " " : "NOT"); > + msg_pdbg("GbE can %s read descr\n", fmba.GbE_descr_read ? " " : "NOT"); > +} > + > +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP > +void pretty_print_ich_descriptor_straps_ich8(void) > +{ > + const char * str_GPIO12[4] = { > + "GPIO12", > + "LAN PHY Power Control Function (Native Output)", > + " GLAN_DOCK# (Native Input)", > Is the space before GLAN_DOCK# intentional? > + "invalid configuration", > + }; > + > + msg_pdbg("\n"); > + msg_pdbg("=== FISBA ===\n"); > + msg_pdbg("STRP0 0x%8.8x\n", fisba.ich8.STRP0); > + > + msg_pdbg("\n"); > + msg_pdbg("--- FISBA details ---\n"); > + msg_pdbg("ME SMBus addr2 0x%2.2x\n", fisba.ich8.ASD2); > + msg_pdbg("ME SMBus addr1 0x%2.2x\n", fisba.ich8.ASD); > + msg_pdbg("ME SMBus Controller is connected to %s\n", fisba.ich8.MESM2SEL ? "SMLink pins" : "SMBus pins"); > + msg_pdbg("SPI CS1 is used for %s\n", fisba.ich8.SPICS1_LANPHYPC_SEL ? "LAN PHY Power Control Function" : "SPI Chip Select"); > + msg_pdbg("GPIO12_SEL is used as %s\n", str_GPIO12[fisba.ich8.GPIO12_SEL]); > Out of bounds? > + msg_pdbg("PCIe Port 6 is used for %s\n", fisba.ich8.GLAN_PCIE_SEL ? "integrated GLAN" : "PCI Express"); > + msg_pdbg("Intel AMT SMBus Controller 1 is connected to %s\n", fisba.ich8.BMCMODE ? "SMLink" : "SMBus"); > + msg_pdbg("TCO slave is on %s. Intel AMT SMBus Controller 1 is %sabled\n", > + fisba.ich8.TCOMODE ? "SMBus" : "SMLink", fisba.ich8.TCOMODE ? "en" : "dis"); > + msg_pdbg("ME A is %sabled\n", fisba.ich8.ME_DISABLE ? "dis" : "en"); > + > + msg_pdbg("\n"); > + msg_pdbg("=== FMSBA ===\n"); > + msg_pdbg("STRP1 0x%8.8x\n", fisba.ich8.STRP1); > + > + msg_pdbg("\n"); > + msg_pdbg("--- FMSBA details ---\n"); > + msg_pdbg("ME B is %sabled\n", fisba.ich8.ME_disable_B ? "dis" : "en"); > +} > + > +void pretty_print_ich_descriptor_straps_ibex(void) > +{ > + int i; > + msg_pdbg("\n"); > + msg_pdbg("=== FPSBA ===\n"); > + for(i = 0; i <= 15; i++) > + msg_pdbg("STRP%-2d = 0x%8.8x\n", i, fisba.ibex.STRPs[i]); > +} > + > +void pretty_print_ich_descriptor_straps(enum chipset cs) > +{ > + switch (cs) { > + case CHIPSET_ICH8: > + pretty_print_ich_descriptor_straps_ich8(); > + break; > + case CHIPSET_SERIES_5_IBEX_PEAK: > + pretty_print_ich_descriptor_straps_ibex(); > + break; > + default: > + break; > + } > +} > + > +void pretty_print_ich_descriptor_upper_map(void) > +{ > + int i; > + msg_pdbg("\n"); > + msg_pdbg("=== FLUMAP ===\n"); > + msg_pdbg("FLUMAP1 0x%8.8x\n", flumap.FLUMAP1); > + > + msg_pdbg("\n"); > + msg_pdbg("--- FLUMAP details ---\n"); > + msg_pdbg("VTL 0x%8.8x\n", flumap.VTL); > + msg_pdbg("VTBA 0x%8.8x\n", desc_addr.VTBA()); > + msg_pdbg("\n"); > + > + for (i=0; i < flumap.VTL/2; i++) > + { > + msg_pdbg(" JID%d = 0x%8.8x\n", i, flumap.vscc_table[i].JID ); > Out of bounds if flumap.VTL contains garbage? > + msg_pdbg(" VSCC%d = 0x%8.8x\n", i, flumap.vscc_table[i].VSCC); > Out of bounds? > + } > +} > + > +int read_ich_descriptors_from_dump(uint32_t *dump) > +{ > + int i; > + uint8_t pch_bug_offset = 0; > + if (dump[0] != DESCRIPTOR_MODE_MAGIC) { > + if (dump[4] == DESCRIPTOR_MODE_MAGIC) > + pch_bug_offset = 4; > + else > + return -1; > + } > + > + /* map */ > + fdbar.FLVALSIG = dump[0 + pch_bug_offset]; > + fdbar.FLMAP0 = dump[1 + pch_bug_offset]; > + fdbar.FLMAP1 = dump[2 + pch_bug_offset]; > + fdbar.FLMAP2 = dump[3 + pch_bug_offset]; > Please either align with tabs or kill the alignment. If you think aligning with spaces is essential, please tell me why. > + > + /* component */ > + fcba.FLCOMP = dump[(desc_addr.FCBA() >> 2) + 0]; > + fcba.FLILL = dump[(desc_addr.FCBA() >> 2) + 1]; > + fcba.FLPB = dump[(desc_addr.FCBA() >> 2) + 2]; > Out of bounds? > + > + /* region */ > + frba.FLREG0 = dump[(desc_addr.FRBA() >> 2) + 0]; > + frba.FLREG1 = dump[(desc_addr.FRBA() >> 2) + 1]; > + frba.FLREG2 = dump[(desc_addr.FRBA() >> 2) + 2]; > + frba.FLREG3 = dump[(desc_addr.FRBA() >> 2) + 3]; > Out of bounds? > + > + /* master */ > + fmba.FLMSTR1 = dump[(desc_addr.FMBA() >> 2) + 0]; > + fmba.FLMSTR2 = dump[(desc_addr.FMBA() >> 2) + 1]; > + fmba.FLMSTR3 = dump[(desc_addr.FMBA() >> 2) + 2]; > Out of bounds? > + > + /* upper map */ > + flumap.FLUMAP1 = dump[(0x0efc >> 2) + 0]; > + > + for (i=0; i < flumap.VTL; i++) > + { > + flumap.vscc_table[i].JID = dump[(desc_addr.VTBA() >> 2) + i * 2 + 0]; > + flumap.vscc_table[i].VSCC = dump[(desc_addr.VTBA() >> 2) + i * 2 + 1]; > Out of bounds? > + } > + /* straps */ > + /* FIXME: detect chipset correctly */ > + switch (CHIPSET_SERIES_5_IBEX_PEAK) { > WTF? > + case CHIPSET_ICH8: > + fisba.ich8.STRP0 = dump[(desc_addr.FISBA() >> 2) + 0]; > + fisba.ich8.STRP1 = dump[(desc_addr.FMSBA() >> 2) + 0]; > Out of bounds? > + break; > + case CHIPSET_SERIES_5_IBEX_PEAK: > + for(i = 0; i <= 15; i++) > + fisba.ibex.STRPs[i] = dump[(desc_addr.FISBA() >> 2) + i]; > Out of bounds? > + break; > + default: > + break; > + } > + > + return 0; > +} > +#else // ICH_DESCRIPTORS_FROM_MMAP_DUMP > + > +static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) > +{ > + uint32_t control = 0; > + control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS; > + control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI; > + *(volatile uint32_t *) (spibar + ICH9_REG_FDOC) = control; > + return *(volatile uint32_t *)(spibar + ICH9_REG_FDOD); > +} > + > +void read_ich_descriptors_from_fdo(void *spibar) > +{ > + msg_pdbg("Reading flash descriptors " > + "mapped by the chipset via FDOC/FDOD..."); > + /* descriptor map section */ > + fdbar.FLVALSIG = read_descriptor_reg(0, 0, spibar); > + fdbar.FLMAP0 = read_descriptor_reg(0, 1, spibar); > + fdbar.FLMAP1 = read_descriptor_reg(0, 2, spibar); > + fdbar.FLMAP2 = read_descriptor_reg(0, 3, spibar); > Alignment with tabs... > + > + /* component section */ > + fcba.FLCOMP = read_descriptor_reg(1, 0, spibar); > + fcba.FLILL = read_descriptor_reg(1, 1, spibar); > + fcba.FLPB = read_descriptor_reg(1, 2, spibar); > + > + /* region section */ > + frba.FLREG0 = read_descriptor_reg(2, 0, spibar); > + frba.FLREG1 = read_descriptor_reg(2, 1, spibar); > + frba.FLREG2 = read_descriptor_reg(2, 2, spibar); > + frba.FLREG3 = read_descriptor_reg(2, 3, spibar); > + > + /* master section */ > + fmba.FLMSTR1 = read_descriptor_reg(3, 0, spibar); > + fmba.FLMSTR2 = read_descriptor_reg(3, 1, spibar); > + fmba.FLMSTR3 = read_descriptor_reg(3, 2, spibar); > + > + /* strap section and upper map */ > + /* impossible via FDOC/FDOD(?) */ > + msg_pdbg(" done\n"); > +} > + > +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP > +#endif // defined(__i386__) || defined(__x86_64__) > diff --git a/ich_descriptors.h b/ich_descriptors.h > new file mode 100644 > index 0000000..af9d0ba > --- /dev/null > +++ b/ich_descriptors.h > @@ -0,0 +1,408 @@ > +/* This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * authors: > + * (c) 2010 Matthias Wenzel <bios at mazzoo dot de> > + * (c) 2011 Stefan Tauner > + */ > + > +#include <stdint.h> > + > +#if defined(__i386__) || defined(__x86_64__) > +#ifndef __ICH_DESCRIPTORS_H__ > +#define __ICH_DESCRIPTORS_H__ 1 > + > +/* should probably be in ichspi.h */ > +#define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */ > +#define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Select */ > +#define FDOC_FDSI (0x3f << FDOC_FDSI_OFF) > +#define FDOC_FDSS_OFF 12 /* 12-14: Flash Descriptor Section Select */ > +#define FDOC_FDSS (0x3 << FDOC_FDSS_OFF) > +#define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */ > + > +enum chipset { > + CHIPSET_ICH8, > + CHIPSET_ICH9, > + CHIPSET_ICH10, > + CHIPSET_SERIES_5_IBEX_PEAK, > + CHIPSET_SERIES_6_COUGAR_POINT, > + CHIPSET_SERIES_7_PANTHER_POINT > +}; > Are those all possible chipsets? > + > +struct flash_descriptor_addresses { > + uint32_t (*FCBA)(void); > + uint32_t (*FRBA)(void); > + uint32_t (*FMBA)(void); > + uint32_t (*FMSBA)(void); > + uint32_t (*FLREG_limit)(uint32_t flreg); > + uint32_t (*FLREG_base)(uint32_t flreg); > + uint32_t (*FISBA)(void); > +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP > + uint32_t (*VTBA)(void); > +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP > +}; > + > +struct flash_descriptor { > + uint32_t FLVALSIG; /* 0x00 */ > + union { /* 0x04 */ > + uint32_t FLMAP0; > + struct { > + uint8_t FCBA :8; > + uint8_t NC :2; > + unsigned :6; > + uint8_t FRBA :8; > + uint8_t NR :3; > + unsigned :5; > + }; > + }; > + union { /* 0x08 */ > + uint32_t FLMAP1; > + struct { > + uint8_t FMBA :8; > + uint8_t NM :3; > + unsigned :5; > + union { > + uint8_t FISBA :8; > + uint8_t FPSBA :8; > + }; > + uint8_t ISL :8; > + }; > + }; > + union { /* 0x0c */ > + uint32_t FLMAP2; > + struct { > + uint8_t FMSBA :8; > + uint8_t MSL :8; > + unsigned :16; > + }; > + }; > +}; > This won't fly. At the very least, it needs __attribute__((packed)), but even then I see pretty explosions because the bitfield ordering is implementation defined and I expect this to do the wrong thing if anyone ever runs that code on bigendian hosts (looking at a file is possible even if you don't have ICH SPI hardware). Heck, each gcc version could do something else. I might have misunderstood C99, so feel free to correct me. > + > +struct flash_component { > + union { /* 0x00 */ > + uint32_t FLCOMP; > + struct { > + uint8_t comp1_density :3; > + uint8_t comp2_density :3; > + unsigned :11; > + uint8_t freq_read :3; > + uint8_t fastread :1; > + uint8_t freq_fastread :3; > + uint8_t freq_write :3; > + uint8_t freq_read_id :3; > + unsigned :2; > + }; > + }; > + union { /* 0x04 */ > + uint32_t FLILL; > + struct { > + uint8_t invalid_instr0; > + uint8_t invalid_instr1; > + uint8_t invalid_instr2; > + uint8_t invalid_instr3; > + }; > + }; > + union { /* 0x08 */ > + uint32_t FLPB; > + struct { > + uint16_t FPBA :13; > + unsigned :19; > + }; > + }; > +}; > Same problem. > + > +struct flash_region { > + > + union { > + uint32_t FLREG0; /* Flash Descriptor */ > + struct { > + uint16_t reg0_base :13; > + unsigned :3; > + uint16_t reg0_limit :13; > + unsigned :3; > + }; > + }; > + union { > + uint32_t FLREG1; /* BIOS */ > + struct { > + uint16_t reg1_base :13; > + unsigned :3; > + uint16_t reg1_limit :13; > + unsigned :3; > + }; > + }; > + union { > + uint32_t FLREG2; /* ME */ > + struct { > + uint16_t reg2_base :13; > + unsigned :3; > + uint16_t reg2_limit :13; > + unsigned :3; > + }; > + }; > + union { > + uint32_t FLREG3; /* GbE */ > + struct { > + uint16_t reg3_base :13; > + unsigned :3; > + uint16_t reg3_limit :13; > + unsigned :3; > + }; > + }; > +} frba; > Dito. > + > +struct flash_master { > + union { > + uint32_t FLMSTR1; > + struct { > + uint16_t BIOS_req_ID :16; > + uint8_t BIOS_descr_read :1; > + uint8_t BIOS_BIOS_read :1; > + uint8_t BIOS_ME_read :1; > + uint8_t BIOS_GbE_read :1; > + uint8_t BIOS_plat_read :1; > + unsigned :3; > + uint8_t BIOS_descr_write :1; > + uint8_t BIOS_BIOS_write :1; > + uint8_t BIOS_ME_write :1; > + uint8_t BIOS_GbE_write :1; > + uint8_t BIOS_plat_write :1; > + unsigned :3; > + }; > + }; > + union { > + uint32_t FLMSTR2; > + struct { > + uint16_t ME_req_ID :16; > + uint8_t ME_descr_read :1; > + uint8_t ME_BIOS_read :1; > + uint8_t ME_ME_read :1; > + uint8_t ME_GbE_read :1; > + uint8_t ME_plat_read :1; > + unsigned :3; > + uint8_t ME_descr_write :1; > + uint8_t ME_BIOS_write :1; > + uint8_t ME_ME_write :1; > + uint8_t ME_GbE_write :1; > + uint8_t ME_plat_write :1; > + unsigned :3; > + }; > + }; > + union { > + uint32_t FLMSTR3; > + struct { > + uint16_t GbE_req_ID :16; > + uint8_t GbE_descr_read :1; > + uint8_t GbE_BIOS_read :1; > + uint8_t GbE_ME_read :1; > + uint8_t GbE_GbE_read :1; > + uint8_t GbE_plat_read :1; > + unsigned :3; > + uint8_t GbE_descr_write :1; > + uint8_t GbE_BIOS_write :1; > + uint8_t GbE_ME_write :1; > + uint8_t GbE_GbE_write :1; > + uint8_t GbE_plat_write :1; > + unsigned :3; > + }; > + }; > +}; > Dito. > + > +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP > +struct flash_strap { > + union { > + struct { > + union { > + uint32_t STRP0; > + struct { > + uint8_t ME_DISABLE :1; > + unsigned :6; > + uint8_t TCOMODE :1; > + uint8_t ASD :7; > + uint8_t BMCMODE :1; > + unsigned :3; > + uint8_t GLAN_PCIE_SEL :1; > + uint8_t GPIO12_SEL :2; > + uint8_t SPICS1_LANPHYPC_SEL :1; > + uint8_t MESM2SEL :1; > + unsigned :1; > + uint8_t ASD2 :7; > + }; > + }; > + union { > + uint32_t STRP1; > + struct { > + uint8_t ME_disable_B :1; > + unsigned :31; > + }; > + }; > + }ich8; > + union { > + uint32_t STRPs[15]; > + struct { > + union { > + uint32_t STRP0; > + struct { > + unsigned :1; > + uint8_t cs_ss2 :1; > + unsigned :5; > + uint8_t SMB_EN :1; > + uint8_t SML0_EN :1; > + uint8_t SML1_EN :1; > + uint8_t SML1FRQ :2; > + uint8_t SMB0FRQ :2; > + uint8_t SML0FRQ :2; > + unsigned :4; > + uint8_t LANPHYPC_GP12_SEL :1; > + uint8_t cs_ss1 :1; > + unsigned :2; > + uint8_t DMI_REQID_DIS :1; > + unsigned :4; > + uint8_t BBBS :2; > + unsigned :1; > + }; > + }; > + union { > + uint32_t STRP1; > + struct { > + }; > Why an empty struct? > + }; > + union { > + uint32_t STRP2; > + struct { > + }; > Dito. > + }; > + union { > + uint32_t STRP3; > + struct { > + }; > + }; > You get the point. > + union { > + uint32_t STRP4; > + struct { > + }; > + }; > + union { > + uint32_t STRP5; > + struct { > + }; > + }; > + union { > + uint32_t STRP6; > + struct { > + }; > + }; > + union { > + uint32_t STRP7; > + struct { > + }; > + }; > + union { > + uint32_t STRP8; > + struct { > + }; > + }; > + union { > + uint32_t STRP9; > + struct { > + }; > + }; > + union { > + uint32_t STRP10; > + struct { > + }; > + }; > + union { > + uint32_t STRP11; > + struct { > + }; > + }; > + union { > + uint32_t STRP12; > + struct { > + }; > + }; > + union { > + uint32_t STRP13; > + struct { > + }; > + }; > + union { > + uint32_t STRP14; > + struct { > + }; > + }; > + union { > + uint32_t STRP15; > + struct { > + }; > + }; > + }; > + }ibex; > + }; > +}; > __attribute__((packed)) > + > +struct flash_upper_map { > + union { > + uint32_t FLUMAP1; > + struct { > + uint8_t VTBA :8; > + uint8_t VTL :8; > + unsigned :16; > + }; > + }; > + struct { > + union { > + uint32_t JID; > + struct { > + uint8_t vid :8; > + uint8_t cid0 :8; > + uint8_t cid1 :8; > + unsigned :8; > + }; > + }; > + union { > + uint32_t VSCC; > + struct { > + uint8_t ubes :2; > + uint8_t uwg :1; > + uint8_t uwsr :1; > + uint8_t uwews :1; > + unsigned :3; > + uint8_t ueo :8; > + uint8_t lbes :2; > + uint8_t lwg :1; > + uint8_t lwsr :1; > + uint8_t lwews :1; > + unsigned :3; > + uint16_t leo :16; > + }; > + }; > + }vscc_table[128]; > +}; > Dito. > +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP > + > +void pretty_print_ich_descriptors(void); > + > +void pretty_print_ich_descriptor_map(void); > +void pretty_print_ich_descriptor_component(void); > +void pretty_print_ich_descriptor_region(void); > +void pretty_print_ich_descriptor_master(void); > + > +int getFCBA_component_density(uint8_t comp); > + > +#ifdef ICH_DESCRIPTORS_FROM_MMAP_DUMP > + > +void pretty_print_ich_descriptor_upper_map(void); > +void pretty_print_ich_descriptor_straps(enum chipset cs); > +int read_ich_descriptors_from_dump(uint32_t *dump); > + > +#else // ICH_DESCRIPTORS_FROM_MMAP_DUMP > + > +void read_ich_descriptors_from_fdo(void *spibar); > + > +#endif // ICH_DESCRIPTORS_FROM_MMAP_DUMP > + > +#endif // __ICH_DESCRIPTORS_H__ > +#endif // defined(__i386__) || defined(__x86_64__) > diff --git a/ichspi.c b/ichspi.c > index 584cab4..d8df898 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -6,6 +6,7 @@ > * Copyright (C) 2008 Dominik Geyer <dominik.geyer(a)kontron.com> > * Copyright (C) 2008 coresystems GmbH <info(a)coresystems.de> > * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger > + * Copyright (C) 2011 Stefan Tauner > * > * This program is free software; you can redistribute it and/or modify > * it under the terms of the GNU General Public License as published by > @@ -41,6 +42,7 @@ > #include "chipdrivers.h" > #include "programmer.h" > #include "spi.h" > +#include "ich_descriptors.h" > > /* ICH9 controller register definition */ > #define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ > @@ -1197,6 +1199,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > uint8_t old, new; > uint16_t spibar_offset, tmp2; > uint32_t tmp; > + int ichspi_desc = 0; > > switch (ich_generation) { > case 7: > @@ -1268,6 +1271,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); > ichspi_lock = 1; > } > + if (tmp2 & HSFS_FDV) > + ichspi_desc = 1; > > tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); > msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); > @@ -1316,6 +1321,11 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); > msg_pdbg("0xA0: 0x%08x (BBAR)\n", > ichspi_bbar); > + msg_pdbg("\n"); > + if (ichspi_desc) { > + read_ich_descriptors_from_fdo(ich_spibar); > + pretty_print_ich_descriptors(); > + } > ich_init_opcodes(); > break; > default: > diff --git a/util/ich_descriptors_tool/Makefile b/util/ich_descriptors_tool/Makefile > new file mode 100644 > index 0000000..9b1d096 > --- /dev/null > +++ b/util/ich_descriptors_tool/Makefile > @@ -0,0 +1,42 @@ > +CC ?= gcc > + > +PROGRAM=ich_descriptors_tool > +EXTRAINCDIRS = ../../ . > +DEPPATH = .dep > +OBJATH = .obj > +SHAREDSRC = ich_descriptors.c > +SHAREDSRCDIR = ../.. > + > +SRC = $(wildcard *.c) > + > +CFLAGS=-Wall > +CFLAGS += -MMD -MP -MF $(DEPPATH)/$((a)F).d > +# enables functions that populate the descriptor structs from plain dump arrays > +CFLAGS += -D ICH_DESCRIPTORS_FROM_MMAP_DUMP > +CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) > + > +OBJ = $(OBJATH)/$(SRC:%.c=%.o) > + > +SHAREDOBJ = $(OBJATH)/$(notdir $(SHAREDSRC:%.c=%.o)) > + > +all:$(PROGRAM) > + > +$(OBJ): $(OBJATH)/%.o : %.c > + $(CC) $(CFLAGS) -o $@ -c $< > + > +# this enables us to NOT share object files with flashrom, > +# which would lead to unexpected results otherwise (w/o running make clean) > +$(SHAREDOBJ): $(OBJATH)/%.o : $(SHAREDSRCDIR)/%.c > + $(CC) $(CFLAGS) -o $@ -c $< > + > +$(PROGRAM): $(OBJ) $(SHAREDOBJ) > + $(CC) -o $(PROGRAM) $(OBJ) $(SHAREDOBJ) > + > +clean: > + rm -f $(PROGRAM) > + rm -rf $(DEPPATH) $(OBJATH) > + > +# Include the dependency files. > +-include $(shell mkdir -p $(DEPPATH) $(OBJATH) 2>/dev/null) $(wildcard $(DEPPATH)/*) > + > +.PHONY: all clean > \ No newline at end of file > A newline at the end of the file would be nice. > diff --git a/util/ich_descriptors_tool/TODO b/util/ich_descriptors_tool/TODO > new file mode 100644 > index 0000000..e3933ee > --- /dev/null > +++ b/util/ich_descriptors_tool/TODO > @@ -0,0 +1,5 @@ > +- reverse the path, as in assemble a descriptormode image from various > + blobs (BIOS, GbE, ME, OEM) and a description (xml? custom config? > + sane defaults and cmd-line switches?) > +- dump 256 OEM bytes > +- handle descriptors of various chipsets correctly > \ No newline at end of file > diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c > new file mode 100644 > index 0000000..8ce7677 > --- /dev/null > +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c > @@ -0,0 +1,226 @@ > +/* > + * dump information and binaries from BIOS images that are in descriptor mode/soft-strap > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * authors: > + * (c) 2010 Matthias Wenzel <bios at mazzoo dot de> > + * (c) 2011 Stefan Tauner > + * > + * */ > +#include <stdio.h> > +#include <stdint.h> > +#include <stdlib.h> > +#include <sys/mman.h> > +#include <sys/types.h> > +#include <sys/stat.h> > +#include <fcntl.h> > +#include <unistd.h> > +#include <string.h> > +#include <errno.h> > +#include "flash.h" > +#include "ich_descriptors.h" > + > +extern struct flash_descriptor fdbar; > +extern struct flash_component fcba; > +extern struct flash_region frba; > +extern struct flash_master fmba; > +extern struct flash_strap fisba; > +extern struct flash_upper_map flumap; > +extern struct flash_descriptor_addresses desc_addr; > + > +static int f; /* file descriptor to flash file */ > +static int fs; /* file size */ > +static uint32_t *fm; /* mmap'd file */ > + > +void dump_file_descriptor(char * fn) > +{ > + char * n = malloc(strlen(fn) + 11); > + snprintf(n, strlen(fn) + 11, "%s.descr.bin", fn); > + printf("\n"); > + printf("+++ dumping %s ... ", n); > + int fh = open(n, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); > + free(n); > + if (fh < 0) > + { > + printf("ERROR: couldn't open(%s): %s\n", n, strerror(errno)); > + exit(1); > + } > + > + int ret; > + ret = write(fh, &fm[frba.reg0_base >> 2], frba.reg0_limit); > + if (ret != frba.reg0_limit) > + { > + printf("FAILED.\n"); > + exit(1); > + } > + > + printf("done.\n"); > + > + close(fh); > +} > + > +void dump_file_BIOS(char * fn) > +{ > + char * n = malloc(strlen(fn) + 10); > + snprintf(n, strlen(fn) + 10, "%s.BIOS.bin", fn); > + printf("\n"); > + printf("+++ dumping %s ... ", n); > + int fh = open(n, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); > + free(n); > + if (fh < 0) > + { > + printf("ERROR: couldn't open(%s): %s\n", n, strerror(errno)); > + exit(1); > + } > + > + int ret; > + ret = write(fh, &fm[frba.reg1_base >> 2], frba.reg1_limit); > + if (ret != frba.reg1_limit) > + { > + printf("FAILED.\n"); > + exit(1); > + } > + > + printf("done.\n"); > + > + close(fh); > +} > + > +void dump_file_ME(char * fn) > +{ > + char * n = malloc(strlen(fn) + 8); > + snprintf(n, strlen(fn) + 8, "%s.ME.bin", fn); > + printf("\n"); > + printf("+++ dumping %s ... ", n); > + int fh = open(n, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); > + free(n); > + if (fh < 0) > + { > + printf("ERROR: couldn't open(%s): %s\n", n, strerror(errno)); > + exit(1); > + } > + > + int ret; > + ret = write(fh, &fm[frba.reg2_base >> 2], frba.reg2_limit); > + if (ret != frba.reg2_limit) > + { > + printf("FAILED.\n"); > + exit(1); > + } > + > + printf("done.\n"); > + > + close(fh); > +} > + > +void dump_file_GbE(char * fn) > +{ > + char * n = malloc(strlen(fn) + 9); > + snprintf(n, strlen(fn) + 9, "%s.GbE.bin", fn); > + printf("\n"); > + printf("+++ dumping %s ... ", n); > + int fh = open(n, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); > + free(n); > + if (fh < 0) > + { > + printf("ERROR: couldn't open(%s): %s\n", n, strerror(errno)); > + exit(1); > + } > + > + int ret; > + ret = write(fh, &fm[frba.reg3_base >> 2], frba.reg3_limit); > + if (ret != frba.reg3_limit) > + { > + printf("FAILED.\n"); > + exit(1); > + } > + > + printf("done.\n"); > + uint8_t * pMAC = (uint8_t *) &fm[frba.reg3_base >> 2]; > + printf("the MAC-address might be: %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n", > + pMAC[0], > + pMAC[1], > + pMAC[2], > + pMAC[3], > + pMAC[4], > + pMAC[5] > + ); > + > + close(fh); > +} > + > +void dump_files(char * n) > +{ > + printf("=== dumping section files ===\n"); > + if (frba.reg0_limit) > + dump_file_descriptor(n); > + if (frba.reg1_limit) > + dump_file_BIOS(n); > + if (frba.reg2_limit) > + dump_file_ME(n); > + if (frba.reg3_limit) > + dump_file_GbE(n); > +} > + > +void usage(char ** argv, char* error) > +{ > + printf("%s\n", error); > + printf("\n"); > + printf("usage: '%s <bios image file> [-d]'\n", argv[0]); > + printf("\n"); > + printf("\twhere <bios image file> isn't actually a BIOS image, but the SPI flash\n"); > + printf("\tcontents of the SPI connected to your intel chipset.\n"); > + printf("\tIn case that image is really in descriptor mode (a.k.a soft-strap)\n"); > + printf("\t%s will pretty print all relevant information.\n", argv[0]); > + printf("\tIf '-d' is specified as the second parameter some sections such as\n"); > + printf("\tthe real BIOS image as seen by the CPU or a GbE blob that is\n"); > + printf("\trequired to initialize your ICH GbE are also dumped to files.\n"); > + exit(1); > +} > + > +int main(int argc, char **argv) > +{ > + if (argc < 2) > + usage(argv, "Need at least one parameter"); > + f = open(argv[1], O_RDONLY); > + if (f < 0) > + usage(argv, "No such file"); > + if (argc >= 3 && (strcmp("-d", argv[2]) == 0)) > + usage(argv, "Bogus second argument"); > + > + fs = lseek(f, 0, SEEK_END); > + if (fs < 0) > + usage(argv, "Seeking to the end of the file failed"); > + > + fm = mmap(NULL, fs, PROT_READ, MAP_PRIVATE, f, 0); > + if (fm == (void *) -1) > + { > + /* fallback for stupid OSes like cygwin */ > + int ret; > + fm = malloc(fs); > + if (!fm) > + usage(argv, "Could not allocate memory"); > + lseek(f, 0, SEEK_SET); > + ret = read(f, fm, fs); > + if (ret != fs) > + usage(argv, "Seeking to the end of the file failed"); > + } > + printf("flash image is %d [0x%x] bytes\n", fs, fs); > + close(f); > + > + if(read_ich_descriptors_from_dump(fm)){ > + printf("not in descriptor mode\n"); > + exit(1); > + } > + > + pretty_print_ich_descriptors(); > + > + if (argc >= 3) > + dump_files(argv[1]); > + > + return 0; > +} > + > Regards, Carl-Daniel -- http://www.hailfinger.org/

3 4

Re: [flashrom] [PATCH] fix the ASUS A8N-VM CSM board enable
by Joshua Roys 20 Jul '11

20 Jul '11

On 07/20/2011 08:39 AM, Stefan Tauner wrote: > apparantly based on joshua's work, see: > http://www.flashrom.org/pipermail/flashrom/2011-June/007015.html > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Joshua Roys <roysjosh(a)gmail.com> > --- > board_enable.c | 8 ++++---- > 1 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/board_enable.c b/board_enable.c > index dc457a0..ffa522a 100644 > --- a/board_enable.c > +++ b/board_enable.c > @@ -334,14 +334,14 @@ static int w83627hf_gpio25_raise_2e(void) > } > > /* > - * Winbond W83627EHF: Raise GPIO24. > + * Winbond W83627EHF: Raise GPIO22. > * > * Suited for: > * - ASUS A8N-VM CSM: AMD Socket 939 + GeForce 6150 (C51) + MCP51 > */ > -static int w83627ehf_gpio24_raise_2e(void) > +static int w83627ehf_gpio22_raise_2e(void) > { > - return winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, 24, 1); > + return winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, 22, 1); > } > > /* > @@ -2002,7 +2002,7 @@ const struct board_pciid_enable board_pciid_enables[] = { > {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, P3, "ASUS", "A8Jm", 0, NT, intel_ich_gpio34_raise}, > {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI2L", NULL, NULL, P3, "ASUS", "A8N-LA (Nagami-GL8E)", 0, OK, nvidia_mcp_gpio0_raise}, > {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, "^A8N-SLI", NULL, NULL, P3, "ASUS", "A8N-SLI Deluxe", 0, NT, board_shuttle_fn25}, > - {0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, P3, "ASUS", "A8N-VM CSM", 0, NT, w83627ehf_gpio24_raise_2e}, > + {0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, P3, "ASUS", "A8N-VM CSM", 0, OK, w83627ehf_gpio22_raise_2e}, > {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, P3, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise}, > {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, P3, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise}, > {0x8086, 0x24cc, 0, 0, 0x8086, 0x24c3, 0x1043, 0x1869, "^M6Ne$", NULL, NULL, P3, "ASUS", "M6Ne", 0, NT, intel_ich_gpio43_raise},

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