- flashrom - mail.coreboot.org

Re: [flashrom] [PATCH 3/3] an obvious but dubios refactor opportunity
by Tadas Slotkus 15 Aug '11

15 Aug '11

> diff --git a/layout.c b/layout.c > index 8283e36..fe29852 100644 > --- a/layout.c > +++ b/layout.c > @@ -240,6 +240,19 @@ static struct rom_entry *get_next_included_romentry(unsigned int start) > return best_entry; > } > > +static void copy_old_content(struct flashchip *flash, int oldcontents_valid, uint8_t *oldcontents, uint8_t *newcontents, unsigned int start, unsigned int size) Could you split it to multiple lines? Nice work! :) Acked-by: Tadas Slotkus <devtadas(a)gmail.com> Thanks, Tadas

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Re: [flashrom] [PATCH 2/3] Make read before write configurable (infrastructure part)
by Tadas Slotkus 15 Aug '11

15 Aug '11

> @@ -1961,11 +1961,13 @@ int doit(struct flashchip *flash, int force, const char *filename, int read_it, > ret = 1; > goto out; > } > - } > - emergency_help_message(); > - ret = 1; > - goto out; > - } > + } else Could you kill that last curly bracket? :) Acked-by: Tadas Slotkus <devtadas(a)gmail.com>

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wiki output
by Stefan Tauner 14 Aug '11

14 Aug '11

i'd like to improve the wiki output. first of all i'd like to get the voltage printing of chips in. after that i would like to add support for linked footnotes, because our tables are long and right now the user has to scroll a lot to read them. i think those two things are not controversial, so we can discuss them when i am sending the patches (voltage printing has already been posted a few weeks ago actually). the other thing i want to do is to improve the list of supported mainboards. right now - we don't differentiate between revisions (besides adding them to the name as string). - we can't distinguish between not supported at all and untested board enable (we use the note field for this). - we try to link to the vendor... which fails more often than it works over the time imho. i presume the most problematic thing is removal of the urls. basically i don't care if support for them remains, but i will stop adding them myself. it is just a waste of time imho because they change so often or the targets just vanish. if i can persuade all of you to think that too, it would be even better. so... i don't see the reason we do this at all (besides the obvious hypertext argument that one should link as much as possible). i doubt any user will follow those links to find "his" board. why should s/he? what's the use case for those links? carldani replied "identification of supported revisions" (more or less). this is a bogus argument. the URLs don't do that now, and in most of the cases they can't (because there is only one single page for multiple revisions or even models). anyway, we should not be divided by this particular detail, so now to the really important stuff. i'd like to add a ? "icon" to boards with untested board enables (just like we do everywhere else if we are not sure yet). this would require extending the "working" field of struct board_info and using OK, NT and a to-be-defined third macro instead of just 0 and 1 in the table itself (or, an enum... much preferred solution by me). quite easy stuff. then i had the idea to somehow add board revisions more explicitly. just adding additional columns like it is done for the chip statuses won't cut it, because we need to fit the names of the revisions in there too. but maybe it is enough nonetheless: what about - adding n columns where n is the maximum number of revisions of a single board, and - in each column we print the revision name followed by OK, No, or ?; or nothing if there are less revisions to support this we would need to expand the existing struct and macros, but it is doable imho. other ideas are welcome. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[PATCH] Always read chip before writing, avoid emergency messages
by Carl-Daniel Hailfinger 14 Aug '11

14 Aug '11

Always read the flash chip before writing. This will allow flashrom to skip erase of already-erased blocks and to skip write of blocks which already have the wanted contents. Avoid emergency messages by checking if the chip contents after a failed write operation (erase/write) are unchanged. Keep the emergency messages after a failed pure erase. That part is debatable because if someone wants erase, he pretty sure doesn't care about the flash contents anymore. Please note that this introduces additional overhead of a full chip read before write. This is frowned upon by people with slow programmers. Maybe we should make this configurable. Either way, this patch needs a review to make sure I'm not going in the wrong direction. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-always_read_no_scary_warning/flash.h =================================================================== --- flashrom-always_read_no_scary_warning/flash.h (Revision 1212) +++ flashrom-always_read_no_scary_warning/flash.h (Arbeitskopie) @@ -239,7 +239,7 @@ /* layout.c */ int read_romlayout(char *name); int find_romentry(char *name); -int handle_romentries(uint8_t *buffer, struct flashchip *flash); +int handle_romentries(struct flashchip *flash, uint8_t *oldcontents, uint8_t *newcontents); /* spi.c */ struct spi_command { Index: flashrom-always_read_no_scary_warning/layout.c =================================================================== --- flashrom-always_read_no_scary_warning/layout.c (Revision 1212) +++ flashrom-always_read_no_scary_warning/layout.c (Arbeitskopie) @@ -205,7 +205,7 @@ return -1; } -int handle_romentries(uint8_t *buffer, struct flashchip *flash) +int handle_romentries(struct flashchip *flash, uint8_t *oldcontents, uint8_t *newcontents) { int i; @@ -225,13 +225,12 @@ // normal will be updated and the rest will be kept. for (i = 0; i < romimages; i++) { - if (rom_entries[i].included) continue; - flash->read(flash, buffer + rom_entries[i].start, - rom_entries[i].start, - rom_entries[i].end - rom_entries[i].start + 1); + memcpy(newcontents + rom_entries[i].start, + oldcontents + rom_entries[i].start, + rom_entries[i].end - rom_entries[i].start + 1); } return 0; Index: flashrom-always_read_no_scary_warning/flashrom.c =================================================================== --- flashrom-always_read_no_scary_warning/flashrom.c (Revision 1212) +++ flashrom-always_read_no_scary_warning/flashrom.c (Arbeitskopie) @@ -1343,6 +1343,19 @@ return ret; } +void nonfatal_help_message(void) +{ + msg_gerr("Writing to the flash chip apparently didn't do anything.\n" + "This means we have to add special support for your board, " + "programmer or flash chip.\n" + "Please report this on IRC at irc.freenode.net (channel " + "#flashrom) or\n" + "mail flashrom(a)flashrom.org!\n" + "-------------------------------------------------------------" + "------------------\n" + "You may now reboot or simply leave the machine running.\n"); +} + void emergency_help_message(void) { msg_gerr("Your flash chip is in an unknown state.\n" @@ -1602,9 +1615,10 @@ */ int doit(struct flashchip *flash, int force, char *filename, int read_it, int write_it, int erase_it, int verify_it) { - uint8_t *buf; + uint8_t *oldcontents; + uint8_t *newcontents; int ret = 0; - unsigned long size; + unsigned long size = flash->total_size * 1024; if (chip_safety_check(flash, force, filename, read_it, write_it, erase_it, verify_it)) { msg_cerr("Aborting.\n"); @@ -1612,9 +1626,6 @@ return 1; } - size = flash->total_size * 1024; - buf = (uint8_t *) calloc(size, sizeof(char)); - /* Given the existence of read locks, we want to unlock for read, * erase and write. */ @@ -1627,6 +1638,12 @@ return ret; } if (erase_it) { + /* FIXME: Do we really want the scary warning if erase failed? + * After all, after erase the chip is either blank or partially + * blank or it has the old contents. A blank chip won't boot, + * so if the user wanted erase and reboots afterwards, the user + * knows very well that booting won't work. + */ if (erase_flash(flash)) { emergency_help_message(); programmer_shutdown(); @@ -1634,33 +1651,71 @@ } } + newcontents = (uint8_t *) calloc(size, sizeof(char)); + if (write_it || verify_it) { - if (read_buf_from_file(buf, flash->total_size * 1024, filename)) { + if (read_buf_from_file(newcontents, size, filename)) { programmer_shutdown(); return 1; } #if CONFIG_INTERNAL == 1 - show_id(buf, size, force); + if (programmer == PROGRAMMER_INTERNAL) + show_id(newcontents, size, force); #endif } + oldcontents = (uint8_t *) calloc(size, sizeof(char)); + + /* Read the whole chip to be able to check whether regions need to be + * erased and to give better diagnostics in case write fails. + * The alternative would be to read only the regions which are to be + * preserved, but in that case we might perform unneeded erase which + * takes time as well. + */ + msg_cdbg("Reading old flash chip contents...\n"); + if (flash->read(flash, oldcontents, 0, size)) { + programmer_shutdown(); + return 1; + } + // This should be moved into each flash part's code to do it // cleanly. This does the job. - handle_romentries(buf, flash); + handle_romentries(flash, oldcontents, newcontents); // //////////////////////////////////////////////////////////// if (write_it) { if (erase_flash(flash)) { + msg_cerr("Uh oh. Erase failed. Checking if anything " + "changed.\n"); + if (!flash->read(flash, newcontents, 0, size)) { + if (!memcmp(oldcontents, newcontents, size)) { + msg_cinfo("Good. It seems nothing was " + "changed.\n"); + nonfatal_help_message(); + programmer_shutdown(); + return 1; + } + } emergency_help_message(); programmer_shutdown(); return 1; } msg_cinfo("Writing flash chip... "); - ret = flash->write(flash, buf, 0, flash->total_size * 1024); + ret = flash->write(flash, newcontents, 0, size); if (ret) { - msg_cerr("FAILED!\n"); + msg_cerr("Uh oh. Write failed. Checking if anything " + "changed.\n"); + if (!flash->read(flash, newcontents, 0, size)) { + if (!memcmp(oldcontents, newcontents, size)) { + msg_cinfo("Good. It seems nothing was " + "changed.\n"); + nonfatal_help_message(); + programmer_shutdown(); + return 1; + } + } emergency_help_message(); programmer_shutdown(); return 1; @@ -1673,7 +1728,7 @@ /* Work around chips which need some time to calm down. */ if (write_it) programmer_delay(1000*1000); - ret = verify_flash(flash, buf); + ret = verify_flash(flash, newcontents); /* If we tried to write, and verification now fails, we * might have an emergency situation. */ -- http://www.hailfinger.org/

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HP Pavilion dv6-6030er
by pol kh 14 Aug '11

14 Aug '11

# flashrom -VV flashrom v0.9.4-r1394 on Linux 2.6.39-2-amd64 (x86_64), built with libpci 3.1.7, GCC 4.6.1 20110616 (prerelease), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 959M loops per second, 10 myus = 10 us, 100 myus = 116 us, 1000 myus = 1085 us, 10000 myus = 10240 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Hewlett-Packard" DMI string system-product-name: "HP Pavilion dv6 Notebook PC" DMI string system-version: "0596100000244710000010100" DMI string baseboard-manufacturer: "Hewlett-Packard" DMI string baseboard-product-name: "164B" DMI string baseboard-version: "06.1F" DMI string chassis-type: "Notebook" Laptop detected via DMI. Found ITE EC, ID 0x8518,Rev 0x02 on port 0x4e. ======================================================================== WARNING! You seem to be running flashrom on an unsupported laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Aborting. # flashrom -VV -r 01649F20.bin flashrom v0.9.4-r1394 on Linux 2.6.39-2-amd64 (x86_64), built with libpci 3.1.7, GCC 4.6.1 20110616 (prerelease), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 997M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1000 us, 10000 myus = 10005 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Hewlett-Packard" DMI string system-product-name: "HP Pavilion dv6 Notebook PC" DMI string system-version: "0596100000244710000010100" DMI string baseboard-manufacturer: "Hewlett-Packard" DMI string baseboard-product-name: "164B" DMI string baseboard-version: "06.1F" DMI string chassis-type: "Notebook" Laptop detected via DMI. Found ITE EC, ID 0x8518,Rev 0x02 on port 0x4e. ======================================================================== WARNING! You seem to be running flashrom on an unsupported laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Aborting. # lspci -nnvvvxxx 00:00.0 Host bridge [0600]: Advanced Micro Devices [AMD] RS880 Host Bridge [1022:9601] Subsystem: Advanced Micro Devices [AMD] Device [1022:1234] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx- Latency: 0 Capabilities: [c4] HyperTransport: Slave or Primary Interface Command: BaseUnitID=0 UnitCnt=12 MastHost- DefDir- DUL- Link Control 0: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 0: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Link Control 1: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 1: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 3.00 Link Frequency 0: [a] Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 0: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC- LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- Link Frequency 1: 200MHz Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 1: 200MHz- 300MHz- 400MHz- 500MHz- 600MHz- 800MHz- 1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend- Error Handling: PFlE- OFlE- PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE+ PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE- Prefetchable memory behind bridge Upper: 00-00 Bus Number: 00 Capabilities: [54] HyperTransport: UnitID Clumping Capabilities: [40] HyperTransport: Retry Mode Capabilities: [9c] HyperTransport: #1a Capabilities: [f8] HyperTransport: #1c 00: 22 10 01 96 06 00 30 22 00 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 34 12 30: 00 00 00 00 c4 00 00 00 00 00 00 00 00 00 00 00 40: 08 9c 00 c0 c1 00 00 00 56 00 00 00 42 20 05 00 50: 22 10 34 12 08 40 00 90 08 10 05 00 00 00 05 00 60: 00 00 00 00 8e 00 00 00 00 02 20 00 0f 80 86 81 70: 00 00 00 00 00 00 00 00 ad 00 01 11 00 00 00 20 80: 00 00 00 00 10 00 06 03 20 c8 00 00 13 26 00 10 90: 00 00 00 d0 3d 01 00 00 47 00 00 00 08 f8 7c d0 a0: 26 00 66 00 00 00 00 82 00 00 00 00 79 01 c0 07 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 80 08 54 80 01 20 00 11 00 d0 00 00 00 d0: 60 0a 75 1e 02 00 00 00 00 00 00 02 00 00 00 00 e0: 00 00 00 00 ff ff ff ff 0d 02 00 00 64 40 05 00 f0: 00 00 00 00 01 00 00 00 08 00 00 e0 00 00 00 00 00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] RS780/RS880 PCI to PCI bridge (int gfx) [1022:9602] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 00004000-00004fff Memory behind bridge: f0500000-f06fffff Prefetchable memory behind bridge: 00000000d0000000-00000000dfffffff Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA+ MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [44] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] Device [1022:1235] 00: 22 10 02 96 07 00 30 02 00 00 04 06 00 40 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 41 41 20 02 20: 50 f0 60 f0 01 d0 f1 df 00 00 00 00 00 00 00 00 30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 00 08 00 40: 00 00 00 00 08 b0 03 a8 00 00 00 00 22 10 35 12 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 0d 00 00 00 22 10 35 12 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:03.0 PCI bridge [0604]: Advanced Micro Devices [AMD] RS780 PCI to PCI bridge (ext gfx port 1) [1022:960b] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 I/O behind bridge: 00003000-00003fff Memory behind bridge: f0400000-f04fffff Prefetchable memory behind bridge: 00000000e0000000-00000000efffffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #1, Speed 5GT/s, Width x8, ASPM L0s L1, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt+ SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Slot #3, PowerLimit 75.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Not Supported, TimeoutDis- ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0300c Data: 4161 Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] Device [1022:1234] Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [110 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Kernel driver in use: pcieport 00: 22 10 0b 96 07 04 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 02 02 00 31 31 00 20 20: 40 f0 40 f0 01 e0 f1 ef 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 03 c8 00 00 00 00 10 a0 42 01 20 80 00 00 60: 10 08 00 00 82 0c 30 01 43 00 82 f0 e0 25 1c 00 70: 00 00 48 01 00 00 01 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 42 00 01 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 b0 01 00 0c 30 e0 fe 61 41 00 00 00 00 00 00 b0: 0d b8 00 00 22 10 34 12 08 00 03 a8 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 ff ff ff ff 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:04.0 PCI bridge [0604]: Advanced Micro Devices [AMD] RS780 PCI to PCI bridge (PCIE port 0) [1022:9604] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=03, subordinate=03, sec-latency=0 I/O behind bridge: 00002000-00002fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: 00000000f0000000-00000000f00fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #1, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #4, PowerLimit 25.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Not Supported, TimeoutDis- ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0300c Data: 4169 Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] Device [1022:1234] Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [110 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Kernel driver in use: pcieport 00: 22 10 04 96 07 04 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 03 03 00 21 21 00 00 20: f0 ff 00 00 01 f0 01 f0 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 03 c8 00 00 00 00 10 a0 42 01 20 80 00 00 60: 10 08 00 00 12 0c 30 01 40 00 11 70 80 0c 24 00 70: 00 00 48 01 00 00 01 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 42 00 01 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 b0 01 00 0c 30 e0 fe 69 41 00 00 00 00 00 00 b0: 0d b8 00 00 22 10 34 12 08 00 03 a8 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 ff ff ff ff 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:05.0 PCI bridge [0604]: Advanced Micro Devices [AMD] RS780 PCI to PCI bridge (PCIE port 1) [1022:9605] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=04, subordinate=04, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: f0300000-f03fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #2, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #5, PowerLimit 25.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Not Supported, TimeoutDis- ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0300c Data: 4171 Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] Device [1022:1234] Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [110 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Kernel driver in use: pcieport 00: 22 10 05 96 07 04 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 04 04 00 f1 01 00 20 20: 30 f0 30 f0 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 03 c8 00 00 00 00 10 a0 42 01 20 80 00 00 60: 10 08 00 00 12 0c 30 02 40 00 11 70 80 0c 2c 00 70: 00 00 48 01 00 00 01 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 42 00 01 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 b0 01 00 0c 30 e0 fe 71 41 00 00 00 00 00 00 b0: 0d b8 00 00 22 10 34 12 08 00 03 a8 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 ff ff ff ff 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:06.0 PCI bridge [0604]: Advanced Micro Devices [AMD] RS780 PCI to PCI bridge (PCIE port 2) [1022:9606] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=05, subordinate=05, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: f0200000-f02fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #3, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #6, PowerLimit 25.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Not Supported, TimeoutDis- ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0300c Data: 4179 Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] Device [1022:1234] Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [110 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Kernel driver in use: pcieport 00: 22 10 06 96 07 04 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 05 05 00 f1 01 00 20 20: 20 f0 20 f0 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 03 c8 00 00 00 00 10 a0 42 01 20 80 00 00 60: 10 08 00 00 12 0c 30 03 40 00 11 70 80 0c 34 00 70: 00 00 48 01 00 00 01 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 42 00 01 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 b0 01 00 0c 30 e0 fe 79 41 00 00 00 00 00 00 b0: 0d b8 00 00 22 10 34 12 08 00 03 a8 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 ff ff ff ff 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:07.0 PCI bridge [0604]: Advanced Micro Devices [AMD] RS780 PCI to PCI bridge (PCIE port 3) [1022:9607] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=06, subordinate=06, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: f0100000-f01fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #4, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt+ SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #7, PowerLimit 25.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Not Supported, TimeoutDis- ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0300c Data: 4181 Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] Device [1022:1234] Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [110 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Kernel driver in use: pcieport 00: 22 10 07 96 07 04 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 06 06 00 f1 01 00 20 20: 10 f0 10 f0 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 03 c8 00 00 00 00 10 a0 42 01 20 80 00 00 60: 10 08 00 00 12 0c 30 04 43 00 12 f0 80 0c 3c 00 70: 00 00 48 01 00 00 01 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 42 00 01 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 b0 01 00 0c 30 e0 fe 81 41 00 00 00 00 00 00 b0: 0d b8 00 00 22 10 34 12 08 00 03 a8 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 ff ff ff ff 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:11.0 SATA controller [0106]: ATI Technologies Inc SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] [1002:4391] (prog-if 01 [AHCI 1.0]) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 19 Region 0: I/O ports at 5038 [size=8] Region 1: I/O ports at 504c [size=4] Region 2: I/O ports at 5030 [size=8] Region 3: I/O ports at 5048 [size=4] Region 4: I/O ports at 5010 [size=16] Region 5: Memory at f070a000 (32-bit, non-prefetchable) [size=1K] Capabilities: [70] SATA HBA v1.0 InCfgSpace Capabilities: [a4] PCI Advanced Features AFCap: TP+ FLR+ AFCtrl: FLR- AFStatus: TP- Kernel driver in use: ahci 00: 02 10 91 43 07 00 30 02 00 01 06 01 10 40 00 00 10: 39 50 00 00 4d 50 00 00 31 50 00 00 49 50 00 00 20: 11 50 00 00 00 a0 70 f0 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 70 00 00 00 00 00 00 00 0b 01 00 00 40: 14 80 b5 00 01 00 20 00 00 00 80 00 00 00 00 00 50: 05 70 84 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 01 50 22 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 12 a4 10 00 0f 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 06 16 14 00 ab 01 08 00 f0 00 00 00 90: 27 60 74 c7 02 45 06 00 08 01 00 00 01 58 11 00 a0: 0c 00 00 00 13 00 06 03 00 00 64 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 20 00 00 e0: 80 00 00 00 00 00 00 00 00 00 00 00 10 00 00 3f f0: 00 00 00 00 00 00 00 00 77 77 77 00 00 00 00 00 00:12.0 USB Controller [0c03]: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397] (prog-if 10 [OHCI]) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 18 Region 0: Memory at f0709000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci_hcd 00: 02 10 97 43 17 00 a0 02 00 10 03 0c 10 40 80 00 10: 00 90 70 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 01 00 00 40: 80 01 00 f0 11 00 00 00 00 00 00 00 00 00 00 00 50: 40 00 00 f0 00 00 00 00 ff ff ff ff 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 ff 00 00 80 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 10 01 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:12.2 USB Controller [0c03]: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396] (prog-if 20 [EHCI]) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin B routed to IRQ 17 Region 0: Memory at f0708000 (32-bit, non-prefetchable) [size=256] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME+ Bridge: PM- B3+ Capabilities: [e4] Debug port: BAR=1 offset=00e0 Kernel driver in use: ehci_hcd 00: 02 10 96 43 17 00 b0 02 00 20 03 0c 10 40 00 00 10: 00 80 70 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 c0 00 00 00 00 00 00 00 05 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 40 21 80 a0 01 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 20 00 00 01 00 00 00 00 00 00 00 00 a0: 01 00 00 01 00 00 08 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 e4 02 7e 00 80 40 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 0a 00 e0 20 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:13.0 USB Controller [0c03]: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397] (prog-if 10 [OHCI]) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 18 Region 0: Memory at f0707000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci_hcd 00: 02 10 97 43 17 00 a0 02 00 10 03 0c 10 40 80 00 10: 00 70 70 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 01 00 00 40: 80 01 00 f0 11 00 00 00 00 00 00 00 00 00 00 00 50: 40 00 00 f0 00 00 00 00 ff ff ff ff 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 ff 00 00 80 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 10 01 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:13.2 USB Controller [0c03]: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396] (prog-if 20 [EHCI]) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin B routed to IRQ 17 Region 0: Memory at f0706000 (32-bit, non-prefetchable) [size=256] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME+ Bridge: PM- B3+ Capabilities: [e4] Debug port: BAR=1 offset=00e0 Kernel driver in use: ehci_hcd 00: 02 10 96 43 17 00 b0 02 00 20 03 0c 10 40 00 00 10: 00 60 70 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 c0 00 00 00 00 00 00 00 05 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 40 21 80 a0 01 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 20 00 00 01 00 00 00 00 00 00 00 00 a0: 01 00 00 01 00 00 08 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 e4 02 7e 00 80 40 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 0a 00 e0 20 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.0 SMBus [0c05]: ATI Technologies Inc SBx00 SMBus Controller [1002:4385] (rev 42) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Kernel driver in use: piix4_smbus 00: 02 10 85 43 03 04 20 02 42 00 05 0c 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.2 Audio device [0403]: ATI Technologies Inc SBx00 Azalia (Intel HDA) [1002:4383] (rev 40) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=slow >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 16 Region 0: Memory at f0700000 (64-bit, non-prefetchable) [size=16K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=55mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: HDA Intel 00: 02 10 83 43 06 00 10 04 40 00 03 04 10 40 00 00 10: 04 00 70 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 50 00 00 00 00 00 00 00 07 01 00 00 40: 00 00 02 00 01 10 00 00 00 00 00 00 01 00 00 00 50: 01 00 42 c8 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.3 ISA bridge [0601]: ATI Technologies Inc SB7x0/SB8x0/SB9x0 LPC host controller [1002:439d] (rev 40) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 00: 02 10 9d 43 0f 00 20 02 40 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 04 00 00 00 d5 ff 03 ff 07 ff 20 01 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 0e 68 00 00 00 0f 00 e0 ff ff ff 70: 67 45 23 00 04 00 00 00 1c 00 00 00 05 0a 00 00 80: 08 00 03 a8 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 10 d6 fe a0: 02 00 c1 fe 2e 01 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 09 39 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.4 PCI bridge [0604]: ATI Technologies Inc SBx00 PCI to PCI Bridge [1002:4384] (rev 40) (prog-if 01 [Subtractive decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 Bus: primary=00, secondary=07, subordinate=07, sec-latency=64 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: fff00000-000fffff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 00: 02 10 84 43 07 01 a0 02 40 01 04 06 00 40 81 00 10: 00 00 00 00 00 00 00 00 00 07 07 40 f0 00 80 22 20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 40: 26 00 00 ff 00 00 00 00 0c 0f 3c d1 00 00 00 00 50: 01 00 00 00 08 00 03 a8 00 00 00 00 85 00 ff ff 60: ca 0e 17 00 ba 98 10 02 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 02 06 e0: 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:16.0 USB Controller [0c03]: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397] (prog-if 10 [OHCI]) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 18 Region 0: Memory at f0705000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci_hcd 00: 02 10 97 43 17 00 a0 02 00 10 03 0c 10 40 80 00 10: 00 50 70 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 01 00 00 40: 80 01 00 f0 11 00 00 00 00 00 00 00 00 00 00 00 50: 40 00 00 f0 00 00 00 00 ff ff ff ff 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 ff 00 00 80 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 10 01 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:16.2 USB Controller [0c03]: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396] (prog-if 20 [EHCI]) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin B routed to IRQ 17 Region 0: Memory at f0704000 (32-bit, non-prefetchable) [size=256] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Bridge: PM- B3+ Capabilities: [e4] Debug port: BAR=1 offset=00e0 Kernel driver in use: ehci_hcd 00: 02 10 96 43 17 00 b0 02 00 20 03 0c 10 40 00 00 10: 00 40 70 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 c0 00 00 00 00 00 00 00 05 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 40 21 80 a0 01 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 20 00 00 01 00 00 00 00 00 00 00 00 a0: 01 00 00 01 00 00 08 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 e4 02 7e 00 00 40 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 0a 00 e0 20 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor HyperTransport Configuration [1022:1200] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn+ ExtCTL- 64b+ Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 3.00 Link Frequency: [a] Link Error: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz+ 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA+ UIDRD- ExtRS- UCnfE- 00: 22 10 00 12 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 01 02 04 00 01 02 04 00 01 02 04 00 01 02 04 00 50: 01 02 04 00 01 02 04 00 01 02 04 00 01 02 04 00 60: 00 00 01 00 e0 00 00 00 20 a8 2e 01 10 fe 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 00 01 21 20 a0 11 00 60 0a f5 87 13 00 00 00 90: d0 02 85 80 00 00 00 00 07 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.1 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor Address Map [1022:1201] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 01 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 03 00 00 00 00 00 2f 01 00 00 00 00 01 00 00 00 50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00 60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00 70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00 80: 03 00 d0 00 80 ff df 00 03 00 e0 00 00 4f f0 00 90: 03 50 f0 00 80 6f f0 00 03 70 f0 00 00 ff f7 00 a0: 03 00 f8 00 80 ff fb 00 03 00 fc 00 00 bf fe 00 b0: 03 c0 fe 00 80 fe ff 00 03 ff ff 00 00 ff ff 00 c0: 13 00 00 00 00 f0 ff 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 03 00 00 1f 00 00 00 00 00 00 00 00 00 00 00 00 f0: 03 30 00 d0 01 00 00 00 00 00 00 00 00 00 00 00 00:18.2 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor DRAM Controller [1022:1202] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 02 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 04 00 00 0a 00 00 00 00 80: 00 00 00 00 04 00 00 00 00 00 00 ff 00 00 00 00 90: 00 00 01 08 00 41 08 00 0a 00 00 80 e7 88 71 0e a0: 00 02 00 00 00 00 00 00 00 00 01 00 00 00 00 00 b0: 5c 6b 78 84 6b 00 00 00 80 2e f0 07 01 f8 80 36 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: ef 00 10 fb 1f 97 3b 17 fd 00 00 21 33 02 e0 02 e0: 54 7c c4 f1 02 02 a0 f8 1c 01 f0 7d ff 57 26 9b f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.3 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor Miscellaneous Control [1022:1203] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [f0] Secure device <?> Kernel driver in use: k10temp 00: 22 10 03 12 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 00 40: ff ff ff 3f 5c 00 b0 4a 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 05 00 73 3a c0 00 00 30 51 80 01 60 70: 51 11 32 60 01 01 98 00 14 0c 20 00 11 08 07 00 80: 81 f6 0b e6 e6 41 e6 01 08 00 00 00 00 60 58 02 90: 43 00 00 00 60 00 00 00 00 18 18 01 00 00 00 00 a0: a9 0a 19 b0 ef 0f 68 39 70 07 04 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 c6 10 04 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 25 0f 81 c8 15 07 3b 03 45 54 27 70 e0: 00 00 00 00 30 06 40 01 41 5f 07 00 00 00 00 00 f0: 0f 00 10 00 00 00 00 00 00 00 00 00 63 0f 10 00 00:18.4 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor Link Control [1022:1204] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 04 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:05.0 VGA compatible controller [0300]: ATI Technologies Inc M880G [Mobility Radeon HD 4200] [1002:9712] (prog-if 00 [VGA controller]) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 18 Region 0: Memory at d0000000 (32-bit, prefetchable) [size=256M] Region 1: I/O ports at 4000 [size=256] Region 2: Memory at f0600000 (32-bit, non-prefetchable) [size=64K] Region 5: Memory at f0500000 (32-bit, non-prefetchable) [size=1M] Expansion ROM at <unassigned> [disabled] Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Kernel driver in use: fglrx_pci 00: 02 10 12 97 07 00 10 00 00 00 00 03 10 00 80 00 10: 08 00 00 d0 01 40 00 00 00 00 60 f0 00 00 00 00 20: 00 00 00 00 00 00 50 f0 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 50: 01 a0 03 06 00 00 00 00 10 a0 12 00 a0 8f 00 00 60: 10 08 0a 00 01 0d 00 00 00 00 01 11 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 01 00 01 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:05.1 Audio device [0403]: ATI Technologies Inc RS880 Audio Device [Radeon HD 4200] [1002:970f] Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin B routed to IRQ 19 Region 0: Memory at f0610000 (32-bit, non-prefetchable) [size=16K] Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Kernel driver in use: HDA Intel 00: 02 10 0f 97 07 00 10 00 00 00 03 04 10 00 80 00 10: 00 00 61 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 50: 01 a0 03 06 00 00 00 00 10 a0 12 00 a0 8f 00 00 60: 10 08 0a 00 01 0d 00 00 00 00 01 11 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02:00.0 VGA compatible controller [0300]: ATI Technologies Inc NI Whistler [AMD Radeon HD 6600M Series] [1002:6741] (prog-if 00 [VGA controller]) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 49 Region 0: Memory at e0000000 (64-bit, prefetchable) [size=256M] Region 2: Memory at f0400000 (64-bit, non-prefetchable) [size=128K] Region 4: I/O ports at 3000 [size=256] [virtual] Expansion ROM at f0420000 [disabled] [size=128K] Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Legacy Endpoint, MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <4us, L1 unlimited ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #1, Speed 5GT/s, Width x16, ASPM L0s L1, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+ Address: 00000000fee0300c Data: 41a9 Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [150 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap+ ChkEn- Kernel driver in use: fglrx_pci 00: 02 10 41 67 07 04 10 00 00 00 00 03 10 00 00 00 10: 0c 00 00 e0 00 00 00 00 04 00 40 f0 00 00 00 00 20: 01 30 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 50: 01 58 03 06 00 00 00 00 10 a0 12 00 a1 8f 2c 01 60: 10 29 00 00 02 0d 00 01 43 00 82 10 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 02 00 01 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 00 81 00 0c 30 e0 fe 00 00 00 00 a9 41 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168] (rev 06) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 45 Region 0: I/O ports at 2000 [size=256] Region 2: Memory at f0004000 (64-bit, prefetchable) [size=4K] Region 4: Memory at f0000000 (64-bit, prefetchable) [size=16K] Capabilities: [40] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+ Address: 00000000fee0300c Data: 4189 Capabilities: [70] Express (v2) Endpoint, MSI 01 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 4096 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <64us ClockPM+ Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [b0] MSI-X: Enable- Count=4 Masked- Vector table: BAR=4 offset=00000000 PBA: BAR=4 offset=00000800 Capabilities: [d0] Vital Product Data Unknown small resource type 00, will not decode more. Capabilities: [100 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr+ BadTLP- BadDLLP+ Rollover- Timeout- NonFatalErr+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn- Capabilities: [140 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Capabilities: [160 v1] Device Serial Number 01-00-00-00-68-4c-e0-00 Kernel driver in use: r8169 00: ec 10 68 81 07 04 10 00 06 00 00 02 10 00 00 00 10: 01 20 00 00 00 00 00 00 0c 40 00 f0 00 00 00 00 20: 0c 00 00 f0 00 00 00 00 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 40 00 00 00 00 00 00 00 07 01 00 00 40: 01 50 c3 ff 08 00 00 00 00 00 00 00 00 00 00 00 50: 05 70 81 00 0c 30 e0 fe 00 00 00 00 89 41 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 10 b0 02 02 c1 8c 64 00 10 50 19 00 11 3c 07 00 80: 40 00 11 10 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 11 d0 03 00 04 00 00 00 04 08 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 03 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 04:00.0 Network controller [0280]: Ralink corp. Device [1814:539f] Subsystem: Hewlett-Packard Company Device [103c:1637] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 17 Region 0: Memory at f0300000 (32-bit, non-prefetchable) [size=64K] Capabilities: [40] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable- Count=1/32 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [70] Express (v2) Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 unlimited ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <64us ClockPM+ Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis+ LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [100 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ CEMsk: RxErr+ BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn- Capabilities: [140 v1] Device Serial Number 00-00-5a-8a-65-4e-00-90 Kernel driver in use: rt5390 00: 14 18 9f 53 07 00 10 00 00 00 80 02 10 00 00 00 10: 00 00 30 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 37 16 30: 00 00 00 00 40 00 00 00 00 00 00 00 05 01 00 00 40: 01 50 c3 01 00 00 00 00 00 00 00 00 00 00 00 00 50: 05 70 8a 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 10 00 02 00 c0 8e 64 00 10 20 09 00 11 3c 07 00 80: 40 00 11 10 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 10 00 00 00 10 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 05:00.0 Unassigned class [ff00]: Realtek Semiconductor Co., Ltd. Device [10ec:5209] (rev 01) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 18 Region 0: Memory at f0200000 (32-bit, non-prefetchable) [size=4K] Capabilities: [40] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [70] Express (v2) Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <1us, L1 <8us ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 unlimited, L1 <64us ClockPM+ Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [100 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout+ NonFatalErr+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn- Capabilities: [140 v1] Device Serial Number 00-00-00-01-00-4c-e0-00 Kernel driver in use: rts_pstor 00: ec 10 09 52 07 00 10 00 01 00 00 ff 10 00 00 00 10: 00 00 20 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 01 00 00 40: 01 50 c3 77 00 00 00 00 00 00 00 00 00 00 00 00 50: 05 70 80 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 10 00 02 00 00 87 64 00 10 20 09 00 11 7c 07 00 80: 00 01 11 10 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 06:00.0 USB Controller [0c03]: NEC Corporation uPD720200 USB 3.0 Host Controller [1033:0194] (rev 04) (prog-if 30 [XHCI]) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 19 Region 0: Memory at f0100000 (64-bit, non-prefetchable) [size=8K] Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [70] MSI: Enable- Count=1/8 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [90] MSI-X: Enable+ Count=8 Masked- Vector table: BAR=0 offset=00001000 PBA: BAR=0 offset=00001080 Capabilities: [a0] Express (v2) Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend- LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <4us, L1 unlimited ClockPM+ Surprise- LLActRep- BwNot- LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB Capabilities: [100 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- Capabilities: [140 v1] Device Serial Number ff-ff-ff-ff-ff-ff-ff-ff Capabilities: [150 v1] #18 Kernel driver in use: xhci_hcd 00: 33 10 94 01 06 04 10 00 04 30 03 0c 10 00 00 00 10: 04 00 10 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 70 c3 c9 08 00 00 00 00 00 00 00 00 00 00 00 60: 30 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 05 90 86 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 11 a0 07 80 00 10 00 00 80 10 00 00 00 00 00 00 a0: 10 00 02 00 c0 8f 00 00 00 28 19 00 12 ec 07 00 b0: 43 01 12 10 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 10 08 00 00 00 00 00 00 00 00 00 00 d0: 02 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: fc 1f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 08 14 60 00 00 00 00 00 00 00 00 00 00 00 00 00 # superiotool -deV superiotool r6637 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0x0001, id=0x1885 Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0x0001, id=0x1885 Probing for ITE Super I/O (init=standard) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0x8518, rev=0x2 Probing for ITE Super I/O (init=it8502e) at 0x4e... Failed. Returned data: id=0x8518, rev=0x2 Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0x8518, rev=0x2 Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0x8518, rev=0x2 Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0x8518, rev=0x2 Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: sid=0x85, srid=0x00 Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x164e... Failed. Returned data: port=0xff, port+1=0xff Probing for Nuvoton Super I/O at 0x164e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x2e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x4e... Failed. Returned data: chip_id=0x8518 Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e... Failed. Returned data: sid=0x85, id=0x8518, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Found SMSC SCH5317 (id=0x85, rev=0x18) at 0x4e No dump available for this Super I/O No extra registers known for this chip. Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0x85/0x00, rev=0x18 Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0x85/0x00, rev=0x18 Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0x85/0x00, rev=0x18 Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0x85/0x00, rev=0x18 Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for VIA Super I/O at 0x3f0... PCI device 1106:0686 not found. Probing for Server Engines Super I/O at 0x2e... Failed. Returned data: id=0xffff, rev=0xff # dmidecode # dmidecode 2.9 SMBIOS 2.6 present. 23 structures occupying 1205 bytes. Table at 0x000E3EE0. Handle 0x0000, DMI type 4, 42 bytes Processor Information Socket Designation: Socket S1G4 Type: Central Processor Family: <OUT OF SPEC> Manufacturer: AMD processor ID: 63 0F 10 00 FF FB 8B 17 Version: AMD Phenom(tm) II N660 Dual-Core Processor Voltage: 1.2 V External Clock: 200 MHz Max Speed: 3000 MHz Current Speed: 3000 MHz Status: Populated, Enabled Upgrade: <OUT OF SPEC> L1 Cache Handle: 0x0001 L2 Cache Handle: 0x0002 L3 Cache Handle: Not Provided Serial Number: NotSupport Asset Tag: FFFF Part Number: FFFF Core Count: 2 Core Enabled: 2 Thread Count: 2 Characteristics: 64-bit capable Handle 0x0001, DMI type 7, 19 bytes Cache Information Socket Designation: L1 Cache Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Write Back Location: Internal Installed Size: 256 KB Maximum Size: 256 KB Supported SRAM Types: Synchronous Installed SRAM Type: Synchronous Speed: Unknown Error Correction Type: Multi-bit ECC System Type: Unified Associativity: 2-way Set-associative Handle 0x0002, DMI type 7, 19 bytes Cache Information Socket Designation: L2 Cache Configuration: Enabled, Not Socketed, Level 2 Operational Mode: Write Back Location: Internal Installed Size: 2048 KB Maximum Size: 2048 KB Supported SRAM Types: Synchronous Installed SRAM Type: Synchronous Speed: Unknown Error Correction Type: Multi-bit ECC System Type: Unified Associativity: 16-way Set-associative Handle 0x0003, DMI type 0, 24 bytes BIOS Information Vendor: Hewlett-Packard Version: F.20 Release Date: 07/13/2011 ROM Size: 2048 kB Characteristics: PCI is supported BIOS is upgradeable BIOS shadowing is allowed Boot from CD is supported Selectable boot is supported BIOS ROM is socketed EDD is supported Japanese floppy for NEC 9800 1.2 MB is supported (int 13h) Japanese floppy for Toshiba 1.2 MB is supported (int 13h) 5.25"/360 KB floppy services are supported (int 13h) 5.25"/1.2 MB floppy services are supported (int 13h) 3.5"/720 KB floppy services are supported (int 13h) 3.5"/2.88 MB floppy services are supported (int 13h) 8042 keyboard services are supported (int 9h) CGA/mono video services are supported (int 10h) ACPI is supported USB legacy is supported Targeted content distribution is supported BIOS Revision: 15.32 Firmware Revision: 6.31 Handle 0x0004, DMI type 1, 27 bytes System Information Manufacturer: Hewlett-Packard Product Name: HP Pavilion dv6 Notebook PC Version: 0596100000244710000010100 Serial Number: 5CH1110E5K UUID: 4D7AD3D7-B40F-9D31-5273-68B599DFAFB0 Wake-up Type: Power Switch SKU Number: LK971EA#ACB Family: 103C_5335KV G=N L=CON B=HP S=PAV Handle 0x0005, DMI type 2, 16 bytes Base Board Information Manufacturer: Hewlett-Packard Product Name: 164B Version: 06.1F Serial Number: PBUME05HT031Y8 Asset Tag: Base Board Asset Tag Features: Board is a hosting board Board is replaceable Location In Chassis: Base Board Chassis Location Chassis Handle: 0x0006 Type: Motherboard Contained Object Handles: 0 Handle 0x0006, DMI type 3, 22 bytes Chassis Information Manufacturer: Hewlett-Packard Type: Notebook Lock: Not Present Version: Chassis Version Serial Number: Chassis Serial Number Asset Tag: Chassis Asset Tag Boot-up State: Safe Power Supply State: Safe Thermal State: Safe Security Status: None OEM Information: 0x00000147 Height: Unspecified Number Of Power Cords: 1 Contained Elements: 0 Handle 0x0007, DMI type 9, 17 bytes System Slot Information Designation: CN_WLAN1 Type: x1 <OUT OF SPEC> Current Usage: Available Length: Short Characteristics: 3.3 V is provided Handle 0x0008, DMI type 11, 5 bytes OEM Strings String 1: $HP$ String 2: LOC# String 3: ABS 70/71 78 79 7A 7B String 4: CNB1 0596100000244710000010100 String 5: HP_Mute_LED_0_0 Handle 0x0009, DMI type 22, 26 bytes Portable Battery Location: Primary Manufacturer: 13DP-SDI Name: MU06055 Chemistry: Lithium Ion Design Capacity: 165240 mWh Design Voltage: 10800 mV SBDS Version: 1.1 Maximum Error: 0% SBDS Serial Number: 6ABA SBDS Manufacture Date: 2011-01-31 OEM-specific Information: 0x0000FFFF Handle 0x000A, DMI type 32, 20 bytes System Boot Information Status: No errors detected Handle 0x000B, DMI type 41, 11 bytes Unknown Type Header and Data: 29 0B 0B 00 01 83 01 00 00 01 28 Strings: ATI iGPU Handle 0x000C, DMI type 16, 15 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: None Maximum Capacity: 16 GB Error Information Handle: No Error Number Of Devices: 2 Handle 0x000D, DMI type 17, 28 bytes Memory Device Array Handle: 0x000C Error Information Handle: Not Provided Total Width: Unknown Data Width: Unknown Size: No Module Installed Form Factor: DIMM Set: None Locator: DIMM1 Bank Locator: BANK0 Type: <OUT OF SPEC> Type Detail: None Speed: Unknown Manufacturer: Not Specified Serial Number: Not Specified Asset Tag: Unknown Part Number: Not Specified Handle 0x000E, DMI type 17, 28 bytes Memory Device Array Handle: 0x000C Error Information Handle: 0x000F Total Width: 64 bits Data Width: 8 bits Size: 4096 MB Form Factor: DIMM Set: None Locator: DIMM2 Bank Locator: BANK0 Type: <OUT OF SPEC> Type Detail: Synchronous Speed: 1333 MHz (0.8 ns) Manufacturer: Micron Technology Serial Number: 3313A3F8 Asset Tag: Unknown Part Number: 16JSF51264HZ-1G4D1 Handle 0x000F, DMI type 18, 23 bytes 32-bit Memory Error Information Type: OK Granularity: Unknown Operation: Unknown Vendor Syndrome: Unknown Memory Array Address: Unknown Device Address: Unknown Resolution: Unknown Handle 0x0010, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00000000000 Ending Address: 0x000FFFFFFFF Range Size: 4 GB Physical Device Handle: 0x000E Memory Array Mapped Address Handle: 0x0012 Partition Row Position: 1 Handle 0x0011, DMI type 18, 23 bytes 32-bit Memory Error Information Type: OK Granularity: Unknown Operation: Unknown Vendor Syndrome: Unknown Memory Array Address: Unknown Device Address: Unknown Resolution: Unknown Handle 0x0012, DMI type 19, 15 bytes Memory Array Mapped Address Starting Address: 0x00000000000 Ending Address: 0x000FFFFFFFF Range Size: 4 GB Physical Array Handle: 0x000C Partition Width: 0 Handle 0x0013, DMI type 41, 11 bytes Unknown Type Header and Data: 29 0B 13 00 01 83 01 00 00 02 00 Strings: ATI Whistler PRO Handle 0x0014, DMI type 41, 11 bytes Unknown Type Header and Data: 29 0B 14 00 01 85 01 00 00 03 00 Strings: Realtek Lan Controller Handle 0x0015, DMI type 41, 11 bytes Unknown Type Header and Data: 29 0B 15 00 01 81 01 00 00 04 00 Strings: Ralink 5390BC8 802.11bgn/BT combo Adapter Handle 0x0016, DMI type 127, 4 bytes End Of Table # biosdecode # biosdecode 2.9 ACPI 2.0 present. OEM Identifier: HPQOEM RSD Table 32-bit Address: 0xCFEF50AC XSD Table 64-bit Address: 0x00000000CFEF5120 PNP BIOS 1.0 present. Event Notification: Not Supported Real Mode 16-bit Code Address: F000:B891 Real Mode 16-bit Data Address: 0040:0000 16-bit Protected Mode Code Address: 0x000FB89C 16-bit Protected Mode Data Address: 0x00000400 OEM Device Identifier: SST2400 SMBIOS 2.6 present. Structure Table Length: 1205 bytes Structure Table Address: 0x000E3EE0 Number Of Structures: 23 Maximum Structure Size: 162 bytes BIOS32 Service Directory present. Revision: 0 Calling Interface Address: 0x000EF735 PCI Interrupt Routing 1.0 present. Router ID: 00:14.0 Exclusive IRQs: None Compatible Router: 1002:4385 Slot Entry 1: ID 00:11, on-board Slot Entry 2: ID 00:12, on-board Slot Entry 3: ID 00:13, on-board Slot Entry 4: ID 00:16, on-board Slot Entry 5: ID 00:14, on-board Slot Entry 6: ID 00:15, on-board Slot Entry 7: ID 01:05, on-board Slot Entry 8: ID ff:00, slot number 1 Slot Entry 9: ID 03:00, slot number 2 Slot Entry 10: ID 04:00, slot number 3 Slot Entry 11: ID 05:00, slot number 4 Slot Entry 12: ID 06:00, slot number 5 Slot Entry 13: ID ff:00, slot number 6 Slot Entry 14: ID ff:00, slot number 7 Slot Entry 15: ID 07:04, slot number 8 Slot Entry 16: ID 07:05, slot number 8 Slot Entry 17: ID 07:06, slot number 9 Slot Entry 18: ID 07:07, slot number 10 Slot Entry 19: ID ff:00, slot number 11 Slot Entry 20: ID ff:00, slot number 12 Slot Entry 21: ID ff:00, slot number 13 Slot Entry 22: ID ff:00, slot number 14 Installed BIOS version is F.20 07/13/2011. It can be found at http://ftp.hp.com/pub/softpaq/sp54001-54500/sp54025.exe

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Re: [flashrom] Initial version of autotools support for Flashrom
by Carl-Daniel Hailfinger 14 Aug '11

14 Aug '11

Am 14.08.2011 09:58 schrieb Peter Lemenkov: > 2011/8/14 Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>: > >> Hi Peter, >> >> thanks for your patch. >> I think your code looks clean. >> It does not work, though: >> > Yes, I forgot to add bootstrap script, which regenerates all necessary > files. You may invoke the following sequence of commands or simply run > autoreconf -ivf : > > aclocal --force > autoconf --force > autoheader --force > automake --add-missing --copy --force-missing > Thanks, it seems to work now. Cosmetic comment: configure is awfully verbose by default, though. Is it possible to silence it without specifying -q manually? We don't want to flood users with useless messages. Bug: configure checks for the presence of MacOSX/SunOS headers under Linux. Does this work on the oldest supported RHEL and the oldest supported SLES (SLES 8)? We have users on those platforms, and at least SLES 8 still has a 2.4 kernel. Regards, Carl-Daniel -- http://www.hailfinger.org/

1 0

[PATCH] [1/n] SPI FAST READ infrastructure
by Carl-Daniel Hailfinger 14 Aug '11

14 Aug '11

SPI FAST READ infrastructure. Add feature bits to allow annotation of SPI flash chips with possible read methods. This includes the not-yet-supported Dual and Quad I/O read operations just in case we ever encounter programmer hardware which can use that feature. An alternative design would be to create a separate spi_chip_fast_read function and have a per-chip array of allowable read functions similar to what we have for erase functions. A similar design problem exists for chips supporting multiple write functions (e.g. classic SPI write and SPI AAI write). Thorough design review appreciated. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_fast_read/flash.h =================================================================== --- flashrom-spi_fast_read/flash.h (Revision 1249) +++ flashrom-spi_fast_read/flash.h (Arbeitskopie) @@ -92,6 +92,11 @@ #define FEATURE_WRSR_EWSR (1 << 6) #define FEATURE_WRSR_WREN (1 << 7) #define FEATURE_WRSR_EITHER (FEATURE_WRSR_EWSR | FEATURE_WRSR_WREN) +#define FEATURE_SPI_FAST_READ (1 << 8) +#define FEATURE_SPI_FAST_READ_DUAL_O (1 << 9) +#define FEATURE_SPI_FAST_READ_DUAL_IO (1 << 10) +#define FEATURE_SPI_FAST_READ_QUAD_O (1 << 11) +#define FEATURE_SPI_FAST_READ_QUAD_IO (1 << 12) struct flashchip { const char *vendor; Index: flashrom-spi_fast_read/dediprog.c =================================================================== --- flashrom-spi_fast_read/dediprog.c (Revision 1249) +++ flashrom-spi_fast_read/dediprog.c (Arbeitskopie) @@ -220,8 +220,15 @@ /* Round down. */ bulklen = (len - residue) / chunksize * chunksize; - ret = dediprog_spi_bulk_read(flash, buf + residue, start + residue, - bulklen); + if (flash->feature_bits & FEATURE_SPI_FAST_READ) { + ret = dediprog_spi_bulk_read(flash, buf + residue, + start + residue, bulklen); + } else { + msg_pdbg("Using slow read because your flash chip is not " + "listed as supporting fast read (yet).\n"); + ret = spi_read_chunked(flash, buf + residue, start + residue, + bulklen, 16); + } if (ret) return ret; Index: flashrom-spi_fast_read/flashchips.c =================================================================== --- flashrom-spi_fast_read/flashchips.c (Revision 1249) +++ flashrom-spi_fast_read/flashchips.c (Arbeitskopie) @@ -282,6 +282,7 @@ .model_id = AMIC_A25L05PT, .total_size = 64, .page_size = 256, + .feature_bits = FEATURE_SPI_FAST_READ | FEATURE_SPI_FAST_READ_DUAL_O | FEATURE_SPI_FAST_READ_DUAL_IO, .tested = TEST_UNTESTED, .probe = probe_spi_rdid4, .probe_timing = TIMING_ZERO, @@ -313,6 +314,7 @@ .model_id = AMIC_A25L05PU, .total_size = 64, .page_size = 256, + .feature_bits = FEATURE_SPI_FAST_READ | FEATURE_SPI_FAST_READ_DUAL_O | FEATURE_SPI_FAST_READ_DUAL_IO, .tested = TEST_UNTESTED, .probe = probe_spi_rdid4, .probe_timing = TIMING_ZERO, @@ -344,6 +346,7 @@ .model_id = AMIC_A25L10PT, .total_size = 128, .page_size = 256, + .feature_bits = FEATURE_SPI_FAST_READ | FEATURE_SPI_FAST_READ_DUAL_O | FEATURE_SPI_FAST_READ_DUAL_IO, .tested = TEST_UNTESTED, .probe = probe_spi_rdid4, .probe_timing = TIMING_ZERO, @@ -376,6 +379,7 @@ .model_id = AMIC_A25L10PU, .total_size = 128, .page_size = 256, + .feature_bits = FEATURE_SPI_FAST_READ | FEATURE_SPI_FAST_READ_DUAL_O | FEATURE_SPI_FAST_READ_DUAL_IO, .tested = TEST_UNTESTED, .probe = probe_spi_rdid4, .probe_timing = TIMING_ZERO, @@ -408,6 +412,7 @@ .model_id = AMIC_A25L20PT, .total_size = 256, .page_size = 256, + .feature_bits = FEATURE_SPI_FAST_READ | FEATURE_SPI_FAST_READ_DUAL_O | FEATURE_SPI_FAST_READ_DUAL_IO, .tested = TEST_UNTESTED, .probe = probe_spi_rdid4, .probe_timing = TIMING_ZERO, @@ -440,6 +445,7 @@ .model_id = AMIC_A25L20PU, .total_size = 256, .page_size = 256, + .feature_bits = FEATURE_SPI_FAST_READ | FEATURE_SPI_FAST_READ_DUAL_O | FEATURE_SPI_FAST_READ_DUAL_IO, .tested = TEST_UNTESTED, .probe = probe_spi_rdid4, .probe_timing = TIMING_ZERO, -- http://www.hailfinger.org/

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Re: [flashrom] Initial version of autotools support for Flashrom
by Carl-Daniel Hailfinger 14 Aug '11

14 Aug '11

Hi Peter, thanks for your patch. Am 13.08.2011 18:23 schrieb Peter Lemenkov: > Some time ago I mentioned that I've got patches for full autotools > support - here is the first patch in a patchset for your further > consideration: > > https://github.com/lemenkov/flashrom/commits/autotools > > It was tested on RHEL 5, 6, Fedora 1x, i386, i586, i686, x86_64 and > ppc (I'm using it for building Flashrom's RPM for a half of the year > at least). > > It's rebased on top of svn1412 and cleaned up to be a full drop-in > replacement for handmade Makefile. Unfortunately I didn't test in on > anything else than Linux, so I must admit that it's not in a very good > shape for MinGW / BSD / DOS / Darwin users (ARM, MIPS users could be > also hurt as well - that's why I didn't touch anything else in this > commit except adding these two files). > I think your code looks clean. It does not work, though: compiler@p35:flashrom-autotools> rm Makefile compiler@p35:flashrom-autotools> make make: *** Keine Targets angegeben und keine »make«-Steuerdatei gefunden. Schluss. (No targets specified, no make control file. Aborting.) compiler@p35:flashrom-autotools> autoconf --version autoconf (GNU Autoconf) 2.65 compiler@p35:flashrom-autotools> automake --version automake (GNU automake) 1.11.1 compiler@p35:flashrom-autotools> automake configure.ac: no proper invocation of AM_INIT_AUTOMAKE was found. configure.ac: You should verify that configure.ac invokes AM_INIT_AUTOMAKE, configure.ac: that aclocal.m4 is present in the top-level directory, configure.ac: and that aclocal.m4 was recently regenerated (using aclocal). configure.ac:5: required file `./config.guess' not found configure.ac:5: `automake --add-missing' can install `config.guess' configure.ac:5: required file `./config.sub' not found configure.ac:5: `automake --add-missing' can install `config.sub' configure.ac:170: required file `./install-sh' not found configure.ac:170: `automake --add-missing' can install `install-sh' Makefile.am:8: HAVE_SYS_UTSNAME does not appear in AM_CONDITIONAL Makefile.am:9: HAVE_UNAME does not appear in AM_CONDITIONAL Makefile.am:14: HAVE_DMIDECODE does not appear in AM_CONDITIONAL Makefile.am:21: HAVE_INTERNAL does not appear in AM_CONDITIONAL Makefile.am:29: HAVE_X86_ONLY_INTERNAL does not appear in AM_CONDITIONAL Makefile.am:41: HAVE_SERPROG does not appear in AM_CONDITIONAL Makefile.am:46: HAVE_RAYER_SPI does not appear in AM_CONDITIONAL Makefile.am:51: HAVE_BITBANG_SPI does not appear in AM_CONDITIONAL Makefile.am:56: HAVE_NIC3COM does not appear in AM_CONDITIONAL Makefile.am:61: HAVE_GFXNVIDIA does not appear in AM_CONDITIONAL Makefile.am:66: HAVE_SATASII does not appear in AM_CONDITIONAL Makefile.am:71: HAVE_ATAHPT does not appear in AM_CONDITIONAL Makefile.am:76: HAVE_FT2232_SPI does not appear in AM_CONDITIONAL Makefile.am:81: HAVE_DUMMY does not appear in AM_CONDITIONAL Makefile.am:86: HAVE_DRKAISER does not appear in AM_CONDITIONAL Makefile.am:91: HAVE_NICREALTEK does not appear in AM_CONDITIONAL Makefile.am:96: HAVE_NICNATSEMI does not appear in AM_CONDITIONAL Makefile.am:101: HAVE_NICINTEL does not appear in AM_CONDITIONAL Makefile.am:106: HAVE_NICINTEL_SPI does not appear in AM_CONDITIONAL Makefile.am:111: HAVE_GFXOGP does not appear in AM_CONDITIONAL Makefile.am:116: HAVE_BUSPIRATE_SPI does not appear in AM_CONDITIONAL Makefile.am:121: HAVE_DEDIPROG does not appear in AM_CONDITIONAL Makefile.am:126: HAVE_SATAMV does not appear in AM_CONDITIONAL Makefile.am:131: HAVE_SERIAL does not appear in AM_CONDITIONAL Makefile.am:135: HAVE_PRINT_WIKI does not appear in AM_CONDITIONAL Makefile.am:140: HAVE_PCI does not appear in AM_CONDITIONAL Makefile.am: required file `./INSTALL' not found Makefile.am: `automake --add-missing' can install `INSTALL' Makefile.am: required file `./NEWS' not found Makefile.am: required file `./AUTHORS' not found Makefile.am: required file `./ChangeLog' not found configure.ac:8: required file `config.h.in' not found Makefile.am: required file `./depcomp' not found Makefile.am: `automake --add-missing' can install `depcomp' /usr/share/automake-1.11/am/depend2.am: am__fastdepCC does not appear in AM_CONDITIONAL /usr/share/automake-1.11/am/depend2.am: The usual way to define `am__fastdepCC' is to add `AC_PROG_CC' /usr/share/automake-1.11/am/depend2.am: to `configure.ac' and run `aclocal' and `autoconf' again. /usr/share/automake-1.11/am/depend2.am: AMDEP does not appear in AM_CONDITIONAL /usr/share/automake-1.11/am/depend2.am: The usual way to define `AMDEP' is to add one of the compiler tests /usr/share/automake-1.11/am/depend2.am: AC_PROG_CC, AC_PROG_CXX, AC_PROG_CXX, AC_PROG_OBJC, /usr/share/automake-1.11/am/depend2.am: AM_PROG_AS, AM_PROG_GCJ, AM_PROG_UPC /usr/share/automake-1.11/am/depend2.am: to `configure.ac' and run `aclocal' and `autoconf' again. compiler@p35:flashrom-autotools> autoconf configure.ac:9: error: possibly undefined macro: AM_INIT_AUTOMAKE If this token and others are legitimate, please use m4_pattern_allow. See the Autoconf documentation. configure.ac:223: error: possibly undefined macro: AM_CONDITIONAL Next try: compiler@p35:flashrom-autotools> aclocal compiler@p35:/sources/tmptrees/ready/flashrom-autotools> autoconf compiler@p35:/sources/tmptrees/ready/flashrom-autotools> automake configure.ac:5: required file `./config.guess' not found configure.ac:5: `automake --add-missing' can install `config.guess' configure.ac:5: required file `./config.sub' not found configure.ac:5: `automake --add-missing' can install `config.sub' configure.ac:9: required file `./install-sh' not found configure.ac:9: `automake --add-missing' can install `install-sh' configure.ac:9: required file `./missing' not found configure.ac:9: `automake --add-missing' can install `missing' configure.ac:8: required file `config.h.in' not found Makefile.am: required file `./depcomp' not found Makefile.am: `automake --add-missing' can install `depcomp' Next try: compiler@p35:flashrom-autotools> automake --add-missing configure.ac:5: installing `./config.guess' configure.ac:5: installing `./config.sub' configure.ac:9: installing `./install-sh' configure.ac:9: installing `./missing' configure.ac:8: required file `config.h.in' not found Makefile.am: installing `./depcomp' compiler@p35:flashrom-autotools> ./configure checking build system type... i686-suse-linux-gnu checking host system type... i686-suse-linux-gnu checking target system type... i686-suse-linux-gnu checking for a BSD-compatible install... /usr/bin/install -c checking whether build environment is sane... yes checking for a thread-safe mkdir -p... /bin/mkdir -p checking for gawk... gawk checking whether make sets $(MAKE)... yes checking for style of include used by make... GNU checking for gcc... gcc checking whether the C compiler works... yes checking for C compiler default output file name... a.out checking for suffix of executables... checking whether we are cross compiling... no checking for suffix of object files... o checking whether we are using the GNU C compiler... yes checking whether gcc accepts -g... yes checking for gcc option to accept ISO C89... none needed checking dependency style of gcc... gcc3 checking how to run the C preprocessor... gcc -E checking for grep that handles long lines and -e... /usr/bin/grep checking for egrep... /usr/bin/grep -E checking for ANSI C header files... yes checking for sys/types.h... yes checking for sys/stat.h... yes checking for stdlib.h... yes checking for string.h... yes checking for memory.h... yes checking for strings.h... yes checking for inttypes.h... yes checking for stdint.h... yes checking for unistd.h... yes checking whether byte ordering is bigendian... no checking for gcc... (cached) gcc checking whether we are using the GNU C compiler... (cached) yes checking whether gcc accepts -g... (cached) yes checking for gcc option to accept ISO C89... (cached) none needed checking dependency style of gcc... (cached) gcc3 checking whether make sets $(MAKE)... (cached) yes checking for dmidecode... /usr/sbin/dmidecode checking DirectIO/darwinio.h usability... no checking DirectIO/darwinio.h presence... no checking for DirectIO/darwinio.h... no checking arpa/inet.h usability... yes checking arpa/inet.h presence... yes checking for arpa/inet.h... yes checking asm/sunddi.h usability... no checking asm/sunddi.h presence... no checking for asm/sunddi.h... no checking fcntl.h usability... yes checking fcntl.h presence... yes checking for fcntl.h... yes checking for inttypes.h... (cached) yes checking limits.h usability... yes checking limits.h presence... yes checking for limits.h... yes checking machine/cpufunc.h usability... no checking machine/cpufunc.h presence... no checking for machine/cpufunc.h... no checking machine/sysarch.h usability... no checking machine/sysarch.h presence... no checking for machine/sysarch.h... no checking netdb.h usability... yes checking netdb.h presence... yes checking for netdb.h... yes checking netinet/in.h usability... yes checking netinet/in.h presence... yes checking for netinet/in.h... yes checking stddef.h usability... yes checking stddef.h presence... yes checking for stddef.h... yes checking for stdint.h... (cached) yes checking for stdlib.h... (cached) yes checking for string.h... (cached) yes checking for strings.h... (cached) yes checking sys/io.h usability... yes checking sys/io.h presence... yes checking for sys/io.h... yes checking sys/ioctl.h usability... yes checking sys/ioctl.h presence... yes checking for sys/ioctl.h... yes checking sys/psw.h usability... no checking sys/psw.h presence... no checking for sys/psw.h... no checking sys/socket.h usability... yes checking sys/socket.h presence... yes checking for sys/socket.h... yes checking sys/sysi86.h usability... no checking sys/sysi86.h presence... no checking for sys/sysi86.h... no checking sys/time.h usability... yes checking sys/time.h presence... yes checking for sys/time.h... yes checking sys/utsname.h usability... yes checking sys/utsname.h presence... yes checking for sys/utsname.h... yes checking termios.h usability... yes checking termios.h presence... yes checking for termios.h... yes checking for unistd.h... (cached) yes checking for inline... inline checking for off_t... yes checking for size_t... yes checking size of int... 4 checking for ssize_t... yes checking for uint8_t... yes checking for uint16_t... yes checking for uint64_t... yes checking for uint32_t... yes checking for stdlib.h... (cached) yes checking for GNU libc compatible malloc... yes checking for stdlib.h... (cached) yes checking for unistd.h... (cached) yes checking for sys/param.h... yes checking for getpagesize... yes checking for working mmap... yes checking for stdlib.h... (cached) yes checking for GNU libc compatible realloc... yes checking for gethostbyaddr... yes checking for gethostbyname... yes checking for getpagesize... (cached) yes checking for gettimeofday... yes checking for memmove... yes checking for memset... yes checking for munmap... yes checking for socket... yes checking for strcasecmp... yes checking for strchr... yes checking for strcspn... yes checking for strdup... yes checking for strerror... yes checking for strncasecmp... yes checking for strspn... yes checking for strstr... yes checking for strtol... yes checking for strtoul... yes checking for uname... yes checking for pci_alloc in -lpci... yes checking for socket in -lsocket... no checking for usb_init in -lusb... yes checking for main in -lftdi... yes configure: creating ./config.status config.status: error: cannot find input file: `Makefile.in' This is openSUSE 11.3 i586. autoconf and automake are installed. Any ideas how to fix this portability problem of autotools or what I'm doing wrong? The autotools branch and fedora-1412 branch in your repository both have that problem. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[PATCH 6/6] Add ich_descriptor_tool to decode all flash descriptors stored in a flash dump file
by Stefan Tauner 14 Aug '11

14 Aug '11

additionally to what is available via FDOC/FDOD this allows to access: - the softstraps which are used to configure the chipset by flash content without the need for BIOS routines. on ICH8 it is possible to read those with FDOC/FDOC too, but this was removed in later chipsets. - the ME VSCC (Vendor Specific Component Capabilities) table. simply put, this is an SPI chip database used to figure out the flash's capabilities Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ich_descriptors.c | 434 ++++++++++++++++++++++ ich_descriptors.h | 205 ++++++++++ util/ich_descriptors_tool/Makefile | 42 ++ util/ich_descriptors_tool/TODO | 6 + util/ich_descriptors_tool/ich_descriptors_tool.c | 225 +++++++++++ 5 files changed, 912 insertions(+), 0 deletions(-) create mode 100644 util/ich_descriptors_tool/Makefile create mode 100644 util/ich_descriptors_tool/TODO create mode 100644 util/ich_descriptors_tool/ich_descriptors_tool.c diff --git a/ich_descriptors.c b/ich_descriptors.c index ce40d9f..57c1d51 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -22,9 +22,33 @@ #if defined(__i386__) || defined(__x86_64__) #include "ich_descriptors.h" + +#ifdef ICH_DESCRIPTORS_FROM_DUMP + +#include <stdio.h> +#define msg_perr printf +#define msg_pdbg printf +#define msg_pdbg2 printf +#define msg_pspew printf +#define print(t, ...) printf(__VA_ARGS__) +#define DESCRIPTOR_MODE_SIGNATURE 0x0ff0a55a +/* The upper map is located in the word before the 256B-long OEM section at the + * end of the 4kB-long flash descriptor. + */ +#define UPPER_MAP_OFFSET (4096 - 256 - 4) +#define getVTBA(flumap) (((flumap)->FLUMAP1 << 4) & 0x00000ff0) + +#else /* ICH_DESCRIPTORS_FROM_DUMP */ + #include "flash.h" /* for msg_* */ #include "programmer.h" +#endif /* ICH_DESCRIPTORS_FROM_DUMP */ + +#ifndef min +#define min(a, b) (a < b) ? a : b +#endif + void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity) { print(verbosity, "BES=0x%x, ", (reg_val & VSCC_BES) >> VSCC_BES_OFF); @@ -48,6 +72,12 @@ void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descripto prettyprint_ich_descriptor_component(desc); prettyprint_ich_descriptor_region(desc); prettyprint_ich_descriptor_master(&desc->master); +#ifdef ICH_DESCRIPTORS_FROM_DUMP + if (cs >= CHIPSET_ICH8) { + prettyprint_ich_descriptor_upper_map(&desc->upper); + prettyprint_ich_descriptor_straps(cs, desc); + } +#endif /* ICH_DESCRIPTORS_FROM_DUMP */ } void prettyprint_ich_descriptor_content(const struct ich_desc_content *cont) @@ -214,6 +244,409 @@ void prettyprint_ich_descriptor_master(const struct ich_desc_master *mstr) msg_pdbg2("\n"); } +#ifdef ICH_DESCRIPTORS_FROM_DUMP + +void prettyprint_ich_descriptor_straps_ich8(const struct ich_descriptors *desc) +{ + static const char * const str_GPIO12[4] = { + "GPIO12", + "LAN PHY Power Control Function (Native Output)", + "GLAN_DOCK# (Native Input)", + "invalid configuration", + }; + + + msg_pdbg2("--- MCH details ---\n"); + msg_pdbg2("ME B is %sabled.\n", desc->north.ich8.MDB ? "dis" : "en"); + msg_pdbg2("\n"); + + msg_pdbg2("--- ICH details ---\n"); + msg_pdbg2("ME SMBus Address 1: 0x%02x\n", desc->south.ich8.ASD); + msg_pdbg2("ME SMBus Address 2: 0x%02x\n", desc->south.ich8.ASD2); + msg_pdbg2("ME SMBus Controller is connected to the %s.\n", + desc->south.ich8.MESM2SEL ? "SMLink pins" : "SMBus pins"); + msg_pdbg2("SPI CS1 is used for %s.\n", + desc->south.ich8.SPICS1_LANPHYPC_SEL ? + "LAN PHY Power Control Function" : + "SPI Chip Select"); + msg_pdbg2("GPIO12 Select is used as %s.\n", + str_GPIO12[desc->south.ich8.GPIO12_SEL]); + msg_pdbg2("PCIe Port 6 is used for %s.\n", + desc->south.ich8.GLAN_PCIE_SEL ? "integrated LAN" : "PCI Express"); + msg_pdbg2("%sn BMC Mode: " + "Intel AMT SMBus Controller 1 is connected to %s.\n", + desc->south.ich8.BMCMODE ? "I" : "Not i", + desc->south.ich8.BMCMODE ? "SMLink" : "SMBus"); + msg_pdbg2("TCO is in %s Mode.\n", + desc->south.ich8.TCOMODE ? "Advanced TCO" : "Legacy/Compatible"); + msg_pdbg2("ME A is %sabled.\n", + desc->south.ich8.ME_DISABLE ? "dis" : "en"); + msg_pdbg2("\n"); +} + +static void prettyprint_ich_descriptor_straps_ibex_pciecs(uint8_t conf, uint8_t off) +{ + msg_pdbg2("PCI Express Port Configuration Strap %d: ", off+1); + + off *= 4; + switch(conf){ + case 0: + msg_pdbg2("4x1 Ports %d-%d (x1)", 1+off, 4+off); + break; + case 1: + msg_pdbg2("1x2, 2x1 Port %d (x2), Port %d (disabled), " + "Ports %d, %d (x1)", 1+off, 2+off, 3+off, 4+off); + break; + case 2: + msg_pdbg2("2x2 Port %d (x2), Port %d (x2), Ports " + "%d, %d (disabled)", 1+off, 3+off, 2+off, 4+off); + break; + case 3: + msg_pdbg2("1x4 Port %d (x4), Ports %d-%d (disabled)", + 1+off, 2+off, 4+off); + break; + } + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_straps_ibex(const struct ich_desc_south_strap *s) +{ + static const uint8_t const dec_t209min[4] = { + 100, + 50, + 5, + 1 + }; + + msg_pdbg2("--- PCH ---\n"); + + /* PCHSTRP1 */ + msg_pdbg2("Chipset configuration Softstrap 2: %d\n", s->ibex.cs_ss2); + msg_pdbg2("Intel ME SMBus Select is %sabled.\n", + s->ibex.SMB_EN ? "en" : "dis"); + msg_pdbg2("SMLink0 segment is %sabled.\n", + s->ibex.SML0_EN ? "en" : "dis"); + msg_pdbg2("SMLink1 segment is %sabled.\n", + s->ibex.SML1_EN ? "en" : "dis"); + msg_pdbg2("SMLink1 Frequency: %s\n", + (s->ibex.SML1FRQ == 1) ? "100 kHz" : "reserved"); + msg_pdbg2("Intel ME SMBus Frequency: %s\n", + (s->ibex.SMB0FRQ == 1) ? "100 kHz" : "reserved"); + msg_pdbg2("SMLink0 Frequency: %s\n", + (s->ibex.SML0FRQ == 1) ? "100 kHz" : "reserved"); + msg_pdbg2("GPIO12 is used as %s.\n", s->ibex.LANPHYPC_GP12_SEL ? + "LAN_PHY_PWR_CTRL" : "general purpose output"); + + /* PCHSTRP2 */ + msg_pdbg2("Chipset configuration Softstrap 3: 0x%x\n", s->ibex.cs_ss3); + + /* PCHSTRP3 */ + msg_pdbg2("ME SMBus ASD address is %sabled.\n", + s->ibex.MESMASDEN ? "en" : "dis"); + msg_pdbg2("ME SMBus Controller ASD Target address: 0x%02x\n", + s->ibex.MESMASDA); + msg_pdbg2("ME SMBus I2C address is %sabled.\n", + s->ibex.MESMI2CEN ? "en" : "dis"); + msg_pdbg2("ME SMBus I2C target address: 0x%02x\n", + s->ibex.MESMI2CA); + + /* PCHSTRP4 */ + /* PCHSTRP5 */ + msg_pdbg2("Intel PHY is %s.\n", + (s->ibex.PHYCON == 2) ? "connected" : + (s->ibex.PHYCON == 0) ? "disconnected" : "reserved"); + msg_pdbg2("GbE MAC SMBus address is %sabled.\n", + s->ibex.GBEMAC_SMBUS_ADDR_EN ? "en" : "dis"); + msg_pdbg2("GbE MAC SMBus address: 0x%02x\n", + s->ibex.GBEMAC_SMBUS_ADDR); + msg_pdbg2("GbE PHY SMBus address: 0x%02x\n", + s->ibex.GBEPHY_SMBUS_ADDR); + + /* PCHSTRP6 */ + /* PCHSTRP7 */ + msg_pdbg2("Intel ME SMBus Subsystem Vendor ID: 0x%04x\n", + s->ibex.MESMA2UDID_VENDOR); + msg_pdbg2("Intel ME SMBus Subsystem Device ID: 0x%04x\n", + s->ibex.MESMA2UDID_VENDOR); + + /* PCHSTRP8 */ + /* PCHSTRP9 */ + prettyprint_ich_descriptor_straps_ibex_pciecs(s->ibex.PCIEPCS1, 0); + prettyprint_ich_descriptor_straps_ibex_pciecs(s->ibex.PCIEPCS1, 1); + msg_pdbg2("PCIe Lane Reversal 1: PCIe Lanes 0-3 are %sreserved.\n", + s->ibex.PCIELR1 ? "" : "not "); + msg_pdbg2("PCIe Lane Reversal 2: PCIe Lanes 4-7 are %sreserved.\n", + s->ibex.PCIELR2 ? "" : "not "); + msg_pdbg2("DMI Lane Reversal: DMI Lanes 0-3 are %sreserved.\n", + s->ibex.DMILR ? "" : "not "); + msg_pdbg2("Default PHY PCIe Port is %d.\n", s->ibex.PHY_PCIEPORTSEL+1); + msg_pdbg2("Integrated MAC/PHY communication over PCIe is %sabled.\n", + s->ibex.PHY_PCIE_EN ? "en" : "dis"); + + /* PCHSTRP10 */ + msg_pdbg2("Management Engine will boot from %sflash.\n", + s->ibex.ME_BOOT_FLASH ? "" : "ROM, then "); + msg_pdbg2("Chipset configuration Softstrap 5: %d\n", s->ibex.cs_ss5); + msg_pdbg2("Virtualization Engine Enable 1 is %sabled.\n", + s->ibex.VE_EN ? "en" : "dis"); + msg_pdbg2("ME Memory-attached Debug Display Device is %sabled.\n", + s->ibex.MMDDE ? "en" : "dis"); + msg_pdbg2("ME Memory-attached Debug Display Device address: 0x%02x\n", + s->ibex.MMADDR); + msg_pdbg2("Chipset configuration Softstrap 7: %d\n", s->ibex.cs_ss7); + msg_pdbg2("Integrated Clocking Configuration is %d.\n", + (s->ibex.ICC_SEL == 7) ? 0 : s->ibex.ICC_SEL); + msg_pdbg2("PCH Signal CL_RST1# does %sassert when Intel ME performs a " + "reset.\n", s->ibex.MER_CL1 ? "" : "not "); + + /* PCHSTRP11 */ + msg_pdbg2("SMLink1 GP Address is %sabled.\n", + s->ibex.SML1GPAEN ? "en" : "dis"); + msg_pdbg2("SMLink1 controller General Purpose Target address: 0x%02x\n", + s->ibex.SML1GPA); + msg_pdbg2("SMLink1 I2C Target address is %sabled.\n", + s->ibex.SML1I2CAEN ? "en" : "dis"); + msg_pdbg2("SMLink1 I2C Target address: 0x%02x\n", + s->ibex.SML1I2CA); + + /* PCHSTRP12 */ + /* PCHSTRP13 */ + /* PCHSTRP14 */ + msg_pdbg2("Virtualization Engine Enable 2 is %sabled.\n", + s->ibex.VE_EN2 ? "en" : "dis"); + msg_pdbg2("Virtualization Engine will boot from %sflash.\n", + s->ibex.VE_BOOT_FLASH ? "" : "ROM, then "); + msg_pdbg2("Braidwood SSD functionality is %sabled.\n", + s->ibex.BW_SSD ? "en" : "dis"); + msg_pdbg2("Braidwood NVMHCI functionality is %sabled.\n", + s->ibex.NVMHCI_EN ? "en" : "dis"); + + /* PCHSTRP15 */ + msg_pdbg2("Chipset configuration Softstrap 6: %d\n", s->ibex.cs_ss6); + msg_pdbg2("Integrated wired LAN Solution is %sabled.\n", + s->ibex.IWL_EN ? "en" : "dis"); + msg_pdbg2("t209 min Timing: %d ms\n", + dec_t209min[s->ibex.t209min]); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_straps(enum ich_chipset cs, const struct ich_descriptors *desc) +{ + unsigned int i, max; + msg_pdbg2("=== Softstraps ===\n"); + + if (sizeof(desc->north.STRPs) / 4 + 1 < desc->content.MSL) { + max = sizeof(desc->north.STRPs) / 4 + 1; + msg_pdbg2("MSL (%u) is greater than the current maximum of %u " + "entries.\n", desc->content.MSL, max + 1); + msg_pdbg2("Only the first %u entries will be printed.\n", max); + } else + max = desc->content.MSL; + + msg_pdbg2("--- North/MCH/PROC (%d entries) ---\n", max); + for(i = 0; i < max; i++) + msg_pdbg2("STRP%-2d = 0x%08x\n", i, desc->north.STRPs[i]); + msg_pdbg2("\n"); + + if (sizeof(desc->south.STRPs) / 4 < desc->content.ISL) { + max = sizeof(desc->south.STRPs) / 4; + msg_pdbg2("ISL (%u) is greater than the current maximum of %u " + "entries.\n", desc->content.ISL, max); + msg_pdbg2("Only the first %u entries will be printed.\n", max); + } else + max = desc->content.ISL; + + msg_pdbg2("--- South/ICH/PCH (%d entries) ---\n", max); + for(i = 0; i < max; i++) + msg_pdbg2("STRP%-2d = 0x%08x\n", i, desc->south.STRPs[i]); + msg_pdbg2("\n"); + + switch (cs) { + case CHIPSET_ICH8: + if (sizeof(desc->north.ich8) / 4 != desc->content.MSL) + msg_pdbg2("Detailed North/MCH/PROC information is " + "probably not reliable, printing anyway.\n"); + if (sizeof(desc->south.ich8) / 4 != desc->content.ISL) + msg_pdbg2("Detailed South/ICH/PCH information is " + "probably not reliable, printing anyway.\n"); + prettyprint_ich_descriptor_straps_ich8(desc); + break; + case CHIPSET_5_SERIES_IBEX_PEAK: + /* PCH straps only. PROCSTRPs are unknown. */ + if (sizeof(desc->south.ibex) / 4 != desc->content.ISL) + msg_pdbg2("Detailed South/ICH/PCH information is " + "probably not reliable, printing anyway.\n"); + prettyprint_ich_descriptor_straps_ibex(&desc->south); + break; + case CHIPSET_ICH_UNKNOWN: + break; + default: + msg_pdbg2("The meaning of the descriptor straps are unknown " + "yet.\n\n"); + break; + } +} + +void prettyprint_rdid(uint32_t reg_val) +{ + uint8_t mid = reg_val & 0xFF; + uint16_t did = ((reg_val >> 16) & 0xFF) | (reg_val & 0xFF00); + msg_pdbg2("Manufacturer ID 0x%02x, Device ID 0x%04x\n", mid, did); +} + +void prettyprint_ich_descriptor_upper_map(const struct ich_desc_upper_map *umap) +{ + int i; + msg_pdbg2("=== Upper Map Section ===\n"); + msg_pdbg2("FLUMAP1 0x%08x\n", umap->FLUMAP1); + msg_pdbg2("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2("VTL (length in DWORDS) = %d\n", umap->VTL); + msg_pdbg2("VTBA (base address) = 0x%6.6x\n", getVTBA(umap)); + msg_pdbg2("\n"); + + msg_pdbg2("VSCC Table: %d entries\n", umap->VTL/2); + for (i = 0; i < umap->VTL/2; i++) + { + uint32_t jid = umap->vscc_table[i].JID; + uint32_t vscc = umap->vscc_table[i].VSCC; + msg_pdbg2(" JID%d = 0x%08x\n", i, jid); + msg_pdbg2(" VSCC%d = 0x%08x\n", i, vscc); + msg_pdbg2(" "); /* indention */ + prettyprint_rdid(jid); + msg_pdbg2(" "); /* indention */ + prettyprint_ich_reg_vscc(vscc, 0); + } + msg_pdbg2("\n"); +} + +/* len is the length of dump in bytes */ +int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, enum ich_chipset cs, struct ich_descriptors *desc) +{ + unsigned int i, max; + uint8_t pch_bug_offset = 0; + + if (dump == NULL || desc == NULL) + return RET_PARAM; + + if (dump[0] != DESCRIPTOR_MODE_SIGNATURE) { + if (dump[4] == DESCRIPTOR_MODE_SIGNATURE) + pch_bug_offset = 4; + else + return RET_ERR; + } + + /* map */ + if (len < (4 + pch_bug_offset) * 4 - 1) + return RET_OOB; + desc->content.FLVALSIG = dump[0 + pch_bug_offset]; + desc->content.FLMAP0 = dump[1 + pch_bug_offset]; + desc->content.FLMAP1 = dump[2 + pch_bug_offset]; + desc->content.FLMAP2 = dump[3 + pch_bug_offset]; + + /* component */ + if (len < (getFCBA(&desc->content) + 3 * 4 - 1)) + return RET_OOB; + desc->component.FLCOMP = dump[(getFCBA(&desc->content) >> 2) + 0]; + desc->component.FLILL = dump[(getFCBA(&desc->content) >> 2) + 1]; + desc->component.FLPB = dump[(getFCBA(&desc->content) >> 2) + 2]; + + /* region */ + if (len < (getFRBA(&desc->content) + 5 * 4 - 1)) + return RET_OOB; + desc->region.FLREGs[0] = dump[(getFRBA(&desc->content) >> 2) + 0]; + desc->region.FLREGs[1] = dump[(getFRBA(&desc->content) >> 2) + 1]; + desc->region.FLREGs[2] = dump[(getFRBA(&desc->content) >> 2) + 2]; + desc->region.FLREGs[3] = dump[(getFRBA(&desc->content) >> 2) + 3]; + desc->region.FLREGs[4] = dump[(getFRBA(&desc->content) >> 2) + 4]; + + /* master */ + if (len < (getFMBA(&desc->content) + 3 * 4 - 1)) + return RET_OOB; + desc->master.FLMSTR1 = dump[(getFMBA(&desc->content) >> 2) + 0]; + desc->master.FLMSTR2 = dump[(getFMBA(&desc->content) >> 2) + 1]; + desc->master.FLMSTR3 = dump[(getFMBA(&desc->content) >> 2) + 2]; + + /* upper map */ + desc->upper.FLUMAP1 = dump[(UPPER_MAP_OFFSET >> 2) + 0]; + + /* VTL is 8 bits long. Quote from the Ibex Peak SPI programming guide: + * "Identifies the 1s based number of DWORDS contained in the VSCC + * Table. Each SPI component entry in the table is 2 DWORDS long." So + * the maximum of 255 gives us 127.5 SPI components(!?) 8 bytes each. A + * check ensures that the maximum offset actually accessed is available. + */ + if (len < (getVTBA(&desc->upper) + (desc->upper.VTL / 2 * 8) - 1)) + return RET_OOB; + + for (i = 0; i < desc->upper.VTL/2; i++) { + desc->upper.vscc_table[i].JID = + dump[(getVTBA(&desc->upper) >> 2) + i * 2 + 0]; + desc->upper.vscc_table[i].VSCC = + dump[(getVTBA(&desc->upper) >> 2) + i * 2 + 1]; + } + + /* MCH/PROC (aka. North) straps */ + if (len < getFMSBA(&desc->content) + desc->content.MSL * 4) + return RET_OOB; + + /* limit the range to be written */ + max = min(sizeof(desc->north.STRPs) / 4, desc->content.MSL); + for (i = 0; i < max; i++) + desc->north.STRPs[i] = + dump[(getFMSBA(&desc->content) >> 2) + i]; + + /* ICH/PCH (aka. South) straps */ + if (len < getFISBA(&desc->content) + desc->content.ISL * 4) + return RET_OOB; + + /* limit the range to be written */ + max = min(sizeof(desc->south.STRPs) / 4, desc->content.ISL); + for (i = 0; i < max; i++) + desc->south.STRPs[i] = + dump[(getFISBA(&desc->content) >> 2) + i]; + + return RET_OK; +} + +#else /* ICH_DESCRIPTORS_FROM_DUMP */ + +/** Returns the integer representation of the component density with index +idx in bytes or 0 if a correct size can not be determined. */ +int getFCBA_component_density(uint8_t idx, const struct ich_descriptors *desc) +{ + uint8_t size_enc; + static const int const dec_mem[6] = { + 512 * 1024, + 1 * 1024 * 1024, + 2 * 1024 * 1024, + 4 * 1024 * 1024, + 8 * 1024 * 1024, + 16 * 1024 * 1024, + }; + + switch(idx) { + case 0: + size_enc = desc->component.comp1_density; + break; + case 1: + if (desc->content.NC == 0) + return 0; + size_enc = desc->component.comp2_density; + break; + default: + msg_perr("Only component index 0 or 1 are supported yet.\n"); + return 0; + } + if (size_enc > 5) { + msg_perr("Density of component with index %d is invalid. " + "Encoded density is 0x%x.\n", idx, size_enc); + return 0; + } + return dec_mem[size_enc]; +} + static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) { uint32_t control = 0; @@ -284,5 +717,6 @@ int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc) msg_pdbg2(" done.\n"); return RET_OK; } +#endif /* ICH_DESCRIPTORS_FROM_DUMP */ #endif /* BITFIELDS == 1 */ #endif /* defined(__i386__) || defined(__x86_64__) */ diff --git a/ich_descriptors.h b/ich_descriptors.h index b1da914..56d1b3e 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -240,11 +240,206 @@ struct ich_desc_master { }; }; +#ifdef ICH_DESCRIPTORS_FROM_DUMP +struct ich_desc_north_strap { + union { + uint32_t STRPs[1]; /* current maximum: ich8 */ + struct { /* ich8 */ + struct { /* STRP2 (in the datasheet) */ + uint32_t MDB :1, + :31; + }; + } ich8; + }; +}; + +struct ich_desc_south_strap { + union { + uint32_t STRPs[16]; /* current maximum: ibex peak */ + struct { /* ich8 */ + struct { /* STRP1 */ + uint32_t ME_DISABLE :1, + :6, + TCOMODE :1, + ASD :7, + BMCMODE :1, + :3, + GLAN_PCIE_SEL :1, + GPIO12_SEL :2, + SPICS1_LANPHYPC_SEL :1, + MESM2SEL :1, + :1, + ASD2 :7; + }; + } ich8; + struct { /* ibex peak */ + struct { /* STRP0 */ + uint32_t :1, + cs_ss2 :1, + :5, + SMB_EN :1, + SML0_EN :1, + SML1_EN :1, + SML1FRQ :2, + SMB0FRQ :2, + SML0FRQ :2, + :4, + LANPHYPC_GP12_SEL :1, + cs_ss1 :1, + :2, + DMI_REQID_DIS :1, + :4, + BBBS :2, + :1; + }; + struct { /* STRP1 */ + uint32_t cs_ss3 :4, + :28; + }; + struct { /* STRP2 */ + uint32_t :8, + MESMASDEN :1, + MESMASDA :7, + :8, + MESMI2CEN :1, + MESMI2CA :7; + }; + struct { /* STRP3 */ + uint32_t :32; + }; + struct { /* STRP4 */ + uint32_t PHYCON :2, + :6, + GBEMAC_SMBUS_ADDR_EN :1, + GBEMAC_SMBUS_ADDR :7, + :1, + GBEPHY_SMBUS_ADDR :7, + :8; + }; + struct { /* STRP5 */ + uint32_t :32; + }; + struct { /* STRP6 */ + uint32_t :32; + }; + struct { /* STRP7 */ + uint32_t MESMA2UDID_VENDOR :16, + MESMA2UDID_DEVICE :16; + }; + struct { /* STRP8 */ + uint32_t :32; + }; + struct { /* STRP9 */ + uint32_t PCIEPCS1 :2, + PCIEPCS2 :2, + PCIELR1 :1, + PCIELR2 :1, + DMILR :1, + :1, + PHY_PCIEPORTSEL :3, + PHY_PCIE_EN :1, + :20; + }; + struct { /* STRP10 */ + uint32_t :1, + ME_BOOT_FLASH :1, + cs_ss5 :1, + VE_EN :1, + :4, + MMDDE :1, + MMADDR :7, + cs_ss7 :1, + :1, + ICC_SEL :3, + MER_CL1 :1, + :10; + }; + struct { /* STRP11 */ + uint32_t SML1GPAEN :1, + SML1GPA :7, + :16, + SML1I2CAEN :1, + SML1I2CA :7; + }; + struct { /* STRP12 */ + uint32_t :32; + }; + struct { /* STRP13 */ + uint32_t :32; + }; + struct { /* STRP14 */ + uint32_t :8, + VE_EN2 :1, + :5, + VE_BOOT_FLASH :1, + :1, + BW_SSD :1, + NVMHCI_EN :1, + :14; + }; + struct { /* STRP15 */ + uint32_t :3, + cs_ss6 :2, + :1, + IWL_EN :1, + :1, + t209min :2, + :22; + }; + }ibex; + }; +}; + +struct ich_desc_upper_map { + union { + uint32_t FLUMAP1; /* Flash Upper Map 1 */ + struct { + uint32_t VTBA :8, /* ME VSCC Table Base Address */ + VTL :8, /* ME VSCC Table Length */ + :16; + }; + }; + struct { + union { /* JEDEC-ID Register */ + uint32_t JID; + struct { + uint32_t vid :8, /* Vendor ID */ + cid0 :8, /* Component ID 0 */ + cid1 :8, /* Component ID 1 */ + :8; + }; + }; + union { /* Vendor Specific Component Capabilities */ + uint32_t VSCC; + struct { + uint32_t ubes :2, /* Upper Block/Sector Erase Size */ + uwg :1, /* Upper Write Granularity */ + uwsr :1, /* Upper Write Status Required */ + uwews :1, /* Upper Write Enable on Write Status */ + :3, + ueo :8, /* Upper Erase Opcode */ + lbes :2, /* Lower Block/Sector Erase Size */ + lwg :1, /* Lower Write Granularity */ + lwsr :1, /* Lower Write Status Required */ + lwews :1, /* Lower Write Enable on Write Status */ + :3, + leo :16; /* Lower Erase Opcode */ + }; + }; + } vscc_table[128]; +}; +#endif /* ICH_DESCRIPTORS_FROM_DUMP */ + struct ich_descriptors { struct ich_desc_content content; struct ich_desc_component component; struct ich_desc_region region; struct ich_desc_master master; +#ifdef ICH_DESCRIPTORS_FROM_DUMP + struct ich_desc_north_strap north; + struct ich_desc_south_strap south; + struct ich_desc_upper_map upper; +#endif /* ICH_DESCRIPTORS_FROM_DUMP */ }; void prettyprint_ich_descriptors(enum ich_chipset, const struct ich_descriptors *desc); @@ -254,8 +449,18 @@ void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc); void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc); void prettyprint_ich_descriptor_master(const struct ich_desc_master *master); +#ifdef ICH_DESCRIPTORS_FROM_DUMP + +void prettyprint_ich_descriptor_upper_map(const struct ich_desc_upper_map *umap); +void prettyprint_ich_descriptor_straps(enum ich_chipset cs, const struct ich_descriptors *desc); +int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, enum ich_chipset cs, struct ich_descriptors *desc); + +#else /* ICH_DESCRIPTORS_FROM_DUMP */ + int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc); +int getFCBA_component_density(uint8_t idx, const struct ich_descriptors *desc); +#endif /* ICH_DESCRIPTORS_FROM_DUMP */ #endif /* BITFIELDS == 1 */ #endif /* __ICH_DESCRIPTORS_H__ */ #endif /* defined(__i386__) || defined(__x86_64__) */ diff --git a/util/ich_descriptors_tool/Makefile b/util/ich_descriptors_tool/Makefile new file mode 100644 index 0000000..1af90ce --- /dev/null +++ b/util/ich_descriptors_tool/Makefile @@ -0,0 +1,42 @@ +CC ?= gcc + +PROGRAM=ich_descriptors_tool +EXTRAINCDIRS = ../../ . +DEPPATH = .dep +OBJATH = .obj +SHAREDSRC = ich_descriptors.c +SHAREDSRCDIR = ../.. + +SRC = $(wildcard *.c) + +CFLAGS += -Wall +CFLAGS += -MMD -MP -MF $(DEPPATH)/$((a)F).d +# enables functions that populate the descriptor structs from plain binary dumps +CFLAGS += -D ICH_DESCRIPTORS_FROM_DUMP +CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) + +OBJ = $(OBJATH)/$(SRC:%.c=%.o) + +SHAREDOBJ = $(OBJATH)/$(notdir $(SHAREDSRC:%.c=%.o)) + +all:$(PROGRAM) + +$(OBJ): $(OBJATH)/%.o : %.c + $(CC) $(CFLAGS) -o $@ -c $< + +# this enables us to share source files without simultaneously sharing .o files +# with flashrom, which would lead to unexpected results (w/o running make clean) +$(SHAREDOBJ): $(OBJATH)/%.o : $(SHAREDSRCDIR)/%.c + $(CC) $(CFLAGS) -o $@ -c $< + +$(PROGRAM): $(OBJ) $(SHAREDOBJ) + $(CC) -o $(PROGRAM) $(OBJ) $(SHAREDOBJ) + +clean: + rm -f $(PROGRAM) + rm -rf $(DEPPATH) $(OBJATH) + +# Include the dependency files. +-include $(shell mkdir -p $(DEPPATH) $(OBJATH) 2>/dev/null) $(wildcard $(DEPPATH)/*) + +.PHONY: all clean diff --git a/util/ich_descriptors_tool/TODO b/util/ich_descriptors_tool/TODO new file mode 100644 index 0000000..03701bf --- /dev/null +++ b/util/ich_descriptors_tool/TODO @@ -0,0 +1,6 @@ +- reverse the path, as in assemble a descriptormode image from various + blobs (BIOS, GbE, ME, OEM) and a description (xml? custom config? + sane defaults and cmd-line switches?) +- dump 256 OEM bytes +- handle descriptors of various chipsets correctly +- little endian only diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c new file mode 100644 index 0000000..3721eb4 --- /dev/null +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -0,0 +1,225 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (C) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * dump information and binaries from BIOS images that are in descriptor mode + */ +#include <stdio.h> +#include <stdint.h> +#include <stdlib.h> +#include <sys/mman.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <fcntl.h> +#include <unistd.h> +#include <string.h> +#include <errno.h> +#include "ich_descriptors.h" + +static void dump_file(const char *basename, const uint32_t *dump, unsigned int len, struct ich_desc_region *reg, unsigned int i) +{ + int ret; + char *fn; + const char *reg_name; + uint32_t file_len; + const char *const region_names[5] = { + "Descriptor", "BIOS", "ME", "GbE", "Platform" + }; + uint32_t base = ICH_FREG_BASE(reg->FLREGs[i]); + uint32_t limit = ICH_FREG_LIMIT(reg->FLREGs[i]); + + reg_name = region_names[i]; + if (base > limit) { + printf("The %s region is unused and thus not dumped.\n", + reg_name); + return; + } + + limit = limit | 0x0fff; + file_len = limit + 1 - base; + if (base + file_len > len) { + printf("The %s region is spanning 0x%08x-0x%08x, but it is " + "not (fully) included in the image (0-0x%08x), thus not " + "dumped.\n", reg_name, base, limit, len - 1); + return; + } + + fn = malloc(strlen(basename) + strlen(reg_name) + strlen(".bin") + 2); + if (!fn) { + fprintf(stderr, "Out of memory!\n"); + exit(1); + } + snprintf(fn, strlen(basename) + strlen(reg_name) + strlen(".bin") + 2, + "%s.%s.bin", basename, reg_name); + printf("Dumping %u bytes of the %s region from 0x%08x-0x%08x to %s... ", + file_len, region_names[i], base, limit, fn); + int fh = open(fn, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); + free(fn); + if (fh < 0) { + fprintf(stderr, + "ERROR: couldn't open(%s): %s\n", fn, strerror(errno)); + exit(1); + } + + ret = write(fh, &dump[base >> 2], file_len); + if (ret != file_len) { + fprintf(stderr, "FAILED.\n"); + exit(1); + } + + printf("done.\n"); + close(fh); +} + +void dump_files(const char *n, const uint32_t *buf, unsigned int len, struct ich_desc_region *reg) +{ + unsigned int i; + printf("=== Dumping region files ===\n"); + for (i = 0; i < 5; i++) + dump_file(n, buf, len, reg, i); + printf("\n"); +} + +static void usage(char *argv[], char *error) +{ + if (error != NULL) { + fprintf(stderr, "%s\n", error); + } + printf("usage: '%s -f <image file name> [-c <chipset name>] [-d]'\n\n" +"where <image file name> points to an image of the contents of the SPI flash.\n" +"In case that image is really in descriptor mode %s\n" +"will pretty print some of the contained information.\n" +"To also print the data stored in the descriptor strap you have to indicate\n" +"the chipset series with the '-c' parameter and one of the possible arguments:\n" +"\t- \"ich8\",\n" +"\t- \"ich9\",\n" +"\t- \"ich10\",\n" +"\t- \"5\" or \"ibex\" for Intel's 5 series chipsets,\n" +"\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n" +"\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n" +"If '-d' is specified some regions such as the BIOS image as seen by the CPU or\n" +"the GbE blob that is required to initialize the GbE are also dumped to files.\n", + argv[0], argv[0]); + exit(1); +} + +int main(int argc, char *argv[]) +{ + int fd; /* file descriptor to flash file */ + int len; /* file/buffer size in bytes */ + uint32_t *buf; /* mmap'd file */ + + int opt; + int ret; + int dump = 0; + const char *fn = NULL; + const char *csn = NULL; + enum ich_chipset cs = CHIPSET_ICH_UNKNOWN; + struct ich_descriptors desc = {{ 0 }}; + + while ((opt = getopt(argc, argv, "df:c:")) != -1) { + switch (opt) { + case 'd': + dump = 1; + break; + case 'f': + fn = optarg; + break; + case 'c': + csn = optarg; + break; + default: /* '?' */ + usage(argv, NULL); + } + } + if (fn == NULL) + usage(argv, + "Need a file name of a descriptor image to read from."); + + fd = open(fn, O_RDONLY); + if (fd < 0) + usage(argv, "No such file"); + len = lseek(fd, 0, SEEK_END); + if (len < 0) + usage(argv, "Seeking to the end of the file failed"); + + buf = mmap(NULL, len, PROT_READ, MAP_PRIVATE, fd, 0); + if (buf == (void *) -1) { + /* fallback for stupid OSes like cygwin */ + int ret; + buf = malloc(len); + if (!buf) + usage(argv, "Could not allocate memory"); + lseek(fd, 0, SEEK_SET); + ret = read(fd, buf, len); + if (ret != len) + usage(argv, "Seeking to the end of the file failed"); + } + printf("The flash image has a size of %d [0x%x] bytes.\n", len, len); + close(fd); + + if (csn != NULL) { + if (strcmp(csn, "ich8") == 0) + cs = CHIPSET_ICH8; + else if (strcmp(csn, "ich9") == 0) + cs = CHIPSET_ICH9; + else if (strcmp(csn, "ich10") == 0) + cs = CHIPSET_ICH10; + else if ((strcmp(csn, "5") == 0) || + (strcmp(csn, "ibex") == 0)) + cs = CHIPSET_5_SERIES_IBEX_PEAK; + else if ((strcmp(csn, "6") == 0) || + (strcmp(csn, "cougar") == 0)) + cs = CHIPSET_6_SERIES_COUGAR_POINT; + else if ((strcmp(csn, "7") == 0) || + (strcmp(csn, "panther") == 0)) + cs = CHIPSET_7_SERIES_PANTHER_POINT; + } + + ret = read_ich_descriptors_from_dump(buf, len, cs, &desc); + switch (ret) { + case RET_OK: + break; + case RET_ERR: + printf("Image not in descriptor mode.\n"); + exit(1); + case RET_OOB: + printf("Tried to access a location out of bounds of the image. " + "- Corrupt image?\n"); + exit(1); + default: + printf("Unhandled return value at %s:%u, please report this.\n", + __FILE__, __LINE__); + exit(1); + } + + prettyprint_ich_descriptors(cs, &desc); + + //uint8_t *pMAC = (uint8_t *) &buf[r->reg3_base >> 2]; + //printf("The MAC-address might be: %02x:%02x:%02x:%02x:%02x:%02x\n", + //pMAC[0], pMAC[1], pMAC[2], pMAC[3], pMAC[4], pMAC[5]); + + if (dump == 1) + dump_files(fn, buf, len, &desc.region); + + return 0; +} + -- 1.7.1

1 0

[PATCH 5/6] ichspi: add support for Intel Hardware Sequencing
by Stefan Tauner 14 Aug '11

14 Aug '11

todo: - revise hwseq activation: when should hwseq be used, when swseq? in the current version i have added a programmer parameter to tell flashrom when one wants to use hwseq _if it is available_ (i.e. descriptor valid), example: flashrom -p internal:laptop=force_I_want_a_brick,hwseq=yes -VV this needs to be documented in the man page if it gets merged like that. - commit message (is a link to my blog post a good idea (additionally)?) - revise (levels of) prints - revise timeout values (for optimal performance) - build upon the upcoming opaque interface framework instead Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipdrivers.h | 6 + flashchips.c | 23 ++++- flashchips.h | 2 + ichspi.c | 352 +++++++++++++++++++++++++++++++++++++++++++++++++++++++-- programmer.h | 1 + 5 files changed, 373 insertions(+), 11 deletions(-) diff --git a/chipdrivers.h b/chipdrivers.h index 92ddbea..f97e2ad 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -84,6 +84,12 @@ void print_status_82802ab(uint8_t status); int unlock_82802ab(struct flashchip *flash); int unlock_28f004s5(struct flashchip *flash); +/* ichspi.c */ +int ich_hwseq_probe(struct flashchip *flash); +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int start, int len); +int ich_hwseq_block_erase(struct flashchip *flash, unsigned int addr, unsigned int blocklen); +int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); + /* jedec.c */ uint8_t oddparity(uint8_t val); void toggle_ready_jedec(chipaddr dst); diff --git a/flashchips.c b/flashchips.c index 1a5622f..041b9a5 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8752,7 +8752,27 @@ const struct flashchip flashchips[] = { .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program */ }, - +#if defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) + { + .vendor = "Intel", + .name = "Hardware Sequencing", + .bustype = BUS_SPI, + .manufacture_id = INTEL_ID, + .model_id = INTEL_HWSEQ, + .total_size = 0, + .page_size = 256, + .tested = TEST_OK_PREW, + .probe = ich_hwseq_probe, + .block_erasers = + { + { /* erase blocks will be set by the probing function */ + .block_erase = ich_hwseq_block_erase, + } + }, + .write = ich_hwseq_write_256, + .read = ich_hwseq_read, + }, +#endif // defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) { .vendor = "AMIC", .name = "unknown AMIC SPI chip", @@ -8885,6 +8905,7 @@ const struct flashchip flashchips[] = { .probe = probe_spi_rdid, .write = NULL, }, + { .vendor = "Generic", .name = "unknown SPI chip (REMS)", diff --git a/flashchips.h b/flashchips.h index ff49d31..1374b2f 100644 --- a/flashchips.h +++ b/flashchips.h @@ -346,6 +346,8 @@ #define SHARP_LH28F008SA 0xA2 /* Sharp chip, Intel Vendor ID */ #define SHARP_LH28F008SC 0xA6 /* Sharp chip, Intel Vendor ID */ +#define INTEL_HWSEQ 0xFFFE /* dummy ID for hardware sequencing */ + #define ISSI_ID 0xD5 /* ISSI Integrated Silicon Solutions */ /* diff --git a/ichspi.c b/ichspi.c index 737613b..eaaf98e 100644 --- a/ichspi.c +++ b/ichspi.c @@ -26,7 +26,9 @@ #if defined(__i386__) || defined(__x86_64__) #include <string.h> +#include <stdlib.h> #include "flash.h" +#include "flashchips.h" #include "chipdrivers.h" #include "programmer.h" #include "spi.h" @@ -1084,6 +1086,298 @@ static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, return result; } +static struct hwseq { + uint32_t size_comp0; + uint32_t size_comp1; +} hwseq; + +static void ich_hwseq_set_addr(uint32_t addr) +{ + uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF; + REGWRITE32(ICH9_REG_FADDR, (addr & 0x01FFFFFF) | addr_old); +} + +/* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes + * of the block containing this address. */ +static uint32_t ich_hwseq_get_erase_block_size(unsigned int addr) +{ + uint8_t enc_berase; + static const uint32_t const dec_berase[4] = { + 256, + 4 * 1024, + 8 * 1024, + 64 * 1024 + }; + + ich_hwseq_set_addr(addr); + enc_berase = (REGREAD16(ICH9_REG_HSFS) & HSFS_BERASE) >> + HSFS_BERASE_OFF; + return dec_berase[enc_berase]; +} + +/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 10 us intervals. + Resets all error flags in HSFS. + Returns 0 if the cycle completes successfully without errors within + timeout us, 1 on errors. */ +static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, + unsigned int len) +{ + uint16_t hsfs; + uint32_t addr; + + while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) & + (HSFS_FDONE | HSFS_FCERR)) == 0) && + --timeout) { + programmer_delay(10); + } + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + if (!timeout) { + addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; + msg_perr("Timeout error between offset 0x%08x and " + "0x%08x + %d (=0x%08x)!\n", + addr, addr, len - 1, addr + len - 1); + prettyprint_ich9_reg_hsfs(hsfs); + prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); + return 1; + } + + if (hsfs & HSFS_FCERR) { + addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; + msg_perr("Transaction error between offset 0x%08x and " + "0x%08x (=0x%08x + %d)!\n", + addr, addr + len - 1, addr, len - 1); + prettyprint_ich9_reg_hsfs(hsfs); + prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); + return 1; + } + return 0; +} + +int ich_hwseq_probe(struct flashchip *flash) +{ + uint32_t total_size, boundary; + uint32_t erase_size_low, size_low, erase_size_high, size_high; + struct block_eraser *eraser; + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_cerr("This chip (%s) is not supported in hardware" + "sequencing mode and should never have been probed.\n", + flash->name); + msg_cerr("%s: Please report a bug at flashrom(a)flashrom.org\n", + __func__); + return 0; + } + + msg_cdbg("Prerequisites for Intel Hardware Sequencing are "); + if (spi_programmer->type != SPI_CONTROLLER_ICH_HWSEQ) { + msg_cdbg("not met.\n"); + return 0; + } + msg_cdbg("met.\n"); + + total_size = hwseq.size_comp0 + hwseq.size_comp1; + msg_cdbg("Found %d attached SPI flash chip", + (hwseq.size_comp1 != 0) ? 2 : 1); + if (hwseq.size_comp1 != 0) + msg_cdbg("s with a combined"); + else + msg_cdbg(" with a"); + msg_cdbg(" density of %d kB.\n", total_size / 1024); + flash->total_size = total_size / 1024; + + eraser = &(flash->block_erasers[0]); + boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12; + size_high = total_size - boundary; + erase_size_high = ich_hwseq_get_erase_block_size(boundary); + + if (boundary == 0) { + msg_cdbg("There is only one partition containing the whole " + "address space (0x%06x - 0x%06x).\n", 0, size_high-1); + eraser->eraseblocks[0].size = erase_size_high; + eraser->eraseblocks[0].count = size_high / erase_size_high; + msg_cdbg("There are %d erase blocks with %d B each.\n", + size_high / erase_size_high, erase_size_high); + } else { + msg_cdbg("The flash address space (0x%06x - 0x%06x) is divided " + "at address 0x%06x in two partitions.\n", + 0, size_high-1, boundary); + size_low = total_size - size_high; + erase_size_low = ich_hwseq_get_erase_block_size(0); + + eraser->eraseblocks[0].size = erase_size_low; + eraser->eraseblocks[0].count = size_low / erase_size_low; + msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n", + 0, size_low-1); + msg_cdbg("In that range are %d erase blocks with %d B each.\n", + size_low / erase_size_low, erase_size_low); + + eraser->eraseblocks[1].size = erase_size_high; + eraser->eraseblocks[1].count = size_high / erase_size_high; + msg_cdbg("The second partition ranges from 0x%06x to 0x%06x.\n", + boundary, size_high-1); + msg_cdbg("In that range are %d erase blocks with %d B each.\n", + size_high / erase_size_high, erase_size_high); + } + return 1; +} + +static int ich_hwseq_send_command(unsigned int writecnt, + unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + msg_pdbg("skipped. Intel Hardware Sequencing does not support sending " + "arbitrary commands."); + return -1; +} + +int ich_hwseq_block_erase(struct flashchip *flash, + unsigned int addr, + unsigned int len) +{ + uint32_t erase_block; + uint16_t hsfc; + uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */ + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode\n", flash->name); + return -1; + } + + erase_block = ich_hwseq_get_erase_block_size(addr); + if (len != erase_block) { + msg_cerr("Erase block size for address 0x%06x is %d B, " + "but requested erase block size is %d B. " + "Not erasing anything.\n", addr, erase_block, len); + return -1; + } + + /* Although the hardware supports this (it would erase the whole block + * containing the address) we play safe here. */ + if (addr % erase_block != 0) { + msg_cerr("Erase address 0x%06x is not aligned to the erase " + "block boundary (any multiple of %d). " + "Not erasing anything.\n", addr, erase_block); + return -1; + } + + if (addr + len > flash->total_size * 1024) { + msg_perr("Request to erase some inaccessible memory address(es)" + " (addr=0x%x, len=%d). " + "Not erasing anything.\n", addr, len); + return -1; + } + + msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr); + + /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ + hsfc |= HSFC_FGO; /* start */ + msg_pdbg("HSFC used for block erasing: "); + prettyprint_ich9_reg_hsfc(hsfc); + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, len)) + return -1; + return 0; +} + +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int addr, int len) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode.\n", flash->name); + return -1; + } + + if (addr < 0 || addr + len > flash->total_size * 1024) { + msg_perr("Request to read from an inaccessible memory address " + "(addr=0x%x, len=%d).\n", addr, len); + return -1; + } + + msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + while (len > 0) { + block_len = min(len, spi_programmer->max_data_read); + ich_hwseq_set_addr(addr); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* set read operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + return 1; + ich_read_data(buf, block_len, ICH9_REG_FDATA0); + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} + +int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, int addr, int len) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode\n", flash->name); + return -1; + } + + if (addr < 0 || addr + len > flash->total_size * 1024) { + msg_perr("Request to write to an inaccessible memory address " + "(addr=0x%x, len=%d).\n", addr, len); + return -1; + } + + msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + while (len > 0) { + ich_hwseq_set_addr(addr); + block_len = min(len, spi_programmer->max_data_write); + ich_fill_data(buf, block_len, ICH9_REG_FDATA0); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + return -1; + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} + static int ich_spi_send_multicommand(struct spi_command *cmds) { int ret = 0; @@ -1207,6 +1501,16 @@ static const struct spi_programmer spi_programmer_ich9 = { .write_256 = default_spi_write_256, }; +static const struct spi_programmer spi_programmer_ich_hwseq = { + .type = SPI_CONTROLLER_ICH_HWSEQ, + .max_data_read = 64, + .max_data_write = 64, + .command = ich_hwseq_send_command, + .multicommand = default_spi_send_multicommand, + .read = ich_hwseq_read, + .write_256 = ich_hwseq_write_256, +}; + int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, int ich_generation) { @@ -1214,21 +1518,20 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, uint8_t old, new; uint16_t spibar_offset, tmp2; uint32_t tmp; + char *arg; int ichspi_desc = 0; + int hwseq_en = 0; switch (ich_generation) { case 7: - register_spi_programmer(&spi_programmer_ich7); spibar_offset = 0x3020; break; case 8: - register_spi_programmer(&spi_programmer_ich9); spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ - register_spi_programmer(&spi_programmer_ich9); spibar_offset = 0x3800; break; } @@ -1239,8 +1542,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, /* Assign Virtual Address */ ich_spibar = rcrb + spibar_offset; - switch (spi_programmer->type) { - case SPI_CONTROLLER_ICH7: + switch (ich_generation) { + case 7: msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", @@ -1277,9 +1580,21 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, ichspi_lock = 1; } ich_set_bbar(0); + register_spi_programmer(&spi_programmer_ich7); ich_init_opcodes(); break; - case SPI_CONTROLLER_ICH9: + case 8: + case 9: + case 10: + default: /* Future version might behave the same */ + arg = extract_programmer_param("hwseq"); + if (arg && !strcmp(arg, "yes")) + hwseq_en = 1; + else if (arg && !strlen(arg)) + msg_pinfo("Missing argument for hwseq.\n"); + else if (arg) + msg_pinfo("Unknown argument for hwseq: %s\n", arg); + free(arg); tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); prettyprint_ich9_reg_hsfs(tmp2); @@ -1363,19 +1678,36 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pdbg("\n"); #if BITFIELDS == 1 + { /* to be able to declare desc here and avoid another + * "#if BITFIELDS == 1" on top + */ + struct ich_descriptors desc = {{ 0 }}; if (ichspi_desc) { - struct ich_descriptors desc = {{ 0 }}; if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == RET_OK) prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, &desc); + /* If the descriptor is valid and indicates multiple + * flash devices we need to use hwseq to be able to + * access the second flash device. + */ + if (desc.content.NC != 0) + hwseq_en = 1; + } else + hwseq_en = 0; /* disable it even if the user said yes */ + + if (hwseq_en > 0) { + hwseq.size_comp0 = getFCBA_component_density(0, &desc); + hwseq.size_comp1 = getFCBA_component_density(1, &desc); + register_spi_programmer(&spi_programmer_ich_hwseq); + } else { + register_spi_programmer(&spi_programmer_ich9); + ich_init_opcodes(); + } } #endif /* BITFIELDS == 1 */ ich_init_opcodes(); break; - default: - /* Nothing */ - break; } old = pci_read_byte(dev, 0xdc); diff --git a/programmer.h b/programmer.h index 6a28dbe..6e316d1 100644 --- a/programmer.h +++ b/programmer.h @@ -517,6 +517,7 @@ enum spi_controller { #if defined(__i386__) || defined(__x86_64__) SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, + SPI_CONTROLLER_ICH_HWSEQ, SPI_CONTROLLER_IT85XX, SPI_CONTROLLER_IT87XX, SPI_CONTROLLER_SB600, -- 1.7.1

1 0

[PATCH 4/6] ichspi: improve prettyprint_opcodes
by Stefan Tauner 14 Aug '11

14 Aug '11

add headers for the columns and some decoding into human readable format. --- before: […] Reading OPCODES... done preop0=0x06, preop1=0x50 op[0]=0x02, 3, 0 op[1]=0x03, 2, 0 op[2]=0x20, 3, 0 op[3]=0x05, 0, 0 op[4]=0x9f, 0, 1 op[5]=0x20, 1, 2 op[6]=0x01, 1, 0 op[7]=0x06, 0, 0 SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: FWH, SPI. […] after: […] Reading OPCODES... done OP Type Pre-OP op[0]: 0x02, write w/ addr, none op[1]: 0x03, read w/ addr, none op[2]: 0x20, write w/ addr, none op[3]: 0x05, read w/o addr, none op[4]: 0x9f, read w/o addr, none op[5]: 0x20, write w/o addr, 1 op[6]: 0x01, write w/o addr, 2 op[7]: 0x06, read w/o addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x50 SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: FWH, SPI. […] i could also print the preops directly in the preop column instead of using that redirection. but i think as debug output it is better to know the index of the two preops too. side note: does it make sense to create an opcode -> string decoder for flashrom-wide usage in user output (in spi25.c)? an erase opcode -> function pointer decoder is used in sfdp, that could also be generalized like that. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 34 +++++++++++++++++++++++----------- 1 files changed, 23 insertions(+), 11 deletions(-) diff --git a/ichspi.c b/ichspi.c index daa4a8a..737613b 100644 --- a/ichspi.c +++ b/ichspi.c @@ -295,22 +295,34 @@ static OPCODES O_EXISTING = {}; /* pretty printing functions */ static void prettyprint_opcodes(OPCODES *ops) { - if(ops == NULL) - return; - - msg_pdbg("preop0=0x%02x, preop1=0x%02x\n", ops->preop[0], - ops->preop[1]); - OPCODE oc; + const char *t; + const char *a; uint8_t i; + static const char *const spi_type[4] = { + "read w/o addr", + "write w/o addr", + "read w/ addr", + "write w/ addr" + }; + static const char *const atomic_type[3] = { + "none", + " 0 ", + " 1 " + }; + + if (ops == NULL) + return; + + msg_pdbg(" OP Type Pre-OP\n"); for (i = 0; i < 8; i++) { oc = ops->opcode[i]; - msg_pdbg("op[%d]=0x%02x, %d, %d\n", - i, - oc.opcode, - oc.spi_type, - oc.atomic); + t = (oc.spi_type > 3) ? "invalid" : spi_type[oc.spi_type]; + a = (oc.atomic > 2) ? "invalid" : atomic_type[oc.atomic]; + msg_pdbg("op[%d]: 0x%02x, %s, %s\n", i, oc.opcode, t, a); } + msg_pdbg("Pre-OP 0: 0x%02x, Pre-OP 1: 0x%02x\n", ops->preop[0], + ops->preop[1]); } #define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) -- 1.7.1

1 0

[PATCH 3/6] ichspi: don't touch the nonexistent(?) BBAR register on ICH8
by Stefan Tauner 14 Aug '11

14 Aug '11

There is no sign of BBAR (BIOS Base Address Configuration Register) in the public datasheet (or specification update) of the ICH8. Also, the offset of that register has changed between ICH7 (SPIBAR + 50h) and ICH9 (SPIBAR + A0h), so we have no clue if or where it is on ICH8. Better don't try to touch it at all and assume/hope it is 0. --- Until now we implicitly accessed it via the ICH9 offset. I think this is an evident sign that the naming of the spi controller types in ichspi.c (SPI_CONTROLLER_VIA, SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9) might not cut it and we should think about introducing a special ICH8 one, even if its struct is identical to the ICH9. having most of the ICH8 code path guarded/controlled by SPI_CONTROLLER_ICH7 or SPI_CONTROLLER_ICH9 (depending on which is more similar in one situation), is an open invitation to similar bugs because one easily forgets that ICH8 is very special. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 8 +++----- 1 files changed, 3 insertions(+), 5 deletions(-) diff --git a/ichspi.c b/ichspi.c index 85f82fa..daa4a8a 100644 --- a/ichspi.c +++ b/ichspi.c @@ -658,11 +658,6 @@ static int ich_init_opcodes(void) msg_pdbg("Programming OPCODES... "); curopcodes_done = &O_ST_M25P; rc = program_opcodes(curopcodes_done, 1); - /* Technically not part of opcode init, but it allows opcodes - * to run without transaction errors by setting the lowest - * allowed address to zero. - */ - ich_set_bbar(0); } if (rc) { @@ -1269,6 +1264,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } + ich_set_bbar(0); ich_init_opcodes(); break; case SPI_CONTROLLER_ICH9: @@ -1350,6 +1346,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + ich_set_bbar(0); } msg_pdbg("\n"); @@ -1440,6 +1437,7 @@ int via_init_spi(struct pci_dev *dev) ichspi_lock = 1; } + ich_set_bbar(0); ich_init_opcodes(); return 0; -- 1.7.1

1 0

[PATCH 2/6] ichspi: disable writes when locked or read-only regions are detected
by Stefan Tauner 14 Aug '11

14 Aug '11

Until we are able to unlock regions or at least understand better what consequences writing single regions have, disable writing completely whenever a non-writeable region is detected. NB: the registers might not always reflect the real access status. http://www.flashrom.org/pipermail/flashrom/2011-April/006309.html (this is the sole such report i can remember) --- Might not be the best location to do this, but currently i don't recognize a better one. The warnings are repeated for each non-writeable region. We could surpress it by checking if programmer_may_write is already 0 before printing. the output on my thinkpad is: […] Proceeding anyway because user specified laptop=force_I_want_a_brick Found chipset "Intel QS57". Enabling flash write... WARNING: SPI Configuration Lockdown activated. WARNING: Flash Descriptor region is read-only. Disabling writes. WARNING: Management Engine region is locked. Disabling writes. OK. This chipset supports the following protocols: FWH, SPI. Found Winbond flash chip "W25X64" (8192 kB, SPI) at physical address 0xff800000. […] verbose output is: […] 0x54: 0x00000000 (FREG0: Flash Descriptor) 0x00000000-0x00000fff is read-only WARNING: Flash Descriptor region is read-only. Disabling writes. 0x58: 0x07ff0500 (FREG1: BIOS) 0x00500000-0x007fffff is read-write 0x5C: 0x04ff0003 (FREG2: Management Engine) 0x00003000-0x004fffff is locked WARNING: Management Engine region is locked. Disabling writes. 0x60: 0x00020001 (FREG3: Gigabit Ethernet) 0x00001000-0x00002fff is read-write 0x64: 0x00000fff (FREG4: Platform Data) Platform Data region is unused. […] i think that is ok. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/ichspi.c b/ichspi.c index 611f054..85f82fa 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1169,6 +1169,15 @@ static void do_ich9_spi_frap(uint32_t frap, int i) msg_pdbg("0x%08x-0x%08x is %s\n", base, (limit | 0x0fff), access_names[rwperms]); + if (rwperms <= 0x1) { + msg_pinfo("WARNING: %s region is %s. Disabling writes.\n", + region_names[i], access_names[rwperms]); + /* FIXME: This needs some refinement when we know how unlocking + * of region works. + */ + programmer_may_write = 0; + } + } static const struct spi_programmer spi_programmer_ich7 = { -- 1.7.1

1 0

[PATCH 1/6] ichspi: add ICH/PCH flash descriptor decoding via FDOC/FDOD
by Stefan Tauner 14 Aug '11

14 Aug '11

based on the work of Matthias 'mazzoo' Wenzel this patch adds pretty printing of those ICH/PCH flash descriptor sections that are cached/mapped by the chipset (and which are therefore reachable via FDOC/FDOD registers). this includes the following: - content section: describes the image and some generic properties (number of sections, offset of sections, PCH/ICH and MCH/PROC strap offsets and lengths) - component section: identify the different SPI flash chips and their capabilities. - region section similarly to a partition table this describes the different regions. the content of FLREG* is derived from this section. - master section defines SPI master (host, ME, GbE) access rights of the individual regions. the content of PR* is derived from this section. this is only a part of the data included in the descriptor. other information can be retrieved from a complete binary dump of the descriptor region only. this patch also adds macros and pretty printing for "Vendor Specific Component Capabilities" registers: there are two of them: lower and upper. they describe the properties of the address space divided by FPBA (which allows to use multiple flash chips or partitions with different properties). the properties of all supported flash chips (together with their RDIDs) are stored in the same format in table in a descriptor section (which is used by the ME apparently). a later patch will use the macros outside of ichspi.c which is the reason why the prettyprinting function and the register bit macros are not defined in ichspi.c but ich_descriptors.h (else they would be moved in the follow-up patch). because this patch relies on (compiler) implementation-specific layouting of bit-fields, it checks for basic compiler support in the makefile and for correct layout before taking any action on runtime. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- Makefile | 22 ++++- ich_descriptors.c | 288 +++++++++++++++++++++++++++++++++++++++++++++++++++++ ich_descriptors.h | 261 ++++++++++++++++++++++++++++++++++++++++++++++++ ichspi.c | 60 +++++++++-- 4 files changed, 619 insertions(+), 12 deletions(-) create mode 100644 ich_descriptors.c create mode 100644 ich_descriptors.h diff --git a/Makefile b/Makefile index e0b45ec..930ea4a 100644 --- a/Makefile +++ b/Makefile @@ -340,9 +340,11 @@ endif ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' +FEATURE_CFLAGS += $(shell LC_ALL=C grep -q "BITFIELDS := yes" .features && printf "%s" "-D'BITFIELDS=1'") PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o ifeq ($(ARCH),"x86") -PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += it87spi.o it85spi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += ichspi.o ich_descriptors.o else endif NEED_PCI := yes @@ -583,6 +585,19 @@ int main(int argc, char **argv) endef export UTSNAME_TEST +define BITFIELDS_TEST +#include "ich_descriptors.h" +int main(int argc, char **argv) +{ + struct ich_descriptors desc; + (void) argc; + (void) argv; + desc.region.FLREGs[4] = 0x5aa5a55a; + return desc.region.reg4_base; +} +endef +export BITFIELDS_TEST + compiler: featuresavailable @printf "Checking for a C compiler... " @echo "$$COMPILER_TEST" > .test.c @@ -648,6 +663,11 @@ endif @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) >/dev/null 2>&1 && \ ( echo "found."; echo "UTSNAME := yes" >> .features.tmp ) || \ ( echo "not found."; echo "UTSNAME := no" >> .features.tmp ) + @printf "Checking if bit-fields support is sufficient... " + @echo "$$BITFIELDS_TEST" > .featuretest.c + @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) -D BITFIELDS .featuretest.c -o .featuretest$(EXEC_SUFFIX) >/dev/null 2>&1 && \ + ( echo "yes."; echo "BITFIELDS := yes" >> .features.tmp ) || \ + ( echo "no."; echo "BITFIELDS := no" >> .features.tmp ) @$(DIFF) -q .features.tmp .features >/dev/null 2>&1 && rm .features.tmp || mv .features.tmp .features @rm -f .featuretest.c .featuretest$(EXEC_SUFFIX) diff --git a/ich_descriptors.c b/ich_descriptors.c new file mode 100644 index 0000000..ce40d9f --- /dev/null +++ b/ich_descriptors.c @@ -0,0 +1,288 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (c) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if defined(__i386__) || defined(__x86_64__) + +#include "ich_descriptors.h" +#include "flash.h" /* for msg_* */ +#include "programmer.h" + +void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity) +{ + print(verbosity, "BES=0x%x, ", (reg_val & VSCC_BES) >> VSCC_BES_OFF); + print(verbosity, "WG=%d, ", (reg_val & VSCC_WG) >> VSCC_WG_OFF); + print(verbosity, "WSR=%d, ", (reg_val & VSCC_WSR) >> VSCC_WSR_OFF); + print(verbosity, "WEWS=%d, ", (reg_val & VSCC_WEWS) >> VSCC_WEWS_OFF); + print(verbosity, "EO=0x%x, ", (reg_val & VSCC_EO) >> VSCC_EO_OFF); + print(verbosity, "VCL=%d\n", (reg_val & VSCC_VCL) >> VSCC_VCL_OFF); +} + +#if BITFIELDS == 1 +#define getFCBA(cont) (((cont)->FLMAP0 << 4) & 0x00000ff0) +#define getFRBA(cont) (((cont)->FLMAP0 >> 12) & 0x00000ff0) +#define getFMBA(cont) (((cont)->FLMAP1 << 4) & 0x00000ff0) +#define getFISBA(cont) (((cont)->FLMAP1 >> 12) & 0x00000ff0) +#define getFMSBA(cont) (((cont)->FLMAP2 << 4) & 0x00000ff0) + +void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc) +{ + prettyprint_ich_descriptor_content(&desc->content); + prettyprint_ich_descriptor_component(desc); + prettyprint_ich_descriptor_region(desc); + prettyprint_ich_descriptor_master(&desc->master); +} + +void prettyprint_ich_descriptor_content(const struct ich_desc_content *cont) +{ + msg_pdbg2("=== Content Section ===\n"); + msg_pdbg2("FLVALSIG 0x%08x\n", cont->FLVALSIG); + msg_pdbg2("FLMAP0 0x%08x\n", cont->FLMAP0); + msg_pdbg2("FLMAP1 0x%08x\n", cont->FLMAP1); + msg_pdbg2("FLMAP2 0x%08x\n", cont->FLMAP2); + msg_pdbg2("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2("NR (Number of Regions): %5d\n", + cont->NR + 1); + msg_pdbg2("FRBA (Flash Region Base Address): 0x%03x\n", + getFRBA(cont)); + msg_pdbg2("NC (Number of Components): %5d\n", + cont->NC + 1); + msg_pdbg2("FCBA (Flash Component Base Address): 0x%03x\n", + getFCBA(cont)); + msg_pdbg2("ISL (ICH/PCH Strap Length): %5d\n", + cont->ISL); + msg_pdbg2("FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x%03x\n", + getFISBA(cont)); + msg_pdbg2("NM (Number of Masters): %5d\n", + cont->NM + 1); + msg_pdbg2("FMBA (Flash Master Base Address): 0x%03x\n", + getFMBA(cont)); + msg_pdbg2("MSL/PSL (MCH/PROC Strap Length): %5d\n", + cont->MSL); + msg_pdbg2("FMSBA (Flash MCH/PROC Strap Base Address): 0x%03x\n", + getFMSBA(cont)); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc) +{ + static const char * const str_freq[8] = { + "20 MHz", /* 000 */ + "33 MHz", /* 001 */ + "reserved", /* 010 */ + "reserved", /* 011 */ + "50 MHz", /* 100 */ + "reserved", /* 101 */ + "reserved", /* 110 */ + "reserved" /* 111 */ + }; + static const char * const str_mem[8] = { + "512 kB", /* 000 */ + " 1 MB", /* 001 */ + " 2 MB", /* 010 */ + " 4 MB", /* 011 */ + " 8 MB", /* 100 */ + " 16 MB", /* 101 */ + "reserved", /* 110 */ + "reserved", /* 111 */ + }; + + msg_pdbg2("=== Component Section ===\n"); + msg_pdbg2("FLCOMP 0x%08x\n", desc->component.FLCOMP); + msg_pdbg2("FLILL 0x%08x\n", desc->component.FLILL ); + msg_pdbg2("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2("Component 1 density: %s\n", + str_mem[desc->component.comp1_density]); + if (desc->content.NC) + msg_pdbg2("Component 2 density: %s\n", + str_mem[desc->component.comp2_density]); + else + msg_pdbg2("Component 2 is not used.\n"); + msg_pdbg2("Read Clock Frequency: %s\n", + str_freq[desc->component.freq_read]); + msg_pdbg2("Read ID and Status Clock Freq.: %s\n", + str_freq[desc->component.freq_read_id]); + msg_pdbg2("Write and Erase Clock Freq.: %s\n", + str_freq[desc->component.freq_write]); + msg_pdbg2("Fast Read is %ssupported.\n", + desc->component.fastread ? "" : "not "); + if (desc->component.fastread) + msg_pdbg2("Fast Read Clock Frequency: %s\n", + str_freq[desc->component.freq_fastread]); + if (desc->component.FLILL == 0) + msg_pdbg2("No forbidden opcodes.\n"); + else { + msg_pdbg2("Invalid instruction 0: 0x%02x\n", + desc->component.invalid_instr0); + msg_pdbg2("Invalid instruction 1: 0x%02x\n", + desc->component.invalid_instr1); + msg_pdbg2("Invalid instruction 2: 0x%02x\n", + desc->component.invalid_instr2); + msg_pdbg2("Invalid instruction 3: 0x%02x\n", + desc->component.invalid_instr3); + } + msg_pdbg2("\n"); +} + +static void pprint_freg(const struct ich_desc_region *reg, uint32_t i) +{ + static const char *const region_names[5] = { + "Descr.", "BIOS", "ME", "GbE", "Platf." + }; + if (i >= 5) { + msg_pdbg2("%s: region index too high.\n", __func__); + return; + } + uint32_t base = ICH_FREG_BASE(reg->FLREGs[i]); + uint32_t limit = ICH_FREG_LIMIT(reg->FLREGs[i]); + msg_pdbg2("Region %d (%-6s) ", i, region_names[i]); + if (base > limit) + msg_pdbg2("is unused.\n"); + else + msg_pdbg2("0x%08x - 0x%08x\n", base, limit | 0x0fff); +} + +void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc) +{ + uint8_t i; + uint8_t nr = desc->content.NR + 1; + msg_pdbg2("=== Region Section ===\n"); + if (nr >= 5) { + msg_pdbg2("%s: number of regions too high (%d).\n", __func__, + nr); + return; + } + for (i = 0; i <= nr; i++) + msg_pdbg2("FLREG%d 0x%08x\n", i, desc->region.FLREGs[i]); + msg_pdbg2("\n"); + + msg_pdbg2("--- Details ---\n"); + for (i = 0; i <= nr; i++) + pprint_freg(&desc->region, i); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_master(const struct ich_desc_master *mstr) +{ + msg_pdbg2("=== Master Section ===\n"); + msg_pdbg2("FLMSTR1 0x%08x\n", mstr->FLMSTR1); + msg_pdbg2("FLMSTR2 0x%08x\n", mstr->FLMSTR2); + msg_pdbg2("FLMSTR3 0x%08x\n", mstr->FLMSTR3); + msg_pdbg2("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2(" Descr. BIOS ME GbE Platf.\n"); + msg_pdbg2("BIOS %c%c %c%c %c%c %c%c %c%c\n", + (mstr->BIOS_descr_r) ?'r':' ', (mstr->BIOS_descr_w) ?'w':' ', + (mstr->BIOS_BIOS_r) ?'r':' ', (mstr->BIOS_BIOS_w) ?'w':' ', + (mstr->BIOS_ME_r) ?'r':' ', (mstr->BIOS_ME_w) ?'w':' ', + (mstr->BIOS_GbE_r) ?'r':' ', (mstr->BIOS_GbE_w) ?'w':' ', + (mstr->BIOS_plat_r) ?'r':' ', (mstr->BIOS_plat_w) ?'w':' '); + msg_pdbg2("ME %c%c %c%c %c%c %c%c %c%c\n", + (mstr->ME_descr_r) ?'r':' ', (mstr->ME_descr_w) ?'w':' ', + (mstr->ME_BIOS_r) ?'r':' ', (mstr->ME_BIOS_w) ?'w':' ', + (mstr->ME_ME_r) ?'r':' ', (mstr->ME_ME_w) ?'w':' ', + (mstr->ME_GbE_r) ?'r':' ', (mstr->ME_GbE_w) ?'w':' ', + (mstr->ME_plat_r) ?'r':' ', (mstr->ME_plat_w) ?'w':' '); + msg_pdbg2("GbE %c%c %c%c %c%c %c%c %c%c\n", + (mstr->GbE_descr_r) ?'r':' ', (mstr->GbE_descr_w) ?'w':' ', + (mstr->GbE_BIOS_r) ?'r':' ', (mstr->GbE_BIOS_w) ?'w':' ', + (mstr->GbE_ME_r) ?'r':' ', (mstr->GbE_ME_w) ?'w':' ', + (mstr->GbE_GbE_r) ?'r':' ', (mstr->GbE_GbE_w) ?'w':' ', + (mstr->GbE_plat_r) ?'r':' ', (mstr->GbE_plat_w) ?'w':' '); + msg_pdbg2("\n"); +} + +static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) +{ + uint32_t control = 0; + control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS; + control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI; + mmio_le_writel(control, spibar + ICH9_REG_FDOC); + return mmio_le_readl(spibar + ICH9_REG_FDOD); +} + +int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc) +{ + uint8_t i; + uint8_t nr; + struct ich_desc_region *r = &desc->region; + + /* Test if bit-fields are working as expected */ + for (i = 0; i < 4; i++) + desc->region.FLREGs[i] = 0x5A << (i * 8); + if (r->reg0_base != 0x005A || r->reg0_limit != 0x0000 || + r->reg1_base != 0x1A00 || r->reg1_limit != 0x0000 || + r->reg2_base != 0x0000 || r->reg2_limit != 0x005A || + r->reg3_base != 0x0000 || r->reg3_limit != 0x1A00) { + msg_pdbg("The combination of compiler and CPU architecture used" + "does not lay out bit-fields as expected, sorry.\n"); + msg_pspew("r->reg0_base = 0x%04X (0x005A)\n", r->reg0_base); + msg_pspew("r->reg0_limit = 0x%04X (0x0000)\n", r->reg0_limit); + msg_pspew("r->reg1_base = 0x%04X (0x1A00)\n", r->reg1_base); + msg_pspew("r->reg1_limit = 0x%04X (0x0000)\n", r->reg1_limit); + msg_pspew("r->reg2_base = 0x%04X (0x0000)\n", r->reg2_base); + msg_pspew("r->reg2_limit = 0x%04X (0x005A)\n", r->reg2_limit); + msg_pspew("r->reg3_base = 0x%04X (0x0000)\n", r->reg3_base); + msg_pspew("r->reg3_limit = 0x%04X (0x1A00)\n", r->reg3_limit); + return RET_ERR; + } + + msg_pdbg2("Reading flash descriptors " + "mapped by the chipset via FDOC/FDOD..."); + /* content section */ + desc->content.FLVALSIG = read_descriptor_reg(0, 0, spibar); + desc->content.FLMAP0 = read_descriptor_reg(0, 1, spibar); + desc->content.FLMAP1 = read_descriptor_reg(0, 2, spibar); + desc->content.FLMAP2 = read_descriptor_reg(0, 3, spibar); + + /* component section */ + desc->component.FLCOMP = read_descriptor_reg(1, 0, spibar); + desc->component.FLILL = read_descriptor_reg(1, 1, spibar); + desc->component.FLPB = read_descriptor_reg(1, 2, spibar); + + /* region section */ + nr = desc->content.NR + 1; + if (nr >= 5) { + msg_pdbg2("%s: number of regions too high (%d) - failed\n", + __func__, nr); + return RET_ERR; + } + for (i = 0; i <= nr; i++) + desc->region.FLREGs[i] = read_descriptor_reg(2, i, spibar); + + /* master section */ + desc->master.FLMSTR1 = read_descriptor_reg(3, 0, spibar); + desc->master.FLMSTR2 = read_descriptor_reg(3, 1, spibar); + desc->master.FLMSTR3 = read_descriptor_reg(3, 2, spibar); + + /* Accessing the strap section via FDOC/D is only possible on ICH8 and + * reading the upper map is impossible on all chipsets, so don't bother. + */ + + msg_pdbg2(" done.\n"); + return RET_OK; +} +#endif /* BITFIELDS == 1 */ +#endif /* defined(__i386__) || defined(__x86_64__) */ diff --git a/ich_descriptors.h b/ich_descriptors.h new file mode 100644 index 0000000..b1da914 --- /dev/null +++ b/ich_descriptors.h @@ -0,0 +1,261 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (c) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if defined(__i386__) || defined(__x86_64__) +#ifndef __ICH_DESCRIPTORS_H__ +#define __ICH_DESCRIPTORS_H__ 1 + +#include <stdint.h> + +#define RET_OK 0 +#define RET_ERR -1 +#define RET_WARN -2 +#define RET_PARAM -3 +#define RET_OOB -4 + +#define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */ + /* 0-1: reserved */ +#define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */ +#define FDOC_FDSI (0x3f << FDOC_FDSI_OFF) +#define FDOC_FDSS_OFF 12 /* 12-14: Flash Descriptor Section Select */ +#define FDOC_FDSS (0x3 << FDOC_FDSS_OFF) + /* 15-31: reserved */ + +#define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */ + +/* Field locations and semantics for LVSCC, UVSCC and related words in the flash + * descriptor are equal therefore they all share the same macros below. */ +#define VSCC_BES_OFF 0 /* 0-1: Block/Sector Erase Size */ +#define VSCC_BES (0x3 << VSCC_BES_OFF) +#define VSCC_WG_OFF 2 /* 2: Write Granularity */ +#define VSCC_WG (0x1 << VSCC_WG_OFF) +#define VSCC_WSR_OFF 3 /* 3: Write Status Required */ +#define VSCC_WSR (0x1 << VSCC_WSR_OFF) +#define VSCC_WEWS_OFF 4 /* 4: Write Enable on Write Status */ +#define VSCC_WEWS (0x1 << VSCC_WEWS_OFF) + /* 5-7: reserved */ +#define VSCC_EO_OFF 8 /* 8-15: Erase Opcode */ +#define VSCC_EO (0xff << VSCC_EO_OFF) + /* 16-22: reserved */ +#define VSCC_VCL_OFF 23 /* 23: Vendor Component Lock */ +#define VSCC_VCL (0x1 << VSCC_VCL_OFF) + /* 24-31: reserved */ + +#define ICH_FREG_BASE(flreg) (((flreg) << 12) & 0x01fff000) +#define ICH_FREG_LIMIT(flreg) (((flreg) >> 4) & 0x01fff000) + +/* Used to select the right descriptor printing function. + * Currently only ICH8 and Ibex Peak are supported. + */ +enum ich_chipset { + CHIPSET_ICH_UNKNOWN, + CHIPSET_ICH7 = 7, + CHIPSET_ICH8, + CHIPSET_ICH9, + CHIPSET_ICH10, + CHIPSET_5_SERIES_IBEX_PEAK, + CHIPSET_6_SERIES_COUGAR_POINT, + CHIPSET_7_SERIES_PANTHER_POINT +}; + +void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity); + +#if BITFIELDS == 1 +struct ich_desc_content { + uint32_t FLVALSIG; /* 0x00 */ + union { /* 0x04 */ + uint32_t FLMAP0; + struct { + uint32_t FCBA :8, /* Flash Component Base Address */ + NC :2, /* Number Of Components */ + :6, + FRBA :8, /* Flash Region Base Address */ + NR :3, /* Number Of Regions */ + :5; + }; + }; + union { /* 0x08 */ + uint32_t FLMAP1; + struct { + uint32_t FMBA :8, /* Flash Master Base Address */ + NM :3, /* Number Of Masters */ + :5, + FISBA :8, /* Flash ICH Strap Base Address */ + ISL :8; /* ICH Strap Length */ + }; + }; + union { /* 0x0c */ + uint32_t FLMAP2; + struct { + uint32_t FMSBA :8, /* Flash (G)MCH Strap Base Addr. */ + MSL :8, /* MCH Strap Length */ + :16; + }; + }; +}; + +struct ich_desc_component { + union { /* 0x00 */ + uint32_t FLCOMP; /* Flash Components Register */ + struct { + uint32_t comp1_density :3, + comp2_density :3, + :11, + freq_read :3, + fastread :1, + freq_fastread :3, + freq_write :3, + freq_read_id :3, + :2; + }; + }; + union { /* 0x04 */ + uint32_t FLILL; /* Flash Invalid Instructions Register */ + struct { + uint32_t invalid_instr0 :8, + invalid_instr1 :8, + invalid_instr2 :8, + invalid_instr3 :8; + }; + }; + union { /* 0x08 */ + uint32_t FLPB; /* Flash Partition Boundary Register */ + struct { + uint32_t FPBA :13, /* Flash Partition Boundary Addr */ + :19; + }; + }; +}; + +struct ich_desc_region { + union { + uint32_t FLREGs[5]; + struct { + struct { /* FLREG0 Flash Descriptor */ + uint32_t reg0_base :13, + :3, + reg0_limit :13, + :3; + }; + struct { /* FLREG1 BIOS */ + uint32_t reg1_base :13, + :3, + reg1_limit :13, + :3; + }; + struct { /* FLREG2 ME */ + uint32_t reg2_base :13, + :3, + reg2_limit :13, + :3; + }; + struct { /* FLREG3 GbE */ + uint32_t reg3_base :13, + :3, + reg3_limit :13, + :3; + }; + struct { /* FLREG4 Platform */ + uint32_t reg4_base :13, + :3, + reg4_limit :13, + :3; + }; + }; + }; +}; + +struct ich_desc_master { + union { + uint32_t FLMSTR1; + struct { + uint32_t BIOS_req_ID :16, + BIOS_descr_r :1, + BIOS_BIOS_r :1, + BIOS_ME_r :1, + BIOS_GbE_r :1, + BIOS_plat_r :1, + :3, + BIOS_descr_w :1, + BIOS_BIOS_w :1, + BIOS_ME_w :1, + BIOS_GbE_w :1, + BIOS_plat_w :1, + :3; + }; + }; + union { + uint32_t FLMSTR2; + struct { + uint32_t ME_req_ID :16, + ME_descr_r :1, + ME_BIOS_r :1, + ME_ME_r :1, + ME_GbE_r :1, + ME_plat_r :1, + :3, + ME_descr_w :1, + ME_BIOS_w :1, + ME_ME_w :1, + ME_GbE_w :1, + ME_plat_w :1, + :3; + }; + }; + union { + uint32_t FLMSTR3; + struct { + uint32_t GbE_req_ID :16, + GbE_descr_r :1, + GbE_BIOS_r :1, + GbE_ME_r :1, + GbE_GbE_r :1, + GbE_plat_r :1, + :3, + GbE_descr_w :1, + GbE_BIOS_w :1, + GbE_ME_w :1, + GbE_GbE_w :1, + GbE_plat_w :1, + :3; + }; + }; +}; + +struct ich_descriptors { + struct ich_desc_content content; + struct ich_desc_component component; + struct ich_desc_region region; + struct ich_desc_master master; +}; + +void prettyprint_ich_descriptors(enum ich_chipset, const struct ich_descriptors *desc); + +void prettyprint_ich_descriptor_content(const struct ich_desc_content *content); +void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc); +void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc); +void prettyprint_ich_descriptor_master(const struct ich_desc_master *master); + +int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc); + +#endif /* BITFIELDS == 1 */ +#endif /* __ICH_DESCRIPTORS_H__ */ +#endif /* defined(__i386__) || defined(__x86_64__) */ diff --git a/ichspi.c b/ichspi.c index 34f0891..611f054 100644 --- a/ichspi.c +++ b/ichspi.c @@ -30,6 +30,7 @@ #include "chipdrivers.h" #include "programmer.h" #include "spi.h" +#include "ich_descriptors.h" /* ICH9 controller register definition */ #define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ @@ -120,6 +121,16 @@ #define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */ #define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */ +#define ICH8_REG_VSCC 0xC1 /* 32 Bits Vendor Specific Component Capabilities */ +#define ICH9_REG_LVSCC 0xC4 /* 32 Bits Host Lower Vendor Specific Component Capabilities */ +#define ICH9_REG_UVSCC 0xC8 /* 32 Bits Host Upper Vendor Specific Component Capabilities */ +/* The individual fields of the VSCC registers are defined in the file + * ich_descriptors.h. The reason is that the same layout is also used in the + * flash descriptor to define the properties of the different flash chips + * supported. The BIOS (or the ME?) is responsible to populate the ICH registers + * with the information from the descriptor on startup depending on the actual + * chip(s) detected. */ + #define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */ #define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */ #define FPB_FPBA (0x1FFF << FPB_FPBA_OFF) @@ -1130,9 +1141,6 @@ static int ich_spi_send_multicommand(struct spi_command *cmds) #define ICH_BRWA(x) ((x >> 8) & 0xff) #define ICH_BRRA(x) ((x >> 0) & 0xff) -#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff) -#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff) - static void do_ich9_spi_frap(uint32_t frap, int i) { static const char *const access_names[4] = { @@ -1159,9 +1167,8 @@ static void do_ich9_spi_frap(uint32_t frap, int i) return; } - msg_pdbg("0x%08x-0x%08x is %s\n", - (base << 12), (limit << 12) | 0x0fff, - access_names[rwperms]); + msg_pdbg("0x%08x-0x%08x is %s\n", base, (limit | 0x0fff), + access_names[rwperms]); } static const struct spi_programmer spi_programmer_ich7 = { @@ -1191,6 +1198,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, uint8_t old, new; uint16_t spibar_offset, tmp2; uint32_t tmp; + int ichspi_desc = 0; switch (ich_generation) { case 7: @@ -1262,6 +1270,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } + if (tmp2 & HSFS_FDV) + ichspi_desc = 1; tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); @@ -1309,12 +1319,40 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, mmio_readl(ich_spibar + ICH9_REG_OPMENU)); msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + ICH9_REG_OPMENU + 4)); - ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); - msg_pdbg("0xA0: 0x%08x (BBAR)\n", - ichspi_bbar); - tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); - msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + if (ich_generation == 8) { + tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC); + msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp); + msg_pdbg("VSCC: "); + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); + } else { + ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); + msg_pdbg("0xA0: 0x%08x (BBAR)\n", + ichspi_bbar); + + tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); + msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); + msg_pdbg("LVSCC: "); + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); + + tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); + msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); + msg_pdbg("UVSCC: "); + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); + + tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); + msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + } + msg_pdbg("\n"); +#if BITFIELDS == 1 + if (ichspi_desc) { + struct ich_descriptors desc = {{ 0 }}; + if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == + RET_OK) + prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, + &desc); + } +#endif /* BITFIELDS == 1 */ ich_init_opcodes(); break; default: -- 1.7.1

1 0

[PATCH 0/6] ichspi 8.0
by Stefan Tauner 14 Aug '11

14 Aug '11

this is based on my makefile patch "Makefile: fix and simplify test program compilations" not sure if it applies without that. 2/6 and 3/6 are new; 4/6 and 5/6 are ~unchanged iirc 1/6 was modified based on carldani's review 6/6 got also a few improvements Stefan Tauner (6): ichspi: add ICH/PCH flash descriptor decoding via FDOC/FDOD ichspi: disable writes when locked or read-only regions are detected ichspi: don't touch the nonexistent(?) BBAR register on ICH8 ichspi: improve prettyprint_opcodes ichspi: add support for Intel Hardware Sequencing Add ich_descriptor_tool to decode all flash descriptors stored in a flash dump file Makefile | 22 +- chipdrivers.h | 6 + flashchips.c | 23 +- flashchips.h | 2 + ich_descriptors.c | 722 ++++++++++++++++++++++ ich_descriptors.h | 466 ++++++++++++++ ichspi.c | 461 +++++++++++++-- programmer.h | 1 + util/ich_descriptors_tool/Makefile | 42 ++ util/ich_descriptors_tool/TODO | 6 + util/ich_descriptors_tool/ich_descriptors_tool.c | 225 +++++++ 11 files changed, 1938 insertions(+), 38 deletions(-) create mode 100644 ich_descriptors.c create mode 100644 ich_descriptors.h create mode 100644 util/ich_descriptors_tool/Makefile create mode 100644 util/ich_descriptors_tool/TODO create mode 100644 util/ich_descriptors_tool/ich_descriptors_tool.c

1 0

MSI k9N6GM-V flashrom -V
by Roman Fuks 13 Aug '11

13 Aug '11

[root@Archlinux romanarch]# flashrom flashrom v0.9.4-r1395 on Linux 3.0-ARCH (x86_64), built with libpci 3.1.7, GCC 4.6.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. sh: dmidecode: no se encontró la orden dmidecode execution unsuccessful - continuing without DMI info Found chipset "NVIDIA MCP61". This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... This chipset is not really supported yet. Guesswork... Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: LPC. No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. [root@Archlinux romanarch]# flashrom -V flashrom v0.9.4-r1395 on Linux 3.0-ARCH (x86_64), built with libpci 3.1.7, GCC 4.6.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 870M loops per second, 10 myus = 11 us, 100 myus = 100 us, 1000 myus = 1010 us, 10000 myus = 10016 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. sh: dmidecode: no se encontró la orden dmidecode execution unsuccessful - continuing without DMI info Found chipset "NVIDIA MCP61" with PCI ID 10de:03e0. This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 Flash bus type is LPC Found SMBus device 10de:03eb at 00:01:1 MCP SPI BAR is at 0xfec80000 Strange. MCP SPI BAR is valid, but chipset apparently doesn't have SPI enabled. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: LPC. Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2 0x06, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xff, id2 0x06, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xff, id2 0x06, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xff, id2 0x06, id1 parity violation, id1 is normal flash content, id2 is normal flash content No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. Restoring PCI config space for 00:01:0 reg 0x6d Restoring PCI config space for 00:01:0 reg 0x90 Restoring PCI config space for 00:01:0 reg 0x8c Restoring PCI config space for 00:01:0 reg 0x88

1 0

[PATCH] Warn about unhandled one-time programmable memory
by Daniel Lenski 13 Aug '11

13 Aug '11

Added feature bit FEATURE_UNHANDLED_OTP, and a warning for chips like AMIC A25L032 and A25LQ032 which contain small regions of one-time programmable memory that flashrom can neither read, nor write, nor erase. Signed-off-by: Daniel Lenski <dlenski(a)gmail.com> --- flash.h | 1 + flashchips.c | 2 ++ flashrom.c | 8 ++++++++ 3 files changed, 11 insertions(+), 0 deletions(-) diff --git a/flash.h b/flash.h index 6f0d7c0..6db4c48 100644 --- a/flash.h +++ b/flash.h @@ -85,6 +85,7 @@ enum chipbustype { #define FEATURE_ADDR_SHIFTED (1 << 5) #define FEATURE_WRSR_EWSR (1 << 6) #define FEATURE_WRSR_WREN (1 << 7) +#define FEATURE_UNHANDLED_OTP (1 << 8) #define FEATURE_WRSR_EITHER (FEATURE_WRSR_EWSR | FEATURE_WRSR_WREN) struct flashchip { diff --git a/flashchips.c b/flashchips.c index efd7599..07b9635 100644 --- a/flashchips.c +++ b/flashchips.c @@ -817,6 +817,7 @@ struct flashchip flashchips[] = { .model_id = AMIC_A25L032, .total_size = 4096, .page_size = 256, + .feature_bits = FEATURE_UNHANDLED_OTP, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -852,6 +853,7 @@ struct flashchip flashchips[] = { .model_id = AMIC_A25LQ032, .total_size = 4096, .page_size = 256, + .feature_bits = FEATURE_UNHANDLED_OTP, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, diff --git a/flashrom.c b/flashrom.c index 2690151..a7471a6 100644 --- a/flashrom.c +++ b/flashrom.c @@ -1434,6 +1434,14 @@ void check_chip_supported(struct flashchip *flash) "Thanks for your help!\n" "===\n"); } + if (flash->feature_bits & FEATURE_UNHANDLED_OTP) { + msg_cinfo("===\n" + "This flash part contains a region of one-time programmable memory\n" + "which flashrom cannot read, and may never be able to write or\n" + "erase. flashrom may not be able to completely backup and rewrite\n" + "the contents of this chip.\n" + "===\n"); + } } int main(int argc, char *argv[]) -- 1.7.0.4

2 1

Re: [flashrom] flashrom on PowerPC
by Peter Lemenkov 13 Aug '11

13 Aug '11

2011/7/27 Mattias Mattsson <vitplister(a)gmail.com>: > Hi all, > > I was able to run flashrom under Linux on PPC (big endian) hardware > with two small modifications in internal.c and processor_enable.c (see > attached patch). Not sure if this is the right way to do it but it > seems to work for me. > > Note that for Apple hardware you have to use a special power on method > to make the flash chip accessible (hold power button until beep). On > some models you have to press and hold an additional button on the > machine ("programmer's button") or keyboard ("Command"). > http://support.apple.com/kb/HT2322 > http://support.apple.com/kb/DL1284 > http://support.apple.com/kb/DL1126 > > I have tested this on two pieces of Apple hardware: "Mac Mini" (model > ID: PowerMac10,1) and "Mac mini (Late 2005)" (model ID: PowerMac10,2): > http://support.apple.com/kb/ht3476 > > By taking the hardware apart I can confirm they have the following flash chips: > > PowerMac10,1: AMD Am29LV008BB-90EC > PowerMac10,2: SHARP LH28F008BJT-BTLZ1 > > Flash chips seem to be mapped top-aligned in the 4GB address space. > Looking at the Open Firmware forth code inside Apple's own firmware > updates also suggests this is the case. > > I was able to probe, read, write and erase on both machines. Read > files seem to contain valid data. > > Added support for LH28F008BJT-BTLZ1 and marked Am29LV008B as fully tested. What's the status of these patches? Could anyone ACK them? -- With best regards, Peter Lemenkov.

1 0

Initial version of autotools support for Flashrom
by Peter Lemenkov 13 Aug '11

13 Aug '11

Hello All. Some time ago I mentioned that I've got patches for full autotools support - here is the first patch in a patchset for your further consideration: https://github.com/lemenkov/flashrom/commits/autotools It was tested on RHEL 5, 6, Fedora 1x, i386, i586, i686, x86_64 and ppc (I'm using it for building Flashrom's RPM for a half of the year at least). It's rebased on top of svn1412 and cleaned up to be a full drop-in replacement for handmade Makefile. Unfortunately I didn't test in on anything else than Linux, so I must admit that it's not in a very good shape for MinGW / BSD / DOS / Darwin users (ARM, MIPS users could be also hurt as well - that's why I didn't touch anything else in this commit except adding these two files). -- With best regards, Peter Lemenkov.

1 0

Re: [flashrom] [PATCH] Makefile: fix and simplify test program compilations
by Stefan Tauner 12 Aug '11

12 Aug '11

On Fri, 12 Aug 2011 21:38:37 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > side note: we use $(CC) all over the place before we even check if > it is there. e.g.: > override ARCH = $(strip $(shell LC_ALL=C $(CC) -E arch.h|grep -v '^\#')) > > this creates unwanted output like: > make -j1 CC=eiugthes > /bin/sh: eiugthes: not found > /bin/sh: eiugthes: not found > /bin/sh: eiugthes: not found > /bin/sh: eiugthes: not found > Checking for a C compiler... not found. > make: *** [compiler] Error 1 actually it is only this one line that creates the output. the reason it executes the command 4 times instead of caching it is the use of "=" instead of ":=", see http://www.gnu.org/s/hello/manual/make/Flavors.html#Flavors i have added the : to the ARCH definition, but it does not solve the underlying problem that it is executed before the compiler test: make -j1 CC=eiugthes /bin/sh: eiugthes: not found Checking for a C compiler... not found. make: *** [compiler] Error 1 -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

Re: [flashrom] [PATCH] Makefile: fix and simplify test program compilations
by Stefan Tauner 12 Aug '11

12 Aug '11

On Fri, 12 Aug 2011 21:38:37 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > +define COMPILER_TEST > +int main(int argc, char **argv) > +{ > + (void) argafc; testing leftovers, fixed locally... -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

Message levels and content
by Carl-Daniel Hailfinger 12 Aug '11

12 Aug '11

Hi, it has become quite obvious that there are different views about how much output flashrom should provide at default verbosity. I'd like to keep line count down, but at the same time I acknowledge that long-running operations need some user feedback. Those goals are not easily reconcilable and there will be some friction. Others would like to upgrade the message levels of quite a few messages and introduce a separate quiet mode which is less verbose than default mode. Given that this dicussion revolves around the UI and different people expect different things, I don't want to "solve" this by decree. Instead, I hope for consensus. We definitely need to reach a decision, but maybe we can do this with the help of use cases and by examining typical flashrom output. I'm sure there is some low-hanging fruit where the message content/level can be adjusted and where people agree on the changes. Regards, Carl-Daniel -- http://www.hailfinger.org/

3 8

[PATCH] Fix all ASUS P5GD* board enables
by Stefan Tauner 12 Aug '11

12 Aug '11

Changes related to P5GD1 variants: - Reorder "P5GD1 Pro" in print.c and include a DMI patter to its board enable - Add an untested "P5GD1(-VM)" board enable and add an entry to print.c Changes related to P5GD(2/C) variants: - Fix the name of "P5GDC-V Deluxe" board enable and add a DMI pattern and print.c entry. NB: there is no "P5GDC-V" board. - Add a generic match for P5GD(2/C)* boards with a not tested tag. This are the potential targets for this according to the asus ftp: ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/ Unsupported variants of the P5GD2: P5GD2, P5GD2 Deluxe, P5GD2 Pro, P5GD2-X (P5GD2 Premium is already tested) (there seems to be also a P5GD2-TVM/GB/SI in the wild, which is not known to asus :) Unsupported variants of the P5GDC: P5GDC Pro, P5GDC-MX (P5GDC Deluxe and P5GDC-V Deluxe are already tested) References: P5GD1 PRO (dmi "P5GD1 PRO") smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, *0x814e* http://www.coreboot.org/pipermail/flashrom/2010-August/004539.html P5GD1 (dmi "P5GD1") The non-pro version seems to match the pro pci pattern, but could be distinguished by the SATA ID of 1043:2604 vs. 1043:2601: https://launchpadlibrarian.net/62167576/Lspci.txt or a DMI pattern of course. P5GD1-VM (dmi "P5GD1-VM") This does also match the current PCI IDs. https://bugs.launchpad.net/ubuntu/+source/linux/+bug/465379 - P5GD2 Premium (dmi "P5GD2-Premium") smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, 0x813d http://www.flashrom.org/pipermail/flashrom/2010-August/004555.html - P5GDC-V Deluxe (dmi "P5GDC-V") smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, 0x813d http://www.flashrom.org/pipermail/flashrom/2010-September/004939.html - P5GDC Deluxe (dmi "P5GDC") smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, 0x813d http://www.flashrom.org/pipermail/flashrom/2010-September/004684.html - P5GDC Pro, P5GDC-MX, P5GD2-X, P5GD2 Pro, P5GD2 no useful logs found - P5GD2-Deluxe (dmi "P5GD2-Deluxe") smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, 0x813d https://bugs.launchpad.net/ubuntu/+source/foomatic-filters/+bug/572514 - P5GD2-TVM/GB/SI (dmi "P5GD2-TVM/GB/SI") smbus: 0x8086, 0x266a, 0x1043, 0x266a; audio: 0x8086, 0x2668, 0x1043, *0x81a7* https://bugs.launchpad.net/ubuntu/+source/linux/+bug/462500 Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- adding tested board enable with exact matches for identified and tested boards and NT board enables for potentially compatible boards should be the scheme to be used in the future for all mainboard families instead of adding an uncertain generic board enable or none at all (just because the user does not reply). The policy should be to add board enables as soon as they become available or at least no longer than a week after posting it, even without success reports. Rationale: This scheme guarantees that we get success reports for untested boards which allows us to combine them later when we are sure (enough). OTOH it allows users to easily test the yet unsupported boards without recompiling by forcing the generic board enables. And it keeps the patch queue short. Investigating all of the above was certainly not worth it on its own and id suggest to avoid similar efforts in the future by following the scheme :) --- board_enable.c | 7 +++++-- print.c | 5 ++++- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/board_enable.c b/board_enable.c index aba6f38..ab9aff4 100644 --- a/board_enable.c +++ b/board_enable.c @@ -2022,9 +2022,12 @@ const struct board_pciid_enable board_pciid_enables[] = { {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, P3, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise}, {0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x5513, 0x1043, 0x8087, NULL, NULL, NULL, P3, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", P3, "ASUS", "P5A", 0, OK, board_asus_p5a}, - {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, P3, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, "^P5GD1 PRO$", NULL, NULL, P3, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, P3, "ASUS", "P5GD1(-VM)", 0, NT, intel_ich_gpio21_raise}, {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GD2-Premium$", NULL, NULL, P3, "ASUS", "P5GD2 Premium", 0, OK, intel_ich_gpio21_raise}, - {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, P3, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GDC-V$", NULL, NULL, P3, "ASUS", "P5GDC-V Deluxe", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GDC$", NULL, NULL, P3, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, P3, "ASUS", "P5GD2/C variants", 0, NT, intel_ich_gpio21_raise}, {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, NT, intel_ich_gpio16_raise}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, P3, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, P3, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise}, diff --git a/print.c b/print.c index 21b4570..dfee33d 100644 --- a/print.c +++ b/print.c @@ -479,12 +479,15 @@ const struct board_info boards_known[] = { B("ASUS", "P5B-Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=bswT66IBSb2rEWNa", NULL), B("ASUS", "P5BV-M", 0, "ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/P5B-VM/", "Reported by Bernhard M. Wiedemann <bernhard(a)uml12d.zq1.de> to flashrom(a)coreboot.org, no public archive. Missing board enable and/or SST49LF008A unlocking. May work now."), B("ASUS", "P5GC-MX/1333", 1, "http://www.asus.com/product.aspx?P_ID=PYvbfOokwxUzJky3", NULL), + B("ASUS", "P5GD1 Pro", 1, "http://www.asus.com/product.aspx?P_ID=50M49xQh71EZOeM1", NULL), + B("ASUS", "P5GD1(-VM)", 0, NULL, "Untested board enable."), B("ASUS", "P5GD2 Premium", 1, "http://www.asus.it/product.aspx?P_ID=lRKaz1Rb6Xb0OFM7", NULL), B("ASUS", "P5GDC Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=AbeoopyNpI2TZixg", NULL), + B("ASUS", "P5GDC-V Deluxe", 1, NULL, NULL), + B("ASUS", "P5GD2/C variants", 0, NULL, "Untested board enable."), B("ASUS", "P5KC", 1, "http://www.asus.com/product.aspx?P_ID=fFZ8oUIGmLpwNMjj", NULL), B("ASUS", "P5L-MX", 1, "http://www.asus.com/product.aspx?P_ID=X70d3NCzH2DE9vWH", NULL), B("ASUS", "P5LD2", 0, NULL, "Untested board enable."), - B("ASUS", "P5GD1 Pro", 1, "http://www.asus.com/product.aspx?P_ID=50M49xQh71EZOeM1", NULL), B("ASUS", "P5N-E SLI", 0, "http://www.asus.com/product.aspx?P_ID=KyHOsOKWujC2QguJ", "Needs a board enable (http://patchwork.coreboot.org/patch/3298/)."), B("ASUS", "P5N32-E SLI", 1, "http://www.asus.com/product.aspx?P_ID=vBZLIBtPzYB2bLcb", NULL), B("ASUS", "P5ND2-SLI Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=WY7XroDuUImVbgp5", NULL), -- 1.7.1

1 0

SuperMicro X8DTU-6TF+: flashrom -Vr failed
by Scott Silverman 12 Aug '11

12 Aug '11

# ./flashrom -Vr ../current.bios flashrom v0.9.4-r1412 on Linux 2.6.29.6-sxtickless (x86_64), built with libpci 3.1.7, GCC 4.1.2 20080704 (Red Hat 4.1.2-50), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1523M loops per second, 10 myus = 11 us, 100 myus = 100 us, 1000 myus = 998 us, 10000 myus = 9990 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Supermicro" DMI string system-product-name: "X8DTU-6+" DMI string system-version: "1234567890" DMI string baseboard-manufacturer: "Supermicro" DMI string baseboard-product-name: "X8DTU-6+" DMI string baseboard-version: "2.01" DMI string chassis-type: "Main Server Chassis" Found chipset "Intel ICH10R" with PCI ID 8086:3a16. Enabling flash write... 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x4 0x7fffffff/0x7fffffff FWH IDSEL: 0x5 0x7fffffff/0x7fffffff FWH IDSEL: 0x6 0x7fffffff/0x7fffffff FWH IDSEL: 0x7 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 Root Complex Register Block address = 0xfed1c000 GCS = 0x460: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0x6008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=0 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00002000 (FADDR) 0x50: 0x00001a1b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x1a, BRRA 0x1b 0x54: 0x00010000 (FREG0: Flash Descriptor) 0x00000000-0x00001fff is read-only 0x58: 0x03ff0200 (FREG1: BIOS) 0x00200000-0x003fffff is read-write 0x5C: 0x01ff0002 (FREG2: Management Engine) 0x00002000-0x001fffff is locked 0x60: 0x00001fff (FREG3: Gigabit Ethernet) Gigabit Ethernet region is unused. 0x64: 0x00001fff (FREG4: Platform Data) Platform Data region is unused. 0x74: 0x00000000 (PR0) 0x78: 0x00000000 (PR1) 0x7C: 0x00000000 (PR2) 0x80: 0x00000000 (PR3) 0x84: 0x00000000 (PR4) 0x90: 0x04 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0x000000 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=0 0x94: 0x3906 (PREOP) 0x96: 0xd43b (OPTYPE) 0x98: 0x05200302 (OPMENU) 0x9C: 0x3906019f (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xD0: 0x00000000 (FPB) Programming OPCODES... program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 done preop0=0x06, preop1=0x50 op[0]=0x02, 3, 0 op[1]=0x03, 2, 0 op[2]=0xd8, 3, 0 op[3]=0x05, 0, 0 op[4]=0x90, 2, 0 op[5]=0x01, 1, 0 op[6]=0x9f, 0, 0 op[7]=0xc7, 1, 0 SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Chip status register is 10 Found Atmel flash chip "AT25DF321A" (4096 kB, SPI) at physical address 0xffc00000. Ignoring security lockdown (if present) Ignoring status register byte 2 Chip status register is 10 Chip status register: Sector Protection Register Lock (SRPL) is not set Chip status register: Bit 6 is not set Chip status register: Erase/Program Error (EPE) is not set Chip status register: WP# pin (WPP) is not asserted Chip status register: Software Protection Status (SWP): no sectors are protected Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x2f, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x2f, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for SST SST25VF010.REMS, 128 kB: probe_spi_rems: id1 0xff, id2 0xff Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for SST SST25VF040.REMS, 512 kB: probe_spi_rems: id1 0xff, id2 0xff Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for SST SST25LF040A.RES, 512 kB: program_opcodes: preop=5006 optype=462b opmenu=05ab0302c79f0190 on-the-fly OPCODE (0xAB) re-programmed, op-pos=2 probe_spi_res2: id1 0xff, id2 0xff Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xff, id2 0xff Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x2f, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x2f, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x80, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for ST M25P05.RES, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for ST M25P10.RES, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x2f, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x2f, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x80, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x2f, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x2f, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x2f, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x2f, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x2f, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xff, id2 0xff === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Ignoring security lockdown (if present) Reading flash... Transaction error! SSFS: SCIP=0, FDONE=1, FCERR=1, AEL=0 SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=63, SME=0, SCF=0 Running OPCODE 0x03 failed at address 0x002000 (payload length was 64). Read operation failed! FAILED. Restoring MMIO space at 0x7fe44a3648a0 Restoring MMIO space at 0x7fe44a36489c Restoring MMIO space at 0x7fe44a364898 Restoring MMIO space at 0x7fe44a364896 Restoring MMIO space at 0x7fe44a364894 Restoring PCI config space for 00:1f:0 reg 0xdc

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[PATCH] Makefile: fix and simplify test program compilations
by Stefan Tauner 12 Aug '11

12 Aug '11

this was totally broken due to the time behavior of make's shell function's temporal behavior. quote from the gnu make documentation http://www.gnu.org/s/hello/manual/make/Shell-Function.html): "The commands run by calls to the shell function are run when the function calls are expanded" we have used the shell function to echo the test programs to a file. the file name used was equal for all tests and was overwritten for each test. the result was that all tests (in a single target?) used the last test program because the echoing of the test programs was done before all test compilations(!) also the branching for testing ifeq ($(CONFIG_FT2232_SPI), yes) was unnecessary. in my approach here i am using verbatim variables (allows to define even complex test programs in the makefile without jumping through hoops) that get exported to environment variables (via "export", reference afterwards with "$$<varname>"). i have also added the missing redirection of stderr to the compiler test. --- alternatively one could just use different file names of course, but i think my approach is superior due to the separation and readability of the tested code and the fact that the temporal behavior is MUCH clearer now (else this bug would have not crept in in the first place :P) if line count is an issue one could of course compress the test programs to something unreadable again :) side note: we use $(CC) all over the place before we even check if it is there. e.g.: override ARCH = $(strip $(shell LC_ALL=C $(CC) -E arch.h|grep -v '^\#')) this creates unwanted output like: make -j1 CC=eiugthes /bin/sh: eiugthes: not found /bin/sh: eiugthes: not found /bin/sh: eiugthes: not found /bin/sh: eiugthes: not found Checking for a C compiler... not found. make: *** [compiler] Error 1 Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- Makefile | 91 ++++++++++++++++++++++++++++++++++++++++---------------------- 1 files changed, 59 insertions(+), 32 deletions(-) diff --git a/Makefile b/Makefile index c72d10a..672a0df 100644 --- a/Makefile +++ b/Makefile @@ -531,11 +531,62 @@ distclean: clean strip: $(PROGRAM)$(EXEC_SUFFIX) $(STRIP) $(STRIP_ARGS) $(PROGRAM)$(EXEC_SUFFIX) +# below are the definitions of test programs as verbatim variables, which get +# exported to environment variables and are referenced with $$<varname> later +define COMPILER_TEST +int main(int argc, char **argv) +{ + (void) argafc; + (void) argv; + return 0; +} +endef +export COMPILER_TEST + +define LIBPCI_TEST +/* Avoid a failing test due to libpci header symbol shadowing breakage */ +#define index shadow_workaround_index +#include <pci/pci.h> +struct pci_access *pacc; +int main(int argc, char **argv) +{ + (void) argc; + (void) argv; + pacc = pci_alloc(); + return 0; +} +endef +export LIBPCI_TEST + +define FTDI_TEST +#include <ftdi.h> +struct ftdi_context *ftdic = NULL; +int main(int argc, char **argv) +{ + (void) argc; + (void) argv; + return ftdi_init(ftdic); +} +endef +export FTDI_TEST + +define UTSNAME_TEST +#include <sys/utsname.h> +struct utsname osinfo; +int main(int argc, char **argv) +{ + (void) argc; + (void) argv; + uname (&osinfo); + return 0; +} +endef +export UTSNAME_TEST + compiler: featuresavailable @printf "Checking for a C compiler... " - @$(shell ( echo "int main(int argc, char **argv)"; \ - echo "{ (void) argc; (void) argv; return 0; }"; ) > .test.c ) - @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .test.c -o .test$(EXEC_SUFFIX) >/dev/null && \ + @echo "$$COMPILER_TEST" > .test.c + @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .test.c -o .test$(EXEC_SUFFIX) >/dev/null 2>&1 && \ echo "found." || ( echo "not found."; \ rm -f .test.c .test$(EXEC_SUFFIX); exit 1) @rm -f .test.c .test$(EXEC_SUFFIX) @@ -548,12 +599,7 @@ compiler: featuresavailable ifeq ($(CHECK_LIBPCI), yes) pciutils: compiler @printf "Checking for libpci headers... " - @# Avoid a failing test due to libpci header symbol shadowing breakage - @$(shell ( echo "#define index shadow_workaround_index"; \ - echo "#include <pci/pci.h>"; \ - echo "struct pci_access *pacc;"; \ - echo "int main(int argc, char **argv)"; \ - echo "{ (void) argc; (void) argv; pacc = pci_alloc(); return 0; }"; ) > .test.c ) + @echo "$$LIBPCI_TEST" > .test.c @$(CC) -c $(CPPFLAGS) $(CFLAGS) .test.c -o .test.o >/dev/null 2>&1 && \ echo "found." || ( echo "not found."; echo; \ echo "Please install libpci headers (package pciutils-devel)."; \ @@ -588,41 +634,22 @@ featuresavailable: @false endif -ifeq ($(CONFIG_FT2232_SPI), yes) features: compiler @echo "FEATURES := yes" > .features.tmp +ifeq ($(CONFIG_FT2232_SPI), yes) @printf "Checking for FTDI support... " - @$(shell ( echo "#include <ftdi.h>"; \ - echo "struct ftdi_context *ftdic = NULL;"; \ - echo "int main(int argc, char **argv)"; \ - echo "{ (void) argc; (void) argv; return ftdi_init(ftdic); }"; ) > .featuretest.c ) + @echo "$$FTDI_TEST" > .featuretest.c @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) $(FTDILIBS) $(LIBS) >/dev/null 2>&1 && \ ( echo "found."; echo "FTDISUPPORT := yes" >> .features.tmp ) || \ ( echo "not found."; echo "FTDISUPPORT := no" >> .features.tmp ) +endif @printf "Checking for utsname support... " - @$(shell ( echo "#include <sys/utsname.h>"; \ - echo "struct utsname osinfo;"; \ - echo "int main(int argc, char **argv)"; \ - echo "{ (void) argc; (void) argv; uname (&osinfo); return 0; }"; ) > .featuretest.c ) - @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) >/dev/null 2>&1 && \ - ( echo "found."; echo "UTSNAME := yes" >> .features.tmp ) || \ - ( echo "not found."; echo "UTSNAME := no" >> .features.tmp ) - @$(DIFF) -q .features.tmp .features >/dev/null 2>&1 && rm .features.tmp || mv .features.tmp .features - @rm -f .featuretest.c .featuretest$(EXEC_SUFFIX) -else -features: compiler - @echo "FEATURES := yes" > .features.tmp - @printf "Checking for utsname support... " - @$(shell ( echo "#include <sys/utsname.h>"; \ - echo "struct utsname osinfo;"; \ - echo "int main(int argc, char **argv)"; \ - echo "{ (void) argc; (void) argv; uname (&osinfo); return 0; }"; ) > .featuretest.c ) + @echo "$$UTSNAME_TEST" > .featuretest.c @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) >/dev/null 2>&1 && \ ( echo "found."; echo "UTSNAME := yes" >> .features.tmp ) || \ ( echo "not found."; echo "UTSNAME := no" >> .features.tmp ) @$(DIFF) -q .features.tmp .features >/dev/null 2>&1 && rm .features.tmp || mv .features.tmp .features @rm -f .featuretest.c .featuretest$(EXEC_SUFFIX) -endif install: $(PROGRAM)$(EXEC_SUFFIX) mkdir -p $(DESTDIR)$(PREFIX)/sbin -- 1.7.1

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