- flashrom - mail.coreboot.org

Fw: BIOS "VIA VT82C693A"
by Fam. Scapin Luigi e Paola 08 Sep '11

08 Sep '11

Luigi Scapinit may be useful to attach the old bios best regards Luigi ----- Original Message ----- From: Fam. Scapin Luigi e Paola To: flashrom(a)flashrom.org Sent: Wednesday, September 07, 2011 4:06 PM Subject: BIOS "VIA VT82C693A" volare@volare-desktop:~$ sudo flashrom [sudo] password for volare: flashrom v0.9.2-r1141 on Linux 2.6.38-11-generic (i686), built with libpci 3.1.7, GCC 4.5.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... delay loop is unreliable, trying to continue OK. No coreboot table found. Found chipset "VIA VT82C69x", enabling flash write... OK - searching further chips. Found chipset "VIA VT82C596", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Found chip "SyncMOS/MoselVitelic {F,S,V}29C51002T" (256 KB, Parallel) at physical address 0xfffc0000. === This flash part has status UNTESTED for operations: ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Thanks for your help! === No operations were specified. CURRENTLY SUPPORT THE MEMORY SIZE UP TO 128 MB Thanks Luigi Scapin � Paola Pellanda [filter: street address removed] P Rispetta l'ambiente: se non ti � necessario, non stampare questa mail. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Il presente messaggio e gli eventuali allegati sono di natura confidenziale: qualora vi fosse pervenuto per errore, vi preghiamo di cancellarlo dal vostro sistema. Per eventuali chiarimenti, vogliate rivolgervi al mittente. Grazie. This message and any attachments are confidential. If you have received this message in error please delete it from your system. If you require any assistance please notify the sender. Thank You. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ A non-text attachment has been stripped: 10191999 It is available at http://paste.flashrom.org/view.php?id�3

1 0

[PATCH] Change programmer selection in cli and generic code
by Carl-Daniel Hailfinger 07 Sep '11

07 Sep '11

Change programmer selection in cli and generic code Bugfix: Do not accept multiple conflicting --programmer selections. Restriction: Do not accept multiple --programmer selections even if there is no conflict. Do not rely on exported programmer variable anymore. programmer_init requires the programmer as first parameter. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-programmer_selection_fix/cli_classic.c =================================================================== --- flashrom-programmer_selection_fix/cli_classic.c (Revision 1427) +++ flashrom-programmer_selection_fix/cli_classic.c (Arbeitskopie) @@ -111,6 +111,7 @@ #endif int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0; int dont_verify_it = 0, list_supported = 0, operation_specified = 0; + enum programmer prog = PROGRAMMER_INVALID; int ret = 0; static const char optstring[] = "r:Rw:v:nVEfc:m:l:i:p:Lzh"; @@ -258,8 +259,16 @@ #endif break; case 'p': - for (programmer = 0; programmer < PROGRAMMER_INVALID; programmer++) { - name = programmer_table[programmer].name; + if (prog != PROGRAMMER_INVALID) { + fprintf(stderr, "Error: --programmer specified " + "more than once. You can specify " + "multiple progammer parameters with " + "\",\". Please see the man page for " + "details.\n"); + cli_classic_abort_usage(); + } + for (prog = 0; prog < PROGRAMMER_INVALID; prog++) { + name = programmer_table[prog].name; namelen = strlen(name); if (strncmp(optarg, name, namelen) == 0) { switch (optarg[namelen]) { @@ -283,7 +292,7 @@ break; } } - if (programmer == PROGRAMMER_INVALID) { + if (prog == PROGRAMMER_INVALID) { fprintf(stderr, "Error: Unknown programmer " "%s.\n", optarg); cli_classic_abort_usage(); @@ -332,14 +341,6 @@ } #endif -#if CONFIG_INTERNAL == 1 - if ((programmer != PROGRAMMER_INTERNAL) && (lb_part || lb_vendor)) { - fprintf(stderr, "Error: --mainboard requires the internal " - "programmer. Aborting.\n"); - cli_classic_abort_usage(); - } -#endif - if (chip_to_probe) { for (flash = flashchips; flash && flash->name; flash++) if (!strcmp(flash->name, chip_to_probe)) @@ -355,10 +356,21 @@ flash = NULL; } + if (prog == PROGRAMMER_INVALID) + prog = default_programmer; + +#if CONFIG_INTERNAL == 1 + if ((prog != PROGRAMMER_INTERNAL) && (lb_part || lb_vendor)) { + fprintf(stderr, "Error: --mainboard requires the internal " + "programmer. Aborting.\n"); + cli_classic_abort_usage(); + } +#endif + /* FIXME: Delay calibration should happen in programmer code. */ myusec_calibrate_delay(); - if (programmer_init(pparam)) { + if (programmer_init(prog, pparam)) { fprintf(stderr, "Error: Programmer initialization failed.\n"); ret = 1; goto out_shutdown; Index: flashrom-programmer_selection_fix/flashrom.c =================================================================== --- flashrom-programmer_selection_fix/flashrom.c (Revision 1427) +++ flashrom-programmer_selection_fix/flashrom.c (Arbeitskopie) @@ -42,10 +42,12 @@ char *chip_to_probe = NULL; int verbose = 0; +enum programmer programmer = PROGRAMMER_INVALID; + #if CONFIG_INTERNAL == 1 -enum programmer programmer = PROGRAMMER_INTERNAL; +enum programmer default_programmer = PROGRAMMER_INTERNAL; #elif CONFIG_DUMMY == 1 -enum programmer programmer = PROGRAMMER_DUMMY; +enum programmer default_programmer = PROGRAMMER_DUMMY; #else /* If neither internal nor dummy are selected, we must pick a sensible default. * Since there is no reason to prefer a particular external programmer, we fail @@ -55,7 +57,7 @@ #if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG+CONFIG_RAYER_SPI+CONFIG_NICINTEL+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV > 1 #error Please enable either CONFIG_DUMMY or CONFIG_INTERNAL or disable support for all programmers except one. #endif -enum programmer programmer = +enum programmer default_programmer = #if CONFIG_NIC3COM == 1 PROGRAMMER_NIC3COM #endif @@ -515,9 +517,15 @@ return 0; } -int programmer_init(char *param) +int programmer_init(enum programmer prog, char *param) { int ret; + + if (prog >= PROGRAMMER_INVALID) { + msg_perr("Invalid programmer specified!\n"); + return -1; + } + programmer = prog; /* Initialize all programmer specific data. */ /* Default to unlimited decode sizes. */ max_rom_decode = (const struct decode_sizes) { Index: flashrom-programmer_selection_fix/programmer.h =================================================================== --- flashrom-programmer_selection_fix/programmer.h (Revision 1427) +++ flashrom-programmer_selection_fix/programmer.h (Arbeitskopie) @@ -86,6 +86,7 @@ }; extern enum programmer programmer; +extern enum programmer default_programmer; struct programmer_entry { const char *vendor; @@ -110,7 +111,7 @@ extern const struct programmer_entry programmer_table[]; -int programmer_init(char *param); +int programmer_init(enum programmer prog, char *param); int programmer_shutdown(void); enum bitbang_spi_master_type { -- http://www.hailfinger.org/

4 10

[commit] r1433 - trunk
by repository service 07 Sep '11

07 Sep '11

Author: hailfinger Date: Thu Sep 8 02:00:29 2011 New Revision: 1433 URL: http://flashrom.org/trac/flashrom/changeset/1433 Log: Change programmer selection in cli and generic code Bugfix: Do not accept multiple conflicting --programmer selections. Restriction: Do not accept multiple --programmer selections even if there is no conflict. Unexport the programmer variable. programmer_init requires the programmer as first parameter. The default programmer selection is now part of cli_classic. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/cli_classic.c trunk/flashrom.c trunk/it87spi.c trunk/programmer.h Modified: trunk/cli_classic.c ============================================================================== --- trunk/cli_classic.c Wed Sep 7 22:48:34 2011 (r1432) +++ trunk/cli_classic.c Thu Sep 8 02:00:29 2011 (r1433) @@ -31,6 +31,74 @@ #include "flashchips.h" #include "programmer.h" +#if CONFIG_INTERNAL == 1 +static enum programmer default_programmer = PROGRAMMER_INTERNAL; +#elif CONFIG_DUMMY == 1 +static enum programmer default_programmer = PROGRAMMER_DUMMY; +#else +/* If neither internal nor dummy are selected, we must pick a sensible default. + * Since there is no reason to prefer a particular external programmer, we fail + * if more than one of them is selected. If only one is selected, it is clear + * that the user wants that one to become the default. + */ +#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG+CONFIG_RAYER_SPI+CONFIG_NICINTEL+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV > 1 +#error Please enable either CONFIG_DUMMY or CONFIG_INTERNAL or disable support for all programmers except one. +#endif +static enum programmer default_programmer = +#if CONFIG_NIC3COM == 1 + PROGRAMMER_NIC3COM +#endif +#if CONFIG_NICREALTEK == 1 + PROGRAMMER_NICREALTEK +#endif +#if CONFIG_NICNATSEMI == 1 + PROGRAMMER_NICNATSEMI +#endif +#if CONFIG_GFXNVIDIA == 1 + PROGRAMMER_GFXNVIDIA +#endif +#if CONFIG_DRKAISER == 1 + PROGRAMMER_DRKAISER +#endif +#if CONFIG_SATASII == 1 + PROGRAMMER_SATASII +#endif +#if CONFIG_ATAHPT == 1 + PROGRAMMER_ATAHPT +#endif +#if CONFIG_FT2232_SPI == 1 + PROGRAMMER_FT2232_SPI +#endif +#if CONFIG_SERPROG == 1 + PROGRAMMER_SERPROG +#endif +#if CONFIG_BUSPIRATE_SPI == 1 + PROGRAMMER_BUSPIRATE_SPI +#endif +#if CONFIG_DEDIPROG == 1 + PROGRAMMER_DEDIPROG +#endif +#if CONFIG_RAYER_SPI == 1 + PROGRAMMER_RAYER_SPI +#endif +#if CONFIG_NICINTEL == 1 + PROGRAMMER_NICINTEL +#endif +#if CONFIG_NICINTEL_SPI == 1 + PROGRAMMER_NICINTEL_SPI +#endif +#if CONFIG_OGP_SPI == 1 + PROGRAMMER_OGP_SPI +#endif +#if CONFIG_SATAMV == 1 + PROGRAMMER_SATAMV +#endif +#if CONFIG_LINUX_SPI == 1 + PROGRAMMER_LINUX_SPI +#endif +; +#endif + static void cli_classic_usage(const char *name) { printf("Usage: flashrom [-n] [-V] [-f] [-h|-R|-L|" @@ -111,6 +179,7 @@ #endif int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0; int dont_verify_it = 0, list_supported = 0, operation_specified = 0; + enum programmer prog = PROGRAMMER_INVALID; int ret = 0; static const char optstring[] = "r:Rw:v:nVEfc:m:l:i:p:Lzh"; @@ -258,8 +327,16 @@ #endif break; case 'p': - for (programmer = 0; programmer < PROGRAMMER_INVALID; programmer++) { - name = programmer_table[programmer].name; + if (prog != PROGRAMMER_INVALID) { + fprintf(stderr, "Error: --programmer specified " + "more than once. You can separate " + "multiple\nparameters for a programmer " + "with \",\". Please see the man page " + "for details.\n"); + cli_classic_abort_usage(); + } + for (prog = 0; prog < PROGRAMMER_INVALID; prog++) { + name = programmer_table[prog].name; namelen = strlen(name); if (strncmp(optarg, name, namelen) == 0) { switch (optarg[namelen]) { @@ -283,7 +360,7 @@ break; } } - if (programmer == PROGRAMMER_INVALID) { + if (prog == PROGRAMMER_INVALID) { fprintf(stderr, "Error: Unknown programmer " "%s.\n", optarg); cli_classic_abort_usage(); @@ -332,14 +409,6 @@ } #endif -#if CONFIG_INTERNAL == 1 - if ((programmer != PROGRAMMER_INTERNAL) && (lb_part || lb_vendor)) { - fprintf(stderr, "Error: --mainboard requires the internal " - "programmer. Aborting.\n"); - cli_classic_abort_usage(); - } -#endif - if (chip_to_probe) { for (flash = flashchips; flash && flash->name; flash++) if (!strcmp(flash->name, chip_to_probe)) @@ -355,10 +424,21 @@ flash = NULL; } + if (prog == PROGRAMMER_INVALID) + prog = default_programmer; + +#if CONFIG_INTERNAL == 1 + if ((prog != PROGRAMMER_INTERNAL) && (lb_part || lb_vendor)) { + fprintf(stderr, "Error: --mainboard requires the internal " + "programmer. Aborting.\n"); + cli_classic_abort_usage(); + } +#endif + /* FIXME: Delay calibration should happen in programmer code. */ myusec_calibrate_delay(); - if (programmer_init(pparam)) { + if (programmer_init(prog, pparam)) { fprintf(stderr, "Error: Programmer initialization failed.\n"); ret = 1; goto out_shutdown; Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Wed Sep 7 22:48:34 2011 (r1432) +++ trunk/flashrom.c Thu Sep 8 02:00:29 2011 (r1433) @@ -42,73 +42,7 @@ char *chip_to_probe = NULL; int verbose = 0; -#if CONFIG_INTERNAL == 1 -enum programmer programmer = PROGRAMMER_INTERNAL; -#elif CONFIG_DUMMY == 1 -enum programmer programmer = PROGRAMMER_DUMMY; -#else -/* If neither internal nor dummy are selected, we must pick a sensible default. - * Since there is no reason to prefer a particular external programmer, we fail - * if more than one of them is selected. If only one is selected, it is clear - * that the user wants that one to become the default. - */ -#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG+CONFIG_RAYER_SPI+CONFIG_NICINTEL+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV > 1 -#error Please enable either CONFIG_DUMMY or CONFIG_INTERNAL or disable support for all programmers except one. -#endif -enum programmer programmer = -#if CONFIG_NIC3COM == 1 - PROGRAMMER_NIC3COM -#endif -#if CONFIG_NICREALTEK == 1 - PROGRAMMER_NICREALTEK -#endif -#if CONFIG_NICNATSEMI == 1 - PROGRAMMER_NICNATSEMI -#endif -#if CONFIG_GFXNVIDIA == 1 - PROGRAMMER_GFXNVIDIA -#endif -#if CONFIG_DRKAISER == 1 - PROGRAMMER_DRKAISER -#endif -#if CONFIG_SATASII == 1 - PROGRAMMER_SATASII -#endif -#if CONFIG_ATAHPT == 1 - PROGRAMMER_ATAHPT -#endif -#if CONFIG_FT2232_SPI == 1 - PROGRAMMER_FT2232_SPI -#endif -#if CONFIG_SERPROG == 1 - PROGRAMMER_SERPROG -#endif -#if CONFIG_BUSPIRATE_SPI == 1 - PROGRAMMER_BUSPIRATE_SPI -#endif -#if CONFIG_DEDIPROG == 1 - PROGRAMMER_DEDIPROG -#endif -#if CONFIG_RAYER_SPI == 1 - PROGRAMMER_RAYER_SPI -#endif -#if CONFIG_NICINTEL == 1 - PROGRAMMER_NICINTEL -#endif -#if CONFIG_NICINTEL_SPI == 1 - PROGRAMMER_NICINTEL_SPI -#endif -#if CONFIG_OGP_SPI == 1 - PROGRAMMER_OGP_SPI -#endif -#if CONFIG_SATAMV == 1 - PROGRAMMER_SATAMV -#endif -#if CONFIG_LINUX_SPI == 1 - PROGRAMMER_LINUX_SPI -#endif -; -#endif +static enum programmer programmer = PROGRAMMER_INVALID; static char *programmer_param = NULL; @@ -515,9 +449,15 @@ return 0; } -int programmer_init(char *param) +int programmer_init(enum programmer prog, char *param) { int ret; + + if (prog >= PROGRAMMER_INVALID) { + msg_perr("Invalid programmer specified!\n"); + return -1; + } + programmer = prog; /* Initialize all programmer specific data. */ /* Default to unlimited decode sizes. */ max_rom_decode = (const struct decode_sizes) { Modified: trunk/it87spi.c ============================================================================== --- trunk/it87spi.c Wed Sep 7 22:48:34 2011 (r1432) +++ trunk/it87spi.c Thu Sep 8 02:00:29 2011 (r1433) @@ -129,10 +129,8 @@ enter_conf_mode_ite(port); /* NOLDN, reg 0x24, mask out lowest bit (suspend) */ tmp = sio_read(port, 0x24) & 0xFE; - /* If IT87SPI was not explicitly selected, we want to check - * quickly if LPC->SPI translation is active. - */ - if ((programmer == PROGRAMMER_INTERNAL) && !(tmp & (0x0E))) { + /* Check if LPC->SPI translation is active. */ + if (!(tmp & 0x0e)) { msg_pdbg("No IT87* serial flash segment enabled.\n"); exit_conf_mode_ite(port); /* Nothing to do. */ Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Wed Sep 7 22:48:34 2011 (r1432) +++ trunk/programmer.h Thu Sep 8 02:00:29 2011 (r1433) @@ -85,8 +85,6 @@ PROGRAMMER_INVALID /* This must always be the last entry. */ }; -extern enum programmer programmer; - struct programmer_entry { const char *vendor; const char *name; @@ -110,7 +108,7 @@ extern const struct programmer_entry programmer_table[]; -int programmer_init(char *param); +int programmer_init(enum programmer prog, char *param); int programmer_shutdown(void); enum bitbang_spi_master_type {

1 0

[PATCH 3/3] serprog: add support for setting the SPI frequency
by Stefan Tauner 07 Sep '11

07 Sep '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- serprog-protocol.txt | 8 ++++++++ serprog.c | 30 ++++++++++++++++++++++++++---- 2 files changed, 34 insertions(+), 4 deletions(-) diff --git a/serprog-protocol.txt b/serprog-protocol.txt index b22d1b2..0cf5432 100644 --- a/serprog-protocol.txt +++ b/serprog-protocol.txt @@ -33,6 +33,7 @@ COMMAND Description Parameters Return Value 0x12 Set used bustype 8-bit flags (as with 0x05) ACK / NAK 0x13 Perform SPI operation 24-bit slen + 24-bit rlen ACK + rlen bytes of data / NAK + slen bytes of data +0x14 Set SPI clock frequency 16-bit requested frequency ACK + 16-bit set frequency / NAK 0x?? unimplemented command - invalid. @@ -73,6 +74,12 @@ Additional information of the above commands: Maximum slen is Q_WRNMAXLEN result after Q_BUSTYPE returns only SPI or S_BUSTYPE == SPI is used. Same for rlen and Q_RDNMAXLEN. This operation is immediate, meaning it doesnt use the operation buffer. + 0x14 (S_SPI_SCK): + Set the SPI clock frequency. + The requested frequency should be mapped by the programmer software + to a supported frequency lower than the one requested. If there is + no lower frequency available the lowest possible should be used. + The value chosen is sent back in the reply with an ACK. About mandatory commands: The only truly mandatory commands for any device are 0x00, 0x01, 0x02 and 0x10, but one can't really do anything with these commands. @@ -107,3 +114,4 @@ This define listing should help C coders - (it's here to be the single source fo #define S_CMD_Q_RDNMAXLEN 0x11 /* Query read-n maximum length */ #define S_CMD_S_BUSTYPE 0x12 /* Set used bustype(s). */ #define S_CMD_O_SPIOP 0x13 /* Perform SPI operation. */ +#define S_CMD_S_SPI_SCK 0x14 /* Set SPI clock frequency */ diff --git a/serprog.c b/serprog.c index 182edd1..1b231a3 100644 --- a/serprog.c +++ b/serprog.c @@ -69,6 +69,7 @@ static int serprog_shutdown(void *data); #define S_CMD_Q_RDNMAXLEN 0x11 /* Query read-n maximum length */ #define S_CMD_S_BUSTYPE 0x12 /* Set used bustype(s). */ #define S_CMD_O_SPIOP 0x13 /* Perform SPI operation. */ +#define S_CMD_S_SPI_SCK 0x14 /* Set SPI clock frequency */ static uint16_t sp_device_serbuf_size = 16; static uint16_t sp_device_opbuf_size = 300; @@ -424,13 +425,14 @@ int serprog_init(void) } buses_supported = c; msg_pdbg(MSGHEADER "Bus support: parallel=%s, LPC=%s, FWH=%s, SPI=%s\n", - (c & CHIP_BUSTYPE_PARALLEL) ? "on" : "off", - (c & CHIP_BUSTYPE_LPC) ? "on" : "off", - (c & CHIP_BUSTYPE_FWH) ? "on" : "off", - (c & CHIP_BUSTYPE_SPI) ? "on" : "off"); + (c & BUS_PARALLEL) ? "on" : "off", + (c & BUS_LPC) ? "on" : "off", + (c & BUS_FWH) ? "on" : "off", + (c & BUS_SPI) ? "on" : "off"); /* Check for the minimum operational set of commands. */ if (buses_supported & BUS_SPI) { uint8_t bt = BUS_SPI; + char *f_spi; if (sp_check_commandavail(S_CMD_O_SPIOP) == 0) { msg_perr("Error: SPI operation not supported while the " "bustype is SPI\n"); @@ -461,6 +463,26 @@ int serprog_init(void) spi_programmer_serprog.max_data_read = v; msg_pdbg(MSGHEADER "Maximum read-n length is %d\n", v); } + f_spi = extract_programmer_param("sck"); + if (f_spi && strlen(f_spi)) { + uint8_t buf[2]; + uint16_t tmp = atoi(f_spi); + buf[0] = tmp & 0xFF; + buf[1] = tmp >> 8; + if (sp_check_commandavail(S_CMD_S_SPI_SCK) == 0) + msg_pdbg(MSGHEADER "Setting SPI clock rate is " + "not supported!\n"); + else if (sp_docommand(S_CMD_S_SPI_SCK, 2, buf, 2, buf) + == 0) { + tmp = buf[0] | (buf[1]<<8); + msg_pdbg(MSGHEADER "Requested to set SPI clock " + "frequency to %s kHz. It was actually " + "set to %d kHz\n", f_spi, tmp); + } else + msg_pdbg(MSGHEADER "Setting SPI clock rate " + "failed!\n"); + } + free(f_spi); bt = buses_supported; sp_docommand(S_CMD_S_BUSTYPE, 1, &bt, 0, NULL); register_spi_programmer(&spi_programmer_serprog); -- 1.7.1

1 0

[PATCH 2/3] serprog: small improvements
by Stefan Tauner 07 Sep '11

07 Sep '11

- rename serprog_delay parameter to usecs - fix code style, (output) formatting issues and comments - sp_docommand: remove unnecessary malloc+memcpy and fix formatting Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- programmer.h | 5 ++- serprog-protocol.txt | 2 +- serprog.c | 72 +++++++++++++++++++++++++------------------------ 3 files changed, 41 insertions(+), 38 deletions(-) diff --git a/programmer.h b/programmer.h index 1b7f591..6e78738 100644 --- a/programmer.h +++ b/programmer.h @@ -609,9 +609,10 @@ int serprog_init(void); void serprog_chip_writeb(uint8_t val, chipaddr addr); uint8_t serprog_chip_readb(const chipaddr addr); void serprog_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); -void serprog_delay(int delay); +void serprog_delay(int usecs); int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, - const unsigned char *writearr, unsigned char *readarr); + const unsigned char *writearr, + unsigned char *readarr); int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); #endif diff --git a/serprog-protocol.txt b/serprog-protocol.txt index 06e3bac..b22d1b2 100644 --- a/serprog-protocol.txt +++ b/serprog-protocol.txt @@ -19,7 +19,7 @@ COMMAND Description Parameters Return Value 0x05 Query supported bustypes none ACK + 8-bit flags (as per flashrom) / NAK 0x06 Query connected address lines none ACK + 8bit line count / NAK 0x07 Query operation buffer size none ACK + 16bit size / NAK -0x08 Query write-n maximum data len none ACK + 24bit maximum length / NAK +0x08 Query maximum write-n length none ACK + 24bit length (0==2^24) / NAK 0x09 Read byte 24-bit addr ACK + BYTE / NAK 0x0A Read n bytes 24-bit addr + 24-bit length ACK + length bytes / NAK 0x0B Initialize operation buffer none ACK / NAK diff --git a/serprog.c b/serprog.c index 915eb5b..182edd1 100644 --- a/serprog.c +++ b/serprog.c @@ -38,7 +38,7 @@ #include "programmer.h" #include "chipdrivers.h" -#define MSGHEADER "serprog:" +#define MSGHEADER "serprog: " /* * FIXME: This prototype was added to help reduce diffs for the shutdown @@ -204,7 +204,7 @@ static void sp_synchronize(void) return; } } - msg_perr("Error: cannot synchronize protocol\n" + msg_perr("Error: cannot synchronize protocol " "- check communications and reset device?\n"); exit(1); } @@ -220,32 +220,27 @@ static int sp_check_commandavail(uint8_t command) static int sp_automatic_cmdcheck(uint8_t cmd) { if ((sp_check_avail_automatic) && (sp_check_commandavail(cmd) == 0)) { - msg_pdbg("Warning: Automatic command availability check" - " failed for cmd %d - wont execute cmd\n",cmd); + msg_pdbg("Warning: Automatic command availability check failed " + "for cmd 0x%x - wont execute cmd\n", cmd); return 1; } return 0; } static int sp_docommand(uint8_t command, uint32_t parmlen, - uint8_t * params, uint32_t retlen, void *retparms) + uint8_t *params, uint32_t retlen, void *retparms) { - unsigned char *sendpacket; unsigned char c; if (sp_automatic_cmdcheck(command)) return 1; - sendpacket = malloc(1 + parmlen); - if (!sendpacket) - sp_die("Error: cannot malloc command buffer"); - sendpacket[0] = command; - memcpy(&(sendpacket[1]), params, parmlen); - if (write(sp_fd, sendpacket, 1 + parmlen) != (1 + parmlen)) { - sp_die("Error: cannot write command"); - } - free(sendpacket); + if (write(sp_fd, &command, 1) != 1) + sp_die("Error: cannot write op code"); + if (write(sp_fd, params, parmlen) != (parmlen)) + sp_die("Error: cannot write parameters"); if (read(sp_fd, &c, 1) != 1) sp_die("Error: cannot read from device"); - if (c == S_NAK) return 1; + if (c == S_NAK) + return 1; if (c != S_ACK) { msg_perr("Error: invalid response 0x%02X from device\n",c); exit(1); @@ -256,8 +251,8 @@ static int sp_docommand(uint8_t command, uint32_t parmlen, int r; r = read(sp_fd, retparms + rd_bytes, retlen - rd_bytes); - if (r <= 0) sp_die - ("Error: cannot read return parameters"); + if (r <= 0) + sp_die("Error: cannot read return parameters"); rd_bytes += r; } while (rd_bytes != retlen); } @@ -404,12 +399,12 @@ int serprog_init(void) msg_pdbg(MSGHEADER "Synchronized\n"); if (sp_docommand(S_CMD_Q_IFACE, 0, NULL, 2, &iface)) { - msg_perr("Error: NAK to Query Interface version\n"); + msg_perr("Error: NAK to query interface version\n"); exit(1); } if (iface != 1) { - msg_perr("Error: Unknown interface version %d\n", iface); + msg_perr("Error: Unknown interface version: %d\n", iface); exit(1); } @@ -428,6 +423,11 @@ int serprog_init(void) c = BUS_NONSPI; /* A reasonable default for now. */ } buses_supported = c; + msg_pdbg(MSGHEADER "Bus support: parallel=%s, LPC=%s, FWH=%s, SPI=%s\n", + (c & CHIP_BUSTYPE_PARALLEL) ? "on" : "off", + (c & CHIP_BUSTYPE_LPC) ? "on" : "off", + (c & CHIP_BUSTYPE_FWH) ? "on" : "off", + (c & CHIP_BUSTYPE_SPI) ? "on" : "off"); /* Check for the minimum operational set of commands. */ if (buses_supported & BUS_SPI) { uint8_t bt = BUS_SPI; @@ -538,12 +538,12 @@ int serprog_init(void) strcpy((char *)pgmname, "(unknown)"); } pgmname[16] = 0; - msg_pinfo(MSGHEADER "Programmer name \"%s\"\n", pgmname); + msg_pinfo(MSGHEADER "Programmer name is \"%s\"\n", pgmname); if (sp_docommand(S_CMD_Q_SERBUF, 0, NULL, 2, &sp_device_serbuf_size)) { msg_perr("Warning: NAK to query serial buffer size\n"); } - msg_pdbg(MSGHEADER "serial buffer size %d\n", + msg_pdbg(MSGHEADER "Serial buffer size is %d\n", sp_device_serbuf_size); if (sp_check_commandavail(S_CMD_O_INIT)) { @@ -564,7 +564,7 @@ int serprog_init(void) msg_perr("Warning: NAK to query operation buffer " "size\n"); } - msg_pdbg(MSGHEADER "operation buffer size %d\n", + msg_pdbg(MSGHEADER "operation buffer size is %d\n", sp_device_opbuf_size); } @@ -581,7 +581,7 @@ static void sp_pass_writen(void) { unsigned char header[7]; msg_pspew(MSGHEADER "Passing write-n bytes=%d addr=0x%x\n", - sp_write_n_bytes, sp_write_n_addr); + sp_write_n_bytes, sp_write_n_addr); if (sp_streamed_transmit_bytes >= (7 + sp_write_n_bytes + sp_device_serbuf_size)) sp_flush_stream(); @@ -735,30 +735,32 @@ void serprog_chip_readn(uint8_t * buf, const chipaddr addr, size_t len) { size_t lenm = len; chipaddr addrm = addr; - while ((sp_max_read_n)&&(lenm > sp_max_read_n)) { - sp_do_read_n(&(buf[addrm-addr]),addrm,sp_max_read_n); + while ((sp_max_read_n != 0) && (lenm > sp_max_read_n)) { + sp_do_read_n(&(buf[addrm-addr]), addrm, sp_max_read_n); addrm += sp_max_read_n; lenm -= sp_max_read_n; } - if (lenm) sp_do_read_n(&(buf[addrm-addr]),addrm,lenm); + if (lenm) + sp_do_read_n(&(buf[addrm-addr]), addrm, lenm); } -void serprog_delay(int delay) +void serprog_delay(int usecs) { unsigned char buf[4]; - msg_pspew("%s\n", __func__); + msg_pspew("%s usecs=%d\n", __func__, usecs); if (!sp_check_commandavail(S_CMD_O_DELAY)) { - internal_delay(delay); - msg_pdbg("Note: serprog_delay used, but the programmer doesnt support delay\n"); + msg_pdbg("Note: using internal_delay, because the attached " + "programmer does not support the delay opcode.\n"); + internal_delay(usecs); return; } if ((sp_max_write_n) && (sp_write_n_bytes)) sp_pass_writen(); sp_check_opbuf_usage(5); - buf[0] = ((delay >> 0) & 0xFF); - buf[1] = ((delay >> 8) & 0xFF); - buf[2] = ((delay >> 16) & 0xFF); - buf[3] = ((delay >> 24) & 0xFF); + buf[0] = ((usecs >> 0) & 0xFF); + buf[1] = ((usecs >> 8) & 0xFF); + buf[2] = ((usecs >> 16) & 0xFF); + buf[3] = ((usecs >> 24) & 0xFF); sp_stream_buffer_op(S_CMD_O_DELAY, 4, buf); sp_opbuf_usage += 5; sp_prev_was_write = 0; -- 1.7.1

1 0

[PATCH 1/3] serprog: add SPI support
by Stefan Tauner 07 Sep '11

07 Sep '11

Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- programmer.h | 6 + serprog-protocol.txt | 10 ++- serprog.c | 261 ++++++++++++++++++++++++++++++++++++-------------- 3 files changed, 204 insertions(+), 73 deletions(-) diff --git a/programmer.h b/programmer.h index f878a53..1b7f591 100644 --- a/programmer.h +++ b/programmer.h @@ -547,6 +547,9 @@ enum spi_controller { #if CONFIG_LINUX_SPI == 1 SPI_CONTROLLER_LINUX, #endif +#if CONFIG_SERPROG == 1 + SPI_CONTROLLER_SERPROG, +#endif }; extern const int spi_programmer_count; @@ -607,6 +610,9 @@ void serprog_chip_writeb(uint8_t val, chipaddr addr); uint8_t serprog_chip_readb(const chipaddr addr); void serprog_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); void serprog_delay(int delay); +int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr); +int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); #endif /* serial.c */ diff --git a/serprog-protocol.txt b/serprog-protocol.txt index 52f901a..06e3bac 100644 --- a/serprog-protocol.txt +++ b/serprog-protocol.txt @@ -31,6 +31,8 @@ COMMAND Description Parameters Return Value 0x10 Sync NOP none NAK + ACK (for synchronization) 0x11 Query maximum read-n length none ACK + 24-bit length (0==2^24) / NAK 0x12 Set used bustype 8-bit flags (as with 0x05) ACK / NAK +0x13 Perform SPI operation 24-bit slen + 24-bit rlen ACK + rlen bytes of data / NAK + + slen bytes of data 0x?? unimplemented command - invalid. @@ -50,7 +52,7 @@ Additional information of the above commands: it should return a big bogus value - eg 0xFFFF. 0x05 (Q_BUSTYPE): The bit's are defined as follows: - bit 0: PARALLEL, bit 1: LPC, bit 2: FWH, bit 3: SPI (if ever supported). + bit 0: PARALLEL, bit 1: LPC, bit 2: FWH, bit 3: SPI. 0x06 (Q_CHIPSIZE): Only applicable to parallel programmers. An LPC/FWH/SPI-programmer can report this as not supported in the command bitmap. @@ -66,6 +68,11 @@ Additional information of the above commands: Set's the used bustype if the programmer can support more than one flash protocol. Sending a byte with more than 1 bit set will make the programmer decide among them on it's own. Bit values as with Q_BUSTYPE. + 0x13 (O_SPIOP): + Send and receive bytes via SPI. + Maximum slen is Q_WRNMAXLEN result after Q_BUSTYPE returns + only SPI or S_BUSTYPE == SPI is used. Same for rlen and Q_RDNMAXLEN. + This operation is immediate, meaning it doesnt use the operation buffer. About mandatory commands: The only truly mandatory commands for any device are 0x00, 0x01, 0x02 and 0x10, but one can't really do anything with these commands. @@ -99,3 +106,4 @@ This define listing should help C coders - (it's here to be the single source fo #define S_CMD_SYNCNOP 0x10 /* Special no-operation that returns NAK+ACK */ #define S_CMD_Q_RDNMAXLEN 0x11 /* Query read-n maximum length */ #define S_CMD_S_BUSTYPE 0x12 /* Set used bustype(s). */ +#define S_CMD_O_SPIOP 0x13 /* Perform SPI operation. */ diff --git a/serprog.c b/serprog.c index 3adb958..915eb5b 100644 --- a/serprog.c +++ b/serprog.c @@ -1,7 +1,7 @@ /* * This file is part of the flashrom project. * - * Copyright (C) 2009 Urja Rannikko <urjaman(a)gmail.com> + * Copyright (C) 2009, 2011 Urja Rannikko <urjaman(a)gmail.com> * Copyright (C) 2009 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify @@ -36,6 +36,7 @@ #include <termios.h> #include "flash.h" #include "programmer.h" +#include "chipdrivers.h" #define MSGHEADER "serprog:" @@ -67,6 +68,7 @@ static int serprog_shutdown(void *data); #define S_CMD_SYNCNOP 0x10 /* Special no-operation that returns NAK+ACK */ #define S_CMD_Q_RDNMAXLEN 0x11 /* Query read-n maximum length */ #define S_CMD_S_BUSTYPE 0x12 /* Set used bustype(s). */ +#define S_CMD_O_SPIOP 0x13 /* Perform SPI operation. */ static uint16_t sp_device_serbuf_size = 16; static uint16_t sp_device_opbuf_size = 300; @@ -302,6 +304,16 @@ static int sp_stream_buffer_op(uint8_t cmd, uint32_t parmlen, uint8_t * parms) return 0; } +static struct spi_programmer spi_programmer_serprog = { + .type = SPI_CONTROLLER_SERPROG, + .max_data_read = MAX_DATA_READ_UNLIMITED, + .max_data_write = MAX_DATA_WRITE_UNLIMITED, + .command = serprog_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = serprog_spi_read, + .write_256 = default_spi_write_256, +}; + int serprog_init(void) { uint16_t iface; @@ -325,7 +337,7 @@ int serprog_init(void) msg_perr("Error: No baudrate specified.\n" "Use flashrom -p serprog:dev=/dev/device:baud\n"); free(device); - return 1; + return 1; } if (strlen(device)) { sp_fd = sp_openserport(device, atoi(baudport)); @@ -358,7 +370,7 @@ int serprog_init(void) msg_perr("Error: No port specified.\n" "Use flashrom -p serprog:ip=ipaddr:port\n"); free(device); - return 1; + return 1; } if (strlen(device)) { sp_fd = sp_opensocket(device, atoi(baudport)); @@ -410,35 +422,115 @@ int serprog_init(void) sp_check_avail_automatic = 1; - /* Check for the minimum operational set of commands */ - if (sp_check_commandavail(S_CMD_R_BYTE) == 0) { - msg_perr("Error: Single byte read not supported\n"); - exit(1); - } - /* This could be translated to single byte reads (if missing), * - * but now we dont support that. */ - if (sp_check_commandavail(S_CMD_R_NBYTES) == 0) { - msg_perr("Error: Read n bytes not supported\n"); - exit(1); - } - /* In the future one could switch to read-only mode if these * - * are not available. */ - if (sp_check_commandavail(S_CMD_O_INIT) == 0) { - msg_perr("Error: Initialize operation buffer not supported\n"); - exit(1); - } - if (sp_check_commandavail(S_CMD_O_WRITEB) == 0) { - msg_perr("Error: Write to opbuf: write byte not supported\n"); - exit(1); + + if (sp_docommand(S_CMD_Q_BUSTYPE, 0, NULL, 1, &c)) { + msg_perr("Warning: NAK to query supported buses\n"); + c = BUS_NONSPI; /* A reasonable default for now. */ } - if (sp_check_commandavail(S_CMD_O_DELAY) == 0) { - msg_perr("Error: Write to opbuf: delay not supported\n"); - exit(1); + buses_supported = c; + /* Check for the minimum operational set of commands. */ + if (buses_supported & BUS_SPI) { + uint8_t bt = BUS_SPI; + if (sp_check_commandavail(S_CMD_O_SPIOP) == 0) { + msg_perr("Error: SPI operation not supported while the " + "bustype is SPI\n"); + exit(1); + } + /* Success of any of these commands is optional. We dont need + the programmer to tell us it's limits, but if it doesnt, we + will assume stuff, so it's in the programmers best interest + to tell us. */ + sp_docommand(S_CMD_S_BUSTYPE, 1, &bt, 0, NULL); + if (!sp_docommand(S_CMD_Q_WRNMAXLEN, 0, NULL, 3, rbuf)) { + uint32_t v; + v = ((unsigned int)(rbuf[0]) << 0); + v |= ((unsigned int)(rbuf[1]) << 8); + v |= ((unsigned int)(rbuf[2]) << 16); + if (v == 0) + v = (1 << 24) - 1; /* SPI-op maximum. */ + spi_programmer_serprog.max_data_write = v; + msg_pdbg(MSGHEADER "Maximum write-n length is %d\n", v); + } + if (!sp_docommand(S_CMD_Q_RDNMAXLEN, 0, NULL, 3, rbuf)) { + uint32_t v; + v = ((unsigned int)(rbuf[0]) << 0); + v |= ((unsigned int)(rbuf[1]) << 8); + v |= ((unsigned int)(rbuf[2]) << 16); + if (v == 0) + v = (1 << 24) - 1; /* SPI-op maximum. */ + spi_programmer_serprog.max_data_read = v; + msg_pdbg(MSGHEADER "Maximum read-n length is %d\n", v); + } + bt = buses_supported; + sp_docommand(S_CMD_S_BUSTYPE, 1, &bt, 0, NULL); + register_spi_programmer(&spi_programmer_serprog); } - if (sp_check_commandavail(S_CMD_O_EXEC) == 0) { - msg_perr( - "Error: Execute operation buffer not supported\n"); - exit(1); + + if (buses_supported & BUS_NONSPI) { + if (sp_check_commandavail(S_CMD_O_INIT) == 0) { + msg_perr("Error: Initialize operation buffer " + "not supported\n"); + exit(1); + } + + if (sp_check_commandavail(S_CMD_O_DELAY) == 0) { + msg_perr("Error: Write to opbuf: " + "delay not supported\n"); + exit(1); + } + + /* S_CMD_O_EXEC availability checked later. */ + + if (sp_check_commandavail(S_CMD_R_BYTE) == 0) { + msg_perr("Error: Single byte read not supported\n"); + exit(1); + } + /* This could be translated to single byte reads (if missing), + * but now we dont support that. */ + if (sp_check_commandavail(S_CMD_R_NBYTES) == 0) { + msg_perr("Error: Read n bytes not supported\n"); + exit(1); + } + if (sp_check_commandavail(S_CMD_O_WRITEB) == 0) { + msg_perr("Error: Write to opbuf: " + "write byte not supported\n"); + exit(1); + } + + if (sp_docommand(S_CMD_Q_WRNMAXLEN, 0, NULL, 3, rbuf)) { + msg_pdbg(MSGHEADER "Write-n not supported"); + sp_max_write_n = 0; + } else { + sp_max_write_n = ((unsigned int)(rbuf[0]) << 0); + sp_max_write_n |= ((unsigned int)(rbuf[1]) << 8); + sp_max_write_n |= ((unsigned int)(rbuf[2]) << 16); + if (!sp_max_write_n) { + sp_max_write_n = (1 << 24); + } + msg_pdbg(MSGHEADER "Maximum write-n length is %d\n", + sp_max_write_n); + sp_write_n_buf = malloc(sp_max_write_n); + if (!sp_write_n_buf) { + msg_perr("Error: cannot allocate memory for " + "Write-n buffer\n"); + exit(1); + } + sp_write_n_bytes = 0; + } + + if (sp_check_commandavail(S_CMD_Q_RDNMAXLEN) && + (sp_docommand(S_CMD_Q_RDNMAXLEN, 0, NULL, 3, rbuf) == 0)) { + sp_max_read_n = ((unsigned int)(rbuf[0]) << 0); + sp_max_read_n |= ((unsigned int)(rbuf[1]) << 8); + sp_max_read_n |= ((unsigned int)(rbuf[2]) << 16); + msg_pdbg(MSGHEADER "Maximum read-n length is %d\n", + sp_max_read_n ? sp_max_read_n : (1 << 24)); + } else { + msg_pdbg(MSGHEADER "Maximum read-n length " + "not reported\n"); + sp_max_read_n = 0; + } + } if (sp_docommand(S_CMD_Q_PGMNAME, 0, NULL, 16, pgmname)) { @@ -454,51 +546,27 @@ int serprog_init(void) msg_pdbg(MSGHEADER "serial buffer size %d\n", sp_device_serbuf_size); - if (sp_docommand(S_CMD_Q_OPBUF, 0, NULL, 2, &sp_device_opbuf_size)) { - msg_perr("Warning: NAK to query operation buffer size\n"); - } - msg_pdbg(MSGHEADER "operation buffer size %d\n", - sp_device_opbuf_size); - - if (sp_docommand(S_CMD_Q_BUSTYPE, 0, NULL, 1, &c)) { - msg_perr("Warning: NAK to query supported buses\n"); - c = BUS_NONSPI; /* A reasonable default for now. */ - } - buses_supported = c; - - if (sp_docommand(S_CMD_O_INIT, 0, NULL, 0, NULL)) { - msg_perr("Error: NAK to initialize operation buffer\n"); - exit(1); - } + if (sp_check_commandavail(S_CMD_O_INIT)) { + /* This would be inconsistent. */ + if (sp_check_commandavail(S_CMD_O_EXEC) == 0) { + msg_perr("Error: Execute operation buffer not " + "supported\n"); + exit(1); + } - if (sp_docommand(S_CMD_Q_WRNMAXLEN, 0, NULL, 3, rbuf)) { - msg_pdbg(MSGHEADER "Write-n not supported"); - sp_max_write_n = 0; - } else { - sp_max_write_n = ((unsigned int)(rbuf[0]) << 0); - sp_max_write_n |= ((unsigned int)(rbuf[1]) << 8); - sp_max_write_n |= ((unsigned int)(rbuf[2]) << 16); - msg_pdbg(MSGHEADER "Maximum write-n length %d\n", - sp_max_write_n); - sp_write_n_buf = malloc(sp_max_write_n); - if (!sp_write_n_buf) { - msg_perr("Error: cannot allocate memory for Write-n buffer\n"); + if (sp_docommand(S_CMD_O_INIT, 0, NULL, 0, NULL)) { + msg_perr("Error: NAK to initialize operation buffer\n"); exit(1); } - sp_write_n_bytes = 0; - } - - if ((sp_check_commandavail(S_CMD_Q_RDNMAXLEN)) - &&((sp_docommand(S_CMD_Q_RDNMAXLEN,0,NULL, 3, rbuf) == 0))) { - sp_max_read_n = ((unsigned int)(rbuf[0]) << 0); - sp_max_read_n |= ((unsigned int)(rbuf[1]) << 8); - sp_max_read_n |= ((unsigned int)(rbuf[2]) << 16); - msg_pdbg(MSGHEADER "Maximum read-n length %d\n", - sp_max_read_n ? sp_max_read_n : (1<<24)); - } else { - msg_pdbg(MSGHEADER "Maximum read-n length not reported\n"); - sp_max_read_n = 0; - } + + if (sp_docommand(S_CMD_Q_OPBUF, 0, NULL, 2, + &sp_device_opbuf_size)) { + msg_perr("Warning: NAK to query operation buffer " + "size\n"); + } + msg_pdbg(MSGHEADER "operation buffer size %d\n", + sp_device_opbuf_size); + } sp_prev_was_write = 0; sp_streamed_transmit_ops = 0; @@ -679,6 +747,11 @@ void serprog_delay(int delay) { unsigned char buf[4]; msg_pspew("%s\n", __func__); + if (!sp_check_commandavail(S_CMD_O_DELAY)) { + internal_delay(delay); + msg_pdbg("Note: serprog_delay used, but the programmer doesnt support delay\n"); + return; + } if ((sp_max_write_n) && (sp_write_n_bytes)) sp_pass_writen(); sp_check_opbuf_usage(5); @@ -690,3 +763,47 @@ void serprog_delay(int delay) sp_opbuf_usage += 5; sp_prev_was_write = 0; } + +int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + unsigned char *parmbuf; + int ret; + msg_pspew("%s, writecnt=%i, readcnt=%i\n", __func__, writecnt, readcnt); + if ((sp_opbuf_usage) || (sp_max_write_n && sp_write_n_bytes)) + sp_execute_opbuf(); + parmbuf = malloc(writecnt + 6); + if (!parmbuf) + sp_die("Error: cannot malloc SPI send param buffer"); + parmbuf[0] = (writecnt >> 0) & 0xFF; + parmbuf[1] = (writecnt >> 8) & 0xFF; + parmbuf[2] = (writecnt >> 16) & 0xFF; + parmbuf[3] = (readcnt >> 0) & 0xFF; + parmbuf[4] = (readcnt >> 8) & 0xFF; + parmbuf[5] = (readcnt >> 16) & 0xFF; + memcpy(parmbuf + 6, writearr, writecnt); + ret = sp_docommand(S_CMD_O_SPIOP, writecnt + 6, parmbuf, readcnt, + readarr); + free(parmbuf); + return ret; +} + +/* FIXME: This function is optimized so that it does not split each + * transaction into chip page_size long blocks unnecessarily like + * spi_read_chunked. When spi_read_chunked is fixed this method can be + * removed. */ +int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + int i; + const int max_read = spi_programmer_serprog.max_data_read; + for(i = 0; i < len; ) { + int ret; + int cur_len = min(max_read, (len - i)); + ret = spi_nbyte_read(start + i, buf + i, cur_len); + if (ret) + return ret; + i += cur_len; + } + return 0; +} -- 1.7.1

1 0

[PATCH 0/3] serprog improvements 2.0
by Stefan Tauner 07 Sep '11

07 Sep '11

hey! uwe signaled that he wants to review this, so here is a rebased (onto r1432)) version. i have integrated all fixups to date, but there should probably be a few dbg -> dbg2 conversions too... this can wait though: getting SPI support for serprog is probably useful for quite a few people (since there have been 2,5 implementations from 3 ppl for this already ;) this is untested, but i will test it with spi hardware before committing. anyone around with other interfaces who can test those? Stefan Tauner (3): serprog: add SPI support serprog: small improvements serprog: add support for setting the SPI frequency programmer.h | 9 +- serprog-protocol.txt | 20 +++- serprog.c | 349 +++++++++++++++++++++++++++++++++++--------------- 3 files changed, 271 insertions(+), 107 deletions(-)

1 0

[PATCH] Add Linux SPI support
by Sven Schnelle 07 Sep '11

07 Sep '11

Hi List, this patch adds support for the Linux SPI subsystem. See http://www.kernel.org/doc/Documentation/spi/spidev for a short introduction. Usage is as follows: flashrom -p linux_spi:dev=/dev/spidevX.Y where X is the bus number, and Y device. It accepts an optional parameter 'speed' which allows to set the SPI CLK speed in KHz. I'm using a AVR32 Board (http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4102) to program my ThinkPad X60, but it should work on every Linux system. Signed-off-by: Sven Schnelle <svens(a)stackframe.org>

3 6

[commit] r1432 - trunk
by repository service 07 Sep '11

07 Sep '11

Author: uwe Date: Wed Sep 7 22:48:34 2011 New Revision: 1432 URL: http://flashrom.org/trac/flashrom/changeset/1432 Log: Small fixes for the linux_spi programmer code. Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/linux_spi.c Modified: trunk/linux_spi.c ============================================================================== --- trunk/linux_spi.c Wed Sep 7 22:20:25 2011 (r1431) +++ trunk/linux_spi.c Wed Sep 7 22:48:34 2011 (r1432) @@ -54,7 +54,7 @@ int linux_spi_init(void) { char *p, *endp, *dev; - int speed = 0; + uint32_t speed = 0; dev = extract_programmer_param("dev"); if (!dev || !strlen(dev)) { @@ -65,24 +65,29 @@ p = extract_programmer_param("speed"); if (p && strlen(p)) { - speed = strtoul(p, &endp, 10) * 1024; + speed = (uint32_t)strtoul(p, &endp, 10) * 1024; if (p == endp) { msg_perr("%s: invalid clock: %s kHz\n", __func__, p); return 1; } } + msg_pdbg("Using device %s\n", dev); if ((fd = open(dev, O_RDWR)) == -1) { msg_perr("%s: failed to open %s: %s\n", __func__, dev, strerror(errno)); return 1; } - if (speed > 0 && ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed) == -1) { - msg_perr("%s: failed to set speed %dHz: %s\n", - __func__, speed, strerror(errno)); - close(fd); - return 1; + if (speed > 0) { + if (ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed) == -1) { + msg_perr("%s: failed to set speed %dHz: %s\n", + __func__, speed, strerror(errno)); + close(fd); + return 1; + } + + msg_pdbg("Using %d kHz clock\n", speed); } if (register_shutdown(linux_spi_shutdown, NULL))

1 0

[PATCH] Mark the GIGABYTE GA-8I945GZME-RH / SST25LF040A.RES as supported
by Uwe Hermann 07 Sep '11

07 Sep '11

Hi, see patch. Not sure if I should mark the SST25VF040.REMS as supported too? The code worked too, but it's not the correct chip, of course. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

1 1

[commit] r1431 - trunk
by repository service 07 Sep '11

07 Sep '11

Author: uwe Date: Wed Sep 7 22:20:25 2011 New Revision: 1431 URL: http://flashrom.org/trac/flashrom/changeset/1431 Log: Mark the GIGABYTE GA-8I945GZME-RH and SST SST25LF040A as supported. Success report: http://www.flashrom.org/pipermail/flashrom/2011-June/006797.html lspci and other info: http://www.flashrom.org/pipermail/flashrom/2010-August/004531.html Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/flashchips.c trunk/print.c Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Wed Sep 7 21:18:25 2011 (r1430) +++ trunk/flashchips.c Wed Sep 7 22:20:25 2011 (r1431) @@ -5583,7 +5583,7 @@ .model_id = SST_SST25VF040_REMS, .total_size = 512, .page_size = 256, - .tested = TEST_OK_PROBE, + .tested = TEST_OK_PREW, .probe = probe_spi_res2, .probe_timing = TIMING_ZERO, .block_erasers = Modified: trunk/print.c ============================================================================== --- trunk/print.c Wed Sep 7 21:18:25 2011 (r1430) +++ trunk/print.c Wed Sep 7 22:20:25 2011 (r1431) @@ -545,6 +545,7 @@ B("GIGABYTE", "GA-7DXR", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1302", NULL), B("GIGABYTE", "GA-7VT600", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1666", NULL), B("GIGABYTE", "GA-7ZM", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1366", "Works fine if you remove jumper JP9 on the board and disable the flash protection BIOS option."), + B("GIGABYTE", "GA-8I945GZME-RH", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=2304", NULL), B("GIGABYTE", "GA-8IP775", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1830", NULL), B("GIGABYTE", "GA-8IRML", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1343", NULL), B("GIGABYTE", "GA-8PE667 Ultra 2", 1, "http://www.gigabyte.com/products/product-page.aspx?pid=1607", NULL),

1 0

Submitting patches for flashrom?
by Feldschmid, Ingo 07 Sep '11

07 Sep '11

Hi there, How do I submit patches if I have changed code for the flashrom utility? Do I just post them here, or do I have to do something else? (I have mailed changes to support the Intel Tunnel Creek SPI chipset, but didn't get any response so far, so I assume I have to do something else?) Best regards, Ingo Es gelten unsere Allgemeinen Leistungsbedingungen die unter http://www.msc-ge.com/alb abrufbar sind. Our standard terms and conditions apply which are available under http://www.msc-ge.com/alb . MSC Vertriebs GmbH Sitz der Gesellschaft: Industriestrasse 16, 76297 Stutensee Handelsregister: Mannheim, HRB Nr. 10 3631 Geschaftsfuhrung: Manfred Schwarztrauber, Lothar Kummerlin, Rudiger Kuhn, Silvano Geissler Umsatzsteuer ID Nr.: DE 143 585 507 WEEE Reg. Nr. : DE 31011852 Gleichmann & Co. Electronics GmbH Sitz der Gesellschaft: Schraderstrasse 44, 67227 Frankenthal Handelsregister: Ludwigshafen, HRB Nr. 21305 Geschaftsfuhrung: Manfred Schwarztrauber, Thomas Klein Umsatzsteuer ID Nr. : DE 148 421 329 WEEE Reg. Nr.: DE 72277043 Diese E-Mail enthalt vertrauliche und/ oder rechtlich geschutzte Informationen. Wenn Sie nicht der beabsichtigte Empfanger sind, informieren Sie bitte sofort den Absender und loschen Sie diese E-Mail. The information contained in this message is confidential and/ or protected by law. If you are not the intended recipient, please contact the sender and delete this message.

4 3

[commit] r1430 - trunk
by repository service 07 Sep '11

07 Sep '11

Author: uwe Date: Wed Sep 7 21:18:25 2011 New Revision: 1430 URL: http://flashrom.org/trac/flashrom/changeset/1430 Log: Add Intel Tunnel Creek chipset support, mark it as tested. Intel's Tunnel Creek chipset supports both an SPI and an LPC bus. Set the chipset table entry for Tunnel Creek to the new function enable_flash_tunnelcreek(), which will read the hardware straps and return support for the bus that has been used for booting. This function uses ich_init_spi() with ich_generation set to 7 for initializing the SPI bus if necessary. SPI functionality tested on actual hardware, Tunnel Creek LPC interface not tested yet (missing hardware for that). Log file / success report: http://www.flashrom.org/pipermail/flashrom/2011-September/007823.html Signed-off-by: Ingo Feldschmid <ifel(a)msc-ge.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/chipset_enable.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Tue Sep 6 20:49:31 2011 (r1429) +++ trunk/chipset_enable.c Wed Sep 7 21:18:25 2011 (r1430) @@ -437,6 +437,50 @@ return 0; } +static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name) +{ + uint16_t old, new; + uint32_t tmp, bnt; + void *rcrb; + int ret; + + /* Enable Flash Writes */ + ret = enable_flash_ich(dev, name, 0xd8); + if (ret == ERROR_FATAL) + return ret; + + /* Make sure BIOS prefetch mechanism is disabled */ + old = pci_read_byte(dev, 0xd9); + msg_pdbg("BIOS Prefetch Enable: %sabled, ", (old & 1) ? "en" : "dis"); + new = old & ~1; + if (new != old) + rpci_write_byte(dev, 0xd9, new); + + /* Get physical address of Root Complex Register Block */ + tmp = pci_read_long(dev, 0xf0) & 0xffffc000; + msg_pdbg("\nRoot Complex Register Block address = 0x%x\n", tmp); + + /* Map RCBA to virtual memory */ + rcrb = physmap("ICH RCRB", tmp, 0x4000); + + /* Test Boot BIOS Strap Status */ + bnt = mmio_readl(rcrb + 0x3410); + if (bnt & 0x02) { + /* If strapped to LPC, no SPI initialization is required */ + buses_supported = BUS_FWH; + return 0; + } + + /* This adds BUS_SPI */ + buses_supported = BUS_SPI; + if (ich_init_spi(dev, tmp, rcrb, 7) != 0) { + if (!ret) + ret = ERROR_NONFATAL; + } + + return ret; +} + static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name) { /* Do we really need no write enable? */ @@ -1268,7 +1312,7 @@ {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4}, {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4}, {0x8086, 0x8119, OK, "Intel", "SCH Poulsbo", enable_flash_poulsbo}, - {0x8086, 0x8186, NT, "Intel", "Atom E6xx(T)/Tunnel Creek", enable_flash_poulsbo}, + {0x8086, 0x8186, OK, "Intel", "Atom E6xx(T)/Tunnel Creek", enable_flash_tunnelcreek}, #endif {}, };

1 0

Flashrom failed on Axiomtek eBOX620-823 embedded computer
by Kenneth Frost 07 Sep '11

07 Sep '11

Greetings, I tried to flash this system with an updated bios using flashrom utility. The flash chip found was a "SST 49LF008A". I successfully read the flash to a filename, verified the image read and determined the flash chip on the board. I still have the system up and running. Information on the motherboard can be found at: http://us.axiomtek.com/Products/ViewProduct.asp?view=780 Are there other options available to resurrect the Bios? Best regards, Ken Frost -- OEM CONTROLS Inc. 10 Controls Drive work: (203) 929-8431 Shelton, CT 06484 email: kfrost(a)oemcontrols.com

3 5

[PATCH 1/1] Introduce ERROR_FATAL in chipset enables
by Tadas Slotkus 06 Sep '11

06 Sep '11

Currently we are continuing even if chipset enable has failed. Some chipset enables do exits, so to kill those exits I have prepared one sneaky check :) Errors are negative there, so I have chosen this constant. Signed-off-by: Tadas Slotkus <devtadas(a)gmail.com> --- chipset_enable.c | 4 ++++ flash.h | 3 ++- internal.c | 3 ++- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index 687682a..f6c5d81 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1289,6 +1289,10 @@ int chipset_flash_enable(void) msg_pinfo("OK.\n"); else if (ret == ERROR_NONFATAL) msg_pinfo("PROBLEMS, continuing anyway\n"); + else if (ret == ERROR_FATAL) { + msg_perr("FATAL ERROR!\n") + return ret; + } } s = flashbuses_to_text(buses_supported); diff --git a/flash.h b/flash.h index 3d47a16..7386ecb 100644 --- a/flash.h +++ b/flash.h @@ -224,8 +224,9 @@ int write_buf_to_file(unsigned char *buf, unsigned long size, const char *filena #define OK 0 #define NT 1 /* Not tested */ -/* Something happened that shouldn't happen, but we can go on */ +/* Something happened that shouldn't happen, but we can go on, or not */ #define ERROR_NONFATAL 0x100 +#define ERROR_FATAL -0xEE /* cli_output.c */ /* Let gcc and clang check for correct printf-style format strings. */ diff --git a/internal.c b/internal.c index 846cf1e..46836b7 100644 --- a/internal.c +++ b/internal.c @@ -268,7 +268,8 @@ int internal_init(void) if (ret == -2) { msg_perr("WARNING: No chipset found. Flash detection " "will most likely fail.\n"); - } + } else if (ret == ERROR_FATAL) + return ret; #if defined(__i386__) || defined(__x86_64__) /* Probe unconditionally for IT87* LPC->SPI translation and for -- 1.7.6

3 9

[commit] r1429 - trunk
by repository service 06 Sep '11

06 Sep '11

Author: uwe Date: Tue Sep 6 20:49:31 2011 New Revision: 1429 URL: http://flashrom.org/trac/flashrom/changeset/1429 Log: Kill all exit() calls in chipset_enable.c. Signed-off-by: Tadas Slotkus <devtadas(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/chipset_enable.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Tue Sep 6 20:17:02 2011 (r1428) +++ trunk/chipset_enable.c Tue Sep 6 20:49:31 2011 (r1429) @@ -343,10 +343,7 @@ msg_perr("Error: fwh_idsel= specified, but no value given.\n"); idsel_garbage_out: free(idsel); - /* FIXME: Return failure here once internal_init() starts - * to care about the return value of the chipset enable. - */ - exit(1); + return ERROR_FATAL; } free(idsel); @@ -489,6 +486,8 @@ /* Enable Flash Writes */ ret = enable_flash_ich_dc(dev, name); + if (ret == ERROR_FATAL) + return ret; /* Get physical address of Root Complex Register Block */ tmp = pci_read_long(dev, 0xf0) & 0xffffc000; @@ -894,7 +893,7 @@ if (!smbusdev) { msg_perr("ERROR: SMBus device not found. Aborting.\n"); - exit(1); + return ERROR_FATAL; } /* Enable some SMBus stuff. */

1 0

[commit] r1428 - trunk
by repository service 06 Sep '11

06 Sep '11

Author: uwe Date: Tue Sep 6 20:17:02 2011 New Revision: 1428 URL: http://flashrom.org/trac/flashrom/changeset/1428 Log: Fix linux_spi.c build on 32bit systems. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/linux_spi.c Modified: trunk/linux_spi.c ============================================================================== --- trunk/linux_spi.c Sat Sep 3 20:37:52 2011 (r1427) +++ trunk/linux_spi.c Tue Sep 6 20:17:02 2011 (r1428) @@ -107,11 +107,11 @@ { struct spi_ioc_transfer msg[2] = { { - .tx_buf = (uint64_t)txbuf, + .tx_buf = (uint64_t)(ptrdiff_t)txbuf, .len = writecnt, }, { - .rx_buf = (uint64_t)rxbuf, + .rx_buf = (uint64_t)(ptrdiff_t)rxbuf, .len = readcnt, }, };

1 0

NVIDIA MCP67 chipset in HP DV9820US running flashrom -V results
by Jon Jensen 06 Sep '11

06 Sep '11

Here is the output when I ran "sudo flashrom -V" on my HP DV9820US laptop under 64-bit Ubuntu 10.04.3 LTS Lucid Lynx: http://h10025.www1.hp.com/ewfrf/wc/searchResults?product=3689897&tmp_qt=dri… http://h10025.www1.hp.com/ewfrf/wc/product?product=3689897&lc=en&cc=us&dlc=… --------------BEGIN QUOTED flashrom v0.9.1-r946 No coreboot table found. DMI string system-manufacturer: "Hewlett-Packard" DMI string system-product-name: "HP Pavilion dv9700 Notebook PC " DMI string system-version: "Rev 1" DMI string baseboard-manufacturer: "Quanta" DMI string baseboard-product-name: "30D1" DMI string baseboard-version: "85.26" DMI string chassis-type: "Notebook" Laptop detected via DMI ======================================================================== WARNING! You seem to be running flashrom on a laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See http://www.flashrom.org/Laptops for details. ======================================================================== Found chipset "NVIDIA MCP67", enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 Guessed flash bus type is LPC Found SMBus device 10de:0542 at 00:01:1 SPI BAR is at 0xf2300000, after clearing low bits BAR is at 0xf2300000 Strange. MCP SPI BAR is valid, but chipset apparently doesn't have SPI enabled. Please send the output of "flashrom -V" to flashrom(a)flashrom.org to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: LPC. Calibrating delay loop... 97M loops per second, 100 myus = 34 us. OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F016D, 2048 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F080B, 1024 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29LV040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29LV081B, 1024 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ASD AE49F2008, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT29C010A, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT29C020, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT29C040A, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N), 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMIC A25L40PT, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for AMIC A25L40PU, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMIC A29002T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMIC A29040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for EMST F49B002UA, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Eon EN25B05, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B05T, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B10T, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B20T, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B40T, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B80T, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B16T, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B32T, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B64T, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN29F010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Intel 28F004S5, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Intel 82802AB, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Intel 82802AC, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Macronix MX25L512, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm29F002T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for PMC Pm29F002B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0x19, id2 0x6b, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Sharp LHF00L04, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Spansion S25FL008A, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST29EE010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST29LE010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST29EE020A, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST29LE020, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39SF512, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39SF010A, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39SF020A, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39SF040, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF512, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF020, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF040, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF080, 1024 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST49LF002A/B, 256 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF003A/B, 384 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF004A/B, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF004C, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF008A, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF008C, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF016C, 2048 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0x19, id2 0x6b, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0x19, id2 0x6b, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x02, id2 0x01, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M25P05-A, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29F040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29F400BT, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29W010B, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29W040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29W512B, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x4e, id2 0x41 Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x4e, id2 0x41 Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0x02, id2 0x01 Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0x02, id2 0x01 Probing for ST M50FW002, 256 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for ST M50FW016, 2048 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for ST M50FW040, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for ST M50FW080, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W25x10, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x32, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x64, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W29C020C, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W29C040P, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W29EE011, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0x02, id2 0x01, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0x19, id2 0x6b, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Winbond W39V080FA, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically. ---------------------------END QUOTED

2 1

Flashrom 0.9.4-r1395 compiled, running, detected Flash modchip on Xbox running Linux
by Matt Falcon 06 Sep '11

06 Sep '11

Here's a curiosity of the day... :) I knew my Xbox used an LPC Flash ROM for its modchip, and that it could flash its own ROMs once a chip is installed. And I had restored a bad BIOS onto a PC*. Lack of an LPC-compatible board, and failure in my serprog+Arduino endeavors, I was kinda looking for anything. So, putting these things together, I thought I'd try getting Flashrom working inside XDSL. Most of the work was done through VNC, as jerking around with an on-screen keyboard and the Xbox controller was hardly rewarding... * -Flashrom seems to have some "read" bugs - it's bricked 2 different PCs so far by restoring a backup it made - the file was mostly correct, but uniformly-but-lightly littered with "p____________" ("p" followed by about 24 0x00 bytes) garbage data - found out after-the-fact when looking back at the backup data! As you can see in the photo (attached), it runs, but doesn't detect the chipset (though it somehow detects the flash - weird!). This is properly identified as well, and that's even going through an LPC adapter chip of some sort (Xilinx something-or-other on the modchip, a Duo X2). I hadn't tested read/write, since that wasn't the chip I needed to flash. Sadly, if I hot-swap the chip into the Xbox while it's booted, it craps out and freezes. I can only do it in a tiny 3-4 second window after powering it on, while the Xbox animation is playing (presumably it's already loaded the ROM into memory). That works, but I haven't been able to get it to detect the chip yet. I still get the same chipset error, but it doesn't detect the SST49LF020 chip I'm trying to test with (ultimately I have a SST49LF040B that I need to program). But anywho, I figured this might be some useful, or at least entertaining, information. Yup, Flashrom runs on an Xbox. :) - Matt

1 0

Re: [flashrom] report for Intel QM67 | Winbond W25Q64 - layout patches
by Stefan Tauner 05 Sep '11

05 Sep '11

On Mon, 5 Sep 2011 10:00:24 +0200 "Frei, Thomas (GE Germany)" <Thomas.Frei(a)ge.com> wrote: > Hi Stefan, > > today I loaded the sources again and I got the R1427. > > The patches do not work on this. > > So: What revision will I have to check out? Which revision are the patches for? > i have answered this multiple times already e.g. in http://www.flashrom.org/pipermail/flashrom/2011-August/007751.html you have even quoted it below your message: > i am not using svn but i think the right command to fetch the correct version of source for those patches is: > svn update -r 1421 -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

Re: [flashrom] report for Intel QM67 | Winbond W25Q64 - layout patches
by Paul Menzel 05 Sep '11

05 Sep '11

Dear Thomas, Am Montag, den 05.09.2011, 10:00 +0200 schrieb Frei, Thomas (GE Germany): > today I loaded the sources again and I got the R1427. > > The patches do not work on this. > > So: What revision will I have to check out? Which revision are the patches for? we asked you several times to paste your steps/commands into the message. Please do as we ask you to as otherwise it is very time consuming to help you. Thanks, Paul PS: Are you subscribed to the list? Do I have to put your address into CC?

1 0

Re: [flashrom] report for Intel QM67 | Winbond W25Q64 - layout patches
by Stefan Tauner 05 Sep '11

05 Sep '11

On Thu, 1 Sep 2011 15:28:42 +0200 "Frei, Thomas (GE Germany)" <Thomas.Frei(a)ge.com> wrote: > Hi, > > I tried to clean the build environment (make clean), and reloaded the sources. > > With this clean base I started step by step to patch: > > Make -> PASS > Patch < 0001....patch -> PASS > Make -> PASS > Patch < 0002....patch -> ERROR!!! > > --- snip --- > (Stripping trailing CRs from patch) > patching file cli_classic.c > Hunk #1 FAILED at 226. > Hunk #2 FAILED at 318. > 2 out of 2 hunks FAILED -- saving rejects to cli_classic.c.rej > (Stripping trailing CRs from patch) > patching file flash.h > Hunk #1 FAILED at 255. > 1 out of 1 hunk FAILED -- saving rejects to flash.h.rej > (Stripping trailing CRs from patch) > patching file layout.c > --- snip --- > > Am I doinf wrong, or what else can be? > you are using the wrong revision of source code (probably the most current one?) imo. the patches encode differences of files. when the files change too much 'patch' is not able to find the right spots to insert the hunks of code in the patches... i am not using svn but i think the right command to fetch the correct version of source for those patches is: svn update -r 1421 i am not sure if that eliminates all of your local changes though. please check with svn st and revert them with svn revert or something similar before you try. of course i could be wrong too. if the above does not work please post the commands used and complete outputs. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

Re: [flashrom] [PATCH] spi25: get rid of unneccessary line breaks (on failed probes)
by Uwe Hermann 04 Sep '11

04 Sep '11

On Mon, Aug 22, 2011 at 01:07:50PM +0200, Stefan Tauner wrote: > --- > not sure if this is correct for all execution paths, but it fixes the > output of a probe on my thinkpad. i have looked a bit around to find > examples of code that this patch would break and found none though. > > without this patch: > Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3017 > Probing for SST SST25LF040A, 512 kB: Invalid OPCODE 0xab, will not execute. > > Probing for SST SST25LF080A, 1024 kB: Invalid OPCODE 0xab, will not execute. > > Probing for SST SST25VF010.REMS, 128 kB: Invalid OPCODE 0x90, will not execute. > > Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3017 > > with this patch: > Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3017 > Probing for SST SST25LF040A, 512 kB: Invalid OPCODE 0xab, will not execute. > Probing for SST SST25LF080A, 1024 kB: Invalid OPCODE 0xab, will not execute. > Probing for SST SST25VF010.REMS, 128 kB: Invalid OPCODE 0x90, will not execute. > Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x3017 > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Untested, but I can't see any obvious problems either. Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

2 1

Re: [flashrom] [PATCH 1/8] ichspi: add ICH/PCH flash descriptor decoding via FDOC/FDOD
by Carl-Daniel Hailfinger 04 Sep '11

04 Sep '11

Am 20.08.2011 12:39 schrieb Stefan Tauner: > based on the work of Matthias 'mazzoo' Wenzel this patch adds pretty > printing of those ICH/PCH flash descriptor sections that are > cached/mapped by the chipset (and which are therefore reachable via > FDOC/FDOD registers). > > this includes the following: > - content section: > describes the image and some generic properties (number of > sections, offset of sections, PCH/ICH and MCH/PROC strap > offsets and lengths) > - component section: > identify the different SPI flash chips and their capabilities. > - region section > similarly to a partition table this describes the different regions. > the content of FLREG* is derived from this section. > - master section > defines SPI master (host, ME, GbE) access rights of the > individual regions. the content of PR* is derived from this section. > > this is only a part of the data included in the descriptor. other > information can be retrieved from a complete binary dump of the > descriptor region only. > > this patch also adds macros and pretty printing for "Vendor Specific > Component Capabilities" registers: there are two of them: lower and > upper. they describe the properties of the address space divided by > FPBA (which allows to use multiple flash chips or partitions with > different properties). the properties of all supported flash chips > (together with their RDIDs) are stored in the same format in table > in a descriptor section (which is used by the ME apparently). a > later patch will use the macros outside of ichspi.c which is the > reason why the prettyprinting function and the register bit macros > are not defined in ichspi.c but ich_descriptors.h (else they would > be moved in the follow-up patch). > > because this patch relies on (compiler) implementation-specific > layouting of bit-fields, it checks for basic compiler support in the > makefile and for correct layout before taking any action on runtime. > Checking for presence of bitfield support in the compiler is the way to madness. Next we have to test for C99 capability and other fun stuff. Just assume that bitfields are supported, otherwise compilation will blow up or the runtime checks will catch a miscompilation. That compile-time check (including the #if BITFIELDS) is nacked. > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > Makefile | 25 +++++- > ich_descriptors.c | 288 +++++++++++++++++++++++++++++++++++++++++++++++++++++ > ich_descriptors.h | 261 ++++++++++++++++++++++++++++++++++++++++++++++++ > ichspi.c | 60 +++++++++-- > 4 files changed, 622 insertions(+), 12 deletions(-) > create mode 100644 ich_descriptors.c > create mode 100644 ich_descriptors.h > > diff --git a/Makefile b/Makefile > index 26f978f..247a60c 100644 > --- a/Makefile > +++ b/Makefile > @@ -340,9 +340,11 @@ endif > > ifeq ($(CONFIG_INTERNAL), yes) > FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' > +FEATURE_CFLAGS += $(shell LC_ALL=C grep -q "BITFIELDS := yes" .features && printf "%s" "-D'BITFIELDS=1'") > PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o > ifeq ($(ARCH),"x86") > -PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o > +PROGRAMMER_OBJS += it87spi.o it85spi.o sb600spi.o wbsio_spi.o mcp6x_spi.o > +PROGRAMMER_OBJS += ichspi.o ich_descriptors.o > else > endif > NEED_PCI := yes > @@ -635,6 +637,19 @@ int main(int argc, char **argv) > endef > export UTSNAME_TEST > > +define BITFIELDS_TEST > +#include "ich_descriptors.h" > +int main(int argc, char **argv) > +{ > + struct ich_descriptors desc; > + (void) argc; > + (void) argv; > + desc.region.FLREGs[4] = 0x5aa5a55a; > + return desc.region.reg4_base; > +} > +endef > +export BITFIELDS_TEST > + > features: compiler > @echo "FEATURES := yes" > .features.tmp > ifeq ($(CONFIG_FT2232_SPI), yes) > @@ -649,6 +664,14 @@ endif > @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) >/dev/null 2>&1 && \ > ( echo "found."; echo "UTSNAME := yes" >> .features.tmp ) || \ > ( echo "not found."; echo "UTSNAME := no" >> .features.tmp ) > +# ugly hack to get a logical AND *sigh* > +ifeq ($(CONFIG_INTERNAL)$(ARCH), yes"x86") > + @printf "Checking if bit-fields support is sufficient... " > + @echo "$$BITFIELDS_TEST" > .featuretest.c > + @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) -D BITFIELDS .featuretest.c -o .featuretest$(EXEC_SUFFIX) >/dev/null 2>&1 && \ > + ( echo "yes."; echo "BITFIELDS := yes" >> .features.tmp ) || \ > + ( echo "no."; echo "BITFIELDS := no" >> .features.tmp ) > +endif > @$(DIFF) -q .features.tmp .features >/dev/null 2>&1 && rm .features.tmp || mv .features.tmp .features > @rm -f .featuretest.c .featuretest$(EXEC_SUFFIX) > > That Makefile change needs to be dropped except for the PROGRAMMER_OBJS addition. > diff --git a/ich_descriptors.c b/ich_descriptors.c > new file mode 100644 > index 0000000..ce40d9f > --- /dev/null > +++ b/ich_descriptors.c > @@ -0,0 +1,288 @@ > [...] > +int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc) > +{ > + uint8_t i; > + uint8_t nr; > + struct ich_desc_region *r = &desc->region; > + > The snippet below needs to be in its own function named selfcheck_bitfields(), and that function should live in flashrom.c (or any other reasonably central place) and be called in the initial selfcheck() function. We want to know where this explodes, even if the functionality would not be necessary. > + /* Test if bit-fields are working as expected */ > + for (i = 0; i < 4; i++) > + desc->region.FLREGs[i] = 0x5A << (i * 8); > + if (r->reg0_base != 0x005A || r->reg0_limit != 0x0000 || > + r->reg1_base != 0x1A00 || r->reg1_limit != 0x0000 || > + r->reg2_base != 0x0000 || r->reg2_limit != 0x005A || > + r->reg3_base != 0x0000 || r->reg3_limit != 0x1A00) { > + msg_pdbg("The combination of compiler and CPU architecture used" > + "does not lay out bit-fields as expected, sorry.\n"); > + msg_pspew("r->reg0_base = 0x%04X (0x005A)\n", r->reg0_base); > + msg_pspew("r->reg0_limit = 0x%04X (0x0000)\n", r->reg0_limit); > + msg_pspew("r->reg1_base = 0x%04X (0x1A00)\n", r->reg1_base); > + msg_pspew("r->reg1_limit = 0x%04X (0x0000)\n", r->reg1_limit); > + msg_pspew("r->reg2_base = 0x%04X (0x0000)\n", r->reg2_base); > + msg_pspew("r->reg2_limit = 0x%04X (0x005A)\n", r->reg2_limit); > + msg_pspew("r->reg3_base = 0x%04X (0x0000)\n", r->reg3_base); > + msg_pspew("r->reg3_limit = 0x%04X (0x1A00)\n", r->reg3_limit); > + return RET_ERR; > + } > Snippet ends here. If you want, I can send my own bitfield checker code to the list so you can compare both implementations. > diff --git a/ich_descriptors.h b/ich_descriptors.h > new file mode 100644 > index 0000000..b1da914 > --- /dev/null > +++ b/ich_descriptors.h > @@ -0,0 +1,261 @@ > +/* > + * This file is part of the flashrom project. > + * > + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> > + * Copyright (c) 2011 Stefan Tauner > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + */ > + > +#if defined(__i386__) || defined(__x86_64__) > +#ifndef __ICH_DESCRIPTORS_H__ > +#define __ICH_DESCRIPTORS_H__ 1 > + > +#include <stdint.h> > + > +#define RET_OK 0 > +#define RET_ERR -1 > +#define RET_WARN -2 > +#define RET_PARAM -3 > +#define RET_OOB -4 > Too generic names. > + > +#define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */ > + /* 0-1: reserved */ > +#define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */ > +#define FDOC_FDSI (0x3f << FDOC_FDSI_OFF) > +#define FDOC_FDSS_OFF 12 /* 12-14: Flash Descriptor Section Select */ > +#define FDOC_FDSS (0x3 << FDOC_FDSS_OFF) > + /* 15-31: reserved */ > + > +#define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */ > + > +/* Field locations and semantics for LVSCC, UVSCC and related words in the flash > + * descriptor are equal therefore they all share the same macros below. */ > +#define VSCC_BES_OFF 0 /* 0-1: Block/Sector Erase Size */ > +#define VSCC_BES (0x3 << VSCC_BES_OFF) > +#define VSCC_WG_OFF 2 /* 2: Write Granularity */ > +#define VSCC_WG (0x1 << VSCC_WG_OFF) > +#define VSCC_WSR_OFF 3 /* 3: Write Status Required */ > +#define VSCC_WSR (0x1 << VSCC_WSR_OFF) > +#define VSCC_WEWS_OFF 4 /* 4: Write Enable on Write Status */ > +#define VSCC_WEWS (0x1 << VSCC_WEWS_OFF) > + /* 5-7: reserved */ > +#define VSCC_EO_OFF 8 /* 8-15: Erase Opcode */ > +#define VSCC_EO (0xff << VSCC_EO_OFF) > + /* 16-22: reserved */ > +#define VSCC_VCL_OFF 23 /* 23: Vendor Component Lock */ > +#define VSCC_VCL (0x1 << VSCC_VCL_OFF) > + /* 24-31: reserved */ > + > +#define ICH_FREG_BASE(flreg) (((flreg) << 12) & 0x01fff000) > +#define ICH_FREG_LIMIT(flreg) (((flreg) >> 4) & 0x01fff000) > + > +/* Used to select the right descriptor printing function. > + * Currently only ICH8 and Ibex Peak are supported. > + */ > +enum ich_chipset { > + CHIPSET_ICH_UNKNOWN, > + CHIPSET_ICH7 = 7, > + CHIPSET_ICH8, > + CHIPSET_ICH9, > + CHIPSET_ICH10, > + CHIPSET_5_SERIES_IBEX_PEAK, > + CHIPSET_6_SERIES_COUGAR_POINT, > + CHIPSET_7_SERIES_PANTHER_POINT > +}; > + > +void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity); > + > +#if BITFIELDS == 1 > +struct ich_desc_content { > + uint32_t FLVALSIG; /* 0x00 */ > + union { /* 0x04 */ > + uint32_t FLMAP0; > + struct { > + uint32_t FCBA :8, /* Flash Component Base Address */ > + NC :2, /* Number Of Components */ > + :6, > + FRBA :8, /* Flash Region Base Address */ > + NR :3, /* Number Of Regions */ > + :5; > + }; > + }; > + union { /* 0x08 */ > + uint32_t FLMAP1; > + struct { > + uint32_t FMBA :8, /* Flash Master Base Address */ > + NM :3, /* Number Of Masters */ > + :5, > + FISBA :8, /* Flash ICH Strap Base Address */ > + ISL :8; /* ICH Strap Length */ > + }; > + }; > + union { /* 0x0c */ > + uint32_t FLMAP2; > + struct { > + uint32_t FMSBA :8, /* Flash (G)MCH Strap Base Addr. */ > + MSL :8, /* MCH Strap Length */ > + :16; > + }; > + }; > +}; > + > +struct ich_desc_component { > + union { /* 0x00 */ > + uint32_t FLCOMP; /* Flash Components Register */ > + struct { > + uint32_t comp1_density :3, > + comp2_density :3, > + :11, > + freq_read :3, > + fastread :1, > + freq_fastread :3, > + freq_write :3, > + freq_read_id :3, > + :2; > + }; > + }; > + union { /* 0x04 */ > + uint32_t FLILL; /* Flash Invalid Instructions Register */ > + struct { > + uint32_t invalid_instr0 :8, > + invalid_instr1 :8, > + invalid_instr2 :8, > + invalid_instr3 :8; > + }; > + }; > + union { /* 0x08 */ > + uint32_t FLPB; /* Flash Partition Boundary Register */ > + struct { > + uint32_t FPBA :13, /* Flash Partition Boundary Addr */ > + :19; > + }; > + }; > +}; > + > +struct ich_desc_region { > + union { > + uint32_t FLREGs[5]; > + struct { > + struct { /* FLREG0 Flash Descriptor */ > + uint32_t reg0_base :13, > + :3, > + reg0_limit :13, > + :3; > + }; > + struct { /* FLREG1 BIOS */ > + uint32_t reg1_base :13, > + :3, > + reg1_limit :13, > + :3; > + }; > + struct { /* FLREG2 ME */ > + uint32_t reg2_base :13, > + :3, > + reg2_limit :13, > + :3; > + }; > + struct { /* FLREG3 GbE */ > + uint32_t reg3_base :13, > + :3, > + reg3_limit :13, > + :3; > + }; > + struct { /* FLREG4 Platform */ > + uint32_t reg4_base :13, > + :3, > + reg4_limit :13, > + :3; > + }; > + }; > + }; > +}; > + > +struct ich_desc_master { > + union { > + uint32_t FLMSTR1; > + struct { > + uint32_t BIOS_req_ID :16, > + BIOS_descr_r :1, > + BIOS_BIOS_r :1, > + BIOS_ME_r :1, > + BIOS_GbE_r :1, > + BIOS_plat_r :1, > + :3, > + BIOS_descr_w :1, > + BIOS_BIOS_w :1, > + BIOS_ME_w :1, > + BIOS_GbE_w :1, > + BIOS_plat_w :1, > + :3; > + }; > + }; > + union { > + uint32_t FLMSTR2; > + struct { > + uint32_t ME_req_ID :16, > + ME_descr_r :1, > + ME_BIOS_r :1, > + ME_ME_r :1, > + ME_GbE_r :1, > + ME_plat_r :1, > + :3, > + ME_descr_w :1, > + ME_BIOS_w :1, > + ME_ME_w :1, > + ME_GbE_w :1, > + ME_plat_w :1, > + :3; > + }; > + }; > + union { > + uint32_t FLMSTR3; > + struct { > + uint32_t GbE_req_ID :16, > + GbE_descr_r :1, > + GbE_BIOS_r :1, > + GbE_ME_r :1, > + GbE_GbE_r :1, > + GbE_plat_r :1, > + :3, > + GbE_descr_w :1, > + GbE_BIOS_w :1, > + GbE_ME_w :1, > + GbE_GbE_w :1, > + GbE_plat_w :1, > + :3; > + }; > + }; > +}; > + > +struct ich_descriptors { > + struct ich_desc_content content; > + struct ich_desc_component component; > + struct ich_desc_region region; > + struct ich_desc_master master; > +}; > + > +void prettyprint_ich_descriptors(enum ich_chipset, const struct ich_descriptors *desc); > + > +void prettyprint_ich_descriptor_content(const struct ich_desc_content *content); > +void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc); > +void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc); > +void prettyprint_ich_descriptor_master(const struct ich_desc_master *master); > + > +int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc); > + > +#endif /* BITFIELDS == 1 */ > +#endif /* __ICH_DESCRIPTORS_H__ */ > +#endif /* defined(__i386__) || defined(__x86_64__) */ > diff --git a/ichspi.c b/ichspi.c > index 8b4210e..09af2b3 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -1190,6 +1197,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > uint8_t old, new; > uint16_t spibar_offset, tmp2; > uint32_t tmp; > + int ichspi_desc = 0; > > switch (ich_generation) { > case 7: > @@ -1261,6 +1269,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); > ichspi_lock = 1; > } > + if (tmp2 & HSFS_FDV) > + ichspi_desc = 1; > How does FDOVR (or whatever the correct acronym for Flash Descriptor Override is) relate to this? > > tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); > msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); > @@ -1308,12 +1318,40 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > mmio_readl(ich_spibar + ICH9_REG_OPMENU)); > msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", > mmio_readl(ich_spibar + ICH9_REG_OPMENU + 4)); > - ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); > - msg_pdbg("0xA0: 0x%08x (BBAR)\n", > - ichspi_bbar); > - tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); > - msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); > + if (ich_generation == 8) { > + tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC); > + msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp); > + msg_pdbg("VSCC: "); > + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); > + } else { > + ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); > + msg_pdbg("0xA0: 0x%08x (BBAR)\n", > + ichspi_bbar); > + > + tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); > + msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); > + msg_pdbg("LVSCC: "); > + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); > + > + tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); > + msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); > + msg_pdbg("UVSCC: "); > + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); > + > + tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); > + msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); > + } > > + msg_pdbg("\n"); > +#if BITFIELDS == 1 > + if (ichspi_desc) { > + struct ich_descriptors desc = {{ 0 }}; > + if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == > + RET_OK) > + prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, > + &desc); > + } > +#endif /* BITFIELDS == 1 */ > ich_init_opcodes(); > break; > default: > Regards, Carl-Daniel -- http://www.hailfinger.org/

2 5

[PATCH] Kill exit() calls in cli_classic
by Tadas Slotkus 03 Sep '11

03 Sep '11

exit() calls are very bad. GUI's and payload don't like it, so remove it for easier flashrom usage across projects. P.S. currently return values are the same as vere to exit calls, so if you have a clue what these should be please tell it now. Signed-off-by: Tadas Slotkus <devtadas(a)gmail.com> --- cli_classic.c | 55 ++++++++++++++++++++++++++----------------------------- 1 files changed, 26 insertions(+), 29 deletions(-) diff --git a/cli_classic.c b/cli_classic.c index c6fb379..43b435f 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -93,7 +93,6 @@ static void cli_classic_usage(const char *name) static void cli_classic_abort_usage(void) { printf("Please run \"flashrom --help\" for usage info.\n"); - exit(1); } int main(int argc, char *argv[]) @@ -142,7 +141,7 @@ int main(int argc, char *argv[]) print_banner(); if (selfcheck()) - exit(1); + return 1; setbuf(stdout, NULL); /* FIXME: Delay all operation_specified checks until after command @@ -155,7 +154,7 @@ int main(int argc, char *argv[]) if (++operation_specified > 1) { fprintf(stderr, "More than one operation " "specified. Aborting.\n"); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; } filename = strdup(optarg); read_it = 1; @@ -164,7 +163,7 @@ int main(int argc, char *argv[]) if (++operation_specified > 1) { fprintf(stderr, "More than one operation " "specified. Aborting.\n"); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; } filename = strdup(optarg); write_it = 1; @@ -174,12 +173,12 @@ int main(int argc, char *argv[]) if (++operation_specified > 1) { fprintf(stderr, "More than one operation " "specified. Aborting.\n"); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; } if (dont_verify_it) { fprintf(stderr, "--verify and --noverify are" "mutually exclusive. Aborting.\n"); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; } filename = strdup(optarg); verify_it = 1; @@ -188,7 +187,7 @@ int main(int argc, char *argv[]) if (verify_it) { fprintf(stderr, "--verify and --noverify are" "mutually exclusive. Aborting.\n"); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; } dont_verify_it = 1; break; @@ -202,7 +201,7 @@ int main(int argc, char *argv[]) if (++operation_specified > 1) { fprintf(stderr, "More than one operation " "specified. Aborting.\n"); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; } erase_it = 1; break; @@ -214,7 +213,7 @@ int main(int argc, char *argv[]) fprintf(stderr, "Error: Internal programmer support " "was not compiled in and --mainboard only\n" "applies to the internal programmer. Aborting.\n"); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; #endif break; case 'f': @@ -222,8 +221,9 @@ int main(int argc, char *argv[]) break; case 'l': tempstr = strdup(optarg); - if (read_romlayout(tempstr)) - cli_classic_abort_usage(); + if (read_romlayout(tempstr)) { + cli_classic_abort_usage(); return 1; + } break; case 'i': /* FIXME: -l has to be specified before -i. */ @@ -232,14 +232,14 @@ int main(int argc, char *argv[]) fprintf(stderr, "Error: image %s not found in " "layout file or -i specified before " "-l\n", tempstr); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; } break; case 'L': if (++operation_specified > 1) { fprintf(stderr, "More than one operation " "specified. Aborting.\n"); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; } list_supported = 1; break; @@ -248,13 +248,13 @@ int main(int argc, char *argv[]) if (++operation_specified > 1) { fprintf(stderr, "More than one operation " "specified. Aborting.\n"); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; } list_supported_wiki = 1; #else fprintf(stderr, "Error: Wiki output was not compiled " "in. Aborting.\n"); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; #endif break; case 'p': @@ -286,7 +286,7 @@ int main(int argc, char *argv[]) if (programmer == PROGRAMMER_INVALID) { fprintf(stderr, "Error: Unknown programmer " "%s.\n", optarg); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; } break; case 'R': @@ -294,41 +294,38 @@ int main(int argc, char *argv[]) if (++operation_specified > 1) { fprintf(stderr, "More than one operation " "specified. Aborting.\n"); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; } - exit(0); - break; + return 0; case 'h': if (++operation_specified > 1) { fprintf(stderr, "More than one operation " "specified. Aborting.\n"); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; } cli_classic_usage(argv[0]); - exit(0); - break; + return 0; default: - cli_classic_abort_usage(); - break; + cli_classic_abort_usage(); return 1; } } if (optind < argc) { fprintf(stderr, "Error: Extra parameter found.\n"); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; } /* FIXME: Print the actions flashrom will take. */ if (list_supported) { print_supported(); - exit(0); + return 0; } #if CONFIG_PRINT_WIKI == 1 if (list_supported_wiki) { print_supported_wiki(); - exit(0); + return 0; } #endif @@ -336,7 +333,7 @@ int main(int argc, char *argv[]) if ((programmer != PROGRAMMER_INTERNAL) && (lb_part || lb_vendor)) { fprintf(stderr, "Error: --mainboard requires the internal " "programmer. Aborting.\n"); - cli_classic_abort_usage(); + cli_classic_abort_usage(); return 1; } #endif @@ -349,7 +346,7 @@ int main(int argc, char *argv[]) chip_to_probe); printf("Run flashrom -L to view the hardware supported " "in this flashrom version.\n"); - exit(1); + return 1; } /* Clean up after the check. */ flash = NULL; -- 1.7.6

2 2

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

flashrom