- flashrom - mail.coreboot.org

Unable to read “Boyamicro” SPI chip.
by Frankie LEE (HTX) 22 Apr '22

22 Apr '22

Hi, Unable to read “Boyamicro” SPI chip? Any workaround? Thanks. ============================================================================================== ack@ack:~$ flashrom -p ft2232_spi:type=2232H,port=B,divisor=4 -r firmware.bin flashrom v1.2 on Linux 5.13.0-40-generic (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Found Generic flash chip "unknown SPI chip (RDID)" (0 kB, SPI) on ft2232_spi. === This flash part has status NOT WORKING for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org<mailto:flashrom@flashrom.org> if any of the above operations work correctly for you with this flash chip. Please include the flashrom log file for all operations you tested (see the man page for details), and mention which mainboard or programmer you tested in the subject line. Thanks for your help! Read is not working on this chip. Aborting.

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flashrom dev meeting notes 21.04.22
by Felix Singer 21 Apr '22

21 Apr '22

# 21th April 2022, 6:00 - 7:00 am UTC+0 Attendees: Thomas, David, Edward, Nico, Anastasia, Nikolai ## Decisions Summary * Anastasia will be doing next release. She has never done release before, and needs help from more experienced people. ## Agenda * [FelixS] Redmine is ready to use * If you wonder, new registrations require an unlock by an administrator. This is to prevent spamming and bots. Maybe we can work out something better in the future. * I added additional fields to issues, so that important information is easily visible. For example affected hardware, affected OS, affected version. Please tell me if you find these useful or if you need other fields, trackers, .. * aklm: let’s start using, I will try to create an account and see how it goes * [FelixS] Created a proposal for closing GitHub issues and pull requests automatically * Closes newly created issues and pull requests and adds a comment using GitHub Actions hook. Old issues and pull requests stay untouched. * [flashrom patch](https://review.coreboot.org/c/flashrom/+/63671), based on GitHub Actions hook and [repo- lockdown](https://github.com/dessant/repo-lockdown). * My playground [https://github.com/felixsinger/awesome-repo](https://github.com/felixsinger… * [Nico] ChromeOS fork and attempted convergence * (in case witnesses of that time are present) What led to the fork? * [PatrickG] Velocity requirements: stuff needed to happen to make progress on the products using flashrom and it didn’t happen in time. Not much of a problem when it’s temporary but stuff just piled up over time. * Nico: lots of things went wrong. And it took around 8 months to converge * David: Fork happened when Carl-Daniel was the maintainer, and he was really busy. Tools were worse that time. * We had irreconcilable differences at that time * Edward: Stefan asked me to unfork flashrom. I had to work out how things were done, how to re-write parts of the system. It was just me, on my own, no other resources. I took upstream and tried to make chrome os work with upstream. Except for a few patches: mapping hack inside of sb600spi, I am trying to chase AMD to get documentation , so that I can improve it. * David: Timer stuff I was trying to deal locally. There were a bunch of things that had to be dealt locally. * David: It was uglier downstream than it should have been. Trying to minimize the number of hacks. There are things that can be tr * Edward: Where we are today: I was trying to have a team for flashrom, to spend dedicated time to work on flashrom. We had good results on that, but it takes time. Hard to allocate people. * (in case somebody knows) What is Google’s current strategy to avoid repeating mistakes of the past? * [PatrickG] Generally CrOS is willing to go upstream-first (as with coreboot) after divergence has been resolved. Depends on the upstream, so probably need to work on the questions raised by Edward et al. * [Nico] Upstream-first of a dominant vendor made it harder for others to work upstream on coreboot. It’s not what I had in mind, but this would be repeating a mistake, IMHO. * Nico: There were very good and very bad contributions during last years * Edward: how do you quantify that nothing is happening? * Nico : sb600 is bricking machines , but nothing is happening * Edward: maybe it is a visibility problem, also some things are really hard * Nico: maybe devs in google need to talk to each other? * Edward: original patch came from AMD, not from google * Nico: if it takes a long time to find a solution, maybe just revert? * Edward: we didn’t know it would take so long * David: board bringup. There is 3-4 months time before chromebooks get into users hands, and then bugs get filed. Bugs in the code which is 6 months old, but people are already reassigned to other tasks. * Edward: maybe have a parameter which turns on the behaviour, default is turned off. The problem exists, but it is not trivial. * Nico: The problem with the “upstream-first” idea: when something is not trivial, you push it upstream first, and then try to figure out how to fix it. * Edward: that was exceptional situation, it is better now * Nico: most of the issues in the list are from google. When someone looks at the code, it is clear that code it is not understood. * Edward: we opened issues about non-documented programmer, and added documentation * Nico: one of the drivers is mixing all layers of flashrom. * Nikolai: what are concerns with the code? We will try to remove them. * Edward: The datasheet was in mandarin, and lots of questions were discussed in mandarin with the vendor. Vendors were not giving documentation, despite us asking them many times. * Nico: Who is doing reviews for google? We need reviewers who know all layers of flashrom. * David: Can we simplify the process of adding a new chipset? So that it would be easier to contribute without introducing bugs? * Thomas: It would be nice to have more structure in the code repository. It is hard to understand where the code needs to go. Having a specific place for every component is a good idea * David : flash.h and flashrom.c are dumping grounds * Anastasia: Nico do you think it is possible so that we all work together normally and peacefully? If we resolve issues from the past, and also write guidelines so that new issues won’t appear and development goes normally? >> Yes it is possible. * Let's make a release! * Nico: I spent a lot of time on this already, I can’t spend even more time. Anyone else? * Nikolai: What if the vendor does not give documentation, do you think it’s better to have a driver which is not documented, or no driver at all? * David: for early chromebooks , drivers were not documented. That’s why an option was called “I want brick” * Edward: some of the changes in the chromium tree we are not sending upstream, because there is no documentation * Nikolai: Can we have a flag for situations like sb600spi ? Finer granularity than the whole driver. Feature flags? * Nico: other people work on the sb600spi code, affects everyone who works on the code. * Edward: something similar in kernel hardware quark framework. * Nico: this needs documentation, whatever is needed to understand the quark. Man pages are for the users, but there also should be documentation for developers. In what product is this chip? You can document what you know * [dhendrix] Is this the kind of finger pointing that Edward mentioned above? At this point, CrOS has proved more than happy to move upstream. The Github mirror is probably more of a concern. Perhaps upstream should consider how to get developers to choose upstream rather than the Github mirror or some other fork. * [Nico] Pointing at Google, actually. If one company forks and later wants their code upstream without proper review, something seems wrong. As if they never reflected on the problems. * [aklm] I am not sure we are on the same page on what are “mistakes of the past”. Everyone has their own idea on what the mistakes were. I can start from myself. From my observations, converging the code was considered a purely technical task, and so it was done as a technical task. However, converging the code means converging the people/the teams, converging very different workflows and work cultures. This does not seem to be thought through or ever discussed, and to me this is a mistake. * [quasisec] I am also unclear how CrOS convergence had really much of an impact on upstream considering >99% of the work was adjusting the CrOS fork to realign with upstream. Only an extremely small amount of alignment was in the form of upstream commits, e.g., missing raiden_debug and some unfortunate part of sb600spi. Is there a specific area that stands out? * [Nico] No idea if related to the original reasons for the fork, but that the convergence is stalling new releases for years stands out pretty much. * Anastasia: We currently have more GSOC project proposals than mentors (5 vs 3). If someone wants to be a mentor, it is not too late. Contact Anastasia or Felix.

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[GSoC 2022] Restructure Shutdown Function
by Joursoir 14 Apr '22

14 Apr '22

Good day, I am a student and very interested in flashrom. I fit the description of experienced C programmer. Open-source and low-level programming are my interests. I already have real experience with flashrom (CH341A programmer + chip "MX25L6436E") and want to become a GSoC 2022 contributor in this project. I find the "Restructure Shutdown Function" project interestring to me. But right now it has no mentors. Maybe someone from the mailing can help me. I have gone through sources and understand how things are now. The project description says "have a defined shutdown function in the programmer API". But we already have it. It's programmer_shutdown(). Or no? The first and easiest thing that comes to my mind is to refuse using callbacks and use enums, thusly: enum shutdown_func { SERPROG = 1 << 0, SPI = 1 << 1, ... }; int programmer_shutdown(enum shutdown_func execfunc) { ... if(execfunc & SERPROG) ret |= serprog_shutdown(...); if(execfunc & SPI) { /* the problem is that SPI programmers have own shutdown funcs, like dlc5_shutdown, byteblaster_shutdown, stlinkv3_spi_shutdown, so use struct spi_master, that contains shutdown callback */ ret |= spi_master_shutdown(...); } ... } This system has disadvantages, but it'll make easier to track the code flow. What are the potential problems in this implementation? What's with struct flashrom_programmer? Is not implemented yet? I would appreciate any feedback. -- Joursoir

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Future of DirectHW
by Thomas Heijligen 12 Apr '22

12 Apr '22

Hi, is there someone in the flashrom community who has worked with DirectHW and knows if it's still working on supported MacOS systems? I want to figure out how to deal with it in the future of flashrom. -- Thomas

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Couldn't parse the descriptor?
by Pete Smith 12 Apr '22

12 Apr '22

I'm using a Raspberry Pi Zero and SOIC clip to communicate with a MX25L12873F chip, using flashrom built from master branch (1b1066e). Reading the chip is working fine, no matter how many times I do a read operation, the resulting firmware image is correct. However, I'm unable to write to the chip: ======================================================================== flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=1000 -c \ MX25L12833F/MX25L12835F/MX25L12845E/MX25L12865E/MX25L12873F \ -w firmware.bin --ifd -i fd -i bios -i me --noverify-all -VVV -o out.log Initializing linux_spi programmer Using device /dev/spidev0.0 Using 1000kHz clock get_max_kernel_buf_size: Using value from \ /sys/module/spidev/parameters/bufsiz as max buffer size. linux_spi_init: max_kernel_buf_size: 4096 The following protocols are supported: SPI. Probing for Macronix \ MX25L12833F/MX25L12835F/MX25L12845E/MX25L12865E/MX25L12873F, \ 16384 kB: programmer_map_flash_region: mapping \ MX25L12833F/MX25L12835F/MX25L12845E/MX25L12865E/MX25L12873F from \ 0xff000000 to 0x00000000 RDID returned 0xc2 0x20 0x18. compare_id: id1 0xc2, id2 0x2018 Added layout entry 00000000 - 00ffffff named complete flash Found Macronix flash chip \ "MX25L12833F/MX25L12835F/MX25L12845E/MX25L12865E/MX25L12873F" \ (16384 kB, SPI) on linux_spi. Chip status register is 0x7c. Chip status register: Status Register Write Disable (SRWD, SRP, ...) \ is not set Chip status register: Bit 6 is set Chip status register: Block Protect 3 (BP3) is set Chip status register: Block Protect 2 (BP2) is set Chip status register: Block Protect 1 (BP1) is set Chip status register: Block Protect 0 (BP0) is set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set programmer_unmap_flash_region: unmapped 0x00000000 This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to \ completely clone the contents of this chip (see man page for details). programmer_map_flash_region: mapping \ MX25L12833F/MX25L12835F/MX25L12845E/MX25L12865E/MX25L12873F from \ 0xff000000 to 0x00000000 Some block protection in effect, disabling... \ Block protection could not be disabled! Chip status register is 0x7c. Chip status register: Status Register Write Disable (SRWD, SRP, ...) \ is not set Chip status register: Bit 6 is set Chip status register: Block Protect 3 (BP3) is set Chip status register: Block Protect 2 (BP2) is set Chip status register: Block Protect 1 (BP1) is set Chip status register: Block Protect 0 (BP0) is set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Reading ich descriptor... done. layout_from_ich_descriptors():1367, returned with value -1. Couldn't parse the descriptor! Illegal instruction ======================================================================== On an identical system, I have been using the flashrom internal programmer to write the same firmware image without any errors parsing the descriptor. Any ideas why this happens? I'm a doing something wrong? Thanks. Best regards, Pete Smith

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Invitation: Flashrom Dev Meeting (monthly) @ Every 2 weeks from 8am to 9am on Thursday (CEST) (flashrom@flashrom.org)
by felix.singer12＠gmail.com 12 Apr '22

12 Apr '22

You have been invited to the following event. Title: Flashrom Dev Meeting (monthly) Monthly meeting of Flashrom project developers. Meeting notes doc: https://docs.google.com/document/d/18qKvEbfPszjsJJGJhwi8kRVDUG3GZ… When: Every 2 weeks from 8am to 9am on Thursday Central European Time - Berlin Joining info: Join with Google Meet https://meet.google.com/iuf-mtri-zva?hs=224 Join by phone (AU) +61 2 9051 6791 (PIN: 304642402) More phone numbers: https://tel.meet/iuf-mtri-zva?pin=9271993818880&hs=0 Calendar: flashrom(a)flashrom.org Who: * aklm(a)chromium.org- creator * felix.singer12(a)gmail.com * david.hendricks(a)gmail.com * quasisec(a)google.com * nico.h(a)gmx.de * Martin Roth * src(a)posteo.de * martonmiklosqdev(a)gmail.com * piotr.krol(a)3mdeb.com * Maciej Pijanowski * michal.zygowski(a)3mdeb.com * th3fanbus(a)gmail.com * stefan.k.reinauer(a)gmail.com * nartemiev(a)google.com * arthur(a)aheymans.xyz * flashrom(a)flashrom.org Event details: https://calendar.google.com/calendar/event?action=VIEW&eid=MmVscGY2cjNsdTZw… Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this courtesy email at the account flashrom(a)flashrom.org because you are an attendee of this event. To stop receiving future updates for this event, decline this event. Alternatively, you can sign up for a Google Account at https://calendar.google.com/calendar/ and control your notification settings for your entire calendar. Forwarding this invitation could allow any recipient to send a response to the organiser and be added to the guest list, invite others regardless of their own invitation status or to modify your RSVP. Learn more at https://support.google.com/calendar/answer/37135#forwarding

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Board Testing - ASRock TRX40 Creator
by Dario Dorando 09 Apr '22

09 Apr '22

Hey folks, I've tested compatibility of this tool with my mainboard today. Boardname: ASRock TRX40 Creator Vendor website: http://www.asrock.com/mb/AMD/TRX40%20Creator/#Specification Flash-chip: Winbond 25Q128FWSQ - 16MBSuperI/O: nuvoTon NCT6683D-T For the folks interested - A webpage with amazingly detailed photos of that mainboard, including chips and whatnot: https://news.xfastest.com/review/review-03/72941/asrock-trx40-creator-revie… Note that this page is currently down for me, but you can still access it via the wayback machine. Commands ran: sudo flashrom/flashrom -r biosdump.bin -p internal # Note that TRX4CTR1.70 is the rom file that's freely downloadable from ASRock's website. binwalk -W -i TRX4CTR1.70 biosdump.bin > binwalk_diff.txt # Since I'm not really fond of firmware file layouts yet, somebody who's smarter than me might want to verify whether # the differences are mainly due to different bios configs and hardware I've added into my system,# or if some firmware section got omitted on read. more binwalk_diff.txt | grep 0x0 | wc -l # This command showed '17430'. Since binwalk shows 16 bytes per line, there should be about 34kb of differences in binary. # Flashed back the official rom, since I don't really trust the read one. sudo flashrom/flashrom -p internal -w TRX4CTR1.70 # The output from that is in the attached file. sudo flashrom/flashrom -p internal -V lspci -nnvvxxxsuperiotool -deV Flashing the machine with the stock rom did work as well! - Dario

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EU/AU flashrom dev meeting appointment time change
by Felix Singer 08 Apr '22

08 Apr '22

Hi all, as discussed in the last dev meeting, we can not have one appointment for EU, AU and US people during the time from 1. April until 30. September because of the time change. For this time, we have decided to split the meeting up into one meeting for EU/AU and another one for EU/US and we will alternate between them, so that all groups have a chance to participate. The next meeting will be on 6. April, which will target EU/AU. We created a poll [1] for voting. For EU/AU, we are proposing the following dates (UTC+0): * Monday, Wednesday, Thursday 7:00-8:00 * Monday, Wednesday, Thursday 9:15-10:15 // Felix [1] https://terminplaner4.dfn.de/dBtjEZxKqmcm721C

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flashrom dev meeting notes 7.04.22
by Felix Singer 08 Apr '22

08 Apr '22

# 7th April 2022, 6:00 - 7:00 am UTC+0 Attendees: Martin, Michal, Felix, Anastasia, Nikolai, David, Thomas, Nico, Arthur, Edward ## Decisions Summary * Write a script to email out a summary every weekend. Martin can work on a script. * Gerrit guidelines document. Anastasia will start something. * Start using the redmine bug tracker. There are still issues with it, but we’re going to start using it in its current state and work on it as we go. Felix will work on this. ## Agenda * [FelixS] Hackathons need a reboot. So I’m thinking about doing one. Please share :) * [Poll and some more details](https://terminplaner4.dfn.de/pBooK8FBDlM2zDwa) * Darmstadt, Germany. 10. - 12 June * [Edward] Not every developer has the resources to spend their whole time in IRC and have a spiritual connection with a select few. * How to ensure each code review pass results in a contributor that knows where they stand? - what's next, what's done, when things are going to be merged. * How to avoid walking on eggshells and guessing how to avoid arguments on every contribution but at the same time make tangible progress? * Looks like this topic is closely related to the next one, let's discuss them together? (All notes are done below). * [Edward] How to avoid constant politics in every contribution and instead find a path to allow contributors to not feel ostracized for daring to make a change even when the change may not be useful to others in the immediate sense. * Nikolai: hard to understand whether people are looking at the change, do they have thoughts. Hard to get to know the current status of patch? How to coordinate things? There are many channels? * Nikolai: hard to know whether it is ok. If there is no response, does it mean everything is okay, or no one had a look? * Edward: If people send patches, they need to know what the next step is? * David: gerrit plugin which pings reviewers every 48h ? we need some automation * Edward: observation. Both sides expecting action, or both sides are not sure whose turn? If something is +2 , can it be merged? How to understand that something is ready to merge? * Nikolai: how to ensure there is a consensus? People who are unfamiliar with the process don’t know how to proceed and then give up. * Silicon vendors are unfamiliar with the process. Can they officially support new chips? They attempt to send a patch, and then they are confused on what are next steps. Sometimes good ideas come up in code reviews, and it is not clear who should do that. * David: If adding a new chip requires some refactoring, maybe someone can take that work and do a refactoring? * Edward: We can create a bug in this situation, and prioritize the bug, so that refactor idea is not dropped. * Martin: We need guidelines, maybe “gerrit guidelines”. Coreboot has [https://doc.coreboot.org/contributing/gerrit_guidelines.html](https://doc.c… * Review comments should make clear what is next step * [Edward] How to make the project more accommodating to silicon partners so we can start getting direct support from manufacturers? * Often non-native speakers, * Often not well practiced in free software workflows, * Often need help and guidance to bring them into the fold. * [Edward] How to avoid commits sitting around for years in some weird state between reviewed and unmerged. * Improve project velocity while maintaining stability (improved testing, capture mistakes in tests) * Nico: Can we cherry-pick from coreboot guidelines? Only the bits that apply? * Nico: we can say “write to the mailing list if you don’t know what to do and patch needs attention” * Felix: Can we share the same guidelines as coreboot? We share processes and concepts * Edward: Let's start with our own. Copy-paste and cherry pick model. * Edward: at the end of week an email with the list “everything that has +2”. Martin: We can write it in bash. * [David] We have a GSOC student who wants to do some of the easy projects. Are those projects supposed to be saved for new contributors to have something easy to do? * [Anastasia] The easy projects page needs to be updated, but the projects do need to be done. Since they haven’t been done in 5 years, let’s let the students do them. * [Felix] Employees at companies aren’t interested in doing the easy projects. * [Edward] Let’s adopt the bug tracker and mark bugs as “easy” for people to work on. * [Anastasia] Students should do a single easy project, then move on to a single full project. * [Edward] How to get the mailing list into a usable medium and the code review tools into being for code review only. Move noise to a bug tracker. * Capture ideas in bug tracker. Ideas come up in code reviews, good ideas that need to be done “in a separate patch” and then this is lost. * Felix: some issues left to be configured in the redmine instance. * Nico: we can start using bug tracker with email feature disabled, and then see how it goes. Setup email feature can be the first ticket? * Let’s start using it? * [Edward] How to move to a culture of searched responsibility over constant finger pointing? * Some kind of policy for breakage. * Understanding that software breaks, it is impossible to catch everything in review. * Culture around writing tests and documentation. * Edward: revert policy? Anastasia: There is a thread on mailing list, revert policy is one of the topics

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Join GSoC
by Sayed 08 Apr '22

08 Apr '22

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GSOC 2022
by Wynn K 08 Apr '22

08 Apr '22

Hello, I recently found this project and was wondering if this project was still interested in applicants for the 2022 summer. I was looking into the project ideas and am looking into "Emulate hardware and filesystem in platform-independent way for unit tests" and "Optimize Erase-Function Selection". As many of the projects require programmers, flash chips, and hardware, I was wondering to what extent I would need to have these. I saw the following lists which demonstrate the supported hardware, but I would appreciate it if I could have a more descriptive explanation of what I would need. https://www.flashrom.org/Supported_programmers https://www.flashrom.org/Supported_hardware Additionally, I noticed that some projects want low-level programming, which I would be interested in. However, as I have only a small amount of experience with MIPS, would it not be worthwhile to apply to this position? Thank you for your time

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One Build System Working Group
by Thomas Heijligen 07 Apr '22

07 Apr '22

Hi, As discoursed last dev meeting, we are going to start a working group to adopt meson as single, all cases covering, build system for flashrom. The first step will be to write down all requirements that we need to meet. Therefor, we'll meet today at 8:30 UTC at https://meet.google.com/sag-dyik-bbr and posting the working draft afterwards on the mailing list. The google doc can be visited at any time. https://docs.google.com/document/d/1TVso_VbrLEbGc7BNrYxqlrP8jMxB23TuMqEI3Pn… Please feel free to join the meetings, the next ones will be announced much earlier, add comments to the document or reply to this mail with and question or suggestion. -- Thomas

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ERASE FAILED!
by Pascal Boidart 06 Apr '22

06 Apr '22

Hello Flashrom, I'm on latest Linux Mint. programmer ch341a_spi chip is a Macronix type MX25L6406E I'm trying to erase a chip with: sudo flashrom --programmer ch341a_spi --erase -c "MX25L6406E/MX25L6408E" And I'm getting a erase failed. See log. pascal@pascal-mini:~/Desktop/Flashrom$ sudo flashrom --programmer ch341a_spi --erase -c "MX25L6406E/MX25L6408E" flashrom v1.2 on Linux 5.4.0-107-generic (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Found Macronix flash chip "MX25L6406E/MX25L6408E" (8192 kB, SPI) on ch341a_spi. Erasing and writing flash chip... FAILED at 0x00000000! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x00000fff: 0x1000 ERASE FAILED! Looking for another erase function. FAILED at 0x00000000! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x0000ffff: 0xfad7 ERASE FAILED! Looking for another erase function. FAILED at 0x00000000! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x0000ffff: 0xfad7 ERASE FAILED! Looking for another erase function. FAILED at 0x00000000! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x007fffff: 0x6b7ef1 ERASE FAILED! Looking for another erase function. FAILED at 0x00000000! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x007fffff: 0x6b7ef1 ERASE FAILED! Looking for another erase function. Looking for another erase function. Looking for another erase function. No usable erase functions left. FAILED! Your flash chip is in an unknown state. Please report this on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org, thanks! Any idea? Thanks Pascal

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Google Summer of Code
by Alp 05 Apr '22

05 Apr '22

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Questions regarding Easy projects
by Prakhar Agrawal 04 Apr '22

04 Apr '22

Hello, Hope you are doing well, I am Prakhar Agrawal, currently pursuing Electronics and Communications Engineering from Amrita Vishwa Vidhyapeetham Amritapuri. (2019-2022). For the past 1 year, I have been working with startups to design and develop low latency embedded devices and have also been actively involved in running and managing the bi0s students club(India's best CTF team) While going through different organizations for GSOC 2022, I found Flashrom, and it caught my interest. I was trying to get familiar with the flashrom code-base through easy projects listed here <https://www.flashrom.org/Easy_projects#Fix_issues_found_by_scan-build> I had a few queries in '*Fix issues found by scan-build':-* - In serprog.c, function static int sp_stream_buffer_op( ), if (!sp) { msg_perr("Error: cannot malloc command buffer\n"); return 1; } sp is a pointer, in which a block of memory is being allocated, but in this function, if (!sp) i.e pointer is not null, i.e the memory has been allocated, then why should there be an error message? - While fixing the error generated from the error report, null was being passed to memcpy, here if (sp_stream_buffer_op(S_CMD_O_EXEC, 0, NULL) != 0) to try and fix this issue, I updated the function definition static int sp_stream_buffer_op(uint8_t cmd, uint32_t parmlen, uint8_t *parms){ uint8_t *sp; if (sp_automatic_cmdcheck(cmd)) return 1; sp = malloc(1 + parmlen); if (!sp) { msg_perr("Error: cannot malloc command buffer\n"); return 1; } sp[0] = cmd; /* * Fixed: Added an If block to check the parameter length, * if parameter length is 0 i.e- param is NULL return 1, * else do memcpy */ if(parmlen==0){ //memcpy(&(sp[1]),0, parmlen); msg_perr("Error: Cannot pass Empty parameter\n"); return 1; } else{ memcpy(&(sp[1]),parms, parmlen); } The above changes fixed the error of null value being passed, but now I am getting a memory leak error. Can someone guide me in the right direction on how to fix it? Hoping for a quick and positive response. Warm Regards Prakhar Agrawal Amritapuri <https://www.amrita.edu/campus/amritapuri> LinkedIn <https://www.linkedin.com/in/prakar-agrawal-984555154/>

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Inquiry about your GSOC idea: 'Modernize the flashrom website'
by Mohit Nehra 01 Apr '22

01 Apr '22

Sir/ Ma'am, I hope you are having a wonderful day, The GSOC project idea 'Modernize the flashrom website' was present in the ideas list a week ago but now it is not visible anymore. Please tell if you have intentionally removed it from the ideas list or there is some bug resulting in its removal. Thank you. Mohit Nehra (An aspiring student/ contributor to flashrom GSOC 2022)

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Gsoc 2022 Proposal help
by Shivesh Chaturvedi 31 Mar '22

31 Mar '22

Sir, My name is Shivesh Chaturvedi, I am a second year undergraduate student of the department of Mechanical Engineering enrolled in its btech course at Indian Institute of Technology, Kharagpur, West Bengal India. I am a resident of Lucknow Uttar Pradesh, India. I had worked on the project Idea of Modernising the UI of FlashRom website. I had now gone through the website nearly 2-3 dozen times and I had found some issues which I thought rectifying would help a lot of new people like me. I had worked on basically 5 main points :- 1. Improvement of UI. 2. Having a basic Tutorial on How to use the Website. 3. Some Pages are too long so the idea is to use their pagination view. 4. Having database support for pages like Supported Devices and other pages also will help to improve the website. 5. Having a community chat box feature will help the users very much. Currently I am trying to use Flashrom, but finding it very difficult as there is no proper tutorial available over the internet. I was attempting to contact using Liber Chat, but there was some miscommunication on the website. As a result, I'm sending a draft proposal to this email. Please Kindly take a look over them and do give me pointers that I am going in the right direction or not. Yours Sincerely Shivesh Chaturvedi (+91) 8840884608

1 0

Sharing info about flashrom HW seq code refactoring https://review.coreboot.org/q/topic:PCH_HW_SEQ_Cleanup
by Subrata Banik 31 Mar '22

31 Mar '22

Hello Team, Hope you are doing well. I would like bring this activity in your notice https://review.coreboot.org/q/topic:PCH_HW_SEQ_Cleanup and seek help to review the code. The reason for this refactoring of HW sequencing SPI driver code are: 1. We (Chrome OS team) recently ran into a firmware update issue on dogfooders (test device utilise by real users and share feedback) systems, where the attempt to perform SPI flash update operation from host-cpu (using underlying flashrom utility) is silently failing. Furthermore, we debug the issue with help of Intel and figure out the problem is related to multiple master is accessing the SPI flash and operation triggered by host-cpu side using flashrom (write and erase operation) is getting timed out (due to given lesser timeout boundary) due to underlying SPI bus is occupied by other master. This is the special case, starting from Tiger Lake Chrome Platform, where we have enable the PVAP (Protected Audio Video Path) which request CSE to perform some erase and write operation as needed. Now an attempt to perform firmware update from host-cpu side might coincide with the CSE performing SPI operations. The recommendation that coming out from Intel is to account the multiple master SPI operation while we are issuing the timeout from flashrom side. We are also expecting a doc update from Intel to share the exact timeout calculation (although I have attempted to document that early here https://review.coreboot.org/c/flashrom/+/62867/1/ichspi.c#35). 2. Maintain the code symmetry between coreboot and flashrom SPI hardware sequencing operations. From the testing side, I have tested this code on Alderlake `Brya`, Tigerlake `volteer` and Kabylake `eve` devices, and looking for help from community to check on other systems as well (if possible). Furthermore, I have attempted to increase the timeout which won't impact the flashrom performance on the older and/or existing systems. Looking forward for your help on this request. Thanks, Subrata

3 7

Inquiry about a required task for GSOC.
by Israa Odeh 31 Mar '22

31 Mar '22

Dear Flashrom Org, While I was looking for a GSOC contribution that appeals to my interests and attracts my attention. I noticed your GSOC project ideas for Flashrom, and specifically, the task labeled as "Modernize the flashrom website", which I found quite interesting. Generally, I enjoy web development using CSS, HTML, JavaScript, and PHP, and I'm willing to learn new skills, work with various frameworks, and learn about other helping platforms to enhance my abilities. However, I would like to gain more details about what this project idea requires in minute details so that I could prepare an appropriate proposal and a good plan if it is suitable to me. Please Kindly, provide me with additional information about the requirements. Examples of a bunch of details that I need to know: - Who will be the mentors? (This isn't clarified for each task separately). - What are the expected outcomes you hope to accomplish with this task? - Do you mean specifically that you need to improve the front-end? (Is it specifically a front-end improvement?) - Must the design be responsive? - Are there any predetermined languages or frameworks to use? - Could you clarify what do you mean by saying "However, we have to find out what we need and which framework supports what. Then, various frameworks need to be evaluated and we need a plan on how to migrate to the new site." I'd appreciate hearing the required details from you. Kind Regards Israa Odeh. Sent from Mail<https://go.microsoft.com/fwlink/?LinkId=550986> for Windows

2 1

SPI flashing is the future! :-)
by Stefan Zett 27 Mar '22

27 Mar '22

Hi, i am no developer and spi flashing is very interesting for me. Please can someone write a short explanation about the status registers and block protect? Just for the usual hacker. Thanks Stefan

1 0

Board Asus P7P55D-E Chipset intel P55 reading works
by Stefan Zett 26 Mar '22

26 Mar '22

sudo flashrom -V -p internal -c "MX25L1605" -r 4d.rom flashrom v1.2 on Linux 5.4.0-91-generic (x86_64) flashrom is free software, get the source code at https://flashrom.org flashrom was built with libpci 3.6.4, GCC 9.2.1 20200304, little endian Command line (7 args): flashrom -V -p internal -c MX25L1605 -r 4d.rom Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Initializing internal programmer /sys/class/mtd/mtd0 does not exist No coreboot table found. Using Internal DMI decoder. DMI string chassis-type: "Desktop" DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "P7P55D-E" DMI string baseboard-version: "Rev 1.xx" Found chipset "Intel P55" with PCI ID 8086:3b02. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... Root Complex Register Block address = 0xfed1c000 GCS = 0xc65: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI) Top Swap: not enabled 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x4 0x7fffffff/0x7fffffff FWH IDSEL: 0x5 0x7fffffff/0x7fffffff FWH IDSEL: 0x6 0x7fffffff/0x7fffffff FWH IDSEL: 0x7 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled Maximum FWH chip size: 0x100000 bytes SPI Read Configuration: prefetching enabled, caching enabled, BIOS_CNTL = 0x0b: BIOS Lock Enable: enabled, BIOS Write Enable: enabled Warning: Setting Bios Control at 0xdc from 0x0a to 0x09 failed. New value is 0x0b. SPIBAR = 0x00007fc4c1fbd000 + 0x3800 0x04: 0x6008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=0 Programming OPCODES... done 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x50: 0x0000ffff (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff 0x54: 0x000f0000 FREG0: Flash Descriptor region (0x00000000-0x0000ffff) is read-write. 0x58: 0x01ff0000 FREG1: BIOS region (0x00000000-0x001fffff) is read-write. 0x5C: 0x002f0010 FREG2: Management Engine region (0x00010000-0x0002ffff) is read-write. 0x64: 0x01ff0050 FREG4: Platform Data region (0x00050000-0x001fffff) is read-write. 0x90: 0x04 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xf87f10 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=63, SME=0, SCF=0 0x94: 0x5006 (PREOP) 0x96: 0x463b (OPTYPE) 0x98: 0x05200302 (OPMENU) 0x9c: 0xc79f0190 (OPMENU+4) 0xa0: 0x00000000 (BBAR) 0xc4: 0x00000000 (LVSCC) LVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x0, VCL=0 0xc8: 0x00002001 (UVSCC) UVSCC: BES=0x1, WG=0, WSR=0, WEWS=0, EO=0x20 0xd0: 0x00000000 (FPB) OK. The following protocols are supported: FWH, SPI. Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2015 Found Macronix flash chip "MX25L1605" (2048 kB, SPI) mapped at physical address 0x00000000ffe00000. Chip status register is 0x00. Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 is not set Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Reading flash... done. Restoring MMIO space at 0x7fc4c1fc08a0 Restoring MMIO space at 0x7fc4c1fc0874 Restoring MMIO space at 0x7fc4c1fc089c Restoring MMIO space at 0x7fc4c1fc0898 Restoring MMIO space at 0x7fc4c1fc0896 Restoring MMIO space at 0x7fc4c1fc0894 Restoring PCI config space for 00:1f:0 reg 0xdc

1 0

flashrom and ASUS PRIME_X370-PRO
by Andrew Grzegorek 26 Mar '22

26 Mar '22

sudo flashrom --programmer internal flashrom v1.2 on Linux 5.11.22-100.fc32.x86_64 (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Found chipset "AMD FP4". Enabling flash write... FCH device found but SMBus revision 0x59 does not match known values. Please report this to flashrom(a)flashrom.org and include this log and the output of lspci -nnvx, thanks!. Could not determine chipset generation.PROBLEMS, continuing anyway No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. ----------------------------------------------------- lspci -nnvx 00:00.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Root Complex [1022:1450] Subsystem: ASUSTeK Computer Inc. Device [1043:8747] Flags: fast devsel 00: 22 10 50 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 47 87 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:00.2 IOMMU [0806]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) I/O Memory Management Unit [1022:1451] Subsystem: ASUSTeK Computer Inc. Device [1043:8747] Flags: fast devsel, IRQ 27 Capabilities: <access denied> 00: 22 10 51 14 00 04 10 00 00 00 06 08 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 47 87 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 00:01.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] Flags: fast devsel, IOMMU group 0 00: 22 10 52 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:01.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) PCIe GPP Bridge [1022:1453] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 28, IOMMU group 1 Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: fe900000-fe9fffff [size=1M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 53 14 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 f1 01 00 00 20: 90 fe 90 fe f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 12 00 00:01.3 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) PCIe GPP Bridge [1022:1453] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 29, IOMMU group 2 Bus: primary=00, secondary=02, subordinate=09, sec-latency=0 I/O behind bridge: 0000e000-0000efff [size=4K] Memory behind bridge: fe400000-fe6fffff [size=3M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 53 14 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 02 09 00 e1 e1 00 20 20: 40 fe 60 fe f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 12 00 00:02.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] DeviceName: Onboard IGD Flags: fast devsel, IOMMU group 3 00: 22 10 52 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:03.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] Flags: fast devsel, IOMMU group 4 00: 22 10 52 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:03.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) PCIe GPP Bridge [1022:1453] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 30, IOMMU group 5 Bus: primary=00, secondary=0a, subordinate=0a, sec-latency=0 I/O behind bridge: 0000d000-0000dfff [size=4K] Memory behind bridge: fe800000-fe8fffff [size=1M] Prefetchable memory behind bridge: 00000000e0000000-00000000efffffff [size=256M] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 53 14 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 0a 0a 00 d1 d1 00 20 20: 80 fe 80 fe 01 e0 f1 ef 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 1a 00 00:04.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] Flags: fast devsel, IOMMU group 6 00: 22 10 52 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:07.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] Flags: fast devsel, IOMMU group 7 00: 22 10 52 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:07.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Internal PCIe GPP Bridge 0 to Bus B [1022:1454] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 31, IOMMU group 8 Bus: primary=00, secondary=0b, subordinate=0b, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: fe100000-fe3fffff [size=3M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 54 14 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 0b 0b 00 f1 01 00 00 20: 10 fe 30 fe f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 12 00 00:08.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] Flags: fast devsel, IOMMU group 9 00: 22 10 52 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:08.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Internal PCIe GPP Bridge 0 to Bus B [1022:1454] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 32, IOMMU group 10 Bus: primary=00, secondary=0c, subordinate=0c, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: fe700000-fe7fffff [size=1M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 54 14 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 0c 0c 00 f1 01 00 00 20: 70 fe 70 fe f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 12 00 00:14.0 SMBus [0c05]: Advanced Micro Devices, Inc. [AMD] FCH SMBus Controller [1022:790b] (rev 59) Subsystem: ASUSTeK Computer Inc. Device [1043:8747] Flags: 66MHz, medium devsel, IOMMU group 11 Kernel driver in use: piix4_smbus Kernel modules: i2c_piix4, sp5100_tco 00: 22 10 0b 79 03 04 20 02 59 00 05 0c 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 47 87 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.3 ISA bridge [0601]: Advanced Micro Devices, Inc. [AMD] FCH LPC Bridge [1022:790e] (rev 51) Subsystem: ASUSTeK Computer Inc. Device [1043:8747] Flags: bus master, 66MHz, medium devsel, latency 0, IOMMU group 11 00: 22 10 0e 79 0f 00 20 02 51 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 47 87 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 0 [1022:1460] Flags: fast devsel, IOMMU group 12 00: 22 10 60 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.1 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 1 [1022:1461] Flags: fast devsel, IOMMU group 12 00: 22 10 61 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.2 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 2 [1022:1462] Flags: fast devsel, IOMMU group 12 00: 22 10 62 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.3 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 3 [1022:1463] Flags: fast devsel, IOMMU group 12 Kernel driver in use: k10temp Kernel modules: k10temp 00: 22 10 63 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.4 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 4 [1022:1464] Flags: fast devsel, IOMMU group 12 00: 22 10 64 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.5 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 5 [1022:1465] Flags: fast devsel, IOMMU group 12 00: 22 10 65 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.6 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 6 [1022:1466] Flags: fast devsel, IOMMU group 12 00: 22 10 66 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.7 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 7 [1022:1467] Flags: fast devsel, IOMMU group 12 00: 22 10 67 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:00.0 Non-Volatile memory controller [0108]: Samsung Electronics Co Ltd NVMe SSD Controller SM981/PM981/PM983 [144d:a808] (prog-if 02 [NVM Express]) Subsystem: Samsung Electronics Co Ltd Device [144d:a801] Flags: bus master, fast devsel, latency 0, IRQ 70, NUMA node 0, IOMMU group 13 Memory at fe900000 (64-bit, non-prefetchable) [size=16K] Capabilities: <access denied> Kernel driver in use: nvme Kernel modules: nvme 00: 4d 14 08 a8 06 04 10 00 00 02 08 01 10 00 00 00 10: 04 00 90 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 4d 14 01 a8 30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 00 00 02:00.0 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] X370 Series Chipset USB 3.1 xHCI Controller [1022:43b9] (rev 02) (prog-if 30 [XHCI]) Subsystem: ASMedia Technology Inc. Device [1b21:1142] Flags: bus master, fast devsel, latency 0, IRQ 25, IOMMU group 14 Memory at fe6a0000 (64-bit, non-prefetchable) [size=32K] Capabilities: <access denied> Kernel driver in use: xhci_hcd 00: 22 10 b9 43 06 04 10 00 02 30 03 0c 10 00 80 00 10: 04 00 6a fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 21 1b 42 11 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 00 00 02:00.1 SATA controller [0106]: Advanced Micro Devices, Inc. [AMD] X370 Series Chipset SATA Controller [1022:43b5] (rev 02) (prog-if 01 [AHCI 1.0]) Subsystem: ASMedia Technology Inc. Device [1b21:1062] Flags: bus master, fast devsel, latency 0, IRQ 42, IOMMU group 14 Memory at fe680000 (32-bit, non-prefetchable) [size=128K] Expansion ROM at fe600000 [disabled] [size=512K] Capabilities: <access denied> Kernel driver in use: ahci 00: 22 10 b5 43 06 04 10 00 02 01 06 01 10 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 68 fe 00 00 00 00 21 1b 62 10 30: 00 00 60 fe 50 00 00 00 00 00 00 00 0a 02 00 00 02:00.2 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] X370 Series Chipset PCIe Upstream Port [1022:43b0] (rev 02) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 33, IOMMU group 14 Bus: primary=02, secondary=03, subordinate=09, sec-latency=0 I/O behind bridge: 0000e000-0000efff [size=4K] Memory behind bridge: fe400000-fe5fffff [size=2M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 b0 43 07 04 10 00 02 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 02 03 09 00 e1 e1 00 00 20: 40 fe 50 fe f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 0f 03 12 00 03:00.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] 300 Series Chipset PCIe Port [1022:43b4] (rev 02) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 34, IOMMU group 14 Bus: primary=03, secondary=04, subordinate=04, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: [disabled] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 b4 43 07 04 10 00 02 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 03 04 04 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 12 00 03:02.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] 300 Series Chipset PCIe Port [1022:43b4] (rev 02) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 35, IOMMU group 14 Bus: primary=03, secondary=05, subordinate=05, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: [disabled] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 b4 43 07 04 10 00 02 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 03 05 05 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 0f 01 12 00 03:03.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] 300 Series Chipset PCIe Port [1022:43b4] (rev 02) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 37, IOMMU group 14 Bus: primary=03, secondary=06, subordinate=06, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: [disabled] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 b4 43 07 04 10 00 02 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 03 06 06 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 05 01 12 00 03:04.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] 300 Series Chipset PCIe Port [1022:43b4] (rev 02) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 38, IOMMU group 14 Bus: primary=03, secondary=07, subordinate=07, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: fe500000-fe5fffff [size=1M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 b4 43 07 04 10 00 02 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 03 07 07 00 f1 01 00 00 20: 50 fe 50 fe f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 12 00 03:06.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] 300 Series Chipset PCIe Port [1022:43b4] (rev 02) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 39, IOMMU group 14 Bus: primary=03, secondary=08, subordinate=08, sec-latency=0 I/O behind bridge: 0000e000-0000efff [size=4K] Memory behind bridge: fe400000-fe4fffff [size=1M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 b4 43 07 04 10 00 02 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 03 08 08 00 e1 e1 00 00 20: 40 fe 40 fe f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 0f 01 12 00 03:07.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] 300 Series Chipset PCIe Port [1022:43b4] (rev 02) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 40, IOMMU group 14 Bus: primary=03, secondary=09, subordinate=09, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: [disabled] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 b4 43 07 04 10 00 02 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 03 09 09 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 05 01 12 00 07:00.0 USB controller [0c03]: ASMedia Technology Inc. ASM1143 USB 3.1 Host Controller [1b21:1343] (prog-if 30 [XHCI]) Subsystem: ASUSTeK Computer Inc. Device [1043:86f2] Flags: bus master, fast devsel, latency 0, IRQ 25, IOMMU group 14 Memory at fe500000 (64-bit, non-prefetchable) [size=32K] Capabilities: <access denied> Kernel driver in use: xhci_hcd 00: 21 1b 43 13 06 04 10 00 00 30 03 0c 10 00 00 00 10: 04 00 50 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 f2 86 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 00 00 08:00.0 Ethernet controller [0200]: Intel Corporation I211 Gigabit Network Connection [8086:1539] (rev 03) Subsystem: ASUSTeK Computer Inc. Device [1043:85f0] Flags: bus master, fast devsel, latency 0, IRQ 24, IOMMU group 14 Memory at fe400000 (32-bit, non-prefetchable) [size=128K] I/O ports at e000 [size=32] Memory at fe420000 (32-bit, non-prefetchable) [size=16K] Capabilities: <access denied> Kernel driver in use: igb Kernel modules: igb 00: 86 80 39 15 07 04 10 00 03 00 00 02 10 00 00 00 10: 00 00 40 fe 00 00 00 00 01 e0 00 00 00 00 42 fe 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 f0 85 30: 00 00 00 00 40 00 00 00 00 00 00 00 0f 01 00 00 0a:00.0 VGA compatible controller [0300]: Advanced Micro Devices, Inc. [AMD/ATI] Oland PRO [Radeon R7 240/340] [1002:6613] (rev 87) (prog-if 00 [VGA controller]) Subsystem: Micro-Star International Co., Ltd. [MSI] Device [1462:8094] Flags: bus master, fast devsel, latency 0, IRQ 97, IOMMU group 15 Memory at e0000000 (64-bit, prefetchable) [size=256M] Memory at fe800000 (64-bit, non-prefetchable) [size=256K] I/O ports at d000 [size=256] Expansion ROM at 000c0000 [disabled] [size=128K] Capabilities: <access denied> Kernel driver in use: radeon Kernel modules: radeon, amdgpu 00: 02 10 13 66 07 04 10 00 87 00 00 03 10 00 80 00 10: 0c 00 00 e0 00 00 00 00 04 00 80 fe 00 00 00 00 20: 01 d0 00 00 00 00 00 00 00 00 00 00 62 14 94 80 30: 00 00 84 fe 48 00 00 00 00 00 00 00 0e 01 00 00 0a:00.1 Audio device [0403]: Advanced Micro Devices, Inc. [AMD/ATI] Oland/Hainan/Cape Verde/Pitcairn HDMI Audio [Radeon HD 7000 Series] [1002:aab0] Subsystem: Micro-Star International Co., Ltd. [MSI] Device [1462:aab0] Flags: bus master, fast devsel, latency 0, IRQ 99, IOMMU group 15 Memory at fe860000 (64-bit, non-prefetchable) [size=16K] Capabilities: <access denied> Kernel driver in use: snd_hda_intel Kernel modules: snd_hda_intel 00: 02 10 b0 aa 07 04 10 00 00 00 03 04 10 00 80 00 10: 04 00 86 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 62 14 b0 aa 30: 00 00 00 00 48 00 00 00 00 00 00 00 0b 02 00 00 0b:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Zeppelin/Raven/Raven2 PCIe Dummy Function [1022:145a] Subsystem: Advanced Micro Devices, Inc. [AMD] Zeppelin/Raven/Raven2 PCIe Dummy Function [1022:145a] Flags: fast devsel, IOMMU group 16 Capabilities: <access denied> 00: 22 10 5a 14 00 00 10 00 00 00 00 13 10 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 5a 14 30: 00 00 00 00 48 00 00 00 00 00 00 00 ff 00 00 00 0b:00.2 Encryption controller [1080]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Platform Security Processor [1022:1456] Subsystem: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Platform Security Processor [1022:1456] Flags: bus master, fast devsel, latency 0, IRQ 72, IOMMU group 17 Memory at fe200000 (32-bit, non-prefetchable) [size=1M] Memory at fe300000 (32-bit, non-prefetchable) [size=8K] Capabilities: <access denied> Kernel driver in use: ccp Kernel modules: ccp 00: 22 10 56 14 06 04 10 00 00 00 80 10 10 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 20 fe 00 00 00 00 20: 00 00 00 00 00 00 30 fe 00 00 00 00 22 10 56 14 30: 00 00 00 00 48 00 00 00 00 00 00 00 0a 02 00 00 0b:00.3 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] Zeppelin USB 3.0 Host controller [1022:145f] (prog-if 30 [XHCI]) Subsystem: ASUSTeK Computer Inc. Device [1043:8747] Flags: bus master, fast devsel, latency 0, IRQ 61, IOMMU group 18 Memory at fe100000 (64-bit, non-prefetchable) [size=1M] Capabilities: <access denied> Kernel driver in use: xhci_hcd 00: 22 10 5f 14 07 04 10 00 00 30 03 0c 10 00 80 00 10: 04 00 10 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 47 87 30: 00 00 00 00 48 00 00 00 00 00 00 00 0f 03 00 00 0c:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Zeppelin/Renoir PCIe Dummy Function [1022:1455] Subsystem: Advanced Micro Devices, Inc. [AMD] Zeppelin/Renoir PCIe Dummy Function [1022:1455] Flags: fast devsel, IOMMU group 19 Capabilities: <access denied> 00: 22 10 55 14 00 00 10 00 00 00 00 13 10 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 55 14 30: 00 00 00 00 48 00 00 00 00 00 00 00 ff 00 00 00 0c:00.2 SATA controller [0106]: Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI mode] [1022:7901] (rev 51) (prog-if 01 [AHCI 1.0]) Subsystem: ASUSTeK Computer Inc. Device [1043:8747] Flags: bus master, fast devsel, latency 0, IRQ 44, IOMMU group 20 Memory at fe708000 (32-bit, non-prefetchable) [size=4K] Capabilities: <access denied> Kernel driver in use: ahci 00: 22 10 01 79 07 04 10 00 51 01 06 01 10 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 80 70 fe 00 00 00 00 43 10 47 87 30: 00 00 00 00 48 00 00 00 00 00 00 00 0f 02 00 00 0c:00.3 Audio device [0403]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) HD Audio Controller [1022:1457] Subsystem: ASUSTeK Computer Inc. Device [1043:8733] Flags: bus master, fast devsel, latency 0, IRQ 101, IOMMU group 21 Memory at fe700000 (32-bit, non-prefetchable) [size=32K] Capabilities: <access denied> Kernel driver in use: snd_hda_intel Kernel modules: snd_hda_intel 00: 22 10 57 14 06 04 10 00 00 00 03 04 10 00 80 00 10: 00 00 70 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 33 87 30: 00 00 00 00 48 00 00 00 00 00 00 00 05 03 00 00 ----------------------------------------------------- Best Regards, Andrew

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Re: Questions About Flashrom Of Gsoc
by Anastasia Klimchuk 25 Mar '22

25 Mar '22

Hi Hui, First of all, I wanted to say, you replied to me only and not to the mailing list (and I only noticed now). Most likely you clicked the "Reply" button instead of "Reply All". I am adding the mailing list back, but for future please keep in mind to Reply All. The most important reason is that if you send your questions to the mailing list, then everyone in our community can help you! Which is really good. You will have various questions, and you never know who is the best person to answer. So, pay attention that the mailing list is on the To line ;) Some things I can answer: >> The platform Gerrit is mentioned in the "Development Guidelines." All I know about it is that it is a code management tool. Are there any tutorial videos or articles that I can use to learn more about Gerrit? Gerrit is also a code review tool. Gerrit has an official website with lots of presentations, look here https://www.gerritcodereview.com/presentations.html , hopefully that's useful! >> I went to GitHub's official Flashrom mirror. You can browse all code on GitHub, no problem, and yes it can be a convenient way to browse. Just keep in mind GitHub is a mirror, so that's pretty much only for browsing code. When you start with trying to make changes by yourself, you need to set up flashrom git repository locally. When you come to that point, open https://review.coreboot.org/admin/repos/flashrom and choose your desired method to clone the repository. Supported methods are HTTPS and SSH. The same method will also be used when you push your changes to Gerrit later. >> My current devices are a Windows 11 laptop (processor 11370H, Tiger Lake-H35) and a Mac. Is it possible for me to try out some patches on my computer? Also, could you provide me with any resources or introductions to chip packaging (DIP32, PLCC32, DIP8...)? I am wondering if someone else can take these questions? We need community help on this :) Thanks! On Thu, Mar 10, 2022 at 6:59 AM Hui Xiang <zavier2001(a)outlook.com> wrote: > Dear Anastasia, > > > > Thank you for your response. I read the "Contributor Guidelines" and have > some questions. > > > > >> "work with our git repository." > > I went to GitHub's official Flashrom mirror. The repository contains a > large number of files. Which file would you recommend I start with if I > want to familiarize myself with the current codes on GitHub? The platform > Gerrit is mentioned in the "Development Guidelines." All I know about it is > that it is a code management tool. Are there any tutorial videos or > articles that I can use to learn more about Gerrit? > > > > >> "downloaded and built flashrom as well as applied some patches." > > My current devices are a Windows 11 laptop (processor 11370H, Tiger > Lake-H35) and a Mac. Is it possible for me to try out some patches on my > computer? Also, could you provide me with any resources or introductions to > chip packaging (DIP32, PLCC32, DIP8...)? I looked them up on Google, but > there is not much information about them. > > > > >> "Check Easy projects or ask for simple tasks on the mailing list or on > IRC." > > I went to the "Easy projects" page and decided to start my job with "Find > chips without voltage data." What can I do about it? Could you provide me > with any tips and advice? Thank you very much. > > > > I joined the IRC channel through Libera. Chat. My nickname is Hui_Xiang. > Is it necessary for me to install an IRC client on my computer? Thank you > for looking into this for me. I appreciate it. > > > > Best Regards, > > Hui > > > > > > *From:* Anastasia Klimchuk <aklm(a)chromium.org> > *Sent:* 09 March 2022 01:50 > *To:* flashrom(a)flashrom.org; Hui Xiang <zavier2001(a)outlook.com> > *Subject:* Re: [flashrom] Questions About Flashrom Of Gsoc > > > > Hello Hui, > > Nice to meet you! Great to know that you are interested to work with us > this Summer of Code! > > It is very good that you looked into the list of project ideas and are > interested in one of them, and your experience in C is very relevant. > > > What resources can I use to learn more about it? > > First thing, please have a read of our Contributor Guidelines > https://www.flashrom.org/GSoC especially the “Contributor commitments & > requirements” section, and see if you can gradually start with p.1 “Prior > to project acceptance, you need to demonstrate that you can work with the > flashrom codebase”. It is important that you complete all steps from 1 to 5. > Definitely tell us how it goes! You can reply to this email, tell us what > steps you did successfully, or if not, what are the problems. > > Also look into the “How to contact us” section, join our IRC channel and > say hello! :) > > Just in case, if you haven’t read these already, here are official > guidelines for gsoc program: > https://google.github.io/gsocguides/student/ > Rules https://summerofcode.withgoogle.com/rules (at least check p.7 from > here) > > > What skills do I need to improve to get accepted from Flashrom? > > For the project you are interested in, good knowledge of C language is a > critical skill. > > Thank you! > > Anastasia. > > > -- Anastasia.

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flashrom dev meeting notes 23.03.22
by Felix Singer 24 Mar '22

24 Mar '22

# Decisions on 23th March 2022: * Meeting times from not until November will alternate between two different times (to be voted upon) so that no one group will be excluded from every meeting. Time1 is EU+AU, Time2 is EU+US. * In the short term, any money collected for the Flashrom project, will be given to the coreboot project. coreboot will maintain a ledger for flashrom money. * We want a single build system (either Make or Meson). Anastasia will set up a separate meeting to discuss the “Makefile vs Meson” topic. * Next meeting will be in 2 weeks since there's still so much on the agenda. # 23th March 2022, 21:00-22:00 UTC+0 **Attendees: **Thomas, Michal, Felix, Anastasia, David, Nico, Patrick, Edward, Martin, Carl-Daniel **Agenda:** * [FelixS] Before we start discussing new topics, anything we need to discuss from the last meeting? * Leadership question is relevant to the item below, about fiscal sponsorship * [aklm] Reminder: daylight saving time is approaching. Next time we will use this time (21.00-22.00 UTC+0) in November. * For the next occurrence of dev meeting, Felix will send a poll to vote on days/times for the interval Apr-Sept. * In October we can have a vacation from each other (because there is a month diff when DST happens in different locations). * Martin: Can we have a schedule where the bad time rotates? So one out of every 3 times is poor for 1 group, but better for the other two. * Will do alternating times until november. Alternating between EU+AU and EU+US. * [Martinr] Should flashrom look for a fiscal sponsor so that it can accept donations? * [aklm] (possibly related) As an organization we can get some money per successful gsoc project (around 500 USD IIRC). Where do we put it? A bank account? * That's exactly the issue. In the past, before coreboot joined the SFC, the coreboot project had no way to accept donations, so the money was just donated directly to the SFC. By joining a fiscal sponsor, that allows money to be donated to the flashrom project to be used for purchasing test equipment, boards, servers, or whatever is needed. * [https://opensource.com/article/19/1/fiscal-sponsors-open-source](https://op… * [aklm] I just (10/03) got this comms from gsoc orgs: “For orgs who need to change their financial details for GSoC 2022, the deadline to have all of your Payoneer account information completed is July 15, 2022 as described in the Program Rules. We will not pay out stipends to any orgs who miss this hard deadline. We'll send more details about receiving stipends etc. in May so you'll have 2 months to get everything in order.” * It takes a long time to join a fiscal sponsor, so if flashrom is going to join a group, we're probably looking at 2023. * [FelixS] Since there is no legal entity around flashrom, we would have to create one first or a private person needs to take the money for now. In any case, this brings a lot of complicated implications and work (e.g. taxes). Can we just transfer the money to coreboot? * Since flashrom currently shares the coreboot infrastructure, in the short term, combining the financial interests makes sense. In the long term, we might want to look at having the projects be more separate, and getting a fiscal sponsorship for flashrom itself. * aklm will ask gsoc organizers on a mailing list, to get official reply whether 2 orgs can have the same account. * [Patrick] SFC needs some point of contact that can make decisions (e.g. about spending project money), so that's where the "leadership" thing came from in coreboot. They also strongly suggest to have at least 3 people and to avoid having outsized impact of any particular company contributing which informed how we defined our leadership group make up. * [aklm] Meson and Makefile. For upstream, Makefile is officially supported and used by developers, Meson is only used for unit tests. For chromium, Meson is officially supported and used for everything, including tests. Logically, these two should be in sync, since they are building the same code. Each side is interested in one build system (the one they are using). Can we join forces and keep two build systems in sync? * [FelixS] Thomas is about cleaning up both build systems and bringing them closer. * [Thomas] I’m working on getting the Makefile in a readable and usable state. A lot of configuration was / is done by C preprocessor macros. I’m trying to get rid of those. Since the meson.build is mostly a copy of the Makefile I want to update it when the Makefile is in a good shape. Currently the meson.build lags support for non Linux systems. I personally would prefer meson as a single build system, but we are not at this point yet. * [Edward and Martin] we need to test builds in both build systems until a single build system is selected. * [David] Are there any fundamental differences between the two build systems that cannot be resolved? We need to do gap analysis * [FelixS] I think Thomas mentioned a few things that can’t be done with Meson, or which are harder to do, but AFAIK he is working on it adding this functionality to upstream Meson. * [aklm] Do we all agree that we ideally have one build system? * YES! * Why did googlers decide to use meson? * [Edward] we want to use libflashrom instead of subprocessing, and that was supported well by meson. Also I have experience with both, and IMO meson is easier to maintain. Makefile is more ugly to do configurations for boards. * [Nico] secunet uses it in combination with FILO for firmware updates * [Thomas] I did lots of readability improvements and rework, but would like to switch to meson completely. It would be good to work with google to implement meson as the primary (and eventually only) build system. * Aklm to set up meeting (in 2 weeks from now) about meson and Makefile work, google will happily join this effort. Aklm is a google point of contact for the effort. * [Nico] Is meson capable of doing everything that Makefile is doing? Is ninja available on all platforms? * [CDH] if everything works for meson, I have no preference. But if not everything is working, then everyone will be unhappy. * [David] if we can cross-compile to DOS with meson, that would be a POC * [aklm] we do cross-compile with meson, just not for DOS * [Edward] How do we make it easy for new contributors to get involved in the project and grow the community to have more resources? * Improvements to community guidelines, * Improvements to developer documentation and expectations, * Convey appreciation to contributors and make them feel like no contribution is too small, * [aklm] Good news: this is exactly what we are doing right now! Literally, all of that starting from “How do we make it easy ….” to “.... no contribution is too small”. Importantly, these are not just words, but _lots of tasks to be done._ Since we got accepted to gsoc, already 6 people contacted us, they want to contribute. I really encourage everyone who can, to talk, respond to people, answer their questions, review their patches. I can quote myself from a previous meeting: “If you want to help and don’t know what to do, contact Anastasia or Felix.” * [dhendrix] Better automation. Git precommit hooks for style checks, etc. so that we don't waste review time telling newcomers where to put their braces, how to write a commit message, etc. * [FelixS] In my opinion, the website needs to be reworked. From my view, it’s not really inviting or motivating to read it. Also, many texts are outdated. * [David] What do we do about the GitHub mirror? Many issues and pull requests there, people are waiting for responses. * Edward suggests using [PRBot](https://github.com/ajdlinux/PRBot) * Martin: Do we want to add checks similar to coreboot's linters to the jenkins build? * Edward: Clang-format would be good. * [dhendrix]: revisit [https://review.coreboot.org/c/flashrom/+/44095](https://review.coreboot.org… ? * CDH: An automated message is much better than nothing. We need some sort of onboarding, and onboarding is always hard. * [aklm] Easy projects page, we need more easy projects for new people, please add if you have ideas. * [Nico] we have checkpatch set up for coreboot, I think this is a good thing, * [Martin] I think I can set this up. * [Martin] I can set up scan-build too * [Edward] we can display coverage in gerrit, contributors will see the progress for the changes in their patch? * [Thomas] note: tests are only for meson * [Martinr] The tests need to generate an output file, and a gerrit plugin needs to be added. coreboot currently has the files output, but the plugin isn't integrated yet. * [Felix] upstream pull requests as easy projects? * [Nico] These are not very easy projects, but there are unmerged patches on [patchwork](https://patchwork.coreboot.org/project/flashrom/list). We can see if there is some useful stuff there.

1 0

flashrom dev meeting notes 9.03.22
by Felix Singer 24 Mar '22

24 Mar '22

# Decisions 9th March 2022 * Will make this meeting bi-weekly until we've worked our way through the issues listed here. # 9th March 2022, 21:00-22:00 UTC+0 Attendees: Anastasia Klimchuk, Felix Singer, Thomas Heijligen, Stefan Reinauer, Edward O’Callaghan, Maciej Pijanowski, Miklos Marton, Martin Roth, Nico, Carl-Daniel, Piotr, Angel Pons Agenda: * [FelixS] First flashrom meeting. Let’s introduce ourselves and say what we are working on at flashrom. * [FelixS] flashrom has been accepted to GSoC * [GSoC project page](https://summerofcode.withgoogle.com/programs/2022/organizations/flash… ) * [Official announcement](https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom.o… ) * Current tasks? What is left to do? * [aklm] Respond to GSoC candidates, help and guide them * [aklm] Help improve [Development Guidelines](https://www.flashrom.org/Development_Guidelines), [Easy Projects](https://www.flashrom.org/Easy_projects) pages. * If you want to help and don’t know what to do, contact Anastasia or Felix. * [Martinr] Who is the flashrom leadership and how is that decided? * [Nico] For the last years this was rather implicitly who was maintaining the code to be safe and sound. And helping users on IRC and the ML and such. * Is this how the project wants to continue? It seems somewhat disorganized. Just because someone is a good coder doesn't necessarily make them a good leader. * Who decides "safe and sound"? Are there any metrics for this? * The coreboot project has 3 people who actually make the decisions. This was set up when we joined the SFC. Also the 3 leaders need to be from different companies. * SFC has a requirement that organisation defines its leadership. What exactly the leadership is, it is up to organisation, but there should be some leadership". And that's how coreboot got leadership: coreboot wanted to join SFC, so needed to define leadership. * Which means, if flashrom wants to join SFC we need leadership too * Nico: In the past there wasn't much to decide, so there was no need for official leadership. * [Anastasia] We need someone to make decisions after a discussion on the mailing list if there isn't a clear direction. * [Edward] Some kind of election process, [Martin] organized the vote system for coreboot. * [Nico] There are currently two different projects in one repo, so if the leadership picks one, there might end up being two projects? * [Martinr] How are decisions made in the flashrom project? In this meeting, on the mailing list, something else? * [Nico] So far for smaller topics on IRC. For bigger topics, I suggest the mailing list. * [Thomas and Felix] Before deciding on leadership we need to talk more to each other. This is the first meeting we see each other and talk. We need to talk more about development, code, need to know more what we are doing. * Conclusion: let’s everyone think about it and continue discussion later. Topic added to Ongoing Items. * [Martin/Nico] Should we split flashrom into two separate projects? * Nico when I started, the project was for everyone, and stability was a priority. * Now we're trying to add the google fork, which has different objectives. * Edward: This isn't a different objective. * Quality is degrading. * Is code even tested? * Edward: yes, there's a strong emphasis on testing and improving tests. * Felix: what is tested? Is this unit testing? * Google tests any paths that they have available for testing. * Intel, AMD, Linux, mtd, Dediprog, raiden debug. * In the past, we kept all the code working for generic systems, so when support was added for a chip, it works for all of them, or bails out early. * New code is for specific boards, but not documented * [Martin] So let's focus on testing and make stability branches. * Nico: There's nobody to do that testing. * Felix: with the jenkins replacement, I'm thinking about how to add hardware tests as a part of the CI. * Miklos: There was someone who had boards with spi roms on boards with multiplexers for testing. \ Referred to this [document about the Chromium team’s hardware test setup.](https://docs.google.com/document/d/1IoBR7rHXJFiahC6dGnNKqaNFfg-q89_… ) * [Edward] Exactly this has come up between a discussion originally Martin and latter with Nikolai Artemiev to get CI coverage for writeprotect changes. * [Edward] We need to document testing what testing is done on the wiki. * Google is working on testing and making sure that the tests can be run by anyone. * [Edward]: First part of this is upstream-first unit-testing efforts, second part harder. * [Edward]: We need to get boards hooked for E2E tests, looking at what is happening for coreboot CI? * [Piotr] aklm on IRC just received commit rights without any previous discussion [[1]](https://matrix.to/#/!SAlNdlJiEjYGbpbVfu:libera.chat/$eKIApfMuImHqA9T0TowmUaTylyfJAOWTn9iK0q7itQk?via=matrix.org&via=libera.chat&via=nixos.dev ) * [Martinr] Anastasia has earned her commit rights with 125 commits over the past 2 years, more than anyone else. She is active in the community. She has done more than 82 reviews, more than anyone but Angel, Edward, and Nico. If she doesn't deserve her commit rights, Angel, Edward and Nico are the only ones who do. The discussion about commit rights is listed below, but as mentioned there, IMO, Thomas is the only other person who has earned commit rights. * [Nico] Edward’s history in the project is quite unique. He got the submit rights before he landed a single patch and with close to 0 prior activity in the project. So we can’t really put him above or below anyone in this matter. * We can absolutely look at commits and reviews that he's done since then. * [Nico] I don’t think we can decide this matter simply on the amount of patches / reviews. * [Martin] So what are your thoughts on how people should get +2? Is this also the "safe and sound" rule? You don't give any suggestions here. * [Piotr] How to get patch submitting rights in flashrom? We have 4 patches in +2 for some time: [[1]](https://review.coreboot.org/c/flashrom/+/55713/), [[2]](https://review.coreboot.org/c/flashrom/+/55714), [[3]](https://review.coreboot.org/c/flashrom/+/55714), [[4]](https://review.coreboot.org/c/flashrom/+/55848/) * Current Submitters * Anastasia Klimchuk * Angel Pons * Carl-Daniel Hailfinger * David Hendricks * Edward O'Callaghan * Idwer Vollering * Nico Huber * Patrick Georgi * Stefan T * Urja Rannikko * The only other person that has a significant number of commits in the last 5 years is Thomas Heijligen with 83 commits since July 2019. Thomas seems like a good candidate for getting submit rights. * What are the criteria for giving someone +2? When is someone ready, and who makes that decision? * coreboot has a relatively loose criteria for adding people, but decisions are made by the leadership. * Felix: Change the process about how patches are merged * Maybe require 2 +2s? * In case patches are merged too early, request that patches stay on gerrit for greater than 2 days or so? * [Carl-Daniel] We have different strategies, availability. Reviews are harder than writing code. We need to give people time to do reviews. Maybe we need to give 2 weeks time for reviewers. Unless some really bad bug which kills machines. * We have different modes of working on code, different goals. * Nico: 2 weeks is probably too long. * [Angel] too many patches sometimes, too little time. Very stressful. Patches pile up, not enough time to review and respond to everything. A feeling that if I miss something and do not respond in time then things will go wrong (e.g. errors missed during review). * [Anastasia] maybe if reviewer is busy, they can send a message to gerrit saying “sorry I am busy for next X weeks, I will get back to you after X weeks, thanks”, and this gives information to patch owner. Makes a big difference.

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