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flashrom dev meeting notes 30.06.22
by Anastasia Klimchuk 01 Jul '22

01 Jul '22

# 30th June 2022, 6:00 - 7:00 UTC+0 Attendees: Edward, Thomas, Stefan, Nikolai, Anastasia, Felix ## Decisions Summary * Raiden_debug_spi: Thomas will do a review of this programmer and add comments to the bug [https://ticket.coreboot.org/issues/358](https://ticket.coreboot.org/issues/… * As a result of in-depth discussion of lspcon_i2c_spi and realtek_mst_i2c_spi a bunch of bugs will be created (TODO for aklm). Some of them have wider scope like infra improvements. * Sb600spi work has started and needs reviewers attention * [https://review.coreboot.org/c/flashrom/+/65237](https://review.coreboot.org… * [https://review.coreboot.org/c/flashrom/+/65238](https://review.coreboot.org… * [https://review.coreboot.org/c/flashrom/+/65239](https://review.coreboot.org… ## Agenda * [aklm] Bugs for release “document this programmer”. Is there anything left to do, if yes then what is left? * [raiden_debug_spi](https://github.com/flashrom/flashrom/blob/master/raiden_d… [https://ticket.coreboot.org/issues/358](https://ticket.coreboot.org/issues/… (man page and code comments added - [https://review.coreboot.org/c/flashrom/+/62768](https://review.coreboot.org…) * Docs [https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/master/… * Thomas will review raiden_debug and add all comments to the bug * AI(quasisec) work with Tools team to document the hardware schematics to make it easier to find and nativage by putting all the docs in one place. * AI(quasisec) file bug to convert init code so that usb vid:pid pair are in the deventry. Basically FIX the FIXME in [https://github.com/flashrom/flashrom/blob/master/raiden_debug_spi.c#L352](h… and remove lines [https://github.com/flashrom/flashrom/blob/master/raiden_debug_spi.c#L1501](… * Would be nice to consider moving from using packed structs to serialisation functions. * * lspcon_i2c_spi [https://ticket.coreboot.org/issues/360](https://ticket.coreboot.org/issues/… (man page added) * There is nothing to add to the name it seems: no model * Is there a way to know which chip you are talking? * We can try to improve board_enable infra for i2c, and then we can hook i2c programmer. * Board enable is specific to internal programmer. We could make it more generic to support more than internal. So that it can say “this board supports this chip”, or “no lspcon detected”. * Lspcon should query some kind of board enable (not the current one), and then board enable can come back and say “you are safe to run / or not”. * For the release we need to make sure people can’t break their devices easily. * TODO needs a bug1 (upgrade board enable infra), not release blocking * Nik good suggest to have a programmer param of “I_want_a_brick=true” to avoid accidentally picking the wrong programmer. * Until we have the infrastructure for i2c drivers to allow listing drivers. * TODO needs a bug2 for I_want_brick=true, release blocking. Temp solution until bug1 fixed. * Lspcon_i2c_spi_set_mpu_active in init function, is it board specific? If I have another board, can I run the programmer, or does it leave some gpio open? * TODO update lspcon_i2c_spi_write_aai documentation, why it throws an error straight away, why it is not using default aai function. Release blocking. * Can we find out which specific chips lspcon supports? * TODO to add documentation at the top of the file that only very specific chips supported. Document as much as you can on the top. When it is working and when it is not working. Release blocking * [https://github.com/Pulse-Eight/libcec/issues/280](https://github.com/Pulse-… * Where are hardcoded SPI opcodes? * This is a good argument for converting to opaque. * `SWSPI_WDATA_*` defines appear to be JEDEC commands, at least numerically. So a code comment for now until we know more. * TODO needs a bug (converting to opaque), soft blocking release * realtek_mst_i2c_spi [https://ticket.coreboot.org/issues/361](https://ticket.coreboot.org/issues/… (man page added) * ditto I_wanna_brick. * https://review.coreboot.org/c/flashrom/+/65545 * TODO update the comment on `realtek_mst_i2c_spi_toggle_gpio_88_strap` * https://review.coreboot.org/c/flashrom/+/65546 * [https://ticket.coreboot.org/issues/376](https://ticket.coreboot.org/issues/… (it says review mediatek_i2c_spi) * ditto I_wanna_brick. * **_TL;DR All i2c drivers make the assumption that the user knows what they are doing. However this could be a dangerous assumption._** * Immediate fix to have get_param() “I_want_a_brick=true” || bail. * Long term fix, extend board_enable to be more generic. * AI(quasisec): Consolidate usb_device.c / usbdev.c into something more unified. * usb_device is only used by raiden debug * usbdev is only used by [developer_box](https://github.com/flashrom/flashrom/blob/master/developerbo… * TODO needs a bug, not release blocking * [quasisec]: Uploaded some patches to clean up sb600spi. Hard to get support directly from AMD however would like to get a heart beat going reviewing the patches. * [https://review.coreboot.org/c/flashrom/+/65237](https://review.coreboot.org… * [https://review.coreboot.org/c/flashrom/+/65238](https://review.coreboot.org… * [https://review.coreboot.org/c/flashrom/+/65239](https://review.coreboot.org… -- Anastasia.

1 0

What todo with the "document ... programmer" tickets
by Nico Huber 29 Jun '22

29 Jun '22

Hi Anastasia, I've seen you put some questions about the programmer tickets[1-4] on the meeting agenda. I hope I can provide some answers already. Looking at the tickets, I see there are already lists of things to do. But you ask what is left to do. So somewhere seems to be a misunderstanding. * raiden_debug_spi: Seems ok. I think this one was really only missing a manpage entry. Now that it has some context, I guess an independent developer could actually review it now. ^^ * lspcon_i2c_spi & realtek_mst_i2c_spi: There's a misunderstanding I guess. The tickets say "Document ... programmer". But they list actual problems. My idea when I wrote the long lists of issues was not to document issues. But, hopefully, to get them addressed, in code. We could also document the issues, e.g. by cluttering the code with FIXME comments. This might at least slow the spreading of such code down. But I would have to ask, why have these drivers on the master branch? In one of the tickets it even says the driver is not used in production. Does that mean it's abandoned? Like I mentioned elsewhere, many of the issues could be mitigated by going through the board_enabled infrastructure. This was also men- tioned in the review of the mediatek_i2c_spi driver. All these I2C drivers could share a similar design, AFAICT. One of the manpage entries also revealed a new problem: I think it implies that after running `flashrom -p realtek_mst_i2c_spi:bus=0 -E` the device would be broken after a reset. That's unacceptable for flashrom. Another sign that it should go through the infrastructure of the internal programmer. Documentation for the hardware interface would also be very welcome. Basically, everything that one needs to understand the code (and can't be derived from flashrom sources) should be publicly documented. I think we should make this a rule for vendor additions. * mediatek_i2c_spi: What I have to say about this, I did on Gerrit. What happened is clearly against our development guidelines. It's a copy of another driver, but we don't have the time to look into it so let the community take care of it? WTF? Nico [1] https://ticket.coreboot.org/issues/358 [2] https://ticket.coreboot.org/issues/360 [3] https://ticket.coreboot.org/issues/361 [4] https://ticket.coreboot.org/issues/376

3 5

Two-branch development
by Nico Huber 28 Jun '22

28 Jun '22

Hi flashrom fellows, something that's on the agenda for the next dev meeting (30th June)[1]: Should we look at forking flashrom between version 2 (Classic, Legacy, or “Stable” flashrom) and version3 of flashrom (Modern, Tested or Contemporary), where new features are added? I think such a question deserves more attention, hence this email. My own thoughts about the topic are quite mixed. First of all, it's not the first time the idea to work on two branches comes up. When we switched to Git and Gerrit in 2017, we started with a `stable` and a `staging` branch[2]. There were reservations, of course. Most of all that the `staging` branch could fall out-of-sync quickly, so it would be too hard to port anything from there to `stable`. Maybe such problems could be be avoided by allowing merges from `stable` to `staging`. Eventually, we had a lot of new patches on the `staging` branch, including many fixups, so the features could have been ported to `stable`. But they were not, and we renamed `staging` to `master` instead. This was due to personal issues and not technical ones, though. I guess we can't really say if the branch model failed. Now to the current proposition. Again, we have the idea to have one more and one less stable branch. But this time they would drift apart on purpose, focusing on different subsets of program- mers and chips, AIUI. I would not object to continue development on two branches. Personally, I would most likely work on the stable "version 2" only. However, the naming would really be a tough nut to crack. Given my experience with this project, I would expect a branch that focuses on stability to be the more "modern" one very soon. Simply because it's much easier to add new features to something stable. I wouldn't mind if people try such a "version 3". But it seems risky. I fear it might lose focus quickly and be abandoned again. Cheers, Nico [1] https://docs.google.com/document/d/18qKvEbfPszjsJJGJhwi8kRVDUG3GZkADzQSH6WF… [2] https://www.flashrom.org/index.php?title=Development_Guidelines&oldid=2252#…

6 10

New chip: GD25Q64C
by janemba 25 Jun '22

25 Jun '22

Hello, flashrom can extract the eeprom from a GD25Q64C chip in a generic way. I did it and all worked fine. Also, I check the eeprom and its valid. However, flashrom told me to send you an email with some information which you can find attached. However, this is the output while using "-r" switch along with the verbose mode. I hope it will be fine. Cheers,

1 1

Unsupported EEPROM/flash device report
by Armin 25 Jun '22

25 Jun '22

Hi, here is a report of an unsupported EEPROM/flash device: _flashrom output:_ flashrom v1.2 on Linux 5.15.0-40-generic (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Found chipset "AMD FP4". Enabling flash write... FCH device found but SMBus revision 0x59 does not match known values. Please report this to flashrom(a)flashrom.org and include this log and the output of lspci -nnvx, thanks!. Could not determine chipset generation.PROBLEMS, continuing anyway No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. _lspci -nnvx output:_ 00:00.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Root Complex [1022:1450] Subsystem: ASRock Incorporation Family 17h (Models 00h-0fh) Root Complex [1849:1450] Flags: fast devsel, NUMA node 0 00: 22 10 50 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 49 18 50 14 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:01.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] Flags: fast devsel, NUMA node 0 00: 22 10 52 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:01.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) PCIe GPP Bridge [1022:1453] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 26, NUMA node 0 Bus: primary=00, secondary=01, subordinate=07, sec-latency=0 I/O behind bridge: 00001000-00002fff [size=8K] Memory behind bridge: ba000000-ba9fffff [size=10M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 53 14 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 01 07 00 11 21 00 20 20: 00 ba 90 ba f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 12 00 00:02.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] Flags: fast devsel, NUMA node 0 00: 22 10 52 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:03.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] Flags: fast devsel, NUMA node 0 00: 22 10 52 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:04.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] Flags: fast devsel, NUMA node 0 00: 22 10 52 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:07.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] Flags: fast devsel, NUMA node 0 00: 22 10 52 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:07.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Internal PCIe GPP Bridge 0 to Bus B [1022:1454] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 27, NUMA node 0 Bus: primary=00, secondary=08, subordinate=08, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: bab00000-badfffff [size=3M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 54 14 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 08 08 00 f1 01 00 00 20: b0 ba d0 ba f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 12 00 00:08.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] Flags: fast devsel, NUMA node 0 00: 22 10 52 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:08.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Internal PCIe GPP Bridge 0 to Bus B [1022:1454] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 29, NUMA node 0 Bus: primary=00, secondary=09, subordinate=09, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: bae00000-baefffff [size=1M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 54 14 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 09 09 00 f1 01 00 00 20: e0 ba e0 ba f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 12 00 00:14.0 SMBus [0c05]: Advanced Micro Devices, Inc. [AMD] FCH SMBus Controller [1022:790b] (rev 59) Subsystem: ASRock Incorporation FCH SMBus Controller [1849:ffff] Flags: 66MHz, medium devsel, NUMA node 0 Kernel driver in use: piix4_smbus Kernel modules: i2c_piix4, sp5100_tco 00: 22 10 0b 79 03 04 20 02 59 00 05 0c 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 49 18 ff ff 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.3 ISA bridge [0601]: Advanced Micro Devices, Inc. [AMD] FCH LPC Bridge [1022:790e] (rev 51) Subsystem: ASRock Incorporation FCH LPC Bridge [1849:ffff] Flags: bus master, 66MHz, medium devsel, latency 0, NUMA node 0 00: 22 10 0e 79 0f 00 20 02 51 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 49 18 ff ff 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 0 [1022:1460] Flags: fast devsel, NUMA node 0 00: 22 10 60 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.1 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 1 [1022:1461] Flags: fast devsel, NUMA node 0 00: 22 10 61 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.2 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 2 [1022:1462] Flags: fast devsel, NUMA node 0 00: 22 10 62 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.3 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 3 [1022:1463] Flags: fast devsel, NUMA node 0 Kernel driver in use: k10temp Kernel modules: k10temp 00: 22 10 63 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.4 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 4 [1022:1464] Flags: fast devsel, NUMA node 0 00: 22 10 64 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.5 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 5 [1022:1465] Flags: fast devsel, NUMA node 0 00: 22 10 65 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.6 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 6 [1022:1466] Flags: fast devsel, NUMA node 0 00: 22 10 66 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.7 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 7 [1022:1467] Flags: fast devsel, NUMA node 0 00: 22 10 67 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:19.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 0 [1022:1460] Flags: fast devsel, NUMA node 0 00: 22 10 60 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:19.1 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 1 [1022:1461] Flags: fast devsel, NUMA node 0 00: 22 10 61 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:19.2 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 2 [1022:1462] Flags: fast devsel, NUMA node 0 00: 22 10 62 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:19.3 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 3 [1022:1463] Flags: fast devsel, NUMA node 0 Kernel driver in use: k10temp Kernel modules: k10temp 00: 22 10 63 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:19.4 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 4 [1022:1464] Flags: fast devsel, NUMA node 0 00: 22 10 64 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:19.5 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 5 [1022:1465] Flags: fast devsel, NUMA node 0 00: 22 10 65 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:19.6 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 6 [1022:1466] Flags: fast devsel, NUMA node 0 00: 22 10 66 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:19.7 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Data Fabric: Device 18h; Function 7 [1022:1467] Flags: fast devsel, NUMA node 0 00: 22 10 67 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:00.0 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] X399 Series Chipset USB 3.1 xHCI Controller [1022:43ba] (rev 02) (prog-if 30 [XHCI]) Subsystem: ASMedia Technology Inc. X399 Series Chipset USB 3.1 xHCI Controller [1b21:1142] Flags: bus master, fast devsel, latency 0, IRQ 32, NUMA node 0 Memory at ba9a0000 (64-bit, non-prefetchable) [size=32K] Capabilities: <access denied> Kernel driver in use: xhci_hcd Kernel modules: xhci_pci 00: 22 10 ba 43 06 04 10 00 02 30 03 0c 10 00 80 00 10: 04 00 9a ba 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 21 1b 42 11 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 00 00 01:00.1 SATA controller [0106]: Advanced Micro Devices, Inc. [AMD] X399 Series Chipset SATA Controller [1022:43b6] (rev 02) (prog-if 01 [AHCI 1.0]) Subsystem: ASMedia Technology Inc. X399 Series Chipset SATA Controller [1b21:1062] Flags: bus master, fast devsel, latency 0, IRQ 87, NUMA node 0 Memory at ba980000 (32-bit, non-prefetchable) [size=128K] Expansion ROM at ba900000 [disabled] [size=512K] Capabilities: <access denied> Kernel driver in use: ahci Kernel modules: ahci 00: 22 10 b6 43 06 04 10 00 02 01 06 01 10 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 98 ba 00 00 00 00 21 1b 62 10 30: 00 00 90 ba 50 00 00 00 00 00 00 00 0a 02 00 00 01:00.2 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] X399 Series Chipset PCIe Bridge [1022:43b1] (rev 02) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 31, NUMA node 0 Bus: primary=01, secondary=02, subordinate=07, sec-latency=0 I/O behind bridge: 00001000-00002fff [size=8K] Memory behind bridge: ba000000-ba8fffff [size=9M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 b1 43 07 04 10 00 02 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 01 02 07 00 11 21 00 00 20: 00 ba 80 ba f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 05 03 12 00 02:00.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] 300 Series Chipset PCIe Port [1022:43b4] (rev 02) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 33, NUMA node 0 Bus: primary=02, secondary=03, subordinate=03, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: ba000000-ba4fffff [size=5M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 b4 43 07 04 10 00 02 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 02 03 03 00 f1 01 00 00 20: 00 ba 40 ba f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 12 00 02:04.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] 300 Series Chipset PCIe Port [1022:43b4] (rev 02) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 34, NUMA node 0 Bus: primary=02, secondary=04, subordinate=04, sec-latency=0 I/O behind bridge: 00002000-00002fff [size=4K] Memory behind bridge: ba800000-ba8fffff [size=1M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 b4 43 07 04 10 00 02 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 02 04 04 00 21 21 00 00 20: 80 ba 80 ba f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 12 00 02:05.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] 300 Series Chipset PCIe Port [1022:43b4] (rev 02) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 36, NUMA node 0 Bus: primary=02, secondary=05, subordinate=05, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: ba700000-ba7fffff [size=1M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 b4 43 07 04 10 00 02 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 02 05 05 00 f1 01 00 00 20: 70 ba 70 ba f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 01 12 00 02:06.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] 300 Series Chipset PCIe Port [1022:43b4] (rev 02) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 37, NUMA node 0 Bus: primary=02, secondary=06, subordinate=06, sec-latency=0 I/O behind bridge: 00001000-00001fff [size=4K] Memory behind bridge: ba600000-ba6fffff [size=1M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 b4 43 07 04 10 00 02 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 02 06 06 00 11 11 00 00 20: 60 ba 60 ba f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 05 01 12 00 02:07.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] 300 Series Chipset PCIe Port [1022:43b4] (rev 02) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 39, NUMA node 0 Bus: primary=02, secondary=07, subordinate=07, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: [disabled] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 b4 43 07 04 10 00 02 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 02 07 07 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 12 00 03:00.0 Ethernet controller [0200]: Aquantia Corp. AQC107 NBase-T/IEEE 802.3bz Ethernet Controller [AQtion] [1d6a:d107] (rev 02) Subsystem: ASRock Incorporation AQC107 NBase-T/IEEE 802.3bz Ethernet Controller [AQtion] [1849:d107] Flags: bus master, fast devsel, latency 0, IRQ 32, NUMA node 0 Memory at ba440000 (64-bit, non-prefetchable) [size=64K] Memory at ba450000 (64-bit, non-prefetchable) [size=4K] Memory at ba000000 (64-bit, non-prefetchable) [size=4M] Expansion ROM at ba400000 [disabled] [size=256K] Capabilities: <access denied> Kernel driver in use: atlantic Kernel modules: atlantic 00: 6a 1d 07 d1 07 04 10 00 02 00 00 02 10 00 00 00 10: 04 00 44 ba 00 00 00 00 04 00 45 ba 00 00 00 00 20: 04 00 00 ba 00 00 00 00 00 00 00 00 49 18 07 d1 30: 00 00 40 ba 40 00 00 00 00 00 00 00 0b 01 00 00 04:00.0 Ethernet controller [0200]: Intel Corporation I211 Gigabit Network Connection [8086:1539] (rev 03) Subsystem: ASRock Incorporation I211 Gigabit Network Connection [1849:1539] Flags: bus master, fast devsel, latency 0, IRQ 32, NUMA node 0 Memory at ba800000 (32-bit, non-prefetchable) [size=128K] I/O ports at 2000 [size=32] Memory at ba820000 (32-bit, non-prefetchable) [size=16K] Capabilities: <access denied> Kernel driver in use: igb Kernel modules: igb 00: 86 80 39 15 07 04 10 00 03 00 00 02 10 00 00 00 10: 00 00 80 ba 00 00 00 00 01 20 00 00 00 00 82 ba 20: 00 00 00 00 00 00 00 00 00 00 00 00 49 18 39 15 30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 00 00 05:00.0 Network controller [0280]: Intel Corporation Dual Band Wireless-AC 3168NGW [Stone Peak] [8086:24fb] (rev 10) Subsystem: Intel Corporation Dual Band Wireless-AC 3168NGW [Stone Peak] [8086:2110] Flags: bus master, fast devsel, latency 0, IRQ 136, NUMA node 0 Memory at ba700000 (64-bit, non-prefetchable) [size=8K] Capabilities: <access denied> Kernel driver in use: iwlwifi Kernel modules: iwlwifi 00: 86 80 fb 24 06 04 10 00 10 00 80 02 10 00 00 00 10: 04 00 70 ba 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 10 21 30: 00 00 00 00 c8 00 00 00 00 00 00 00 0a 01 00 00 06:00.0 Ethernet controller [0200]: Intel Corporation I211 Gigabit Network Connection [8086:1539] (rev 03) Subsystem: ASRock Incorporation I211 Gigabit Network Connection [1849:1539] Flags: bus master, fast devsel, latency 0, IRQ 30, NUMA node 0 Memory at ba600000 (32-bit, non-prefetchable) [size=128K] I/O ports at 1000 [size=32] Memory at ba620000 (32-bit, non-prefetchable) [size=16K] Capabilities: <access denied> Kernel driver in use: igb Kernel modules: igb 00: 86 80 39 15 07 04 10 00 03 00 00 02 10 00 00 00 10: 00 00 60 ba 00 00 00 00 01 10 00 00 00 00 62 ba 20: 00 00 00 00 00 00 00 00 00 00 00 00 49 18 39 15 30: 00 00 00 00 40 00 00 00 00 00 00 00 05 01 00 00 08:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Zeppelin/Raven/Raven2 PCIe Dummy Function [1022:145a] Subsystem: Advanced Micro Devices, Inc. [AMD] Zeppelin/Raven/Raven2 PCIe Dummy Function [1022:145a] Flags: fast devsel, NUMA node 0 Capabilities: <access denied> 00: 22 10 5a 14 00 00 10 00 00 00 00 13 10 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 5a 14 30: 00 00 00 00 48 00 00 00 00 00 00 00 ff 00 00 00 08:00.2 Encryption controller [1080]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Platform Security Processor [1022:1456] Subsystem: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Platform Security Processor [1022:1456] Flags: bus master, fast devsel, latency 0, IRQ 130, NUMA node 0 Memory at bac00000 (32-bit, non-prefetchable) [size=1M] Memory at bad00000 (32-bit, non-prefetchable) [size=8K] Capabilities: <access denied> Kernel driver in use: ccp Kernel modules: ccp 00: 22 10 56 14 06 04 10 00 00 00 80 10 10 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 c0 ba 00 00 00 00 20: 00 00 00 00 00 00 d0 ba 00 00 00 00 22 10 56 14 30: 00 00 00 00 48 00 00 00 00 00 00 00 0a 02 00 00 08:00.3 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] Zeppelin USB 3.0 Host controller [1022:145f] (prog-if 30 [XHCI]) Subsystem: Advanced Micro Devices, Inc. [AMD] Zeppelin USB 3.0 Host controller [1022:d102] Flags: bus master, fast devsel, latency 0, IRQ 105, NUMA node 0 Memory at bab00000 (64-bit, non-prefetchable) [size=1M] Capabilities: <access denied> Kernel driver in use: xhci_hcd Kernel modules: xhci_pci 00: 22 10 5f 14 07 04 10 00 00 30 03 0c 10 00 80 00 10: 04 00 b0 ba 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 02 d1 30: 00 00 00 00 48 00 00 00 00 00 00 00 05 03 00 00 09:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Zeppelin/Renoir PCIe Dummy Function [1022:1455] Subsystem: Advanced Micro Devices, Inc. [AMD] Zeppelin/Renoir PCIe Dummy Function [1022:1455] Flags: fast devsel, NUMA node 0 Capabilities: <access denied> 00: 22 10 55 14 00 00 10 00 00 00 00 13 10 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 55 14 30: 00 00 00 00 48 00 00 00 00 00 00 00 ff 00 00 00 09:00.2 SATA controller [0106]: Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI mode] [1022:7901] (rev 51) (prog-if 01 [AHCI 1.0]) Subsystem: ASRock Incorporation FCH SATA Controller [AHCI mode] [1849:ffff] Flags: bus master, fast devsel, latency 0, IRQ 104, NUMA node 0 Memory at bae08000 (32-bit, non-prefetchable) [size=4K] Capabilities: <access denied> Kernel driver in use: ahci Kernel modules: ahci 00: 22 10 01 79 07 04 10 00 51 01 06 01 10 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 80 e0 ba 00 00 00 00 49 18 ff ff 30: 00 00 00 00 48 00 00 00 00 00 00 00 05 02 00 00 09:00.3 Audio device [0403]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) HD Audio Controller [1022:1457] Subsystem: ASRock Incorporation Family 17h (Models 00h-0fh) HD Audio Controller [1849:1221] Flags: bus master, fast devsel, latency 0, IRQ 138, NUMA node 0 Memory at bae00000 (32-bit, non-prefetchable) [size=32K] Capabilities: <access denied> Kernel driver in use: snd_hda_intel Kernel modules: snd_hda_intel 00: 22 10 57 14 06 04 10 00 00 00 03 04 10 00 80 00 10: 00 00 e0 ba 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 49 18 21 12 30: 00 00 00 00 48 00 00 00 00 00 00 00 0b 03 00 00 40:00.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Root Complex [1022:1450] Subsystem: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Root Complex [1022:1450] Flags: fast devsel, NUMA node 1 00: 22 10 50 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 50 14 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40:01.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] Flags: fast devsel, NUMA node 1 00: 22 10 52 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40:01.2 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) PCIe GPP Bridge [1022:1453] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 40, NUMA node 1 Bus: primary=40, secondary=41, subordinate=41, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: 9e600000-9e6fffff [size=1M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 53 14 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 40 41 41 00 f1 01 00 20 20: 60 9e 60 9e f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 12 00 40:01.3 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) PCIe GPP Bridge [1022:1453] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 41, NUMA node 1 Bus: primary=40, secondary=42, subordinate=42, sec-latency=0 I/O behind bridge: 00003000-00003fff [size=4K] Memory behind bridge: 9d000000-9e0fffff [size=17M] Prefetchable memory behind bridge: 0000000080000000-0000000091ffffff [size=288M] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 53 14 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 40 42 42 00 31 31 00 20 20: 00 9d 00 9e 01 80 f1 91 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 1a 00 40:02.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] Flags: fast devsel, NUMA node 1 00: 22 10 52 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40:03.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] Flags: fast devsel, NUMA node 1 00: 22 10 52 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40:04.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] Flags: fast devsel, NUMA node 1 00: 22 10 52 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40:07.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] Flags: fast devsel, NUMA node 1 00: 22 10 52 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40:07.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Internal PCIe GPP Bridge 0 to Bus B [1022:1454] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 42, NUMA node 1 Bus: primary=40, secondary=43, subordinate=43, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: 9e200000-9e4fffff [size=3M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 54 14 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 40 43 43 00 f1 01 00 00 20: 20 9e 40 9e f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 12 00 40:08.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-1fh) PCIe Dummy Host Bridge [1022:1452] Flags: fast devsel, NUMA node 1 00: 22 10 52 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40:08.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Internal PCIe GPP Bridge 0 to Bus B [1022:1454] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 44, NUMA node 1 Bus: primary=40, secondary=44, subordinate=44, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: 9e500000-9e5fffff [size=1M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 54 14 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 40 44 44 00 f1 01 00 00 20: 50 9e 50 9e f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 12 00 41:00.0 Non-Volatile memory controller [0108]: Samsung Electronics Co Ltd NVMe SSD Controller SM981/PM981/PM983 [144d:a808] (prog-if 02 [NVM Express]) Subsystem: Samsung Electronics Co Ltd SSD 970 EVO Plus 1TB [144d:a801] Flags: bus master, fast devsel, latency 0, IRQ 45, NUMA node 1 Memory at 9e600000 (64-bit, non-prefetchable) [size=16K] Capabilities: <access denied> Kernel driver in use: nvme Kernel modules: nvme 00: 4d 14 08 a8 06 04 10 00 00 02 08 01 10 00 00 00 10: 04 00 60 9e 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 4d 14 01 a8 30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 01 00 00 42:00.0 VGA compatible controller [0300]: NVIDIA Corporation GP104 [GeForce GTX 1070] [10de:1b81] (rev a1) (prog-if 00 [VGA controller]) Subsystem: Micro-Star International Co., Ltd. [MSI] GP104 [GeForce GTX 1070] [1462:3304] Flags: bus master, fast devsel, latency 0, IRQ 140, NUMA node 1 Memory at 9d000000 (32-bit, non-prefetchable) [size=16M] Memory at 80000000 (64-bit, prefetchable) [size=256M] Memory at 90000000 (64-bit, prefetchable) [size=32M] I/O ports at 3000 [size=128] Expansion ROM at 000c0000 [virtual] [disabled] [size=128K] Capabilities: <access denied> Kernel driver in use: nvidia Kernel modules: nvidiafb, nouveau, nvidia_drm, nvidia 00: de 10 81 1b 07 04 10 00 a1 00 00 03 00 00 80 00 10: 00 00 00 9d 0c 00 00 80 00 00 00 00 0c 00 00 90 20: 00 00 00 00 01 30 00 00 00 00 00 00 62 14 04 33 30: 00 00 00 00 60 00 00 00 00 00 00 00 0b 01 00 00 42:00.1 Audio device [0403]: NVIDIA Corporation GP104 High Definition Audio Controller [10de:10f0] (rev a1) Subsystem: Micro-Star International Co., Ltd. [MSI] GP104 High Definition Audio Controller [1462:3304] Flags: bus master, fast devsel, latency 0, IRQ 139, NUMA node 1 Memory at 9e080000 (32-bit, non-prefetchable) [size=16K] Capabilities: <access denied> Kernel driver in use: snd_hda_intel Kernel modules: snd_hda_intel 00: de 10 f0 10 06 00 10 00 a1 00 03 04 10 00 80 00 10: 00 00 08 9e 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 62 14 04 33 30: 00 00 00 00 60 00 00 00 00 00 00 00 0a 02 00 00 43:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Zeppelin/Raven/Raven2 PCIe Dummy Function [1022:145a] Subsystem: Advanced Micro Devices, Inc. [AMD] Zeppelin/Raven/Raven2 PCIe Dummy Function [1022:145a] Flags: fast devsel, NUMA node 1 Capabilities: <access denied> 00: 22 10 5a 14 00 00 10 00 00 00 00 13 10 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 5a 14 30: 00 00 00 00 48 00 00 00 00 00 00 00 ff 00 00 00 43:00.2 Encryption controller [1080]: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Platform Security Processor [1022:1456] Subsystem: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 00h-0fh) Platform Security Processor [1022:1456] Flags: bus master, fast devsel, latency 0, IRQ 133, NUMA node 1 Memory at 9e300000 (32-bit, non-prefetchable) [size=1M] Memory at 9e400000 (32-bit, non-prefetchable) [size=8K] Capabilities: <access denied> Kernel driver in use: ccp Kernel modules: ccp 00: 22 10 56 14 06 04 10 00 00 00 80 10 10 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 30 9e 00 00 00 00 20: 00 00 00 00 00 00 40 9e 00 00 00 00 22 10 56 14 30: 00 00 00 00 48 00 00 00 00 00 00 00 0a 02 00 00 43:00.3 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] Zeppelin USB 3.0 Host controller [1022:145f] (prog-if 30 [XHCI]) Subsystem: Advanced Micro Devices, Inc. [AMD] Zeppelin USB 3.0 Host controller [1022:145c] Flags: bus master, fast devsel, latency 0, IRQ 116, NUMA node 1 Memory at 9e200000 (64-bit, non-prefetchable) [size=1M] Capabilities: <access denied> Kernel driver in use: xhci_hcd Kernel modules: xhci_pci 00: 22 10 5f 14 07 04 10 00 00 30 03 0c 10 00 80 00 10: 04 00 20 9e 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 5c 14 30: 00 00 00 00 48 00 00 00 00 00 00 00 05 03 00 00 44:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Zeppelin/Renoir PCIe Dummy Function [1022:1455] Subsystem: Advanced Micro Devices, Inc. [AMD] Zeppelin/Renoir PCIe Dummy Function [1022:1455] Flags: fast devsel, NUMA node 1 Capabilities: <access denied> 00: 22 10 55 14 00 00 10 00 00 00 00 13 10 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 55 14 30: 00 00 00 00 48 00 00 00 00 00 00 00 ff 00 00 00 44:00.2 SATA controller [0106]: Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI mode] [1022:7901] (rev 51) (prog-if 01 [AHCI 1.0]) Subsystem: ASRock Incorporation FCH SATA Controller [AHCI mode] [1849:ffff] Flags: bus master, fast devsel, latency 0, IRQ 113, NUMA node 1 Memory at 9e500000 (32-bit, non-prefetchable) [size=4K] Capabilities: <access denied> Kernel driver in use: ahci Kernel modules: ahci 00: 22 10 01 79 07 04 10 00 51 01 06 01 10 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 50 9e 00 00 00 00 49 18 ff ff 30: 00 00 00 00 48 00 00 00 00 00 00 00 05 02 00 00 hopefully this flashing device can be supported. Greets

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One Build System Working Group
by Thomas Heijligen 22 Jun '22

22 Jun '22

Hi folks, we want to meet again to discuss the progress and problems under the One Build Sytem Topic. If you are interested, please participate on the poll [0] to find a suitable date. On Gerrit, relevant patches can be found under the `one_build_system` topic. [1] The working document can be found on Google Docs [3] and gets also posted in plain text to the mailing list after the meeting. -- Thomas [0] https://terminplaner4.dfn.de/Eha1mJJ8jS2z2dkw [1] https://review.coreboot.org/q/project:flashrom+topic:one_build_system [3] https://docs.google.com/document/d/1TVso_VbrLEbGc7BNrYxqlrP8jMxB23TuMqEI3Pn…

1 3

Flashrom failure
by Peter 21 Jun '22

21 Jun '22

Please refer attached, chip is Winbond 25Q80BVNIG

1 0

flashrom dev meeting notes 16.06.22
by Felix Singer 16 Jun '22

16 Jun '22

# 16th June 2022, 6:00 - 7:00 UTC+0 Attendees: Nikolai, Evan, Felix, Anastasia, Nico, Edward ## Decisions Summary * We want a maintainers file as coreboot has one. Felix will take care of adding one and hooking it up to Gerrit so that the magic happens. * Active members of the community need to take care of other people's patches/discussions and if something goes wrong, help. For example, join a discussion on Gerrit and try to help to calm down people; bring people to talk in-person (for example on the meeting) instead of texting; ask each other if everything is okay with a patch/feature etc. Take care of each other. ## Agenda * [FelixS] Reusing coreboot’s maintainer [file](https://github.com/coreboot/coreboot/blob/master/MAINTAINERS) mechanism for flashrom hooked up with the following [script](https://github.com/coreboot/coreboot/blob/51f3b3225504707ce6df81b12… ). * I think it would be great if we could add a maintainers file, like coreboot has one, where people can be assigned to specific files or folders, and hook this file up to Gerrit so that maintainers are notified. * Edward +1 for driver owners. * aklm +1 especially for new people. * AI Felix to create a patch to introduce the MAINTAINER file and aklm to review to get this idea going. * [Edward] How do we get the community to adopt the [https://flashrom.org/Friendliness](https://flashrom.org/Friendliness) policy for real? * Examples of violations are snide remarks of code reviews to poor grammar (non-native speaker), dissecting peoples speech and building up encyclopedias of text of authors motivations instead of straight to the point actionable items. * This *must* end! * How are remediation dealt with? * How are violations considered and what is the result of a violation? * Who (more than one person hopefully) is responsible for enforcement? * Maybe find a group of people outside of the flashrom community who could help with this? It seems like this is an issue that many groups struggle with. Maybe we can look at creating a group of people from various open source projects that can look objectively at any issues and make some decisions about how to deal with problems. Whether the projects want to accept and implement those decisions would be up to the individual project. My fear is that the flashrom project is too small to police these issues objectively. * [aklm] just for completeness: existing rules on the Friendliness page say the following: * “If you feel like you have been treated in an unfair way, we want to hear about it so we can fix it. Our arbitration committee (Carl-Daniel Hailfinger <email> and Stefan Reinauer <email>) can be contacted directly and will listen to you. If you don't get a response within a few days, your mail was probably lost. Feel free to resend your mail to another member of the arbitration committee in that case.” * Is this still up-to-date? Does this strategy work? * If code review goes bad , maybe pause for a moment . Maybe try to get a conversation in person? * Bring up very concerning issues in GVC. * It’s hard to admit fault or in trouble. * Take care of others to allow people to say they are in trouble. * If someone notices a discussion is going off the rails that person should be afforded the chance to try and help bring things back to the topic. * What to do (for active members of community) * First starting with the person is ok before deep diving into the technical issue that went off the rails. * Add yourself to the patch and comment on the patch, trying to extract relevant ideas * If a person is on the meeting , you can ask them if everything is alright with the patch/feature * Reach out to person by email , or private chat * Bring people to the meeting? * For new people: ask what they are trying to achieve? What are you trying to do? * Two separate patches should be considered independent. * Actively try to determine the point where things got misunderstood and try to refocus the discussion back to a simpler point to realign to make progress. * Less is more, simple points to bring things back to focus and help build bridges. * What can a person do who feels in trouble? * [aklm] I created a category in bugtracker “Easy Projects” so that we can have a collection of easy tasks (for example for new people). This may be easier to keep alive than [https://www.flashrom.org/Easy_projects](https://www.flashrom.org/Easy_proje… * Thanks!

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GSOC Project Thread - Optimising Erase Function Selection
by Aarya Chaumal 16 Jun '22

16 Jun '22

Hi, Today I had my first meet with my mentors Thomas and Simon, and we discussed a few things involving the timeline and initial tasks for the project. There are mainly two parts to the project : 1. Developing a strategy to optimize the selection of the erase function to reduce the overall time required to do the operation 2. Filtering out the erase functions that the programmer does not support For now, I'm working on the first one. Also, I will be writing a test case to check whether the erase functions in the flashchips struct are sorted according to the block size. Aarya

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SMBus revision 0x61 (AMD FP4) unknown
by Adrien Dessemond 16 Jun '22

16 Jun '22

Hello, Flashrom reports an unsupported chipset. See below and the attached file for a lspci report. Motherboard is an ASRock Taichi x370 with a AMD 5900X processor. # flashrom --programmer internal flashrom v1.2 on Linux 5.17.14-gentoo-x86_64 (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Found chipset "AMD FP4". Enabling flash write... FCH device found but SMBus revision 0x61 does not match known values. Please report this to flashrom(a)flashrom.org and include this log and the output of lspci -nnvx, thanks!. Could not determine chipset generation.PROBLEMS, continuing anyway No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. Best regards, -- Adrien Dessemond

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(no subject)
by Eduardo Ferro 16 Jun '22

16 Jun '22

Hello, I would like to know if flashrom returns some value in percentage while writing or reading the file. I thank the attention Regards, Eduardo Ferro.

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Updated invitation: Flashrom Dev Meeting (monthly) @ Thu 16 Jun 2022 16:00 - 17:00 (AEST) (flashrom@flashrom.org)
by evanbenn＠google.com 16 Jun '22

16 Jun '22

This event has been changed. Title: Flashrom Dev Meeting (monthly) Monthly meeting of Flashrom project developers. Meeting notes doc: https://docs.google.com/document/d/18qKvEbfPszjsJJGJhwi8kRVDUG3GZ… When: Thu 16 Jun 2022 16:00 – 17:00 Eastern Australia Time - Sydney Where: AU-SYD-ODI-3-Lothlorien (7) [GVC] (changed) Joining info: Join with Google Meet https://meet.google.com/iuf-mtri-zva?hs=224 Join by phone (AU) +61 2 9051 6791 (PIN: 304642402) More phone numbers: https://tel.meet/iuf-mtri-zva?pin=9271993818880&hs=0 Calendar: flashrom(a)flashrom.org Who: * aklm(a)chromium.org- creator * felix.singer12(a)gmail.com * david.hendricks(a)gmail.com * quasisec(a)google.com * nico.h(a)gmx.de * Martin Roth * src(a)posteo.de * martonmiklosqdev(a)gmail.com * piotr.krol(a)3mdeb.com * Maciej Pijanowski * michal.zygowski(a)3mdeb.com * th3fanbus(a)gmail.com * stefan.k.reinauer(a)gmail.com * nartemiev(a)google.com * arthur(a)aheymans.xyz * evanbenn(a)google.com * flashrom(a)flashrom.org * c-d.hailfinger.devel.2006(a)gmx.net Event details: https://calendar.google.com/calendar/event?action=VIEW&eid=MmVscGY2cjNsdTZw… Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this courtesy email at the account flashrom(a)flashrom.org because you are an attendee of this event. To stop receiving future updates for this event, decline this event. Alternatively, you can sign up for a Google Account at https://calendar.google.com/calendar/ and control your notification settings for your entire calendar. Forwarding this invitation could allow any recipient to send a response to the organiser and be added to the guest list, invite others regardless of their own invitation status or to modify your RSVP. Learn more at https://support.google.com/calendar/answer/37135#forwarding

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Updated invitation: Flashrom Dev Meeting (monthly) @ Every 2 weeks from 4pm to 5pm on Thursday (AEST) (flashrom@flashrom.org)
by aklm＠chromium.org 16 Jun '22

16 Jun '22

This event has been changed. Title: Flashrom Dev Meeting (monthly) Monthly meeting of Flashrom project developers. Meeting notes doc: https://docs.google.com/document/d/18qKvEbfPszjsJJGJhwi8kRVDUG3GZ… When: Every 2 weeks from 4pm to 5pm on Thursday Eastern Australia Time - Sydney Joining info: Join with Google Meet https://meet.google.com/iuf-mtri-zva?hs=224 Join by phone (AU) +61 2 9051 6791 (PIN: 304642402) More phone numbers: https://tel.meet/iuf-mtri-zva?pin=9271993818880&hs=0 Calendar: flashrom(a)flashrom.org Who: * aklm(a)chromium.org - creator * felix.singer12(a)gmail.com * david.hendricks(a)gmail.com * quasisec(a)google.com * nico.h(a)gmx.de * Martin Roth * src(a)posteo.de * martonmiklosqdev(a)gmail.com * piotr.krol(a)3mdeb.com * Maciej Pijanowski * michal.zygowski(a)3mdeb.com * th3fanbus(a)gmail.com * stefan.k.reinauer(a)gmail.com * nartemiev(a)google.com * arthur(a)aheymans.xyz * flashrom(a)flashrom.org * c-d.hailfinger.devel.2006(a)gmx.net * evanbenn(a)google.com Event details: https://calendar.google.com/calendar/event?action=VIEW&eid=MmVscGY2cjNsdTZw… Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this courtesy email at the account flashrom(a)flashrom.org because you are an attendee of this event. To stop receiving future updates for this event, decline this event. Alternatively you can sign up for a Google account at https://calendar.google.com/calendar/ and control your notification settings for your entire calendar. Forwarding this invitation could allow any recipient to send a response to the organizer and be added to the guest list, or invite others regardless of their own invitation status, or to modify your RSVP. Learn more at https://support.google.com/calendar/answer/37135#forwarding

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Updated invitation: Flashrom Dev Meeting (monthly) @ Every 2 weeks from 4pm to 5pm on Thursday from Thu May 5 to Wed Jun 15 (AEST) (flashrom@flashrom.org)
by aklm＠chromium.org 16 Jun '22

16 Jun '22

This event has been changed. Title: Flashrom Dev Meeting (monthly) Monthly meeting of Flashrom project developers. Meeting notes doc: https://docs.google.com/document/d/18qKvEbfPszjsJJGJhwi8kRVDUG3GZ… When: Every 2 weeks from 4pm to 5pm on Thursday from Thu May 5 to Wed Jun 15 Eastern Australia Time - Sydney (changed) Joining info: Join with Google Meet https://meet.google.com/iuf-mtri-zva?hs=224 Join by phone (AU) +61 2 9051 6791 (PIN: 304642402) More phone numbers: https://tel.meet/iuf-mtri-zva?pin=9271993818880&hs=0 Calendar: flashrom(a)flashrom.org Who: * aklm(a)chromium.org - creator * felix.singer12(a)gmail.com * david.hendricks(a)gmail.com * quasisec(a)google.com * nico.h(a)gmx.de * Martin Roth * src(a)posteo.de * martonmiklosqdev(a)gmail.com * piotr.krol(a)3mdeb.com * Maciej Pijanowski * michal.zygowski(a)3mdeb.com * th3fanbus(a)gmail.com * stefan.k.reinauer(a)gmail.com * nartemiev(a)google.com * arthur(a)aheymans.xyz * flashrom(a)flashrom.org * c-d.hailfinger.devel.2006(a)gmx.net Event details: https://calendar.google.com/calendar/event?action=VIEW&eid=MmVscGY2cjNsdTZw… Invitation from Google Calendar: https://calendar.google.com/calendar/ You are receiving this courtesy email at the account flashrom(a)flashrom.org because you are an attendee of this event. To stop receiving future updates for this event, decline this event. Alternatively you can sign up for a Google account at https://calendar.google.com/calendar/ and control your notification settings for your entire calendar. Forwarding this invitation could allow any recipient to send a response to the organizer and be added to the guest list, or invite others regardless of their own invitation status, or to modify your RSVP. Learn more at https://support.google.com/calendar/answer/37135#forwarding

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FlashRom error report
by 이준기 15 Jun '22

15 Jun '22

Hello. I'm Junki Lee and I'm using a translator, so please understand. I used flashrom on my laptop and it gave me an error. ubuntu@ubuntu:~/Documents$ sudo flashrom --programmer ch341a_spi -w X5BF.B08 -c MX25L6406E/MX25L6408E flashrom v1.2 on Linux 5.13.0-30-generic (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Found Macronix flash chip "MX25L6406E/MX25L6408E" (8192 kB, SPI) on ch341a_spi. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... FAILED at 0x0004801f! Expected=0x32, Found=0x22, failed byte count from 0x00000000-0x007fffff: 0x3c5a Your flash chip is in an unknown state. Please report this on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org, thanks! The model name of the laptop is Aorus X5.(https://www.gigabyte.com/Laptop/X5) CH341A was used as equipment. The name of the EEPROM is MX25L6406E from Macronix. The rom file used was downloaded from the link above. I've used flashrom several times, but the error was almost the same. It was always the same up to the failed byte 0x007fffff part, only the hexadecimal number after it was slightly different. I also tried CH341A programmer and AsProgrammer. Tried with multiple versions, same error as above. The delete worked fine, but the write operation always throws an error. My laptop is bricked. Can you help me?

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flashrom for windows build/download
by JOHN WESTMORELAND 14 Jun '22

14 Jun '22

Hello, I was wondering if someone could point me in the right direction to find prebuilt binaries for windows. Thanks In Advance, John W.

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Refactor arguments parser - GSOC project thread
by Chinmay Lonkar 10 Jun '22

10 Jun '22

Hello, Today I had a meeting with my mentors Felix and Anastasia. The project plan has been broken into phases. I'll work on the first phase, which will entail creating an alternative to extract_programmer_param() that will parse the programmer's sub-arguments according to the data type in which they have to be utilized in the code. So, I'll be reading through the code and working out a solution for this task, as well as analyzing all of the other parameters that the programmers utilize. Regards, Chinmay Lonkar

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Verify problem with W25Q256JVEQ
by Mathieu Othacehe 08 Jun '22

08 Jun '22

Hello, I am trying to flash a Winbond 25Q256JVEQ with a dediprog programmer. The W25Q256JVEQ flash is put in a WSON8 socket. The socket pins are directly wired to the dediprog. The chip is detected and can be erased. However, the verification always fail this way: --8<---------------cut here---------------start------------->8--- Found Winbond flash chip "W25Q256.V" (32768 kB, SPI) on dediprog. Chip status register is 0x00. ... Found Winbond flash chip "W25Q256.V" (32768 kB, SPI). This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:EW Erase/write done. Verifying flash... FAILED at 0x00000000! Expected=0x71, Found=0xff, failed byte count from 0x00000000-0x01ffffff: 0x268 Your flash chip is in an unknown state. --8<---------------cut here---------------end--------------->8--- I tried to add a 0.1uF decoupling resistor on VCC as well as pull-ups on CS, WP and HOLD pins and pull down on CLK as proposed in the "Winbond SPI NOR Flash Device APPLICATION NOTE", without any progress. I tried several W25Q256JVEQ flash memories and always observed the same behaviour. Any idea what could be wrong? Thanks, Mathieu

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Good Afternoon, ( Bios Help )
by RED-LAB ? 03 Jun '22

03 Jun '22

Good Afternoon, Can You Guys Help Me I Have A Virus In My Bios My is Computer Booting and executing a code inside computer dell precision t5500 dual xeon my tel 954-305-1626 david

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flashrom dev meeting notes 2.06.22
by Felix Singer 03 Jun '22

03 Jun '22

# 2nd June 2022, 6:00 - 7:00 am UTC+0 Attendees: Felix Singer, Chinmay Lonkar, Edward O’Callaghan, Joursoir, Anastasia Klimchuk, Nikolai Artemiev, Evan Benn, Aarya Chaumal, Thomas Heijligen, Arthur Heymans ## Decisions Summary * We want to look into git hooks and build bot scripts which check the code style for compliance. Discussion thread will be opened on the mailing list. * We want to renew the flashrom website and we will look into static site generators. Discussion thread will be opened on the mailing list. ## Agenda * [aklm] Welcome our students! * Aarya * Chinmay * Joursoir * [aklm] We have people from 3 software companies here, and also independent developers. This makes 4 parties, each one is using flashrom in their own ways, each one has some critical use cases. Can we talk and describe to each other how we use flashrom, what are critical use cases (unless it’s confidential)? My main goal is that we have more understanding (and maybe more patience) of each other’s work. * Servers: LinuxBoot, e.g. for updating CrOS-style `vpd` variables. This usually necessitates static binaries which are currently quite large (>1MB). Short of re-writing relevant bits of Flashrom (e.g. in Go), is there a good way to shrink the flashrom binary size? Some users are compiling with musl, for example: [https://github.com/flashrom/flashrom/pull/155](https://github.com/flashrom/… * How to make binary smaller * [quasisec] * Convert flash chips. C into parseable database * Make more parts of flashrom as re-usable units - i.e., modularity, remove globals etc. * Reduce binary size via build system changes * Removing globals plays into this, it adds more modularity * Edward: Chrome OS uses flashrom to update EC and AP. There are few other components that are updated with flashrom. We go through the internal path. Main programmers are ichspi, sb600spi, linux_mtd. * Thomas: (from Simon) Making things with FPGA , nothing to do with coreboot. Completely writing the whole flash chips. * Flashrom is Swiss army knife * Thomas (Secunet) : Development of coreboot, external programmer to read/write chip. Internal programmer for spi. libflashrom on the payload base. * [FelixS] coreboot uses a git-hook to run clang-format stylecheck. Should we use it too? * [https://review.coreboot.org/c/flashrom/+/43602](https://review.coreboot.org… * The script aborts the creation of a commit if the changed code doesn’t comply with the style guidelines. * We need to add make target * Is the check-style script blocking? What if false-positives appear? * Maybe another target on the build bot? Comments are added into Gerrit patch. * Script will run on git commit, locally * Arthur: I tried to make coreboot tree consistent, but clang choked on this, had a runtime. ~1 month ago I was trying this. * Thomas : data structures can be hard to format, like flashchip.c * We can put exceptions in the tool, so that formatting is not touched. * Arthur: We can just try, have a play with it and maybe it works in the tree? * It is hard to configure for parts of file, usually whole file or nothing. * First step can be a page on the build bot, which is not blocking. Second step adding comments to gerrit. * The patch will install a hook with make, meson is not adding a hook at the moment. * TODO start a topic on the mailing list * [FelixS] Should we use a tool for code formatting? * uncrustify: [https://review.coreboot.org/c/flashrom/+/42556](https://review.coreboot.org… * clang-format: [https://review.coreboot.org/c/flashrom/+/38673](https://review.coreboot.org… * Arthur: Uncrisfity works on coreboot * quasisec@: I one word: Yes. * quasisec@: Actually we can go beyond syntax checking and perhaps add: * Scan-build as a buildbot target to check for possible bugs (overflows etc) * Also coccinelle semantic patching for common bad or good patterns that should be applied. https://www.kernel.org/doc/html/v4.14/dev-tools/coccinelle.html * [FelixS] Should we rework / rebuild / modernize the flashrom.org website? * The flashrom website looks like a site from the early 2000’s. That’s not very attractive for potential interested people. The site should be replaced with something which looks modern. * quasisec@ needs more shiny! :D * Static site generators are easy to manage, they reduce maintenance burden (e.g. less or no updates) and also the risk for server-side security issues. * quasisec@ +1, also easy for the community to check in changes under review. All just markdown. * FelixS: More democratic to make changes for the wider community. * quasisec@ suggestions: * [https://www.getzola.org/](https://www.getzola.org/) also, * [https://jaspervdj.be/hakyll/](https://jaspervdj.be/hakyll/) is fantastic. * Check out [https://jamstack.org/generators/](https://jamstack.org/generators/) * Furthermore, it makes hooking up Doxygen code documentation generation trivial. * We have to find out what we need and which framework supports what. Then, various frameworks need to be evaluated and we need a plan on how to migrate to the new site. * [aklm] how do we build a knowledge base for users? Ideally such that users can update content themselves? * TODO start thread on mailing list * aklm: Wiki has 33 users, but wiki is rarely updated * Chinmay: There is a tool docsify. Lots of themes, or you can make your own theme. I can show an example? Yes! * Thomas: we need to make a list of requirements * There is some C code which generates wiki markdown with the list of chips. It needs to be run manually. It can be run on buildbot. * Mediawiki edit page says “Please note that all contributions to flashrom may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here. You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see [flashrom:Copyrights](https://www.flashrom.org/index.php?title=flashrom:Copy… ) for details). Do not submit copyrighted work without permission!”

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Spansion S25FL128L readout
by Hilco de Lathouder 31 May '22

31 May '22

Hi All, I have a Spansion chip I want to read but it seems not supported by flashrom. I can connect and read JEDEC ID with BusPirate: it says 01-60-18 which corresponds with the Spansion S25FL128L (specs available online). Flashrom does not detect it. I tried reading it while forcing any of the other 128Mbit Spansion chips, but could not make anything of the rom with Binwalk. What would be the best strategy to get to the contents of this chip? Thanks in advance, Hilco

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Decision making process
by Anastasia Klimchuk 30 May '22

30 May '22

Hello People, The topic initially came up in the “Gatekeeping” thread. However it was suggested that it should be a separate thread, which makes sense so I am starting one. So, straight to the point: it looks like we have a decision making process emerging! (below). What do people think about it? #1 Discuss things on the mailing list first. It could be ongoing for months - so that everyone who is interested has time to read and respond. However, it doesn’t have to be for months. #2 When/if the discussion seems to be settled and people are in agreement, the item can be added to the agenda of the meeting. #3 At the meeting the item can be discussed again, and a decision can be made (or not made, if people disagree). #4 After the meeting we send an email with meeting notes and “Decisions summary” on the top of the email. #5 Since stuff never gets done immediately, there always be some time to react on #4 If someone has objections/concerns, it would be great if you can propose improvements or alternative solutions. Please don’t just say “this is all wrong!” Many thanks for sharing your thoughts! -- Anastasia.

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Request for clarification on "per-region file arguments" issue
by Daniel Campello 25 May '22

25 May '22

Hello, I decided to take a look at https://ticket.coreboot.org/issues/372 and I would like to get a better understanding of what is being requested on the issue tracker. I took a look at the submitted patch (comments and code diff) and everything seems in order to me. I appreciate any assistance you can provide, Regards, Daniel Campello

3 2

new chip - GD25LR256E
by Igor Omelchenko 24 May '22

24 May '22

Hello guys, trying to add a new chip GigaDevices into flashchips.c, without success. Can someone help me to add it. Thanks. trying something like this: { .vendor = "GigaDevice", .name = "GD25LR256E", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, .model_id = GIGADEVICE_GD25LR256E, .total_size = 32768, .page_size = 256, /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { .eraseblocks = { {4 * 1024, 8192} }, .block_erase = spi_block_erase_20, }, { .eraseblocks = { {32 * 1024, 1024} }, .block_erase = spi_block_erase_52, }, { .eraseblocks = { {64 * 1024, 512} }, .block_erase = spi_block_erase_d8, }, { .eraseblocks = { {32 * 1024 * 1024, 1} }, .block_erase = spi_block_erase_60, }, { .eraseblocks = { {32 * 1024 * 1024, 1} }, .block_erase = spi_block_erase_c7, } }, .printlock = spi_prettyprint_status_register_bp4_srwd, .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1695, 1950},} -- *Omelchenko Igor* *0543-066-855*

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Any users of the flashrom_*_info querying functions in libflashrom API?
by Nico Huber 24 May '22

24 May '22

Hi folks, for a while now, we have some functions in the libflashrom API to query information about supported devices and such. The original patch[1] left some questions open. And, alas, as there was some broken code and no feedback, parts of it were dropped. So, I wonder if there are any users of this API already? Anything that might break if we change it? Why I'm picking this up is that there are some issues with the design. For instance, the exposed structs form an ABI that might need versioning if somebody wants to link a shared library. And the cleanup part of the API is too simple, i.e. flashrom_data_free() doesn't allow anything but a shallow free(). There's also an associated ticket[2]. Nico [1] https://review.coreboot.org/c/flashrom/+/34363 [2] https://ticket.coreboot.org/issues/355

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