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[PATCH 2/5] Move check_chip_supported() to cli_classic.c.
by Stefan Tauner 09 Jun '14

09 Jun '14

This function clearly belongs to the command line interface and should therefore reside in cli_classic.c and not in flashrom.c. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- cli_classic.c | 67 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ flashrom.c | 67 ----------------------------------------------------------- programmer.h | 1 - 3 files changed, 67 insertions(+), 68 deletions(-) diff --git a/cli_classic.c b/cli_classic.c index fc1b9ba..54b0d07 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -89,6 +89,73 @@ static int check_filename(char *filename, char *type) return 0; } +static void check_chip_supported(const struct flashchip *chip) +{ + if (chip->feature_bits & FEATURE_OTP) { + msg_cdbg("This chip may contain one-time programmable memory. " + "flashrom cannot read\nand may never be able to write " + "it, hence it may not be able to completely\n" + "clone the contents of this chip (see man page for " + "details).\n"); + } + + if ((chip->tested.erase == NA) && (chip->tested.write == NA)) { + msg_cdbg("This chip's main memory can not be erased/written by design.\n"); + } + + if ((chip->tested.probe == BAD) || (chip->tested.probe == NT) || + (chip->tested.read == BAD) || (chip->tested.read == NT) || + (chip->tested.erase == BAD) || (chip->tested.erase == NT) || + (chip->tested.write == BAD) || (chip->tested.write == NT)){ + msg_cinfo("===\n"); + if ((chip->tested.probe == BAD) || + (chip->tested.read == BAD) || + (chip->tested.erase == BAD) || + (chip->tested.write == BAD)) { + msg_cinfo("This flash part has status NOT WORKING for operations:"); + if (chip->tested.probe == BAD) + msg_cinfo(" PROBE"); + if (chip->tested.read == BAD) + msg_cinfo(" READ"); + if (chip->tested.erase == BAD) + msg_cinfo(" ERASE"); + if (chip->tested.write == BAD) + msg_cinfo(" WRITE"); + msg_cinfo("\n"); + } + if ((chip->tested.probe == NT) || + (chip->tested.read == NT) || + (chip->tested.erase == NT) || + (chip->tested.write == NT)) { + msg_cinfo("This flash part has status UNTESTED for operations:"); + if (chip->tested.probe == NT) + msg_cinfo(" PROBE"); + if (chip->tested.read == NT) + msg_cinfo(" READ"); + if (chip->tested.erase == NT) + msg_cinfo(" ERASE"); + if (chip->tested.write == NT) + msg_cinfo(" WRITE"); + msg_cinfo("\n"); + } + /* FIXME: This message is designed towards CLI users. */ + msg_cinfo("The test status of this chip may have been updated " + "in the latest development\n" + "version of flashrom. If you are running the latest " + "development version,\n" + "please email a report to flashrom(a)flashrom.org if " + "any of the above operations\n" + "work correctly for you with this flash part. Please " + "include the flashrom\n" + "output with the additional -V option for all " + "operations you tested (-V, -Vr,\n" + "-VE, -Vw), and mention which mainboard or " + "programmer you tested.\n" + "Please mention your board in the subject line. " + "Thanks for your help!\n"); + } +} + int main(int argc, char *argv[]) { unsigned long size; diff --git a/flashrom.c b/flashrom.c index a8a8533..f8978f1 100644 --- a/flashrom.c +++ b/flashrom.c @@ -1798,73 +1798,6 @@ int selfcheck(void) return ret; } -void check_chip_supported(const struct flashchip *chip) -{ - if (chip->feature_bits & FEATURE_OTP) { - msg_cdbg("This chip may contain one-time programmable memory. " - "flashrom cannot read\nand may never be able to write " - "it, hence it may not be able to completely\n" - "clone the contents of this chip (see man page for " - "details).\n"); - } - - if ((chip->tested.erase == NA) && (chip->tested.write == NA)) { - msg_cdbg("This chip's main memory can not be erased/written by design.\n"); - } - - if ((chip->tested.probe == BAD) || (chip->tested.probe == NT) || - (chip->tested.read == BAD) || (chip->tested.read == NT) || - (chip->tested.erase == BAD) || (chip->tested.erase == NT) || - (chip->tested.write == BAD) || (chip->tested.write == NT)){ - msg_cinfo("===\n"); - if ((chip->tested.probe == BAD) || - (chip->tested.read == BAD) || - (chip->tested.erase == BAD) || - (chip->tested.write == BAD)) { - msg_cinfo("This flash part has status NOT WORKING for operations:"); - if (chip->tested.probe == BAD) - msg_cinfo(" PROBE"); - if (chip->tested.read == BAD) - msg_cinfo(" READ"); - if (chip->tested.erase == BAD) - msg_cinfo(" ERASE"); - if (chip->tested.write == BAD) - msg_cinfo(" WRITE"); - msg_cinfo("\n"); - } - if ((chip->tested.probe == NT) || - (chip->tested.read == NT) || - (chip->tested.erase == NT) || - (chip->tested.write == NT)) { - msg_cinfo("This flash part has status UNTESTED for operations:"); - if (chip->tested.probe == NT) - msg_cinfo(" PROBE"); - if (chip->tested.read == NT) - msg_cinfo(" READ"); - if (chip->tested.erase == NT) - msg_cinfo(" ERASE"); - if (chip->tested.write == NT) - msg_cinfo(" WRITE"); - msg_cinfo("\n"); - } - /* FIXME: This message is designed towards CLI users. */ - msg_cinfo("The test status of this chip may have been updated " - "in the latest development\n" - "version of flashrom. If you are running the latest " - "development version,\n" - "please email a report to flashrom(a)flashrom.org if " - "any of the above operations\n" - "work correctly for you with this flash part. Please " - "include the flashrom\n" - "output with the additional -V option for all " - "operations you tested (-V, -Vr,\n" - "-VE, -Vw), and mention which mainboard or " - "programmer you tested.\n" - "Please mention your board in the subject line. " - "Thanks for your help!\n"); - } -} - /* FIXME: This function signature needs to be improved once doit() has a better * function signature. */ diff --git a/programmer.h b/programmer.h index d299656..867eee9 100644 --- a/programmer.h +++ b/programmer.h @@ -503,7 +503,6 @@ struct decode_sizes { extern struct decode_sizes max_rom_decode; extern int programmer_may_write; extern unsigned long flashbase; -void check_chip_supported(const struct flashchip *chip); int check_max_decode(enum chipbustype buses, uint32_t size); char *extract_programmer_param(const char *param_name); -- Kind regards, Stefan Tauner

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[PATCH 1/5] Fix FWH IDSEL message printing.
by Stefan Tauner 09 Jun '14

09 Jun '14

Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- chipset_enable.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index 40761d2..46cc79c 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -404,7 +404,7 @@ static int enable_flash_ich_fwh_decode(struct pci_dev *dev, enum ich_chipset ich uint64_t fwh_idsel_old = pci_read_long(dev, fwh_sel1); fwh_idsel_old <<= 16; fwh_idsel_old |= pci_read_word(dev, fwh_sel2); - msg_pdbg("\nSetting IDSEL from 0x%012" PRIx64 " to 0x%012" PRIx64 " for top 16 MB.", + msg_pdbg("Setting IDSEL from 0x%012" PRIx64 " to 0x%012" PRIx64 " for top 16 MB.\n", fwh_idsel_old, fwh_idsel); rpci_write_long(dev, fwh_sel1, (fwh_idsel >> 16) & 0xffffffff); rpci_write_word(dev, fwh_sel2, fwh_idsel & 0xffff); @@ -418,7 +418,7 @@ idsel_garbage_out: free(idsel); if (!implemented) { - msg_pdbg2("FWH IDSEL handling is not implemented on this chipset."); + msg_pdbg2("FWH IDSEL handling is not implemented on this chipset.\n"); return 0; } @@ -434,7 +434,7 @@ idsel_garbage_out: /* FWH_SEL1 */ for (i = 7; i >= 0; i--) { int tmp = (fwh_conf >> (i * 4)) & 0xf; - msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x", + msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n", (0x1ff8 + i) * 0x80000, (0x1ff0 + i) * 0x80000, tmp); @@ -448,7 +448,7 @@ idsel_garbage_out: fwh_conf = pci_read_word(dev, fwh_sel2); for (i = 3; i >= 0; i--) { int tmp = (fwh_conf >> (i * 4)) & 0xf; - msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x", + msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n", (0xff4 + i) * 0x100000, (0xff0 + i) * 0x100000, tmp); @@ -465,7 +465,7 @@ idsel_garbage_out: fwh_conf |= pci_read_byte(dev, fwh_dec_en_lo); for (i = 7; i >= 0; i--) { int tmp = (fwh_conf >> (i + 0x8)) & 0x1; - msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled", + msg_pdbg("0x%08x/0x%08x FWH decode %sabled\n", (0x1ff8 + i) * 0x80000, (0x1ff0 + i) * 0x80000, tmp ? "en" : "dis"); @@ -477,7 +477,7 @@ idsel_garbage_out: } for (i = 3; i >= 0; i--) { int tmp = (fwh_conf >> i) & 0x1; - msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled", + msg_pdbg("0x%08x/0x%08x FWH decode %sabled\n", (0xff4 + i) * 0x100000, (0xff0 + i) * 0x100000, tmp ? "en" : "dis"); @@ -488,7 +488,7 @@ idsel_garbage_out: } } max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode); - msg_pdbg("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh); + msg_pdbg("Maximum FWH chip size: 0x%x bytes\n", max_rom_decode.fwh); return 0; } -- Kind regards, Stefan Tauner

1 0

[PATCH 0/5] Bunch of stuff on the way to new probing
by Stefan Tauner 09 Jun '14

09 Jun '14

While I was hacking around to prepare for the probing rewrite I have found a few things that could be improved. This is the first batch of such changes that are not directly related to the probing, could easily be factored out and make sense even without the new proving IMHO. The existence and naming of helpers.c was discussed previously in the context of layout patches (in case you seem to have a deja vu ;). Stefan Tauner (5): Fix FWH IDSEL message printing. Move check_chip_supported() to cli_classic.c. Introduce helpers.c. Refine handling chips that exceed maximum programmer sizes. Reorder and cleanup feature flags. Makefile | 2 +- chipset_enable.c | 14 +++--- cli_classic.c | 83 ++++++++++++++++++++++++++++++++++-- flash.h | 19 +++++---- flashchips.c | 9 +--- flashrom.c | 127 ++++--------------------------------------------------- helpers.c | 60 ++++++++++++++++++++++++++ programmer.h | 3 +- 8 files changed, 168 insertions(+), 149 deletions(-) create mode 100644 helpers.c -- Kind regards, Stefan Tauner

1 0

report about AT25F4096
by 공준혁 07 Jun '14

07 Jun '14

2 1

Unable to flash MX25L3206E
by HyDzFR 05 Jun '14

05 Jun '14

Hi, I try to flash a mx25L3206E from macronix with flashrom 0.9.7-r1817 with a raspberry pi via spi. The chip is on the motherboard. I've disconnect Vcc from motherboard. Flashrom failed to erase the chip and say "flash chip is in an unknow state ». I launch the following command: sudo flashrom -w XXX.bin -V -p linux_spi:dev=/dev/spidev0.0 -c MX25L3206E Here is the output http://paste.flashrom.org/view.php?id=2621 Regards Hydz

2 1

Re: [flashrom] Flashrom Update Failure
by Will Choe 05 Jun '14

05 Jun '14

Resolved it by copy & modifying: else if (force && chip_to_probe) { struct registered_programmer *pgm; int compatible_programmers = 0; msg_cinfo("Force read (-f -r -c) requested, pretending the chip is there:\n"); /* This loop just counts compatible controllers. */ for (j = 0; j < registered_programmer_count; j++) { pgm = &registered_programmers[j]; /* chip is still set from the chip_to_probe earlier in this function. */ if (pgm->buses_supported & chip->bustype) compatible_programmers++; } if (!compatible_programmers) { msg_cinfo("No compatible controller found for the requested flash chip.\n"); ret = 1; goto out_shutdown; } if (compatible_programmers > 1) msg_cinfo("More than one compatible controller found for the requested flash " "chip, using the first one.\n"); for (j = 0; j < registered_programmer_count; j++) { pgm = &registered_programmers[j]; startchip = probe_flash(pgm, 0, &flashes[0], 1); if (startchip != -1) break; } msg_cinfo("Please note that forced writes most likely contain garbage.\n"); } if (startchip == -1) { ret = 1; goto out_shutdown; } to the cli_classic.c I think it's better to have 'force & force' option to do the writing. Will 2014. 6. 5., pm 5:05, Will Choe <jazzbearz(a)gmail.com> wrote: > Hi, > > Flashrom update failed due to sudden network interruption. After then, when I try the flashrom, following message appears: > > flashrom v0.9.7-r1711 on Linux 2.6.32-431.5.1.el6.x86_64 (x86_64) > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > sh: dmidecode: command not found > dmidecode execution unsuccessful - continuing without DMI info > Found chipset "Intel ICH10R". Enabling flash write... OK. > No EEPROM/flash device found. > Note: flashrom can never write if the flash chip isn't found automatically. > > How do I make the flashrom to force rewrite the rom? > > Thanks in advance. > > Will > > > >

1 0

Flashrom Update Failure
by Will Choe 05 Jun '14

05 Jun '14

Hi, Flashrom update failed due to sudden network interruption. After then, when I try the flashrom, following message appears: flashrom v0.9.7-r1711 on Linux 2.6.32-431.5.1.el6.x86_64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. sh: dmidecode: command not found dmidecode execution unsuccessful - continuing without DMI info Found chipset "Intel ICH10R". Enabling flash write... OK. No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. How do I make the flashrom to force rewrite the rom? Thanks in advance. Will

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Re: [flashrom] ft2232_spi:type=jtagkey
by Stefan Tauner 04 Jun '14

04 Jun '14

On Tue, 3 Jun 2014 19:48:12 +0700 Alfin Cahya <alfincp(a)gmail.com> wrote: > Hello Stefan, > > Thanks for your response. I have connected all the pins (CLK,DI,DO,CS) > and 3.3v to VCC, HOLD, WP. > IC type is EN25QH128A-HIP ( 4 pins ). > Try using Arduino Duemilanove (serprog:dev=/dev/ttyUSB0:2000000) > result remains the same. Then it may be one of the problems listed here: http://flashrom.org/ISP Could you please post a complete verbose log? Is the chip always detected? If you read the chip multiple times, is the content read always the same? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

Try to add support for LE25FW106/1Mbit spi flash
by The Raven 04 Jun '14

04 Jun '14

Hello, i am trying to add this chip (ID 0x62 0x15). It works so far, but erase function 1 is not working. The datasheet tells that it supports 2K small sector, 32K sector and chip erase. 2K Small Sector and chip erase works. But 32K not. And i don't know why. Please have a look: .vendor = "Sanyo", .name = "LE25FW106", .bustype = BUS_SPI, .manufacture_id = SANYO_ID, .model_id = SANYO_LE25FW106, .total_size = 128, .page_size = 256, .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_OK_PREW, .probe = probe_spi_res2, .probe_timing = TIMING_ZERO, .block_erasers = { { // .eraseblocks = { {2 * 1024, 64} }, //ok // .block_erase = spi_block_erase_d7, // }, { .eraseblocks = { {32 * 1024, 4} }, //not ok .block_erase = spi_block_erase_d8, // }, { // .eraseblocks = { {128 * 1024, 1} }, //ok // .block_erase = spi_block_erase_c7, } }, .printlock = spi_prettyprint_status_register_plain, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, I am also not sure if "FEATURE_WRSR_WREN" is correct. The code is taken from "LE25FW406A" chip and changed to fit the "LE25FW106". This is the error: Found Sanyo flash chip "LE25FW106" (128 kB, SPI). Erasing and writing flash chip... Trying erase function 0... 0x000000-0x007fff:E, 0x008000-0x00ffff:EError: invalid response 0xAF from device spi_block_erase_d8 failed during command execution at address 0x8000 Looking for another erase function. No usable erase functions left. FAILED! Attention: It tells function 0, but this is because i have removed the other functions for testing. ;-) BTW: Chips was found an a 2.5" hitachi harddisk. Chip is a "T" model (MSOP8).

2 5

[commit] r1818 - trunk
by repository service 04 Jun '14

04 Jun '14

Author: stefanct Date: Wed Jun 4 18:17:03 2014 New Revision: 1818 URL: http://flashrom.org/trac/flashrom/changeset/1818 Log: Add support for Sanyo LE25FW106. Also, add spi_disable_blockprotect_bp1_srwd(). Originally written and tested by The Raven <originalraven(a)hotmail.com>. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/chipdrivers.h trunk/flashchips.c trunk/flashchips.h trunk/spi25_statusreg.c Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Mon Jun 2 02:46:02 2014 (r1817) +++ trunk/chipdrivers.h Wed Jun 4 18:17:03 2014 (r1818) @@ -73,6 +73,7 @@ int spi_prettyprint_status_register_bp4_srwd(struct flashctx *flash); int spi_prettyprint_status_register_bp2_bpl(struct flashctx *flash); int spi_disable_blockprotect(struct flashctx *flash); +int spi_disable_blockprotect_bp1_srwd(struct flashctx *flash); int spi_disable_blockprotect_bp2_srwd(struct flashctx *flash); int spi_disable_blockprotect_bp3_srwd(struct flashctx *flash); int spi_disable_blockprotect_bp4_srwd(struct flashctx *flash); Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Mon Jun 2 02:46:02 2014 (r1817) +++ trunk/flashchips.c Wed Jun 4 18:17:03 2014 (r1818) @@ -9153,6 +9153,37 @@ { .vendor = "Sanyo", + .name = "LE25FW106", + .bustype = BUS_SPI, + .manufacture_id = SANYO_ID, + .model_id = SANYO_LE25FW106, + .total_size = 128, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_res2, + .probe_timing = TIMING_ZERO, + .block_erasers = { + { + .eraseblocks = { {2 * 1024, 64} }, + .block_erase = spi_block_erase_d7, + }, { + .eraseblocks = { {32 * 1024, 4} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {128 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_bp1_srwd, /* FIXME: Add ERSER error flag. */ + .unlock = spi_disable_blockprotect_bp1_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Sanyo", .name = "LE25FW406A", .bustype = BUS_SPI, .manufacture_id = SANYO_ID, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Mon Jun 2 02:46:02 2014 (r1817) +++ trunk/flashchips.h Wed Jun 4 18:17:03 2014 (r1818) @@ -537,6 +537,7 @@ #define SANYO_ID 0x62 /* Sanyo */ #define SANYO_LE25FW203A 0x1600 #define SANYO_LE25FW403A 0x1100 +#define SANYO_LE25FW106 0x15 #define SANYO_LE25FW406 0x07 /* RES2 */ #define SANYO_LE25FW418A 0x10 /* RES2 and some weird 1 byte RDID variant */ #define SANYO_LE25FW406A 0x1A /* RES2, no datasheet */ Modified: trunk/spi25_statusreg.c ============================================================================== --- trunk/spi25_statusreg.c Mon Jun 2 02:46:02 2014 (r1817) +++ trunk/spi25_statusreg.c Wed Jun 4 18:17:03 2014 (r1818) @@ -196,6 +196,13 @@ return spi_disable_blockprotect_generic(flash, 0x3C, 0, 0, 0xFF); } +/* A common block protection disable that tries to unset the status register bits masked by 0x0C (BP0-1) and + * protected/locked by bit #7. Useful when bits 4-5 may be non-0). */ +int spi_disable_blockprotect_bp1_srwd(struct flashctx *flash) +{ + return spi_disable_blockprotect_generic(flash, 0x0C, 1 << 7, 0, 0xFF); +} + /* A common block protection disable that tries to unset the status register bits masked by 0x1C (BP0-2) and * protected/locked by bit #7. Useful when bit #5 is neither a protection bit nor reserved (and hence possibly * non-0). */

1 0

[PATCH 2/2] Remove MCP6/7/8 SPI log requests.
by Stefan Tauner 03 Jun '14

03 Jun '14

We got enough (and no one is looking at them for the time being anyway). Also, return an error code in the case no bus type could be detected. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- chipset_enable.c | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index 40761d2..ec3c12c 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1244,8 +1244,6 @@ static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name) int ret = 0, want_spi = 0; uint8_t val; - msg_pinfo("This chipset is not really supported yet. Guesswork...\n"); - /* dev is the ISA bridge. No idea what the stuff below does. */ val = pci_read_byte(dev, 0x8a); msg_pdbg("ISA/LPC bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 " @@ -1264,17 +1262,15 @@ static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name) */ internal_buses_supported = BUS_NONE; msg_pdbg("Flash bus type is SPI\n"); - msg_pinfo("SPI on this chipset is WIP. Please report any " - "success or failure by mailing us the verbose " - "output to flashrom(a)flashrom.org, thanks!\n"); break; default: /* Should not happen. */ internal_buses_supported = BUS_NONE; - msg_pdbg("Flash bus type is unknown (none)\n"); - msg_pinfo("Something went wrong with bus type detection.\n"); - goto out_msg; - break; + msg_pwarn("Flash bus type is unknown (none)\n"); + msg_pinfo("Please send the log files created by \"flashrom -p internal -o logfile\" to \n" + "flashrom(a)flashrom.org with \"your board name: flashrom -V\" as the subject to\n" + "help us finish support for your chipset. Thanks.\n"); + return ERROR_NONFATAL; } /* Force enable SPI and disable LPC? Not a good idea. */ @@ -1287,11 +1283,6 @@ static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name) if (mcp6x_spi_init(want_spi)) ret = 1; -out_msg: - msg_pinfo("Please send the output of \"flashrom -V -p internal\" to flashrom(a)flashrom.org\n" - "with \"your board name: flashrom -V\" as the subject to help us finish support\n" - "for your chipset. Thanks.\n"); - return ret; } -- Kind regards, Stefan Tauner

1 0

[PATCH 1/2] Remove W836xx log requests.
by Stefan Tauner 03 Jun '14

03 Jun '14

We got enough (and no one is looking at them for the time being anyway). Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- board_enable.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/board_enable.c b/board_enable.c index 2cf6776..782db35 100644 --- a/board_enable.c +++ b/board_enable.c @@ -333,12 +333,9 @@ void probe_superio_winbond(void) continue; } } - msg_pinfo("Active config mode, unknown reg 0x20 ID: %02x.\n", model); - msg_pinfo("Please send the output of \"flashrom -V -p internal\" to \n" - "flashrom(a)flashrom.org with W836xx: your board name: flashrom -V\n" - "as the subject to help us finish support for your Super I/O. Thanks.\n"); + msg_pdbg("Active config mode, unknown reg 0x20 ID: %02x.\n", model); continue; - } + } /* The Super I/O reacts to W836xx enter and exit config mode, it's probably Winbond. */ w836xx_ext_enter(s.port); s.model = sio_read(s.port, 0x20); -- Kind regards, Stefan Tauner

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Re: [flashrom] ft2232_spi:type=jtagkey
by Stefan Tauner 03 Jun '14

03 Jun '14

Hello Alfin, thanks for your report. Have you connected all input pins of the flash chip to the programmer? The behavior shown in the log extract could be coming from a floating write protection pin. That's pin #9 (diagonally opposite to the pin #1 marker on the 16-pin sop/soic package). I'd check if that pin is pulled-high towards VCC (pin #2). Likewise all other *input* pins should be driven - either statically to GND or VCC (ideally by resistors), or dynamically by the programmer's clock and data out pins. HTH -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

W836xx: J1800N-D2H: flashrom -V
by Maarten Wouters 03 Jun '14

03 Jun '14

1 0

Re: [flashrom] Add PICkit2 as an SPI programmer
by Stefan Tauner 02 Jun '14

02 Jun '14

On Mon, 2 Jun 2014 21:43:09 -0400 Justin Chevrier <jchevrier(a)gmail.com> wrote: > +.BR "* atavia" " (for flash ROMs on VIA VT6421A SATA controllers)" > +.sp > +.BR "* it8212" " (for flash ROMs on ITE IT8212F ATA/RAID controller)" > +.sp Hi, thanks for your updated patch! You seem to have mixed up a few bits while rebasing. I could clear that up too, but if you beat me at it, I'd feel lucky ;) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Add PICkit2 as an SPI programmer
by Justin Chevrier 02 Jun '14

02 Jun '14

On Mon, Jun 2, 2014 at 9:43 PM, Justin Chevrier <jchevrier(a)gmail.com> wrote: > Hi Stefan, > > Attached is a second revision of my patch. Hopefully it addresses > everything you pointed out previously! Keep me posted if more work > needs to be done. > > I have attached a log of a write as well. > > Thanks again, > > Justin > > On Fri, May 30, 2014 at 8:27 PM, Stefan Tauner > <stefan.tauner(a)alumni.tuwien.ac.at> wrote: >> On Thu, 1 May 2014 13:39:44 -0400 >> Justin Chevrier <jchevrier(a)gmail.com> wrote: >> >>> Very sorry for not replying to your email (thanks for the review by the way). >>> >>> I do have a newer patch that fixes most if not all of the points you >>> made, but I've been slacking in going over it one last time and >>> getting it sent in. I had someone contact me directly around December >>> and they successfully used this updated patch on their hardware. >>> >>> I'll see if I can get the patch brushed up and sent in shortly. >>> >>> Thanks for the reminder (ugh, can't believe it's been over one year). >> >> Hi Justin, >> >> this is just a friendly ping. I am planning to do a stable release in >> the not too distant future (next few weeks) and would like to include >> your module if it gets ready by then. >> >> -- >> Kind regards/Mit freundlichen Grüßen, Stefan Tauner Ugh, sorry for the top post and the flashrom.8 junk in the patch. New version attached. Justin

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Re: [flashrom] Add PICkit2 as an SPI programmer
by Stefan Tauner 02 Jun '14

02 Jun '14

On Thu, 1 May 2014 13:39:44 -0400 Justin Chevrier <jchevrier(a)gmail.com> wrote: > Very sorry for not replying to your email (thanks for the review by the way). > > I do have a newer patch that fixes most if not all of the points you > made, but I've been slacking in going over it one last time and > getting it sent in. I had someone contact me directly around December > and they successfully used this updated patch on their hardware. > > I'll see if I can get the patch brushed up and sent in shortly. > > Thanks for the reminder (ugh, can't believe it's been over one year). Hi Justin, this is just a friendly ping. I am planning to do a stable release in the not too distant future (next few weeks) and would like to include your module if it gets ready by then. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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W836xx: HP ProLiant DL585 G7: flashrom -V
by Arnold, Scott C. (JSC-DD42)[LOCKHEED MARTIN CORP] 02 Jun '14

02 Jun '14

./flashrom -V -p internal -r /tmp/flash.out flashrom v0.9.7-r1711 on Linux 3.7.9.lite (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.10, GCC 4.4.7 20120313 (Red Hat 4.4.7-4), little endian Command line (5 args): ./flashrom -V -p internal -r /tmp/flash.out Calibrating delay loop... OS timer resolution is 1 usecs, 1047M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 999 us, 10000 myus = 10001 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "HP" DMI string system-product-name: "ProLiant DL585 G7" DMI string system-version: "Not Specified" DMI string baseboard-manufacturer: "" DMI string baseboard-product-name: "" DMI string baseboard-version: "" DMI string chassis-type: "Rack Mount Chassis" W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 03. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. Found chipset "AMD SB7x0/SB8x0/SB9x0" with PCI ID 1002:439d. Enabling flash write... SPI base address is at 0x0 ROM strap override is not active OK. Note: Coreboot superiotool says the superio is a SMSC FDC37C93xFR Thanks Scott

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[PATCH][RFC] uisp_spi programmer support
by Andrew 02 Jun '14

02 Jun '14

Hello, all. I've been playing around with buspirate and my uISP ( https://github.com/uISP/ ) dongle. Even with newer firmware buspirate is really slow, and on average, takes 3m 49s to read out a 2MiB SPI flash. So I decided to play around and see if I can make a faster programmer with my uISP dongle. Basically it's an atmega8 with 12M crystal running vusb stack (no hardware usb). Any other similar hardware would do. This hardware is really cheap (BOM is less than 5$ including the pcb). My first attempt was creating a serprog-compatible firmware for uISP. It can be found here: https://github.com/uISP/uisp-app-serprog The results weren't very exciting. It took 4m 30s to read out a 2MiB SPI flash (EN25QH16) on 12M crystal. Same for 20M crystal. It seems like it was a limitation of bulk out transfers via vusb. The second attempt required patching flashrom itself, but resulted in a MUCH simpler firmware that fits roughly 115 lines of code (not counting vusb). It just uses control transfers for both reads and writes. With vusb long transfers enabled, 20Mhz crystal, 10Mhz SPI speed and max_data_read/max_data_write set to 4096 bytes reading a 2MiB SPI flash took only 2m 13s which I consider a WIN. 4096 is not a vusb limit. USB spec limits maximum transfers to control endpoint to 4096 bytes anyway. Using 254 byte max_data_read/max_data_write and long transfers disabled would be slower, but it is possible to fit everything into 2K flash and use some attiny2313, which will make it even cheaper. The protocol's simple as hell, so anyone with a better hardware around (STM32, atmega8u2, pic32, whatever) can implement it with very little effort and get lighting-fast speeds. My WIP patch to flashrom's attached, although I have a few silly questions left: * Do I need to implement SPI frequency changing via a dedicated command or is it okay to hardcode it to 10Mhz in firmware? * Right now I'm using the same spi_read as serprog does. Is okay, or should I add an option to disable it? * firmware version checking, etc. (Is it a good idea to implement?) * Is there a better way to benchmark read/write speed in flashrom, since delay loop calibration interferes with speed measurements (currently I just used "time flashrom ...") -- Regards, Andrew

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Re: [flashrom] [PATCH 2/2] print_wiki.c: there is only one way to represent time.
by Stefan Tauner 01 Jun '14

01 Jun '14

On Sat, 31 May 2014 02:05:13 +0200 Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> wrote: > ISO 8601. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Self-acked and committed in r1817. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH 1/2] print_wiki.c: refine header and include a legend explaining the test state representation.
by Stefan Tauner 01 Jun '14

01 Jun '14

On Sat, 31 May 2014 02:05:12 +0200 Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> wrote: > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Self-acked and committed in r1816 with small refinements. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1817 - trunk
by repository service 01 Jun '14

01 Jun '14

Author: stefanct Date: Mon Jun 2 02:46:02 2014 New Revision: 1817 URL: http://flashrom.org/trac/flashrom/changeset/1817 Log: print_wiki.c: there is only one way to represent time. ISO 8601. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/print_wiki.c Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Mon Jun 2 02:45:57 2014 (r1816) +++ trunk/print_wiki.c Mon Jun 2 02:46:02 2014 (r1817) @@ -31,7 +31,7 @@ <div style=\"margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; \ background-color:#eeeeee; text-align:left; border:1px solid #aabbcc;\">\ <small>\n\ -'''Last update:''' %s(generated by flashrom %s)<br />\n\ +'''Last update:''' %s (generated by flashrom %s)<br />\n\ The tables below are generated from flashrom's source by copying the output of '''flashrom -z'''.<br /><br />\n\ A short explanation of the cells representing the support state follows:<br />\n\ {| border=\"0\" valign=\"top\"\n\ @@ -443,8 +443,10 @@ void print_supported_wiki(void) { time_t t = time(NULL); + char buf[sizeof("1986-02-28T12:37:42Z")]; + strftime(buf, sizeof(buf), "%Y-%m-%dT%H:%M:%SZ", gmtime(&t)); - printf(wiki_header, ctime(&t), flashrom_version); + printf(wiki_header, buf, flashrom_version); print_supported_chips_wiki(2); #if CONFIG_INTERNAL == 1 print_supported_chipsets_wiki(3);

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[commit] r1816 - trunk
by repository service 01 Jun '14

01 Jun '14

Author: stefanct Date: Mon Jun 2 02:45:57 2014 New Revision: 1816 URL: http://flashrom.org/trac/flashrom/changeset/1816 Log: print_wiki.c: refine header and include a legend explaining the test state representation. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/print_wiki.c Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Mon Jun 2 02:34:58 2014 (r1815) +++ trunk/print_wiki.c Mon Jun 2 02:45:57 2014 (r1816) @@ -29,11 +29,33 @@ static const char wiki_header[] = "= Supported devices =\n\n\ <div style=\"margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; \ -background-color:#eeeeee; text-align:right; border:1px solid #aabbcc;\">\ +background-color:#eeeeee; text-align:left; border:1px solid #aabbcc;\">\ <small>\n\ -Please do '''not''' edit these tables in the wiki directly, they are \ -generated by pasting '''flashrom -z''' output.<br />\ -'''Last update:''' %s(generated by flashrom %s)\n</small></div>\n"; +'''Last update:''' %s(generated by flashrom %s)<br />\n\ +The tables below are generated from flashrom's source by copying the output of '''flashrom -z'''.<br /><br />\n\ +A short explanation of the cells representing the support state follows:<br />\n\ +{| border=\"0\" valign=\"top\"\n\ +! style=\"text-align:left;\" |\n\ +! style=\"text-align:left;\" |\n\ +|-\n\ +|{{OK}}\n\ +| The feature was '''tested and should work''' in general unless there is a bug in flashrom or another component in \ +the system prohibits some functionality.\n\ +|-\n\ +|{{Dep}}\n\ +| '''Configuration-dependent'''. The feature was tested and should work in general but there are common \ +configurations that drastically limit flashrom's capabilities or make it completely stop working.\n\ +|-\n\ +|{{?3}}\n\ +| The feature is '''untested''' but believed to be working.\n\ +|-\n\ +|{{NA}}\n\ +| The feature is '''not applicable''' in this configuration (e.g. write operations on ROM chips).\n\ +|-\n\ +|{{No}}\n\ +| The feature is '''known to not work'''. Don't bother testing (nor reporting. Patches welcome! ;).\n\ +|}\n\ +</small></div>\n"; static const char th_start[] = "| valign=\"top\"|\n\n\ {| border=\"0\" style=\"font-size: smaller\" valign=\"top\"\n\

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Re: [flashrom] [PATCH 2/2] Utilize new tested states for chipsets as well.
by Carl-Daniel Hailfinger 01 Jun '14

01 Jun '14

Am 30.05.2014 05:15 schrieb Stefan Tauner: > Mark all ME-enabled Intel chipsets as DEP, alter print.c accordingly > (print_wiki.c was already prepared). > > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Thanks for your patch! Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

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[commit] r1815 - trunk
by repository service 01 Jun '14

01 Jun '14

Author: stefanct Date: Mon Jun 2 02:34:58 2014 New Revision: 1815 URL: http://flashrom.org/trac/flashrom/changeset/1815 Log: Utilize new tested states for chipsets as well. Mark all ME-enabled Intel chipsets as DEP, alter print.c accordingly (print_wiki.c was already prepared). And realign the chipset enable table when we are at it already. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/chipset_enable.c trunk/print.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Mon Jun 2 02:12:23 2014 (r1814) +++ trunk/chipset_enable.c Mon Jun 2 02:34:58 2014 (r1815) @@ -1366,60 +1366,60 @@ /* Please keep this list numerically sorted by vendor/device ID. */ const struct penable chipset_enables[] = { #if defined(__i386__) || defined(__x86_64__) - {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400}, - {0x1002, 0x438d, OK, "AMD", "SB600", enable_flash_sb600}, - {0x1002, 0x439d, OK, "AMD", "SB7x0/SB8x0/SB9x0", enable_flash_sb600}, - {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100}, - {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536}, - {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536}, - {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520}, - {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd_768_8111}, - {0x1022, 0x7468, OK, "AMD", "AMD-8111", enable_flash_amd_768_8111}, - {0x1022, 0x780e, OK, "AMD", "FCH", enable_flash_sb600}, - {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501}, - {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496}, - {0x1039, 0x0530, OK, "SiS", "530", enable_flash_sis530}, - {0x1039, 0x0540, NT, "SiS", "540", enable_flash_sis540}, - {0x1039, 0x0620, NT, "SiS", "620", enable_flash_sis530}, - {0x1039, 0x0630, NT, "SiS", "630", enable_flash_sis540}, - {0x1039, 0x0635, NT, "SiS", "635", enable_flash_sis540}, - {0x1039, 0x0640, NT, "SiS", "640", enable_flash_sis540}, - {0x1039, 0x0645, NT, "SiS", "645", enable_flash_sis540}, - {0x1039, 0x0646, OK, "SiS", "645DX", enable_flash_sis540}, - {0x1039, 0x0648, OK, "SiS", "648", enable_flash_sis540}, - {0x1039, 0x0650, OK, "SiS", "650", enable_flash_sis540}, - {0x1039, 0x0651, OK, "SiS", "651", enable_flash_sis540}, - {0x1039, 0x0655, NT, "SiS", "655", enable_flash_sis540}, - {0x1039, 0x0661, OK, "SiS", "661", enable_flash_sis540}, - {0x1039, 0x0730, OK, "SiS", "730", enable_flash_sis540}, - {0x1039, 0x0733, NT, "SiS", "733", enable_flash_sis540}, - {0x1039, 0x0735, OK, "SiS", "735", enable_flash_sis540}, - {0x1039, 0x0740, NT, "SiS", "740", enable_flash_sis540}, - {0x1039, 0x0741, OK, "SiS", "741", enable_flash_sis540}, - {0x1039, 0x0745, OK, "SiS", "745", enable_flash_sis540}, - {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis540}, - {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis540}, - {0x1039, 0x0755, OK, "SiS", "755", enable_flash_sis540}, - {0x1039, 0x5511, NT, "SiS", "5511", enable_flash_sis5511}, - {0x1039, 0x5571, NT, "SiS", "5571", enable_flash_sis530}, - {0x1039, 0x5591, NT, "SiS", "5591/5592", enable_flash_sis530}, - {0x1039, 0x5596, NT, "SiS", "5596", enable_flash_sis5511}, - {0x1039, 0x5597, NT, "SiS", "5597/5598/5581/5120", enable_flash_sis530}, - {0x1039, 0x5600, NT, "SiS", "600", enable_flash_sis530}, - {0x1078, 0x0100, OK, "AMD", "CS5530(A)", enable_flash_cs5530}, - {0x10b9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533}, - {0x10de, 0x0030, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2}, - {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */ - {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */ - {0x10de, 0x0060, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2}, - {0x10de, 0x00e0, OK, "NVIDIA", "NForce3", enable_flash_nvidia_nforce2}, + {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400}, + {0x1002, 0x438d, OK, "AMD", "SB600", enable_flash_sb600}, + {0x1002, 0x439d, OK, "AMD", "SB7x0/SB8x0/SB9x0", enable_flash_sb600}, + {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100}, + {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536}, + {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536}, + {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520}, + {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd_768_8111}, + {0x1022, 0x7468, OK, "AMD", "AMD-8111", enable_flash_amd_768_8111}, + {0x1022, 0x780e, OK, "AMD", "FCH", enable_flash_sb600}, + {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501}, + {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496}, + {0x1039, 0x0530, OK, "SiS", "530", enable_flash_sis530}, + {0x1039, 0x0540, NT, "SiS", "540", enable_flash_sis540}, + {0x1039, 0x0620, NT, "SiS", "620", enable_flash_sis530}, + {0x1039, 0x0630, NT, "SiS", "630", enable_flash_sis540}, + {0x1039, 0x0635, NT, "SiS", "635", enable_flash_sis540}, + {0x1039, 0x0640, NT, "SiS", "640", enable_flash_sis540}, + {0x1039, 0x0645, NT, "SiS", "645", enable_flash_sis540}, + {0x1039, 0x0646, OK, "SiS", "645DX", enable_flash_sis540}, + {0x1039, 0x0648, OK, "SiS", "648", enable_flash_sis540}, + {0x1039, 0x0650, OK, "SiS", "650", enable_flash_sis540}, + {0x1039, 0x0651, OK, "SiS", "651", enable_flash_sis540}, + {0x1039, 0x0655, NT, "SiS", "655", enable_flash_sis540}, + {0x1039, 0x0661, OK, "SiS", "661", enable_flash_sis540}, + {0x1039, 0x0730, OK, "SiS", "730", enable_flash_sis540}, + {0x1039, 0x0733, NT, "SiS", "733", enable_flash_sis540}, + {0x1039, 0x0735, OK, "SiS", "735", enable_flash_sis540}, + {0x1039, 0x0740, NT, "SiS", "740", enable_flash_sis540}, + {0x1039, 0x0741, OK, "SiS", "741", enable_flash_sis540}, + {0x1039, 0x0745, OK, "SiS", "745", enable_flash_sis540}, + {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis540}, + {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis540}, + {0x1039, 0x0755, OK, "SiS", "755", enable_flash_sis540}, + {0x1039, 0x5511, NT, "SiS", "5511", enable_flash_sis5511}, + {0x1039, 0x5571, NT, "SiS", "5571", enable_flash_sis530}, + {0x1039, 0x5591, NT, "SiS", "5591/5592", enable_flash_sis530}, + {0x1039, 0x5596, NT, "SiS", "5596", enable_flash_sis5511}, + {0x1039, 0x5597, NT, "SiS", "5597/5598/5581/5120", enable_flash_sis530}, + {0x1039, 0x5600, NT, "SiS", "600", enable_flash_sis530}, + {0x1078, 0x0100, OK, "AMD", "CS5530(A)", enable_flash_cs5530}, + {0x10b9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533}, + {0x10de, 0x0030, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2}, + {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */ + {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */ + {0x10de, 0x0060, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2}, + {0x10de, 0x00e0, OK, "NVIDIA", "NForce3", enable_flash_nvidia_nforce2}, /* Slave, should not be here, to fix known bug for A01. */ - {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804}, - {0x10de, 0x0260, OK, "NVIDIA", "MCP51", enable_flash_ck804}, - {0x10de, 0x0261, OK, "NVIDIA", "MCP51", enable_flash_ck804}, - {0x10de, 0x0262, NT, "NVIDIA", "MCP51", enable_flash_ck804}, - {0x10de, 0x0263, NT, "NVIDIA", "MCP51", enable_flash_ck804}, - {0x10de, 0x0360, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* M57SLI*/ + {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804}, + {0x10de, 0x0260, OK, "NVIDIA", "MCP51", enable_flash_ck804}, + {0x10de, 0x0261, OK, "NVIDIA", "MCP51", enable_flash_ck804}, + {0x10de, 0x0262, NT, "NVIDIA", "MCP51", enable_flash_ck804}, + {0x10de, 0x0263, NT, "NVIDIA", "MCP51", enable_flash_ck804}, + {0x10de, 0x0360, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* M57SLI*/ /* 10de:0361 is present in Tyan S2915 OEM systems, but not connected to * the flash chip. Instead, 10de:0364 is connected to the flash chip. * Until we have PCI device class matching or some fallback mechanism, @@ -1427,221 +1427,221 @@ * dual-MCP55 boards. */ #if 0 - {0x10de, 0x0361, NT, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ + {0x10de, 0x0361, NT, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ #endif - {0x10de, 0x0362, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ - {0x10de, 0x0363, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ - {0x10de, 0x0364, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ - {0x10de, 0x0365, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ - {0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ - {0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */ - {0x10de, 0x03e0, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, - {0x10de, 0x03e1, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, - {0x10de, 0x03e3, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, - {0x10de, 0x0440, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, - {0x10de, 0x0441, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, - {0x10de, 0x0442, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, - {0x10de, 0x0443, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, - {0x10de, 0x0548, OK, "NVIDIA", "MCP67", enable_flash_mcp6x_7x}, - {0x10de, 0x075c, OK, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x}, - {0x10de, 0x075d, OK, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x}, - {0x10de, 0x07d7, OK, "NVIDIA", "MCP73", enable_flash_mcp6x_7x}, - {0x10de, 0x0aac, OK, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, - {0x10de, 0x0aad, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, - {0x10de, 0x0aae, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, - {0x10de, 0x0aaf, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, - {0x10de, 0x0d80, NT, "NVIDIA", "MCP89", enable_flash_mcp6x_7x}, + {0x10de, 0x0362, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ + {0x10de, 0x0363, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ + {0x10de, 0x0364, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ + {0x10de, 0x0365, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ + {0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ + {0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */ + {0x10de, 0x03e0, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, + {0x10de, 0x03e1, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, + {0x10de, 0x03e3, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, + {0x10de, 0x0440, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, + {0x10de, 0x0441, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, + {0x10de, 0x0442, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, + {0x10de, 0x0443, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, + {0x10de, 0x0548, OK, "NVIDIA", "MCP67", enable_flash_mcp6x_7x}, + {0x10de, 0x075c, OK, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x}, + {0x10de, 0x075d, OK, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x}, + {0x10de, 0x07d7, OK, "NVIDIA", "MCP73", enable_flash_mcp6x_7x}, + {0x10de, 0x0aac, OK, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, + {0x10de, 0x0aad, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, + {0x10de, 0x0aae, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, + {0x10de, 0x0aaf, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, + {0x10de, 0x0d80, NT, "NVIDIA", "MCP89", enable_flash_mcp6x_7x}, /* VIA northbridges */ - {0x1106, 0x0585, NT, "VIA", "VT82C585VPX", via_no_byte_merge}, - {0x1106, 0x0595, NT, "VIA", "VT82C595", via_no_byte_merge}, - {0x1106, 0x0597, NT, "VIA", "VT82C597", via_no_byte_merge}, - {0x1106, 0x0601, NT, "VIA", "VT8601/VT8601A", via_no_byte_merge}, - {0x1106, 0x0691, OK, "VIA", "VT82C69x", via_no_byte_merge}, - {0x1106, 0x8601, NT, "VIA", "VT8601T", via_no_byte_merge}, + {0x1106, 0x0585, NT, "VIA", "VT82C585VPX", via_no_byte_merge}, + {0x1106, 0x0595, NT, "VIA", "VT82C595", via_no_byte_merge}, + {0x1106, 0x0597, NT, "VIA", "VT82C597", via_no_byte_merge}, + {0x1106, 0x0601, NT, "VIA", "VT8601/VT8601A", via_no_byte_merge}, + {0x1106, 0x0691, OK, "VIA", "VT82C69x", via_no_byte_merge}, + {0x1106, 0x8601, NT, "VIA", "VT8601T", via_no_byte_merge}, /* VIA southbridges */ - {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_vt82c586}, - {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_vt82c596}, - {0x1106, 0x0686, OK, "VIA", "VT82C686A/B", enable_flash_vt82c596}, - {0x1106, 0x3074, OK, "VIA", "VT8233", enable_flash_vt823x}, - {0x1106, 0x3147, OK, "VIA", "VT8233A", enable_flash_vt823x}, - {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x}, - {0x1106, 0x3227, OK, "VIA", "VT8237(R)", enable_flash_vt823x}, - {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x}, - {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi}, - {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x}, - {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x}, - {0x1106, 0x8353, NT, "VIA", "VX800/VX820", enable_flash_vt_vx}, - {0x1106, 0x8409, NT, "VIA", "VX855/VX875", enable_flash_vt_vx}, - {0x1106, 0x8410, NT, "VIA", "VX900", enable_flash_vt_vx}, - {0x1166, 0x0200, OK, "Broadcom", "OSB4", enable_flash_osb4}, - {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000}, - {0x17f3, 0x6030, OK, "RDC", "R8610/R3210", enable_flash_rdc_r8610}, - {0x8086, 0x0c60, NT, "Intel", "S12x0", enable_flash_s12x0}, - {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4}, - {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4}, - {0x8086, 0x1c44, OK, "Intel", "Z68", enable_flash_pch6}, - {0x8086, 0x1c46, OK, "Intel", "P67", enable_flash_pch6}, - {0x8086, 0x1c47, NT, "Intel", "UM67", enable_flash_pch6}, - {0x8086, 0x1c49, NT, "Intel", "HM65", enable_flash_pch6}, - {0x8086, 0x1c4a, OK, "Intel", "H67", enable_flash_pch6}, - {0x8086, 0x1c4b, NT, "Intel", "HM67", enable_flash_pch6}, - {0x8086, 0x1c4c, NT, "Intel", "Q65", enable_flash_pch6}, - {0x8086, 0x1c4d, NT, "Intel", "QS67", enable_flash_pch6}, - {0x8086, 0x1c4e, NT, "Intel", "Q67", enable_flash_pch6}, - {0x8086, 0x1c4f, OK, "Intel", "QM67", enable_flash_pch6}, - {0x8086, 0x1c50, NT, "Intel", "B65", enable_flash_pch6}, - {0x8086, 0x1c52, NT, "Intel", "C202", enable_flash_pch6}, - {0x8086, 0x1c54, OK, "Intel", "C204", enable_flash_pch6}, - {0x8086, 0x1c56, NT, "Intel", "C206", enable_flash_pch6}, - {0x8086, 0x1c5c, OK, "Intel", "H61", enable_flash_pch6}, - {0x8086, 0x1d40, OK, "Intel", "C60x/X79", enable_flash_pch6}, - {0x8086, 0x1d41, OK, "Intel", "C60x/X79", enable_flash_pch6}, - {0x8086, 0x1e44, OK, "Intel", "Z77", enable_flash_pch7}, - {0x8086, 0x1e46, NT, "Intel", "Z75", enable_flash_pch7}, - {0x8086, 0x1e47, NT, "Intel", "Q77", enable_flash_pch7}, - {0x8086, 0x1e48, NT, "Intel", "Q75", enable_flash_pch7}, - {0x8086, 0x1e49, OK, "Intel", "B75", enable_flash_pch7}, - {0x8086, 0x1e4a, OK, "Intel", "H77", enable_flash_pch7}, - {0x8086, 0x1e53, NT, "Intel", "C216", enable_flash_pch7}, - {0x8086, 0x1e55, OK, "Intel", "QM77", enable_flash_pch7}, - {0x8086, 0x1e56, NT, "Intel", "QS77", enable_flash_pch7}, - {0x8086, 0x1e57, OK, "Intel", "HM77", enable_flash_pch7}, - {0x8086, 0x1e58, NT, "Intel", "UM77", enable_flash_pch7}, - {0x8086, 0x1e59, NT, "Intel", "HM76", enable_flash_pch7}, - {0x8086, 0x1e5d, NT, "Intel", "HM75", enable_flash_pch7}, - {0x8086, 0x1e5e, NT, "Intel", "HM70", enable_flash_pch7}, - {0x8086, 0x1e5f, OK, "Intel", "NM70", enable_flash_pch7}, - {0x8086, 0x2310, NT, "Intel", "DH89xxCC", enable_flash_pch7}, - {0x8086, 0x2390, NT, "Intel", "Coleto Creek", enable_flash_pch7}, - {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich0}, - {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich0}, - {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich2345}, - {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich2345}, - {0x8086, 0x2450, NT, "Intel", "C-ICH", enable_flash_ich2345}, - {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich2345}, - {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich2345}, - {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich2345}, - {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich2345}, - {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich2345}, - {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich2345}, - {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich6}, - {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich6}, - {0x8086, 0x2642, NT, "Intel", "ICH6W/ICH6RW", enable_flash_ich6}, - {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich6}, - {0x8086, 0x27b0, OK, "Intel", "ICH7DH", enable_flash_ich7}, - {0x8086, 0x27b8, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7}, - {0x8086, 0x27b9, OK, "Intel", "ICH7M", enable_flash_ich7}, - {0x8086, 0x27bc, OK, "Intel", "NM10", enable_flash_ich7}, - {0x8086, 0x27bd, OK, "Intel", "ICH7MDH", enable_flash_ich7}, - {0x8086, 0x2810, OK, "Intel", "ICH8/ICH8R", enable_flash_ich8}, - {0x8086, 0x2811, OK, "Intel", "ICH8M-E", enable_flash_ich8}, - {0x8086, 0x2812, OK, "Intel", "ICH8DH", enable_flash_ich8}, - {0x8086, 0x2814, OK, "Intel", "ICH8DO", enable_flash_ich8}, - {0x8086, 0x2815, OK, "Intel", "ICH8M", enable_flash_ich8}, - {0x8086, 0x2910, OK, "Intel", "ICH9 Engineering Sample", enable_flash_ich9}, - {0x8086, 0x2912, OK, "Intel", "ICH9DH", enable_flash_ich9}, - {0x8086, 0x2914, OK, "Intel", "ICH9DO", enable_flash_ich9}, - {0x8086, 0x2916, OK, "Intel", "ICH9R", enable_flash_ich9}, - {0x8086, 0x2917, OK, "Intel", "ICH9M-E", enable_flash_ich9}, - {0x8086, 0x2918, OK, "Intel", "ICH9", enable_flash_ich9}, - {0x8086, 0x2919, OK, "Intel", "ICH9M", enable_flash_ich9}, - {0x8086, 0x3a10, NT, "Intel", "ICH10R Engineering Sample", enable_flash_ich10}, - {0x8086, 0x3a14, OK, "Intel", "ICH10DO", enable_flash_ich10}, - {0x8086, 0x3a16, OK, "Intel", "ICH10R", enable_flash_ich10}, - {0x8086, 0x3a18, OK, "Intel", "ICH10", enable_flash_ich10}, - {0x8086, 0x3a1a, OK, "Intel", "ICH10D", enable_flash_ich10}, - {0x8086, 0x3a1e, NT, "Intel", "ICH10 Engineering Sample", enable_flash_ich10}, - {0x8086, 0x3b00, NT, "Intel", "3400 Desktop", enable_flash_pch5}, - {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_pch5}, - {0x8086, 0x3b02, NT, "Intel", "P55", enable_flash_pch5}, - {0x8086, 0x3b03, NT, "Intel", "PM55", enable_flash_pch5}, - {0x8086, 0x3b06, OK, "Intel", "H55", enable_flash_pch5}, - {0x8086, 0x3b07, OK, "Intel", "QM57", enable_flash_pch5}, - {0x8086, 0x3b08, NT, "Intel", "H57", enable_flash_pch5}, - {0x8086, 0x3b09, NT, "Intel", "HM55", enable_flash_pch5}, - {0x8086, 0x3b0a, NT, "Intel", "Q57", enable_flash_pch5}, - {0x8086, 0x3b0b, NT, "Intel", "HM57", enable_flash_pch5}, - {0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF", enable_flash_pch5}, - {0x8086, 0x3b0e, NT, "Intel", "B55", enable_flash_pch5}, - {0x8086, 0x3b0f, OK, "Intel", "QS57", enable_flash_pch5}, - {0x8086, 0x3b12, NT, "Intel", "3400", enable_flash_pch5}, - {0x8086, 0x3b14, OK, "Intel", "3420", enable_flash_pch5}, - {0x8086, 0x3b16, NT, "Intel", "3450", enable_flash_pch5}, - {0x8086, 0x3b1e, NT, "Intel", "B55", enable_flash_pch5}, - {0x8086, 0x5031, OK, "Intel", "EP80579", enable_flash_ich7}, - {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4}, - {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4}, - {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4}, - {0x8086, 0x8119, OK, "Intel", "SCH Poulsbo", enable_flash_poulsbo}, - {0x8086, 0x8186, OK, "Intel", "Atom E6xx(T)/Tunnel Creek", enable_flash_tunnelcreek}, - {0x8086, 0x8c40, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c41, NT, "Intel", "Lynx Point Mobile Engineering Sample", enable_flash_pch8}, - {0x8086, 0x8c42, NT, "Intel", "Lynx Point Desktop Engineering Sample", enable_flash_pch8}, - {0x8086, 0x8c43, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c44, OK, "Intel", "Z87", enable_flash_pch8}, - {0x8086, 0x8c45, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c46, NT, "Intel", "Z85", enable_flash_pch8}, - {0x8086, 0x8c47, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c48, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c49, NT, "Intel", "HM86", enable_flash_pch8}, - {0x8086, 0x8c4a, OK, "Intel", "H87", enable_flash_pch8}, - {0x8086, 0x8c4b, OK, "Intel", "HM87", enable_flash_pch8}, - {0x8086, 0x8c4c, NT, "Intel", "Q85", enable_flash_pch8}, - {0x8086, 0x8c4d, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c4e, NT, "Intel", "Q87", enable_flash_pch8}, - {0x8086, 0x8c4f, NT, "Intel", "QM87", enable_flash_pch8}, - {0x8086, 0x8c50, OK, "Intel", "B85", enable_flash_pch8}, - {0x8086, 0x8c51, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c52, NT, "Intel", "C222", enable_flash_pch8}, - {0x8086, 0x8c53, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c54, NT, "Intel", "C224", enable_flash_pch8}, - {0x8086, 0x8c55, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c56, NT, "Intel", "C226", enable_flash_pch8}, - {0x8086, 0x8c57, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c58, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c59, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c5a, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c5b, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c5c, NT, "Intel", "H81", enable_flash_pch8}, - {0x8086, 0x8c5d, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c5e, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x8c5f, NT, "Intel", "Lynx Point", enable_flash_pch8}, - {0x8086, 0x9c41, NT, "Intel", "Lynx Point LP Engineering Sample", enable_flash_pch8_lp}, - {0x8086, 0x9c43, NT, "Intel", "Lynx Point LP Premium", enable_flash_pch8_lp}, - {0x8086, 0x9c45, NT, "Intel", "Lynx Point LP Mainstream", enable_flash_pch8_lp}, - {0x8086, 0x9c47, NT, "Intel", "Lynx Point LP Value", enable_flash_pch8_lp}, - {0x8086, 0x8d40, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d41, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d42, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d43, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d44, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d45, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d46, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d47, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d48, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d49, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d4a, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d4b, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d4c, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d4d, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d4e, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d4f, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d50, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d51, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d52, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d53, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d54, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d55, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d56, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d57, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d58, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d59, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d5a, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d5b, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d5c, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d5d, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d5e, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, - {0x8086, 0x8d5f, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_vt82c586}, + {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_vt82c596}, + {0x1106, 0x0686, OK, "VIA", "VT82C686A/B", enable_flash_vt82c596}, + {0x1106, 0x3074, OK, "VIA", "VT8233", enable_flash_vt823x}, + {0x1106, 0x3147, OK, "VIA", "VT8233A", enable_flash_vt823x}, + {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x}, + {0x1106, 0x3227, OK, "VIA", "VT8237(R)", enable_flash_vt823x}, + {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x}, + {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi}, + {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x}, + {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x}, + {0x1106, 0x8353, NT, "VIA", "VX800/VX820", enable_flash_vt_vx}, + {0x1106, 0x8409, NT, "VIA", "VX855/VX875", enable_flash_vt_vx}, + {0x1106, 0x8410, NT, "VIA", "VX900", enable_flash_vt_vx}, + {0x1166, 0x0200, OK, "Broadcom", "OSB4", enable_flash_osb4}, + {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000}, + {0x17f3, 0x6030, OK, "RDC", "R8610/R3210", enable_flash_rdc_r8610}, + {0x8086, 0x0c60, NT, "Intel", "S12x0", enable_flash_s12x0}, + {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4}, + {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4}, + {0x8086, 0x1c44, DEP, "Intel", "Z68", enable_flash_pch6}, + {0x8086, 0x1c46, DEP, "Intel", "P67", enable_flash_pch6}, + {0x8086, 0x1c47, NT, "Intel", "UM67", enable_flash_pch6}, + {0x8086, 0x1c49, NT, "Intel", "HM65", enable_flash_pch6}, + {0x8086, 0x1c4a, DEP, "Intel", "H67", enable_flash_pch6}, + {0x8086, 0x1c4b, NT, "Intel", "HM67", enable_flash_pch6}, + {0x8086, 0x1c4c, NT, "Intel", "Q65", enable_flash_pch6}, + {0x8086, 0x1c4d, NT, "Intel", "QS67", enable_flash_pch6}, + {0x8086, 0x1c4e, NT, "Intel", "Q67", enable_flash_pch6}, + {0x8086, 0x1c4f, DEP, "Intel", "QM67", enable_flash_pch6}, + {0x8086, 0x1c50, NT, "Intel", "B65", enable_flash_pch6}, + {0x8086, 0x1c52, NT, "Intel", "C202", enable_flash_pch6}, + {0x8086, 0x1c54, DEP, "Intel", "C204", enable_flash_pch6}, + {0x8086, 0x1c56, NT, "Intel", "C206", enable_flash_pch6}, + {0x8086, 0x1c5c, DEP, "Intel", "H61", enable_flash_pch6}, + {0x8086, 0x1d40, DEP, "Intel", "C60x/X79", enable_flash_pch6}, + {0x8086, 0x1d41, DEP, "Intel", "C60x/X79", enable_flash_pch6}, + {0x8086, 0x1e44, DEP, "Intel", "Z77", enable_flash_pch7}, + {0x8086, 0x1e46, NT, "Intel", "Z75", enable_flash_pch7}, + {0x8086, 0x1e47, NT, "Intel", "Q77", enable_flash_pch7}, + {0x8086, 0x1e48, NT, "Intel", "Q75", enable_flash_pch7}, + {0x8086, 0x1e49, DEP, "Intel", "B75", enable_flash_pch7}, + {0x8086, 0x1e4a, DEP, "Intel", "H77", enable_flash_pch7}, + {0x8086, 0x1e53, NT, "Intel", "C216", enable_flash_pch7}, + {0x8086, 0x1e55, DEP, "Intel", "QM77", enable_flash_pch7}, + {0x8086, 0x1e56, NT, "Intel", "QS77", enable_flash_pch7}, + {0x8086, 0x1e57, DEP, "Intel", "HM77", enable_flash_pch7}, + {0x8086, 0x1e58, NT, "Intel", "UM77", enable_flash_pch7}, + {0x8086, 0x1e59, NT, "Intel", "HM76", enable_flash_pch7}, + {0x8086, 0x1e5d, NT, "Intel", "HM75", enable_flash_pch7}, + {0x8086, 0x1e5e, NT, "Intel", "HM70", enable_flash_pch7}, + {0x8086, 0x1e5f, DEP, "Intel", "NM70", enable_flash_pch7}, + {0x8086, 0x2310, NT, "Intel", "DH89xxCC", enable_flash_pch7}, + {0x8086, 0x2390, NT, "Intel", "Coleto Creek", enable_flash_pch7}, + {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich0}, + {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich0}, + {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich2345}, + {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich2345}, + {0x8086, 0x2450, NT, "Intel", "C-ICH", enable_flash_ich2345}, + {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich2345}, + {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich2345}, + {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich2345}, + {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich2345}, + {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich2345}, + {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich2345}, + {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich6}, + {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich6}, + {0x8086, 0x2642, NT, "Intel", "ICH6W/ICH6RW", enable_flash_ich6}, + {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich6}, + {0x8086, 0x27b0, OK, "Intel", "ICH7DH", enable_flash_ich7}, + {0x8086, 0x27b8, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7}, + {0x8086, 0x27b9, OK, "Intel", "ICH7M", enable_flash_ich7}, + {0x8086, 0x27bc, OK, "Intel", "NM10", enable_flash_ich7}, + {0x8086, 0x27bd, OK, "Intel", "ICH7MDH", enable_flash_ich7}, + {0x8086, 0x2810, DEP, "Intel", "ICH8/ICH8R", enable_flash_ich8}, + {0x8086, 0x2811, DEP, "Intel", "ICH8M-E", enable_flash_ich8}, + {0x8086, 0x2812, DEP, "Intel", "ICH8DH", enable_flash_ich8}, + {0x8086, 0x2814, DEP, "Intel", "ICH8DO", enable_flash_ich8}, + {0x8086, 0x2815, DEP, "Intel", "ICH8M", enable_flash_ich8}, + {0x8086, 0x2910, DEP, "Intel", "ICH9 Eng. Sample", enable_flash_ich9}, + {0x8086, 0x2912, DEP, "Intel", "ICH9DH", enable_flash_ich9}, + {0x8086, 0x2914, DEP, "Intel", "ICH9DO", enable_flash_ich9}, + {0x8086, 0x2916, DEP, "Intel", "ICH9R", enable_flash_ich9}, + {0x8086, 0x2917, DEP, "Intel", "ICH9M-E", enable_flash_ich9}, + {0x8086, 0x2918, DEP, "Intel", "ICH9", enable_flash_ich9}, + {0x8086, 0x2919, DEP, "Intel", "ICH9M", enable_flash_ich9}, + {0x8086, 0x3a10, NT, "Intel", "ICH10R Eng. Sample", enable_flash_ich10}, + {0x8086, 0x3a14, DEP, "Intel", "ICH10DO", enable_flash_ich10}, + {0x8086, 0x3a16, DEP, "Intel", "ICH10R", enable_flash_ich10}, + {0x8086, 0x3a18, DEP, "Intel", "ICH10", enable_flash_ich10}, + {0x8086, 0x3a1a, DEP, "Intel", "ICH10D", enable_flash_ich10}, + {0x8086, 0x3a1e, NT, "Intel", "ICH10 Eng. Sample", enable_flash_ich10}, + {0x8086, 0x3b00, NT, "Intel", "3400 Desktop", enable_flash_pch5}, + {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_pch5}, + {0x8086, 0x3b02, NT, "Intel", "P55", enable_flash_pch5}, + {0x8086, 0x3b03, NT, "Intel", "PM55", enable_flash_pch5}, + {0x8086, 0x3b06, DEP, "Intel", "H55", enable_flash_pch5}, + {0x8086, 0x3b07, DEP, "Intel", "QM57", enable_flash_pch5}, + {0x8086, 0x3b08, NT, "Intel", "H57", enable_flash_pch5}, + {0x8086, 0x3b09, NT, "Intel", "HM55", enable_flash_pch5}, + {0x8086, 0x3b0a, NT, "Intel", "Q57", enable_flash_pch5}, + {0x8086, 0x3b0b, NT, "Intel", "HM57", enable_flash_pch5}, + {0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF", enable_flash_pch5}, + {0x8086, 0x3b0e, NT, "Intel", "B55", enable_flash_pch5}, + {0x8086, 0x3b0f, DEP, "Intel", "QS57", enable_flash_pch5}, + {0x8086, 0x3b12, NT, "Intel", "3400", enable_flash_pch5}, + {0x8086, 0x3b14, DEP, "Intel", "3420", enable_flash_pch5}, + {0x8086, 0x3b16, NT, "Intel", "3450", enable_flash_pch5}, + {0x8086, 0x3b1e, NT, "Intel", "B55", enable_flash_pch5}, + {0x8086, 0x5031, OK, "Intel", "EP80579", enable_flash_ich7}, + {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4}, + {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4}, + {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4}, + {0x8086, 0x8119, OK, "Intel", "SCH Poulsbo", enable_flash_poulsbo}, + {0x8086, 0x8186, OK, "Intel", "Atom E6xx(T)/Tunnel Creek", enable_flash_tunnelcreek}, + {0x8086, 0x8c40, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c41, NT, "Intel", "Lynx Point Mobile Eng. Sample", enable_flash_pch8}, + {0x8086, 0x8c42, NT, "Intel", "Lynx Point Desktop Eng. Sample",enable_flash_pch8}, + {0x8086, 0x8c43, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c44, DEP, "Intel", "Z87", enable_flash_pch8}, + {0x8086, 0x8c45, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c46, NT, "Intel", "Z85", enable_flash_pch8}, + {0x8086, 0x8c47, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c48, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c49, NT, "Intel", "HM86", enable_flash_pch8}, + {0x8086, 0x8c4a, DEP, "Intel", "H87", enable_flash_pch8}, + {0x8086, 0x8c4b, DEP, "Intel", "HM87", enable_flash_pch8}, + {0x8086, 0x8c4c, NT, "Intel", "Q85", enable_flash_pch8}, + {0x8086, 0x8c4d, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c4e, NT, "Intel", "Q87", enable_flash_pch8}, + {0x8086, 0x8c4f, NT, "Intel", "QM87", enable_flash_pch8}, + {0x8086, 0x8c50, DEP, "Intel", "B85", enable_flash_pch8}, + {0x8086, 0x8c51, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c52, NT, "Intel", "C222", enable_flash_pch8}, + {0x8086, 0x8c53, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c54, NT, "Intel", "C224", enable_flash_pch8}, + {0x8086, 0x8c55, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c56, NT, "Intel", "C226", enable_flash_pch8}, + {0x8086, 0x8c57, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c58, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c59, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c5a, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c5b, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c5c, NT, "Intel", "H81", enable_flash_pch8}, + {0x8086, 0x8c5d, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c5e, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x8c5f, NT, "Intel", "Lynx Point", enable_flash_pch8}, + {0x8086, 0x9c41, NT, "Intel", "Lynx Point LP Eng. Sample", enable_flash_pch8_lp}, + {0x8086, 0x9c43, NT, "Intel", "Lynx Point LP Premium", enable_flash_pch8_lp}, + {0x8086, 0x9c45, NT, "Intel", "Lynx Point LP Mainstream", enable_flash_pch8_lp}, + {0x8086, 0x9c47, NT, "Intel", "Lynx Point LP Value", enable_flash_pch8_lp}, + {0x8086, 0x8d40, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d41, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d42, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d43, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d44, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d45, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d46, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d47, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d48, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d49, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d4a, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d4b, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d4c, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d4d, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d4e, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d4f, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d50, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d51, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d52, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d53, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d54, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d55, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d56, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d57, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d58, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d59, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d5a, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d5b, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d5c, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d5d, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d5e, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, + {0x8086, 0x8d5f, NT, "Intel", "Wellsburg", enable_flash_pch8_wb}, #endif {0}, }; Modified: trunk/print.c ============================================================================== --- trunk/print.c Mon Jun 2 02:12:23 2014 (r1814) +++ trunk/print.c Mon Jun 2 02:34:58 2014 (r1815) @@ -395,7 +395,7 @@ for (i = strlen("Chipset"); i < maxchipsetlen; i++) msg_ginfo(" "); - msg_ginfo("PCI IDs State\n\n"); + msg_ginfo("PCI IDs Status\n\n"); for (c = chipset_enables; c->vendor_name != NULL; c++) { msg_ginfo("%s", c->vendor_name); @@ -404,8 +404,8 @@ msg_ginfo("%s", c->device_name); for (i = 0; i < maxchipsetlen - strlen(c->device_name); i++) msg_ginfo(" "); - msg_ginfo("%04x:%04x%s\n", c->vendor_id, c->device_id, - (c->status == NT) ? " (untested)" : ""); + msg_ginfo("%04x:%04x %s\n", c->vendor_id, c->device_id, + test_state_to_text(c->status)); } }

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