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Re: [flashrom] [PATCH] Enable Dediprog SF100 programmers with FW 5.5.1
by Pablo Cases 01 Aug '14

01 Aug '14

Playing around with non "Chip Erasers" (e.g. Block and Sector Erasers) uncovered a bug and a few problems in the previous patch submission: Fairly trivial: * Block and Sector Erase USB commands were not modified appropriately (writecnt != 1 for these commands). This is easily patched. Major problem(?): * Partial writes to the chip does not work with dediprog SF100 FW 5.5.1. The reason is that the start address supplied to dediprog through dediprog_spi_bulk_write() is not honored by dediprog. Writes will always start at address 0x0. As side note; the Dediprog Software application, which actually has functionality for partial writes, will actually not perform a partial write in its true meaning. The Dediprog Software will prepend relevant parts of the existing chip data to every partial write and then start writing from address 0x0. * Partial reads are also broken as the start address supplied to dediprog through dediprog_spi_bulk_read() is not honored either. This error is more subtle though; when validating the erase status dediprog will always supply the chip data with start at address 0x0, not at the specified start address. The result is that only the first block is checked for successful erasing. I'm not really sure on how to overcome these problems with the dediprog programmer... Regards, Pablo > -----Original Message----- > From: Pablo Cases > Sent: Thursday, July 31, 2014 1:51 PM > To: 'flashrom(a)flashrom.org' > Subject: [PATCH] Enable Dediprog SF100 programmers with FW 5.5.1 > > This patch enables Dediprog SF100 programmers with FW 5.5.1 to work > properly with flashrom. > > The following functionality has been fixed and verified on a W25Q64.V flash > chip. All fixes relate to changes in the USB commands issued to the SF100 > programmer: > * chip discovery (flashrom could not read out the ManufacturerID and > DeviceID fields properly, got parts of the devicestring instead) > * chip data readout (SF100 issued SPI Fast Read from address 0xF30000 > instead of 0x0) > * chip data write (SF100 issued SPI Page Program to address 0xF30000 instead > of 0x0) > * chip erase (verification failed as a consequence of that chip data readout > was problematic) > * SF100 LED management (LEDs could be turned on but not turned off) > > Signed-off-by: Pablo Cases <pablo.cases at flatfrog.com> > > Index: dediprog.c > ========================================================== > ========= > --- dediprog.c (revision 1832) > +++ dediprog.c (working copy) > @@ -101,8 +101,13 @@ > target_leds = leds; > } > > - ret = usb_control_msg(dediprog_handle, 0x42, 0x07, 0x09, > target_leds, > + if (dediprog_firmwareversion >= FIRMWARE_VERSION(5,5,1)) > + ret = usb_control_msg(dediprog_handle, 0x42, 0x07, > (target_leds << 8) > +| 0x09, 0x0, > NULL, 0x0, DEFAULT_TIMEOUT); > + else > + ret = usb_control_msg(dediprog_handle, 0x42, 0x07, 0x09, > target_leds, > + NULL, 0x0, DEFAULT_TIMEOUT); > + > if (ret != 0x0) { > msg_perr("Command Set LED 0x%x failed (%s)!\n", > leds, usb_strerror()); > @@ -216,8 +221,22 @@ > const char count_and_chunk[] = {count & 0xff, > (count >> 8) & 0xff, > chunksize & 0xff, > - (chunksize >> 8) & 0xff}; > + (chunksize >> 8) & 0xff, > + 0xFF, 0,0,0,0,0}; > + unsigned int count_and_chunk_size; > > + /* Reverse engineering note: > + * ======================== > + * Omitting the {0xFF, 0,0,0,0,0} appendage of SF100 FW 5.5.1 > + * results in SF100 to incorrectly issue 0x0B (Fast Read) command with > + * start at SPI address 0xF30000 instead of the expected address 0x0. > + * (On a 8MiB W25Q64.V chip this wraps around to physical address > 0x730000) > + */ > + if (dediprog_firmwareversion >= FIRMWARE_VERSION(5,5,1)) > + count_and_chunk_size = 10; > + else > + count_and_chunk_size = 4; > + > if ((start % chunksize) || (len % chunksize)) { > msg_perr("%s: Unaligned start=%i, len=%i! Please report a > bug " > "at flashrom(a)flashrom.org\n", __func__, start, len); > @@ -232,8 +251,8 @@ > */ > ret = usb_control_msg(dediprog_handle, 0x42, 0x20, start % > 0x10000, > start / 0x10000, (char *)count_and_chunk, > - sizeof(count_and_chunk), DEFAULT_TIMEOUT); > - if (ret != sizeof(count_and_chunk)) { > + count_and_chunk_size, DEFAULT_TIMEOUT); > + if (ret != count_and_chunk_size) { > msg_perr("Command Read SPI Bulk failed, %i %s!\n", ret, > usb_strerror()); > return 1; > @@ -316,9 +335,27 @@ > * space in a USB bulk transfer must be filled with 0xff padding. > */ > const unsigned int count = len / chunksize; > - const char count_and_cmd[] = {count & 0xff, (count >> 8) & 0xff, > 0x00, dedi_spi_cmd}; > + const char count_and_cmd[] = {count & 0xff, (count >> 8) & 0xff, > 0x00, dedi_spi_cmd, 0xFF, 0,0,0,0,0}; > + unsigned int count_and_cmd_size; > char usbbuf[512]; > - > + > + /* Reverse engineering note: > + * ======================== > + * Omitting the {0xFF, 0,0,0,0,0} appendage of SF100 FW 5.5.1 > + * results in SF100 to incorrectly issue 0x02 (Page Program) command > with > + * start at SPI address 0xF30000 instead of the expected address 0x0. > + * (On a 8MiB W25Q64.V chip this wraps around to physical address > 0x730000) > + * Issuing a single spi_bulk_write() command with this appendage will > + * correct the addressing so that all further spi_bulk_write() > commands > + * (with or without the appendage) will start at SPI address 0x0. > + * Only a power cycle of the SF100 will reset the behavior > + * (i.e. reintroduce the error). > + */ > + if (dediprog_firmwareversion >= FIRMWARE_VERSION(5,5,1)) > + count_and_cmd_size = 10; > + else > + count_and_cmd_size = 4; > + > /* > * We should change this check to > * chunksize > 512 > @@ -343,8 +380,8 @@ > * SPI side. > */ > ret = usb_control_msg(dediprog_handle, 0x42, 0x30, start % > 0x10000, start / 0x10000, > - (char *)count_and_cmd, sizeof(count_and_cmd), > DEFAULT_TIMEOUT); > - if (ret != sizeof(count_and_cmd)) { > + (char *)count_and_cmd, count_and_cmd_size, > DEFAULT_TIMEOUT); > + if (ret != count_and_cmd_size) { > msg_perr("Command Write SPI Bulk failed, %i %s!\n", ret, > usb_strerror()); > return 1; > @@ -447,10 +484,29 @@ > msg_perr("Untested readcnt=%i, aborting.\n", readcnt); > return 1; > } > - > - ret = usb_control_msg(dediprog_handle, 0x42, 0x1, 0xff, > - readcnt ? 0x1 : 0x0, (char *)writearr, writecnt, > - DEFAULT_TIMEOUT); > + > + if (dediprog_firmwareversion >= FIRMWARE_VERSION(5,5,1)) > + if (writecnt == 1 && > + (*writearr == 0x6 || // Write > Enable > + *writearr == 0x60 || *writearr == 0xc7 ||// Chip > Erase > + *writearr == 0x52 || *writearr == 0xd8 ||// Block > Erase > + *writearr == 0x20)) // Sector > Erase > + /* These commands are treated differently > otherwise > + * Read Status Register-1 (05h) will return incorrect > + * results for WEL and WIP bits > + * (at least on Winbond W25Q64BV Flash) > + */ > + ret = usb_control_msg(dediprog_handle, 0x42, 0x1, > 0x0, > + 0x0, (char *)writearr, writecnt, > + DEFAULT_TIMEOUT); > + else > + ret = usb_control_msg(dediprog_handle, 0x42, 0x1, > 0x1, > + 0x0, (char *)writearr, writecnt, > + DEFAULT_TIMEOUT); > + else > + ret = usb_control_msg(dediprog_handle, 0x42, 0x1, 0xff, > + readcnt ? 0x1 : 0x0, (char *)writearr, writecnt, > + DEFAULT_TIMEOUT); > if (ret != writecnt) { > msg_perr("Send SPI failed, expected %i, got %i %s!\n", > writecnt, ret, usb_strerror()); > @@ -459,8 +515,13 @@ > if (!readcnt) > return 0; > memset(readarr, 0, readcnt); > - ret = usb_control_msg(dediprog_handle, 0xc2, 0x01, 0xbb8, 0x0000, > - (char *)readarr, readcnt, DEFAULT_TIMEOUT); > + > + if (dediprog_firmwareversion >= FIRMWARE_VERSION(5,5,1)) > + ret = usb_control_msg(dediprog_handle, 0xc2, 0x1, 0x1, 0x0, > + (char *)readarr, readcnt, DEFAULT_TIMEOUT); > + else > + ret = usb_control_msg(dediprog_handle, 0xc2, 0x1, 0xbb8, > 0x0000, > + (char *)readarr, readcnt, DEFAULT_TIMEOUT); > if (ret != readcnt) { > msg_perr("Receive SPI failed, expected %i, got %i %s!\n", > readcnt, ret, usb_strerror()); > @@ -485,6 +546,12 @@ > " String!\n"); > return 1; > } > + /* Reverse engineering note: > + * ======================== > + * Dediprog Software SF6.0.4.33 application sends the devicestring > + * command with wValue and wIndex values of 0x0 instead of 0xFF. > + * Both commands yield the same result, so nothing is changed for > now. > + */ > /* Command Receive Device String. */ > memset(buf, 0, sizeof(buf)); > ret = usb_control_msg(dediprog_handle, 0xc2, 0x8, 0xff, 0xff, buf, > > > ---------------------------------------------------------------------- > > Pablo Cases, M.Sc. > Senior Software Engineer > FlatFrog Laboratories AB

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Re: [flashrom] [PATCH] Reorder block_erasers to favor large block erasers over small block erasers
by Stefan Tauner 01 Aug '14

01 Aug '14

On Thu, 31 Jul 2014 12:08:11 +0000 Pablo Cases <pablo.cases(a)flatfrog.com> wrote: > This patch reorders the block_erasers by increasing block count with the assumption that the fewer block erase commands that have to be issued the lower the erase times. E.g. this will favor chip erase instructions (as their block count is 1) even though they are generally listed last in the block_erasers list for each chip in flashchips.c > > As an example this reduces the erase time for a W25Q64.V chip from 14 minutes to 8 seconds as a single Chip Erase (60h) instruction will be used instead of issuing a sequence of 2048 Sector Erase (20h) commands. > Hi Pablo, i think there is one major problem with this: it breaks partial updates. If the data on the chip and the data requested (i.e. the data residing in the file) are equal, flashrom skips the whole write process. If there are changes, flashrom tries the smallest block size first and modifies only those blocks that are different. AFAICS your patch would reverse the order and hence any change would require to erase and write the flash completely even if only one byte has changed and the flash chip (and programmer) support smaller blocks. The partial updates are not only a performance strategy: If some blocks are write-protected without a (working) way to unlock them your patch would introduce a regression in the case only unprotected blocks are to be modified. Your benchmark seems to measure an extreme case. What programmer do you use, something USB-based I guess, a bus pirate maybe? Even for that 14 mins seem to be quite slow (almost half a second for one block, which is btw about the maximum erase time stated in the datasheet, although that is probably not really the bottleneck). Also, the 8 seconds are half of the specified typical chip erase time(!). No idea how you managed to do that. :) I was looking at revision C of the W25Q64CV datasheet for the timing values. To sum up: I don't think this is the right way to do this and a proper implementation would require quite some effort (pre-calculating necessary erases, estimating the best block eraser(s) to use etc). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

[PATCH] Clean up action parameter handling
by Nate Case 31 Jul '14

31 Jul '14

Condense 'read_it', 'write_it', 'erase_it', 'verify_it', and 'force' into a single 'flags' parameter. This makes the function signatures much more sane, while also making it much easier to add new features/flags in the future. Signed-off-by: Nate Case <ncase(a)xes-inc.com> --- cli_classic.c | 34 +++++++++++++++++----------------- flash.h | 13 ++++++++++++- flashrom.c | 44 +++++++++++++++++++------------------------- 3 files changed, 48 insertions(+), 43 deletions(-) Index: flashrom.c =================================================================== --- flashrom.c (revision 1832) +++ flashrom.c (working copy) @@ -1850,30 +1850,26 @@ } } -/* FIXME: This function signature needs to be improved once doit() has a better - * function signature. - */ -int chip_safety_check(const struct flashctx *flash, int force, int read_it, int write_it, int erase_it, - int verify_it) +int chip_safety_check(const struct flashctx *flash, int flags) { const struct flashchip *chip = flash->chip; - if (!programmer_may_write && (write_it || erase_it)) { + if (!programmer_may_write && (flags & (ACTION_FLAG_WRITE | ACTION_FLAG_ERASE))) { msg_perr("Write/erase is not working yet on your programmer in " "its current configuration.\n"); /* --force is the wrong approach, but it's the best we can do * until the generic programmer parameter parser is merged. */ - if (!force) + if (!(flags & ACTION_FLAG_FORCE)) return 1; msg_cerr("Continuing anyway.\n"); } - if (read_it || erase_it || write_it || verify_it) { + if (flags & ACTION_FLAGS_RWEV) { /* Everything needs read. */ if (chip->tested.read == BAD) { msg_cerr("Read is not working on this chip. "); - if (!force) + if (!(flags & ACTION_FLAG_FORCE)) return 1; msg_cerr("Continuing anyway.\n"); } @@ -1883,7 +1879,7 @@ return 1; } } - if (erase_it || write_it) { + if (flags & (ACTION_FLAG_ERASE | ACTION_FLAG_WRITE)) { /* Write needs erase. */ if (chip->tested.erase == NA) { msg_cerr("Erase is not possible on this chip.\n"); @@ -1891,7 +1887,7 @@ } if (chip->tested.erase == BAD) { msg_cerr("Erase is not working on this chip. "); - if (!force) + if (!(flags & ACTION_FLAG_FORCE)) return 1; msg_cerr("Continuing anyway.\n"); } @@ -1901,14 +1897,14 @@ return 1; } } - if (write_it) { + if (flags & ACTION_FLAG_WRITE) { if (chip->tested.write == NA) { msg_cerr("Write is not possible on this chip.\n"); return 1; } if (chip->tested.write == BAD) { msg_cerr("Write is not working on this chip. "); - if (!force) + if (!(flags & ACTION_FLAG_FORCE)) return 1; msg_cerr("Continuing anyway.\n"); } @@ -1921,19 +1917,17 @@ return 0; } -/* This function signature is horrible. We need to design a better interface, - * but right now it allows us to split off the CLI code. - * Besides that, the function itself is a textbook example of abysmal code flow. +/* + * FIXME: Abysmal code flow */ -int doit(struct flashctx *flash, int force, const char *filename, int read_it, - int write_it, int erase_it, int verify_it) +int doit(struct flashctx *flash, const char *filename, int flags) { uint8_t *oldcontents; uint8_t *newcontents; int ret = 0; unsigned long size = flash->chip->total_size * 1024; - if (chip_safety_check(flash, force, read_it, write_it, erase_it, verify_it)) { + if (chip_safety_check(flash, flags)) { msg_cerr("Aborting.\n"); return 1; } @@ -1949,7 +1943,7 @@ if (flash->chip->unlock) flash->chip->unlock(flash); - if (read_it) { + if (flags & ACTION_FLAG_READ) { return read_flash_to_file(flash, filename); } @@ -1973,7 +1967,7 @@ * before we can write. */ - if (erase_it) { + if (flags & ACTION_FLAG_ERASE) { /* FIXME: Do we really want the scary warning if erase failed? * After all, after erase the chip is either blank or partially * blank or it has the old contents. A blank chip won't boot, @@ -1987,7 +1981,7 @@ goto out; } - if (write_it || verify_it) { + if (flags & (ACTION_FLAG_WRITE | ACTION_FLAG_VERIFY)) { if (read_buf_from_file(newcontents, size, filename)) { ret = 1; goto out; @@ -2026,7 +2020,7 @@ // //////////////////////////////////////////////////////////// - if (write_it) { + if (flags & ACTION_FLAG_WRITE) { if (erase_and_write_flash(flash, oldcontents, newcontents)) { msg_cerr("Uh oh. Erase/write failed. Checking if anything has changed.\n"); msg_cinfo("Reading current flash chip contents... "); @@ -2047,10 +2041,10 @@ } /* Verify only if we either did not try to write (verify operation) or actually changed something. */ - if (verify_it && (!write_it || !all_skipped)) { + if ((flags & ACTION_FLAG_VERIFY) && (!(flags & ACTION_FLAG_WRITE) || !all_skipped)) { msg_cinfo("Verifying flash... "); - if (write_it) { + if (flags & ACTION_FLAG_WRITE) { /* Work around chips which need some time to calm down. */ programmer_delay(1000*1000); ret = verify_range(flash, newcontents, 0, size); Index: cli_classic.c =================================================================== --- cli_classic.c (revision 1832) +++ cli_classic.c (working copy) @@ -98,11 +98,11 @@ struct flashctx *fill_flash; const char *name; int namelen, opt, i, j; - int startchip = -1, chipcount = 0, option_index = 0, force = 0; + int startchip = -1, chipcount = 0, option_index = 0; #if CONFIG_PRINT_WIKI == 1 int list_supported_wiki = 0; #endif - int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0; + int flags = 0; int dont_verify_it = 0, list_supported = 0, operation_specified = 0; enum programmer prog = PROGRAMMER_INVALID; int ret = 0; @@ -156,7 +156,7 @@ cli_classic_abort_usage(); } filename = strdup(optarg); - read_it = 1; + flags |= ACTION_FLAG_READ; break; case 'w': if (++operation_specified > 1) { @@ -165,7 +165,7 @@ cli_classic_abort_usage(); } filename = strdup(optarg); - write_it = 1; + flags |= ACTION_FLAG_WRITE; break; case 'v': //FIXME: gracefully handle superfluous -v @@ -179,10 +179,10 @@ cli_classic_abort_usage(); } filename = strdup(optarg); - verify_it = 1; + flags |= ACTION_FLAG_VERIFY; break; case 'n': - if (verify_it) { + if (flags & ACTION_FLAG_VERIFY) { fprintf(stderr, "--verify and --noverify are mutually exclusive. Aborting.\n"); cli_classic_abort_usage(); } @@ -202,10 +202,10 @@ "specified. Aborting.\n"); cli_classic_abort_usage(); } - erase_it = 1; + flags |= ACTION_FLAG_ERASE; break; case 'f': - force = 1; + flags |= ACTION_FLAG_FORCE; break; case 'l': if (layoutfile) { @@ -327,7 +327,7 @@ cli_classic_abort_usage(); } - if ((read_it | write_it | verify_it) && check_filename(filename, "image")) { + if ((flags & ACTION_FLAGS_RWV) && check_filename(filename, "image")) { cli_classic_abort_usage(); } if (layoutfile && check_filename(layoutfile, "layout")) { @@ -369,7 +369,7 @@ ret = 1; goto out; } - if (layoutfile != NULL && !write_it) { + if (layoutfile != NULL && !(flags & ACTION_FLAG_WRITE)) { msg_gerr("Layout files are currently supported for write operations only.\n"); ret = 1; goto out; @@ -447,11 +447,11 @@ goto out_shutdown; } else if (!chipcount) { msg_cinfo("No EEPROM/flash device found.\n"); - if (!force || !chip_to_probe) { + if (!(flags & ACTION_FLAG_FORCE) || !chip_to_probe) { msg_cinfo("Note: flashrom can never write if the flash chip isn't found " "automatically.\n"); } - if (force && read_it && chip_to_probe) { + if ((flags & ACTION_FLAG_FORCE) && (flags & ACTION_FLAG_READ) && chip_to_probe) { struct registered_master *mst; int compatible_masters = 0; msg_cinfo("Force read (-f -r -c) requested, pretending the chip is there:\n"); @@ -502,27 +502,27 @@ check_chip_supported(fill_flash->chip); size = fill_flash->chip->total_size * 1024; - if (check_max_decode(fill_flash->mst->buses_supported & fill_flash->chip->bustype, size) && (!force)) { + if (check_max_decode(fill_flash->mst->buses_supported & fill_flash->chip->bustype, size) && !(flags & ACTION_FLAG_FORCE)) { msg_cerr("Chip is too big for this programmer (-V gives details). Use --force to override.\n"); ret = 1; goto out_shutdown; } - if (!(read_it | write_it | verify_it | erase_it)) { + if (!(flags & ACTION_FLAGS_RWEV)) { msg_ginfo("No operations were specified.\n"); goto out_shutdown; } /* Always verify write operations unless -n is used. */ - if (write_it && !dont_verify_it) - verify_it = 1; + if ((flags & ACTION_FLAG_WRITE) && !dont_verify_it) + flags |= ACTION_FLAG_VERIFY; /* FIXME: We should issue an unconditional chip reset here. This can be * done once we have a .reset function in struct flashchip. * Give the chip time to settle. */ programmer_delay(100000); - ret |= doit(fill_flash, force, filename, read_it, write_it, erase_it, verify_it); + ret |= doit(fill_flash, filename, flags); out_shutdown: programmer_shutdown(); Index: flash.h =================================================================== --- flash.h (revision 1832) +++ flash.h (working copy) @@ -121,6 +121,17 @@ #define FEATURE_OTP (1 << 8) #define FEATURE_QPI (1 << 9) +#define ACTION_FLAG_READ (1 << 1) +#define ACTION_FLAG_WRITE (1 << 2) +#define ACTION_FLAG_ERASE (1 << 3) +#define ACTION_FLAG_VERIFY (1 << 4) +#define ACTION_FLAG_FORCE (1 << 5) + +#define ACTION_FLAGS_RWEV (ACTION_FLAG_READ | ACTION_FLAG_WRITE | \ + ACTION_FLAG_ERASE | ACTION_FLAG_VERIFY) +#define ACTION_FLAGS_RWV (ACTION_FLAG_READ | ACTION_FLAG_WRITE | \ + ACTION_FLAG_VERIFY) + enum test_state { OK = 0, NT = 1, /* Not tested */ @@ -268,7 +279,7 @@ void print_banner(void); void list_programmers_linebreak(int startcol, int cols, int paren); int selfcheck(void); -int doit(struct flashctx *flash, int force, const char *filename, int read_it, int write_it, int erase_it, int verify_it); +int doit(struct flashctx *flash, const char *filename, int flags); int read_buf_from_file(unsigned char *buf, unsigned long size, const char *filename); int write_buf_to_file(const unsigned char *buf, unsigned long size, const char *filename);

2 7

[PATCH] Reorder block_erasers to favor large block erasers over small block erasers
by Pablo Cases 31 Jul '14

31 Jul '14

This patch reorders the block_erasers by increasing block count with the assumption that the fewer block erase commands that have to be issued the lower the erase times. E.g. this will favor chip erase instructions (as their block count is 1) even though they are generally listed last in the block_erasers list for each chip in flashchips.c As an example this reduces the erase time for a W25Q64.V chip from 14 minutes to 8 seconds as a single Chip Erase (60h) instruction will be used instead of issuing a sequence of 2048 Sector Erase (20h) commands. Signed-off-by: Pablo Cases <pablo.cases at flatfrog.com> Index: flashrom.c =================================================================== --- flashrom.c (revision 1832) +++ flashrom.c (working copy) @@ -1432,22 +1432,20 @@ return 0; } -static int check_block_eraser(const struct flashctx *flash, int k, int log) +static int check_block_eraser2(struct block_eraser* eraser, int log) { - struct block_eraser eraser = flash->chip->block_erasers[k]; - - if (!eraser.block_erase && !eraser.eraseblocks[0].count) { + if (!eraser->block_erase && !eraser->eraseblocks[0].count) { if (log) msg_cdbg("not defined. "); return 1; } - if (!eraser.block_erase && eraser.eraseblocks[0].count) { + if (!eraser->block_erase && eraser->eraseblocks[0].count) { if (log) msg_cdbg("eraseblock layout is known, but matching " "block erase function is not implemented. "); return 1; } - if (eraser.block_erase && !eraser.eraseblocks[0].count) { + if (eraser->block_erase && !eraser->eraseblocks[0].count) { if (log) msg_cdbg("block erase function found, but " "eraseblock layout is not defined. "); @@ -1457,6 +1455,38 @@ return 0; } +static int check_block_eraser(const struct flashctx *flash, int k, int log) +{ + struct block_eraser eraser = flash->chip->block_erasers[k]; + return check_block_eraser2(&eraser, log); +} + +static struct block_eraser* get_block_erasers(struct flashctx* flash) +{ + return flash->chip->block_erasers; +} + +static int compare_by_block_count(const void *a, const void *b) +{ + struct block_eraser* bea = (struct block_eraser*)a; + struct block_eraser* beb = (struct block_eraser*)b; + + if (check_block_eraser2(bea, 0) && check_block_eraser2(beb, 0)) + // both erasers are invalid + return 0; + else if (!check_block_eraser2(bea, 0) && check_block_eraser2(beb, 0)) + // first eraser valid, second eraser invalid + return -1; + else if (check_block_eraser2(bea, 0) && !check_block_eraser2(beb, 0)) + // second eraser valid, first eraser invalid + return 1; + else { + // both erasers are valid, ignore that some chips have + // differently sized erase regions + return bea->eraseblocks[0].count - beb->eraseblocks[0].count; + } +} + int erase_and_write_flash(struct flashctx *flash, uint8_t *oldcontents, uint8_t *newcontents) { int k, ret = 1; @@ -1463,6 +1493,7 @@ uint8_t *curcontents; unsigned long size = flash->chip->total_size * 1024; unsigned int usable_erasefunctions = count_usable_erasers(flash); + struct block_eraser* sorted_erasers; msg_cinfo("Erasing and writing flash chip... "); curcontents = malloc(size); @@ -1473,6 +1504,22 @@ /* Copy oldcontents to curcontents to avoid clobbering oldcontents. */ memcpy(curcontents, oldcontents, size); + /* only get the pointer to the block_erasers, + i.e. block_erasers are sorted in place at their original location, + hence the order might no longer match the order defined in + flashchips.c */ + sorted_erasers = get_block_erasers(flash); + qsort(sorted_erasers, NUM_ERASEFUNCTIONS, sizeof(struct block_eraser), + compare_by_block_count); + + /* block_erasers are now sorted by ascending block count + with the assumption on that a low block count results in lower + erase times than a high block counts */ + msg_gspew("\nSorted erase functions listed by ascending block count:\n"); + msg_gspew("Block Size\tBlock Count\n"); + for (k = 0; k < NUM_ERASEFUNCTIONS; k++) + msg_gspew("%d\t\t%d\n", sorted_erasers[k].eraseblocks[0].size, sorted_erasers[k].eraseblocks[0].count); + for (k = 0; k < NUM_ERASEFUNCTIONS; k++) { if (k != 0) msg_cinfo("Looking for another erase function.\n"); ---------------------------------------------------------------------- Pablo Cases, M.Sc. Senior Software Engineer FlatFrog Laboratories AB

1 0

[PATCH] Enable Dediprog SF100 programmers with FW 5.5.1
by Pablo Cases 31 Jul '14

31 Jul '14

This patch enables Dediprog SF100 programmers with FW 5.5.1 to work properly with flashrom. The following functionality has been fixed and verified on a W25Q64.V flash chip. All fixes relate to changes in the USB commands issued to the SF100 programmer: * chip discovery (flashrom could not read out the ManufacturerID and DeviceID fields properly, got parts of the devicestring instead) * chip data readout (SF100 issued SPI Fast Read from address 0xF30000 instead of 0x0) * chip data write (SF100 issued SPI Page Program to address 0xF30000 instead of 0x0) * chip erase (verification failed as a consequence of that chip data readout was problematic) * SF100 LED management (LEDs could be turned on but not turned off) Signed-off-by: Pablo Cases <pablo.cases at flatfrog.com> Index: dediprog.c =================================================================== --- dediprog.c (revision 1832) +++ dediprog.c (working copy) @@ -101,8 +101,13 @@ target_leds = leds; } - ret = usb_control_msg(dediprog_handle, 0x42, 0x07, 0x09, target_leds, + if (dediprog_firmwareversion >= FIRMWARE_VERSION(5,5,1)) + ret = usb_control_msg(dediprog_handle, 0x42, 0x07, (target_leds << 8) | 0x09, 0x0, NULL, 0x0, DEFAULT_TIMEOUT); + else + ret = usb_control_msg(dediprog_handle, 0x42, 0x07, 0x09, target_leds, + NULL, 0x0, DEFAULT_TIMEOUT); + if (ret != 0x0) { msg_perr("Command Set LED 0x%x failed (%s)!\n", leds, usb_strerror()); @@ -216,8 +221,22 @@ const char count_and_chunk[] = {count & 0xff, (count >> 8) & 0xff, chunksize & 0xff, - (chunksize >> 8) & 0xff}; + (chunksize >> 8) & 0xff, + 0xFF, 0,0,0,0,0}; + unsigned int count_and_chunk_size; + /* Reverse engineering note: + * ======================== + * Omitting the {0xFF, 0,0,0,0,0} appendage of SF100 FW 5.5.1 + * results in SF100 to incorrectly issue 0x0B (Fast Read) command with + * start at SPI address 0xF30000 instead of the expected address 0x0. + * (On a 8MiB W25Q64.V chip this wraps around to physical address 0x730000) + */ + if (dediprog_firmwareversion >= FIRMWARE_VERSION(5,5,1)) + count_and_chunk_size = 10; + else + count_and_chunk_size = 4; + if ((start % chunksize) || (len % chunksize)) { msg_perr("%s: Unaligned start=%i, len=%i! Please report a bug " "at flashrom(a)flashrom.org\n", __func__, start, len); @@ -232,8 +251,8 @@ */ ret = usb_control_msg(dediprog_handle, 0x42, 0x20, start % 0x10000, start / 0x10000, (char *)count_and_chunk, - sizeof(count_and_chunk), DEFAULT_TIMEOUT); - if (ret != sizeof(count_and_chunk)) { + count_and_chunk_size, DEFAULT_TIMEOUT); + if (ret != count_and_chunk_size) { msg_perr("Command Read SPI Bulk failed, %i %s!\n", ret, usb_strerror()); return 1; @@ -316,9 +335,27 @@ * space in a USB bulk transfer must be filled with 0xff padding. */ const unsigned int count = len / chunksize; - const char count_and_cmd[] = {count & 0xff, (count >> 8) & 0xff, 0x00, dedi_spi_cmd}; + const char count_and_cmd[] = {count & 0xff, (count >> 8) & 0xff, 0x00, dedi_spi_cmd, 0xFF, 0,0,0,0,0}; + unsigned int count_and_cmd_size; char usbbuf[512]; - + + /* Reverse engineering note: + * ======================== + * Omitting the {0xFF, 0,0,0,0,0} appendage of SF100 FW 5.5.1 + * results in SF100 to incorrectly issue 0x02 (Page Program) command with + * start at SPI address 0xF30000 instead of the expected address 0x0. + * (On a 8MiB W25Q64.V chip this wraps around to physical address 0x730000) + * Issuing a single spi_bulk_write() command with this appendage will + * correct the addressing so that all further spi_bulk_write() commands + * (with or without the appendage) will start at SPI address 0x0. + * Only a power cycle of the SF100 will reset the behavior + * (i.e. reintroduce the error). + */ + if (dediprog_firmwareversion >= FIRMWARE_VERSION(5,5,1)) + count_and_cmd_size = 10; + else + count_and_cmd_size = 4; + /* * We should change this check to * chunksize > 512 @@ -343,8 +380,8 @@ * SPI side. */ ret = usb_control_msg(dediprog_handle, 0x42, 0x30, start % 0x10000, start / 0x10000, - (char *)count_and_cmd, sizeof(count_and_cmd), DEFAULT_TIMEOUT); - if (ret != sizeof(count_and_cmd)) { + (char *)count_and_cmd, count_and_cmd_size, DEFAULT_TIMEOUT); + if (ret != count_and_cmd_size) { msg_perr("Command Write SPI Bulk failed, %i %s!\n", ret, usb_strerror()); return 1; @@ -447,10 +484,29 @@ msg_perr("Untested readcnt=%i, aborting.\n", readcnt); return 1; } - - ret = usb_control_msg(dediprog_handle, 0x42, 0x1, 0xff, - readcnt ? 0x1 : 0x0, (char *)writearr, writecnt, - DEFAULT_TIMEOUT); + + if (dediprog_firmwareversion >= FIRMWARE_VERSION(5,5,1)) + if (writecnt == 1 && + (*writearr == 0x6 || // Write Enable + *writearr == 0x60 || *writearr == 0xc7 ||// Chip Erase + *writearr == 0x52 || *writearr == 0xd8 ||// Block Erase + *writearr == 0x20)) // Sector Erase + /* These commands are treated differently otherwise + * Read Status Register-1 (05h) will return incorrect + * results for WEL and WIP bits + * (at least on Winbond W25Q64BV Flash) + */ + ret = usb_control_msg(dediprog_handle, 0x42, 0x1, 0x0, + 0x0, (char *)writearr, writecnt, + DEFAULT_TIMEOUT); + else + ret = usb_control_msg(dediprog_handle, 0x42, 0x1, 0x1, + 0x0, (char *)writearr, writecnt, + DEFAULT_TIMEOUT); + else + ret = usb_control_msg(dediprog_handle, 0x42, 0x1, 0xff, + readcnt ? 0x1 : 0x0, (char *)writearr, writecnt, + DEFAULT_TIMEOUT); if (ret != writecnt) { msg_perr("Send SPI failed, expected %i, got %i %s!\n", writecnt, ret, usb_strerror()); @@ -459,8 +515,13 @@ if (!readcnt) return 0; memset(readarr, 0, readcnt); - ret = usb_control_msg(dediprog_handle, 0xc2, 0x01, 0xbb8, 0x0000, - (char *)readarr, readcnt, DEFAULT_TIMEOUT); + + if (dediprog_firmwareversion >= FIRMWARE_VERSION(5,5,1)) + ret = usb_control_msg(dediprog_handle, 0xc2, 0x1, 0x1, 0x0, + (char *)readarr, readcnt, DEFAULT_TIMEOUT); + else + ret = usb_control_msg(dediprog_handle, 0xc2, 0x1, 0xbb8, 0x0000, + (char *)readarr, readcnt, DEFAULT_TIMEOUT); if (ret != readcnt) { msg_perr("Receive SPI failed, expected %i, got %i %s!\n", readcnt, ret, usb_strerror()); @@ -485,6 +546,12 @@ " String!\n"); return 1; } + /* Reverse engineering note: + * ======================== + * Dediprog Software SF6.0.4.33 application sends the devicestring + * command with wValue and wIndex values of 0x0 instead of 0xFF. + * Both commands yield the same result, so nothing is changed for now. + */ /* Command Receive Device String. */ memset(buf, 0, sizeof(buf)); ret = usb_control_msg(dediprog_handle, 0xc2, 0x8, 0xff, 0xff, buf, ---------------------------------------------------------------------- Pablo Cases, M.Sc. Senior Software Engineer FlatFrog Laboratories AB

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[PATCH 2/2] Add support for Atmel AT49LH004 and AT49LH00B4.
by Stefan Tauner 29 Jul '14

29 Jul '14

Also, slightly refine the definition of AT49LH002. TODO: unlocking is mandatory because the chips are write-protected by default. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- flashchips.c | 84 +++++++++++++++++++++++++++++++++++++++++++++++++++++++----- flashchips.h | 2 ++ 2 files changed, 80 insertions(+), 6 deletions(-) diff --git a/flashchips.c b/flashchips.c index 489f7c3..e8ac789 100644 --- a/flashchips.c +++ b/flashchips.c @@ -3049,10 +3049,10 @@ const struct flashchip flashchips[] = { .model_id = ATMEL_AT49LH002, .total_size = 256, .page_size = 0, /* unused */ - .feature_bits = FEATURE_REGISTERMAP, /* TODO: LPC OK too? */ + .feature_bits = FEATURE_REGISTERMAP, .tested = TEST_UNTESTED, - .probe = probe_82802ab, /* TODO: 0xff cmd not documented? */ - .probe_timing = TIMING_FIXME, + .probe = probe_82802ab, + .probe_timing = TIMING_ZERO, .block_erasers = { { @@ -3062,16 +3062,88 @@ const struct flashchip flashchips[] = { {8 * 1024, 2}, {16 * 1024, 1}, }, - .block_erase = erase_block_82802ab, + .block_erase = NULL, /* TODO: Implement. */ }, { .eraseblocks = { {64 * 1024, 4}, }, + .block_erase = erase_block_82802ab, + }, + }, + .printlock = printlock_regspace2_block_eraser_0, + .unlock = unlock_regspace2_block_eraser_0, + .write = write_82802ab, + .read = read_memmapped, + .voltage = {3000, 3600}, + }, + + { + .vendor = "Atmel", + .name = "AT49LH00B4", + .bustype = BUS_LPC | BUS_FWH, /* A/A Mux */ + .manufacture_id = ATMEL_ID, + .model_id = ATMEL_AT49LH00B4, + .total_size = 512, + .page_size = 0, /* unused */ + .feature_bits = FEATURE_REGISTERMAP, + .tested = TEST_UNTESTED, + .probe = probe_82802ab, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {8 * 1024, 2}, + {16 * 1024, 1}, + {32 * 1024, 1}, + {64 * 1024, 7}, + }, + .block_erase = NULL, /* TODO: Implement. */ + }, { + .eraseblocks = { + {64 * 1024, 8}, + }, + .block_erase = erase_block_82802ab, + }, + }, + .printlock = printlock_regspace2_block_eraser_0, + .unlock = unlock_regspace2_block_eraser_0, + .write = write_82802ab, + .read = read_memmapped, + .voltage = {3000, 3600}, + }, + + { + .vendor = "Atmel", + .name = "AT49LH004", + .bustype = BUS_LPC | BUS_FWH, /* A/A Mux */ + .manufacture_id = ATMEL_ID, + .model_id = ATMEL_AT49LH004, + .total_size = 512, + .page_size = 0, /* unused */ + .feature_bits = FEATURE_REGISTERMAP, + .tested = TEST_UNTESTED, + .probe = probe_82802ab, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 7}, + {32 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_block_82802ab, + }, { + .eraseblocks = { + {64 * 1024, 8}, + }, .block_erase = NULL, /* TODO: Implement. */ }, }, - .printlock = NULL, /* TODO */ - .unlock = NULL, /* unlock_82802ab() not correct(?) */ + .printlock = printlock_regspace2_block_eraser_0, + .unlock = unlock_regspace2_block_eraser_0, .write = write_82802ab, .read = read_memmapped, .voltage = {3000, 3600}, diff --git a/flashchips.h b/flashchips.h index 174ab3b..5589714 100644 --- a/flashchips.h +++ b/flashchips.h @@ -190,6 +190,8 @@ #define ATMEL_AT49BV512 0x03 #define ATMEL_AT49F002N 0x07 /* for AT49F002(N) */ #define ATMEL_AT49LH002 0xE9 +#define ATMEL_AT49LH00B4 0xED +#define ATMEL_AT49LH004 0xEE #define ATMEL_AT49F002NT 0x08 /* for AT49F002(N)T */ #define ATMEL_AT49F010 0x17 /* Same as AT49HF010 */ #define ATMEL_AT49F020 0x0B -- Kind regards, Stefan Tauner

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Re: [flashrom] [PATCH] Refactor unlocking of many chips with locking at register space address +2.
by Stefan Tauner 29 Jul '14

29 Jul '14

On Thu, 29 May 2014 19:13:33 +0200 Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> wrote: > This includes PMC Pm49*, SST 49LF00*, ST M50* and Winbond W39* family. > The erase and write test status bits of all affected chips have been reset. > > Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Also, the W39V040FA's unlock method should be unlock_regspace2_uniform_64k() instead of unlock_sst_fwhub(). Fixed locally. BTW, the whole sst_fwhub.c could be unified with the rest too. They are just missing the read lock bit AFAICS. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH] Add support for a bunch of 29GL parallel flash chips.
by Stefan Tauner 29 Jul '14

29 Jul '14

On Sun, 25 May 2014 05:44:18 +0100 Gilbert Klzo <gigimorphe(a)yahoo.com> wrote: > Hi Stefan > Thank you for email > Soon I've done it I will emIl you > Regards > Gilbert Hi, any progress? :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] LR-C1037TN
by Stefan Tauner 29 Jul '14

29 Jul '14

On Tue, 29 Jul 2014 00:24:20 +0100 Luis Manuel Ramos Da Costa <aliasbody(a)gmail.com> wrote: > Hello Everyone, > > So just as requested here are all the informations about this motherboard : > > *Manufacturer : *SZ Realan > *Board Model : *LR-C1037TN v1.3 > *Serial :* LRC1037TN14050466 > *FCC :* TT RU E326167 TC-1 03-01 1404 > *BIOS Chip :* GD25Q32PIG POG497 BH1309 > > *File provided by manufacturer to flash BIOS (with FPT) : * > http://paste.flashrom.org/view.php?id=2648 > > *Full flashrom log :* > http://paste.flashrom.org/view.php?id=2649 > > *"sudo lspci -vv" Log :* > http://paste.flashrom.org/view.php?id=2650 > > If there is a need for any other information please tell. Hello Luis, the output of 'sudo lspci -vvxx' and 'sudo dmidecode' would be nice to have. With that we could look for a way to whitelist the board to be not a laptop (as its DMI data indicates erroneously). Although I doubt there is anything to distinguish this board from other similarly crappy boards... :) Apart from that I don't see any problems with the board in the log... as long as you use the correct binary file of the firmware for the board (and always use the -p internal:laptop=... parameter to override the behavior discussed above), flashrom should just work with it. Did you receive a proper binary firmware for the board from the vendor? I am asking because you referred to the flash chip list of fpt a few times but never to any real firmware yet. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[Aliasbody] Flashrom Mailing List
by Luis Manuel Ramos Da Costa 28 Jul '14

28 Jul '14

Hello Everyone, So just as requested here are all the informations about this motherboard : *Manufacturer : *SZ Realan *Board Model : *LR-C1037TN v1.3 *Serial :* LRC1037TN14050466 *FCC :* TT RU E326167 TC-1 03-01 1404 *BIOS Chip :* GD25Q32PIG POG497 BH1309 *File provided by manufacturer to flash BIOS (with FPT) : * http://paste.flashrom.org/view.php?id=2648 *Full flashrom log :* http://paste.flashrom.org/view.php?id=2649 *"sudo lspci -vv" Log :* http://paste.flashrom.org/view.php?id=2650 If there is a need for any other information please tell. Best Regards, Luis Da Costa

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Re: [flashrom] [PATCH] Add new programmer for SPI EEPROMs attached to Intel 82580 NICs.
by Stefan Tauner 28 Jul '14

28 Jul '14

On Mon, 28 Jul 2014 12:01:54 +0200 Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> wrote: > Tested-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> > Thank you. It was committed in r1832. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1832 - trunk
by repository service 28 Jul '14

28 Jul '14

Author: stefanct Date: Mon Jul 28 22:35:21 2014 New Revision: 1832 URL: http://flashrom.org/trac/flashrom/changeset/1832 Log: Add new programmer for SPI EEPROMs attached to Intel 82580 NICs. This patch lets you read and write the EEPROM on 82580-based gigabit NIC cards. So far it has been tested on copper NICs only, but other variants employing this controller should work too. It is a nice substitution for the official eeupdate tool. Speed is quite decent: less than 4 seconds for erases or writes of 32 kB. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Tested-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Added: trunk/nicintel_eeprom.c (contents, props changed) Modified: trunk/Makefile trunk/flashrom.8.tmpl trunk/flashrom.c trunk/programmer.h Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Sun Jul 20 00:03:29 2014 (r1831) +++ trunk/Makefile Mon Jul 28 22:35:21 2014 (r1832) @@ -227,6 +227,11 @@ else override CONFIG_NICINTEL = no endif +ifeq ($(CONFIG_NICINTEL_EEPROM), yes) +UNSUPPORTED_FEATURES += CONFIG_NICINTEL_EEPROM=yes +else +override CONFIG_NICINTEL_EEPROM = no +endif ifeq ($(CONFIG_NICINTEL_SPI), yes) UNSUPPORTED_FEATURES += CONFIG_NICINTEL_SPI=yes else @@ -426,6 +431,9 @@ # Always enable SPI on Intel NICs for now. CONFIG_NICINTEL_SPI ?= yes +# Always enable EEPROM on Intel NICs for now. +CONFIG_NICINTEL_EEPROM ?= yes + # Always enable SPI on OGP cards for now. CONFIG_OGP_SPI ?= yes @@ -626,6 +634,12 @@ NEED_PCI := yes endif +ifeq ($(CONFIG_NICINTEL_EEPROM), yes) +FEATURE_CFLAGS += -D'CONFIG_NICINTEL_EEPROM=1' +PROGRAMMER_OBJS += nicintel_eeprom.o +NEED_PCI := yes +endif + ifeq ($(CONFIG_OGP_SPI), yes) FEATURE_CFLAGS += -D'CONFIG_OGP_SPI=1' PROGRAMMER_OBJS += ogp_spi.o Modified: trunk/flashrom.8.tmpl ============================================================================== --- trunk/flashrom.8.tmpl Sun Jul 20 00:03:29 2014 (r1831) +++ trunk/flashrom.8.tmpl Mon Jul 28 22:35:21 2014 (r1832) @@ -225,6 +225,8 @@ .sp .BR "* usbblaster_spi" " (for SPI flash ROMs attached to an Altera USB-Blaster compatible cable)" .sp +.BR "* nicintel_eeprom" " (for SPI EEPROMs on Intel Gigabit network cards)" +.sp Some programmers have optional or mandatory parameters which are described in detail in the .B PROGRAMMER SPECIFIC INFO @@ -591,7 +593,7 @@ .B content is an 8-bit hexadecimal value. .SS -.BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel"\ +.BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel", " nicintel_eeprom"\ , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii"\ , " satamv" , " atahpt" ", " atavia " and " it8212 " programmers These programmers have an option to specify the PCI address of the card @@ -625,6 +627,14 @@ .nh .B http://flashrom.org/VT6421A .SS +.BR "nicintel_eeprom " programmer +This is the first programmer module in flashrom that does not provide access to NOR flash chips but EEPROMs +mounted on gigabit Ethernet cards based on Intel's 82580 NIC. Because EEPROMs normally do not announce their +size nor allow to be identified, the controller relies on correct size values written to predefined addresses +within the chip. Flashrom follows this scheme but assumes the minimum size of 16 kB (128 kb) if an unprogrammed +EEPROM/card is detected. Intel specifies following EEPROMs to be compatible: Atmel AT25128, AT25256, Micron (ST) +M95128, M95256 and OnSemi (Catalyst) CAT25CS128. +.SS .BR "ft2232_spi " programmer An optional parameter specifies the controller type and channel/interface/port it should support. For that you have to use the @@ -922,8 +932,8 @@ .B rayer_spi needs raw I/O port access. .sp -.B satasii -needs PCI configuration space read access and raw memory access. +.BR satasii ", " nicintel ", " nicintel_eeprom " and " nicintel_spi +need PCI configuration space read access and raw memory access. .sp .B satamv needs PCI configuration space read access, raw I/O port access and raw memory Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sun Jul 20 00:03:29 2014 (r1831) +++ trunk/flashrom.c Mon Jul 28 22:35:21 2014 (r1832) @@ -297,6 +297,18 @@ }, #endif +#if CONFIG_NICINTEL_EEPROM == 1 + { + .name = "nicintel_eeprom", + .type = PCI, + .devs.dev = nics_intel_ee, + .init = nicintel_ee_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + #if CONFIG_OGP_SPI == 1 { .name = "ogp_spi", Added: trunk/nicintel_eeprom.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/nicintel_eeprom.c Mon Jul 28 22:35:21 2014 (r1832) @@ -0,0 +1,331 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2013 Ricardo Ribalda - Qtechnology A/S + * Copyright (C) 2011, 2014 Stefan Tauner + * + * Based on nicinctel_spi.c and ichspi.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +/* + * Datasheet: Intel 82580 Quad/Dual Gigabit Ethernet LAN Controller Datasheet + * 3.3.1.4: General EEPROM Software Access + * 4.7: Access to shared resources (FIXME: we should probably use this semaphore interface) + * 7.4: Register Descriptions + */ + +#include <stdlib.h> +#include <unistd.h> +#include "flash.h" +#include "spi.h" +#include "programmer.h" +#include "hwaccess.h" + +#define PCI_VENDOR_ID_INTEL 0x8086 +#define MEMMAP_SIZE (0x14 + 3) /* Only EEC and EERD are needed. */ + +#define EEC 0x10 /* EEPROM/Flash Control Register */ +#define EERD 0x14 /* EEPROM Read Register */ + +/* EPROM/Flash Control Register bits */ +#define EE_SCK 0 +#define EE_CS 1 +#define EE_SI 2 +#define EE_SO 3 +#define EE_REQ 6 +#define EE_GNT 7 +#define EE_PRES 8 +#define EE_SIZE 11 +#define EE_SIZE_MASK 0xf + +/* EEPROM Read Register bits */ +#define EERD_START 0 +#define EERD_DONE 1 +#define EERD_ADDR 2 +#define EERD_DATA 16 + +#define BIT(x) (1<<x) +#define PAGE_MASK 0x3f + +static uint8_t *nicintel_eebar; +static struct pci_dev *nicintel_pci; + +#define UNPROG_DEVICE 0x1509 + +const struct dev_entry nics_intel_ee[] = { + {PCI_VENDOR_ID_INTEL, 0x150e, OK, "Intel", "82580 Quad Gigabit Ethernet Controller (Copper)"}, + {PCI_VENDOR_ID_INTEL, 0x150f, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Fiber)"}, + {PCI_VENDOR_ID_INTEL, 0x1510, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Backplane)"}, + {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Ext. PHY)"}, + {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Dual Gigabit Ethernet Controller (Copper)"}, + {PCI_VENDOR_ID_INTEL, UNPROG_DEVICE, OK, "Intel", "Unprogrammed 82580 Quad/Dual Gigabit Ethernet Controller"}, + {0}, +}; + +static int nicintel_ee_probe(struct flashctx *flash) +{ + if (nicintel_pci->device_id == UNPROG_DEVICE) + flash->chip->total_size = 16; /* Fall back to minimum supported size. */ + else { + uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC); + tmp = ((tmp >> EE_SIZE) & EE_SIZE_MASK); + switch (tmp) { + case 7: + flash->chip->total_size = 16; + break; + case 8: + flash->chip->total_size = 32; + break; + default: + msg_cerr("Unsupported chip size 0x%x\n", tmp); + return 0; + } + } + + flash->chip->page_size = PAGE_MASK + 1; + flash->chip->tested = TEST_OK_PREW; + flash->chip->gran = write_gran_1byte_implicit_erase; + flash->chip->block_erasers->eraseblocks[0].size = (PAGE_MASK + 1); + flash->chip->block_erasers->eraseblocks[0].count = (flash->chip->total_size * 1024) / (PAGE_MASK + 1); + + return 1; +} + +static int nicintel_ee_read_word(unsigned int addr, uint16_t *word) +{ + uint32_t tmp = BIT(EERD_START) | (addr << EERD_ADDR); + pci_mmio_writel(tmp, nicintel_eebar + EERD); + + /* Poll done flag. 10.000.000 cycles seem to be enough. */ + uint32_t i; + for (i = 0; i < 10000000; i++) { + tmp = pci_mmio_readl(nicintel_eebar + EERD); + if (tmp & BIT(EERD_DONE)) { + *word = (tmp >> EERD_DATA) & 0xffff; + return 0; + } + } + + return -1; +} + +static int nicintel_ee_read(struct flashctx *flash, uint8_t *buf, unsigned int addr, unsigned int len) +{ + uint16_t word; + + /* The NIC interface always reads 16 b words so we need to convert the address and handle odd address + * explicitly at the start (and also at the end in the loop below). */ + if (addr & 1) { + if (nicintel_ee_read_word(addr / 2, &word)) + return -1; + *buf++ = word & 0xff; + addr++; + len--; + } + + while (len > 0) { + if (nicintel_ee_read_word(addr / 2, &word)) + return -1; + *buf++ = word & 0xff; + addr++; + len--; + if (len > 0) { + *buf++ = (word >> 8) & 0xff; + addr++; + len--; + } + } + + return 0; +} + +static int nicintel_ee_bitset(int reg, int bit, bool val) +{ + uint32_t tmp; + + tmp = pci_mmio_readl(nicintel_eebar + reg); + if (val) + tmp |= BIT(bit); + else + tmp &= ~BIT(bit); + pci_mmio_writel(tmp, nicintel_eebar + reg); + + return -1; +} + +/* Shifts one byte out while receiving another one by bitbanging (denoted "direct access" in the datasheet). */ +static int nicintel_ee_bitbang(uint8_t mosi, uint8_t *miso) +{ + uint8_t out = 0x0; + + int i; + for (i = 7; i >= 0; i--) { + nicintel_ee_bitset(EEC, EE_SI, mosi & BIT(i)); + nicintel_ee_bitset(EEC, EE_SCK, 1); + if (miso != NULL) { + uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC); + if (tmp & BIT(EE_SO)) + out |= BIT(i); + } + nicintel_ee_bitset(EEC, EE_SCK, 0); + } + + if (miso != NULL) + *miso = out; + + return 0; +} + +/* Polls the WIP bit of the status register of the attached EEPROM via bitbanging. */ +static int nicintel_ee_ready(void) +{ + unsigned int i; + for (i = 0; i < 1000; i++) { + nicintel_ee_bitset(EEC, EE_CS, 0); + + nicintel_ee_bitbang(JEDEC_RDSR, NULL); + uint8_t rdsr; + nicintel_ee_bitbang(0x00, &rdsr); + + nicintel_ee_bitset(EEC, EE_CS, 1); + programmer_delay(1); + if (!(rdsr & SPI_SR_WIP)) { + return 0; + } + } + return -1; +} + +/* Requests direct access to the SPI pins. */ +static int nicintel_ee_req(void) +{ + uint32_t tmp; + nicintel_ee_bitset(EEC, EE_REQ, 1); + + tmp = pci_mmio_readl(nicintel_eebar + EEC); + if (!(tmp & BIT(EE_GNT))) { + msg_perr("Enabling eeprom access failed.\n"); + return 1; + } + + nicintel_ee_bitset(EEC, EE_SCK, 0); + return 0; +} + +static int nicintel_ee_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len) +{ + if (nicintel_ee_req()) + return -1; + + int ret = -1; + if (nicintel_ee_ready()) + goto out; + + while (len > 0) { + /* WREN */ + nicintel_ee_bitset(EEC, EE_CS, 0); + nicintel_ee_bitbang(JEDEC_WREN, NULL); + nicintel_ee_bitset(EEC, EE_CS, 1); + programmer_delay(1); + + /* data */ + nicintel_ee_bitset(EEC, EE_CS, 0); + nicintel_ee_bitbang(JEDEC_BYTE_PROGRAM, NULL); + nicintel_ee_bitbang((addr >> 8) & 0xff, NULL); + nicintel_ee_bitbang(addr & 0xff, NULL); + while (len > 0) { + nicintel_ee_bitbang((buf) ? *buf++ : 0xff, NULL); + len--; + addr++; + if (!(addr & PAGE_MASK)) + break; + } + nicintel_ee_bitset(EEC, EE_CS, 1); + programmer_delay(1); + if (nicintel_ee_ready()) + goto out; + } + ret = 0; +out: + nicintel_ee_bitset(EEC, EE_REQ, 0); /* Give up direct access. */ + return ret; +} + +static int nicintel_ee_erase(struct flashctx *flash, unsigned int addr, unsigned int len) +{ + return nicintel_ee_write(flash, NULL, addr, len); +} + +static const struct opaque_master opaque_master_nicintel_ee = { + .probe = nicintel_ee_probe, + .read = nicintel_ee_read, + .write = nicintel_ee_write, + .erase = nicintel_ee_erase, +}; + +static int nicintel_spi_shutdown(void *eecp) +{ + uint32_t old_eec = *(uint32_t *)eecp; + /* Request bitbanging and unselect the chip first to be safe. */ + if (nicintel_ee_req() || nicintel_ee_bitset(EEC, EE_CS, 1)) + return -1; + + /* Try to restore individual bits we care about. */ + int ret = nicintel_ee_bitset(EEC, EE_SCK, old_eec & BIT(EE_SCK)); + ret |= nicintel_ee_bitset(EEC, EE_SI, old_eec & BIT(EE_SI)); + ret |= nicintel_ee_bitset(EEC, EE_CS, old_eec & BIT(EE_CS)); + /* REQ will be cleared by hardware anyway after 2 seconds of inactivity on the SPI pins (3.3.2.1). */ + ret |= nicintel_ee_bitset(EEC, EE_REQ, old_eec & BIT(EE_REQ)); + + free(eecp); + return ret; +} + +int nicintel_ee_init(void) +{ + if (rget_io_perms()) + return 1; + + struct pci_dev *dev = pcidev_init(nics_intel_ee, PCI_BASE_ADDRESS_0); + if (!dev) + return 1; + + uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + if (!io_base_addr) + return 1; + + nicintel_eebar = rphysmap("Intel Gigabit NIC w/ SPI EEPROM", io_base_addr, MEMMAP_SIZE); + nicintel_pci = dev; + if (dev->device_id != UNPROG_DEVICE) { + uint32_t eec = pci_mmio_readl(nicintel_eebar + EEC); + + /* C.f. 3.3.1.5 for the detection mechanism (maybe? contradicting the EE_PRES definition), + * and 3.3.1.7 for possible recovery. */ + if (!(eec & BIT(EE_PRES))) { + msg_perr("Controller reports no EEPROM is present.\n"); + return 1; + } + + uint32_t *eecp = malloc(sizeof(uint32_t)); + if (eecp == NULL) + return 1; + *eecp = eec; + + if (register_shutdown(nicintel_spi_shutdown, eecp)) + return 1; + } + + return register_opaque_master(&opaque_master_nicintel_ee); +} Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Sun Jul 20 00:03:29 2014 (r1831) +++ trunk/programmer.h Mon Jul 28 22:35:21 2014 (r1832) @@ -84,6 +84,9 @@ #if CONFIG_NICINTEL_SPI == 1 PROGRAMMER_NICINTEL_SPI, #endif +#if CONFIG_NICINTEL_EEPROM == 1 + PROGRAMMER_NICINTEL_EEPROM, +#endif #if CONFIG_OGP_SPI == 1 PROGRAMMER_OGP_SPI, #endif @@ -416,6 +419,12 @@ extern const struct dev_entry nics_intel_spi[]; #endif +/* nicintel_eeprom.c */ +#if CONFIG_NICINTEL_EEPROM == 1 +int nicintel_ee_init(void); +extern const struct dev_entry nics_intel_ee[]; +#endif + /* ogp_spi.c */ #if CONFIG_OGP_SPI == 1 int ogp_spi_init(void);

1 0

Re: [flashrom] [PATCH] Add new programmer for SPI EEPROMs attached to Intel 82580 NICs.
by Ricardo Ribalda Delgado 28 Jul '14

28 Jul '14

Tested-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> Hello I have tested it on 32kb mode: root@qt5022:~# time ./flashrom -p nicintel_eeprom:pci=02:00.0 -r kk.out flashrom v0.9.7-r1831 on Linux 3.16.0-rc6-qtec-standard+ (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found Programmer flash chip "Opaque flash chip" (32 kB, Programmer-specific) on nicintel_eeprom. Reading flash... done. real 0m1.645s user 0m1.631s sys 0m0.014s root@qt5022:~# time ./flashrom -p nicintel_eeprom:pci=02:00.0 -E flashrom v0.9.7-r1831 on Linux 3.16.0-rc6-qtec-standard+ (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found Programmer flash chip "Opaque flash chip" (32 kB, Programmer-specific) on nicintel_eeprom. Erasing and writing flash chip... Erase/write done. real 0m3.926s user 0m3.905s sys 0m0.021s root@qt5022:~# time ./flashrom -p nicintel_eeprom:pci=02:00.0 -w kk.out flashrom v0.9.7-r1831 on Linux 3.16.0-rc6-qtec-standard+ (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found Programmer flash chip "Opaque flash chip" (32 kB, Programmer-specific) on nicintel_eeprom. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. real 0m3.773s user 0m3.753s sys 0m0.020s On Mon, Jul 28, 2014 at 2:10 AM, Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> wrote: > This patch lets you read and write the EEPROM on 82580-based gigabit NIC > cards. So far it has been tested on copper NICs only, but other variants > employing this controller should work too. > It is a nice substitution for the official eeupdate tool. > > Speed is quite decent: less than 5 seconds for erases or writes. > > Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> > Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> > --- > Rebased on r1831 because that breaks the previous version. > Ricardo, if you don't have time or motivation to re-test this then > please make a short note. I'll commit this patch then without any > tested state, thanks. > > Makefile | 14 +++ > flashrom.8.tmpl | 16 ++- > flashrom.c | 12 ++ > nicintel_eeprom.c | 331 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ > programmer.h | 9 ++ > 5 files changed, 379 insertions(+), 3 deletions(-) > create mode 100644 nicintel_eeprom.c > > diff --git a/Makefile b/Makefile > index 7a48889..64798c9 100644 > --- a/Makefile > +++ b/Makefile > @@ -227,6 +227,11 @@ UNSUPPORTED_FEATURES += CONFIG_NICINTEL=yes > else > override CONFIG_NICINTEL = no > endif > +ifeq ($(CONFIG_NICINTEL_EEPROM), yes) > +UNSUPPORTED_FEATURES += CONFIG_NICINTEL_EEPROM=yes > +else > +override CONFIG_NICINTEL_EEPROM = no > +endif > ifeq ($(CONFIG_NICINTEL_SPI), yes) > UNSUPPORTED_FEATURES += CONFIG_NICINTEL_SPI=yes > else > @@ -426,6 +431,9 @@ CONFIG_NICINTEL ?= yes > # Always enable SPI on Intel NICs for now. > CONFIG_NICINTEL_SPI ?= yes > > +# Always enable EEPROM on Intel NICs for now. > +CONFIG_NICINTEL_EEPROM ?= yes > + > # Always enable SPI on OGP cards for now. > CONFIG_OGP_SPI ?= yes > > @@ -626,6 +634,12 @@ PROGRAMMER_OBJS += nicintel_spi.o > NEED_PCI := yes > endif > > +ifeq ($(CONFIG_NICINTEL_EEPROM), yes) > +FEATURE_CFLAGS += -D'CONFIG_NICINTEL_EEPROM=1' > +PROGRAMMER_OBJS += nicintel_eeprom.o > +NEED_PCI := yes > +endif > + > ifeq ($(CONFIG_OGP_SPI), yes) > FEATURE_CFLAGS += -D'CONFIG_OGP_SPI=1' > PROGRAMMER_OBJS += ogp_spi.o > diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl > index 0b4867d..153591a 100644 > --- a/flashrom.8.tmpl > +++ b/flashrom.8.tmpl > @@ -225,6 +225,8 @@ bitbanging adapter) > .sp > .BR "* usbblaster_spi" " (for SPI flash ROMs attached to an Altera USB-Blaster compatible cable)" > .sp > +.BR "* nicintel_eeprom" " (for SPI EEPROMs on Intel Gigabit network cards)" > +.sp > Some programmers have optional or mandatory parameters which are described > in detail in the > .B PROGRAMMER SPECIFIC INFO > @@ -591,7 +593,7 @@ syntax where > .B content > is an 8-bit hexadecimal value. > .SS > -.BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel"\ > +.BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel", " nicintel_eeprom"\ > , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii"\ > , " satamv" , " atahpt" ", " atavia " and " it8212 " programmers > These programmers have an option to specify the PCI address of the card > @@ -625,6 +627,14 @@ For more information please see > .nh > .B http://flashrom.org/VT6421A > .SS > +.BR "nicintel_eeprom " programmer > +This is the first programmer module in flashrom that does not provide access to NOR flash chips but EEPROMs > +mounted on gigabit Ethernet cards based on Intel's 82580 NIC. Because EEPROMs normally do not announce their > +size nor allow to be identified, the controller relies on correct size values written to predefined addresses > +within the chip. Flashrom follows this scheme but assumes the minimum size of 16 kB (128 kb) if an unprogrammed > +EEPROM/card is detected. Intel specifies following EEPROMs to be compatible: Atmel AT25128, AT25256, Micron (ST) > +M95128, M95256 and OnSemi (Catalyst) CAT25CS128. > +.SS > .BR "ft2232_spi " programmer > An optional parameter specifies the controller > type and channel/interface/port it should support. For that you have to use the > @@ -922,8 +932,8 @@ need PCI configuration space access and raw memory access. > .B rayer_spi > needs raw I/O port access. > .sp > -.B satasii > -needs PCI configuration space read access and raw memory access. > +.BR satasii ", " nicintel ", " nicintel_eeprom " and " nicintel_spi > +need PCI configuration space read access and raw memory access. > .sp > .B satamv > needs PCI configuration space read access, raw I/O port access and raw memory > diff --git a/flashrom.c b/flashrom.c > index 83bc89a..fc8b073 100644 > --- a/flashrom.c > +++ b/flashrom.c > @@ -297,6 +297,18 @@ const struct programmer_entry programmer_table[] = { > }, > #endif > > +#if CONFIG_NICINTEL_EEPROM == 1 > + { > + .name = "nicintel_eeprom", > + .type = PCI, > + .devs.dev = nics_intel_ee, > + .init = nicintel_ee_init, > + .map_flash_region = fallback_map, > + .unmap_flash_region = fallback_unmap, > + .delay = internal_delay, > + }, > +#endif > + > #if CONFIG_OGP_SPI == 1 > { > .name = "ogp_spi", > diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c > new file mode 100644 > index 0000000..44bc773 > --- /dev/null > +++ b/nicintel_eeprom.c > @@ -0,0 +1,331 @@ > +/* > + * This file is part of the flashrom project. > + * > + * Copyright (C) 2013 Ricardo Ribalda - Qtechnology A/S > + * Copyright (C) 2011, 2014 Stefan Tauner > + * > + * Based on nicinctel_spi.c and ichspi.c > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; version 2 of the License. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see http://www.gnu.org/licenses/. > + */ > + > +/* > + * Datasheet: Intel 82580 Quad/Dual Gigabit Ethernet LAN Controller Datasheet > + * 3.3.1.4: General EEPROM Software Access > + * 4.7: Access to shared resources (FIXME: we should probably use this semaphore interface) > + * 7.4: Register Descriptions > + */ > + > +#include <stdlib.h> > +#include <unistd.h> > +#include "flash.h" > +#include "spi.h" > +#include "programmer.h" > +#include "hwaccess.h" > + > +#define PCI_VENDOR_ID_INTEL 0x8086 > +#define MEMMAP_SIZE (0x14 + 3) /* Only EEC and EERD are needed. */ > + > +#define EEC 0x10 /* EEPROM/Flash Control Register */ > +#define EERD 0x14 /* EEPROM Read Register */ > + > +/* EPROM/Flash Control Register bits */ > +#define EE_SCK 0 > +#define EE_CS 1 > +#define EE_SI 2 > +#define EE_SO 3 > +#define EE_REQ 6 > +#define EE_GNT 7 > +#define EE_PRES 8 > +#define EE_SIZE 11 > +#define EE_SIZE_MASK 0xf > + > +/* EEPROM Read Register bits */ > +#define EERD_START 0 > +#define EERD_DONE 1 > +#define EERD_ADDR 2 > +#define EERD_DATA 16 > + > +#define BIT(x) (1<<x) > +#define PAGE_MASK 0x3f > + > +static uint8_t *nicintel_eebar; > +static struct pci_dev *nicintel_pci; > + > +#define UNPROG_DEVICE 0x1509 > + > +const struct dev_entry nics_intel_ee[] = { > + {PCI_VENDOR_ID_INTEL, 0x150e, OK, "Intel", "82580 Quad Gigabit Ethernet Controller (Copper)"}, > + {PCI_VENDOR_ID_INTEL, 0x150f, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Fiber)"}, > + {PCI_VENDOR_ID_INTEL, 0x1510, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Backplane)"}, > + {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Ext. PHY)"}, > + {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Dual Gigabit Ethernet Controller (Copper)"}, > + {PCI_VENDOR_ID_INTEL, UNPROG_DEVICE, OK, "Intel", "Unprogrammed 82580 Quad/Dual Gigabit Ethernet Controller"}, > + {0}, > +}; > + > +static int nicintel_ee_probe(struct flashctx *flash) > +{ > + if (nicintel_pci->device_id == UNPROG_DEVICE) > + flash->chip->total_size = 16; /* Fall back to minimum supported size. */ > + else { > + uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC); > + tmp = ((tmp >> EE_SIZE) & EE_SIZE_MASK); > + switch (tmp) { > + case 7: > + flash->chip->total_size = 16; > + break; > + case 8: > + flash->chip->total_size = 32; > + break; > + default: > + msg_cerr("Unsupported chip size 0x%x\n", tmp); > + return 0; > + } > + } > + > + flash->chip->page_size = PAGE_MASK + 1; > + flash->chip->tested = TEST_OK_PREW; > + flash->chip->gran = write_gran_1byte_implicit_erase; > + flash->chip->block_erasers->eraseblocks[0].size = (PAGE_MASK + 1); > + flash->chip->block_erasers->eraseblocks[0].count = (flash->chip->total_size * 1024) / (PAGE_MASK + 1); > + > + return 1; > +} > + > +static int nicintel_ee_read_word(unsigned int addr, uint16_t *word) > +{ > + uint32_t tmp = BIT(EERD_START) | (addr << EERD_ADDR); > + pci_mmio_writel(tmp, nicintel_eebar + EERD); > + > + /* Poll done flag. 10.000.000 cycles seem to be enough. */ > + uint32_t i; > + for (i = 0; i < 10000000; i++) { > + tmp = pci_mmio_readl(nicintel_eebar + EERD); > + if (tmp & BIT(EERD_DONE)) { > + *word = (tmp >> EERD_DATA) & 0xffff; > + return 0; > + } > + } > + > + return -1; > +} > + > +static int nicintel_ee_read(struct flashctx *flash, uint8_t *buf, unsigned int addr, unsigned int len) > +{ > + uint16_t word; > + > + /* The NIC interface always reads 16 b words so we need to convert the address and handle odd address > + * explicitly at the start (and also at the end in the loop below). */ > + if (addr & 1) { > + if (nicintel_ee_read_word(addr / 2, &word)) > + return -1; > + *buf++ = word & 0xff; > + addr++; > + len--; > + } > + > + while (len > 0) { > + if (nicintel_ee_read_word(addr / 2, &word)) > + return -1; > + *buf++ = word & 0xff; > + addr++; > + len--; > + if (len > 0) { > + *buf++ = (word >> 8) & 0xff; > + addr++; > + len--; > + } > + } > + > + return 0; > +} > + > +static int nicintel_ee_bitset(int reg, int bit, bool val) > +{ > + uint32_t tmp; > + > + tmp = pci_mmio_readl(nicintel_eebar + reg); > + if (val) > + tmp |= BIT(bit); > + else > + tmp &= ~BIT(bit); > + pci_mmio_writel(tmp, nicintel_eebar + reg); > + > + return -1; > +} > + > +/* Shifts one byte out while receiving another one by bitbanging (denoted "direct access" in the datasheet). */ > +static int nicintel_ee_bitbang(uint8_t mosi, uint8_t *miso) > +{ > + uint8_t out = 0x0; > + > + int i; > + for (i = 7; i >= 0; i--) { > + nicintel_ee_bitset(EEC, EE_SI, mosi & BIT(i)); > + nicintel_ee_bitset(EEC, EE_SCK, 1); > + if (miso != NULL) { > + uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC); > + if (tmp & BIT(EE_SO)) > + out |= BIT(i); > + } > + nicintel_ee_bitset(EEC, EE_SCK, 0); > + } > + > + if (miso != NULL) > + *miso = out; > + > + return 0; > +} > + > +/* Polls the WIP bit of the status register of the attached EEPROM via bitbanging. */ > +static int nicintel_ee_ready(void) > +{ > + unsigned int i; > + for (i = 0; i < 1000; i++) { > + nicintel_ee_bitset(EEC, EE_CS, 0); > + > + nicintel_ee_bitbang(JEDEC_RDSR, NULL); > + uint8_t rdsr; > + nicintel_ee_bitbang(0x00, &rdsr); > + > + nicintel_ee_bitset(EEC, EE_CS, 1); > + programmer_delay(1); > + if (!(rdsr & SPI_SR_WIP)) { > + return 0; > + } > + } > + return -1; > +} > + > +/* Requests direct access to the SPI pins. */ > +static int nicintel_ee_req(void) > +{ > + uint32_t tmp; > + nicintel_ee_bitset(EEC, EE_REQ, 1); > + > + tmp = pci_mmio_readl(nicintel_eebar + EEC); > + if (!(tmp & BIT(EE_GNT))) { > + msg_perr("Enabling eeprom access failed.\n"); > + return 1; > + } > + > + nicintel_ee_bitset(EEC, EE_SCK, 0); > + return 0; > +} > + > +static int nicintel_ee_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len) > +{ > + if (nicintel_ee_req()) > + return -1; > + > + int ret = -1; > + if (nicintel_ee_ready()) > + goto out; > + > + while (len > 0) { > + /* WREN */ > + nicintel_ee_bitset(EEC, EE_CS, 0); > + nicintel_ee_bitbang(JEDEC_WREN, NULL); > + nicintel_ee_bitset(EEC, EE_CS, 1); > + programmer_delay(1); > + > + /* data */ > + nicintel_ee_bitset(EEC, EE_CS, 0); > + nicintel_ee_bitbang(JEDEC_BYTE_PROGRAM, NULL); > + nicintel_ee_bitbang((addr >> 8) & 0xff, NULL); > + nicintel_ee_bitbang(addr & 0xff, NULL); > + while (len > 0) { > + nicintel_ee_bitbang((buf) ? *buf++ : 0xff, NULL); > + len--; > + addr++; > + if (!(addr & PAGE_MASK)) > + break; > + } > + nicintel_ee_bitset(EEC, EE_CS, 1); > + programmer_delay(1); > + if (nicintel_ee_ready()) > + goto out; > + } > + ret = 0; > +out: > + nicintel_ee_bitset(EEC, EE_REQ, 0); /* Give up direct access. */ > + return ret; > +} > + > +static int nicintel_ee_erase(struct flashctx *flash, unsigned int addr, unsigned int len) > +{ > + return nicintel_ee_write(flash, NULL, addr, len); > +} > + > +static const struct opaque_master opaque_master_nicintel_ee = { > + .probe = nicintel_ee_probe, > + .read = nicintel_ee_read, > + .write = nicintel_ee_write, > + .erase = nicintel_ee_erase, > +}; > + > +static int nicintel_spi_shutdown(void *eecp) > +{ > + uint32_t old_eec = *(uint32_t *)eecp; > + /* Request bitbanging and unselect the chip first to be safe. */ > + if (nicintel_ee_req() || nicintel_ee_bitset(EEC, EE_CS, 1)) > + return -1; > + > + /* Try to restore individual bits we care about. */ > + int ret = nicintel_ee_bitset(EEC, EE_SCK, old_eec & BIT(EE_SCK)); > + ret |= nicintel_ee_bitset(EEC, EE_SI, old_eec & BIT(EE_SI)); > + ret |= nicintel_ee_bitset(EEC, EE_CS, old_eec & BIT(EE_CS)); > + /* REQ will be cleared by hardware anyway after 2 seconds of inactivity on the SPI pins (3.3.2.1). */ > + ret |= nicintel_ee_bitset(EEC, EE_REQ, old_eec & BIT(EE_REQ)); > + > + free(eecp); > + return ret; > +} > + > +int nicintel_ee_init(void) > +{ > + if (rget_io_perms()) > + return 1; > + > + struct pci_dev *dev = pcidev_init(nics_intel_ee, PCI_BASE_ADDRESS_0); > + if (!dev) > + return 1; > + > + uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); > + if (!io_base_addr) > + return 1; > + > + nicintel_eebar = rphysmap("Intel Gigabit NIC w/ SPI EEPROM", io_base_addr, MEMMAP_SIZE); > + nicintel_pci = dev; > + if (dev->device_id != UNPROG_DEVICE) { > + uint32_t eec = pci_mmio_readl(nicintel_eebar + EEC); > + > + /* C.f. 3.3.1.5 for the detection mechanism (maybe? contradicting the EE_PRES definition), > + * and 3.3.1.7 for possible recovery. */ > + if (!(eec & BIT(EE_PRES))) { > + msg_perr("Controller reports no EEPROM is present.\n"); > + return 1; > + } > + > + uint32_t *eecp = malloc(sizeof(uint32_t)); > + if (eecp == NULL) > + return 1; > + *eecp = eec; > + > + if (register_shutdown(nicintel_spi_shutdown, eecp)) > + return 1; > + } > + > + return register_opaque_master(&opaque_master_nicintel_ee); > +} > diff --git a/programmer.h b/programmer.h > index 093240b..3ad553a 100644 > --- a/programmer.h > +++ b/programmer.h > @@ -84,6 +84,9 @@ enum programmer { > #if CONFIG_NICINTEL_SPI == 1 > PROGRAMMER_NICINTEL_SPI, > #endif > +#if CONFIG_NICINTEL_EEPROM == 1 > + PROGRAMMER_NICINTEL_EEPROM, > +#endif > #if CONFIG_OGP_SPI == 1 > PROGRAMMER_OGP_SPI, > #endif > @@ -416,6 +419,12 @@ int nicintel_spi_init(void); > extern const struct dev_entry nics_intel_spi[]; > #endif > > +/* nicintel_eeprom.c */ > +#if CONFIG_NICINTEL_EEPROM == 1 > +int nicintel_ee_init(void); > +extern const struct dev_entry nics_intel_ee[]; > +#endif > + > /* ogp_spi.c */ > #if CONFIG_OGP_SPI == 1 > int ogp_spi_init(void); > -- > Kind regards, Stefan Tauner > -- Ricardo Ribalda

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[PATCH] Add new programmer for SPI EEPROMs attached to Intel 82580 NICs.
by Stefan Tauner 27 Jul '14

27 Jul '14

This patch lets you read and write the EEPROM on 82580-based gigabit NIC cards. So far it has been tested on copper NICs only, but other variants employing this controller should work too. It is a nice substitution for the official eeupdate tool. Speed is quite decent: less than 5 seconds for erases or writes. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- Rebased on r1831 because that breaks the previous version. Ricardo, if you don't have time or motivation to re-test this then please make a short note. I'll commit this patch then without any tested state, thanks. Makefile | 14 +++ flashrom.8.tmpl | 16 ++- flashrom.c | 12 ++ nicintel_eeprom.c | 331 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ programmer.h | 9 ++ 5 files changed, 379 insertions(+), 3 deletions(-) create mode 100644 nicintel_eeprom.c diff --git a/Makefile b/Makefile index 7a48889..64798c9 100644 --- a/Makefile +++ b/Makefile @@ -227,6 +227,11 @@ UNSUPPORTED_FEATURES += CONFIG_NICINTEL=yes else override CONFIG_NICINTEL = no endif +ifeq ($(CONFIG_NICINTEL_EEPROM), yes) +UNSUPPORTED_FEATURES += CONFIG_NICINTEL_EEPROM=yes +else +override CONFIG_NICINTEL_EEPROM = no +endif ifeq ($(CONFIG_NICINTEL_SPI), yes) UNSUPPORTED_FEATURES += CONFIG_NICINTEL_SPI=yes else @@ -426,6 +431,9 @@ CONFIG_NICINTEL ?= yes # Always enable SPI on Intel NICs for now. CONFIG_NICINTEL_SPI ?= yes +# Always enable EEPROM on Intel NICs for now. +CONFIG_NICINTEL_EEPROM ?= yes + # Always enable SPI on OGP cards for now. CONFIG_OGP_SPI ?= yes @@ -626,6 +634,12 @@ PROGRAMMER_OBJS += nicintel_spi.o NEED_PCI := yes endif +ifeq ($(CONFIG_NICINTEL_EEPROM), yes) +FEATURE_CFLAGS += -D'CONFIG_NICINTEL_EEPROM=1' +PROGRAMMER_OBJS += nicintel_eeprom.o +NEED_PCI := yes +endif + ifeq ($(CONFIG_OGP_SPI), yes) FEATURE_CFLAGS += -D'CONFIG_OGP_SPI=1' PROGRAMMER_OBJS += ogp_spi.o diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index 0b4867d..153591a 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -225,6 +225,8 @@ bitbanging adapter) .sp .BR "* usbblaster_spi" " (for SPI flash ROMs attached to an Altera USB-Blaster compatible cable)" .sp +.BR "* nicintel_eeprom" " (for SPI EEPROMs on Intel Gigabit network cards)" +.sp Some programmers have optional or mandatory parameters which are described in detail in the .B PROGRAMMER SPECIFIC INFO @@ -591,7 +593,7 @@ syntax where .B content is an 8-bit hexadecimal value. .SS -.BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel"\ +.BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel", " nicintel_eeprom"\ , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii"\ , " satamv" , " atahpt" ", " atavia " and " it8212 " programmers These programmers have an option to specify the PCI address of the card @@ -625,6 +627,14 @@ For more information please see .nh .B http://flashrom.org/VT6421A .SS +.BR "nicintel_eeprom " programmer +This is the first programmer module in flashrom that does not provide access to NOR flash chips but EEPROMs +mounted on gigabit Ethernet cards based on Intel's 82580 NIC. Because EEPROMs normally do not announce their +size nor allow to be identified, the controller relies on correct size values written to predefined addresses +within the chip. Flashrom follows this scheme but assumes the minimum size of 16 kB (128 kb) if an unprogrammed +EEPROM/card is detected. Intel specifies following EEPROMs to be compatible: Atmel AT25128, AT25256, Micron (ST) +M95128, M95256 and OnSemi (Catalyst) CAT25CS128. +.SS .BR "ft2232_spi " programmer An optional parameter specifies the controller type and channel/interface/port it should support. For that you have to use the @@ -922,8 +932,8 @@ need PCI configuration space access and raw memory access. .B rayer_spi needs raw I/O port access. .sp -.B satasii -needs PCI configuration space read access and raw memory access. +.BR satasii ", " nicintel ", " nicintel_eeprom " and " nicintel_spi +need PCI configuration space read access and raw memory access. .sp .B satamv needs PCI configuration space read access, raw I/O port access and raw memory diff --git a/flashrom.c b/flashrom.c index 83bc89a..fc8b073 100644 --- a/flashrom.c +++ b/flashrom.c @@ -297,6 +297,18 @@ const struct programmer_entry programmer_table[] = { }, #endif +#if CONFIG_NICINTEL_EEPROM == 1 + { + .name = "nicintel_eeprom", + .type = PCI, + .devs.dev = nics_intel_ee, + .init = nicintel_ee_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + #if CONFIG_OGP_SPI == 1 { .name = "ogp_spi", diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c new file mode 100644 index 0000000..44bc773 --- /dev/null +++ b/nicintel_eeprom.c @@ -0,0 +1,331 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2013 Ricardo Ribalda - Qtechnology A/S + * Copyright (C) 2011, 2014 Stefan Tauner + * + * Based on nicinctel_spi.c and ichspi.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +/* + * Datasheet: Intel 82580 Quad/Dual Gigabit Ethernet LAN Controller Datasheet + * 3.3.1.4: General EEPROM Software Access + * 4.7: Access to shared resources (FIXME: we should probably use this semaphore interface) + * 7.4: Register Descriptions + */ + +#include <stdlib.h> +#include <unistd.h> +#include "flash.h" +#include "spi.h" +#include "programmer.h" +#include "hwaccess.h" + +#define PCI_VENDOR_ID_INTEL 0x8086 +#define MEMMAP_SIZE (0x14 + 3) /* Only EEC and EERD are needed. */ + +#define EEC 0x10 /* EEPROM/Flash Control Register */ +#define EERD 0x14 /* EEPROM Read Register */ + +/* EPROM/Flash Control Register bits */ +#define EE_SCK 0 +#define EE_CS 1 +#define EE_SI 2 +#define EE_SO 3 +#define EE_REQ 6 +#define EE_GNT 7 +#define EE_PRES 8 +#define EE_SIZE 11 +#define EE_SIZE_MASK 0xf + +/* EEPROM Read Register bits */ +#define EERD_START 0 +#define EERD_DONE 1 +#define EERD_ADDR 2 +#define EERD_DATA 16 + +#define BIT(x) (1<<x) +#define PAGE_MASK 0x3f + +static uint8_t *nicintel_eebar; +static struct pci_dev *nicintel_pci; + +#define UNPROG_DEVICE 0x1509 + +const struct dev_entry nics_intel_ee[] = { + {PCI_VENDOR_ID_INTEL, 0x150e, OK, "Intel", "82580 Quad Gigabit Ethernet Controller (Copper)"}, + {PCI_VENDOR_ID_INTEL, 0x150f, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Fiber)"}, + {PCI_VENDOR_ID_INTEL, 0x1510, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Backplane)"}, + {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Ext. PHY)"}, + {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Dual Gigabit Ethernet Controller (Copper)"}, + {PCI_VENDOR_ID_INTEL, UNPROG_DEVICE, OK, "Intel", "Unprogrammed 82580 Quad/Dual Gigabit Ethernet Controller"}, + {0}, +}; + +static int nicintel_ee_probe(struct flashctx *flash) +{ + if (nicintel_pci->device_id == UNPROG_DEVICE) + flash->chip->total_size = 16; /* Fall back to minimum supported size. */ + else { + uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC); + tmp = ((tmp >> EE_SIZE) & EE_SIZE_MASK); + switch (tmp) { + case 7: + flash->chip->total_size = 16; + break; + case 8: + flash->chip->total_size = 32; + break; + default: + msg_cerr("Unsupported chip size 0x%x\n", tmp); + return 0; + } + } + + flash->chip->page_size = PAGE_MASK + 1; + flash->chip->tested = TEST_OK_PREW; + flash->chip->gran = write_gran_1byte_implicit_erase; + flash->chip->block_erasers->eraseblocks[0].size = (PAGE_MASK + 1); + flash->chip->block_erasers->eraseblocks[0].count = (flash->chip->total_size * 1024) / (PAGE_MASK + 1); + + return 1; +} + +static int nicintel_ee_read_word(unsigned int addr, uint16_t *word) +{ + uint32_t tmp = BIT(EERD_START) | (addr << EERD_ADDR); + pci_mmio_writel(tmp, nicintel_eebar + EERD); + + /* Poll done flag. 10.000.000 cycles seem to be enough. */ + uint32_t i; + for (i = 0; i < 10000000; i++) { + tmp = pci_mmio_readl(nicintel_eebar + EERD); + if (tmp & BIT(EERD_DONE)) { + *word = (tmp >> EERD_DATA) & 0xffff; + return 0; + } + } + + return -1; +} + +static int nicintel_ee_read(struct flashctx *flash, uint8_t *buf, unsigned int addr, unsigned int len) +{ + uint16_t word; + + /* The NIC interface always reads 16 b words so we need to convert the address and handle odd address + * explicitly at the start (and also at the end in the loop below). */ + if (addr & 1) { + if (nicintel_ee_read_word(addr / 2, &word)) + return -1; + *buf++ = word & 0xff; + addr++; + len--; + } + + while (len > 0) { + if (nicintel_ee_read_word(addr / 2, &word)) + return -1; + *buf++ = word & 0xff; + addr++; + len--; + if (len > 0) { + *buf++ = (word >> 8) & 0xff; + addr++; + len--; + } + } + + return 0; +} + +static int nicintel_ee_bitset(int reg, int bit, bool val) +{ + uint32_t tmp; + + tmp = pci_mmio_readl(nicintel_eebar + reg); + if (val) + tmp |= BIT(bit); + else + tmp &= ~BIT(bit); + pci_mmio_writel(tmp, nicintel_eebar + reg); + + return -1; +} + +/* Shifts one byte out while receiving another one by bitbanging (denoted "direct access" in the datasheet). */ +static int nicintel_ee_bitbang(uint8_t mosi, uint8_t *miso) +{ + uint8_t out = 0x0; + + int i; + for (i = 7; i >= 0; i--) { + nicintel_ee_bitset(EEC, EE_SI, mosi & BIT(i)); + nicintel_ee_bitset(EEC, EE_SCK, 1); + if (miso != NULL) { + uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC); + if (tmp & BIT(EE_SO)) + out |= BIT(i); + } + nicintel_ee_bitset(EEC, EE_SCK, 0); + } + + if (miso != NULL) + *miso = out; + + return 0; +} + +/* Polls the WIP bit of the status register of the attached EEPROM via bitbanging. */ +static int nicintel_ee_ready(void) +{ + unsigned int i; + for (i = 0; i < 1000; i++) { + nicintel_ee_bitset(EEC, EE_CS, 0); + + nicintel_ee_bitbang(JEDEC_RDSR, NULL); + uint8_t rdsr; + nicintel_ee_bitbang(0x00, &rdsr); + + nicintel_ee_bitset(EEC, EE_CS, 1); + programmer_delay(1); + if (!(rdsr & SPI_SR_WIP)) { + return 0; + } + } + return -1; +} + +/* Requests direct access to the SPI pins. */ +static int nicintel_ee_req(void) +{ + uint32_t tmp; + nicintel_ee_bitset(EEC, EE_REQ, 1); + + tmp = pci_mmio_readl(nicintel_eebar + EEC); + if (!(tmp & BIT(EE_GNT))) { + msg_perr("Enabling eeprom access failed.\n"); + return 1; + } + + nicintel_ee_bitset(EEC, EE_SCK, 0); + return 0; +} + +static int nicintel_ee_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len) +{ + if (nicintel_ee_req()) + return -1; + + int ret = -1; + if (nicintel_ee_ready()) + goto out; + + while (len > 0) { + /* WREN */ + nicintel_ee_bitset(EEC, EE_CS, 0); + nicintel_ee_bitbang(JEDEC_WREN, NULL); + nicintel_ee_bitset(EEC, EE_CS, 1); + programmer_delay(1); + + /* data */ + nicintel_ee_bitset(EEC, EE_CS, 0); + nicintel_ee_bitbang(JEDEC_BYTE_PROGRAM, NULL); + nicintel_ee_bitbang((addr >> 8) & 0xff, NULL); + nicintel_ee_bitbang(addr & 0xff, NULL); + while (len > 0) { + nicintel_ee_bitbang((buf) ? *buf++ : 0xff, NULL); + len--; + addr++; + if (!(addr & PAGE_MASK)) + break; + } + nicintel_ee_bitset(EEC, EE_CS, 1); + programmer_delay(1); + if (nicintel_ee_ready()) + goto out; + } + ret = 0; +out: + nicintel_ee_bitset(EEC, EE_REQ, 0); /* Give up direct access. */ + return ret; +} + +static int nicintel_ee_erase(struct flashctx *flash, unsigned int addr, unsigned int len) +{ + return nicintel_ee_write(flash, NULL, addr, len); +} + +static const struct opaque_master opaque_master_nicintel_ee = { + .probe = nicintel_ee_probe, + .read = nicintel_ee_read, + .write = nicintel_ee_write, + .erase = nicintel_ee_erase, +}; + +static int nicintel_spi_shutdown(void *eecp) +{ + uint32_t old_eec = *(uint32_t *)eecp; + /* Request bitbanging and unselect the chip first to be safe. */ + if (nicintel_ee_req() || nicintel_ee_bitset(EEC, EE_CS, 1)) + return -1; + + /* Try to restore individual bits we care about. */ + int ret = nicintel_ee_bitset(EEC, EE_SCK, old_eec & BIT(EE_SCK)); + ret |= nicintel_ee_bitset(EEC, EE_SI, old_eec & BIT(EE_SI)); + ret |= nicintel_ee_bitset(EEC, EE_CS, old_eec & BIT(EE_CS)); + /* REQ will be cleared by hardware anyway after 2 seconds of inactivity on the SPI pins (3.3.2.1). */ + ret |= nicintel_ee_bitset(EEC, EE_REQ, old_eec & BIT(EE_REQ)); + + free(eecp); + return ret; +} + +int nicintel_ee_init(void) +{ + if (rget_io_perms()) + return 1; + + struct pci_dev *dev = pcidev_init(nics_intel_ee, PCI_BASE_ADDRESS_0); + if (!dev) + return 1; + + uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + if (!io_base_addr) + return 1; + + nicintel_eebar = rphysmap("Intel Gigabit NIC w/ SPI EEPROM", io_base_addr, MEMMAP_SIZE); + nicintel_pci = dev; + if (dev->device_id != UNPROG_DEVICE) { + uint32_t eec = pci_mmio_readl(nicintel_eebar + EEC); + + /* C.f. 3.3.1.5 for the detection mechanism (maybe? contradicting the EE_PRES definition), + * and 3.3.1.7 for possible recovery. */ + if (!(eec & BIT(EE_PRES))) { + msg_perr("Controller reports no EEPROM is present.\n"); + return 1; + } + + uint32_t *eecp = malloc(sizeof(uint32_t)); + if (eecp == NULL) + return 1; + *eecp = eec; + + if (register_shutdown(nicintel_spi_shutdown, eecp)) + return 1; + } + + return register_opaque_master(&opaque_master_nicintel_ee); +} diff --git a/programmer.h b/programmer.h index 093240b..3ad553a 100644 --- a/programmer.h +++ b/programmer.h @@ -84,6 +84,9 @@ enum programmer { #if CONFIG_NICINTEL_SPI == 1 PROGRAMMER_NICINTEL_SPI, #endif +#if CONFIG_NICINTEL_EEPROM == 1 + PROGRAMMER_NICINTEL_EEPROM, +#endif #if CONFIG_OGP_SPI == 1 PROGRAMMER_OGP_SPI, #endif @@ -416,6 +419,12 @@ int nicintel_spi_init(void); extern const struct dev_entry nics_intel_spi[]; #endif +/* nicintel_eeprom.c */ +#if CONFIG_NICINTEL_EEPROM == 1 +int nicintel_ee_init(void); +extern const struct dev_entry nics_intel_ee[]; +#endif + /* ogp_spi.c */ #if CONFIG_OGP_SPI == 1 int ogp_spi_init(void); -- Kind regards, Stefan Tauner

1 0

Re: [flashrom] [PATCH] Add Intel Bay Trail, Rangeley/Avoton and Wildcat Point support.
by Stefan Tauner 21 Jul '14

21 Jul '14

On Sun, 22 Jun 2014 01:46:05 +0200 Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> wrote: > Martin: please sign off this patch in a reply as well because you > forgot to sign off previouslly. Ping -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

[PATCH] Trivial: fix spelling in comments and a string
by dforsi＠gmail.com 21 Jul '14

21 Jul '14

This fixes 5 errors found running codespell on the sources. Codespell is at https://github.com/lucasdemarchi/codespell Signed-off-by: Daniele Forsi <dforsi(a)gmail.com> Index: Documentation/serprog-protocol.txt =================================================================== --- Documentation/serprog-protocol.txt (revision 1830) +++ Documentation/serprog-protocol.txt (working copy) @@ -74,7 +74,7 @@ Send and receive bytes via SPI. Maximum slen is Q_WRNMAXLEN in case Q_BUSTYPE returns SPI only or S_BUSTYPE was used to set SPI exclusively before. Same for rlen and Q_RDNMAXLEN. - This operation is immediate, meaning it doesnt use the operation buffer. + This operation is immediate, meaning it doesn't use the operation buffer. 0x14 (S_SPI_FREQ): Set the SPI clock frequency. The 32-bit value indicates the requested frequency in Hertz. Value 0 is reserved and should Index: atavia.c =================================================================== --- atavia.c (revision 1830) +++ atavia.c (working copy) @@ -113,7 +113,7 @@ } msg_pdbg2("\n%s: %s after %d tries (access=0x%02x, status=0x%02x)\n", - __func__, ready ? "suceeded" : "failed", try, access, status); + __func__, ready ? "succeeded" : "failed", try, access, status); atavia_prettyprint_access(access); return ready; } Index: dmi.c =================================================================== --- dmi.c (revision 1830) +++ dmi.c (working copy) @@ -188,7 +188,7 @@ /* - If a short entry is found (less than 4 bytes), not only it * is invalid, but we cannot reliably locate the next entry. * - If the length value indicates that this structure spreads - * accross the table border, something is fishy too. + * across the table border, something is fishy too. * Better stop at this point, and let the user know his/her * table is broken. */ Index: flashchips.c =================================================================== --- flashchips.c (revision 1830) +++ flashchips.c (working copy) @@ -6327,7 +6327,7 @@ .block_erase = spi_block_erase_c7, }, }, - .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6: Continously Program (CP) mode */ + .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6: Continuously Program (CP) mode */ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B), dual I/O supported */ Index: flashrom.8.tmpl =================================================================== --- flashrom.8.tmpl (revision 1830) +++ flashrom.8.tmpl (working copy) @@ -772,7 +772,7 @@ .B value can be .BR 1 " or " 2 -to select target chip 1 or 2 repectively. The default is target chip 1. +to select target chip 1 or 2 respectively. The default is target chip 1. .SS .BR "rayer_spi " programmer The default I/O base address used for the parallel port is 0x378 and you can use

2 1

MSI K9N6PGM2-V: flashrom -V
by appzer0 20 Jul '14

20 Jul '14

Hi Flashrom folks, Please find below (and attached) the flashrom probe output, plus the flashrom -V output, all with the "--programmer internal" option. Please notice that this motherboard is not the one which is referenced on your website, named "MSI K9N6PGM2-V2" (Notice the extra "2" at the end). Note that the verbose probe shows a SST25VF080B chip detected, which is listed as 100% working on your website. So I guess this is good but a confirmation would be much appreciated. :) Thanks for all the great work! appzer0 - http://0linux.org ---

2 1

Re: [flashrom] site down
by Stefan Tauner 19 Jul '14

19 Jul '14

On Fri, 18 Jul 2014 15:10:37 +0100 Javier Camacho <jcnuez(a)gmail.com> wrote: > Hi, your website is down, that is normal? or it is a maintenance shutdown? > thanks! Hi, not it is of course not normal :) and more or less it was for maintenance: the wiki was upgraded. There was also a DNS issue which may have been the cause of what you saw (and why your mail was deferred so long too). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

[PATCH] Rename programmer registration functions
by Carl-Daniel Hailfinger 19 Jul '14

19 Jul '14

register_programmer suggests that we register a programmer. However, that function registers a master for a given bus type, and a programmer may support multiple masters (e.g. SPI, FWH). Rename a few other functions to be more consistent. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-rename_register_programmer_register_master/ogp_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/ogp_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/ogp_spi.c (Arbeitskopie) @@ -140,7 +140,7 @@ if (register_shutdown(ogp_spi_shutdown, NULL)) return 1; - if (bitbang_spi_init(&bitbang_spi_master_ogp)) + if (register_spi_bitbang_master(&bitbang_spi_master_ogp)) return 1; return 0; Index: flashrom-rename_register_programmer_register_master/flash.h =================================================================== --- flashrom-rename_register_programmer_register_master/flash.h (Revision 1587) +++ flashrom-rename_register_programmer_register_master/flash.h (Arbeitskopie) @@ -154,7 +154,7 @@ chipaddr virtual_memory; /* Some flash devices have an additional register space. */ chipaddr virtual_registers; - struct registered_programmer *pgm; + struct registered_master *pgm; }; #define TEST_UNTESTED 0 @@ -215,7 +215,7 @@ void map_flash_registers(struct flashctx *flash); int read_memmapped(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int erase_flash(struct flashctx *flash); -int probe_flash(struct registered_programmer *pgm, int startchip, struct flashctx *fill_flash, int force); +int probe_flash(struct registered_master *pgm, int startchip, struct flashctx *fill_flash, int force); int read_flash_to_file(struct flashctx *flash, const char *filename); int min(int a, int b); int max(int a, int b); Index: flashrom-rename_register_programmer_register_master/drkaiser.c =================================================================== --- flashrom-rename_register_programmer_register_master/drkaiser.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/drkaiser.c (Arbeitskopie) @@ -45,7 +45,7 @@ chipaddr addr); static uint8_t drkaiser_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_drkaiser = { +static const struct par_master par_programmer_drkaiser = { .chip_readb = drkaiser_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -85,7 +85,7 @@ return 1; max_rom_decode.parallel = 128 * 1024; - register_par_programmer(&par_programmer_drkaiser, BUS_PARALLEL); + register_par_master(&par_programmer_drkaiser, BUS_PARALLEL); return 0; } Index: flashrom-rename_register_programmer_register_master/it87spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/it87spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/it87spi.c (Arbeitskopie) @@ -113,7 +113,7 @@ static int it8716f_spi_chip_write_256(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); -static const struct spi_programmer spi_programmer_it87xx = { +static const struct spi_master spi_programmer_it87xx = { .type = SPI_CONTROLLER_IT87XX, .max_data_read = MAX_DATA_UNSPECIFIED, .max_data_write = MAX_DATA_UNSPECIFIED, @@ -199,7 +199,7 @@ if (internal_buses_supported & BUS_SPI) msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); /* FIXME: Add the SPI bus or replace the other buses with it? */ - register_spi_programmer(&spi_programmer_it87xx); + register_spi_master(&spi_programmer_it87xx); return 0; } Index: flashrom-rename_register_programmer_register_master/gfxnvidia.c =================================================================== --- flashrom-rename_register_programmer_register_master/gfxnvidia.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/gfxnvidia.c (Arbeitskopie) @@ -66,7 +66,7 @@ chipaddr addr); static uint8_t gfxnvidia_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_gfxnvidia = { +static const struct par_master par_programmer_gfxnvidia = { .chip_readb = gfxnvidia_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -112,7 +112,7 @@ /* Write/erase doesn't work. */ programmer_may_write = 0; - register_par_programmer(&par_programmer_gfxnvidia, BUS_PARALLEL); + register_par_master(&par_programmer_gfxnvidia, BUS_PARALLEL); return 0; } Index: flashrom-rename_register_programmer_register_master/nicrealtek.c =================================================================== --- flashrom-rename_register_programmer_register_master/nicrealtek.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/nicrealtek.c (Arbeitskopie) @@ -40,7 +40,7 @@ static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr); static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_nicrealtek = { +static const struct par_master par_programmer_nicrealtek = { .chip_readb = nicrealtek_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -82,7 +82,7 @@ if (register_shutdown(nicrealtek_shutdown, NULL)) return 1; - register_par_programmer(&par_programmer_nicrealtek, BUS_PARALLEL); + register_par_master(&par_programmer_nicrealtek, BUS_PARALLEL); return 0; } Index: flashrom-rename_register_programmer_register_master/serprog.c =================================================================== --- flashrom-rename_register_programmer_register_master/serprog.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/serprog.c (Arbeitskopie) @@ -320,7 +320,7 @@ unsigned char *readarr); static int serprog_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); -static struct spi_programmer spi_programmer_serprog = { +static struct spi_master spi_programmer_serprog = { .type = SPI_CONTROLLER_SERPROG, .max_data_read = MAX_DATA_READ_UNLIMITED, .max_data_write = MAX_DATA_WRITE_UNLIMITED, @@ -337,7 +337,7 @@ const chipaddr addr); static void serprog_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len); -static const struct par_programmer par_programmer_serprog = { +static const struct par_master par_programmer_serprog = { .chip_readb = serprog_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -673,10 +673,9 @@ sp_streamed_transmit_bytes = 0; sp_opbuf_usage = 0; if (serprog_buses_supported & BUS_SPI) - register_spi_programmer(&spi_programmer_serprog); + register_spi_master(&spi_programmer_serprog); if (serprog_buses_supported & BUS_NONSPI) - register_par_programmer(&par_programmer_serprog, - serprog_buses_supported & BUS_NONSPI); + register_par_master(&par_programmer_serprog, serprog_buses_supported & BUS_NONSPI); return 0; } Index: flashrom-rename_register_programmer_register_master/bitbang_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/bitbang_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/bitbang_spi.c (Arbeitskopie) @@ -63,7 +63,7 @@ const unsigned char *writearr, unsigned char *readarr); -static const struct spi_programmer spi_programmer_bitbang = { +static const struct spi_master spi_programmer_bitbang = { .type = SPI_CONTROLLER_BITBANG, .max_data_read = MAX_DATA_READ_UNLIMITED, .max_data_write = MAX_DATA_WRITE_UNLIMITED, @@ -82,9 +82,9 @@ } #endif -int bitbang_spi_init(const struct bitbang_spi_master *master) +int register_spi_bitbang_master(const struct bitbang_spi_master *master) { - struct spi_programmer pgm = spi_programmer_bitbang; + struct spi_master pgm = spi_programmer_bitbang; /* BITBANG_SPI_INVALID is 0, so if someone forgot to initialize ->type, * we catch it here. Same goes for missing initialization of bitbanging * functions. @@ -99,7 +99,7 @@ } pgm.data = master; - register_spi_programmer(&pgm); + register_spi_master(&pgm); /* Only mess with the bus if we're sure nobody else uses it. */ bitbang_spi_request_bus(master); Index: flashrom-rename_register_programmer_register_master/satamv.c =================================================================== --- flashrom-rename_register_programmer_register_master/satamv.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/satamv.c (Arbeitskopie) @@ -46,7 +46,7 @@ chipaddr addr); static uint8_t satamv_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_satamv = { +static const struct par_master par_programmer_satamv = { .chip_readb = satamv_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -156,7 +156,7 @@ /* 512 kByte with two 8-bit latches, and * 4 MByte with additional 3-bit latch. */ max_rom_decode.parallel = 4 * 1024 * 1024; - register_par_programmer(&par_programmer_satamv, BUS_PARALLEL); + register_par_master(&par_programmer_satamv, BUS_PARALLEL); return 0; Index: flashrom-rename_register_programmer_register_master/dummyflasher.c =================================================================== --- flashrom-rename_register_programmer_register_master/dummyflasher.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/dummyflasher.c (Arbeitskopie) @@ -119,7 +119,7 @@ static void dummy_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len); -static const struct spi_programmer spi_programmer_dummyflasher = { +static const struct spi_master spi_programmer_dummyflasher = { .type = SPI_CONTROLLER_DUMMY, .max_data_read = MAX_DATA_READ_UNLIMITED, .max_data_write = MAX_DATA_UNSPECIFIED, @@ -130,7 +130,7 @@ .write_aai = default_spi_write_aai, }; -static const struct par_programmer par_programmer_dummy = { +static const struct par_master par_programmer_dummy = { .chip_readb = dummy_chip_readb, .chip_readw = dummy_chip_readw, .chip_readl = dummy_chip_readl, @@ -401,12 +401,10 @@ return 1; } if (dummy_buses_supported & (BUS_PARALLEL | BUS_LPC | BUS_FWH)) - register_par_programmer(&par_programmer_dummy, - dummy_buses_supported & - (BUS_PARALLEL | BUS_LPC | - BUS_FWH)); + register_par_master(&par_programmer_dummy, + dummy_buses_supported & (BUS_PARALLEL | BUS_LPC | BUS_FWH)); if (dummy_buses_supported & BUS_SPI) - register_spi_programmer(&spi_programmer_dummyflasher); + register_spi_master(&spi_programmer_dummyflasher); return 0; } Index: flashrom-rename_register_programmer_register_master/cli_classic.c =================================================================== --- flashrom-rename_register_programmer_register_master/cli_classic.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/cli_classic.c (Arbeitskopie) @@ -421,10 +421,10 @@ msg_pdbg("The following protocols are supported: %s.\n", tempstr); free(tempstr); - for (j = 0; j < registered_programmer_count; j++) { + for (j = 0; j < registered_master_count; j++) { startchip = 0; while (chipcount < ARRAY_SIZE(flashes)) { - startchip = probe_flash(&registered_programmers[j], startchip, &flashes[chipcount], 0); + startchip = probe_flash(&registered_masters[j], startchip, &flashes[chipcount], 0); if (startchip == -1) break; chipcount++; @@ -446,12 +446,12 @@ "automatically.\n"); } if (force && read_it && chip_to_probe) { - struct registered_programmer *pgm; + struct registered_master *pgm; int compatible_programmers = 0; msg_cinfo("Force read (-f -r -c) requested, pretending the chip is there:\n"); /* This loop just counts compatible controllers. */ - for (j = 0; j < registered_programmer_count; j++) { - pgm = &registered_programmers[j]; + for (j = 0; j < registered_master_count; j++) { + pgm = &registered_masters[j]; /* chip is still set from the chip_to_probe earlier in this function. */ if (pgm->buses_supported & chip->bustype) compatible_programmers++; @@ -464,8 +464,8 @@ if (compatible_programmers > 1) msg_cinfo("More than one compatible controller found for the requested flash " "chip, using the first one.\n"); - for (j = 0; j < registered_programmer_count; j++) { - pgm = &registered_programmers[j]; + for (j = 0; j < registered_master_count; j++) { + pgm = &registered_masters[j]; startchip = probe_flash(pgm, 0, &flashes[0], 1); if (startchip != -1) break; Index: flashrom-rename_register_programmer_register_master/internal.c =================================================================== --- flashrom-rename_register_programmer_register_master/internal.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/internal.c (Arbeitskopie) @@ -145,7 +145,7 @@ const chipaddr addr); static void internal_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len); -static const struct par_programmer par_programmer_internal = { +static const struct par_master par_programmer_internal = { .chip_readb = internal_chip_readb, .chip_readw = internal_chip_readw, .chip_readl = internal_chip_readl, @@ -348,7 +348,7 @@ * The error code might have been a warning only. */ #if defined(__i386__) || defined(__x86_64__) || defined (__mips) - register_par_programmer(&par_programmer_internal, internal_buses_supported); + register_par_master(&par_programmer_internal, internal_buses_supported); return 0; #else msg_perr("Your platform is not supported yet for the internal " Index: flashrom-rename_register_programmer_register_master/ichspi.c =================================================================== --- flashrom-rename_register_programmer_register_master/ichspi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/ichspi.c (Arbeitskopie) @@ -1514,7 +1514,7 @@ msg_gspew("resulted in 0x%08x.\n", mmio_readl(addr)); } -static const struct spi_programmer spi_programmer_ich7 = { +static const struct spi_master spi_programmer_ich7 = { .type = SPI_CONTROLLER_ICH7, .max_data_read = 64, .max_data_write = 64, @@ -1525,7 +1525,7 @@ .write_aai = default_spi_write_aai, }; -static const struct spi_programmer spi_programmer_ich9 = { +static const struct spi_master spi_programmer_ich9 = { .type = SPI_CONTROLLER_ICH9, .max_data_read = 64, .max_data_write = 64, @@ -1536,7 +1536,7 @@ .write_aai = default_spi_write_aai, }; -static const struct opaque_programmer opaque_programmer_ich_hwseq = { +static const struct opaque_master opaque_programmer_ich_hwseq = { .max_data_read = 64, .max_data_write = 64, .probe = ich_hwseq_probe, @@ -1623,7 +1623,7 @@ } ich_init_opcodes(); ich_set_bbar(0); - register_spi_programmer(&spi_programmer_ich7); + register_spi_master(&spi_programmer_ich7); break; case CHIPSET_ICH8: default: /* Future version might behave the same */ @@ -1808,9 +1808,9 @@ } hwseq_data.size_comp0 = getFCBA_component_density(&desc, 0); hwseq_data.size_comp1 = getFCBA_component_density(&desc, 1); - register_opaque_programmer(&opaque_programmer_ich_hwseq); + register_opaque_master(&opaque_programmer_ich_hwseq); } else { - register_spi_programmer(&spi_programmer_ich9); + register_spi_master(&spi_programmer_ich9); } break; } @@ -1833,7 +1833,7 @@ return 0; } -static const struct spi_programmer spi_programmer_via = { +static const struct spi_master spi_programmer_via = { .type = SPI_CONTROLLER_VIA, .max_data_read = 16, .max_data_write = 16, @@ -1854,7 +1854,7 @@ /* Not sure if it speaks all these bus protocols. */ internal_buses_supported = BUS_LPC | BUS_FWH; ich_generation = CHIPSET_ICH7; - register_spi_programmer(&spi_programmer_via); + register_spi_master(&spi_programmer_via); msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2)); Index: flashrom-rename_register_programmer_register_master/nicintel_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/nicintel_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/nicintel_spi.c (Arbeitskopie) @@ -196,7 +196,7 @@ if (register_shutdown(nicintel_spi_shutdown, NULL)) return 1; - if (bitbang_spi_init(&bitbang_spi_master_nicintel)) + if (register_spi_bitbang_master(&bitbang_spi_master_nicintel)) return 1; return 0; Index: flashrom-rename_register_programmer_register_master/opaque.c =================================================================== --- flashrom-rename_register_programmer_register_master/opaque.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/opaque.c (Arbeitskopie) @@ -50,9 +50,9 @@ return flash->pgm->opaque.erase(flash, blockaddr, blocklen); } -int register_opaque_programmer(const struct opaque_programmer *pgm) +int register_opaque_master(const struct opaque_master *pgm) { - struct registered_programmer rpgm; + struct registered_master rpgm; if (!pgm->probe || !pgm->read || !pgm->write || !pgm->erase) { msg_perr("%s called with incomplete programmer definition. " Index: flashrom-rename_register_programmer_register_master/nicnatsemi.c =================================================================== --- flashrom-rename_register_programmer_register_master/nicnatsemi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/nicnatsemi.c (Arbeitskopie) @@ -41,7 +41,7 @@ chipaddr addr); static uint8_t nicnatsemi_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_nicnatsemi = { +static const struct par_master par_programmer_nicnatsemi = { .chip_readb = nicnatsemi_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -75,7 +75,7 @@ * functions below wants to be 0x0000FFFF. */ max_rom_decode.parallel = 131072; - register_par_programmer(&par_programmer_nicnatsemi, BUS_PARALLEL); + register_par_master(&par_programmer_nicnatsemi, BUS_PARALLEL); return 0; } Index: flashrom-rename_register_programmer_register_master/dediprog.c =================================================================== --- flashrom-rename_register_programmer_register_master/dediprog.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/dediprog.c (Arbeitskopie) @@ -736,7 +736,7 @@ return millivolt; } -static const struct spi_programmer spi_programmer_dediprog = { +static const struct spi_master spi_programmer_dediprog = { .type = SPI_CONTROLLER_DEDIPROG, .max_data_read = MAX_DATA_UNSPECIFIED, .max_data_write = MAX_DATA_UNSPECIFIED, @@ -854,7 +854,7 @@ return 1; } - register_spi_programmer(&spi_programmer_dediprog); + register_spi_master(&spi_programmer_dediprog); /* RE leftover, leave in until the driver is complete. */ #if 0 Index: flashrom-rename_register_programmer_register_master/rayer_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/rayer_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/rayer_spi.c (Arbeitskopie) @@ -175,7 +175,7 @@ /* Get the initial value before writing to any line. */ lpt_outbyte = INB(lpt_iobase); - if (bitbang_spi_init(&bitbang_spi_master_rayer)) + if (register_spi_bitbang_master(&bitbang_spi_master_rayer)) return 1; return 0; Index: flashrom-rename_register_programmer_register_master/it85spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/it85spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/it85spi.c (Arbeitskopie) @@ -276,7 +276,7 @@ const unsigned char *writearr, unsigned char *readarr); -static const struct spi_programmer spi_programmer_it85xx = { +static const struct spi_master spi_programmer_it85xx = { .type = SPI_CONTROLLER_IT85XX, .max_data_read = 64, .max_data_write = 64, @@ -312,7 +312,7 @@ * a debug message about it. */ /* Set this as SPI controller. */ - register_spi_programmer(&spi_programmer_it85xx); + register_spi_master(&spi_programmer_it85xx); } return ret; } Index: flashrom-rename_register_programmer_register_master/buspirate_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/buspirate_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/buspirate_spi.c (Arbeitskopie) @@ -132,7 +132,7 @@ static int buspirate_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -static const struct spi_programmer spi_programmer_buspirate = { +static const struct spi_master spi_programmer_buspirate = { .type = SPI_CONTROLLER_BUSPIRATE, .max_data_read = 12, .max_data_write = 12, @@ -407,7 +407,7 @@ return 1; } - register_spi_programmer(&spi_programmer_buspirate); + register_spi_master(&spi_programmer_buspirate); return 0; } Index: flashrom-rename_register_programmer_register_master/linux_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/linux_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/linux_spi.c (Arbeitskopie) @@ -46,7 +46,7 @@ static int linux_spi_write_256(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); -static const struct spi_programmer spi_programmer_linux = { +static const struct spi_master spi_programmer_linux = { .type = SPI_CONTROLLER_LINUX, .max_data_read = MAX_DATA_UNSPECIFIED, /* TODO? */ .max_data_write = MAX_DATA_UNSPECIFIED, /* TODO? */ @@ -115,7 +115,7 @@ return 1; } - register_spi_programmer(&spi_programmer_linux); + register_spi_master(&spi_programmer_linux); return 0; } Index: flashrom-rename_register_programmer_register_master/atahpt.c =================================================================== --- flashrom-rename_register_programmer_register_master/atahpt.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/atahpt.c (Arbeitskopie) @@ -45,7 +45,7 @@ chipaddr addr); static uint8_t atahpt_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_atahpt = { +static const struct par_master par_programmer_atahpt = { .chip_readb = atahpt_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -80,7 +80,7 @@ if (register_shutdown(atahpt_shutdown, NULL)) return 1; - register_par_programmer(&par_programmer_atahpt, BUS_PARALLEL); + register_par_master(&par_programmer_atahpt, BUS_PARALLEL); return 0; } Index: flashrom-rename_register_programmer_register_master/nic3com.c =================================================================== --- flashrom-rename_register_programmer_register_master/nic3com.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/nic3com.c (Arbeitskopie) @@ -60,7 +60,7 @@ chipaddr addr); static uint8_t nic3com_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_nic3com = { +static const struct par_master par_programmer_nic3com = { .chip_readb = nic3com_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -116,7 +116,7 @@ return 1; max_rom_decode.parallel = 128 * 1024; - register_par_programmer(&par_programmer_nic3com, BUS_PARALLEL); + register_par_master(&par_programmer_nic3com, BUS_PARALLEL); return 0; } Index: flashrom-rename_register_programmer_register_master/spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/spi.c (Arbeitskopie) @@ -167,9 +167,9 @@ return flash->pgm->spi.write_aai(flash, buf, start, len); } -int register_spi_programmer(const struct spi_programmer *pgm) +int register_spi_master(const struct spi_master *pgm) { - struct registered_programmer rpgm; + struct registered_master rpgm; if (!pgm->write_aai || !pgm->write_256 || !pgm->read || !pgm->command || !pgm->multicommand || Index: flashrom-rename_register_programmer_register_master/ft2232_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/ft2232_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/ft2232_spi.c (Arbeitskopie) @@ -142,7 +142,7 @@ const unsigned char *writearr, unsigned char *readarr); -static const struct spi_programmer spi_programmer_ft2232 = { +static const struct spi_master spi_programmer_ft2232 = { .type = SPI_CONTROLLER_FT2232, .max_data_read = 64 * 1024, .max_data_write = 256, @@ -356,7 +356,7 @@ // msg_pdbg("\nft2232 chosen\n"); - register_spi_programmer(&spi_programmer_ft2232); + register_spi_master(&spi_programmer_ft2232); return 0; Index: flashrom-rename_register_programmer_register_master/satasii.c =================================================================== --- flashrom-rename_register_programmer_register_master/satasii.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/satasii.c (Arbeitskopie) @@ -43,7 +43,7 @@ static void satasii_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr); static uint8_t satasii_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_satasii = { +static const struct par_master par_programmer_satasii = { .chip_readb = satasii_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -90,7 +90,7 @@ if (register_shutdown(satasii_shutdown, NULL)) return 1; - register_par_programmer(&par_programmer_satasii, BUS_PARALLEL); + register_par_master(&par_programmer_satasii, BUS_PARALLEL); return 0; } Index: flashrom-rename_register_programmer_register_master/wbsio_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/wbsio_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/wbsio_spi.c (Arbeitskopie) @@ -68,7 +68,7 @@ static int wbsio_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); -static const struct spi_programmer spi_programmer_wbsio = { +static const struct spi_master spi_programmer_wbsio = { .type = SPI_CONTROLLER_WBSIO, .max_data_read = MAX_DATA_UNSPECIFIED, .max_data_write = MAX_DATA_UNSPECIFIED, @@ -90,7 +90,7 @@ msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " "1024 kB!\n", __func__); max_rom_decode.spi = 1024 * 1024; - register_spi_programmer(&spi_programmer_wbsio); + register_spi_master(&spi_programmer_wbsio); return 0; } Index: flashrom-rename_register_programmer_register_master/pony_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/pony_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/pony_spi.c (Arbeitskopie) @@ -158,7 +158,7 @@ return 1; } - if (bitbang_spi_init(&bitbang_spi_master_pony)) { + if (register_spi_bitbang_master(&bitbang_spi_master_pony)) { return 1; } return 0; Index: flashrom-rename_register_programmer_register_master/nicintel.c =================================================================== --- flashrom-rename_register_programmer_register_master/nicintel.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/nicintel.c (Arbeitskopie) @@ -48,7 +48,7 @@ chipaddr addr); static uint8_t nicintel_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_nicintel = { +static const struct par_master par_programmer_nicintel = { .chip_readb = nicintel_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -110,7 +110,7 @@ pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR); max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE; - register_par_programmer(&par_programmer_nicintel, BUS_PARALLEL); + register_par_master(&par_programmer_nicintel, BUS_PARALLEL); return 0; Index: flashrom-rename_register_programmer_register_master/sb600spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/sb600spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/sb600spi.c (Arbeitskopie) @@ -194,7 +194,7 @@ return 0; } -static const struct spi_programmer spi_programmer_sb600 = { +static const struct spi_master spi_programmer_sb600 = { .type = SPI_CONTROLLER_SB600, .max_data_read = 8, .max_data_write = 5, @@ -320,7 +320,7 @@ /* Bring the FIFO to a clean state. */ reset_internal_fifo_pointer(); - register_spi_programmer(&spi_programmer_sb600); + register_spi_master(&spi_programmer_sb600); return 0; } Index: flashrom-rename_register_programmer_register_master/mcp6x_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/mcp6x_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/mcp6x_spi.c (Arbeitskopie) @@ -161,7 +161,7 @@ (status >> MCP6X_SPI_GRANT) & 0x1); mcp_gpiostate = status & 0xff; - if (bitbang_spi_init(&bitbang_spi_master_mcp6x)) { + if (register_spi_bitbang_master(&bitbang_spi_master_mcp6x)) { /* This should never happen. */ msg_perr("MCP6X bitbang SPI master init failed!\n"); return 1; Index: flashrom-rename_register_programmer_register_master/programmer.c =================================================================== --- flashrom-rename_register_programmer_register_master/programmer.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/programmer.c (Arbeitskopie) @@ -96,10 +96,10 @@ return; } -int register_par_programmer(const struct par_programmer *pgm, +int register_par_master(const struct par_master *pgm, const enum chipbustype buses) { - struct registered_programmer rpgm; + struct registered_master rpgm; if (!pgm->chip_writeb || !pgm->chip_writew || !pgm->chip_writel || !pgm->chip_writen || !pgm->chip_readb || !pgm->chip_readw || !pgm->chip_readl || !pgm->chip_readn) { @@ -115,20 +115,20 @@ } /* The limit of 4 is totally arbitrary. */ -#define PROGRAMMERS_MAX 4 -struct registered_programmer registered_programmers[PROGRAMMERS_MAX]; -int registered_programmer_count = 0; +#define MASTERS_MAX 4 +struct registered_master registered_masters[MASTERS_MAX]; +int registered_master_count = 0; -/* This function copies the struct registered_programmer parameter. */ -int register_programmer(struct registered_programmer *pgm) +/* This function copies the struct registered_master parameter. */ +int register_programmer(struct registered_master *pgm) { - if (registered_programmer_count >= PROGRAMMERS_MAX) { + if (registered_master_count >= MASTERS_MAX) { msg_perr("Tried to register more than %i programmer " - "interfaces.\n", PROGRAMMERS_MAX); + "interfaces.\n", MASTERS_MAX); return ERROR_FLASHROM_LIMIT; } - registered_programmers[registered_programmer_count] = *pgm; - registered_programmer_count++; + registered_masters[registered_master_count] = *pgm; + registered_master_count++; return 0; } @@ -138,8 +138,8 @@ int i; enum chipbustype ret = BUS_NONE; - for (i = 0; i < registered_programmer_count; i++) - ret |= registered_programmers[i].buses_supported; + for (i = 0; i < registered_master_count; i++) + ret |= registered_masters[i].buses_supported; return ret; } Index: flashrom-rename_register_programmer_register_master/flashrom.c =================================================================== --- flashrom-rename_register_programmer_register_master/flashrom.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/flashrom.c (Arbeitskopie) @@ -949,7 +949,7 @@ return 1; } -int probe_flash(struct registered_programmer *pgm, int startchip, struct flashctx *flash, int force) +int probe_flash(struct registered_master *pgm, int startchip, struct flashctx *flash, int force) { const struct flashchip *chip; unsigned long base = 0; Index: flashrom-rename_register_programmer_register_master/programmer.h =================================================================== --- flashrom-rename_register_programmer_register_master/programmer.h (Revision 1587) +++ flashrom-rename_register_programmer_register_master/programmer.h (Arbeitskopie) @@ -445,7 +445,7 @@ #endif /* bitbang_spi.c */ -int bitbang_spi_init(const struct bitbang_spi_master *master); +int register_spi_bitbang_master(const struct bitbang_spi_master *master); /* buspirate_spi.c */ #if CONFIG_BUSPIRATE_SPI == 1 @@ -517,7 +517,7 @@ #define MAX_DATA_UNSPECIFIED 0 #define MAX_DATA_READ_UNLIMITED 64 * 1024 #define MAX_DATA_WRITE_UNLIMITED 256 -struct spi_programmer { +struct spi_master { enum spi_controller type; unsigned int max_data_read; unsigned int max_data_write; @@ -538,7 +538,7 @@ int default_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int default_spi_write_256(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int default_spi_write_aai(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); -int register_spi_programmer(const struct spi_programmer *programmer); +int register_spi_master(const struct spi_master *programmer); /* The following enum is needed by ich_descriptor_tool and ich* code. */ enum ich_chipset { @@ -580,7 +580,7 @@ #endif /* opaque.c */ -struct opaque_programmer { +struct opaque_master { int max_data_read; int max_data_write; /* Specific functions for this programmer */ @@ -590,7 +590,7 @@ int (*erase) (struct flashctx *flash, unsigned int blockaddr, unsigned int blocklen); const void *data; }; -int register_opaque_programmer(const struct opaque_programmer *pgm); +int register_opaque_master(const struct opaque_master *pgm); /* programmer.c */ int noop_shutdown(void); @@ -603,7 +603,7 @@ uint16_t fallback_chip_readw(const struct flashctx *flash, const chipaddr addr); uint32_t fallback_chip_readl(const struct flashctx *flash, const chipaddr addr); void fallback_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len); -struct par_programmer { +struct par_master { void (*chip_writeb) (const struct flashctx *flash, uint8_t val, chipaddr addr); void (*chip_writew) (const struct flashctx *flash, uint16_t val, chipaddr addr); void (*chip_writel) (const struct flashctx *flash, uint32_t val, chipaddr addr); @@ -614,18 +614,18 @@ void (*chip_readn) (const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len); const void *data; }; -int register_par_programmer(const struct par_programmer *pgm, const enum chipbustype buses); -struct registered_programmer { +int register_par_master(const struct par_master *pgm, const enum chipbustype buses); +struct registered_master { enum chipbustype buses_supported; union { - struct par_programmer par; - struct spi_programmer spi; - struct opaque_programmer opaque; + struct par_master par; + struct spi_master spi; + struct opaque_master opaque; }; }; -extern struct registered_programmer registered_programmers[]; -extern int registered_programmer_count; -int register_programmer(struct registered_programmer *pgm); +extern struct registered_master registered_masters[]; +extern int registered_master_count; +int register_programmer(struct registered_master *pgm); /* serprog.c */ #if CONFIG_SERPROG == 1 -- http://www.hailfinger.org/

3 4

[commit] r1831 - trunk
by repository service 19 Jul '14

19 Jul '14

Author: hailfinger Date: Sun Jul 20 00:03:29 2014 New Revision: 1831 URL: http://flashrom.org/trac/flashrom/changeset/1831 Log: Rename programmer registration functions register_programmer suggests that we register a programmer. However, that function registers a master for a given bus type, and a programmer may support multiple masters (e.g. SPI, FWH). Rename a few other functions to be more consistent. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/at45db.c trunk/atahpt.c trunk/atavia.c trunk/bitbang_spi.c trunk/buspirate_spi.c trunk/cli_classic.c trunk/dediprog.c trunk/drkaiser.c trunk/dummyflasher.c trunk/flash.h trunk/flashrom.c trunk/ft2232_spi.c trunk/gfxnvidia.c trunk/ichspi.c trunk/internal.c trunk/it8212.c trunk/it85spi.c trunk/it87spi.c trunk/linux_spi.c trunk/mcp6x_spi.c trunk/nic3com.c trunk/nicintel.c trunk/nicintel_spi.c trunk/nicnatsemi.c trunk/nicrealtek.c trunk/ogp_spi.c trunk/opaque.c trunk/pony_spi.c trunk/programmer.c trunk/programmer.h trunk/rayer_spi.c trunk/satamv.c trunk/satasii.c trunk/sb600spi.c trunk/serprog.c trunk/spi.c trunk/spi25.c trunk/usbblaster_spi.c trunk/wbsio_spi.c Modified: trunk/at45db.c ============================================================================== --- trunk/at45db.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/at45db.c Sun Jul 20 00:03:29 2014 (r1831) @@ -241,7 +241,7 @@ /* We have to split this up into chunks to fit within the programmer's read size limit, but those * chunks can cross page boundaries. */ - const unsigned int max_data_read = flash->pgm->spi.max_data_read; + const unsigned int max_data_read = flash->mst->spi.max_data_read; const unsigned int max_chunk = (max_data_read > 0) ? max_data_read : page_size; while (len > 0) { unsigned int chunk = min(max_chunk, len); @@ -272,7 +272,7 @@ /* We have to split this up into chunks to fit within the programmer's read size limit, but those * chunks can cross page boundaries. */ - const unsigned int max_data_read = flash->pgm->spi.max_data_read; + const unsigned int max_data_read = flash->mst->spi.max_data_read; const unsigned int max_chunk = (max_data_read > 0) ? max_data_read : page_size; while (len > 0) { const unsigned int addr_at45 = at45db_convert_addr(addr, page_size); @@ -463,7 +463,7 @@ } /* Create a suitable buffer to store opcode, address and data chunks for buffer1. */ - const unsigned int max_data_write = flash->pgm->spi.max_data_write; + const unsigned int max_data_write = flash->mst->spi.max_data_write; const unsigned int max_chunk = (max_data_write > 0 && max_data_write <= page_size) ? max_data_write : page_size; uint8_t buf[4 + max_chunk]; Modified: trunk/atahpt.c ============================================================================== --- trunk/atahpt.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/atahpt.c Sun Jul 20 00:03:29 2014 (r1831) @@ -47,7 +47,7 @@ chipaddr addr); static uint8_t atahpt_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_atahpt = { +static const struct par_master par_master_atahpt = { .chip_readb = atahpt_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -79,7 +79,7 @@ reg32 |= (1 << 24); rpci_write_long(dev, REG_FLASH_ACCESS, reg32); - register_par_programmer(&par_programmer_atahpt, BUS_PARALLEL); + register_par_master(&par_master_atahpt, BUS_PARALLEL); return 0; } Modified: trunk/atavia.c ============================================================================== --- trunk/atavia.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/atavia.c Sun Jul 20 00:03:29 2014 (r1831) @@ -60,7 +60,7 @@ static void atavia_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr); static uint8_t atavia_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer lpc_programmer_atavia = { +static const struct par_master lpc_master_atavia = { .chip_readb = atavia_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -164,7 +164,7 @@ return 1; } - register_par_programmer(&lpc_programmer_atavia, BUS_LPC); + register_par_master(&lpc_master_atavia, BUS_LPC); return 0; } Modified: trunk/bitbang_spi.c ============================================================================== --- trunk/bitbang_spi.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/bitbang_spi.c Sun Jul 20 00:03:29 2014 (r1831) @@ -63,7 +63,7 @@ const unsigned char *writearr, unsigned char *readarr); -static const struct spi_programmer spi_programmer_bitbang = { +static const struct spi_master spi_master_bitbang = { .type = SPI_CONTROLLER_BITBANG, .max_data_read = MAX_DATA_READ_UNLIMITED, .max_data_write = MAX_DATA_WRITE_UNLIMITED, @@ -82,9 +82,9 @@ } #endif -int bitbang_spi_init(const struct bitbang_spi_master *master) +int register_spi_bitbang_master(const struct bitbang_spi_master *master) { - struct spi_programmer pgm = spi_programmer_bitbang; + struct spi_master mst = spi_master_bitbang; /* BITBANG_SPI_INVALID is 0, so if someone forgot to initialize ->type, * we catch it here. Same goes for missing initialization of bitbanging * functions. @@ -98,8 +98,8 @@ return ERROR_FLASHROM_BUG; } - pgm.data = master; - register_spi_programmer(&pgm); + mst.data = master; + register_spi_master(&mst); /* Only mess with the bus if we're sure nobody else uses it. */ bitbang_spi_request_bus(master); @@ -137,7 +137,7 @@ unsigned char *readarr) { int i; - const struct bitbang_spi_master *master = flash->pgm->spi.data; + const struct bitbang_spi_master *master = flash->mst->spi.data; /* FIXME: Run bitbang_spi_request_bus here or in programmer init? * Requesting and releasing the SPI bus is handled in here to allow the Modified: trunk/buspirate_spi.c ============================================================================== --- trunk/buspirate_spi.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/buspirate_spi.c Sun Jul 20 00:03:29 2014 (r1831) @@ -134,7 +134,7 @@ static int buspirate_spi_send_command_v2(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -static struct spi_programmer spi_programmer_buspirate = { +static struct spi_master spi_master_buspirate = { .type = SPI_CONTROLLER_BUSPIRATE, .max_data_read = MAX_DATA_UNSPECIFIED, .max_data_write = MAX_DATA_UNSPECIFIED, @@ -355,9 +355,9 @@ /* Sensible default buffer size. */ if (buspirate_commbuf_grow(260 + 5)) return ERROR_OOM; - spi_programmer_buspirate.max_data_read = 2048; - spi_programmer_buspirate.max_data_write = 256; - spi_programmer_buspirate.command = buspirate_spi_send_command_v2; + spi_master_buspirate.max_data_read = 2048; + spi_master_buspirate.max_data_write = 256; + spi_master_buspirate.command = buspirate_spi_send_command_v2; } else { msg_pinfo("Bus Pirate firmware 5.4 and older does not support fast SPI access.\n"); msg_pinfo("Reading/writing a flash chip may take hours.\n"); @@ -365,9 +365,9 @@ /* Sensible default buffer size. */ if (buspirate_commbuf_grow(16 + 3)) return ERROR_OOM; - spi_programmer_buspirate.max_data_read = 12; - spi_programmer_buspirate.max_data_write = 12; - spi_programmer_buspirate.command = buspirate_spi_send_command_v1; + spi_master_buspirate.max_data_read = 12; + spi_master_buspirate.max_data_write = 12; + spi_master_buspirate.command = buspirate_spi_send_command_v1; } /* Workaround for broken speed settings in firmware 6.1 and older. */ @@ -454,7 +454,7 @@ return 1; } - register_spi_programmer(&spi_programmer_buspirate); + register_spi_master(&spi_master_buspirate); return 0; } Modified: trunk/cli_classic.c ============================================================================== --- trunk/cli_classic.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/cli_classic.c Sun Jul 20 00:03:29 2014 (r1831) @@ -426,10 +426,10 @@ msg_pdbg("The following protocols are supported: %s.\n", tempstr); free(tempstr); - for (j = 0; j < registered_programmer_count; j++) { + for (j = 0; j < registered_master_count; j++) { startchip = 0; while (chipcount < ARRAY_SIZE(flashes)) { - startchip = probe_flash(&registered_programmers[j], startchip, &flashes[chipcount], 0); + startchip = probe_flash(&registered_masters[j], startchip, &flashes[chipcount], 0); if (startchip == -1) break; chipcount++; @@ -452,27 +452,27 @@ "automatically.\n"); } if (force && read_it && chip_to_probe) { - struct registered_programmer *pgm; - int compatible_programmers = 0; + struct registered_master *mst; + int compatible_masters = 0; msg_cinfo("Force read (-f -r -c) requested, pretending the chip is there:\n"); /* This loop just counts compatible controllers. */ - for (j = 0; j < registered_programmer_count; j++) { - pgm = &registered_programmers[j]; + for (j = 0; j < registered_master_count; j++) { + mst = &registered_masters[j]; /* chip is still set from the chip_to_probe earlier in this function. */ - if (pgm->buses_supported & chip->bustype) - compatible_programmers++; + if (mst->buses_supported & chip->bustype) + compatible_masters++; } - if (!compatible_programmers) { + if (!compatible_masters) { msg_cinfo("No compatible controller found for the requested flash chip.\n"); ret = 1; goto out_shutdown; } - if (compatible_programmers > 1) + if (compatible_masters > 1) msg_cinfo("More than one compatible controller found for the requested flash " "chip, using the first one.\n"); - for (j = 0; j < registered_programmer_count; j++) { - pgm = &registered_programmers[j]; - startchip = probe_flash(pgm, 0, &flashes[0], 1); + for (j = 0; j < registered_master_count; j++) { + mst = &registered_masters[j]; + startchip = probe_flash(mst, 0, &flashes[0], 1); if (startchip != -1) break; } @@ -502,7 +502,7 @@ check_chip_supported(fill_flash->chip); size = fill_flash->chip->total_size * 1024; - if (check_max_decode(fill_flash->pgm->buses_supported & fill_flash->chip->bustype, size) && (!force)) { + if (check_max_decode(fill_flash->mst->buses_supported & fill_flash->chip->bustype, size) && (!force)) { msg_cerr("Chip is too big for this programmer (-V gives details). Use --force to override.\n"); ret = 1; goto out_shutdown; Modified: trunk/dediprog.c ============================================================================== --- trunk/dediprog.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/dediprog.c Sun Jul 20 00:03:29 2014 (r1831) @@ -750,7 +750,7 @@ return 0; } -static const struct spi_programmer spi_programmer_dediprog = { +static const struct spi_master spi_master_dediprog = { .type = SPI_CONTROLLER_DEDIPROG, .max_data_read = MAX_DATA_UNSPECIFIED, .max_data_write = MAX_DATA_UNSPECIFIED, @@ -929,7 +929,7 @@ return 1; } - register_spi_programmer(&spi_programmer_dediprog); + register_spi_master(&spi_master_dediprog); /* RE leftover, leave in until the driver is complete. */ #if 0 Modified: trunk/drkaiser.c ============================================================================== --- trunk/drkaiser.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/drkaiser.c Sun Jul 20 00:03:29 2014 (r1831) @@ -45,7 +45,7 @@ chipaddr addr); static uint8_t drkaiser_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_drkaiser = { +static const struct par_master par_master_drkaiser = { .chip_readb = drkaiser_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -81,7 +81,7 @@ return 1; max_rom_decode.parallel = 128 * 1024; - register_par_programmer(&par_programmer_drkaiser, BUS_PARALLEL); + register_par_master(&par_master_drkaiser, BUS_PARALLEL); return 0; } Modified: trunk/dummyflasher.c ============================================================================== --- trunk/dummyflasher.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/dummyflasher.c Sun Jul 20 00:03:29 2014 (r1831) @@ -109,7 +109,7 @@ static uint32_t dummy_chip_readl(const struct flashctx *flash, const chipaddr addr); static void dummy_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len); -static const struct spi_programmer spi_programmer_dummyflasher = { +static const struct spi_master spi_master_dummyflasher = { .type = SPI_CONTROLLER_DUMMY, .max_data_read = MAX_DATA_READ_UNLIMITED, .max_data_write = MAX_DATA_UNSPECIFIED, @@ -120,7 +120,7 @@ .write_aai = default_spi_write_aai, }; -static const struct par_programmer par_programmer_dummy = { +static const struct par_master par_master_dummy = { .chip_readb = dummy_chip_readb, .chip_readw = dummy_chip_readw, .chip_readl = dummy_chip_readl, @@ -395,12 +395,10 @@ return 1; } if (dummy_buses_supported & (BUS_PARALLEL | BUS_LPC | BUS_FWH)) - register_par_programmer(&par_programmer_dummy, - dummy_buses_supported & - (BUS_PARALLEL | BUS_LPC | - BUS_FWH)); + register_par_master(&par_master_dummy, + dummy_buses_supported & (BUS_PARALLEL | BUS_LPC | BUS_FWH)); if (dummy_buses_supported & BUS_SPI) - register_spi_programmer(&spi_programmer_dummyflasher); + register_spi_master(&spi_master_dummyflasher); return 0; } Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/flash.h Sun Jul 20 00:03:29 2014 (r1831) @@ -212,7 +212,7 @@ chipaddr virtual_memory; /* Some flash devices have an additional register space. */ chipaddr virtual_registers; - struct registered_programmer *pgm; + struct registered_master *mst; }; /* Timing used in probe routines. ZERO is -2 to differentiate between an unset @@ -258,7 +258,7 @@ void map_flash_registers(struct flashctx *flash); int read_memmapped(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int erase_flash(struct flashctx *flash); -int probe_flash(struct registered_programmer *pgm, int startchip, struct flashctx *fill_flash, int force); +int probe_flash(struct registered_master *mst, int startchip, struct flashctx *fill_flash, int force); int read_flash_to_file(struct flashctx *flash, const char *filename); char *extract_param(const char *const *haystack, const char *needle, const char *delim); int verify_range(struct flashctx *flash, const uint8_t *cmpbuf, unsigned int start, unsigned int len); Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/flashrom.c Sun Jul 20 00:03:29 2014 (r1831) @@ -454,7 +454,7 @@ } programmer_param = NULL; - registered_programmer_count = 0; + registered_master_count = 0; return ret; } @@ -474,43 +474,43 @@ void chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) { - flash->pgm->par.chip_writeb(flash, val, addr); + flash->mst->par.chip_writeb(flash, val, addr); } void chip_writew(const struct flashctx *flash, uint16_t val, chipaddr addr) { - flash->pgm->par.chip_writew(flash, val, addr); + flash->mst->par.chip_writew(flash, val, addr); } void chip_writel(const struct flashctx *flash, uint32_t val, chipaddr addr) { - flash->pgm->par.chip_writel(flash, val, addr); + flash->mst->par.chip_writel(flash, val, addr); } void chip_writen(const struct flashctx *flash, const uint8_t *buf, chipaddr addr, size_t len) { - flash->pgm->par.chip_writen(flash, buf, addr, len); + flash->mst->par.chip_writen(flash, buf, addr, len); } uint8_t chip_readb(const struct flashctx *flash, const chipaddr addr) { - return flash->pgm->par.chip_readb(flash, addr); + return flash->mst->par.chip_readb(flash, addr); } uint16_t chip_readw(const struct flashctx *flash, const chipaddr addr) { - return flash->pgm->par.chip_readw(flash, addr); + return flash->mst->par.chip_readw(flash, addr); } uint32_t chip_readl(const struct flashctx *flash, const chipaddr addr) { - return flash->pgm->par.chip_readl(flash, addr); + return flash->mst->par.chip_readl(flash, addr); } void chip_readn(const struct flashctx *flash, uint8_t *buf, chipaddr addr, size_t len) { - flash->pgm->par.chip_readn(flash, buf, addr, len); + flash->mst->par.chip_readn(flash, buf, addr, len); } void programmer_delay(unsigned int usecs) @@ -1049,7 +1049,7 @@ return 1; } -int probe_flash(struct registered_programmer *pgm, int startchip, struct flashctx *flash, int force) +int probe_flash(struct registered_master *mst, int startchip, struct flashctx *flash, int force) { const struct flashchip *chip; unsigned long base = 0; @@ -1061,7 +1061,7 @@ for (chip = flashchips + startchip; chip && chip->name; chip++) { if (chip_to_probe && strcmp(chip->name, chip_to_probe) != 0) continue; - buses_common = pgm->buses_supported & chip->bustype; + buses_common = mst->buses_supported & chip->bustype; if (!buses_common) continue; msg_gdbg("Probing for %s %s, %d kB: ", chip->vendor, chip->name, chip->total_size); @@ -1080,7 +1080,7 @@ exit(1); } memcpy(flash->chip, chip, sizeof(struct flashchip)); - flash->pgm = pgm; + flash->mst = mst; base = flashbase ? flashbase : (0xffffffff - size + 1); flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); @@ -1098,7 +1098,7 @@ * If this is not the first chip found, accept it only if it is * a non-generic match. SFDP and CFI are generic matches. * startchip==0 means this call to probe_flash() is the first - * one for this programmer interface and thus no other chip has + * one for this programmer interface (master) and thus no other chip has * been found on this interface. */ if (startchip == 0 && flash->chip->model_id == SFDP_DEVICE_ID) { Modified: trunk/ft2232_spi.c ============================================================================== --- trunk/ft2232_spi.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/ft2232_spi.c Sun Jul 20 00:03:29 2014 (r1831) @@ -146,7 +146,7 @@ const unsigned char *writearr, unsigned char *readarr); -static const struct spi_programmer spi_programmer_ft2232 = { +static const struct spi_master spi_master_ft2232 = { .type = SPI_CONTROLLER_FT2232, .max_data_read = 64 * 1024, .max_data_write = 256, @@ -389,7 +389,7 @@ goto ftdi_err; } - register_spi_programmer(&spi_programmer_ft2232); + register_spi_master(&spi_master_ft2232); return 0; Modified: trunk/gfxnvidia.c ============================================================================== --- trunk/gfxnvidia.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/gfxnvidia.c Sun Jul 20 00:03:29 2014 (r1831) @@ -66,7 +66,7 @@ chipaddr addr); static uint8_t gfxnvidia_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_gfxnvidia = { +static const struct par_master par_master_gfxnvidia = { .chip_readb = gfxnvidia_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -107,7 +107,7 @@ /* Write/erase doesn't work. */ programmer_may_write = 0; - register_par_programmer(&par_programmer_gfxnvidia, BUS_PARALLEL); + register_par_master(&par_master_gfxnvidia, BUS_PARALLEL); return 0; } Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/ichspi.c Sun Jul 20 00:03:29 2014 (r1831) @@ -640,7 +640,7 @@ /* Read len bytes from the fdata/spid register into the data array. * - * Note that using len > flash->pgm->spi.max_data_read will return garbage or + * Note that using len > flash->mst->spi.max_data_read will return garbage or * may even crash. */ static void ich_read_data(uint8_t *data, int len, int reg0_off) @@ -658,7 +658,7 @@ /* Fill len bytes from the data array into the fdata/spid registers. * - * Note that using len > flash->pgm->spi.max_data_write will trash the registers + * Note that using len > flash->mst->spi.max_data_write will trash the registers * following the data registers. */ static void ich_fill_data(const uint8_t *data, int len, int reg0_off) @@ -965,7 +965,7 @@ uint8_t datalength, uint8_t * data) { /* max_data_read == max_data_write for all Intel/VIA SPI masters */ - uint8_t maxlength = flash->pgm->spi.max_data_read; + uint8_t maxlength = flash->mst->spi.max_data_read; if (ich_generation == CHIPSET_ICH_UNKNOWN) { msg_perr("%s: unsupported chipset\n", __func__); @@ -1307,7 +1307,7 @@ REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); while (len > 0) { - block_len = min(len, flash->pgm->opaque.max_data_read); + block_len = min(len, flash->mst->opaque.max_data_read); ich_hwseq_set_addr(addr); hsfc = REGREAD16(ICH9_REG_HSFC); hsfc &= ~HSFC_FCYCLE; /* set read operation */ @@ -1345,7 +1345,7 @@ while (len > 0) { ich_hwseq_set_addr(addr); - block_len = min(len, flash->pgm->opaque.max_data_write); + block_len = min(len, flash->mst->opaque.max_data_write); ich_fill_data(buf, block_len, ICH9_REG_FDATA0); hsfc = REGREAD16(ICH9_REG_HSFC); hsfc &= ~HSFC_FCYCLE; /* clear operation */ @@ -1521,7 +1521,7 @@ msg_gspew("resulted in 0x%08x.\n", mmio_readl(addr)); } -static const struct spi_programmer spi_programmer_ich7 = { +static const struct spi_master spi_master_ich7 = { .type = SPI_CONTROLLER_ICH7, .max_data_read = 64, .max_data_write = 64, @@ -1532,7 +1532,7 @@ .write_aai = default_spi_write_aai, }; -static const struct spi_programmer spi_programmer_ich9 = { +static const struct spi_master spi_master_ich9 = { .type = SPI_CONTROLLER_ICH9, .max_data_read = 64, .max_data_write = 64, @@ -1543,7 +1543,7 @@ .write_aai = default_spi_write_aai, }; -static const struct opaque_programmer opaque_programmer_ich_hwseq = { +static const struct opaque_master opaque_master_ich_hwseq = { .max_data_read = 64, .max_data_write = 64, .probe = ich_hwseq_probe, @@ -1604,7 +1604,7 @@ } ich_init_opcodes(); ich_set_bbar(0); - register_spi_programmer(&spi_programmer_ich7); + register_spi_master(&spi_master_ich7); break; case CHIPSET_ICH8: default: /* Future version might behave the same */ @@ -1785,9 +1785,9 @@ } hwseq_data.size_comp0 = getFCBA_component_density(&desc, 0); hwseq_data.size_comp1 = getFCBA_component_density(&desc, 1); - register_opaque_programmer(&opaque_programmer_ich_hwseq); + register_opaque_master(&opaque_master_ich_hwseq); } else { - register_spi_programmer(&spi_programmer_ich9); + register_spi_master(&spi_master_ich9); } break; } @@ -1795,7 +1795,7 @@ return 0; } -static const struct spi_programmer spi_programmer_via = { +static const struct spi_master spi_master_via = { .type = SPI_CONTROLLER_VIA, .max_data_read = 16, .max_data_write = 16, @@ -1818,7 +1818,7 @@ /* Not sure if it speaks all these bus protocols. */ internal_buses_supported = BUS_LPC | BUS_FWH; ich_generation = CHIPSET_ICH7; - register_spi_programmer(&spi_programmer_via); + register_spi_master(&spi_master_via); msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2)); Modified: trunk/internal.c ============================================================================== --- trunk/internal.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/internal.c Sun Jul 20 00:03:29 2014 (r1831) @@ -145,7 +145,7 @@ const chipaddr addr); static void internal_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len); -static const struct par_programmer par_programmer_internal = { +static const struct par_master par_master_internal = { .chip_readb = internal_chip_readb, .chip_readw = internal_chip_readw, .chip_readl = internal_chip_readl, @@ -342,7 +342,7 @@ } #if defined(__i386__) || defined(__x86_64__) || defined (__mips) - register_par_programmer(&par_programmer_internal, internal_buses_supported); + register_par_master(&par_master_internal, internal_buses_supported); return 0; #else msg_perr("Your platform is not supported yet for the internal " Modified: trunk/it8212.c ============================================================================== --- trunk/it8212.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/it8212.c Sun Jul 20 00:03:29 2014 (r1831) @@ -38,7 +38,7 @@ static void it8212_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr); static uint8_t it8212_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_it8212 = { +static const struct par_master par_master_it8212 = { .chip_readb = it8212_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -71,7 +71,7 @@ rpci_write_long(dev, PCI_ROM_ADDRESS, io_base_addr | 0x01); max_rom_decode.parallel = IT8212_MEMMAP_SIZE; - register_par_programmer(&par_programmer_it8212, BUS_PARALLEL); + register_par_master(&par_master_it8212, BUS_PARALLEL); return 0; } Modified: trunk/it85spi.c ============================================================================== --- trunk/it85spi.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/it85spi.c Sun Jul 20 00:03:29 2014 (r1831) @@ -279,7 +279,7 @@ const unsigned char *writearr, unsigned char *readarr); -static const struct spi_programmer spi_programmer_it85xx = { +static const struct spi_master spi_master_it85xx = { .type = SPI_CONTROLLER_IT85XX, .max_data_read = 64, .max_data_write = 64, @@ -315,7 +315,7 @@ * a debug message about it. */ /* Set this as SPI controller. */ - register_spi_programmer(&spi_programmer_it85xx); + register_spi_master(&spi_master_it85xx); } return ret; } Modified: trunk/it87spi.c ============================================================================== --- trunk/it87spi.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/it87spi.c Sun Jul 20 00:03:29 2014 (r1831) @@ -111,7 +111,7 @@ static int it8716f_spi_chip_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); -static const struct spi_programmer spi_programmer_it87xx = { +static const struct spi_master spi_master_it87xx = { .type = SPI_CONTROLLER_IT87XX, .max_data_read = MAX_DATA_UNSPECIFIED, .max_data_write = MAX_DATA_UNSPECIFIED, @@ -228,7 +228,7 @@ if (internal_buses_supported & BUS_SPI) msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); /* FIXME: Add the SPI bus or replace the other buses with it? */ - register_spi_programmer(&spi_programmer_it87xx); + register_spi_master(&spi_master_it87xx); return 0; } Modified: trunk/linux_spi.c ============================================================================== --- trunk/linux_spi.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/linux_spi.c Sun Jul 20 00:03:29 2014 (r1831) @@ -46,7 +46,7 @@ static int linux_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); -static const struct spi_programmer spi_programmer_linux = { +static const struct spi_master spi_master_linux = { .type = SPI_CONTROLLER_LINUX, .max_data_read = MAX_DATA_UNSPECIFIED, /* TODO? */ .max_data_write = MAX_DATA_UNSPECIFIED, /* TODO? */ @@ -120,7 +120,7 @@ return 1; } - register_spi_programmer(&spi_programmer_linux); + register_spi_master(&spi_master_linux); return 0; } Modified: trunk/mcp6x_spi.c ============================================================================== --- trunk/mcp6x_spi.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/mcp6x_spi.c Sun Jul 20 00:03:29 2014 (r1831) @@ -156,7 +156,7 @@ (status >> MCP6X_SPI_GRANT) & 0x1); mcp_gpiostate = status & 0xff; - if (bitbang_spi_init(&bitbang_spi_master_mcp6x)) { + if (register_spi_bitbang_master(&bitbang_spi_master_mcp6x)) { /* This should never happen. */ msg_perr("MCP6X bitbang SPI master init failed!\n"); return 1; Modified: trunk/nic3com.c ============================================================================== --- trunk/nic3com.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/nic3com.c Sun Jul 20 00:03:29 2014 (r1831) @@ -61,7 +61,7 @@ chipaddr addr); static uint8_t nic3com_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_nic3com = { +static const struct par_master par_master_nic3com = { .chip_readb = nic3com_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -124,7 +124,7 @@ return 1; max_rom_decode.parallel = 128 * 1024; - register_par_programmer(&par_programmer_nic3com, BUS_PARALLEL); + register_par_master(&par_master_nic3com, BUS_PARALLEL); return 0; } Modified: trunk/nicintel.c ============================================================================== --- trunk/nicintel.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/nicintel.c Sun Jul 20 00:03:29 2014 (r1831) @@ -48,7 +48,7 @@ chipaddr addr); static uint8_t nicintel_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_nicintel = { +static const struct par_master par_master_nicintel = { .chip_readb = nicintel_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -103,7 +103,7 @@ pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR); max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE; - register_par_programmer(&par_programmer_nicintel, BUS_PARALLEL); + register_par_master(&par_master_nicintel, BUS_PARALLEL); return 0; } Modified: trunk/nicintel_spi.c ============================================================================== --- trunk/nicintel_spi.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/nicintel_spi.c Sun Jul 20 00:03:29 2014 (r1831) @@ -207,7 +207,7 @@ if (register_shutdown(nicintel_spi_shutdown, NULL)) return 1; - if (bitbang_spi_init(&bitbang_spi_master_nicintel)) + if (register_spi_bitbang_master(&bitbang_spi_master_nicintel)) return 1; return 0; Modified: trunk/nicnatsemi.c ============================================================================== --- trunk/nicnatsemi.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/nicnatsemi.c Sun Jul 20 00:03:29 2014 (r1831) @@ -42,7 +42,7 @@ chipaddr addr); static uint8_t nicnatsemi_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_nicnatsemi = { +static const struct par_master par_master_nicnatsemi = { .chip_readb = nicnatsemi_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -75,7 +75,7 @@ * functions below wants to be 0x0000FFFF. */ max_rom_decode.parallel = 131072; - register_par_programmer(&par_programmer_nicnatsemi, BUS_PARALLEL); + register_par_master(&par_master_nicnatsemi, BUS_PARALLEL); return 0; } Modified: trunk/nicrealtek.c ============================================================================== --- trunk/nicrealtek.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/nicrealtek.c Sun Jul 20 00:03:29 2014 (r1831) @@ -41,7 +41,7 @@ static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr); static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_nicrealtek = { +static const struct par_master par_master_nicrealtek = { .chip_readb = nicrealtek_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -90,7 +90,7 @@ if (register_shutdown(nicrealtek_shutdown, NULL)) return 1; - register_par_programmer(&par_programmer_nicrealtek, BUS_PARALLEL); + register_par_master(&par_master_nicrealtek, BUS_PARALLEL); return 0; } Modified: trunk/ogp_spi.c ============================================================================== --- trunk/ogp_spi.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/ogp_spi.c Sun Jul 20 00:03:29 2014 (r1831) @@ -140,7 +140,7 @@ if (ogp_spibar == ERROR_PTR) return 1; - if (bitbang_spi_init(&bitbang_spi_master_ogp)) + if (register_spi_bitbang_master(&bitbang_spi_master_ogp)) return 1; return 0; Modified: trunk/opaque.c ============================================================================== --- trunk/opaque.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/opaque.c Sun Jul 20 00:03:29 2014 (r1831) @@ -1,7 +1,7 @@ /* * This file is part of the flashrom project. * - * Copyright (C) 2011 Carl-Daniel Hailfinger + * Copyright (C) 2011,2013,2014 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,10 +18,10 @@ */ /* - * Contains the opaque programmer framework. - * An opaque programmer is a programmer which does not provide direct access + * Contains the opaque master framework. + * An opaque master is a master which does not provide direct access * to the flash chip and which abstracts all flash chip properties into a - * programmer specific interface. + * master specific interface. */ #include <stdint.h> @@ -32,35 +32,35 @@ int probe_opaque(struct flashctx *flash) { - return flash->pgm->opaque.probe(flash); + return flash->mst->opaque.probe(flash); } int read_opaque(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len) { - return flash->pgm->opaque.read(flash, buf, start, len); + return flash->mst->opaque.read(flash, buf, start, len); } int write_opaque(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len) { - return flash->pgm->opaque.write(flash, buf, start, len); + return flash->mst->opaque.write(flash, buf, start, len); } int erase_opaque(struct flashctx *flash, unsigned int blockaddr, unsigned int blocklen) { - return flash->pgm->opaque.erase(flash, blockaddr, blocklen); + return flash->mst->opaque.erase(flash, blockaddr, blocklen); } -int register_opaque_programmer(const struct opaque_programmer *pgm) +int register_opaque_master(const struct opaque_master *mst) { - struct registered_programmer rpgm; + struct registered_master rmst; - if (!pgm->probe || !pgm->read || !pgm->write || !pgm->erase) { - msg_perr("%s called with incomplete programmer definition. " + if (!mst->probe || !mst->read || !mst->write || !mst->erase) { + msg_perr("%s called with incomplete master definition. " "Please report a bug at flashrom(a)flashrom.org\n", __func__); return ERROR_FLASHROM_BUG; } - rpgm.buses_supported = BUS_PROG; - rpgm.opaque = *pgm; - return register_programmer(&rpgm); + rmst.buses_supported = BUS_PROG; + rmst.opaque = *mst; + return register_master(&rmst); } Modified: trunk/pony_spi.c ============================================================================== --- trunk/pony_spi.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/pony_spi.c Sun Jul 20 00:03:29 2014 (r1831) @@ -212,7 +212,7 @@ return 1; } - if (bitbang_spi_init(&bitbang_spi_master_pony)) { + if (register_spi_bitbang_master(&bitbang_spi_master_pony)) { return 1; } return 0; Modified: trunk/programmer.c ============================================================================== --- trunk/programmer.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/programmer.c Sun Jul 20 00:03:29 2014 (r1831) @@ -95,39 +95,39 @@ return; } -int register_par_programmer(const struct par_programmer *pgm, +int register_par_master(const struct par_master *mst, const enum chipbustype buses) { - struct registered_programmer rpgm; - if (!pgm->chip_writeb || !pgm->chip_writew || !pgm->chip_writel || - !pgm->chip_writen || !pgm->chip_readb || !pgm->chip_readw || - !pgm->chip_readl || !pgm->chip_readn) { - msg_perr("%s called with incomplete programmer definition. " + struct registered_master rmst; + if (!mst->chip_writeb || !mst->chip_writew || !mst->chip_writel || + !mst->chip_writen || !mst->chip_readb || !mst->chip_readw || + !mst->chip_readl || !mst->chip_readn) { + msg_perr("%s called with incomplete master definition. " "Please report a bug at flashrom(a)flashrom.org\n", __func__); return ERROR_FLASHROM_BUG; } - rpgm.buses_supported = buses; - rpgm.par = *pgm; - return register_programmer(&rpgm); + rmst.buses_supported = buses; + rmst.par = *mst; + return register_master(&rmst); } /* The limit of 4 is totally arbitrary. */ -#define PROGRAMMERS_MAX 4 -struct registered_programmer registered_programmers[PROGRAMMERS_MAX]; -int registered_programmer_count = 0; +#define MASTERS_MAX 4 +struct registered_master registered_masters[MASTERS_MAX]; +int registered_master_count = 0; -/* This function copies the struct registered_programmer parameter. */ -int register_programmer(struct registered_programmer *pgm) +/* This function copies the struct registered_master parameter. */ +int register_master(struct registered_master *mst) { - if (registered_programmer_count >= PROGRAMMERS_MAX) { - msg_perr("Tried to register more than %i programmer " - "interfaces.\n", PROGRAMMERS_MAX); + if (registered_master_count >= MASTERS_MAX) { + msg_perr("Tried to register more than %i master " + "interfaces.\n", MASTERS_MAX); return ERROR_FLASHROM_LIMIT; } - registered_programmers[registered_programmer_count] = *pgm; - registered_programmer_count++; + registered_masters[registered_master_count] = *mst; + registered_master_count++; return 0; } @@ -137,8 +137,8 @@ int i; enum chipbustype ret = BUS_NONE; - for (i = 0; i < registered_programmer_count; i++) - ret |= registered_programmers[i].buses_supported; + for (i = 0; i < registered_master_count; i++) + ret |= registered_masters[i].buses_supported; return ret; } Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/programmer.h Sun Jul 20 00:03:29 2014 (r1831) @@ -476,7 +476,7 @@ #endif /* bitbang_spi.c */ -int bitbang_spi_init(const struct bitbang_spi_master *master); +int register_spi_bitbang_master(const struct bitbang_spi_master *master); /* buspirate_spi.c */ #if CONFIG_BUSPIRATE_SPI == 1 @@ -552,7 +552,7 @@ #define MAX_DATA_UNSPECIFIED 0 #define MAX_DATA_READ_UNLIMITED 64 * 1024 #define MAX_DATA_WRITE_UNLIMITED 256 -struct spi_programmer { +struct spi_master { enum spi_controller type; unsigned int max_data_read; unsigned int max_data_write; @@ -560,7 +560,7 @@ const unsigned char *writearr, unsigned char *readarr); int (*multicommand)(struct flashctx *flash, struct spi_command *cmds); - /* Optimized functions for this programmer */ + /* Optimized functions for this master */ int (*read)(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int (*write_256)(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); int (*write_aai)(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); @@ -573,7 +573,7 @@ int default_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int default_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); int default_spi_write_aai(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); -int register_spi_programmer(const struct spi_programmer *programmer); +int register_spi_master(const struct spi_master *mst); /* The following enum is needed by ich_descriptor_tool and ich* code as well as in chipset_enable.c. */ enum ich_chipset { @@ -625,17 +625,17 @@ #endif /* opaque.c */ -struct opaque_programmer { +struct opaque_master { int max_data_read; int max_data_write; - /* Specific functions for this programmer */ + /* Specific functions for this master */ int (*probe) (struct flashctx *flash); int (*read) (struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int (*write) (struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); int (*erase) (struct flashctx *flash, unsigned int blockaddr, unsigned int blocklen); const void *data; }; -int register_opaque_programmer(const struct opaque_programmer *pgm); +int register_opaque_master(const struct opaque_master *mst); /* programmer.c */ int noop_shutdown(void); @@ -648,7 +648,7 @@ uint16_t fallback_chip_readw(const struct flashctx *flash, const chipaddr addr); uint32_t fallback_chip_readl(const struct flashctx *flash, const chipaddr addr); void fallback_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len); -struct par_programmer { +struct par_master { void (*chip_writeb) (const struct flashctx *flash, uint8_t val, chipaddr addr); void (*chip_writew) (const struct flashctx *flash, uint16_t val, chipaddr addr); void (*chip_writel) (const struct flashctx *flash, uint32_t val, chipaddr addr); @@ -659,18 +659,18 @@ void (*chip_readn) (const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len); const void *data; }; -int register_par_programmer(const struct par_programmer *pgm, const enum chipbustype buses); -struct registered_programmer { +int register_par_master(const struct par_master *mst, const enum chipbustype buses); +struct registered_master { enum chipbustype buses_supported; union { - struct par_programmer par; - struct spi_programmer spi; - struct opaque_programmer opaque; + struct par_master par; + struct spi_master spi; + struct opaque_master opaque; }; }; -extern struct registered_programmer registered_programmers[]; -extern int registered_programmer_count; -int register_programmer(struct registered_programmer *pgm); +extern struct registered_master registered_masters[]; +extern int registered_master_count; +int register_master(struct registered_master *mst); /* serprog.c */ #if CONFIG_SERPROG == 1 Modified: trunk/rayer_spi.c ============================================================================== --- trunk/rayer_spi.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/rayer_spi.c Sun Jul 20 00:03:29 2014 (r1831) @@ -228,7 +228,7 @@ if (pinout->preinit) pinout->preinit(pinout); - if (bitbang_spi_init(&bitbang_spi_master_rayer)) + if (register_spi_bitbang_master(&bitbang_spi_master_rayer)) return 1; return 0; Modified: trunk/satamv.c ============================================================================== --- trunk/satamv.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/satamv.c Sun Jul 20 00:03:29 2014 (r1831) @@ -46,7 +46,7 @@ chipaddr addr); static uint8_t satamv_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_satamv = { +static const struct par_master par_master_satamv = { .chip_readb = satamv_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -152,7 +152,7 @@ /* 512 kByte with two 8-bit latches, and * 4 MByte with additional 3-bit latch. */ max_rom_decode.parallel = 4 * 1024 * 1024; - register_par_programmer(&par_programmer_satamv, BUS_PARALLEL); + register_par_master(&par_master_satamv, BUS_PARALLEL); return 0; } Modified: trunk/satasii.c ============================================================================== --- trunk/satasii.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/satasii.c Sun Jul 20 00:03:29 2014 (r1831) @@ -43,7 +43,7 @@ static void satasii_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr); static uint8_t satasii_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_satasii = { +static const struct par_master par_master_satasii = { .chip_readb = satasii_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -104,7 +104,7 @@ if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26)))) msg_pwarn("Warning: Flash seems unconnected.\n"); - register_par_programmer(&par_programmer_satasii, BUS_PARALLEL); + register_par_master(&par_master_satasii, BUS_PARALLEL); return 0; } Modified: trunk/sb600spi.c ============================================================================== --- trunk/sb600spi.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/sb600spi.c Sun Jul 20 00:03:29 2014 (r1831) @@ -64,7 +64,7 @@ static int spi100_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -static struct spi_programmer spi_programmer_sb600 = { +static struct spi_master spi_master_sb600 = { .type = SPI_CONTROLLER_SB600, .max_data_read = FIFO_SIZE_OLD, .max_data_write = FIFO_SIZE_OLD - 3, @@ -75,7 +75,7 @@ .write_aai = default_spi_write_aai, }; -static struct spi_programmer spi_programmer_yangtze = { +static struct spi_master spi_master_yangtze = { .type = SPI_CONTROLLER_YANGTZE, .max_data_read = FIFO_SIZE_YANGTZE - 3, /* Apparently the big SPI 100 buffer is not a ring buffer. */ .max_data_write = FIFO_SIZE_YANGTZE - 3, @@ -184,14 +184,14 @@ /* Check the number of bytes to be transmitted and extract opcode. */ static int check_readwritecnt(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt) { - unsigned int maxwritecnt = flash->pgm->spi.max_data_write + 3; + unsigned int maxwritecnt = flash->mst->spi.max_data_write + 3; if (writecnt > maxwritecnt) { msg_pinfo("%s: SPI controller can not send %d bytes, it is limited to %d bytes\n", __func__, writecnt, maxwritecnt); return SPI_INVALID_LENGTH; } - unsigned int maxreadcnt = flash->pgm->spi.max_data_read + 3; + unsigned int maxreadcnt = flash->mst->spi.max_data_read + 3; if (readcnt > maxreadcnt) { msg_pinfo("%s: SPI controller can not receive %d bytes, it is limited to %d bytes\n", __func__, readcnt, maxreadcnt); @@ -690,9 +690,9 @@ /* Starting with Yangtze the SPI controller got a different interface with a much bigger buffer. */ if (amd_gen != CHIPSET_YANGTZE) - register_spi_programmer(&spi_programmer_sb600); + register_spi_master(&spi_master_sb600); else - register_spi_programmer(&spi_programmer_yangtze); + register_spi_master(&spi_master_yangtze); return 0; } Modified: trunk/serprog.c ============================================================================== --- trunk/serprog.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/serprog.c Sun Jul 20 00:03:29 2014 (r1831) @@ -303,7 +303,7 @@ unsigned char *readarr); static int serprog_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); -static struct spi_programmer spi_programmer_serprog = { +static struct spi_master spi_master_serprog = { .type = SPI_CONTROLLER_SERPROG, .max_data_read = MAX_DATA_READ_UNLIMITED, .max_data_write = MAX_DATA_WRITE_UNLIMITED, @@ -320,7 +320,7 @@ const chipaddr addr); static void serprog_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len); -static const struct par_programmer par_programmer_serprog = { +static const struct par_master par_master_serprog = { .chip_readb = serprog_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -489,7 +489,7 @@ v |= ((unsigned int)(rbuf[2]) << 16); if (v == 0) v = (1 << 24) - 1; /* SPI-op maximum. */ - spi_programmer_serprog.max_data_write = v; + spi_master_serprog.max_data_write = v; msg_pdbg(MSGHEADER "Maximum write-n length is %d\n", v); } if (!sp_docommand(S_CMD_Q_RDNMAXLEN, 0, NULL, 3, rbuf)) { @@ -499,7 +499,7 @@ v |= ((unsigned int)(rbuf[2]) << 16); if (v == 0) v = (1 << 24) - 1; /* SPI-op maximum. */ - spi_programmer_serprog.max_data_read = v; + spi_master_serprog.max_data_read = v; msg_pdbg(MSGHEADER "Maximum read-n length is %d\n", v); } spispeed = extract_programmer_param("spispeed"); @@ -669,10 +669,9 @@ sp_streamed_transmit_bytes = 0; sp_opbuf_usage = 0; if (serprog_buses_supported & BUS_SPI) - register_spi_programmer(&spi_programmer_serprog); + register_spi_master(&spi_master_serprog); if (serprog_buses_supported & BUS_NONSPI) - register_par_programmer(&par_programmer_serprog, - serprog_buses_supported & BUS_NONSPI); + register_par_master(&par_master_serprog, serprog_buses_supported & BUS_NONSPI); return 0; } @@ -932,7 +931,7 @@ unsigned int start, unsigned int len) { unsigned int i, cur_len; - const unsigned int max_read = spi_programmer_serprog.max_data_read; + const unsigned int max_read = spi_master_serprog.max_data_read; for (i = 0; i < len; i += cur_len) { int ret; cur_len = min(max_read, (len - i)); Modified: trunk/spi.c ============================================================================== --- trunk/spi.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/spi.c Sun Jul 20 00:03:29 2014 (r1831) @@ -34,13 +34,13 @@ unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { - return flash->pgm->spi.command(flash, writecnt, readcnt, writearr, + return flash->mst->spi.command(flash, writecnt, readcnt, writearr, readarr); } int spi_send_multicommand(struct flashctx *flash, struct spi_command *cmds) { - return flash->pgm->spi.multicommand(flash, cmds); + return flash->mst->spi.multicommand(flash, cmds); } int default_spi_send_command(struct flashctx *flash, unsigned int writecnt, @@ -78,7 +78,7 @@ int default_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len) { - unsigned int max_data = flash->pgm->spi.max_data_read; + unsigned int max_data = flash->mst->spi.max_data_read; if (max_data == MAX_DATA_UNSPECIFIED) { msg_perr("%s called, but SPI read chunk size not defined " "on this hardware. Please report a bug at " @@ -90,7 +90,7 @@ int default_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len) { - unsigned int max_data = flash->pgm->spi.max_data_write; + unsigned int max_data = flash->mst->spi.max_data_write; if (max_data == MAX_DATA_UNSPECIFIED) { msg_perr("%s called, but SPI write chunk size not defined " "on this hardware. Please report a bug at " @@ -124,7 +124,7 @@ "access window.\n"); msg_perr("Read will probably return garbage.\n"); } - return flash->pgm->spi.read(flash, buf, addrbase + start, len); + return flash->mst->spi.read(flash, buf, addrbase + start, len); } /* @@ -136,17 +136,17 @@ /* real chunksize is up to 256, logical chunksize is 256 */ int spi_chip_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len) { - return flash->pgm->spi.write_256(flash, buf, start, len); + return flash->mst->spi.write_256(flash, buf, start, len); } /* * Get the lowest allowed address for read accesses. This often happens to * be the lowest allowed address for all commands which take an address. - * This is a programmer limitation. + * This is a master limitation. */ uint32_t spi_get_valid_read_addr(struct flashctx *flash) { - switch (flash->pgm->spi.type) { + switch (flash->mst->spi.type) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_ICH7: @@ -162,25 +162,25 @@ int spi_aai_write(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len) { - return flash->pgm->spi.write_aai(flash, buf, start, len); + return flash->mst->spi.write_aai(flash, buf, start, len); } -int register_spi_programmer(const struct spi_programmer *pgm) +int register_spi_master(const struct spi_master *mst) { - struct registered_programmer rpgm; + struct registered_master rmst; - if (!pgm->write_aai || !pgm->write_256 || !pgm->read || !pgm->command || - !pgm->multicommand || - ((pgm->command == default_spi_send_command) && - (pgm->multicommand == default_spi_send_multicommand))) { - msg_perr("%s called with incomplete programmer definition. " + if (!mst->write_aai || !mst->write_256 || !mst->read || !mst->command || + !mst->multicommand || + ((mst->command == default_spi_send_command) && + (mst->multicommand == default_spi_send_multicommand))) { + msg_perr("%s called with incomplete master definition. " "Please report a bug at flashrom(a)flashrom.org\n", __func__); return ERROR_FLASHROM_BUG; } - rpgm.buses_supported = BUS_SPI; - rpgm.spi = *pgm; - return register_programmer(&rpgm); + rmst.buses_supported = BUS_SPI; + rmst.spi = *mst; + return register_master(&rmst); } Modified: trunk/spi25.c ============================================================================== --- trunk/spi25.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/spi25.c Sun Jul 20 00:03:29 2014 (r1831) @@ -172,7 +172,7 @@ /* Some SPI controllers do not support commands with writecnt=1 and * readcnt=4. */ - switch (flash->pgm->spi.type) { + switch (flash->mst->spi.type) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_IT87XX: @@ -1079,7 +1079,7 @@ .readarr = NULL, }}; - switch (flash->pgm->spi.type) { + switch (flash->mst->spi.type) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) case SPI_CONTROLLER_IT87XX: Modified: trunk/usbblaster_spi.c ============================================================================== --- trunk/usbblaster_spi.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/usbblaster_spi.c Sun Jul 20 00:03:29 2014 (r1831) @@ -55,7 +55,7 @@ {} }; -static const struct spi_programmer spi_programmer_usbblaster; +static const struct spi_master spi_master_usbblaster; static struct ftdi_context ftdic; @@ -117,7 +117,7 @@ return -1; } - register_spi_programmer(&spi_programmer_usbblaster); + register_spi_master(&spi_master_usbblaster); return 0; } @@ -211,7 +211,7 @@ } -static const struct spi_programmer spi_programmer_usbblaster = { +static const struct spi_master spi_master_usbblaster = { .type = SPI_CONTROLLER_USBBLASTER, .max_data_read = 256, .max_data_write = 256, Modified: trunk/wbsio_spi.c ============================================================================== --- trunk/wbsio_spi.c Tue Jul 15 15:50:58 2014 (r1830) +++ trunk/wbsio_spi.c Sun Jul 20 00:03:29 2014 (r1831) @@ -68,7 +68,7 @@ static int wbsio_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); -static const struct spi_programmer spi_programmer_wbsio = { +static const struct spi_master spi_master_wbsio = { .type = SPI_CONTROLLER_WBSIO, .max_data_read = MAX_DATA_UNSPECIFIED, .max_data_write = MAX_DATA_UNSPECIFIED, @@ -90,7 +90,7 @@ msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " "1024 kB!\n", __func__); max_rom_decode.spi = 1024 * 1024; - register_spi_programmer(&spi_programmer_wbsio); + register_spi_master(&spi_master_wbsio); return 0; }

1 0

site down
by Javier Camacho 18 Jul '14

18 Jul '14

Hi, your website is down, that is normal? or it is a maintenance shutdown? thanks! -- "De todos los cafés del mundo, tuvo que elegir el mío"

1 0

[PATCH] Add new programmer for SPI EEPROMs attached to Intel 82580 NICs.
by Stefan Tauner 17 Jul '14

17 Jul '14

This patch lets you read and write the EEPROM on 82580-based gigabit NIC cards. So far it has been tested on copper NICs only, but other variants employing this controller should work too. It is a nice substitution for the official eeupdate tool. Speed is quite decent: less than 5 seconds for writes of 32 kB chips. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- Hello Ricardo, the patch is not merged yet but I think the final version is attached below (applicable to r1830). We have integrated proper support for EEPROM semantics in r1822 which is used in this patch. This allows flashrom to write without prior erases which were implicitly scheduled without said patch unnecessarily on EEPROMs. Maybe this even speeds up things a bit. I'll commit the patch as soon as it got tested. Thanks again for the initial patch, all the testing and also your patience with us ;) Makefile | 14 +++ flashrom.8.tmpl | 16 ++- flashrom.c | 12 ++ nicintel_eeprom.c | 331 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ programmer.h | 9 ++ 5 files changed, 379 insertions(+), 3 deletions(-) create mode 100644 nicintel_eeprom.c diff --git a/Makefile b/Makefile index 7a48889..64798c9 100644 --- a/Makefile +++ b/Makefile @@ -227,6 +227,11 @@ UNSUPPORTED_FEATURES += CONFIG_NICINTEL=yes else override CONFIG_NICINTEL = no endif +ifeq ($(CONFIG_NICINTEL_EEPROM), yes) +UNSUPPORTED_FEATURES += CONFIG_NICINTEL_EEPROM=yes +else +override CONFIG_NICINTEL_EEPROM = no +endif ifeq ($(CONFIG_NICINTEL_SPI), yes) UNSUPPORTED_FEATURES += CONFIG_NICINTEL_SPI=yes else @@ -426,6 +431,9 @@ CONFIG_NICINTEL ?= yes # Always enable SPI on Intel NICs for now. CONFIG_NICINTEL_SPI ?= yes +# Always enable EEPROM on Intel NICs for now. +CONFIG_NICINTEL_EEPROM ?= yes + # Always enable SPI on OGP cards for now. CONFIG_OGP_SPI ?= yes @@ -626,6 +634,12 @@ PROGRAMMER_OBJS += nicintel_spi.o NEED_PCI := yes endif +ifeq ($(CONFIG_NICINTEL_EEPROM), yes) +FEATURE_CFLAGS += -D'CONFIG_NICINTEL_EEPROM=1' +PROGRAMMER_OBJS += nicintel_eeprom.o +NEED_PCI := yes +endif + ifeq ($(CONFIG_OGP_SPI), yes) FEATURE_CFLAGS += -D'CONFIG_OGP_SPI=1' PROGRAMMER_OBJS += ogp_spi.o diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index 0b4867d..153591a 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -225,6 +225,8 @@ bitbanging adapter) .sp .BR "* usbblaster_spi" " (for SPI flash ROMs attached to an Altera USB-Blaster compatible cable)" .sp +.BR "* nicintel_eeprom" " (for SPI EEPROMs on Intel Gigabit network cards)" +.sp Some programmers have optional or mandatory parameters which are described in detail in the .B PROGRAMMER SPECIFIC INFO @@ -591,7 +593,7 @@ syntax where .B content is an 8-bit hexadecimal value. .SS -.BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel"\ +.BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel", " nicintel_eeprom"\ , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii"\ , " satamv" , " atahpt" ", " atavia " and " it8212 " programmers These programmers have an option to specify the PCI address of the card @@ -625,6 +627,14 @@ For more information please see .nh .B http://flashrom.org/VT6421A .SS +.BR "nicintel_eeprom " programmer +This is the first programmer module in flashrom that does not provide access to NOR flash chips but EEPROMs +mounted on gigabit Ethernet cards based on Intel's 82580 NIC. Because EEPROMs normally do not announce their +size nor allow to be identified, the controller relies on correct size values written to predefined addresses +within the chip. Flashrom follows this scheme but assumes the minimum size of 16 kB (128 kb) if an unprogrammed +EEPROM/card is detected. Intel specifies following EEPROMs to be compatible: Atmel AT25128, AT25256, Micron (ST) +M95128, M95256 and OnSemi (Catalyst) CAT25CS128. +.SS .BR "ft2232_spi " programmer An optional parameter specifies the controller type and channel/interface/port it should support. For that you have to use the @@ -922,8 +932,8 @@ need PCI configuration space access and raw memory access. .B rayer_spi needs raw I/O port access. .sp -.B satasii -needs PCI configuration space read access and raw memory access. +.BR satasii ", " nicintel ", " nicintel_eeprom " and " nicintel_spi +need PCI configuration space read access and raw memory access. .sp .B satamv needs PCI configuration space read access, raw I/O port access and raw memory diff --git a/flashrom.c b/flashrom.c index 4f41bf4..f7d1803 100644 --- a/flashrom.c +++ b/flashrom.c @@ -297,6 +297,18 @@ const struct programmer_entry programmer_table[] = { }, #endif +#if CONFIG_NICINTEL_EEPROM == 1 + { + .name = "nicintel_eeprom", + .type = PCI, + .devs.dev = nics_intel_ee, + .init = nicintel_ee_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + #if CONFIG_OGP_SPI == 1 { .name = "ogp_spi", diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c new file mode 100644 index 0000000..b03899f --- /dev/null +++ b/nicintel_eeprom.c @@ -0,0 +1,331 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2013 Ricardo Ribalda - Qtechnology A/S + * Copyright (C) 2011, 2014 Stefan Tauner + * + * Based on nicinctel_spi.c and ichspi.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +/* + * Datasheet: Intel 82580 Quad/Dual Gigabit Ethernet LAN Controller Datasheet + * 3.3.1.4: General EEPROM Software Access + * 4.7: Access to shared resources (FIXME: we should probably use this semaphore interface) + * 7.4: Register Descriptions + */ + +#include <stdlib.h> +#include <unistd.h> +#include "flash.h" +#include "spi.h" +#include "programmer.h" +#include "hwaccess.h" + +#define PCI_VENDOR_ID_INTEL 0x8086 +#define MEMMAP_SIZE (0x14 + 3) /* Only EEC and EERD are needed. */ + +#define EEC 0x10 /* EEPROM/Flash Control Register */ +#define EERD 0x14 /* EEPROM Read Register */ + +/* EPROM/Flash Control Register bits */ +#define EE_SCK 0 +#define EE_CS 1 +#define EE_SI 2 +#define EE_SO 3 +#define EE_REQ 6 +#define EE_GNT 7 +#define EE_PRES 8 +#define EE_SIZE 11 +#define EE_SIZE_MASK 0xf + +/* EEPROM Read Register bits */ +#define EERD_START 0 +#define EERD_DONE 1 +#define EERD_ADDR 2 +#define EERD_DATA 16 + +#define BIT(x) (1<<x) +#define PAGE_MASK 0x3f + +static uint8_t *nicintel_eebar; +static struct pci_dev *nicintel_pci; + +#define UNPROG_DEVICE 0x1509 + +const struct dev_entry nics_intel_ee[] = { + {PCI_VENDOR_ID_INTEL, 0x150e, OK, "Intel", "82580 Quad Gigabit Ethernet Controller (Copper)"}, + {PCI_VENDOR_ID_INTEL, 0x150f, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Fiber)"}, + {PCI_VENDOR_ID_INTEL, 0x1510, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Backplane)"}, + {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Ext. PHY)"}, + {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Dual Gigabit Ethernet Controller (Copper)"}, + {PCI_VENDOR_ID_INTEL, UNPROG_DEVICE, OK, "Intel", "Unprogrammed 82580 Quad/Dual Gigabit Ethernet Controller"}, + {0}, +}; + +static int nicintel_ee_probe(struct flashctx *flash) +{ + if (nicintel_pci->device_id == UNPROG_DEVICE) + flash->chip->total_size = 16; /* Fall back to minimum supported size. */ + else { + uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC); + tmp = ((tmp >> EE_SIZE) & EE_SIZE_MASK); + switch (tmp) { + case 7: + flash->chip->total_size = 16; + break; + case 8: + flash->chip->total_size = 32; + break; + default: + msg_cerr("Unsupported chip size 0x%x\n", tmp); + return 0; + } + } + + flash->chip->page_size = PAGE_MASK + 1; + flash->chip->tested = TEST_OK_PREW; + flash->chip->gran = write_gran_1byte_implicit_erase; + flash->chip->block_erasers->eraseblocks[0].size = (PAGE_MASK + 1); + flash->chip->block_erasers->eraseblocks[0].count = (flash->chip->total_size * 1024) / (PAGE_MASK + 1); + + return 1; +} + +static int nicintel_ee_read_word(unsigned int addr, uint16_t *word) +{ + uint32_t tmp = BIT(EERD_START) | (addr << EERD_ADDR); + pci_mmio_writel(tmp, nicintel_eebar + EERD); + + /* Poll done flag. 10.000.000 cycles seem to be enough. */ + uint32_t i; + for (i = 0; i < 10000000; i++) { + tmp = pci_mmio_readl(nicintel_eebar + EERD); + if (tmp & BIT(EERD_DONE)) { + *word = (tmp >> EERD_DATA) & 0xffff; + return 0; + } + } + + return -1; +} + +static int nicintel_ee_read(struct flashctx *flash, uint8_t *buf, unsigned int addr, unsigned int len) +{ + uint16_t word; + + /* The NIC interface always reads 16 b words so we need to convert the address and handle odd address + * explicitly at the start (and also at the end in the loop below). */ + if (addr & 1) { + if (nicintel_ee_read_word(addr / 2, &word)) + return -1; + *buf++ = word & 0xff; + addr++; + len--; + } + + while (len > 0) { + if (nicintel_ee_read_word(addr / 2, &word)) + return -1; + *buf++ = word & 0xff; + addr++; + len--; + if (len > 0) { + *buf++ = (word >> 8) & 0xff; + addr++; + len--; + } + } + + return 0; +} + +static int nicintel_ee_bitset(int reg, int bit, bool val) +{ + uint32_t tmp; + + tmp = pci_mmio_readl(nicintel_eebar + reg); + if (val) + tmp |= BIT(bit); + else + tmp &= ~BIT(bit); + pci_mmio_writel(tmp, nicintel_eebar + reg); + + return -1; +} + +/* Shifts one byte out while receiving another one by bitbanging (denoted "direct access" in the datasheet). */ +static int nicintel_ee_bitbang(uint8_t mosi, uint8_t *miso) +{ + uint8_t out = 0x0; + + int i; + for (i = 7; i >= 0; i--) { + nicintel_ee_bitset(EEC, EE_SI, mosi & BIT(i)); + nicintel_ee_bitset(EEC, EE_SCK, 1); + if (miso != NULL) { + uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC); + if (tmp & BIT(EE_SO)) + out |= BIT(i); + } + nicintel_ee_bitset(EEC, EE_SCK, 0); + } + + if (miso != NULL) + *miso = out; + + return 0; +} + +/* Polls the WIP bit of the status register of the attached EEPROM via bitbanging. */ +static int nicintel_ee_ready(void) +{ + unsigned int i; + for (i = 0; i < 1000; i++) { + nicintel_ee_bitset(EEC, EE_CS, 0); + + nicintel_ee_bitbang(JEDEC_RDSR, NULL); + uint8_t rdsr; + nicintel_ee_bitbang(0x00, &rdsr); + + nicintel_ee_bitset(EEC, EE_CS, 1); + programmer_delay(1); + if (!(rdsr & SPI_SR_WIP)) { + return 0; + } + } + return -1; +} + +/* Requests direct access to the SPI pins. */ +static int nicintel_ee_req(void) +{ + uint32_t tmp; + nicintel_ee_bitset(EEC, EE_REQ, 1); + + tmp = pci_mmio_readl(nicintel_eebar + EEC); + if (!(tmp & BIT(EE_GNT))) { + msg_perr("Enabling eeprom access failed.\n"); + return 1; + } + + nicintel_ee_bitset(EEC, EE_SCK, 0); + return 0; +} + +static int nicintel_ee_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len) +{ + if (nicintel_ee_req()) + return -1; + + int ret = -1; + if (nicintel_ee_ready()) + goto out; + + while (len > 0) { + /* WREN */ + nicintel_ee_bitset(EEC, EE_CS, 0); + nicintel_ee_bitbang(JEDEC_WREN, NULL); + nicintel_ee_bitset(EEC, EE_CS, 1); + programmer_delay(1); + + /* data */ + nicintel_ee_bitset(EEC, EE_CS, 0); + nicintel_ee_bitbang(JEDEC_BYTE_PROGRAM, NULL); + nicintel_ee_bitbang((addr >> 8) & 0xff, NULL); + nicintel_ee_bitbang(addr & 0xff, NULL); + while (len > 0) { + nicintel_ee_bitbang((buf) ? *buf++ : 0xff, NULL); + len--; + addr++; + if (!(addr & PAGE_MASK)) + break; + } + nicintel_ee_bitset(EEC, EE_CS, 1); + programmer_delay(1); + if (nicintel_ee_ready()) + goto out; + } + ret = 0; +out: + nicintel_ee_bitset(EEC, EE_REQ, 0); /* Give up direct access. */ + return ret; +} + +static int nicintel_ee_erase(struct flashctx *flash, unsigned int addr, unsigned int len) +{ + return nicintel_ee_write(flash, NULL, addr, len); +} + +static const struct opaque_programmer opaque_programmer_nicintel_ee = { + .probe = nicintel_ee_probe, + .read = nicintel_ee_read, + .write = nicintel_ee_write, + .erase = nicintel_ee_erase, +}; + +static int nicintel_spi_shutdown(void *eecp) +{ + uint32_t old_eec = *(uint32_t *)eecp; + /* Request bitbanging and unselect the chip first to be safe. */ + if (nicintel_ee_req() || nicintel_ee_bitset(EEC, EE_CS, 1)) + return -1; + + /* Try to restore individual bits we care about. */ + int ret = nicintel_ee_bitset(EEC, EE_SCK, old_eec & BIT(EE_SCK)); + ret |= nicintel_ee_bitset(EEC, EE_SI, old_eec & BIT(EE_SI)); + ret |= nicintel_ee_bitset(EEC, EE_CS, old_eec & BIT(EE_CS)); + /* REQ will be cleared by hardware anyway after 2 seconds of inactivity on the SPI pins (3.3.2.1). */ + ret |= nicintel_ee_bitset(EEC, EE_REQ, old_eec & BIT(EE_REQ)); + + free(eecp); + return ret; +} + +int nicintel_ee_init(void) +{ + if (rget_io_perms()) + return 1; + + struct pci_dev *dev = pcidev_init(nics_intel_ee, PCI_BASE_ADDRESS_0); + if (!dev) + return 1; + + uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + if (!io_base_addr) + return 1; + + nicintel_eebar = rphysmap("Intel Gigabit NIC w/ SPI EEPROM", io_base_addr, MEMMAP_SIZE); + nicintel_pci = dev; + if (dev->device_id != UNPROG_DEVICE) { + uint32_t eec = pci_mmio_readl(nicintel_eebar + EEC); + + /* C.f. 3.3.1.5 for the detection mechanism (maybe? contradicting the EE_PRES definition), + * and 3.3.1.7 for possible recovery. */ + if (!(eec & BIT(EE_PRES))) { + msg_perr("Controller reports no EEPROM is present.\n"); + return 1; + } + + uint32_t *eecp = malloc(sizeof(uint32_t)); + if (eecp == NULL) + return 1; + *eecp = eec; + + if (register_shutdown(nicintel_spi_shutdown, eecp)) + return 1; + } + + return register_opaque_programmer(&opaque_programmer_nicintel_ee); +} diff --git a/programmer.h b/programmer.h index b0df2ba..83a05b9 100644 --- a/programmer.h +++ b/programmer.h @@ -84,6 +84,9 @@ enum programmer { #if CONFIG_NICINTEL_SPI == 1 PROGRAMMER_NICINTEL_SPI, #endif +#if CONFIG_NICINTEL_EEPROM == 1 + PROGRAMMER_NICINTEL_EEPROM, +#endif #if CONFIG_OGP_SPI == 1 PROGRAMMER_OGP_SPI, #endif @@ -416,6 +419,12 @@ int nicintel_spi_init(void); extern const struct dev_entry nics_intel_spi[]; #endif +/* nicintel_eeprom.c */ +#if CONFIG_NICINTEL_EEPROM == 1 +int nicintel_ee_init(void); +extern const struct dev_entry nics_intel_ee[]; +#endif + /* ogp_spi.c */ #if CONFIG_OGP_SPI == 1 int ogp_spi_init(void); -- Kind regards, Stefan Tauner

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Re: [flashrom] ft2232_spi:type=jtagkey
by Stefan Tauner 16 Jul '14

16 Jul '14

On Thu, 5 Jun 2014 12:26:58 +0700 Alfin Cahya <alfincp(a)gmail.com> wrote: > Uh oh. Erase/write failed. Checking if anything has changed. > Reading current flash chip contents... done. > Apparently at least some data has changed. > Your flash chip is in an unknown state. That still looks to me like a floating write protection (or hold) pin. Sorry for the late reply... did you manage to get it to work eventually? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH] Add new programmer for EEPROMs attached to Intel 82580 NICs.
by Ricardo Ribalda Delgado 15 Jul '14

15 Jul '14

Hi Is this currently merged into some branch? Regards On Tue, Jun 17, 2014 at 1:24 AM, Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> wrote: > This patch lets you read and write the EEPROM on 82580-based gigabit NIC > cards. So far it has been tested on copper NICs only, but other variants > employing this controller should work too. > It is a nice substitution for the official eeupdate tool. > > Speed is quite decent: > > root@qt5022:~# time ./flashrom -p nicintel_eeprom:pci=03:00.0 -E > flashrom v0.9.7-r1622 on Linux 3.11.0-qtec-standard (x86_64) > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > Found Programmer flash chip "Opaque flash chip" (32 kB, Programmer-specific) on nicintel_eeprom. > Erasing and writing flash chip... Erase/write done. > > real 0m4.699s > user 0m4.676s > sys 0m0.024s > > root@qt5022:~# time ./flashrom -p nicintel_eeprom:pci=03:00.0 -w original.kk > flashrom v0.9.7-r1622 on Linux 3.11.0-qtec-standard (x86_64) > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > Found Programmer flash chip "Opaque flash chip" (32 kB, Programmer-specific) on nicintel_eeprom. > Reading old flash chip contents... done. > Erasing and writing flash chip... Erase/write done. > Verifying flash... VERIFIED. > > real 0m3.533s > user 0m3.516s > sys 0m0.018s > > Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> > Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> > --- > Makefile | 9 ++ > flashrom.8.tmpl | 13 ++- > flashrom.c | 12 ++ > nicintel_eeprom.c | 334 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ > programmer.h | 9 ++ > 5 files changed, 376 insertions(+), 1 deletion(-) > create mode 100644 nicintel_eeprom.c > > diff --git a/Makefile b/Makefile > index 7a48889..b47b644 100644 > --- a/Makefile > +++ b/Makefile > @@ -426,6 +426,9 @@ CONFIG_NICINTEL ?= yes > # Always enable SPI on Intel NICs for now. > CONFIG_NICINTEL_SPI ?= yes > > +# Always enable EEPROM on Intel NICs for now. > +CONFIG_NICINTEL_EEPROM ?= yes > + > # Always enable SPI on OGP cards for now. > CONFIG_OGP_SPI ?= yes > > @@ -626,6 +629,12 @@ PROGRAMMER_OBJS += nicintel_spi.o > NEED_PCI := yes > endif > > +ifeq ($(CONFIG_NICINTEL_EEPROM), yes) > +FEATURE_CFLAGS += -D'CONFIG_NICINTEL_EEPROM=1' > +PROGRAMMER_OBJS += nicintel_eeprom.o > +NEED_PCI := yes > +endif > + > ifeq ($(CONFIG_OGP_SPI), yes) > FEATURE_CFLAGS += -D'CONFIG_OGP_SPI=1' > PROGRAMMER_OBJS += ogp_spi.o > diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl > index 0b4867d..d3000c2 100644 > --- a/flashrom.8.tmpl > +++ b/flashrom.8.tmpl > @@ -225,6 +225,8 @@ bitbanging adapter) > .sp > .BR "* usbblaster_spi" " (for SPI flash ROMs attached to an Altera USB-Blaster compatible cable)" > .sp > +.BR "* nicintel_eeprom" " (for SPI EEPROMs on Intel Gigabit network cards)" > +.sp > Some programmers have optional or mandatory parameters which are described > in detail in the > .B PROGRAMMER SPECIFIC INFO > @@ -591,7 +593,7 @@ syntax where > .B content > is an 8-bit hexadecimal value. > .SS > -.BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel"\ > +.BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel", " nicintel_eeprom"\ > , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii"\ > , " satamv" , " atahpt" ", " atavia " and " it8212 " programmers > These programmers have an option to specify the PCI address of the card > @@ -625,6 +627,14 @@ For more information please see > .nh > .B http://flashrom.org/VT6421A > .SS > +.BR "nicintel_eeprom " programmer > +This is the first programmer module in flashrom that does not provide access to NOR flash chips but EEPROMs > +mounted on gigabit Ethernet cards based on Intel's 82580 NIC. Because EEPROMs normally do not announce their > +size nor allow to be identified, the controller relies on correct size values written to predefined addresses > +within the chip. Flashrom follows this scheme but assumes the minimum size of 16 kB (128 kb) if an unprogrammed > +EEPROM/card is detected. Intel specifies following EEPROMs to be compatible: Atmel AT25128, AT25256, Micron (ST) > +M95128, M95256 and OnSemi (Catalyst) CAT25CS128. > +.SS > .BR "ft2232_spi " programmer > An optional parameter specifies the controller > type and channel/interface/port it should support. For that you have to use the > @@ -903,6 +913,7 @@ flashrom exits with 0 on success, 1 on most failures but with 3 if a call to mma > .SH REQUIREMENTS > flashrom needs different access permissions for different programmers. > .sp > +.\" FIXME: nicintel* > .B internal > needs raw memory access, PCI configuration space access, raw I/O port > access (x86) and MSR access (x86). > diff --git a/flashrom.c b/flashrom.c > index 408c555..7375b2e 100644 > --- a/flashrom.c > +++ b/flashrom.c > @@ -297,6 +297,18 @@ const struct programmer_entry programmer_table[] = { > }, > #endif > > +#if CONFIG_NICINTEL_EEPROM == 1 > + { > + .name = "nicintel_eeprom", > + .type = PCI, > + .devs.dev = nics_intel_ee, > + .init = nicintel_ee_init, > + .map_flash_region = fallback_map, > + .unmap_flash_region = fallback_unmap, > + .delay = internal_delay, > + }, > +#endif > + > #if CONFIG_OGP_SPI == 1 > { > .name = "ogp_spi", > diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c > new file mode 100644 > index 0000000..48fac4a > --- /dev/null > +++ b/nicintel_eeprom.c > @@ -0,0 +1,334 @@ > +/* > + * This file is part of the flashrom project. > + * > + * Copyright (C) 2013 Ricardo Ribalda - Qtechnology A/S > + * Copyright (C) 2011, 2014 Stefan Tauner > + * > + * Based on nicinctel_spi.c and ichspi.c > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; version 2 of the License. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program. If not, see http://www.gnu.org/licenses/. > + */ > + > +/* > + * Datasheet: Intel 82580 Quad/Dual Gigabit Ethernet LAN Controller Datasheet > + * 3.3.1.4: General EEPROM Software Access > + * 4.7: Access to shared resources (FIXME: we should probably use this semaphore interface) > + * 7.4: Register Descriptions > + */ > + > +#include <stdlib.h> > +#include <unistd.h> > +#include "flash.h" > +#include "spi.h" > +#include "programmer.h" > +#include "hwaccess.h" > + > +#define PCI_VENDOR_ID_INTEL 0x8086 > +#define MEMMAP_SIZE (0x14 + 3) /* Only EEC and EERD are needed. */ > + > +#define EEC 0x10 /* EEPROM/Flash Control Register */ > +#define EERD 0x14 /* EEPROM Read Register */ > + > +/* EPROM/Flash Control Register bits */ > +#define EE_SCK 0 > +#define EE_CS 1 > +#define EE_SI 2 > +#define EE_SO 3 > +#define EE_REQ 6 > +#define EE_GNT 7 > +#define EE_PRES 8 > +#define EE_SIZE 11 > +#define EE_SIZE_MASK 0xf > + > +/* EEPROM Read Register bits */ > +#define EERD_START 0 > +#define EERD_DONE 1 > +#define EERD_ADDR 2 > +#define EERD_DATA 16 > + > +#define BIT(x) (1<<x) > +#define PAGE_MASK 0x3f > + > +static uint8_t *nicintel_eebar; > +static struct pci_dev *nicintel_pci; > + > +#define UNPROG_DEVICE 0x1509 > + > +const struct dev_entry nics_intel_ee[] = { > + {PCI_VENDOR_ID_INTEL, 0x150e, OK, "Intel", "82580 Quad Gigabit Ethernet Controller (Copper)"}, > + {PCI_VENDOR_ID_INTEL, 0x150f, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Fiber)"}, > + {PCI_VENDOR_ID_INTEL, 0x1510, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Backplane)"}, > + {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Quad Gigabit Ethernet Controller (Ext. PHY)"}, > + {PCI_VENDOR_ID_INTEL, 0x1511, NT , "Intel", "82580 Dual Gigabit Ethernet Controller (Copper)"}, > + {PCI_VENDOR_ID_INTEL, UNPROG_DEVICE, OK, "Intel", "Unprogrammed 82580 Quad/Dual Gigabit Ethernet Controller"}, > + {0}, > +}; > + > +static int nicintel_ee_probe(struct flashctx *flash) > +{ > + if (nicintel_pci->device_id == UNPROG_DEVICE) > + flash->chip->total_size = 16; /* Fall back to minimum supported size. */ > + else { > + uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC); > + tmp = ((tmp >> EE_SIZE) & EE_SIZE_MASK); > + switch (tmp) { > + case 7: > + flash->chip->total_size = 16; > + break; > + case 8: > + flash->chip->total_size = 32; > + break; > + default: > + msg_cerr("Unsupported chip size 0x%x\n", tmp); > + return 0; > + } > + } > + > + flash->chip->page_size = PAGE_MASK + 1; > + flash->chip->tested = TEST_OK_PREW; > + /* FIXME: Due to the write_granularity set below we do 0xFF dummy writes to fake erases on every write > + * which is completely pointless and potentially even harmful for the hardware. Programmers/devices > + * should be able to indicate that erases are not needed for writes. */ > + flash->chip->gran = write_gran_1byte; > + flash->chip->block_erasers->eraseblocks[0].size = (PAGE_MASK + 1); > + flash->chip->block_erasers->eraseblocks[0].count = (flash->chip->total_size * 1024) / (PAGE_MASK + 1); > + > + return 1; > +} > + > +static int nicintel_ee_read_word(unsigned int addr, uint16_t *word) > +{ > + uint32_t tmp = BIT(EERD_START) | (addr << EERD_ADDR); > + pci_mmio_writel(tmp, nicintel_eebar + EERD); > + > + /* Poll done flag. 10.000.000 cycles seem to be enough. */ > + uint32_t i; > + for (i = 0; i < 10000000; i++) { > + tmp = pci_mmio_readl(nicintel_eebar + EERD); > + if (tmp & BIT(EERD_DONE)) { > + *word = (tmp >> EERD_DATA) & 0xffff; > + return 0; > + } > + } > + > + return -1; > +} > + > +static int nicintel_ee_read(struct flashctx *flash, uint8_t *buf, unsigned int addr, unsigned int len) > +{ > + uint16_t word; > + > + /* The NIC interface always reads 16 b words so we need to convert the address and handle odd address > + * explicitly at the start (and also at the end in the loop below). */ > + if (addr & 1) { > + if (nicintel_ee_read_word(addr / 2, &word)) > + return -1; > + *buf++ = word & 0xff; > + addr++; > + len--; > + } > + > + while (len > 0) { > + if (nicintel_ee_read_word(addr / 2, &word)) > + return -1; > + *buf++ = word & 0xff; > + addr++; > + len--; > + if (len > 0) { > + *buf++ = (word >> 8) & 0xff; > + addr++; > + len--; > + } > + } > + > + return 0; > +} > + > +static int nicintel_ee_bitset(int reg, int bit, bool val) > +{ > + uint32_t tmp; > + > + tmp = pci_mmio_readl(nicintel_eebar + reg); > + if (val) > + tmp |= BIT(bit); > + else > + tmp &= ~BIT(bit); > + pci_mmio_writel(tmp, nicintel_eebar + reg); > + > + return -1; > +} > + > +/* Shifts one byte out while receiving another one by bitbanging (denoted "direct access" in the datasheet). */ > +static int nicintel_ee_bitbang(uint8_t mosi, uint8_t *miso) > +{ > + uint8_t out = 0x0; > + > + int i; > + for (i = 7; i >= 0; i--) { > + nicintel_ee_bitset(EEC, EE_SI, mosi & BIT(i)); > + nicintel_ee_bitset(EEC, EE_SCK, 1); > + if (miso != NULL) { > + uint32_t tmp = pci_mmio_readl(nicintel_eebar + EEC); > + if (tmp & BIT(EE_SO)) > + out |= BIT(i); > + } > + nicintel_ee_bitset(EEC, EE_SCK, 0); > + } > + > + if (miso != NULL) > + *miso = out; > + > + return 0; > +} > + > +/* Polls the WIP bit of the status register of the attached EEPROM via bitbanging. */ > +static int nicintel_ee_ready(void) > +{ > + unsigned int i; > + for (i = 0; i < 1000; i++) { > + nicintel_ee_bitset(EEC, EE_CS, 0); > + > + nicintel_ee_bitbang(JEDEC_RDSR, NULL); > + uint8_t rdsr; > + nicintel_ee_bitbang(0x00, &rdsr); > + > + nicintel_ee_bitset(EEC, EE_CS, 1); > + programmer_delay(1); > + if (!(rdsr & SPI_SR_WIP)) { > + return 0; > + } > + } > + return -1; > +} > + > +/* Requests direct access to the SPI pins. */ > +static int nicintel_ee_req(void) > +{ > + uint32_t tmp; > + nicintel_ee_bitset(EEC, EE_REQ, 1); > + > + tmp = pci_mmio_readl(nicintel_eebar + EEC); > + if (!(tmp & BIT(EE_GNT))) { > + msg_perr("Enabling eeprom access failed.\n"); > + return 1; > + } > + > + nicintel_ee_bitset(EEC, EE_SCK, 0); > + return 0; > +} > + > +static int nicintel_ee_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len) > +{ > + if (nicintel_ee_req()) > + return -1; > + > + int ret = -1; > + if (nicintel_ee_ready()) > + goto out; > + > + while (len > 0) { > + /* WREN */ > + nicintel_ee_bitset(EEC, EE_CS, 0); > + nicintel_ee_bitbang(JEDEC_WREN, NULL); > + nicintel_ee_bitset(EEC, EE_CS, 1); > + programmer_delay(1); > + > + /* data */ > + nicintel_ee_bitset(EEC, EE_CS, 0); > + nicintel_ee_bitbang(JEDEC_BYTE_PROGRAM, NULL); > + nicintel_ee_bitbang((addr >> 8) & 0xff, NULL); > + nicintel_ee_bitbang(addr & 0xff, NULL); > + while (len > 0) { > + nicintel_ee_bitbang((buf) ? *buf++ : 0xff, NULL); > + len--; > + addr++; > + if (!(addr & PAGE_MASK)) > + break; > + } > + nicintel_ee_bitset(EEC, EE_CS, 1); > + programmer_delay(1); > + if (nicintel_ee_ready()) > + goto out; > + } > + ret = 0; > +out: > + nicintel_ee_bitset(EEC, EE_REQ, 0); /* Give up direct access. */ > + return ret; > +} > + > +static int nicintel_ee_erase(struct flashctx *flash, unsigned int addr, unsigned int len) > +{ > + return nicintel_ee_write(flash, NULL, addr, len); > +} > + > +static const struct opaque_programmer opaque_programmer_nicintel_ee = { > + .probe = nicintel_ee_probe, > + .read = nicintel_ee_read, > + .write = nicintel_ee_write, > + .erase = nicintel_ee_erase, > +}; > + > +static int nicintel_spi_shutdown(void *eecp) > +{ > + uint32_t old_eec = *(uint32_t *)eecp; > + /* Request bitbanging and unselect the chip first to be safe. */ > + if (nicintel_ee_req() || nicintel_ee_bitset(EEC, EE_CS, 1)) > + return -1; > + > + /* Try to restore individual bits we care about. */ > + int ret = nicintel_ee_bitset(EEC, EE_SCK, old_eec & BIT(EE_SCK)); > + ret |= nicintel_ee_bitset(EEC, EE_SI, old_eec & BIT(EE_SI)); > + ret |= nicintel_ee_bitset(EEC, EE_CS, old_eec & BIT(EE_CS)); > + /* REQ will be cleared by hardware anyway after 2 seconds of inactivity on the SPI pins (3.3.2.1). */ > + ret |= nicintel_ee_bitset(EEC, EE_REQ, old_eec & BIT(EE_REQ)); > + > + free(eecp); > + return ret; > +} > + > +int nicintel_ee_init(void) > +{ > + if (rget_io_perms()) > + return 1; > + > + struct pci_dev *dev = pcidev_init(nics_intel_ee, PCI_BASE_ADDRESS_0); > + if (!dev) > + return 1; > + > + uint32_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); > + if (!io_base_addr) > + return 1; > + > + nicintel_eebar = rphysmap("Intel Gigabit NIC w/ SPI EEPROM", io_base_addr, MEMMAP_SIZE); > + nicintel_pci = dev; > + if (dev->device_id != UNPROG_DEVICE) { > + uint32_t eec = pci_mmio_readl(nicintel_eebar + EEC); > + > + /* C.f. 3.3.1.5 for the detection mechanism (maybe? contradicting the EE_PRES definition), > + * and 3.3.1.7 for possible recovery. */ > + if (!(eec & BIT(EE_PRES))) { > + msg_perr("Controller reports no EEPROM is present.\n"); > + return 1; > + } > + > + uint32_t *eecp = malloc(sizeof(uint32_t)); > + if (eecp == NULL) > + return 1; > + *eecp = eec; > + > + if (register_shutdown(nicintel_spi_shutdown, eecp)) > + return 1; > + } > + > + return register_opaque_programmer(&opaque_programmer_nicintel_ee); > +} > diff --git a/programmer.h b/programmer.h > index b0df2ba..83a05b9 100644 > --- a/programmer.h > +++ b/programmer.h > @@ -84,6 +84,9 @@ enum programmer { > #if CONFIG_NICINTEL_SPI == 1 > PROGRAMMER_NICINTEL_SPI, > #endif > +#if CONFIG_NICINTEL_EEPROM == 1 > + PROGRAMMER_NICINTEL_EEPROM, > +#endif > #if CONFIG_OGP_SPI == 1 > PROGRAMMER_OGP_SPI, > #endif > @@ -416,6 +419,12 @@ int nicintel_spi_init(void); > extern const struct dev_entry nics_intel_spi[]; > #endif > > +/* nicintel_eeprom.c */ > +#if CONFIG_NICINTEL_EEPROM == 1 > +int nicintel_ee_init(void); > +extern const struct dev_entry nics_intel_ee[]; > +#endif > + > /* ogp_spi.c */ > #if CONFIG_OGP_SPI == 1 > int ogp_spi_init(void); > -- > Kind regards, Stefan Tauner > -- Ricardo Ribalda

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[commit] r1830 - trunk
by repository service 15 Jul '14

15 Jul '14

Author: stefanct Date: Tue Jul 15 15:50:58 2014 New Revision: 1830 URL: http://flashrom.org/trac/flashrom/changeset/1830 Log: Add support for AMD Bolton chipset. SPI controller on the bolton chipset uses the same 3-bit speed settings as Yangtze, but is otherwise the same as the Hudson chips. Note that the Bolton RRG doesn't specify a speed setting for the bit setting of 0b111, so I'm assuming that it's the same setting as Yangtze. Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/sb600spi.c Modified: trunk/sb600spi.c ============================================================================== --- trunk/sb600spi.c Tue Jul 15 15:50:17 2014 (r1829) +++ trunk/sb600spi.c Tue Jul 15 15:50:58 2014 (r1830) @@ -51,6 +51,7 @@ CHIPSET_SB7XX, /* SP5100 too */ CHIPSET_SB89XX, /* Hudson-1 too */ CHIPSET_HUDSON234, + CHIPSET_BOLTON, CHIPSET_YANGTZE, }; static enum amd_chipset amd_gen = CHIPSET_AMD_UNKNOWN; @@ -137,6 +138,9 @@ if (rev >= 0x11 && rev <= 0x15) { amd_gen = CHIPSET_HUDSON234; msg_pdbg("Hudson-2/3/4 detected.\n"); + } else if (rev == 0x16) { + amd_gen = CHIPSET_BOLTON; + msg_pdbg("Bolton detected.\n"); } else if (rev >= 0x39 && rev <= 0x3A) { amd_gen = CHIPSET_YANGTZE; msg_pdbg("Yangtze detected.\n"); @@ -409,23 +413,11 @@ } /* See the chipset support matrix for SPI Base_Addr below for an explanation of the symbols used. - * bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson234 yangtze + * bit 6xx 7xx/SP5100 8xx 9xx hudson1 hudson234 bolton/yangtze * 18 rsvd <- fastReadEnable ? <- ? SpiReadMode[0] * 29:30 rsvd <- <- ? <- ? SpiReadMode[2:1] */ - if (amd_gen >= CHIPSET_YANGTZE) { - tmp = mmio_readb(sb600_spibar + 0x20); - msg_pdbg("UseSpi100 is %sabled\n", (tmp & 0x1) ? "en" : "dis"); - if ((tmp & 0x1) == 0) { - rmmio_writeb(tmp | 0x1, sb600_spibar + 0x20); - tmp = mmio_readb(sb600_spibar + 0x20) & 0x1; - if (tmp == 0) { - msg_perr("Enabling Spi100 failed.\n"); - return 1; - } - msg_pdbg("Enabling Spi100 succeeded.\n"); - } - + if (amd_gen >= CHIPSET_BOLTON) { static const char *spireadmodes[] = { "Normal (up to 33 MHz)", /* 0 */ "Reserved", /* 1 */ @@ -434,7 +426,7 @@ "Dual IO (1-2-2)", /* 4 */ "Quad IO (1-4-4)", /* 5 */ "Normal (up to 66 MHz)", /* 6 */ - "Fast Read", /* 7 */ + "Fast Read", /* 7 (Not defined in the Bolton datasheet.) */ }; tmp = mmio_readl(sb600_spibar + 0x00); uint8_t read_mode = ((tmp >> 28) & 0x6) | ((tmp >> 18) & 0x1); @@ -448,11 +440,25 @@ msg_pdbg("Setting read mode to \"%s\" succeeded.\n", spireadmodes[read_mode]); } - tmp = mmio_readw(sb600_spibar + 0x22); /* SPI 100 Speed Config */ - msg_pdbg("NormSpeedNew is %s\n", spispeeds[(tmp >> 12) & 0xf].name); - msg_pdbg("FastSpeedNew is %s\n", spispeeds[(tmp >> 8) & 0xf].name); - msg_pdbg("AltSpeedNew is %s\n", spispeeds[(tmp >> 4) & 0xf].name); - msg_pdbg("TpmSpeedNew is %s\n", spispeeds[(tmp >> 0) & 0xf].name); + if (amd_gen >= CHIPSET_YANGTZE) { + tmp = mmio_readb(sb600_spibar + 0x20); + msg_pdbg("UseSpi100 is %sabled\n", (tmp & 0x1) ? "en" : "dis"); + if ((tmp & 0x1) == 0) { + rmmio_writeb(tmp | 0x1, sb600_spibar + 0x20); + tmp = mmio_readb(sb600_spibar + 0x20) & 0x1; + if (tmp == 0) { + msg_perr("Enabling Spi100 failed.\n"); + return 1; + } + msg_pdbg("Enabling Spi100 succeeded.\n"); + } + + tmp = mmio_readw(sb600_spibar + 0x22); /* SPI 100 Speed Config */ + msg_pdbg("NormSpeedNew is %s\n", spispeeds[(tmp >> 12) & 0xf].name); + msg_pdbg("FastSpeedNew is %s\n", spispeeds[(tmp >> 8) & 0xf].name); + msg_pdbg("AltSpeedNew is %s\n", spispeeds[(tmp >> 4) & 0xf].name); + msg_pdbg("TpmSpeedNew is %s\n", spispeeds[(tmp >> 0) & 0xf].name); + } } else { if (amd_gen >= CHIPSET_SB89XX && amd_gen <= CHIPSET_HUDSON234) { bool fast_read = (mmio_readl(sb600_spibar + 0x00) >> 18) & 0x1;

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