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[PATCH] Read/erase/program 4-bytes addressing SPI flash chips 32MB+ for 0.9.7-r1861 build
by Boris Baykov 09 Jan '15

09 Jan '15

Read/erase/program 4-bytes addressing SPI flash chips 32MB+ =========================================================== Current patch is for the last 0.9.7-r1861 build taken by SVN from svn://flashrom.org. The patch is made by SVN diff. This letter text contains spaces instead of tabs. My mail system doesn't want to send text of the patch as it is. For review this is enough but to apply the patch please use attached bzipped .patch file with correct text of the patch. Brief description ----------------- This patch adds ability to read, write and erase flash chips which require 4-bytes (32-bit) addressing to access to them. These are 32MB (256Mb) and larger new flash chips. Flashrom with this patch can support and program all (or most of all) of them. Besides of manually definable chips in flashchips.c this patch adds compliance to new JEDEC JESD216B standard which describes SFDP revision 1.6 procedure to read flash chip 4-bytes addressing details. Full description ---------------- This patch includes code for three types of 4-byte addressing: 1. Flash chip can be switched to 4-bytes addressing mode and then all read/erase/program instructions will be switched from 3-bytes mode to 4-bytes mode. So, well known instructions like 03h (Read), 02h (Program) and 20h,52h,D8h (Erase) are becoming one byte longer and accept 4-bytes address instead of 3-bytes. 4-bytes addressing mode is entered by the instruction B7h with preceding Write Enable (WREN). This is default method. 2. Also Flash chip data with addresses more than 24-bit field can address may be accessed by use of Extended Address Register that has 1-byte size and stores high byte of 32-bit address. So, we read flash from old 3-bytes addressing mode and write high byte of address to special register. Then we have access to full memory of a chip. Some chips may support this method only. 3. Also some new commands avalable and implemented. Large size flash chips support special instructions to use 4-bytes address directly from 3-bytes addressing mode and without do switching to 4-bytes mode. There are 13h (4BA Read), 12h (4BA Program) and 21h,5Ch,DCh (4BA Erase), correspondingly. However not all these commands are supported by all large flash chips. Some chips support 13h only, some 13h,12h,21h and DCh, but not 5Ch. This depends on the manufacturer of the chip. The patch adds code for all 3 types of 4-bytes address access and the exact method should be choosen by person who will manage to add new large chips to flashchips.c source file. I've added one new flash chip: Winbond W25Q256FV (32MB) because this is the only chip I have now for testing. Besides of manual including of new chips to Flashrom we may use SFDP procedure to discover parameters of the exact flash chip. More than a year before JEDEC released new standard JESD216 (revision B) which describes in detail how to receive 4-bytes addressing settings from the chip. This patch provides new code to add compliance to JESD216B to Flashrom. This means that Flashrom now can automatically detect 4-bytes addressing features of large flash chips and use them to access data. However not all thing are so good. Unfortunately JESD216B had come to manufacturer's production lines just 2-3 months ago. So, we have many chips that have large size requires 32-bit addressing but their SFDP tables have revision lower than 1.6 (described in JESD216B standard). For example my W25Q256FV returns SFDP info with revision 1.0, first one :-) This situation leads us to requirement to try to work now without new SFDP info. And it's implemented in the patch too. To test my parser code for SFDP revision 1.6 (from JESD216B) I've added some simulation code to sfdp.c. This code builds fake SFDP 1.6 tables in memory and passes them to the SFDP parser. Surely this simulation code is switched off by default and can be activated via hidden define on the top of sfdp.c Also I've added progress visualization for read, erase and write operations. It's turned out that seeing progress is essential for reading and especially writing 32 MB of data via SPI. The operation can take more then 10 minutes on 15 MHz frequency of SPI. So, it's good to see its progress. I've added percents and slightly modified cli_output.c to send percents to screen only but not to logfile. Testing results --------------- Both patches are tested with Winbond W25Q256FV flash chip using Olimex ARM-USB-OCD-H programmer. Read, Erase and Program functions are fully tested for 4-bytes addressing type 1 (4-bytes mode), type 2 (extended addr. register) and partially tested for type 3 (new 4-bytes instructions with 4-bytes address). My W25Q256FV has support for 4BA_Read (13h) only, but doesn't support 4BA_Program (12h) and 4BA_Erase instructions. So, direct 4BA program and erase should be tested after. Also I should make an excuse about testing of SFDP rev 1.6 parser. I've tested it as good as I can using the simulation code I described above but I'm not able to test it on real flash chips because I don't have a chip complied to JESD216B with SFDP 1.6 now. This should be tested later too. Patched files ------------- chipdrivers.h - added functions declarations for spi4ba.c cli_output.c - print() patched to skip strings which are starting from '\b' to prevent writing progress percents to logfile flash.h - feature definitions added - added set of 4-bytes address functions to flashchip structure definition - added type field to block_eraser structure - added some definitions for progress visialization flashchips.c - added definition for Winbond W25Q256BV/W25Q256FV chips flashrom.c - added switch to 4-bytes addressing more for chips which support it - added progress visualization for erase/write (essensial for 32MB+ chips) - changed in address print %06x to %08x to support 32MB+ chips - added line to the flashrom's banner about this patch (temporary) Makefile - added spi4ba.c serprog.c - added 4-bytes addressing spi_nbyte_read call to serprog_spi_read spi.c - fixed flash chip size check in spi_chip_read spi25.c - added 4-bytes addressing spi_nbyte_read call to spi_read_chunked - added 4-bytes addressing spi_nbyte_program call to spi_write_chunked - added 4-bytes addressing spi_byte_program call to spi_chip_write_1 - added progress visualization for read operation (essensial for 32MB+ chips) sfdp.c - added compliance to JEDEC JESD216B standard (SFDP revision 1.6) - added parse of SFDP 4-Bytes Addressing features (probe_spi_sfdp,sfdp_fill_flash) - added parse of SFDP 4-Bytes Addressing Instruction Table (sfdp_parse_4ba_table) - added choosing of block_erasers for 4-bytes addressing (sfdp_*_uniform_eraser*) - added exact flash page_size recognision from 11th dword in SFDP rev 1.6 - added fix for Micron chips to read 16th dword stating from SFDP revision 1.5 - added simulation of JESD216B for any flash chips (just for testing) Added files ----------- spi4ba.h - definitions for 4-bytes addressing JEDEC commands - definitions for 16th dword bits of SFDP Basic Flash Param Table (JESD216B) - definitions for SFDP 4-Bytes Addressing Instruction Table (JESD216B) - functions declarations from spi4ba.c (same as in chipdrivers.h, just to see) spi4ba.c - functions for enter 4-bytes addressing mode - functions for write Extended Address Register - functions for read/write/erase in 4-bytes addressing mode - functions for read/write/erase with Extended Address Register - functions for read/write/erase directly with 4-bytes address (from any mode) - functions to choose block_eraser by opcode for 4-bytes addressing for sfdp.c - functions to select proper block_eraser (ext.reg or 4-bytes addr) for sfdp.c Signed-off-by: Boris Baykov <dev(a)borisbaykov.com>, Russia, Jan 2014 --- Index: Makefile =================================================================== --- Makefile (revision 1861) +++ Makefile (working copy) @@ -355,11 +355,11 @@ ############################################################################### # Flash chip drivers and bus support infrastructure. CHIP_OBJS = jedec.o stm50.o w39.o w29ee011.o \ sst28sf040.o 82802ab.o \ - sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o spi25_statusreg.o \ + sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o spi25_statusreg.o spi4ba.o \ opaque.o sfdp.o en29lv640b.o at45db.o ############################################################################### # Library code. Index: chipdrivers.h =================================================================== --- chipdrivers.h (revision 1861) +++ chipdrivers.h (working copy) @@ -192,6 +192,33 @@ /* en29lv640b.c */ int probe_en29lv640b(struct flashctx *flash); int write_en29lv640b(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); +/* spi4ba.c */ +int spi_enter_4ba_b7(struct flashctx *flash); +int spi_enter_4ba_b7_we(struct flashctx *flash); +int spi_byte_program_4ba(struct flashctx *flash, unsigned int addr, uint8_t databyte); +int spi_nbyte_program_4ba(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len); +int spi_nbyte_read_4ba(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); +int spi_byte_program_4ba_direct(struct flashctx *flash, unsigned int addr, uint8_t databyte); +int spi_nbyte_program_4ba_direct(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len); +int spi_nbyte_read_4ba_direct(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); +int spi_byte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, uint8_t databyte); +int spi_nbyte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len); +int spi_nbyte_read_4ba_ereg(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); +erasefunc_t *spi_get_erasefn_from_opcode_4ba(uint8_t opcode); +erasefunc_t *spi_get_erasefn_from_opcode_4ba_direct(uint8_t opcode); +int spi_block_erase_20_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_20_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_20_4ba_selector(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_52_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_52_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_52_4ba_selector(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_d8_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_d8_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_d8_4ba_selector(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_21_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_5c_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_dc_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + #endif /* !__CHIPDRIVERS_H__ */ Index: cli_output.c =================================================================== --- cli_output.c (revision 1861) +++ cli_output.c (working copy) @@ -88,11 +88,12 @@ * time-critical operations. Don't slow them down by flushing. */ if (level != MSG_SPEW) fflush(output_type); } #ifndef STANDALONE - if ((level <= verbose_logfile) && logfile) { + /* skip of msgs starting from '\b' added to skip progress percents */ + if ((level <= verbose_logfile) && logfile && (!fmt || fmt[0] != '\b')) { va_start(ap, fmt); ret = vfprintf(logfile, fmt, ap); va_end(ap); if (level != MSG_SPEW) fflush(logfile); Index: flash.h =================================================================== --- flash.h (revision 1861) +++ flash.h (working copy) @@ -119,10 +119,18 @@ #define FEATURE_WRSR_EWSR (1 << 6) #define FEATURE_WRSR_WREN (1 << 7) #define FEATURE_WRSR_EITHER (FEATURE_WRSR_EWSR | FEATURE_WRSR_WREN) #define FEATURE_OTP (1 << 8) #define FEATURE_QPI (1 << 9) +/* Feature bits used for 4-bytes addressing mode */ +#define FEATURE_FOUR_BYTE_ADDR (1 << 10) +#define FEATURE_FOUR_BYTE_ADDR_ONLY (1 << 11) +#define FEATURE_NEED_ENTER_4BA_FOR_READ (1 << 12) +#define FEATURE_NEED_ENTER_4BA_FOR_WRITE (1 << 13) +#define FEATURE_NEED_ENTER_4BA_FOR_ERASE (1 << 14) +#define FEATURE_NEED_USE_EXTENDED_ADDR_REG (1 << 15) +#define FEATURE_ENTER_4BA_ALL (FEATURE_NEED_ENTER_4BA_FOR_READ | FEATURE_NEED_ENTER_4BA_FOR_WRITE | FEATURE_NEED_ENTER_4BA_FOR_ERASE | FEATURE_NEED_USE_EXTENDED_ADDR_REG) enum test_state { OK = 0, NT = 1, /* Not tested */ BAD, /* Known to not work */ @@ -163,10 +171,18 @@ unsigned int total_size; /* Chip page size in bytes */ unsigned int page_size; int feature_bits; + /* set of function pointers to use in 4-bytes addressing mode */ + struct four_bytes_addr_funcs_set { + int (*enter_4ba) (struct flashctx *flash); + int (*read_nbyte) (struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); + int (*program_byte) (struct flashctx *flash, unsigned int addr, const uint8_t databyte); + int (*program_nbyte) (struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len); + } four_bytes_addr_funcs; + /* Indicate how well flashrom supports different operations of this flash chip. */ struct tested { enum test_state probe; enum test_state read; enum test_state erase; @@ -186,10 +202,11 @@ * The first one that fits will be chosen. There is currently no way to * influence that behaviour. For testing just comment out the other * elements or set the function pointer to NULL. */ struct block_eraser { + int type; /* eraser type 1,2,3 or 4 */ struct eraseblock { unsigned int size; /* Eraseblock size in bytes */ unsigned int count; /* Number of contiguous blocks with that size */ } eraseblocks[NUM_ERASEREGIONS]; /* a block_erase function should try to erase one block of size @@ -337,10 +354,15 @@ #define msg_cdbg2(...) print(MSG_DEBUG2, __VA_ARGS__) /* chip debug2 */ #define msg_gspew(...) print(MSG_SPEW, __VA_ARGS__) /* general debug spew */ #define msg_pspew(...) print(MSG_SPEW, __VA_ARGS__) /* programmer debug spew */ #define msg_cspew(...) print(MSG_SPEW, __VA_ARGS__) /* chip debug spew */ +/* Read progress will be shown for reads more than 256KB */ +#define MIN_LENGTH_TO_SHOW_READ_PROGRESS 256 * 1024 +/* Read progress will be shown for erases and writes more than 64KB */ +#define MIN_LENGTH_TO_SHOW_ERASE_AND_WRITE_PROGRESS 64 * 1024 + /* layout.c */ int register_include_arg(char *name); int process_include_args(void); int read_romlayout(const char *name); int normalize_romentries(const struct flashctx *flash); Index: flashchips.c =================================================================== --- flashchips.c (revision 1861) +++ flashchips.c (working copy) @@ -13282,10 +13282,59 @@ .voltage = {2700, 3600}, }, { .vendor = "Winbond", + .name = "W25Q256.V", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q256_V, + .total_size = 32768, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_FOUR_BYTE_ADDR | + FEATURE_NEED_ENTER_4BA_FOR_ERASE | FEATURE_NEED_ENTER_4BA_FOR_WRITE, + .four_bytes_addr_funcs = + { + .enter_4ba = spi_enter_4ba_b7_we, /* enter 4-bytes addressing mode by CMD B7 + WREN */ + .read_nbyte = spi_nbyte_read_4ba_direct, /* read directly from any mode, no need to enter 4ba */ + .program_byte = spi_byte_program_4ba, /* write from 4-bytes addressing mode */ + .program_nbyte = spi_nbyte_program_4ba /* write from 4-bytes addressing mode */ + }, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20_4ba, /* erases 4k from 4-bytes addressing mode */ + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_52_4ba, /* erases 32k from 4-bytes addressing mode */ + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8_4ba, /* erases 64k from 4-bytes addressing mode */ + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Winbond", .name = "W25Q20.W", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, .model_id = WINBOND_NEX_W25Q20_W, .total_size = 256, Index: flashrom.c =================================================================== --- flashrom.c (revision 1861) +++ flashrom.c (working copy) @@ -1366,12 +1366,12 @@ "non-empty erase function. Not an error.\n"); if (!done) continue; if (done != chip->total_size * 1024) { msg_gerr("ERROR: Flash chip %s erase function %i " - "region walking resulted in 0x%06x bytes total," - " expected 0x%06x bytes. Please report a bug at" + "region walking resulted in 0x%08x bytes total," + " expected 0x%08x bytes. Please report a bug at" " flashrom(a)flashrom.org\n", chip->name, k, done, chip->total_size * 1024); ret = 1; } if (!eraser.block_erase) @@ -1460,29 +1460,52 @@ { int i, j; unsigned int start = 0; unsigned int len; struct block_eraser eraser = flash->chip->block_erasers[erasefunction]; + int show_progress = 0; + unsigned int percent_last, percent_current; + unsigned long size = flash->chip->total_size * 1024; + + /* progress visualizaion init */ + if(size >= MIN_LENGTH_TO_SHOW_ERASE_AND_WRITE_PROGRESS) { + msg_cinfo(" "); /* only this space will go to logfile but all strings with \b wont. */ + msg_cinfo("\b 0%%"); + percent_last = percent_current = 0; + show_progress = 1; /* enable progress visualizaion */ + } for (i = 0; i < NUM_ERASEREGIONS; i++) { /* count==0 for all automatically initialized array * members so the loop below won't be executed for them. */ len = eraser.eraseblocks[i].size; for (j = 0; j < eraser.eraseblocks[i].count; j++) { /* Print this for every block except the first one. */ if (i || j) msg_cdbg(", "); - msg_cdbg("0x%06x-0x%06x", start, + msg_cdbg("0x%08x-0x%08x", start, start + len - 1); if (do_something(flash, start, len, param1, param2, eraser.block_erase)) { return 1; } start += len; + + if(show_progress) { + percent_current = (unsigned int) ((unsigned long long)start * 100 / size); + if(percent_current != percent_last) { + msg_cinfo("\b\b\b%2d%%", percent_current); + percent_last = percent_current; + } + } } } + + if(show_progress) + msg_cinfo("\b\b\b\b"); /* remove progress percents from the screen */ + msg_cdbg("\n"); return 0; } static int check_block_eraser(const struct flashctx *flash, int k, int log) @@ -1735,12 +1758,15 @@ } void print_version(void) { msg_ginfo("flashrom v%s", flashrom_version); + msg_ginfo("-4ba"); /* temporary to indicate that version is patched */ print_sysinfo(); msg_ginfo("\n"); + /* temporary to indicate that version is patched */ + msg_ginfo("with patch for support SPI flash chips with 4-bytes addressing\n"); } void print_banner(void) { msg_ginfo("flashrom is free software, get the source code at " @@ -1934,10 +1960,42 @@ * erase and write. */ if (flash->chip->unlock) flash->chip->unlock(flash); + if(flash->chip->feature_bits & FEATURE_FOUR_BYTE_ADDR) { + /* Switching to 4-Bytes Addressing mode if flash chip supports it + and selected operation requires 4-Bytes Addressing mode + (no need for direct and ext.addr.reg operation) */ + if(((read_it || verify_it) && (flash->chip->feature_bits & FEATURE_NEED_ENTER_4BA_FOR_READ)) || + ((erase_it || write_it) && (flash->chip->feature_bits & (FEATURE_NEED_ENTER_4BA_FOR_READ | + FEATURE_NEED_ENTER_4BA_FOR_WRITE | FEATURE_NEED_ENTER_4BA_FOR_ERASE))) ) { + + if (!flash->chip->four_bytes_addr_funcs.enter_4ba) { + msg_cerr("No function for Enter 4-bytes addressing mode for this flash chip.\n" + "Please report to flashrom(a)flashrom.org\n"); + return 1; + } + + if(flash->chip->four_bytes_addr_funcs.enter_4ba(flash)) { + msg_cerr("Switching to 4-bytes addressing mode failed!\n"); + return 1; + } + + msg_cdbg("Switched to 4-bytes addressing mode.\n"); + } + /* Do not switch to 4-Bytes Addressing mode if using Extended Address Register */ + else if(flash->chip->feature_bits & FEATURE_NEED_USE_EXTENDED_ADDR_REG) { + msg_cdbg("Using 4-bytes addressing with extended address register.\n"); + } + /* Do not switch to 4-Bytes Addressing mode if all instructions are direct-4BA + or if the flash chip is 4-Bytes Addressing Only and always in 4BA-mode */ + else { + msg_cdbg2("No need to switch to 4-bytes addressing mode.\n"); + } + } + if (read_it) { return read_flash_to_file(flash, filename); } oldcontents = malloc(size); Index: serprog.c =================================================================== --- serprog.c (revision 1861) +++ serprog.c (working copy) @@ -933,11 +933,14 @@ unsigned int i, cur_len; const unsigned int max_read = spi_master_serprog.max_data_read; for (i = 0; i < len; i += cur_len) { int ret; cur_len = min(max_read, (len - i)); - ret = spi_nbyte_read(flash, start + i, buf + i, cur_len); + ret = (flash->chip->feature_bits & FEATURE_FOUR_BYTE_ADDR) == 0 + ? spi_nbyte_read(flash, start + i, buf + i, cur_len) + : flash->chip->four_bytes_addr_funcs.read_nbyte(flash, + start + i, buf + i, cur_len); if (ret) return ret; } return 0; } Index: sfdp.c =================================================================== --- sfdp.c (revision 1861) +++ sfdp.c (working copy) @@ -1,9 +1,10 @@ /* * This file is part of the flashrom project. * * Copyright (C) 2011-2012 Stefan Tauner + * Copyright (C) 2014 Boris Baykov * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * @@ -15,17 +16,32 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* + * History of changes: + * 05/01/2014 Added compliance to JESD216B standard and SFDP revision 1.6 + * 07/01/2014 Modified to support SFDP revision 1.5 (for Micron flash chips) + */ + #include <stdint.h> #include <stdlib.h> #include <string.h> #include "flash.h" #include "spi.h" +#include "spi4ba.h" #include "chipdrivers.h" +/* Default four bytes addressing behavior: + 1) 4-Bytes Addressing Mode (FBA_USE_EXT_ADDR_REG_BY_DEFAULT not defined) + 2) 3-bytes mode with Ext.Addr.Register (FBA_USE_EXT_ADDR_REG_BY_DEFAULT defined) */ +/* #define FBA_USE_EXT_ADDR_REG_BY_DEFAULT 1 */ + +/* For testing purposes only. Tests JESD216B SFDP compliance without proper flash chip */ +/* #define JESD216B_SIMULATION 1 */ + static int spi_sfdp_read_sfdp_chunk(struct flashctx *flash, uint32_t address, uint8_t *buf, int len) { int i, ret; uint8_t *newbuf; const unsigned char cmd[JEDEC_SFDP_OUTSIZE] = { @@ -72,22 +88,25 @@ } return ret; } struct sfdp_tbl_hdr { - uint8_t id; + uint16_t id; uint8_t v_minor; uint8_t v_major; uint8_t len; uint32_t ptp; /* 24b pointer */ }; -static int sfdp_add_uniform_eraser(struct flashchip *chip, uint8_t opcode, uint32_t block_size) +static int sfdp_add_uniform_eraser(struct flashchip *chip, int eraser_type, uint8_t opcode, uint32_t block_size) { int i; uint32_t total_size = chip->total_size * 1024; - erasefunc_t *erasefn = spi_get_erasefn_from_opcode(opcode); + + /* choosing different eraser functions for 3-bytes and 4-bytes addressing */ + erasefunc_t *erasefn = (chip->feature_bits & FEATURE_FOUR_BYTE_ADDR) ? + spi_get_erasefn_from_opcode_4ba(opcode) : spi_get_erasefn_from_opcode(opcode); if (erasefn == NULL || total_size == 0 || block_size == 0 || total_size % block_size != 0) { msg_cdbg("%s: invalid input, please report to " "flashrom(a)flashrom.org\n", __func__); @@ -109,10 +128,11 @@ msg_cspew(" Block Eraser %d is already occupied.\n", i); continue; } + eraser->type = eraser_type; eraser->block_erase = erasefn; eraser->eraseblocks[0].size = block_size; eraser->eraseblocks[0].count = total_size/block_size; msg_cdbg2(" Block eraser %d: %d x %d B with opcode " "0x%02x\n", i, total_size/block_size, block_size, @@ -123,44 +143,110 @@ " Please report this at flashrom(a)flashrom.org\n", __func__, i); return 1; } -static int sfdp_fill_flash(struct flashchip *chip, uint8_t *buf, uint16_t len) +/* Try of replace exist erasers to new direct 4-bytes addressing erasers + which can be called from ANY addressing mode: 3-byte or 4-bytes. + These erasers opcodes defines in SFDP 4-byte address instruction table + from SFDP revision 1.6 that is defined by JESD216B standard. */ +static int sfdp_change_uniform_eraser_4ba_direct(struct flashchip *chip, int eraser_type, uint8_t opcode) +{ + int i; + erasefunc_t *erasefn = spi_get_erasefn_from_opcode_4ba_direct(opcode); + + if (erasefn == NULL) { + msg_cdbg("%s: invalid input, please report to " + "flashrom(a)flashrom.org\n", __func__); + return 1; + } + + for (i = 0; i < NUM_ERASEFUNCTIONS; i++) { + struct block_eraser *eraser = &chip->block_erasers[i]; + if (eraser->eraseblocks[0].size == 0) + break; + if (eraser->type != eraser_type) + continue; + + eraser->block_erase = erasefn; + msg_cdbg2(" Block eraser %d (type %d) changed to opcode " + "0x%02x\n", i, eraser_type, opcode); + return 0; + } + + msg_cspew("%s: Block Eraser type %d isn't found." + " Please report this at flashrom(a)flashrom.org\n", + __func__, eraser_type); + return 1; +} + +/* Parse of JEDEC SFDP Basic Flash Parameter Table */ +static int sfdp_fill_flash(struct flashchip *chip, uint8_t *buf, uint16_t len, int sfdp_rev_15) { uint8_t opcode_4k_erase = 0xFF; uint32_t tmp32; uint8_t tmp8; uint32_t total_size; /* in bytes */ uint32_t block_size; int j; msg_cdbg("Parsing JEDEC flash parameter table... "); - if (len != 9 * 4 && len != 4 * 4) { + if (len != 16 * 4 && len != 9 * 4 && len != 4 * 4) { msg_cdbg("%s: len out of spec\n", __func__); return 1; } msg_cdbg2("\n"); - + /* 1. double word */ tmp32 = ((unsigned int)buf[(4 * 0) + 0]); tmp32 |= ((unsigned int)buf[(4 * 0) + 1]) << 8; tmp32 |= ((unsigned int)buf[(4 * 0) + 2]) << 16; tmp32 |= ((unsigned int)buf[(4 * 0) + 3]) << 24; + chip->feature_bits = 0; + tmp8 = (tmp32 >> 17) & 0x3; switch (tmp8) { case 0x0: msg_cdbg2(" 3-Byte only addressing.\n"); break; case 0x1: msg_cdbg2(" 3-Byte (and optionally 4-Byte) addressing.\n"); +#ifndef FBA_USE_EXT_ADDR_REG_BY_DEFAULT + /* assuming that 4-bytes addressing mode can be entered + by CMD B7h preceded with WREN and all read, write and + erase commands will be able to receive 4-bytes address */ + chip->feature_bits |= ( FEATURE_FOUR_BYTE_ADDR | + FEATURE_NEED_ENTER_4BA_FOR_READ | + FEATURE_NEED_ENTER_4BA_FOR_WRITE | + FEATURE_NEED_ENTER_4BA_FOR_ERASE ); + chip->four_bytes_addr_funcs.enter_4ba = spi_enter_4ba_b7_we; + chip->four_bytes_addr_funcs.program_byte = spi_byte_program_4ba; + chip->four_bytes_addr_funcs.program_nbyte = spi_nbyte_program_4ba; + chip->four_bytes_addr_funcs.read_nbyte = spi_nbyte_read_4ba; +#else /* if FBA_USE_EXT_ADDR_REG_BY_DEFAULT defined */ + /* assuming that 4-bytes addressing is working using + extended address register which can be assigned + throught CMD C5h and then all commands will use + 3-bytes address as usual */ + chip->feature_bits |= ( FEATURE_FOUR_BYTE_ADDR | + FEATURE_NEED_USE_EXTENDED_ADDR_REG ); + chip->four_bytes_addr_funcs.enter_4ba = NULL; + chip->four_bytes_addr_funcs.program_byte = spi_byte_program_4ba_ereg; + chip->four_bytes_addr_funcs.program_nbyte = spi_nbyte_program_4ba_ereg; + chip->four_bytes_addr_funcs.read_nbyte = spi_nbyte_read_4ba_ereg; +#endif /* FBA_USE_EXT_ADDR_REG_BY_DEFAULT */ break; case 0x2: - msg_cdbg(" 4-Byte only addressing (not supported by " - "flashrom).\n"); - return 1; + msg_cdbg2(" 4-Byte only addressing.\n"); + chip->feature_bits |= ( FEATURE_FOUR_BYTE_ADDR | + FEATURE_FOUR_BYTE_ADDR_ONLY ); + chip->four_bytes_addr_funcs.enter_4ba = NULL; + chip->four_bytes_addr_funcs.program_byte = spi_byte_program_4ba; + chip->four_bytes_addr_funcs.program_nbyte = spi_nbyte_program_4ba; + chip->four_bytes_addr_funcs.read_nbyte = spi_nbyte_read_4ba; + break; default: msg_cdbg(" Required addressing mode (0x%x) not supported.\n", tmp8); return 1; } @@ -168,21 +254,21 @@ msg_cdbg2(" Status register is "); if (tmp32 & (1 << 3)) { msg_cdbg2("volatile and writes to the status register have to " "be enabled with "); if (tmp32 & (1 << 4)) { - chip->feature_bits = FEATURE_WRSR_WREN; + chip->feature_bits |= FEATURE_WRSR_WREN; msg_cdbg2("WREN (0x06).\n"); } else { - chip->feature_bits = FEATURE_WRSR_EWSR; + chip->feature_bits |= FEATURE_WRSR_EWSR; msg_cdbg2("EWSR (0x50).\n"); } } else { msg_cdbg2("non-volatile and the standard does not allow " "vendors to tell us whether EWSR/WREN is needed for " "status register writes - assuming EWSR.\n"); - chip->feature_bits = FEATURE_WRSR_EWSR; + chip->feature_bits |= FEATURE_WRSR_EWSR; } msg_cdbg2(" Write chunk size is "); if (tmp32 & (1 << 2)) { msg_cdbg2("at least 64 B.\n"); @@ -212,56 +298,306 @@ return 1; } total_size = ((tmp32 & 0x7FFFFFFF) + 1) / 8; chip->total_size = total_size / 1024; msg_cdbg2(" Flash chip size is %d kB.\n", chip->total_size); + if (total_size > (1 << 24)) { - msg_cdbg("Flash chip size is bigger than what 3-Byte addressing " - "can access.\n"); - return 1; + if(!sfdp_rev_15) { + msg_cdbg("Flash chip size is bigger than what 3-Byte addressing " + "can access but chip's SFDP revision is lower than 1.6 " + "(1.5).\nConsequently 4-bytes addressing can NOT be " + "properly configured using current SFDP information.\n"); +#ifndef FBA_USE_EXT_ADDR_REG_BY_DEFAULT + msg_cdbg("Assuming that 4-bytes addressing mode can be " + "entered by CMD B7h with WREN.\n"); +#else + msg_cdbg("Assuming that 4-bytes addressing is working via " + "an Extended Address Register which can be written " + "by CMD C5h.\n"); +#endif + } } - if (opcode_4k_erase != 0xFF) - sfdp_add_uniform_eraser(chip, opcode_4k_erase, 4 * 1024); - /* FIXME: double words 3-7 contain unused fast read information */ - if (len == 4 * 4) { + if (len < 9 * 4) { msg_cdbg(" It seems like this chip supports the preliminary " "Intel version of SFDP, skipping processing of double " "words 3-9.\n"); + + /* in the case if BFPT erasers array is not present + trying to add default 4k-eraser */ + if (opcode_4k_erase != 0xFF) + sfdp_add_uniform_eraser(chip, 0, opcode_4k_erase, 4 * 1024); + goto done; } - /* 8. double word */ + /* 8. double word & 9. double word */ + /* for by block eraser types, from Type 1 to Type 4 */ for (j = 0; j < 4; j++) { /* 7 double words from the start + 2 bytes for every eraser */ tmp8 = buf[(4 * 7) + (j * 2)]; - msg_cspew(" Erase Sector Type %d Size: 0x%02x\n", j + 1, - tmp8); + msg_cspew(" Erase Sector (Type %d) Size: 0x%02x\n", j + 1, tmp8); if (tmp8 == 0) { - msg_cspew(" Erase Sector Type %d is unused.\n", j); + msg_cspew(" Erase Sector (Type %d) is unused.\n", j + 1); continue; } if (tmp8 >= 31) { - msg_cdbg2(" Block size of erase Sector Type %d (2^%d) " - "is too big for flashrom.\n", j, tmp8); + msg_cdbg2(" Block size of erase Sector (Type %d): 2^%d " + "is too big for flashrom.\n", j + 1, tmp8); continue; } block_size = 1 << (tmp8); /* block_size = 2 ^ field */ tmp8 = buf[(4 * 7) + (j * 2) + 1]; - msg_cspew(" Erase Sector Type %d Opcode: 0x%02x\n", j + 1, - tmp8); - sfdp_add_uniform_eraser(chip, tmp8, block_size); + msg_cspew(" Erase Sector (Type %d) Opcode: 0x%02x\n", j + 1, tmp8); + sfdp_add_uniform_eraser(chip, j + 1, tmp8, block_size); + } + + /* Trying to adding the default 4k eraser after parsing erasers info. + In most cases this eraser has already been added before. */ + if (opcode_4k_erase != 0xFF) + sfdp_add_uniform_eraser(chip, 0, opcode_4k_erase, 4 * 1024); + + /* If the chip doesn't support 4-bytes addressing mode we don't have + to read and analyze 16th DWORD of Basic Flash Parameter Table */ + if (!(chip->feature_bits & FEATURE_FOUR_BYTE_ADDR)) + goto done; + + /* In the case if the chip is working in 4-bytes addressing mode ONLY we + don't have to read and analyze 16th DWORD of Basic Flash Parameter Table + because we don't have to know how to switch to 4-bytes mode and back + when we are already in 4-bytes mode permanently. */ + if (chip->feature_bits & FEATURE_FOUR_BYTE_ADDR_ONLY) + goto done; + + /* If the SFDP revision supported by the chip is lower that 1.6 (1.5) + we can not read and analyze 16th DWORD of Basic Flash Parameter Table. + Using defaults by FBA_USE_EXT_ADDR_REG_BY_DEFAULT define. */ + if(!sfdp_rev_15) + goto done; + + if (len < 16 * 4) { + msg_cdbg("%s: len of BFPT is out of spec\n", __func__); + msg_cerr("ERROR: Unable read 4-bytes addressing parameters.\n"); + return 1; + } + + /* 11. double word */ + tmp8 = buf[(4*10) + 0] >> 4; /* get upper nibble of LSB of 11th dword */ + chip->page_size = 1 << tmp8; /* page_size = 2 ^ N */ + msg_cdbg2(" Page size is %d B.\n", chip->page_size); + + /* 16. double word */ + tmp32 = ((unsigned int)buf[(4 * 15) + 0]); + tmp32 |= ((unsigned int)buf[(4 * 15) + 1]) << 8; + tmp32 |= ((unsigned int)buf[(4 * 15) + 2]) << 16; + tmp32 |= ((unsigned int)buf[(4 * 15) + 3]) << 24; + + /* Parsing 16th DWORD of Basic Flash Parameter Table according to JESD216B */ + + if(tmp32 & JEDEC_BFPT_DW16_ENTER_B7) { + msg_cdbg2(" Enter 4-bytes addressing mode by CMD B7h\n"); + chip->four_bytes_addr_funcs.enter_4ba = spi_enter_4ba_b7; + chip->four_bytes_addr_funcs.program_byte = spi_byte_program_4ba; + chip->four_bytes_addr_funcs.program_nbyte = spi_nbyte_program_4ba; + chip->four_bytes_addr_funcs.read_nbyte = spi_nbyte_read_4ba; + chip->feature_bits &= ~FEATURE_ENTER_4BA_ALL; // clear defaults + chip->feature_bits |= ( FEATURE_NEED_ENTER_4BA_FOR_READ | + FEATURE_NEED_ENTER_4BA_FOR_WRITE | + FEATURE_NEED_ENTER_4BA_FOR_ERASE ); + } + else if(tmp32 & JEDEC_BFPT_DW16_ENTER_B7_WE) { + msg_cdbg2(" Enter 4-bytes addressing mode by CMD B7h with WREN\n"); + chip->four_bytes_addr_funcs.enter_4ba = spi_enter_4ba_b7_we; + chip->four_bytes_addr_funcs.program_byte = spi_byte_program_4ba; + chip->four_bytes_addr_funcs.program_nbyte = spi_nbyte_program_4ba; + chip->four_bytes_addr_funcs.read_nbyte = spi_nbyte_read_4ba; + chip->feature_bits &= ~FEATURE_ENTER_4BA_ALL; // clear defaults + chip->feature_bits |= ( FEATURE_NEED_ENTER_4BA_FOR_READ | + FEATURE_NEED_ENTER_4BA_FOR_WRITE | + FEATURE_NEED_ENTER_4BA_FOR_ERASE ); + } + else if(tmp32 & JEDEC_BFPT_DW16_ENTER_EXTENDED_ADDR_REG) { + msg_cdbg2(" Extended Address Register used for 4-bytes addressing\n"); + chip->four_bytes_addr_funcs.program_byte = spi_byte_program_4ba_ereg; + chip->four_bytes_addr_funcs.program_nbyte = spi_nbyte_program_4ba_ereg; + chip->four_bytes_addr_funcs.read_nbyte = spi_nbyte_read_4ba_ereg; + chip->feature_bits &= ~FEATURE_ENTER_4BA_ALL; // clear defaults + /* this flag signals to all '*_selector' functions + to use Ext.Addr.Reg while erase operations */ + chip->feature_bits |= FEATURE_NEED_USE_EXTENDED_ADDR_REG; + } + else { + msg_cerr("ERROR: Unable to use 4-bytes addressing for this chip.\n" + " Please report this at flashrom(a)flashrom.org\n\n"); + return 1; } done: msg_cdbg("done.\n"); return 0; } +/* Parse of JEDEC SFDP 4-byte address instruction table. From SFDP revision 1.6 only. + This parsing shoukd be called after basic flash parameter table is parsed. */ +static int sfdp_parse_4ba_table(struct flashchip *chip, uint8_t *buf, uint16_t len) +{ + uint32_t tmp32; + uint8_t tmp8; + int j, direct_erasers; + int direct_count; + + msg_cdbg("Parsing JEDEC 4-byte address instuction table... "); + if (len != 2 * 4) { + msg_cdbg("%s: len out of spec\n", __func__); + return 1; + } + msg_cdbg2("\n"); + + /* 1. double word */ + tmp32 = ((unsigned int)buf[(4 * 0) + 0]); + tmp32 |= ((unsigned int)buf[(4 * 0) + 1]) << 8; + tmp32 |= ((unsigned int)buf[(4 * 0) + 2]) << 16; + tmp32 |= ((unsigned int)buf[(4 * 0) + 3]) << 24; + + direct_count = 0; + + if(tmp32 & JEDEC_4BAIT_READ_SUPPORT) { + msg_cdbg2(" Found Read CMD 13h with 4-bytes address\n"); + chip->four_bytes_addr_funcs.read_nbyte = spi_nbyte_read_4ba_direct; + /* read function has changed to direct 4-bytes function, + so entering 4-bytes mode isn't required for reading bytes */ + chip->feature_bits &= ~FEATURE_NEED_ENTER_4BA_FOR_READ; + direct_count++; + } + + if(tmp32 & JEDEC_4BAIT_PROGRAM_SUPPORT) { + msg_cdbg2(" Found Write CMD 12h with 4-bytes address\n"); + chip->four_bytes_addr_funcs.program_byte = spi_byte_program_4ba_direct; + chip->four_bytes_addr_funcs.program_nbyte = spi_nbyte_program_4ba_direct; + /* write (program) functions have changed to direct 4-bytes functions, + so entering 4-bytes mode isn't required for writing bytes */ + chip->feature_bits &= ~FEATURE_NEED_ENTER_4BA_FOR_WRITE; + direct_count++; + } + + direct_erasers = 0; + + /* 2. double word */ + for (j = 0; j < 4; j++) { + if(!(tmp32 & (JEDEC_4BAIT_ERASE_TYPE_1_SUPPORT << j))) + continue; + + tmp8 = buf[(4 * 1) + j]; + + msg_cdbg2(" Found Erase (type %d) CMD %02Xh with 4-bytes address\n", j + 1, tmp8); + + if(tmp8 == 0xFF) { + msg_cdbg("%s: Eraser (type %d) is supported, but opcode = 0xFF\n" + " Please report to flashrom(a)flashrom.org\n\n", __func__, j + 1); + continue; + } + + /* try of replacing the eraser with direct 4-bytes eraser */ + if(!sfdp_change_uniform_eraser_4ba_direct(chip, j + 1, tmp8)) + direct_erasers++; + } + + for (j = 0; j < NUM_ERASEFUNCTIONS; j++) { + if (chip->block_erasers[j].eraseblocks[0].size == 0) + break; + } + + if( j == direct_erasers ) { + /* if all erasers have been changed to direct 4-bytes ones, + then we don't have to enter 4-bytes mode for erase */ + chip->feature_bits &= ~FEATURE_NEED_ENTER_4BA_FOR_ERASE; + direct_count++; + msg_cspew("All erasers have changed to direct ones.\n"); + } + + if( direct_count == 3 ) { + /* if all read/write/erase functions are direct 4-bytes now, + then we don't have to use extended address register */ + chip->feature_bits &= ~FEATURE_NEED_USE_EXTENDED_ADDR_REG; + msg_cspew("All read/write/erase functions have changed to direct ones.\n"); + } + + msg_cdbg("done.\n"); + return 0; +} + +#ifdef JESD216B_SIMULATION +/* This simulation increases size of Basic Flash Parameter Table + to have 16 dwords size and fills 16th dword with fake information + that is required to test JESD216B compliance. */ +int sfdp_jesd216b_simulation_dw16(uint8_t** ptbuf, uint16_t* plen) +{ + uint8_t* tbufsim; + uint16_t lensim = 16 * 4; + + tbufsim = malloc(lensim); + if (tbufsim == NULL) { + msg_gerr("Out of memory!\n"); + return 1; + } + + msg_cdbg("\n=== SIMULATION of JESD216B 16th Dword of Basic Flash Parameter Table\n"); + + memset(tbufsim, 0, 16 * 4); + memcpy(tbufsim, *ptbuf, min(*plen, 15 * 4)); + + tbufsim[(4*10) + 0] = 8 << 4; /* page size = 256 */ + + *((uint32_t*)&tbufsim[15 * 4]) = /*JEDEC_BFPT_DW16_ENTER_B7 | */ + JEDEC_BFPT_DW16_ENTER_B7_WE | + JEDEC_BFPT_DW16_ENTER_EXTENDED_ADDR_REG /* | + JEDEC_BFPT_DW16_ENTER_BANK_ADDR_REG_EN_BIT | + JEDEC_BFPT_DW16_ENTER_NV_CONFIG_REG | + JEDEC_BFPT_DW16_VENDOR_SET | + JEDEC_BFPT_DW16_4_BYTES_ADDRESS_ONLY */ ; + + free(*ptbuf); + *ptbuf = tbufsim; + *plen = lensim; + return 0; +} + +/* This simulation created fake 4-bytes Address Instruction Table + with features information to test JESD216B compliance. */ +int sfdp_jesd216b_simulation_4bait(uint8_t** ptbuf, uint16_t* plen) +{ + uint8_t* tbufsim; + uint16_t lensim = 2 * 4; + + tbufsim = malloc(lensim); + if (tbufsim == NULL) { + msg_gerr("Out of memory!\n"); + return 1; + } + + msg_cdbg("\n=== SIMULATION of JESD216B 4-bytes Address Instruction Table\n"); + + *((uint32_t*)&tbufsim[0]) = JEDEC_4BAIT_READ_SUPPORT /*| + JEDEC_4BAIT_PROGRAM_SUPPORT | + JEDEC_4BAIT_ERASE_TYPE_1_SUPPORT | + JEDEC_4BAIT_ERASE_TYPE_2_SUPPORT | + JEDEC_4BAIT_ERASE_TYPE_3_SUPPORT | + JEDEC_4BAIT_ERASE_TYPE_4_SUPPORT */; + *((uint32_t*)&tbufsim[4]) = 0xFFFFFFFF; + /* *((uint32_t*)&tbufsim[4]) = 0xFFDC5C21; */ + + free(*ptbuf); + *ptbuf = tbufsim; + *plen = lensim; + return 0; +} +#endif + int probe_spi_sfdp(struct flashctx *flash) { int ret = 0; uint8_t buf[8]; uint32_t tmp32; @@ -269,10 +605,11 @@ /* need to limit the table loop by comparing i to uint8_t nph hence: */ uint16_t i; struct sfdp_tbl_hdr *hdrs; uint8_t *hbuf; uint8_t *tbuf; + int sfdp_rev_16 = 0, sfdp_rev_15 = 0; if (spi_sfdp_read_sfdp(flash, 0x00, buf, 4)) { msg_cdbg("Receiving SFDP signature failed.\n"); return 0; } @@ -296,10 +633,36 @@ if (buf[1] != 0x01) { msg_cdbg("The chip supports an unknown version of SFDP. " "Aborting SFDP probe!\n"); return 0; } + + /* JEDEC JESD216B defines SFDP revision 1.6 and includes: + 1) 16 dwords in Basic Flash Parameter Table + 2) 16th dword has information how to enter + and exit 4-bytes addressing mode + 3) 4-Bytes Address Instruction Table with ID 0xFF84 + + However we can see in the datasheet for Micron's + MT25Q 512Mb chip (MT25QL512AB/MT25QU512AB) that the + chip returnes SFDP revision 1.5 and has 16 dwords + in its Basic Flash Paramater Table. Also the information + about addressing mode switch is exist in the 16th dword. + But 4-Bytes Address Instruction Table is absent. + + So we will use 16th dword from SFDP revision 1.5 + but 4-Bytes Address Instruction Table from SFDP 1.6 only. + This assumption is made for better support of Micron + flash chips. + + FIXME: SFDP revisions compliance should be checked + more carefully after more information about JESD216B + SFDP tables will be known from real flash chips. + */ + sfdp_rev_16 = (buf[1] == 1 && buf[0] >= 6) || buf[1] > 1; + sfdp_rev_15 = (buf[1] == 1 && buf[0] >= 5) || buf[1] > 1; + nph = buf[2]; msg_cdbg2("SFDP number of parameter headers is %d (NPH = %d).\n", nph + 1, nph); /* Fetch all parameter headers, even if we don't use them all (yet). */ @@ -314,17 +677,18 @@ goto cleanup_hdrs; } for (i = 0; i <= nph; i++) { uint16_t len; - hdrs[i].id = hbuf[(8 * i) + 0]; + hdrs[i].id = hbuf[(8 * i) + 0]; /* ID LSB read */ hdrs[i].v_minor = hbuf[(8 * i) + 1]; hdrs[i].v_major = hbuf[(8 * i) + 2]; hdrs[i].len = hbuf[(8 * i) + 3]; hdrs[i].ptp = hbuf[(8 * i) + 4]; hdrs[i].ptp |= ((unsigned int)hbuf[(8 * i) + 5]) << 8; hdrs[i].ptp |= ((unsigned int)hbuf[(8 * i) + 6]) << 16; + hdrs[i].id |= ((uint16_t)hbuf[(8 * i) + 7]) << 8; /* ID MSB read */ msg_cdbg2("\nSFDP parameter table header %d/%d:\n", i, nph); msg_cdbg2(" ID 0x%02x, version %d.%d\n", hdrs[i].id, hdrs[i].v_major, hdrs[i].v_minor); len = hdrs[i].len * 4; tmp32 = hdrs[i].ptp; @@ -366,29 +730,51 @@ } } msg_cspew("\n"); if (i == 0) { /* Mandatory JEDEC SFDP parameter table */ - if (hdrs[i].id != 0) + if (hdrs[i].id != JEDEC_BFPT_ID) msg_cdbg("ID of the mandatory JEDEC SFDP " - "parameter table is not 0 as demanded " - "by JESD216 (warning only).\n"); - + "parameter table is not 0xFF00 as" + "demanded by JESD216 (warning only)." + "\n"); +#ifdef JESD216B_SIMULATION + if(!sfdp_jesd216b_simulation_dw16(&tbuf, &len)) + sfdp_rev_16 = sfdp_rev_15 = 1; /* pretend as SFDP rev 1.6 */ +#endif if (hdrs[i].v_major != 0x01) { msg_cdbg("The chip contains an unknown " "version of the JEDEC flash " "parameters table, skipping it.\n"); - } else if (len != 9 * 4 && len != 4 * 4) { + } else if (len != 16 * 4 && len != 9 * 4 && len != 4 * 4) { msg_cdbg("Length of the mandatory JEDEC SFDP " "parameter table is wrong (%d B), " "skipping it.\n", len); - } else if (sfdp_fill_flash(flash->chip, tbuf, len) == 0) + } else if (sfdp_fill_flash(flash->chip, tbuf, len, sfdp_rev_15) == 0) ret = 1; +#ifdef JESD216B_SIMULATION + if(ret == 1 && !sfdp_jesd216b_simulation_4bait(&tbuf, &len)) + sfdp_parse_4ba_table(flash->chip, tbuf, len); +#endif + } + /* JEDEC SFDP 4-byte address instruction table. From SFDP revision 1.6 only. + This parsing shoukd be called after basic flash parameter table is parsed. */ + else if(sfdp_rev_16 && hdrs[i].id == JEDEC_4BAIT_ID && ret == 1) { + if (hdrs[i].v_major != 0x01) { + msg_cdbg("The chip contains an unknown " + "version of the JEDEC 4-bytes " + "address instruction table, " + "skipping it.\n"); + } + else { /* no result check because this table is optional */ + sfdp_parse_4ba_table(flash->chip, tbuf, len); + } } free(tbuf); } cleanup_hdrs: free(hdrs); free(hbuf); return ret; } + Index: spi.c =================================================================== --- spi.c (revision 1861) +++ spi.c (working copy) @@ -108,11 +108,14 @@ /* Check if the chip fits between lowest valid and highest possible * address. Highest possible address with the current SPI implementation * means 0xffffff, the highest unsigned 24bit number. */ addrbase = spi_get_valid_read_addr(flash); - if (addrbase + flash->chip->total_size * 1024 > (1 << 24)) { + /* Show flash chip size warning if flash chip doesn't support + 4-Bytes Addressing mode and last address excedes 24 bits */ + if (!(flash->chip->feature_bits & FEATURE_FOUR_BYTE_ADDR) && + addrbase + flash->chip->total_size * 1024 > (1 << 24)) { msg_perr("Flash chip size exceeds the allowed access window. "); msg_perr("Read will probably fail.\n"); /* Try to get the best alignment subject to constraints. */ addrbase = (1 << 24) - flash->chip->total_size * 1024; } Index: spi25.c =================================================================== --- spi25.c (revision 1861) +++ spi25.c (working copy) @@ -26,10 +26,11 @@ #include "flash.h" #include "flashchips.h" #include "chipdrivers.h" #include "programmer.h" #include "spi.h" +#include "spi4ba.h" static int spi_rdid(struct flashctx *flash, unsigned char *readarr, int bytes) { static const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID }; int ret; @@ -946,10 +947,20 @@ unsigned int len, unsigned int chunksize) { int rc = 0; unsigned int i, j, starthere, lenhere, toread; unsigned int page_size = flash->chip->page_size; + int show_progress = 0; + unsigned int percent_last, percent_current; + + /* progress visualizaion init */ + if(len >= MIN_LENGTH_TO_SHOW_READ_PROGRESS) { + msg_cinfo(" "); /* only this space will go to logfile but all strings with \b wont. */ + msg_cinfo("\b 0%%"); + percent_last = percent_current = 0; + show_progress = 1; /* enable progress visualizaion */ + } /* Warning: This loop has a very unusual condition and body. * The loop needs to go through each page with at least one affected * byte. The lowest page number is (start / page_size) since that * division rounds down. The highest page number we want is the page @@ -964,18 +975,33 @@ starthere = max(start, i * page_size); /* Length of bytes in the range in this page. */ lenhere = min(start + len, (i + 1) * page_size) - starthere; for (j = 0; j < lenhere; j += chunksize) { toread = min(chunksize, lenhere - j); - rc = spi_nbyte_read(flash, starthere + j, buf + starthere - start + j, toread); + rc = (flash->chip->feature_bits & FEATURE_FOUR_BYTE_ADDR) == 0 + ? spi_nbyte_read(flash, starthere + j, buf + starthere - start + j, toread) + : flash->chip->four_bytes_addr_funcs.read_nbyte(flash, starthere + j, + buf + starthere - start + j, toread); if (rc) break; } if (rc) break; + + if(show_progress) { + percent_current = (unsigned int) ((unsigned long long)(starthere + + lenhere - start) * 100 / len); + if(percent_current != percent_last) { + msg_cinfo("\b\b\b%2d%%", percent_current); + percent_last = percent_current; + } + } } + if(show_progress && !rc) + msg_cinfo("\b\b\b\b"); /* remove progress percents from the screen */ + return rc; } /* * Write a part of the flash chip. @@ -1009,11 +1035,14 @@ starthere = max(start, i * page_size); /* Length of bytes in the range in this page. */ lenhere = min(start + len, (i + 1) * page_size) - starthere; for (j = 0; j < lenhere; j += chunksize) { towrite = min(chunksize, lenhere - j); - rc = spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite); + rc = (flash->chip->feature_bits & FEATURE_FOUR_BYTE_ADDR) == 0 + ? spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite) + : flash->chip->four_bytes_addr_funcs.program_nbyte(flash, starthere + j, + buf + starthere - start + j, towrite); if (rc) break; while (spi_read_status_register(flash) & SPI_SR_WIP) programmer_delay(10); } @@ -1035,11 +1064,13 @@ { unsigned int i; int result = 0; for (i = start; i < start + len; i++) { - result = spi_byte_program(flash, i, buf[i - start]); + result = (flash->chip->feature_bits & FEATURE_FOUR_BYTE_ADDR) == 0 + ? spi_byte_program(flash, i, buf[i - start]) + : flash->chip->four_bytes_addr_funcs.program_byte(flash, i, buf[i - start]); if (result) return 1; while (spi_read_status_register(flash) & SPI_SR_WIP) programmer_delay(10); } Index: spi4ba.c =================================================================== --- spi4ba.c (revision 0) +++ spi4ba.c (working copy) @@ -0,0 +1,1020 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2014 Boris Baykov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * SPI chip driver functions for 4-bytes addressing + */ + +#include <string.h> +#include "flash.h" +#include "chipdrivers.h" +#include "spi.h" +#include "programmer.h" +#include "spi4ba.h" + +/* #define MSG_TRACE_4BA_FUNCS 1 */ + +#ifdef MSG_TRACE_4BA_FUNCS +#define msg_trace(...) print(MSG_DEBUG, __VA_ARGS__) +#else +#define msg_trace(...) +#endif + +/* Enter 4-bytes addressing mode (without sending WREN before) */ +int spi_enter_4ba_b7(struct flashctx *flash) +{ + const unsigned char cmd[JEDEC_ENTER_4_BYTE_ADDR_MODE_OUTSIZE] = { JEDEC_ENTER_4_BYTE_ADDR_MODE }; + + msg_trace("-> %s\n", __func__); + + /* Switch to 4-bytes addressing mode */ + return spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); +} + +/* Enter 4-bytes addressing mode with sending WREN before */ +int spi_enter_4ba_b7_we(struct flashctx *flash) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_ENTER_4_BYTE_ADDR_MODE_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_ENTER_4_BYTE_ADDR_MODE }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s\n", __func__); + + /* Switch to 4-bytes addressing mode */ + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution\n", __func__); + } + return result; +} + +/* Write Extended Address Register value */ +int spi_write_extended_address_register(struct flashctx *flash, uint8_t regdata) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_WRITE_EXT_ADDR_REG_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_WRITE_EXT_ADDR_REG, + regdata + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (%02X)\n", __func__, regdata); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution\n", __func__); + return result; + } + return 0; +} + +/* Assign required value of Extended Address Register. This function + keeps last value of the register and writes the register if the + value has to be changed only. */ +int set_extended_address_register(struct flashctx *flash, uint8_t data) +{ + static uint8_t ext_addr_reg_state; /* memory for last register state */ + static int ext_addr_reg_state_valid = 0; + int result; + + if (ext_addr_reg_state_valid == 0 || data != ext_addr_reg_state) { + result = spi_write_extended_address_register(flash, data); + if (result) { + ext_addr_reg_state_valid = 0; + return result; + } + ext_addr_reg_state = data; + ext_addr_reg_state_valid = 1; + } + return 0; +} + +/* Program one flash byte from 4-bytes addressing mode */ +int spi_byte_program_4ba(struct flashctx *flash, unsigned int addr, + uint8_t databyte) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE + 1, + .writearr = (const unsigned char[]){ + JEDEC_BYTE_PROGRAM, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff), + databyte + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X)\n", __func__, addr); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + } + return result; +} + +/* Program flash bytes from 4-bytes addressing mode */ +int spi_nbyte_program_4ba(struct flashctx *flash, unsigned int addr, + const uint8_t *bytes, unsigned int len) +{ + int result; + unsigned char cmd[(JEDEC_BYTE_PROGRAM_OUTSIZE + 1) - 1 + 256] = { + JEDEC_BYTE_PROGRAM, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr >> 0) & 0xff + }; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = (JEDEC_BYTE_PROGRAM_OUTSIZE + 1) - 1 + len, + .writearr = cmd, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); + + if (!len) { + msg_cerr("%s called for zero-length write\n", __func__); + return 1; + } + if (len > 256) { + msg_cerr("%s called for too long a write\n", __func__); + return 1; + } + + memcpy(&cmd[(JEDEC_BYTE_PROGRAM_OUTSIZE + 1) - 1], bytes, len); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + } + return result; +} + +/* Read flash bytes from 4-bytes addressing mode */ +int spi_nbyte_read_4ba(struct flashctx *flash, unsigned int addr, + uint8_t *bytes, unsigned int len) +{ + const unsigned char cmd[JEDEC_READ_OUTSIZE + 1] = { + JEDEC_READ, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr >> 0) & 0xff + }; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); + + /* Send Read */ + return spi_send_command(flash, sizeof(cmd), len, cmd, bytes); +} + +/* Program one flash byte with 4-bytes address from ANY mode (3-bytes or 4-bytes) + JEDEC_BYTE_PROGRAM_4BA (12h) instruction is new for 4-bytes addressing flash chips. + The presence of this instruction for an exact chip should be checked + by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */ +int spi_byte_program_4ba_direct(struct flashctx *flash, unsigned int addr, + uint8_t databyte) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_4BA_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BYTE_PROGRAM_4BA, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff), + databyte + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X)\n", __func__, addr); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + } + return result; +} + +/* Program flash bytes with 4-bytes address from ANY mode (3-bytes or 4-bytes) + JEDEC_BYTE_PROGRAM_4BA (12h) instruction is new for 4-bytes addressing flash chips. + The presence of this instruction for an exact chip should be checked + by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */ +int spi_nbyte_program_4ba_direct(struct flashctx *flash, unsigned int addr, + const uint8_t *bytes, unsigned int len) +{ + int result; + unsigned char cmd[JEDEC_BYTE_PROGRAM_4BA_OUTSIZE - 1 + 256] = { + JEDEC_BYTE_PROGRAM_4BA, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr >> 0) & 0xff + }; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_4BA_OUTSIZE - 1 + len, + .writearr = cmd, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); + + if (!len) { + msg_cerr("%s called for zero-length write\n", __func__); + return 1; + } + if (len > 256) { + msg_cerr("%s called for too long a write\n", __func__); + return 1; + } + + memcpy(&cmd[JEDEC_BYTE_PROGRAM_4BA_OUTSIZE - 1], bytes, len); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + } + return result; +} + +/* Read flash bytes with 4-bytes address from ANY mode (3-bytes or 4-bytes) + JEDEC_READ_4BA (13h) instruction is new for 4-bytes addressing flash chips. + The presence of this instruction for an exact chip should be checked + by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */ +int spi_nbyte_read_4ba_direct(struct flashctx *flash, unsigned int addr, + uint8_t *bytes, unsigned int len) +{ + const unsigned char cmd[JEDEC_READ_4BA_OUTSIZE] = { + JEDEC_READ_4BA, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr >> 0) & 0xff + }; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); + + /* Send Read */ + return spi_send_command(flash, sizeof(cmd), len, cmd, bytes); +} + +/* Program one flash byte using Extended Address Register + from 3-bytes addressing mode */ +int spi_byte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, + uint8_t databyte) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BYTE_PROGRAM, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff), + databyte + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X)\n", __func__, addr); + + result = set_extended_address_register(flash, (addr >> 24) & 0xff); + if (result) + return result; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + } + return result; +} + +/* Program flash bytes using Extended Address Register + from 3-bytes addressing mode */ +int spi_nbyte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, + const uint8_t *bytes, unsigned int len) +{ + int result; + unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = { + JEDEC_BYTE_PROGRAM, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr >> 0) & 0xff + }; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + len, + .writearr = cmd, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); + + if (!len) { + msg_cerr("%s called for zero-length write\n", __func__); + return 1; + } + if (len > 256) { + msg_cerr("%s called for too long a write\n", __func__); + return 1; + } + + memcpy(&cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1], bytes, len); + + result = set_extended_address_register(flash, (addr >> 24) & 0xff); + if (result) + return result; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + } + return result; +} + +/* Read flash bytes using Extended Address Register + from 3-bytes addressing mode */ +int spi_nbyte_read_4ba_ereg(struct flashctx *flash, unsigned int addr, + uint8_t *bytes, unsigned int len) +{ + int result; + const unsigned char cmd[JEDEC_READ_OUTSIZE] = { + JEDEC_READ, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr >> 0) & 0xff + }; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); + + result = set_extended_address_register(flash, (addr >> 24) & 0xff); + if (result) + return result; + + /* Send Read */ + return spi_send_command(flash, sizeof(cmd), len, cmd, bytes); +} + +/* Chooser for erase function by instruction opcode for block eraser instructions + to work with 4-bytes addressing flash chips. This chooser is called from sfdp.c + during parse of 8th & 9th dwords of SFDP Basic Flash Parameter Table */ +erasefunc_t *spi_get_erasefn_from_opcode_4ba(uint8_t opcode) +{ + msg_trace("-> %s\n", __func__); + + switch(opcode){ + case 0xff: + case 0x00: + /* Not specified, assuming "not supported". */ + return NULL; + case 0x20: + return &spi_block_erase_20_4ba_selector; /* selector */ + case 0x52: + return &spi_block_erase_52_4ba_selector; /* selector */ + case 0x60: + return &spi_block_erase_60; + case 0x62: + return &spi_block_erase_62; + case 0xc7: + return &spi_block_erase_c7; + case 0xd8: + return &spi_block_erase_d8_4ba_selector; /* selector */ + case 0x50: + case 0x81: + case 0xc4: + case 0xd7: + case 0xdb: + msg_cinfo("%s: erase opcode (0x%02x) doesn't have its 4-bytes addressing version." + " Please report this at flashrom(a)flashrom.org\n", __func__, opcode); + return NULL; + default: + msg_cinfo("%s: unknown erase opcode (0x%02x). Please report " + "this at flashrom(a)flashrom.org\n", __func__, opcode); + return NULL; + } +} + +/* Selector for 4k eraser that chooses between 4-bytes addressing mode + and use of Extended Address Register from 3-bytes addressing mode */ +int spi_block_erase_20_4ba_selector(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + msg_trace("-> %s\n", __func__); + + return (flash->chip->feature_bits & FEATURE_NEED_USE_EXTENDED_ADDR_REG) ? + spi_block_erase_20_4ba_ereg(flash, addr, blocklen) : + spi_block_erase_20_4ba(flash, addr, blocklen); +} + +/* Erases 4 KB of flash from 4-bytes addressing mode */ +int spi_block_erase_20_4ba(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_SE_OUTSIZE + 1, + .writearr = (const unsigned char[]){ + JEDEC_SE, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 15-800 ms, so wait in 10 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(10 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Selector for 32k eraser that chooses between 4-bytes addressing mode + and use of Extended Address Register from 3-bytes addressing mode */ +int spi_block_erase_52_4ba_selector(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + msg_trace("-> %s\n", __func__); + + return (flash->chip->feature_bits & FEATURE_NEED_USE_EXTENDED_ADDR_REG) ? + spi_block_erase_52_4ba_ereg(flash, addr, blocklen) : + spi_block_erase_52_4ba(flash, addr, blocklen); +} + +/* Erases 32 KB of flash from 4-bytes addressing mode */ +int spi_block_erase_52_4ba(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_52_OUTSIZE + 1, + .writearr = (const unsigned char[]){ + JEDEC_BE_52, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(100 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Selector for 64k eraser that chooses between 4-bytes addressing mode + and use of Extended Address Register from 3-bytes addressing mode */ +int spi_block_erase_d8_4ba_selector(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + msg_trace("-> %s\n", __func__); + + return (flash->chip->feature_bits & FEATURE_NEED_USE_EXTENDED_ADDR_REG) ? + spi_block_erase_d8_4ba_ereg(flash, addr, blocklen) : + spi_block_erase_d8_4ba(flash, addr, blocklen); +} + +/* Erases 64 KB of flash from 4-bytes addressing mode */ +int spi_block_erase_d8_4ba(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_D8_OUTSIZE + 1, + .writearr = (const unsigned char[]){ + JEDEC_BE_D8, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(100 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Erases 4 KB of flash using Extended Address Register + from 3-bytes addressing mode */ +int spi_block_erase_20_4ba_ereg(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_SE_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_SE, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = set_extended_address_register(flash, (addr >> 24) & 0xff); + if (result) + return result; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 15-800 ms, so wait in 10 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(10 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Erases 32 KB of flash using Extended Address Register + from 3-bytes addressing mode */ +int spi_block_erase_52_4ba_ereg(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_52_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BE_52, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = set_extended_address_register(flash, (addr >> 24) & 0xff); + if (result) + return result; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(100 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Erases 64 KB of flash using Extended Address Register + from 3-bytes addressing mode */ +int spi_block_erase_d8_4ba_ereg(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_D8_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BE_D8, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = set_extended_address_register(flash, (addr >> 24) & 0xff); + if (result) + return result; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(100 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Chooser for erase function by instruction opcode for block eraser instructions + which can be used from ANY mode (3-bytes or 4-bytes). This chooser is called + from sfdp.c during parse of SFDP 4-Bytes Address Instruction Table (JESD216B) */ +erasefunc_t *spi_get_erasefn_from_opcode_4ba_direct(uint8_t opcode) +{ + msg_trace("-> %s\n", __func__); + + switch(opcode){ + case 0xff: + case 0x00: + /* Not specified, assuming "not supported". */ + return NULL; + case 0x21: + return &spi_block_erase_21_4ba_direct; /* direct */ + case 0x5C: + return &spi_block_erase_5c_4ba_direct; /* direct */ + case 0xdc: + return &spi_block_erase_dc_4ba_direct; /* direct */ + default: + msg_cinfo("%s: unknown erase opcode (0x%02x). Please report " + "this at flashrom(a)flashrom.org\n", __func__, opcode); + return NULL; + } +} + +/* Erase 4 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) + JEDEC_SE_4BA (21h) instruction is new for 4-bytes addressing flash chips. + The presence of this instruction for an exact chip should be checked + by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */ +int spi_block_erase_21_4ba_direct(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_SE_4BA_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_SE_4BA, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 15-800 ms, so wait in 10 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(10 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Erase 32 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) + JEDEC_BE_5C_4BA (5Ch) instruction is new for 4-bytes addressing flash chips. + The presence of this instruction for an exact chip should be checked + by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */ +int spi_block_erase_5c_4ba_direct(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_5C_4BA_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BE_5C_4BA, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(100 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Erase 64 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) + JEDEC_BE_DC_4BA (DCh) instruction is new for 4-bytes addressing flash chips. + The presence of this instruction for an exact chip should be checked + by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */ +int spi_block_erase_dc_4ba_direct(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_DC_4BA_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BE_DC_4BA, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(100 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} Property changes on: spi4ba.c ___________________________________________________________________ Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: spi4ba.h =================================================================== --- spi4ba.h (revision 0) +++ spi4ba.h (working copy) @@ -0,0 +1,158 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2014 Boris Baykov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +/* + * JEDEC flash chips instructions for 4-bytes addressing + * SPI chip driver functions for 4-bytes addressing + */ + +#ifndef __SPI_4BA_H__ +#define __SPI_4BA_H__ 1 + +/* Read the memory with 4-byte address + From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ +#define JEDEC_READ_4BA 0x13 +#define JEDEC_READ_4BA_OUTSIZE 0x05 +/* JEDEC_READ_4BA_INSIZE : any length */ + +/* Write memory byte with 4-byte address + From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ +#define JEDEC_BYTE_PROGRAM_4BA 0x12 +#define JEDEC_BYTE_PROGRAM_4BA_OUTSIZE 0x06 +#define JEDEC_BYTE_PROGRAM_4BA_INSIZE 0x00 + +/* Sector Erase 0x21 (with 4-byte address), usually 4k size. + From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ +#define JEDEC_SE_4BA 0x21 +#define JEDEC_SE_4BA_OUTSIZE 0x05 +#define JEDEC_SE_4BA_INSIZE 0x00 + +/* Block Erase 0x5C (with 4-byte address), usually 32k size. + From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ +#define JEDEC_BE_5C_4BA 0x5C +#define JEDEC_BE_5C_4BA_OUTSIZE 0x05 +#define JEDEC_BE_5C_4BA_INSIZE 0x00 + +/* Block Erase 0xDC (with 4-byte address), usually 64k size. + From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ +#define JEDEC_BE_DC_4BA 0xdc +#define JEDEC_BE_DC_4BA_OUTSIZE 0x05 +#define JEDEC_BE_DC_4BA_INSIZE 0x00 + +/* Enter 4-byte Address Mode */ +#define JEDEC_ENTER_4_BYTE_ADDR_MODE 0xB7 +#define JEDEC_ENTER_4_BYTE_ADDR_MODE_OUTSIZE 0x01 +#define JEDEC_ENTER_4_BYTE_ADDR_MODE_INSIZE 0x00 + +/* Exit 4-byte Address Mode */ +#define JEDEC_EXIT_4_BYTE_ADDR_MODE 0xE9 +#define JEDEC_EXIT_4_BYTE_ADDR_MODE_OUTSIZE 0x01 +#define JEDEC_EXIT_4_BYTE_ADDR_MODE_INSIZE 0x00 + +/* Write Extended Address Register */ +#define JEDEC_WRITE_EXT_ADDR_REG 0xC5 +#define JEDEC_WRITE_EXT_ADDR_REG_OUTSIZE 0x02 +#define JEDEC_WRITE_EXT_ADDR_REG_INSIZE 0x00 + +/* Read Extended Address Register */ +#define JEDEC_READ_EXT_ADDR_REG 0xC8 +#define JEDEC_READ_EXT_ADDR_REG_OUTSIZE 0x01 +#define JEDEC_READ_EXT_ADDR_REG_INSIZE 0x01 + + +/* JEDEC Basic Flash Parameters Table definition */ +#define JEDEC_BFPT_ID 0xFF00 + +/* JEDEC Basic Flash Parameters Table 16th dword according to JESD216B */ +/* 16th dword of BFPT, bits 24:31 (Enter 4-Byte Addressing) */ +#define JEDEC_BFPT_DW16_ENTER_B7 (1UL << 24) +#define JEDEC_BFPT_DW16_ENTER_B7_WE (1UL << 25) +#define JEDEC_BFPT_DW16_ENTER_EXTENDED_ADDR_REG (1UL << 26) +#define JEDEC_BFPT_DW16_ENTER_BANK_ADDR_REG_EN_BIT (1UL << 27) +#define JEDEC_BFPT_DW16_ENTER_NV_CONFIG_REG (1UL << 28) +#define JEDEC_BFPT_DW16_VENDOR_SET (1UL << 29) +#define JEDEC_BFPT_DW16_4_BYTES_ADDRESS_ONLY (1UL << 30) +#define JEDEC_BFPT_DW16_ENTER_RESERVED (1UL << 31) +/* 16th dword of BFPT, bits 14:23 (Exit 4-Byte Addressing) */ +#define JEDEC_BFPT_DW16_EXIT_E9 (1UL << 14) +#define JEDEC_BFPT_DW16_EXIT_E9_WE (1UL << 15) +#define JEDEC_BFPT_DW16_EXIT_EXTENDED_ADDR_REG (1UL << 16) +#define JEDEC_BFPT_DW16_EXIT_BANK_ADDR_REG_EN_BIT (1UL << 17) +#define JEDEC_BFPT_DW16_EXIT_NV_CONFIG_REG (1UL << 18) +#define JEDEC_BFPT_DW16_EXIT_HARD_RESET (1UL << 19) +#define JEDEC_BFPT_DW16_EXIT_SOFT_RESET (1UL << 20) +#define JEDEC_BFPT_DW16_EXIT_POWER_CYCLE (1UL << 21) +#define JEDEC_BFPT_DW16_EXIT_RESERVED_1 (1UL << 22) +#define JEDEC_BFPT_DW16_EXIT_RESERVED_2 (1UL << 23) + +/* JEDEC 4-Bytes Addressing Table 1st dword according to JESD216B */ +#define JEDEC_4BAIT_ID 0xFF84 +#define JEDEC_4BAIT_READ_SUPPORT (1UL << 0) +#define JEDEC_4BAIT_PROGRAM_SUPPORT (1UL << 6) +#define JEDEC_4BAIT_ERASE_TYPE_1_SUPPORT (1UL << 9) +#define JEDEC_4BAIT_ERASE_TYPE_2_SUPPORT (1UL << 10) +#define JEDEC_4BAIT_ERASE_TYPE_3_SUPPORT (1UL << 11) +#define JEDEC_4BAIT_ERASE_TYPE_4_SUPPORT (1UL << 12) + +/* read/write flash bytes in 4-bytes addressing mode */ +int spi_byte_program_4ba(struct flashctx *flash, unsigned int addr, uint8_t databyte); +int spi_nbyte_program_4ba(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len); +int spi_nbyte_read_4ba(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); + +/* read/write flash bytes with 4-bytes address from any mode (3-byte or 4-byte) */ +int spi_byte_program_4ba_direct(struct flashctx *flash, unsigned int addr, uint8_t databyte); +int spi_nbyte_program_4ba_direct(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len); +int spi_nbyte_read_4ba_direct(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); + +/* read/write flash bytes from 3-bytes addressing mode using extended address register */ +int spi_byte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, uint8_t databyte); +int spi_nbyte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len); +int spi_nbyte_read_4ba_ereg(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); + +/* enter 4-bytes addressing mode */ +int spi_enter_4ba_b7(struct flashctx *flash); +int spi_enter_4ba_b7_we(struct flashctx *flash); + +/* erase functions choosers for 4-bytes addressing mode */ +erasefunc_t *spi_get_erasefn_from_opcode_4ba(uint8_t opcode); +erasefunc_t *spi_get_erasefn_from_opcode_4ba_direct(uint8_t opcode); + +/* erase flash bytes in 4-bytes addressing mode */ +int spi_block_erase_20_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_52_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_d8_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + +/* erase flash bytes from 3-bytes addressing mode using extended address register */ +int spi_block_erase_20_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_52_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_d8_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + +/* selection of erase function between 4-bytes addressing mode and use of extended address register */ +int spi_block_erase_20_4ba_selector(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_52_4ba_selector(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_d8_4ba_selector(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + +/* erase flash bytes with 4-bytes address from any mode (3-byte or 4-byte) */ +int spi_block_erase_21_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_5c_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_dc_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + + +#endif /* __SPI_4BA_H__ */ Property changes on: spi4ba.h ___________________________________________________________________ Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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please reject my last letter with patch
by Boris Baykov 09 Jan '15

09 Jan '15

Unfortunately, my last patch letter is wrong too. I'll send two right ones soon. Boris Baykov

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[PATCH 1/2] Read/erase/program 4-bytes addressing SPI flash chips 32MB+ for 0.9.7-r1861 build
by dev＠borisbaykov.com 09 Jan '15

09 Jan '15

Current patch is for the last 0.9.7-r1861 build taken by SVN from svn://flashrom.org. The patch is made by SVN diff. Two same patches for different builds (one patch per letter) ------------------------------------------------------------ [1/2] Patch for Flashrom 0.9.7 (build 1861) by SVN diff [2/2] Patch for last 0.9.7 release (build 1711) by Linux diff Brief description ----------------- This patch adds ability to read, write and erase flash chips which require 4-bytes (32-bit) addressing to access to them. These are 32MB (256Mb) and larger new flash chips. Flashrom with this patch can support and program all (or most of all) of them. Besides of manually definable chips in flashchips.c this patch adds compliance to new JEDEC JESD216B standard which describes SFDP revision 1.6 procedure to read flash chip 4-bytes addressing details. Full description ---------------- This patch includes code for three types of 4-byte addressing: 1. Flash chip can be switched to 4-bytes addressing mode and then all read/erase/program instructions will be switched from 3-bytes mode to 4-bytes mode. So, well known instructions like 03h (Read), 02h (Program) and 20h,52h,D8h (Erase) are becoming one byte longer and accept 4-bytes address instead of 3-bytes. 4-bytes addressing mode is entered by the instruction B7h with preceding Write Enable (WREN). This is default method. 2. Also Flash chip data with addresses more than 24-bit field can address may be accessed by use of Extended Address Register that has 1-byte size and stores high byte of 32-bit address. So, we read flash from old 3-bytes addressing mode and write high byte of address to special register. Then we have access to full memory of a chip. Some chips may support this method only. 3. Also some new commands avalable and implemented. Large size flash chips support special instructions to use 4-bytes address directly from 3-bytes addressing mode and without do switching to 4-bytes mode. There are 13h (4BA Read), 12h (4BA Program) and 21h,5Ch,DCh (4BA Erase), correspondingly. However not all these commands are supported by all large flash chips. Some chips support 13h only, some 13h,12h,21h and DCh, but not 5Ch. This depends on the manufacturer of the chip. The patch adds code for all 3 types of 4-bytes address access and the exact method should be choosen by person who will manage to add new large chips to flashchips.c source file. I've added one new flash chip: Winbond W25Q256FV (32MB) because this is the only chip I have now for testing. Besides of manual including of new chips to Flashrom we may use SFDP procedure to discover parameters of the exact flash chip. More than a year before JEDEC released new standard JESD216 (revision B) which describes in detail how to receive 4-bytes addressing settings from the chip. This patch provides new code to add compliance to JESD216B to Flashrom. This means that Flashrom now can automatically detect 4-bytes addressing features of large flash chips and use them to access data. However not all thing are so good. Unfortunately JESD216B had come to manufacturer's production lines just 2-3 months ago. So, we have many chips that have large size requires 32-bit addressing but their SFDP tables have revision lower than 1.6 (described in JESD216B standard). For example my W25Q256FV returns SFDP info with revision 1.0, first one :-) This situation leads us to requirement to try to work now without new SFDP info. And it's implemented in the patch too. To test my parser code for SFDP revision 1.6 (from JESD216B) I've added some simulation code to sfdp.c. This code builds fake SFDP 1.6 tables in memory and passes them to the SFDP parser. Surely this simulation code is switched off by default and can be activated via hidden define on the top of sfdp.c Also I've added progress visualization for read, erase and write operations. It's turned out that seeing progress is essential for reading and especially writing 32 MB of data via SPI. The operation can take more then 10 minutes on 15 MHz frequency of SPI. So, it's good to see its progress. I've added percents and slightly modified cli_output.c to send percents to screen only but not to logfile. Testing results --------------- Both patches are tested with Winbond W25Q256FV flash chip using Olimex ARM-USB-OCD-H programmer. Read, Erase and Program functions are fully tested for 4-bytes addressing type 1 (4-bytes mode), type 2 (extended addr. register) and partially tested for type 3 (new 4-bytes instructions with 4-bytes address). My W25Q256FV has support for 4BA_Read (13h) only, but doesn't support 4BA_Program (12h) and 4BA_Erase instructions. So, direct 4BA program and erase should be tested after. Also I should make an excuse about testing of SFDP rev 1.6 parser. I've tested it as good as I can using the simulation code I described above but I'm not able to test it on real flash chips because I don't have a chip complied to JESD216B with SFDP 1.6 now. This should be tested later too. Patched files ------------- chipdrivers.h - added functions declarations for spi4ba.c cli_output.c - print() patched to skip strings which are starting from '\b' to prevent writing progress percents to logfile flash.h - feature definitions added - added set of 4-bytes address functions to flashchip structure definition - added type field to block_eraser structure - added some definitions for progress visialization flashchips.c - added definition for Winbond W25Q256BV/W25Q256FV chips flashrom.c - added switch to 4-bytes addressing more for chips which support it - added progress visualization for erase/write (essensial for 32MB+ chips) - changed in address print %06x to %08x to support 32MB+ chips - added line to the flashrom's banner about this patch (temporary) Makefile - added spi4ba.c serprog.c - added 4-bytes addressing spi_nbyte_read call to serprog_spi_read spi.c - fixed flash chip size check in spi_chip_read spi25.c - added 4-bytes addressing spi_nbyte_read call to spi_read_chunked - added 4-bytes addressing spi_nbyte_program call to spi_write_chunked - added 4-bytes addressing spi_byte_program call to spi_chip_write_1 - added progress visualization for read operation (essensial for 32MB+ chips) sfdp.c - added compliance to JEDEC JESD216B standard (SFDP revision 1.6) - added parse of SFDP 4-Bytes Addressing features (probe_spi_sfdp,sfdp_fill_flash) - added parse of SFDP 4-Bytes Addressing Instruction Table (sfdp_parse_4ba_table) - added choosing of block_erasers for 4-bytes addressing (sfdp_*_uniform_eraser*) - added exact flash page_size recognision from 11th dword in SFDP rev 1.6 - added fix for Micron chips to read 16th dword stating from SFDP revision 1.5 - added simulation of JESD216B for any flash chips (just for testing) Added files ----------- spi4ba.h - definitions for 4-bytes addressing JEDEC commands - definitions for 16th dword bits of SFDP Basic Flash Param Table (JESD216B) - definitions for SFDP 4-Bytes Addressing Instruction Table (JESD216B) - functions declarations from spi4ba.c (same as in chipdrivers.h, just to see) spi4ba.c - functions for enter 4-bytes addressing mode - functions for write Extended Address Register - functions for read/write/erase in 4-bytes addressing mode - functions for read/write/erase with Extended Address Register - functions for read/write/erase directly with 4-bytes address (from any mode) - functions to choose block_eraser by opcode for 4-bytes addressing for sfdp.c - functions to select proper block_eraser (ext.reg or 4-bytes addr) for sfdp.c Signed-off-by: Boris Baykov <dev(a)borisbaykov.com>, Russia, Jan 2014 --- Index: Makefile =================================================================== --- Makefile (revision 1861) +++ Makefile (working copy) @@ -355,11 +355,11 @@ ############################################################################### # Flash chip drivers and bus support infrastructure. CHIP_OBJS = jedec.o stm50.o w39.o w29ee011.o \ sst28sf040.o 82802ab.o \ - sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o spi25_statusreg.o \ + sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o spi25_statusreg.o spi4ba.o \ opaque.o sfdp.o en29lv640b.o at45db.o ############################################################################### # Library code. Index: chipdrivers.h =================================================================== --- chipdrivers.h (revision 1861) +++ chipdrivers.h (working copy) @@ -192,6 +192,33 @@ /* en29lv640b.c */ int probe_en29lv640b(struct flashctx *flash); int write_en29lv640b(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); +/* spi4ba.c */ +int spi_enter_4ba_b7(struct flashctx *flash); +int spi_enter_4ba_b7_we(struct flashctx *flash); +int spi_byte_program_4ba(struct flashctx *flash, unsigned int addr, uint8_t databyte); +int spi_nbyte_program_4ba(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len); +int spi_nbyte_read_4ba(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); +int spi_byte_program_4ba_direct(struct flashctx *flash, unsigned int addr, uint8_t databyte); +int spi_nbyte_program_4ba_direct(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len); +int spi_nbyte_read_4ba_direct(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); +int spi_byte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, uint8_t databyte); +int spi_nbyte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len); +int spi_nbyte_read_4ba_ereg(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); +erasefunc_t *spi_get_erasefn_from_opcode_4ba(uint8_t opcode); +erasefunc_t *spi_get_erasefn_from_opcode_4ba_direct(uint8_t opcode); +int spi_block_erase_20_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_20_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_20_4ba_selector(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_52_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_52_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_52_4ba_selector(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_d8_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_d8_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_d8_4ba_selector(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_21_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_5c_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_dc_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + #endif /* !__CHIPDRIVERS_H__ */ Index: cli_output.c =================================================================== --- cli_output.c (revision 1861) +++ cli_output.c (working copy) @@ -88,11 +88,12 @@ * time-critical operations. Don't slow them down by flushing. */ if (level != MSG_SPEW) fflush(output_type); } #ifndef STANDALONE - if ((level <= verbose_logfile) && logfile) { + /* skip of msgs starting from '\b' added to skip progress percents */ + if ((level <= verbose_logfile) && logfile && (!fmt || fmt[0] != '\b')) { va_start(ap, fmt); ret = vfprintf(logfile, fmt, ap); va_end(ap); if (level != MSG_SPEW) fflush(logfile); Index: flash.h =================================================================== --- flash.h (revision 1861) +++ flash.h (working copy) @@ -119,10 +119,18 @@ #define FEATURE_WRSR_EWSR (1 << 6) #define FEATURE_WRSR_WREN (1 << 7) #define FEATURE_WRSR_EITHER (FEATURE_WRSR_EWSR | FEATURE_WRSR_WREN) #define FEATURE_OTP (1 << 8) #define FEATURE_QPI (1 << 9) +/* Feature bits used for 4-bytes addressing mode */ +#define FEATURE_FOUR_BYTE_ADDR (1 << 10) +#define FEATURE_FOUR_BYTE_ADDR_ONLY (1 << 11) +#define FEATURE_NEED_ENTER_4BA_FOR_READ (1 << 12) +#define FEATURE_NEED_ENTER_4BA_FOR_WRITE (1 << 13) +#define FEATURE_NEED_ENTER_4BA_FOR_ERASE (1 << 14) +#define FEATURE_NEED_USE_EXTENDED_ADDR_REG (1 << 15) +#define FEATURE_ENTER_4BA_ALL (FEATURE_NEED_ENTER_4BA_FOR_READ | FEATURE_NEED_ENTER_4BA_FOR_WRITE | FEATURE_NEED_ENTER_4BA_FOR_ERASE | FEATURE_NEED_USE_EXTENDED_ADDR_REG) enum test_state { OK = 0, NT = 1, /* Not tested */ BAD, /* Known to not work */ @@ -163,10 +171,18 @@ unsigned int total_size; /* Chip page size in bytes */ unsigned int page_size; int feature_bits; + /* set of function pointers to use in 4-bytes addressing mode */ + struct four_bytes_addr_funcs_set { + int (*enter_4ba) (struct flashctx *flash); + int (*read_nbyte) (struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); + int (*program_byte) (struct flashctx *flash, unsigned int addr, const uint8_t databyte); + int (*program_nbyte) (struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len); + } four_bytes_addr_funcs; + /* Indicate how well flashrom supports different operations of this flash chip. */ struct tested { enum test_state probe; enum test_state read; enum test_state erase; @@ -186,10 +202,11 @@ * The first one that fits will be chosen. There is currently no way to * influence that behaviour. For testing just comment out the other * elements or set the function pointer to NULL. */ struct block_eraser { + int type; /* eraser type 1,2,3 or 4 */ struct eraseblock { unsigned int size; /* Eraseblock size in bytes */ unsigned int count; /* Number of contiguous blocks with that size */ } eraseblocks[NUM_ERASEREGIONS]; /* a block_erase function should try to erase one block of size @@ -337,10 +354,15 @@ #define msg_cdbg2(...) print(MSG_DEBUG2, __VA_ARGS__) /* chip debug2 */ #define msg_gspew(...) print(MSG_SPEW, __VA_ARGS__) /* general debug spew */ #define msg_pspew(...) print(MSG_SPEW, __VA_ARGS__) /* programmer debug spew */ #define msg_cspew(...) print(MSG_SPEW, __VA_ARGS__) /* chip debug spew */ +/* Read progress will be shown for reads more than 256KB */ +#define MIN_LENGTH_TO_SHOW_READ_PROGRESS 256 * 1024 +/* Read progress will be shown for erases and writes more than 64KB */ +#define MIN_LENGTH_TO_SHOW_ERASE_AND_WRITE_PROGRESS 64 * 1024 + /* layout.c */ int register_include_arg(char *name); int process_include_args(void); int read_romlayout(const char *name); int normalize_romentries(const struct flashctx *flash); Index: flashchips.c =================================================================== --- flashchips.c (revision 1861) +++ flashchips.c (working copy) @@ -13282,10 +13282,59 @@ .voltage = {2700, 3600}, }, { .vendor = "Winbond", + .name = "W25Q256.V", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q256_V, + .total_size = 32768, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_FOUR_BYTE_ADDR | + FEATURE_NEED_ENTER_4BA_FOR_ERASE | FEATURE_NEED_ENTER_4BA_FOR_WRITE, + .four_bytes_addr_funcs = + { + .enter_4ba = spi_enter_4ba_b7_we, /* enter 4-bytes addressing mode by CMD B7 + WREN */ + .read_nbyte = spi_nbyte_read_4ba_direct, /* read directly from any mode, no need to enter 4ba */ + .program_byte = spi_byte_program_4ba, /* write from 4-bytes addressing mode */ + .program_nbyte = spi_nbyte_program_4ba /* write from 4-bytes addressing mode */ + }, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20_4ba, /* erases 4k from 4-bytes addressing mode */ + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_52_4ba, /* erases 32k from 4-bytes addressing mode */ + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8_4ba, /* erases 64k from 4-bytes addressing mode */ + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Winbond", .name = "W25Q20.W", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, .model_id = WINBOND_NEX_W25Q20_W, .total_size = 256, Index: flashrom.c =================================================================== --- flashrom.c (revision 1861) +++ flashrom.c (working copy) @@ -1366,12 +1366,12 @@ "non-empty erase function. Not an error.\n"); if (!done) continue; if (done != chip->total_size * 1024) { msg_gerr("ERROR: Flash chip %s erase function %i " - "region walking resulted in 0x%06x bytes total," - " expected 0x%06x bytes. Please report a bug at" + "region walking resulted in 0x%08x bytes total," + " expected 0x%08x bytes. Please report a bug at" " flashrom(a)flashrom.org\n", chip->name, k, done, chip->total_size * 1024); ret = 1; } if (!eraser.block_erase) @@ -1460,29 +1460,52 @@ { int i, j; unsigned int start = 0; unsigned int len; struct block_eraser eraser = flash->chip->block_erasers[erasefunction]; + int show_progress = 0; + unsigned int percent_last, percent_current; + unsigned long size = flash->chip->total_size * 1024; + + /* progress visualizaion init */ + if(size >= MIN_LENGTH_TO_SHOW_ERASE_AND_WRITE_PROGRESS) { + msg_cinfo(" "); /* only this space will go to logfile but all strings with \b wont. */ + msg_cinfo("\b 0%%"); + percent_last = percent_current = 0; + show_progress = 1; /* enable progress visualizaion */ + } for (i = 0; i < NUM_ERASEREGIONS; i++) { /* count==0 for all automatically initialized array * members so the loop below won't be executed for them. */ len = eraser.eraseblocks[i].size; for (j = 0; j < eraser.eraseblocks[i].count; j++) { /* Print this for every block except the first one. */ if (i || j) msg_cdbg(", "); - msg_cdbg("0x%06x-0x%06x", start, + msg_cdbg("0x%08x-0x%08x", start, start + len - 1); if (do_something(flash, start, len, param1, param2, eraser.block_erase)) { return 1; } start += len; + + if(show_progress) { + percent_current = (unsigned int) ((unsigned long long)start * 100 / size); + if(percent_current != percent_last) { + msg_cinfo("\b\b\b%2d%%", percent_current); + percent_last = percent_current; + } + } } } + + if(show_progress) + msg_cinfo("\b\b\b\b"); /* remove progress percents from the screen */ + msg_cdbg("\n"); return 0; } static int check_block_eraser(const struct flashctx *flash, int k, int log) @@ -1735,12 +1758,15 @@ } void print_version(void) { msg_ginfo("flashrom v%s", flashrom_version); + msg_ginfo("-4ba"); /* temporary to indicate that version is patched */ print_sysinfo(); msg_ginfo("\n"); + /* temporary to indicate that version is patched */ + msg_ginfo("with patch for support SPI flash chips with 4-bytes addressing\n"); } void print_banner(void) { msg_ginfo("flashrom is free software, get the source code at " @@ -1934,10 +1960,42 @@ * erase and write. */ if (flash->chip->unlock) flash->chip->unlock(flash); + if(flash->chip->feature_bits & FEATURE_FOUR_BYTE_ADDR) { + /* Switching to 4-Bytes Addressing mode if flash chip supports it + and selected operation requires 4-Bytes Addressing mode + (no need for direct and ext.addr.reg operation) */ + if(((read_it || verify_it) && (flash->chip->feature_bits & FEATURE_NEED_ENTER_4BA_FOR_READ)) || + ((erase_it || write_it) && (flash->chip->feature_bits & (FEATURE_NEED_ENTER_4BA_FOR_READ | + FEATURE_NEED_ENTER_4BA_FOR_WRITE | FEATURE_NEED_ENTER_4BA_FOR_ERASE))) ) { + + if (!flash->chip->four_bytes_addr_funcs.enter_4ba) { + msg_cerr("No function for Enter 4-bytes addressing mode for this flash chip.\n" + "Please report to flashrom(a)flashrom.org\n"); + return 1; + } + + if(flash->chip->four_bytes_addr_funcs.enter_4ba(flash)) { + msg_cerr("Switching to 4-bytes addressing mode failed!\n"); + return 1; + } + + msg_cdbg("Switched to 4-bytes addressing mode.\n"); + } + /* Do not switch to 4-Bytes Addressing mode if using Extended Address Register */ + else if(flash->chip->feature_bits & FEATURE_NEED_USE_EXTENDED_ADDR_REG) { + msg_cdbg("Using 4-bytes addressing with extended address register.\n"); + } + /* Do not switch to 4-Bytes Addressing mode if all instructions are direct-4BA + or if the flash chip is 4-Bytes Addressing Only and always in 4BA-mode */ + else { + msg_cdbg2("No need to switch to 4-bytes addressing mode.\n"); + } + } + if (read_it) { return read_flash_to_file(flash, filename); } oldcontents = malloc(size); Index: serprog.c =================================================================== --- serprog.c (revision 1861) +++ serprog.c (working copy) @@ -933,11 +933,14 @@ unsigned int i, cur_len; const unsigned int max_read = spi_master_serprog.max_data_read; for (i = 0; i < len; i += cur_len) { int ret; cur_len = min(max_read, (len - i)); - ret = spi_nbyte_read(flash, start + i, buf + i, cur_len); + ret = (flash->chip->feature_bits & FEATURE_FOUR_BYTE_ADDR) == 0 + ? spi_nbyte_read(flash, start + i, buf + i, cur_len) + : flash->chip->four_bytes_addr_funcs.read_nbyte(flash, + start + i, buf + i, cur_len); if (ret) return ret; } return 0; } Index: sfdp.c =================================================================== --- sfdp.c (revision 1861) +++ sfdp.c (working copy) @@ -1,9 +1,10 @@ /* * This file is part of the flashrom project. * * Copyright (C) 2011-2012 Stefan Tauner + * Copyright (C) 2014 Boris Baykov * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * @@ -15,17 +16,32 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* + * History of changes: + * 05/01/2014 Added compliance to JESD216B standard and SFDP revision 1.6 + * 07/01/2014 Modified to support SFDP revision 1.5 (for Micron flash chips) + */ + #include <stdint.h> #include <stdlib.h> #include <string.h> #include "flash.h" #include "spi.h" +#include "spi4ba.h" #include "chipdrivers.h" +/* Default four bytes addressing behavior: + 1) 4-Bytes Addressing Mode (FBA_USE_EXT_ADDR_REG_BY_DEFAULT not defined) + 2) 3-bytes mode with Ext.Addr.Register (FBA_USE_EXT_ADDR_REG_BY_DEFAULT defined) */ +/* #define FBA_USE_EXT_ADDR_REG_BY_DEFAULT 1 */ + +/* For testing purposes only. Tests JESD216B SFDP compliance without proper flash chip */ +/* #define JESD216B_SIMULATION 1 */ + static int spi_sfdp_read_sfdp_chunk(struct flashctx *flash, uint32_t address, uint8_t *buf, int len) { int i, ret; uint8_t *newbuf; const unsigned char cmd[JEDEC_SFDP_OUTSIZE] = { @@ -72,22 +88,25 @@ } return ret; } struct sfdp_tbl_hdr { - uint8_t id; + uint16_t id; uint8_t v_minor; uint8_t v_major; uint8_t len; uint32_t ptp; /* 24b pointer */ }; -static int sfdp_add_uniform_eraser(struct flashchip *chip, uint8_t opcode, uint32_t block_size) +static int sfdp_add_uniform_eraser(struct flashchip *chip, int eraser_type, uint8_t opcode, uint32_t block_size) { int i; uint32_t total_size = chip->total_size * 1024; - erasefunc_t *erasefn = spi_get_erasefn_from_opcode(opcode); + + /* choosing different eraser functions for 3-bytes and 4-bytes addressing */ + erasefunc_t *erasefn = (chip->feature_bits & FEATURE_FOUR_BYTE_ADDR) ? + spi_get_erasefn_from_opcode_4ba(opcode) : spi_get_erasefn_from_opcode(opcode); if (erasefn == NULL || total_size == 0 || block_size == 0 || total_size % block_size != 0) { msg_cdbg("%s: invalid input, please report to " "flashrom(a)flashrom.org\n", __func__); @@ -109,10 +128,11 @@ msg_cspew(" Block Eraser %d is already occupied.\n", i); continue; } + eraser->type = eraser_type; eraser->block_erase = erasefn; eraser->eraseblocks[0].size = block_size; eraser->eraseblocks[0].count = total_size/block_size; msg_cdbg2(" Block eraser %d: %d x %d B with opcode " "0x%02x\n", i, total_size/block_size, block_size, @@ -123,44 +143,110 @@ " Please report this at flashrom(a)flashrom.org\n", __func__, i); return 1; } -static int sfdp_fill_flash(struct flashchip *chip, uint8_t *buf, uint16_t len) +/* Try of replace exist erasers to new direct 4-bytes addressing erasers + which can be called from ANY addressing mode: 3-byte or 4-bytes. + These erasers opcodes defines in SFDP 4-byte address instruction table + from SFDP revision 1.6 that is defined by JESD216B standard. */ +static int sfdp_change_uniform_eraser_4ba_direct(struct flashchip *chip, int eraser_type, uint8_t opcode) +{ + int i; + erasefunc_t *erasefn = spi_get_erasefn_from_opcode_4ba_direct(opcode); + + if (erasefn == NULL) { + msg_cdbg("%s: invalid input, please report to " + "flashrom(a)flashrom.org\n", __func__); + return 1; + } + + for (i = 0; i < NUM_ERASEFUNCTIONS; i++) { + struct block_eraser *eraser = &chip->block_erasers[i]; + if (eraser->eraseblocks[0].size == 0) + break; + if (eraser->type != eraser_type) + continue; + + eraser->block_erase = erasefn; + msg_cdbg2(" Block eraser %d (type %d) changed to opcode " + "0x%02x\n", i, eraser_type, opcode); + return 0; + } + + msg_cspew("%s: Block Eraser type %d isn't found." + " Please report this at flashrom(a)flashrom.org\n", + __func__, eraser_type); + return 1; +} + +/* Parse of JEDEC SFDP Basic Flash Parameter Table */ +static int sfdp_fill_flash(struct flashchip *chip, uint8_t *buf, uint16_t len, int sfdp_rev_15) { uint8_t opcode_4k_erase = 0xFF; uint32_t tmp32; uint8_t tmp8; uint32_t total_size; /* in bytes */ uint32_t block_size; int j; msg_cdbg("Parsing JEDEC flash parameter table... "); - if (len != 9 * 4 && len != 4 * 4) { + if (len != 16 * 4 && len != 9 * 4 && len != 4 * 4) { msg_cdbg("%s: len out of spec\n", __func__); return 1; } msg_cdbg2("\n"); - + /* 1. double word */ tmp32 = ((unsigned int)buf[(4 * 0) + 0]); tmp32 |= ((unsigned int)buf[(4 * 0) + 1]) << 8; tmp32 |= ((unsigned int)buf[(4 * 0) + 2]) << 16; tmp32 |= ((unsigned int)buf[(4 * 0) + 3]) << 24; + chip->feature_bits = 0; + tmp8 = (tmp32 >> 17) & 0x3; switch (tmp8) { case 0x0: msg_cdbg2(" 3-Byte only addressing.\n"); break; case 0x1: msg_cdbg2(" 3-Byte (and optionally 4-Byte) addressing.\n"); +#ifndef FBA_USE_EXT_ADDR_REG_BY_DEFAULT + /* assuming that 4-bytes addressing mode can be entered + by CMD B7h preceded with WREN and all read, write and + erase commands will be able to receive 4-bytes address */ + chip->feature_bits |= ( FEATURE_FOUR_BYTE_ADDR | + FEATURE_NEED_ENTER_4BA_FOR_READ | + FEATURE_NEED_ENTER_4BA_FOR_WRITE | + FEATURE_NEED_ENTER_4BA_FOR_ERASE ); + chip->four_bytes_addr_funcs.enter_4ba = spi_enter_4ba_b7_we; + chip->four_bytes_addr_funcs.program_byte = spi_byte_program_4ba; + chip->four_bytes_addr_funcs.program_nbyte = spi_nbyte_program_4ba; + chip->four_bytes_addr_funcs.read_nbyte = spi_nbyte_read_4ba; +#else /* if FBA_USE_EXT_ADDR_REG_BY_DEFAULT defined */ + /* assuming that 4-bytes addressing is working using + extended address register which can be assigned + throught CMD C5h and then all commands will use + 3-bytes address as usual */ + chip->feature_bits |= ( FEATURE_FOUR_BYTE_ADDR | + FEATURE_NEED_USE_EXTENDED_ADDR_REG ); + chip->four_bytes_addr_funcs.enter_4ba = NULL; + chip->four_bytes_addr_funcs.program_byte = spi_byte_program_4ba_ereg; + chip->four_bytes_addr_funcs.program_nbyte = spi_nbyte_program_4ba_ereg; + chip->four_bytes_addr_funcs.read_nbyte = spi_nbyte_read_4ba_ereg; +#endif /* FBA_USE_EXT_ADDR_REG_BY_DEFAULT */ break; case 0x2: - msg_cdbg(" 4-Byte only addressing (not supported by " - "flashrom).\n"); - return 1; + msg_cdbg2(" 4-Byte only addressing.\n"); + chip->feature_bits |= ( FEATURE_FOUR_BYTE_ADDR | + FEATURE_FOUR_BYTE_ADDR_ONLY ); + chip->four_bytes_addr_funcs.enter_4ba = NULL; + chip->four_bytes_addr_funcs.program_byte = spi_byte_program_4ba; + chip->four_bytes_addr_funcs.program_nbyte = spi_nbyte_program_4ba; + chip->four_bytes_addr_funcs.read_nbyte = spi_nbyte_read_4ba; + break; default: msg_cdbg(" Required addressing mode (0x%x) not supported.\n", tmp8); return 1; } @@ -168,21 +254,21 @@ msg_cdbg2(" Status register is "); if (tmp32 & (1 << 3)) { msg_cdbg2("volatile and writes to the status register have to " "be enabled with "); if (tmp32 & (1 << 4)) { - chip->feature_bits = FEATURE_WRSR_WREN; + chip->feature_bits |= FEATURE_WRSR_WREN; msg_cdbg2("WREN (0x06).\n"); } else { - chip->feature_bits = FEATURE_WRSR_EWSR; + chip->feature_bits |= FEATURE_WRSR_EWSR; msg_cdbg2("EWSR (0x50).\n"); } } else { msg_cdbg2("non-volatile and the standard does not allow " "vendors to tell us whether EWSR/WREN is needed for " "status register writes - assuming EWSR.\n"); - chip->feature_bits = FEATURE_WRSR_EWSR; + chip->feature_bits |= FEATURE_WRSR_EWSR; } msg_cdbg2(" Write chunk size is "); if (tmp32 & (1 << 2)) { msg_cdbg2("at least 64 B.\n"); @@ -212,56 +298,306 @@ return 1; } total_size = ((tmp32 & 0x7FFFFFFF) + 1) / 8; chip->total_size = total_size / 1024; msg_cdbg2(" Flash chip size is %d kB.\n", chip->total_size); + if (total_size > (1 << 24)) { - msg_cdbg("Flash chip size is bigger than what 3-Byte addressing " - "can access.\n"); - return 1; + if(!sfdp_rev_15) { + msg_cdbg("Flash chip size is bigger than what 3-Byte addressing " + "can access but chip's SFDP revision is lower than 1.6 " + "(1.5).\nConsequently 4-bytes addressing can NOT be " + "properly configured using current SFDP information.\n"); +#ifndef FBA_USE_EXT_ADDR_REG_BY_DEFAULT + msg_cdbg("Assuming that 4-bytes addressing mode can be " + "entered by CMD B7h with WREN.\n"); +#else + msg_cdbg("Assuming that 4-bytes addressing is working via " + "an Extended Address Register which can be written " + "by CMD C5h.\n"); +#endif + } } - if (opcode_4k_erase != 0xFF) - sfdp_add_uniform_eraser(chip, opcode_4k_erase, 4 * 1024); - /* FIXME: double words 3-7 contain unused fast read information */ - if (len == 4 * 4) { + if (len < 9 * 4) { msg_cdbg(" It seems like this chip supports the preliminary " "Intel version of SFDP, skipping processing of double " "words 3-9.\n"); + + /* in the case if BFPT erasers array is not present + trying to add default 4k-eraser */ + if (opcode_4k_erase != 0xFF) + sfdp_add_uniform_eraser(chip, 0, opcode_4k_erase, 4 * 1024); + goto done; } - /* 8. double word */ + /* 8. double word & 9. double word */ + /* for by block eraser types, from Type 1 to Type 4 */ for (j = 0; j < 4; j++) { /* 7 double words from the start + 2 bytes for every eraser */ tmp8 = buf[(4 * 7) + (j * 2)]; - msg_cspew(" Erase Sector Type %d Size: 0x%02x\n", j + 1, - tmp8); + msg_cspew(" Erase Sector (Type %d) Size: 0x%02x\n", j + 1, tmp8); if (tmp8 == 0) { - msg_cspew(" Erase Sector Type %d is unused.\n", j); + msg_cspew(" Erase Sector (Type %d) is unused.\n", j + 1); continue; } if (tmp8 >= 31) { - msg_cdbg2(" Block size of erase Sector Type %d (2^%d) " - "is too big for flashrom.\n", j, tmp8); + msg_cdbg2(" Block size of erase Sector (Type %d): 2^%d " + "is too big for flashrom.\n", j + 1, tmp8); continue; } block_size = 1 << (tmp8); /* block_size = 2 ^ field */ tmp8 = buf[(4 * 7) + (j * 2) + 1]; - msg_cspew(" Erase Sector Type %d Opcode: 0x%02x\n", j + 1, - tmp8); - sfdp_add_uniform_eraser(chip, tmp8, block_size); + msg_cspew(" Erase Sector (Type %d) Opcode: 0x%02x\n", j + 1, tmp8); + sfdp_add_uniform_eraser(chip, j + 1, tmp8, block_size); + } + + /* Trying to adding the default 4k eraser after parsing erasers info. + In most cases this eraser has already been added before. */ + if (opcode_4k_erase != 0xFF) + sfdp_add_uniform_eraser(chip, 0, opcode_4k_erase, 4 * 1024); + + /* If the chip doesn't support 4-bytes addressing mode we don't have + to read and analyze 16th DWORD of Basic Flash Parameter Table */ + if (!(chip->feature_bits & FEATURE_FOUR_BYTE_ADDR)) + goto done; + + /* In the case if the chip is working in 4-bytes addressing mode ONLY we + don't have to read and analyze 16th DWORD of Basic Flash Parameter Table + because we don't have to know how to switch to 4-bytes mode and back + when we are already in 4-bytes mode permanently. */ + if (chip->feature_bits & FEATURE_FOUR_BYTE_ADDR_ONLY) + goto done; + + /* If the SFDP revision supported by the chip is lower that 1.6 (1.5) + we can not read and analyze 16th DWORD of Basic Flash Parameter Table. + Using defaults by FBA_USE_EXT_ADDR_REG_BY_DEFAULT define. */ + if(!sfdp_rev_15) + goto done; + + if (len < 16 * 4) { + msg_cdbg("%s: len of BFPT is out of spec\n", __func__); + msg_cerr("ERROR: Unable read 4-bytes addressing parameters.\n"); + return 1; + } + + /* 11. double word */ + tmp8 = buf[(4*10) + 0] >> 4; /* get upper nibble of LSB of 11th dword */ + chip->page_size = 1 << tmp8; /* page_size = 2 ^ N */ + msg_cdbg2(" Page size is %d B.\n", chip->page_size); + + /* 16. double word */ + tmp32 = ((unsigned int)buf[(4 * 15) + 0]); + tmp32 |= ((unsigned int)buf[(4 * 15) + 1]) << 8; + tmp32 |= ((unsigned int)buf[(4 * 15) + 2]) << 16; + tmp32 |= ((unsigned int)buf[(4 * 15) + 3]) << 24; + + /* Parsing 16th DWORD of Basic Flash Parameter Table according to JESD216B */ + + if(tmp32 & JEDEC_BFPT_DW16_ENTER_B7) { + msg_cdbg2(" Enter 4-bytes addressing mode by CMD B7h\n"); + chip->four_bytes_addr_funcs.enter_4ba = spi_enter_4ba_b7; + chip->four_bytes_addr_funcs.program_byte = spi_byte_program_4ba; + chip->four_bytes_addr_funcs.program_nbyte = spi_nbyte_program_4ba; + chip->four_bytes_addr_funcs.read_nbyte = spi_nbyte_read_4ba; + chip->feature_bits &= ~FEATURE_ENTER_4BA_ALL; // clear defaults + chip->feature_bits |= ( FEATURE_NEED_ENTER_4BA_FOR_READ | + FEATURE_NEED_ENTER_4BA_FOR_WRITE | + FEATURE_NEED_ENTER_4BA_FOR_ERASE ); + } + else if(tmp32 & JEDEC_BFPT_DW16_ENTER_B7_WE) { + msg_cdbg2(" Enter 4-bytes addressing mode by CMD B7h with WREN\n"); + chip->four_bytes_addr_funcs.enter_4ba = spi_enter_4ba_b7_we; + chip->four_bytes_addr_funcs.program_byte = spi_byte_program_4ba; + chip->four_bytes_addr_funcs.program_nbyte = spi_nbyte_program_4ba; + chip->four_bytes_addr_funcs.read_nbyte = spi_nbyte_read_4ba; + chip->feature_bits &= ~FEATURE_ENTER_4BA_ALL; // clear defaults + chip->feature_bits |= ( FEATURE_NEED_ENTER_4BA_FOR_READ | + FEATURE_NEED_ENTER_4BA_FOR_WRITE | + FEATURE_NEED_ENTER_4BA_FOR_ERASE ); + } + else if(tmp32 & JEDEC_BFPT_DW16_ENTER_EXTENDED_ADDR_REG) { + msg_cdbg2(" Extended Address Register used for 4-bytes addressing\n"); + chip->four_bytes_addr_funcs.program_byte = spi_byte_program_4ba_ereg; + chip->four_bytes_addr_funcs.program_nbyte = spi_nbyte_program_4ba_ereg; + chip->four_bytes_addr_funcs.read_nbyte = spi_nbyte_read_4ba_ereg; + chip->feature_bits &= ~FEATURE_ENTER_4BA_ALL; // clear defaults + /* this flag signals to all '*_selector' functions + to use Ext.Addr.Reg while erase operations */ + chip->feature_bits |= FEATURE_NEED_USE_EXTENDED_ADDR_REG; + } + else { + msg_cerr("ERROR: Unable to use 4-bytes addressing for this chip.\n" + " Please report this at flashrom(a)flashrom.org\n\n"); + return 1; } done: msg_cdbg("done.\n"); return 0; } +/* Parse of JEDEC SFDP 4-byte address instruction table. From SFDP revision 1.6 only. + This parsing shoukd be called after basic flash parameter table is parsed. */ +static int sfdp_parse_4ba_table(struct flashchip *chip, uint8_t *buf, uint16_t len) +{ + uint32_t tmp32; + uint8_t tmp8; + int j, direct_erasers; + int direct_count; + + msg_cdbg("Parsing JEDEC 4-byte address instuction table... "); + if (len != 2 * 4) { + msg_cdbg("%s: len out of spec\n", __func__); + return 1; + } + msg_cdbg2("\n"); + + /* 1. double word */ + tmp32 = ((unsigned int)buf[(4 * 0) + 0]); + tmp32 |= ((unsigned int)buf[(4 * 0) + 1]) << 8; + tmp32 |= ((unsigned int)buf[(4 * 0) + 2]) << 16; + tmp32 |= ((unsigned int)buf[(4 * 0) + 3]) << 24; + + direct_count = 0; + + if(tmp32 & JEDEC_4BAIT_READ_SUPPORT) { + msg_cdbg2(" Found Read CMD 13h with 4-bytes address\n"); + chip->four_bytes_addr_funcs.read_nbyte = spi_nbyte_read_4ba_direct; + /* read function has changed to direct 4-bytes function, + so entering 4-bytes mode isn't required for reading bytes */ + chip->feature_bits &= ~FEATURE_NEED_ENTER_4BA_FOR_READ; + direct_count++; + } + + if(tmp32 & JEDEC_4BAIT_PROGRAM_SUPPORT) { + msg_cdbg2(" Found Write CMD 12h with 4-bytes address\n"); + chip->four_bytes_addr_funcs.program_byte = spi_byte_program_4ba_direct; + chip->four_bytes_addr_funcs.program_nbyte = spi_nbyte_program_4ba_direct; + /* write (program) functions have changed to direct 4-bytes functions, + so entering 4-bytes mode isn't required for writing bytes */ + chip->feature_bits &= ~FEATURE_NEED_ENTER_4BA_FOR_WRITE; + direct_count++; + } + + direct_erasers = 0; + + /* 2. double word */ + for (j = 0; j < 4; j++) { + if(!(tmp32 & (JEDEC_4BAIT_ERASE_TYPE_1_SUPPORT << j))) + continue; + + tmp8 = buf[(4 * 1) + j]; + + msg_cdbg2(" Found Erase (type %d) CMD %02Xh with 4-bytes address\n", j + 1, tmp8); + + if(tmp8 == 0xFF) { + msg_cdbg("%s: Eraser (type %d) is supported, but opcode = 0xFF\n" + " Please report to flashrom(a)flashrom.org\n\n", __func__, j + 1); + continue; + } + + /* try of replacing the eraser with direct 4-bytes eraser */ + if(!sfdp_change_uniform_eraser_4ba_direct(chip, j + 1, tmp8)) + direct_erasers++; + } + + for (j = 0; j < NUM_ERASEFUNCTIONS; j++) { + if (chip->block_erasers[j].eraseblocks[0].size == 0) + break; + } + + if( j == direct_erasers ) { + /* if all erasers have been changed to direct 4-bytes ones, + then we don't have to enter 4-bytes mode for erase */ + chip->feature_bits &= ~FEATURE_NEED_ENTER_4BA_FOR_ERASE; + direct_count++; + msg_cspew("All erasers have changed to direct ones.\n"); + } + + if( direct_count == 3 ) { + /* if all read/write/erase functions are direct 4-bytes now, + then we don't have to use extended address register */ + chip->feature_bits &= ~FEATURE_NEED_USE_EXTENDED_ADDR_REG; + msg_cspew("All read/write/erase functions have changed to direct ones.\n"); + } + + msg_cdbg("done.\n"); + return 0; +} + +#ifdef JESD216B_SIMULATION +/* This simulation increases size of Basic Flash Parameter Table + to have 16 dwords size and fills 16th dword with fake information + that is required to test JESD216B compliance. */ +int sfdp_jesd216b_simulation_dw16(uint8_t** ptbuf, uint16_t* plen) +{ + uint8_t* tbufsim; + uint16_t lensim = 16 * 4; + + tbufsim = malloc(lensim); + if (tbufsim == NULL) { + msg_gerr("Out of memory!\n"); + return 1; + } + + msg_cdbg("\n=== SIMULATION of JESD216B 16th Dword of Basic Flash Parameter Table\n"); + + memset(tbufsim, 0, 16 * 4); + memcpy(tbufsim, *ptbuf, min(*plen, 15 * 4)); + + tbufsim[(4*10) + 0] = 8 << 4; /* page size = 256 */ + + *((uint32_t*)&tbufsim[15 * 4]) = /*JEDEC_BFPT_DW16_ENTER_B7 | */ + JEDEC_BFPT_DW16_ENTER_B7_WE | + JEDEC_BFPT_DW16_ENTER_EXTENDED_ADDR_REG /* | + JEDEC_BFPT_DW16_ENTER_BANK_ADDR_REG_EN_BIT | + JEDEC_BFPT_DW16_ENTER_NV_CONFIG_REG | + JEDEC_BFPT_DW16_VENDOR_SET | + JEDEC_BFPT_DW16_4_BYTES_ADDRESS_ONLY */ ; + + free(*ptbuf); + *ptbuf = tbufsim; + *plen = lensim; + return 0; +} + +/* This simulation created fake 4-bytes Address Instruction Table + with features information to test JESD216B compliance. */ +int sfdp_jesd216b_simulation_4bait(uint8_t** ptbuf, uint16_t* plen) +{ + uint8_t* tbufsim; + uint16_t lensim = 2 * 4; + + tbufsim = malloc(lensim); + if (tbufsim == NULL) { + msg_gerr("Out of memory!\n"); + return 1; + } + + msg_cdbg("\n=== SIMULATION of JESD216B 4-bytes Address Instruction Table\n"); + + *((uint32_t*)&tbufsim[0]) = JEDEC_4BAIT_READ_SUPPORT /*| + JEDEC_4BAIT_PROGRAM_SUPPORT | + JEDEC_4BAIT_ERASE_TYPE_1_SUPPORT | + JEDEC_4BAIT_ERASE_TYPE_2_SUPPORT | + JEDEC_4BAIT_ERASE_TYPE_3_SUPPORT | + JEDEC_4BAIT_ERASE_TYPE_4_SUPPORT */; + *((uint32_t*)&tbufsim[4]) = 0xFFFFFFFF; + /* *((uint32_t*)&tbufsim[4]) = 0xFFDC5C21; */ + + free(*ptbuf); + *ptbuf = tbufsim; + *plen = lensim; + return 0; +} +#endif + int probe_spi_sfdp(struct flashctx *flash) { int ret = 0; uint8_t buf[8]; uint32_t tmp32; @@ -269,10 +605,11 @@ /* need to limit the table loop by comparing i to uint8_t nph hence: */ uint16_t i; struct sfdp_tbl_hdr *hdrs; uint8_t *hbuf; uint8_t *tbuf; + int sfdp_rev_16 = 0, sfdp_rev_15 = 0; if (spi_sfdp_read_sfdp(flash, 0x00, buf, 4)) { msg_cdbg("Receiving SFDP signature failed.\n"); return 0; } @@ -296,10 +633,36 @@ if (buf[1] != 0x01) { msg_cdbg("The chip supports an unknown version of SFDP. " "Aborting SFDP probe!\n"); return 0; } + + /* JEDEC JESD216B defines SFDP revision 1.6 and includes: + 1) 16 dwords in Basic Flash Parameter Table + 2) 16th dword has information how to enter + and exit 4-bytes addressing mode + 3) 4-Bytes Address Instruction Table with ID 0xFF84 + + However we can see in the datasheet for Micron's + MT25Q 512Mb chip (MT25QL512AB/MT25QU512AB) that the + chip returnes SFDP revision 1.5 and has 16 dwords + in its Basic Flash Paramater Table. Also the information + about addressing mode switch is exist in the 16th dword. + But 4-Bytes Address Instruction Table is absent. + + So we will use 16th dword from SFDP revision 1.5 + but 4-Bytes Address Instruction Table from SFDP 1.6 only. + This assumption is made for better support of Micron + flash chips. + + FIXME: SFDP revisions compliance should be checked + more carefully after more information about JESD216B + SFDP tables will be known from real flash chips. + */ + sfdp_rev_16 = (buf[1] == 1 && buf[0] >= 6) || buf[1] > 1; + sfdp_rev_15 = (buf[1] == 1 && buf[0] >= 5) || buf[1] > 1; + nph = buf[2]; msg_cdbg2("SFDP number of parameter headers is %d (NPH = %d).\n", nph + 1, nph); /* Fetch all parameter headers, even if we don't use them all (yet). */ @@ -314,17 +677,18 @@ goto cleanup_hdrs; } for (i = 0; i <= nph; i++) { uint16_t len; - hdrs[i].id = hbuf[(8 * i) + 0]; + hdrs[i].id = hbuf[(8 * i) + 0]; /* ID LSB read */ hdrs[i].v_minor = hbuf[(8 * i) + 1]; hdrs[i].v_major = hbuf[(8 * i) + 2]; hdrs[i].len = hbuf[(8 * i) + 3]; hdrs[i].ptp = hbuf[(8 * i) + 4]; hdrs[i].ptp |= ((unsigned int)hbuf[(8 * i) + 5]) << 8; hdrs[i].ptp |= ((unsigned int)hbuf[(8 * i) + 6]) << 16; + hdrs[i].id |= ((uint16_t)hbuf[(8 * i) + 7]) << 8; /* ID MSB read */ msg_cdbg2("\nSFDP parameter table header %d/%d:\n", i, nph); msg_cdbg2(" ID 0x%02x, version %d.%d\n", hdrs[i].id, hdrs[i].v_major, hdrs[i].v_minor); len = hdrs[i].len * 4; tmp32 = hdrs[i].ptp; @@ -366,29 +730,51 @@ } } msg_cspew("\n"); if (i == 0) { /* Mandatory JEDEC SFDP parameter table */ - if (hdrs[i].id != 0) + if (hdrs[i].id != JEDEC_BFPT_ID) msg_cdbg("ID of the mandatory JEDEC SFDP " - "parameter table is not 0 as demanded " - "by JESD216 (warning only).\n"); - + "parameter table is not 0xFF00 as" + "demanded by JESD216 (warning only)." + "\n"); +#ifdef JESD216B_SIMULATION + if(!sfdp_jesd216b_simulation_dw16(&tbuf, &len)) + sfdp_rev_16 = sfdp_rev_15 = 1; /* pretend as SFDP rev 1.6 */ +#endif if (hdrs[i].v_major != 0x01) { msg_cdbg("The chip contains an unknown " "version of the JEDEC flash " "parameters table, skipping it.\n"); - } else if (len != 9 * 4 && len != 4 * 4) { + } else if (len != 16 * 4 && len != 9 * 4 && len != 4 * 4) { msg_cdbg("Length of the mandatory JEDEC SFDP " "parameter table is wrong (%d B), " "skipping it.\n", len); - } else if (sfdp_fill_flash(flash->chip, tbuf, len) == 0) + } else if (sfdp_fill_flash(flash->chip, tbuf, len, sfdp_rev_15) == 0) ret = 1; +#ifdef JESD216B_SIMULATION + if(ret == 1 && !sfdp_jesd216b_simulation_4bait(&tbuf, &len)) + sfdp_parse_4ba_table(flash->chip, tbuf, len); +#endif + } + /* JEDEC SFDP 4-byte address instruction table. From SFDP revision 1.6 only. + This parsing shoukd be called after basic flash parameter table is parsed. */ + else if(sfdp_rev_16 && hdrs[i].id == JEDEC_4BAIT_ID && ret == 1) { + if (hdrs[i].v_major != 0x01) { + msg_cdbg("The chip contains an unknown " + "version of the JEDEC 4-bytes " + "address instruction table, " + "skipping it.\n"); + } + else { /* no result check because this table is optional */ + sfdp_parse_4ba_table(flash->chip, tbuf, len); + } } free(tbuf); } cleanup_hdrs: free(hdrs); free(hbuf); return ret; } + Index: spi.c =================================================================== --- spi.c (revision 1861) +++ spi.c (working copy) @@ -108,11 +108,14 @@ /* Check if the chip fits between lowest valid and highest possible * address. Highest possible address with the current SPI implementation * means 0xffffff, the highest unsigned 24bit number. */ addrbase = spi_get_valid_read_addr(flash); - if (addrbase + flash->chip->total_size * 1024 > (1 << 24)) { + /* Show flash chip size warning if flash chip doesn't support + 4-Bytes Addressing mode and last address excedes 24 bits */ + if (!(flash->chip->feature_bits & FEATURE_FOUR_BYTE_ADDR) && + addrbase + flash->chip->total_size * 1024 > (1 << 24)) { msg_perr("Flash chip size exceeds the allowed access window. "); msg_perr("Read will probably fail.\n"); /* Try to get the best alignment subject to constraints. */ addrbase = (1 << 24) - flash->chip->total_size * 1024; } Index: spi25.c =================================================================== --- spi25.c (revision 1861) +++ spi25.c (working copy) @@ -26,10 +26,11 @@ #include "flash.h" #include "flashchips.h" #include "chipdrivers.h" #include "programmer.h" #include "spi.h" +#include "spi4ba.h" static int spi_rdid(struct flashctx *flash, unsigned char *readarr, int bytes) { static const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID }; int ret; @@ -946,10 +947,20 @@ unsigned int len, unsigned int chunksize) { int rc = 0; unsigned int i, j, starthere, lenhere, toread; unsigned int page_size = flash->chip->page_size; + int show_progress = 0; + unsigned int percent_last, percent_current; + + /* progress visualizaion init */ + if(len >= MIN_LENGTH_TO_SHOW_READ_PROGRESS) { + msg_cinfo(" "); /* only this space will go to logfile but all strings with \b wont. */ + msg_cinfo("\b 0%%"); + percent_last = percent_current = 0; + show_progress = 1; /* enable progress visualizaion */ + } /* Warning: This loop has a very unusual condition and body. * The loop needs to go through each page with at least one affected * byte. The lowest page number is (start / page_size) since that * division rounds down. The highest page number we want is the page @@ -964,18 +975,33 @@ starthere = max(start, i * page_size); /* Length of bytes in the range in this page. */ lenhere = min(start + len, (i + 1) * page_size) - starthere; for (j = 0; j < lenhere; j += chunksize) { toread = min(chunksize, lenhere - j); - rc = spi_nbyte_read(flash, starthere + j, buf + starthere - start + j, toread); + rc = (flash->chip->feature_bits & FEATURE_FOUR_BYTE_ADDR) == 0 + ? spi_nbyte_read(flash, starthere + j, buf + starthere - start + j, toread) + : flash->chip->four_bytes_addr_funcs.read_nbyte(flash, starthere + j, + buf + starthere - start + j, toread); if (rc) break; } if (rc) break; + + if(show_progress) { + percent_current = (unsigned int) ((unsigned long long)(starthere + + lenhere - start) * 100 / len); + if(percent_current != percent_last) { + msg_cinfo("\b\b\b%2d%%", percent_current); + percent_last = percent_current; + } + } } + if(show_progress && !rc) + msg_cinfo("\b\b\b\b"); /* remove progress percents from the screen */ + return rc; } /* * Write a part of the flash chip. @@ -1009,11 +1035,14 @@ starthere = max(start, i * page_size); /* Length of bytes in the range in this page. */ lenhere = min(start + len, (i + 1) * page_size) - starthere; for (j = 0; j < lenhere; j += chunksize) { towrite = min(chunksize, lenhere - j); - rc = spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite); + rc = (flash->chip->feature_bits & FEATURE_FOUR_BYTE_ADDR) == 0 + ? spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite) + : flash->chip->four_bytes_addr_funcs.program_nbyte(flash, starthere + j, + buf + starthere - start + j, towrite); if (rc) break; while (spi_read_status_register(flash) & SPI_SR_WIP) programmer_delay(10); } @@ -1035,11 +1064,13 @@ { unsigned int i; int result = 0; for (i = start; i < start + len; i++) { - result = spi_byte_program(flash, i, buf[i - start]); + result = (flash->chip->feature_bits & FEATURE_FOUR_BYTE_ADDR) == 0 + ? spi_byte_program(flash, i, buf[i - start]) + : flash->chip->four_bytes_addr_funcs.program_byte(flash, i, buf[i - start]); if (result) return 1; while (spi_read_status_register(flash) & SPI_SR_WIP) programmer_delay(10); } Index: spi4ba.c =================================================================== --- spi4ba.c (revision 0) +++ spi4ba.c (working copy) @@ -0,0 +1,1020 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2014 Boris Baykov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * SPI chip driver functions for 4-bytes addressing + */ + +#include <string.h> +#include "flash.h" +#include "chipdrivers.h" +#include "spi.h" +#include "programmer.h" +#include "spi4ba.h" + +/* #define MSG_TRACE_4BA_FUNCS 1 */ + +#ifdef MSG_TRACE_4BA_FUNCS +#define msg_trace(...) print(MSG_DEBUG, __VA_ARGS__) +#else +#define msg_trace(...) +#endif + +/* Enter 4-bytes addressing mode (without sending WREN before) */ +int spi_enter_4ba_b7(struct flashctx *flash) +{ + const unsigned char cmd[JEDEC_ENTER_4_BYTE_ADDR_MODE_OUTSIZE] = { JEDEC_ENTER_4_BYTE_ADDR_MODE }; + + msg_trace("-> %s\n", __func__); + + /* Switch to 4-bytes addressing mode */ + return spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); +} + +/* Enter 4-bytes addressing mode with sending WREN before */ +int spi_enter_4ba_b7_we(struct flashctx *flash) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_ENTER_4_BYTE_ADDR_MODE_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_ENTER_4_BYTE_ADDR_MODE }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s\n", __func__); + + /* Switch to 4-bytes addressing mode */ + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution\n", __func__); + } + return result; +} + +/* Write Extended Address Register value */ +int spi_write_extended_address_register(struct flashctx *flash, uint8_t regdata) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_WRITE_EXT_ADDR_REG_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_WRITE_EXT_ADDR_REG, + regdata + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (%02X)\n", __func__, regdata); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution\n", __func__); + return result; + } + return 0; +} + +/* Assign required value of Extended Address Register. This function + keeps last value of the register and writes the register if the + value has to be changed only. */ +int set_extended_address_register(struct flashctx *flash, uint8_t data) +{ + static uint8_t ext_addr_reg_state; /* memory for last register state */ + static int ext_addr_reg_state_valid = 0; + int result; + + if (ext_addr_reg_state_valid == 0 || data != ext_addr_reg_state) { + result = spi_write_extended_address_register(flash, data); + if (result) { + ext_addr_reg_state_valid = 0; + return result; + } + ext_addr_reg_state = data; + ext_addr_reg_state_valid = 1; + } + return 0; +} + +/* Program one flash byte from 4-bytes addressing mode */ +int spi_byte_program_4ba(struct flashctx *flash, unsigned int addr, + uint8_t databyte) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE + 1, + .writearr = (const unsigned char[]){ + JEDEC_BYTE_PROGRAM, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff), + databyte + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X)\n", __func__, addr); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + } + return result; +} + +/* Program flash bytes from 4-bytes addressing mode */ +int spi_nbyte_program_4ba(struct flashctx *flash, unsigned int addr, + const uint8_t *bytes, unsigned int len) +{ + int result; + unsigned char cmd[(JEDEC_BYTE_PROGRAM_OUTSIZE + 1) - 1 + 256] = { + JEDEC_BYTE_PROGRAM, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr >> 0) & 0xff + }; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = (JEDEC_BYTE_PROGRAM_OUTSIZE + 1) - 1 + len, + .writearr = cmd, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); + + if (!len) { + msg_cerr("%s called for zero-length write\n", __func__); + return 1; + } + if (len > 256) { + msg_cerr("%s called for too long a write\n", __func__); + return 1; + } + + memcpy(&cmd[(JEDEC_BYTE_PROGRAM_OUTSIZE + 1) - 1], bytes, len); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + } + return result; +} + +/* Read flash bytes from 4-bytes addressing mode */ +int spi_nbyte_read_4ba(struct flashctx *flash, unsigned int addr, + uint8_t *bytes, unsigned int len) +{ + const unsigned char cmd[JEDEC_READ_OUTSIZE + 1] = { + JEDEC_READ, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr >> 0) & 0xff + }; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); + + /* Send Read */ + return spi_send_command(flash, sizeof(cmd), len, cmd, bytes); +} + +/* Program one flash byte with 4-bytes address from ANY mode (3-bytes or 4-bytes) + JEDEC_BYTE_PROGRAM_4BA (12h) instruction is new for 4-bytes addressing flash chips. + The presence of this instruction for an exact chip should be checked + by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */ +int spi_byte_program_4ba_direct(struct flashctx *flash, unsigned int addr, + uint8_t databyte) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_4BA_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BYTE_PROGRAM_4BA, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff), + databyte + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X)\n", __func__, addr); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + } + return result; +} + +/* Program flash bytes with 4-bytes address from ANY mode (3-bytes or 4-bytes) + JEDEC_BYTE_PROGRAM_4BA (12h) instruction is new for 4-bytes addressing flash chips. + The presence of this instruction for an exact chip should be checked + by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */ +int spi_nbyte_program_4ba_direct(struct flashctx *flash, unsigned int addr, + const uint8_t *bytes, unsigned int len) +{ + int result; + unsigned char cmd[JEDEC_BYTE_PROGRAM_4BA_OUTSIZE - 1 + 256] = { + JEDEC_BYTE_PROGRAM_4BA, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr >> 0) & 0xff + }; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_4BA_OUTSIZE - 1 + len, + .writearr = cmd, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); + + if (!len) { + msg_cerr("%s called for zero-length write\n", __func__); + return 1; + } + if (len > 256) { + msg_cerr("%s called for too long a write\n", __func__); + return 1; + } + + memcpy(&cmd[JEDEC_BYTE_PROGRAM_4BA_OUTSIZE - 1], bytes, len); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + } + return result; +} + +/* Read flash bytes with 4-bytes address from ANY mode (3-bytes or 4-bytes) + JEDEC_READ_4BA (13h) instruction is new for 4-bytes addressing flash chips. + The presence of this instruction for an exact chip should be checked + by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */ +int spi_nbyte_read_4ba_direct(struct flashctx *flash, unsigned int addr, + uint8_t *bytes, unsigned int len) +{ + const unsigned char cmd[JEDEC_READ_4BA_OUTSIZE] = { + JEDEC_READ_4BA, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr >> 0) & 0xff + }; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); + + /* Send Read */ + return spi_send_command(flash, sizeof(cmd), len, cmd, bytes); +} + +/* Program one flash byte using Extended Address Register + from 3-bytes addressing mode */ +int spi_byte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, + uint8_t databyte) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BYTE_PROGRAM, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff), + databyte + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X)\n", __func__, addr); + + result = set_extended_address_register(flash, (addr >> 24) & 0xff); + if (result) + return result; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + } + return result; +} + +/* Program flash bytes using Extended Address Register + from 3-bytes addressing mode */ +int spi_nbyte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, + const uint8_t *bytes, unsigned int len) +{ + int result; + unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = { + JEDEC_BYTE_PROGRAM, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr >> 0) & 0xff + }; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + len, + .writearr = cmd, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); + + if (!len) { + msg_cerr("%s called for zero-length write\n", __func__); + return 1; + } + if (len > 256) { + msg_cerr("%s called for too long a write\n", __func__); + return 1; + } + + memcpy(&cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1], bytes, len); + + result = set_extended_address_register(flash, (addr >> 24) & 0xff); + if (result) + return result; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + } + return result; +} + +/* Read flash bytes using Extended Address Register + from 3-bytes addressing mode */ +int spi_nbyte_read_4ba_ereg(struct flashctx *flash, unsigned int addr, + uint8_t *bytes, unsigned int len) +{ + int result; + const unsigned char cmd[JEDEC_READ_OUTSIZE] = { + JEDEC_READ, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr >> 0) & 0xff + }; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); + + result = set_extended_address_register(flash, (addr >> 24) & 0xff); + if (result) + return result; + + /* Send Read */ + return spi_send_command(flash, sizeof(cmd), len, cmd, bytes); +} + +/* Chooser for erase function by instruction opcode for block eraser instructions + to work with 4-bytes addressing flash chips. This chooser is called from sfdp.c + during parse of 8th & 9th dwords of SFDP Basic Flash Parameter Table */ +erasefunc_t *spi_get_erasefn_from_opcode_4ba(uint8_t opcode) +{ + msg_trace("-> %s\n", __func__); + + switch(opcode){ + case 0xff: + case 0x00: + /* Not specified, assuming "not supported". */ + return NULL; + case 0x20: + return &spi_block_erase_20_4ba_selector; /* selector */ + case 0x52: + return &spi_block_erase_52_4ba_selector; /* selector */ + case 0x60: + return &spi_block_erase_60; + case 0x62: + return &spi_block_erase_62; + case 0xc7: + return &spi_block_erase_c7; + case 0xd8: + return &spi_block_erase_d8_4ba_selector; /* selector */ + case 0x50: + case 0x81: + case 0xc4: + case 0xd7: + case 0xdb: + msg_cinfo("%s: erase opcode (0x%02x) doesn't have its 4-bytes addressing version." + " Please report this at flashrom(a)flashrom.org\n", __func__, opcode); + return NULL; + default: + msg_cinfo("%s: unknown erase opcode (0x%02x). Please report " + "this at flashrom(a)flashrom.org\n", __func__, opcode); + return NULL; + } +} + +/* Selector for 4k eraser that chooses between 4-bytes addressing mode + and use of Extended Address Register from 3-bytes addressing mode */ +int spi_block_erase_20_4ba_selector(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + msg_trace("-> %s\n", __func__); + + return (flash->chip->feature_bits & FEATURE_NEED_USE_EXTENDED_ADDR_REG) ? + spi_block_erase_20_4ba_ereg(flash, addr, blocklen) : + spi_block_erase_20_4ba(flash, addr, blocklen); +} + +/* Erases 4 KB of flash from 4-bytes addressing mode */ +int spi_block_erase_20_4ba(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_SE_OUTSIZE + 1, + .writearr = (const unsigned char[]){ + JEDEC_SE, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 15-800 ms, so wait in 10 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(10 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Selector for 32k eraser that chooses between 4-bytes addressing mode + and use of Extended Address Register from 3-bytes addressing mode */ +int spi_block_erase_52_4ba_selector(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + msg_trace("-> %s\n", __func__); + + return (flash->chip->feature_bits & FEATURE_NEED_USE_EXTENDED_ADDR_REG) ? + spi_block_erase_52_4ba_ereg(flash, addr, blocklen) : + spi_block_erase_52_4ba(flash, addr, blocklen); +} + +/* Erases 32 KB of flash from 4-bytes addressing mode */ +int spi_block_erase_52_4ba(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_52_OUTSIZE + 1, + .writearr = (const unsigned char[]){ + JEDEC_BE_52, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(100 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Selector for 64k eraser that chooses between 4-bytes addressing mode + and use of Extended Address Register from 3-bytes addressing mode */ +int spi_block_erase_d8_4ba_selector(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + msg_trace("-> %s\n", __func__); + + return (flash->chip->feature_bits & FEATURE_NEED_USE_EXTENDED_ADDR_REG) ? + spi_block_erase_d8_4ba_ereg(flash, addr, blocklen) : + spi_block_erase_d8_4ba(flash, addr, blocklen); +} + +/* Erases 64 KB of flash from 4-bytes addressing mode */ +int spi_block_erase_d8_4ba(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_D8_OUTSIZE + 1, + .writearr = (const unsigned char[]){ + JEDEC_BE_D8, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(100 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Erases 4 KB of flash using Extended Address Register + from 3-bytes addressing mode */ +int spi_block_erase_20_4ba_ereg(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_SE_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_SE, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = set_extended_address_register(flash, (addr >> 24) & 0xff); + if (result) + return result; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 15-800 ms, so wait in 10 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(10 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Erases 32 KB of flash using Extended Address Register + from 3-bytes addressing mode */ +int spi_block_erase_52_4ba_ereg(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_52_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BE_52, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = set_extended_address_register(flash, (addr >> 24) & 0xff); + if (result) + return result; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(100 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Erases 64 KB of flash using Extended Address Register + from 3-bytes addressing mode */ +int spi_block_erase_d8_4ba_ereg(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_D8_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BE_D8, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = set_extended_address_register(flash, (addr >> 24) & 0xff); + if (result) + return result; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(100 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Chooser for erase function by instruction opcode for block eraser instructions + which can be used from ANY mode (3-bytes or 4-bytes). This chooser is called + from sfdp.c during parse of SFDP 4-Bytes Address Instruction Table (JESD216B) */ +erasefunc_t *spi_get_erasefn_from_opcode_4ba_direct(uint8_t opcode) +{ + msg_trace("-> %s\n", __func__); + + switch(opcode){ + case 0xff: + case 0x00: + /* Not specified, assuming "not supported". */ + return NULL; + case 0x21: + return &spi_block_erase_21_4ba_direct; /* direct */ + case 0x5C: + return &spi_block_erase_5c_4ba_direct; /* direct */ + case 0xdc: + return &spi_block_erase_dc_4ba_direct; /* direct */ + default: + msg_cinfo("%s: unknown erase opcode (0x%02x). Please report " + "this at flashrom(a)flashrom.org\n", __func__, opcode); + return NULL; + } +} + +/* Erase 4 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) + JEDEC_SE_4BA (21h) instruction is new for 4-bytes addressing flash chips. + The presence of this instruction for an exact chip should be checked + by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */ +int spi_block_erase_21_4ba_direct(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_SE_4BA_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_SE_4BA, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 15-800 ms, so wait in 10 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(10 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Erase 32 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) + JEDEC_BE_5C_4BA (5Ch) instruction is new for 4-bytes addressing flash chips. + The presence of this instruction for an exact chip should be checked + by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */ +int spi_block_erase_5c_4ba_direct(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_5C_4BA_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BE_5C_4BA, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(100 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Erase 64 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) + JEDEC_BE_DC_4BA (DCh) instruction is new for 4-bytes addressing flash chips. + The presence of this instruction for an exact chip should be checked + by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */ +int spi_block_erase_dc_4ba_direct(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_DC_4BA_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BE_DC_4BA, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(100 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} Property changes on: spi4ba.c ___________________________________________________________________ Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: spi4ba.h =================================================================== --- spi4ba.h (revision 0) +++ spi4ba.h (working copy) @@ -0,0 +1,158 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2014 Boris Baykov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +/* + * JEDEC flash chips instructions for 4-bytes addressing + * SPI chip driver functions for 4-bytes addressing + */ + +#ifndef __SPI_4BA_H__ +#define __SPI_4BA_H__ 1 + +/* Read the memory with 4-byte address + From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ +#define JEDEC_READ_4BA 0x13 +#define JEDEC_READ_4BA_OUTSIZE 0x05 +/* JEDEC_READ_4BA_INSIZE : any length */ + +/* Write memory byte with 4-byte address + From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ +#define JEDEC_BYTE_PROGRAM_4BA 0x12 +#define JEDEC_BYTE_PROGRAM_4BA_OUTSIZE 0x06 +#define JEDEC_BYTE_PROGRAM_4BA_INSIZE 0x00 + +/* Sector Erase 0x21 (with 4-byte address), usually 4k size. + From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ +#define JEDEC_SE_4BA 0x21 +#define JEDEC_SE_4BA_OUTSIZE 0x05 +#define JEDEC_SE_4BA_INSIZE 0x00 + +/* Block Erase 0x5C (with 4-byte address), usually 32k size. + From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ +#define JEDEC_BE_5C_4BA 0x5C +#define JEDEC_BE_5C_4BA_OUTSIZE 0x05 +#define JEDEC_BE_5C_4BA_INSIZE 0x00 + +/* Block Erase 0xDC (with 4-byte address), usually 64k size. + From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ +#define JEDEC_BE_DC_4BA 0xdc +#define JEDEC_BE_DC_4BA_OUTSIZE 0x05 +#define JEDEC_BE_DC_4BA_INSIZE 0x00 + +/* Enter 4-byte Address Mode */ +#define JEDEC_ENTER_4_BYTE_ADDR_MODE 0xB7 +#define JEDEC_ENTER_4_BYTE_ADDR_MODE_OUTSIZE 0x01 +#define JEDEC_ENTER_4_BYTE_ADDR_MODE_INSIZE 0x00 + +/* Exit 4-byte Address Mode */ +#define JEDEC_EXIT_4_BYTE_ADDR_MODE 0xE9 +#define JEDEC_EXIT_4_BYTE_ADDR_MODE_OUTSIZE 0x01 +#define JEDEC_EXIT_4_BYTE_ADDR_MODE_INSIZE 0x00 + +/* Write Extended Address Register */ +#define JEDEC_WRITE_EXT_ADDR_REG 0xC5 +#define JEDEC_WRITE_EXT_ADDR_REG_OUTSIZE 0x02 +#define JEDEC_WRITE_EXT_ADDR_REG_INSIZE 0x00 + +/* Read Extended Address Register */ +#define JEDEC_READ_EXT_ADDR_REG 0xC8 +#define JEDEC_READ_EXT_ADDR_REG_OUTSIZE 0x01 +#define JEDEC_READ_EXT_ADDR_REG_INSIZE 0x01 + + +/* JEDEC Basic Flash Parameters Table definition */ +#define JEDEC_BFPT_ID 0xFF00 + +/* JEDEC Basic Flash Parameters Table 16th dword according to JESD216B */ +/* 16th dword of BFPT, bits 24:31 (Enter 4-Byte Addressing) */ +#define JEDEC_BFPT_DW16_ENTER_B7 (1UL << 24) +#define JEDEC_BFPT_DW16_ENTER_B7_WE (1UL << 25) +#define JEDEC_BFPT_DW16_ENTER_EXTENDED_ADDR_REG (1UL << 26) +#define JEDEC_BFPT_DW16_ENTER_BANK_ADDR_REG_EN_BIT (1UL << 27) +#define JEDEC_BFPT_DW16_ENTER_NV_CONFIG_REG (1UL << 28) +#define JEDEC_BFPT_DW16_VENDOR_SET (1UL << 29) +#define JEDEC_BFPT_DW16_4_BYTES_ADDRESS_ONLY (1UL << 30) +#define JEDEC_BFPT_DW16_ENTER_RESERVED (1UL << 31) +/* 16th dword of BFPT, bits 14:23 (Exit 4-Byte Addressing) */ +#define JEDEC_BFPT_DW16_EXIT_E9 (1UL << 14) +#define JEDEC_BFPT_DW16_EXIT_E9_WE (1UL << 15) +#define JEDEC_BFPT_DW16_EXIT_EXTENDED_ADDR_REG (1UL << 16) +#define JEDEC_BFPT_DW16_EXIT_BANK_ADDR_REG_EN_BIT (1UL << 17) +#define JEDEC_BFPT_DW16_EXIT_NV_CONFIG_REG (1UL << 18) +#define JEDEC_BFPT_DW16_EXIT_HARD_RESET (1UL << 19) +#define JEDEC_BFPT_DW16_EXIT_SOFT_RESET (1UL << 20) +#define JEDEC_BFPT_DW16_EXIT_POWER_CYCLE (1UL << 21) +#define JEDEC_BFPT_DW16_EXIT_RESERVED_1 (1UL << 22) +#define JEDEC_BFPT_DW16_EXIT_RESERVED_2 (1UL << 23) + +/* JEDEC 4-Bytes Addressing Table 1st dword according to JESD216B */ +#define JEDEC_4BAIT_ID 0xFF84 +#define JEDEC_4BAIT_READ_SUPPORT (1UL << 0) +#define JEDEC_4BAIT_PROGRAM_SUPPORT (1UL << 6) +#define JEDEC_4BAIT_ERASE_TYPE_1_SUPPORT (1UL << 9) +#define JEDEC_4BAIT_ERASE_TYPE_2_SUPPORT (1UL << 10) +#define JEDEC_4BAIT_ERASE_TYPE_3_SUPPORT (1UL << 11) +#define JEDEC_4BAIT_ERASE_TYPE_4_SUPPORT (1UL << 12) + +/* read/write flash bytes in 4-bytes addressing mode */ +int spi_byte_program_4ba(struct flashctx *flash, unsigned int addr, uint8_t databyte); +int spi_nbyte_program_4ba(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len); +int spi_nbyte_read_4ba(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); + +/* read/write flash bytes with 4-bytes address from any mode (3-byte or 4-byte) */ +int spi_byte_program_4ba_direct(struct flashctx *flash, unsigned int addr, uint8_t databyte); +int spi_nbyte_program_4ba_direct(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len); +int spi_nbyte_read_4ba_direct(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); + +/* read/write flash bytes from 3-bytes addressing mode using extended address register */ +int spi_byte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, uint8_t databyte); +int spi_nbyte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len); +int spi_nbyte_read_4ba_ereg(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); + +/* enter 4-bytes addressing mode */ +int spi_enter_4ba_b7(struct flashctx *flash); +int spi_enter_4ba_b7_we(struct flashctx *flash); + +/* erase functions choosers for 4-bytes addressing mode */ +erasefunc_t *spi_get_erasefn_from_opcode_4ba(uint8_t opcode); +erasefunc_t *spi_get_erasefn_from_opcode_4ba_direct(uint8_t opcode); + +/* erase flash bytes in 4-bytes addressing mode */ +int spi_block_erase_20_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_52_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_d8_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + +/* erase flash bytes from 3-bytes addressing mode using extended address register */ +int spi_block_erase_20_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_52_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_d8_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + +/* selection of erase function between 4-bytes addressing mode and use of extended address register */ +int spi_block_erase_20_4ba_selector(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_52_4ba_selector(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_d8_4ba_selector(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + +/* erase flash bytes with 4-bytes address from any mode (3-byte or 4-byte) */ +int spi_block_erase_21_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_5c_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_dc_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + + +#endif /* __SPI_4BA_H__ */ Property changes on: spi4ba.h ___________________________________________________________________ Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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[PATCH 2/2] Read/erase/program 4-bytes addressing SPI flash chips 32MB+ for last 0.9.7 release
by Boris Baykov 09 Jan '15

09 Jan '15

Current patch is for the last 0.9.7 release (build 1711). The patch is made by local Linux diff from downloaded source http://download.flashrom.org/releases/flashrom-0.9.7.tar.bz2. Two same patches for different builds (one patch per letter) ------------------------------------------------------------ [1/2] Patch for Flashrom 0.9.7 (build 1861) by SVN diff [2/2] Patch for last 0.9.7 release (build 1711) by Linux diff Brief description ----------------- This patch adds ability to read, write and erase flash chips which require 4-bytes (32-bit) addressing to access to them. These are 32MB (256Mb) and larger new flash chips. Flashrom with this patch can support and program all (or most of all) of them. Besides of manually definable chips in flashchips.c this patch adds compliance to new JEDEC JESD216B standard which describes SFDP revision 1.6 procedure to read flash chip 4-bytes addressing details. Full description ---------------- This patch includes code for three types of 4-byte addressing: 1. Flash chip can be switched to 4-bytes addressing mode and then all read/erase/program instructions will be switched from 3-bytes mode to 4-bytes mode. So, well known instructions like 03h (Read), 02h (Program) and 20h,52h,D8h (Erase) are becoming one byte longer and accept 4-bytes address instead of 3-bytes. 4-bytes addressing mode is entered by the instruction B7h with preceding Write Enable (WREN). This is default method. 2. Also Flash chip data with addresses more than 24-bit field can address may be accessed by use of Extended Address Register that has 1-byte size and stores high byte of 32-bit address. So, we read flash from old 3-bytes addressing mode and write high byte of address to special register. Then we have access to full memory of a chip. Some chips may support this method only. 3. Also some new commands avalable and implemented. Large size flash chips support special instructions to use 4-bytes address directly from 3-bytes addressing mode and without do switching to 4-bytes mode. There are 13h (4BA Read), 12h (4BA Program) and 21h,5Ch,DCh (4BA Erase), correspondingly. However not all these commands are supported by all large flash chips. Some chips support 13h only, some 13h,12h,21h and DCh, but not 5Ch. This depends on the manufacturer of the chip. The patch adds code for all 3 types of 4-bytes address access and the exact method should be choosen by person who will manage to add new large chips to flashchips.c source file. I've added one new flash chip: Winbond W25Q256FV (32MB) because this is the only chip I have now for testing. Besides of manual including of new chips to Flashrom we may use SFDP procedure to discover parameters of the exact flash chip. More than a year before JEDEC released new standard JESD216 (revision B) which describes in detail how to receive 4-bytes addressing settings from the chip. This patch provides new code to add compliance to JESD216B to Flashrom. This means that Flashrom now can automatically detect 4-bytes addressing features of large flash chips and use them to access data. However not all thing are so good. Unfortunately JESD216B had come to manufacturer's production lines just 2-3 months ago. So, we have many chips that have large size requires 32-bit addressing but their SFDP tables have revision lower than 1.6 (described in JESD216B standard). For example my W25Q256FV returns SFDP info with revision 1.0, first one :-) This situation leads us to requirement to try to work now without new SFDP info. And it's implemented in the patch too. To test my parser code for SFDP revision 1.6 (from JESD216B) I've added some simulation code to sfdp.c. This code builds fake SFDP 1.6 tables in memory and passes them to the SFDP parser. Surely this simulation code is switched off by default and can be activated via hidden define on the top of sfdp.c Also I've added progress visualization for read, erase and write operations. It's turned out that seeing progress is essential for reading and especially writing 32 MB оf data via SPI. The operation can take more then 10 minutes on 15 MHz frequency of SPI. So, it's good to see its progress. I've added percents and slightly modified cli_output.c to send percents to screen only but not to logfile. Testing results --------------- Both patches are tested with Winbond W25Q256FV flash chip using Olimex ARM-USB-OCD-H programmer. Read, Erase and Program functions are fully tested for 4-bytes addressing type 1 (4-bytes mode), type 2 (extended addr. register) and partially tested for type 3 (new 4-bytes instructions with 4-bytes address). My W25Q256FV has support for 4BA_Read (13h) only, but doesn't support 4BA_Program (12h) and 4BA_Erase instructions. So, direct 4BA program and erase should be tested after. Also I should make an excuse about testing of SFDP rev 1.6 parser. I've tested it as good as I can using the simulation code I described above but I'm not able to test it on real flash chips because I don't have a chip complied to JESD216B with SFDP 1.6 now. This should be tested later too. Patched files ------------- chipdrivers.h - added functions declarations for spi4ba.c cli_output.c - print() patched to skip strings which are starting from '\b' to prevent writing progress percents to logfile flash.h - feature definitions added - added set of 4-bytes address functions to flashchip structure definition - added type field to block_eraser structure - added some definitions for progress visialization flashchips.c - added definition for Winbond W25Q256BV/W25Q256FV chips flashrom.c - added switch to 4-bytes addressing more for chips which support it - added progress visualization for erase/write (essensial for 32MB+ chips) - changed in address print %06x to %08x to support 32MB+ chips - added line to the flashrom's banner about this patch (temporary) Makefile - added spi4ba.c serprog.c - added 4-bytes addressing spi_nbyte_read call to serprog_spi_read spi.c - fixed flash chip size check in spi_chip_read spi25.c - added 4-bytes addressing spi_nbyte_read call to spi_read_chunked - added 4-bytes addressing spi_nbyte_program call to spi_write_chunked - added 4-bytes addressing spi_byte_program call to spi_chip_write_1 - added progress visualization for read operation (essensial for 32MB+ chips) sfdp.c - added compliance to JEDEC JESD216B standard (SFDP revision 1.6) - added parse of SFDP 4-Bytes Addressing features (probe_spi_sfdp,sfdp_fill_flash) - added parse of SFDP 4-Bytes Addressing Instruction Table (sfdp_parse_4ba_table) - added choosing of block_erasers for 4-bytes addressing (sfdp_*_uniform_eraser*) - added exact flash page_size recognision from 11th dword in SFDP rev 1.6 - added fix for Micron chips to read 16th dword stating from SFDP revision 1.5 - added simulation of JESD216B for any flash chips (just for testing) Added files ----------- spi4ba.h - definitions for 4-bytes addressing JEDEC commands - definitions for 16th dword bits of SFDP Basic Flash Param Table (JESD216B) - definitions for SFDP 4-Bytes Addressing Instruction Table (JESD216B) - functions declarations from spi4ba.c (same as in chipdrivers.h, just to see) spi4ba.c - functions for enter 4-bytes addressing mode - functions for write Extended Address Register - functions for read/write/erase in 4-bytes addressing mode - functions for read/write/erase with Extended Address Register - functions for read/write/erase directly with 4-bytes address (from any mode) - functions to choose block_eraser by opcode for 4-bytes addressing for sfdp.c - functions to select proper block_eraser (ext.reg or 4-bytes addr) for sfdp.c Signed-off-by: Boris Baykov <dev(a)borisbaykov.com>, Russia, Jan 2014 --- diff -U 5 -N ./flashrom-0.9.7/chipdrivers.h ./flashrom-0.9.7-4ba/chipdrivers.h --- ./flashrom-0.9.7/chipdrivers.h 2013-06-29 01:29:51.000000000 +0400 +++ ./flashrom-0.9.7-4ba/chipdrivers.h 2015-01-07 16:46:11.000000000 +0300 @@ -187,6 +187,33 @@ int probe_en29lv640b(struct flashctx *flash); int block_erase_en29lv640b(struct flashctx *flash, unsigned int start, unsigned int len); int block_erase_chip_en29lv640b(struct flashctx *flash, unsigned int start, unsigned int len); int write_en29lv640b(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); +/* spi4ba.c */ +int spi_enter_4ba_b7(struct flashctx *flash); +int spi_enter_4ba_b7_we(struct flashctx *flash); +int spi_byte_program_4ba(struct flashctx *flash, unsigned int addr, uint8_t databyte); +int spi_nbyte_program_4ba(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); +int spi_nbyte_read_4ba(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); +int spi_byte_program_4ba_direct(struct flashctx *flash, unsigned int addr, uint8_t databyte); +int spi_nbyte_program_4ba_direct(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); +int spi_nbyte_read_4ba_direct(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); +int spi_byte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, uint8_t databyte); +int spi_nbyte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); +int spi_nbyte_read_4ba_ereg(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); +erasefunc_t *spi_get_erasefn_from_opcode_4ba(uint8_t opcode); +erasefunc_t *spi_get_erasefn_from_opcode_4ba_direct(uint8_t opcode); +int spi_block_erase_20_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_20_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_20_4ba_selector(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_52_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_52_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_52_4ba_selector(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_d8_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_d8_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_d8_4ba_selector(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_21_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_5c_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_dc_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + #endif /* !__CHIPDRIVERS_H__ */ diff -U 5 -N ./flashrom-0.9.7/cli_output.c ./flashrom-0.9.7-4ba/cli_output.c --- ./flashrom-0.9.7/cli_output.c 2013-07-26 02:54:25.000000000 +0400 +++ ./flashrom-0.9.7-4ba/cli_output.c 2015-01-07 15:14:14.000000000 +0300 @@ -85,11 +85,12 @@ * time-critical operations. Don't slow them down by flushing. */ if (level != MSG_SPEW) fflush(output_type); } #ifndef STANDALONE - if ((level <= verbose_logfile) && logfile) { + /* skip of msgs starting from '\b' added to skip progress percents */ + if ((level <= verbose_logfile) && logfile && (!fmt || fmt[0] != '\b')) { va_start(ap, fmt); ret = vfprintf(logfile, fmt, ap); va_end(ap); if (level != MSG_SPEW) fflush(logfile); diff -U 5 -N ./flashrom-0.9.7/flashchips.c ./flashrom-0.9.7-4ba/flashchips.c --- ./flashrom-0.9.7/flashchips.c 2013-07-26 02:58:51.000000000 +0400 +++ ./flashrom-0.9.7-4ba/flashchips.c 2015-01-07 15:53:51.000000000 +0300 @@ -11427,10 +11427,59 @@ .voltage = {2700, 3600}, }, { .vendor = "Winbond", + .name = "W25Q256.V", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q256_V, + .total_size = 32768, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_FOUR_BYTE_ADDR | + FEATURE_NEED_ENTER_4BA_FOR_ERASE | FEATURE_NEED_ENTER_4BA_FOR_WRITE, + .four_bytes_addr_funcs = + { + .enter_4ba = spi_enter_4ba_b7_we, /* enter 4-bytes addressing mode by CMD B7 + WREN */ + .read_nbyte = spi_nbyte_read_4ba_direct, /* read directly from any mode, no need to enter 4ba */ + .program_byte = spi_byte_program_4ba, /* write from 4-bytes addressing mode */ + .program_nbyte = spi_nbyte_program_4ba /* write from 4-bytes addressing mode */ + }, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20_4ba, /* erases 4k from 4-bytes addressing mode */ + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_52_4ba, /* erases 32k from 4-bytes addressing mode */ + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8_4ba, /* erases 64k from 4-bytes addressing mode */ + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Winbond", .name = "W25Q20.W", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, .model_id = WINBOND_NEX_W25Q20_W, .total_size = 256, diff -U 5 -N ./flashrom-0.9.7/flash.h ./flashrom-0.9.7-4ba/flash.h --- ./flashrom-0.9.7/flash.h 2013-07-26 02:54:25.000000000 +0400 +++ ./flashrom-0.9.7-4ba/flash.h 2015-01-07 19:57:23.000000000 +0300 @@ -109,10 +109,18 @@ #define FEATURE_WRSR_EWSR (1 << 6) #define FEATURE_WRSR_WREN (1 << 7) #define FEATURE_WRSR_EITHER (FEATURE_WRSR_EWSR | FEATURE_WRSR_WREN) #define FEATURE_OTP (1 << 8) #define FEATURE_QPI (1 << 9) +/* Feature bits used for 4-bytes addressing mode */ +#define FEATURE_FOUR_BYTE_ADDR (1 << 10) +#define FEATURE_FOUR_BYTE_ADDR_ONLY (1 << 11) +#define FEATURE_NEED_ENTER_4BA_FOR_READ (1 << 12) +#define FEATURE_NEED_ENTER_4BA_FOR_WRITE (1 << 13) +#define FEATURE_NEED_ENTER_4BA_FOR_ERASE (1 << 14) +#define FEATURE_NEED_USE_EXTENDED_ADDR_REG (1 << 15) +#define FEATURE_ENTER_4BA_ALL (FEATURE_NEED_ENTER_4BA_FOR_READ | FEATURE_NEED_ENTER_4BA_FOR_WRITE | FEATURE_NEED_ENTER_4BA_FOR_ERASE | FEATURE_NEED_USE_EXTENDED_ADDR_REG) struct flashctx; typedef int (erasefunc_t)(struct flashctx *flash, unsigned int addr, unsigned int blocklen); struct flashchip { @@ -133,10 +141,18 @@ unsigned int total_size; /* Chip page size in bytes */ unsigned int page_size; int feature_bits; + /* set of function pointers to use in 4-bytes addressing mode */ + struct four_bytes_addr_funcs_set { + int (*enter_4ba) (struct flashctx *flash); + int (*read_nbyte) (struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); + int (*program_byte) (struct flashctx *flash, unsigned int addr, uint8_t databyte); + int (*program_nbyte) (struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); + } four_bytes_addr_funcs; + /* * Indicate if flashrom has been tested with this flash chip and if * everything worked correctly. */ uint32_t tested; @@ -154,10 +170,11 @@ * The first one that fits will be chosen. There is currently no way to * influence that behaviour. For testing just comment out the other * elements or set the function pointer to NULL. */ struct block_eraser { + int type; /* eraser type 1,2,3 or 4 */ struct eraseblock{ unsigned int size; /* Eraseblock size in bytes */ unsigned int count; /* Number of contiguous blocks with that size */ } eraseblocks[NUM_ERASEREGIONS]; /* a block_erase function should try to erase one block of size @@ -204,11 +221,11 @@ #define TEST_BAD_PREW (TEST_BAD_PROBE | TEST_BAD_READ | TEST_BAD_ERASE | TEST_BAD_WRITE) #define TEST_BAD_MASK 0xf0 /* Timing used in probe routines. ZERO is -2 to differentiate between an unset * field and zero delay. - * + * * SPI devices will always have zero delay and ignore this field. */ #define TIMING_FIXME -1 /* this is intentionally same value as fixme */ #define TIMING_IGNORED -1 @@ -313,10 +330,15 @@ #define msg_cdbg2(...) print(MSG_DEBUG2, __VA_ARGS__) /* chip debug2 */ #define msg_gspew(...) print(MSG_SPEW, __VA_ARGS__) /* general debug spew */ #define msg_pspew(...) print(MSG_SPEW, __VA_ARGS__) /* programmer debug spew */ #define msg_cspew(...) print(MSG_SPEW, __VA_ARGS__) /* chip debug spew */ +/* Read progress will be shown for reads more than 256KB */ +#define MIN_LENGTH_TO_SHOW_READ_PROGRESS 256 * 1024 +/* Read progress will be shown for erases and writes more than 64KB */ +#define MIN_LENGTH_TO_SHOW_ERASE_AND_WRITE_PROGRESS 64 * 1024 + /* layout.c */ int register_include_arg(char *name); int process_include_args(void); int read_romlayout(char *name); int handle_romentries(const struct flashctx *flash, uint8_t *oldcontents, uint8_t *newcontents); diff -U 5 -N ./flashrom-0.9.7/flashrom.c ./flashrom-0.9.7-4ba/flashrom.c --- ./flashrom-0.9.7/flashrom.c 2013-08-13 11:09:57.000000000 +0400 +++ ./flashrom-0.9.7-4ba/flashrom.c 2015-01-08 17:21:27.000000000 +0300 @@ -1294,12 +1294,12 @@ "non-empty erase function. Not an error.\n"); if (!done) continue; if (done != chip->total_size * 1024) { msg_gerr("ERROR: Flash chip %s erase function %i " - "region walking resulted in 0x%06x bytes total," - " expected 0x%06x bytes. Please report a bug at" + "region walking resulted in 0x%08x bytes total," + " expected 0x%08x bytes. Please report a bug at" " flashrom(a)flashrom.org\n", chip->name, k, done, chip->total_size * 1024); ret = 1; } if (!eraser.block_erase) @@ -1388,29 +1388,52 @@ { int i, j; unsigned int start = 0; unsigned int len; struct block_eraser eraser = flash->chip->block_erasers[erasefunction]; + int show_progress = 0; + unsigned int percent_last, percent_current; + unsigned long size = flash->chip->total_size * 1024; + + /* progress visualizaion init */ + if(size >= MIN_LENGTH_TO_SHOW_ERASE_AND_WRITE_PROGRESS) { + msg_cinfo(" "); /* only this space will go to logfile but all strings with \b wont. */ + msg_cinfo("\b 0%%"); + percent_last = percent_current = 0; + show_progress = 1; /* enable progress visualizaion */ + } for (i = 0; i < NUM_ERASEREGIONS; i++) { /* count==0 for all automatically initialized array * members so the loop below won't be executed for them. */ len = eraser.eraseblocks[i].size; for (j = 0; j < eraser.eraseblocks[i].count; j++) { /* Print this for every block except the first one. */ if (i || j) msg_cdbg(", "); - msg_cdbg("0x%06x-0x%06x", start, + msg_cdbg("0x%08x-0x%08x", start, start + len - 1); if (do_something(flash, start, len, param1, param2, eraser.block_erase)) { return 1; } start += len; + + if(show_progress) { + percent_current = (unsigned int) ((unsigned long long)start * 100 / size); + if(percent_current != percent_last) { + msg_cinfo("\b\b\b%2d%%", percent_current); + percent_last = percent_current; + } + } } } + + if(show_progress) + msg_cinfo("\b\b\b\b"); /* remove progress percents from the screen */ + msg_cdbg("\n"); return 0; } static int check_block_eraser(const struct flashctx *flash, int k, int log) @@ -1664,12 +1687,15 @@ } void print_version(void) { msg_ginfo("flashrom v%s", flashrom_version); + msg_ginfo("-4ba"); /* temporary to indicate that version is patched */ print_sysinfo(); msg_ginfo("\n"); + /* temporary to indicate that version is patched */ + msg_ginfo("with patch for support SPI flash chips with 4-bytes addressing\n"); } void print_banner(void) { msg_ginfo("flashrom is free software, get the source code at " @@ -1908,10 +1934,44 @@ * erase and write. */ if (flash->chip->unlock) flash->chip->unlock(flash); + if(flash->chip->feature_bits & FEATURE_FOUR_BYTE_ADDR) { + /* Switching to 4-Bytes Addressing mode if flash chip supports it + and selected operation requires 4-Bytes Addressing mode + (no need for direct and ext.addr.reg operation) */ + if(((read_it || verify_it) && (flash->chip->feature_bits & FEATURE_NEED_ENTER_4BA_FOR_READ)) || + ((erase_it || write_it) && (flash->chip->feature_bits & (FEATURE_NEED_ENTER_4BA_FOR_READ | + FEATURE_NEED_ENTER_4BA_FOR_WRITE | FEATURE_NEED_ENTER_4BA_FOR_ERASE))) ) { + + if (!flash->chip->four_bytes_addr_funcs.enter_4ba) { + msg_cerr("No function for Enter 4-bytes addressing mode for this flash chip.\n" + "Please report to flashrom(a)flashrom.org\n"); + ret = 1; + goto out_nofree; + } + + if(flash->chip->four_bytes_addr_funcs.enter_4ba(flash)) { + msg_cerr("Switching to 4-bytes addressing mode failed!\n"); + ret = 1; + goto out_nofree; + } + + msg_cdbg("Switched to 4-bytes addressing mode.\n"); + } + /* Do not switch to 4-Bytes Addressing mode if using Extended Address Register */ + else if(flash->chip->feature_bits & FEATURE_NEED_USE_EXTENDED_ADDR_REG) { + msg_cdbg("Using 4-bytes addressing with extended address register.\n"); + } + /* Do not switch to 4-Bytes Addressing mode if all instructions are direct-4BA + or if the flash chip is 4-Bytes Addressing Only and always in 4BA-mode */ + else { + msg_cdbg2("No need to switch to 4-bytes addressing mode.\n"); + } + } + if (read_it) { ret = read_flash_to_file(flash, filename); goto out_nofree; } diff -U 5 -N ./flashrom-0.9.7/Makefile ./flashrom-0.9.7-4ba/Makefile --- ./flashrom-0.9.7/Makefile 2013-08-14 02:00:00.000000000 +0400 +++ ./flashrom-0.9.7-4ba/Makefile 2015-01-07 16:46:18.000000000 +0300 @@ -307,11 +307,11 @@ ############################################################################### # Flash chip drivers and bus support infrastructure. CHIP_OBJS = jedec.o stm50flw0x0x.o w39.o w29ee011.o \ sst28sf040.o m29f400bt.o 82802ab.o pm49fl00x.o \ - sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o spi25_statusreg.o \ + sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o spi25_statusreg.o spi4ba.o \ opaque.o sfdp.o en29lv640b.o ############################################################################### # Library code. diff -U 5 -N ./flashrom-0.9.7/serprog.c ./flashrom-0.9.7-4ba/serprog.c --- ./flashrom-0.9.7/serprog.c 2013-07-26 02:54:25.000000000 +0400 +++ ./flashrom-0.9.7-4ba/serprog.c 2015-01-07 15:43:55.000000000 +0300 @@ -887,11 +887,14 @@ unsigned int i, cur_len; const unsigned int max_read = spi_programmer_serprog.max_data_read; for (i = 0; i < len; i += cur_len) { int ret; cur_len = min(max_read, (len - i)); - ret = spi_nbyte_read(flash, start + i, buf + i, cur_len); + ret = (flash->chip->feature_bits & FEATURE_FOUR_BYTE_ADDR) == 0 + ? spi_nbyte_read(flash, start + i, buf + i, cur_len) + : flash->chip->four_bytes_addr_funcs.read_nbyte(flash, + start + i, buf + i, cur_len); if (ret) return ret; } return 0; } diff -U 5 -N ./flashrom-0.9.7/sfdp.c ./flashrom-0.9.7-4ba/sfdp.c --- ./flashrom-0.9.7/sfdp.c 2012-08-25 05:17:58.000000000 +0400 +++ ./flashrom-0.9.7-4ba/sfdp.c 2015-01-08 14:00:44.000000000 +0300 @@ -1,9 +1,10 @@ /* * This file is part of the flashrom project. * * Copyright (C) 2011-2012 Stefan Tauner + * Copyright (C) 2014 Boris Baykov * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * @@ -15,17 +16,32 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* + * History of changes: + * 05/01/2014 Added compliance to JESD216B standard and SFDP revision 1.6 + * 07/01/2014 Modified to support SFDP revision 1.5 (for Micron flash chips) + */ + #include <stdint.h> #include <stdlib.h> #include <string.h> #include "flash.h" #include "spi.h" +#include "spi4ba.h" #include "chipdrivers.h" +/* Default four bytes addressing behavior: + 1) 4-Bytes Addressing Mode (FBA_USE_EXT_ADDR_REG_BY_DEFAULT not defined) + 2) 3-bytes mode with Ext.Addr.Register (FBA_USE_EXT_ADDR_REG_BY_DEFAULT defined) */ +/* #define FBA_USE_EXT_ADDR_REG_BY_DEFAULT 1 */ + +/* For testing purposes only. Tests JESD216B SFDP compliance without proper flash chip */ +/* #define JESD216B_SIMULATION 1 */ + static int spi_sfdp_read_sfdp_chunk(struct flashctx *flash, uint32_t address, uint8_t *buf, int len) { int i, ret; uint8_t *newbuf; const unsigned char cmd[JEDEC_SFDP_OUTSIZE] = { @@ -72,22 +88,25 @@ } return ret; } struct sfdp_tbl_hdr { - uint8_t id; + uint16_t id; uint8_t v_minor; uint8_t v_major; uint8_t len; uint32_t ptp; /* 24b pointer */ }; -static int sfdp_add_uniform_eraser(struct flashchip *chip, uint8_t opcode, uint32_t block_size) +static int sfdp_add_uniform_eraser(struct flashchip *chip, int eraser_type, uint8_t opcode, uint32_t block_size) { int i; uint32_t total_size = chip->total_size * 1024; - erasefunc_t *erasefn = spi_get_erasefn_from_opcode(opcode); + + /* choosing different eraser functions for 3-bytes and 4-bytes addressing */ + erasefunc_t *erasefn = (chip->feature_bits & FEATURE_FOUR_BYTE_ADDR) ? + spi_get_erasefn_from_opcode_4ba(opcode) : spi_get_erasefn_from_opcode(opcode); if (erasefn == NULL || total_size == 0 || block_size == 0 || total_size % block_size != 0) { msg_cdbg("%s: invalid input, please report to " "flashrom(a)flashrom.org\n", __func__); @@ -109,10 +128,11 @@ msg_cspew(" Block Eraser %d is already occupied.\n", i); continue; } + eraser->type = eraser_type; eraser->block_erase = erasefn; eraser->eraseblocks[0].size = block_size; eraser->eraseblocks[0].count = total_size/block_size; msg_cdbg2(" Block eraser %d: %d x %d B with opcode " "0x%02x\n", i, total_size/block_size, block_size, @@ -123,44 +143,110 @@ " Please report this at flashrom(a)flashrom.org\n", __func__, i); return 1; } -static int sfdp_fill_flash(struct flashchip *chip, uint8_t *buf, uint16_t len) +/* Try of replace exist erasers to new direct 4-bytes addressing erasers + which can be called from ANY addressing mode: 3-byte or 4-bytes. + These erasers opcodes defines in SFDP 4-byte address instruction table + from SFDP revision 1.6 that is defined by JESD216B standard. */ +static int sfdp_change_uniform_eraser_4ba_direct(struct flashchip *chip, int eraser_type, uint8_t opcode) +{ + int i; + erasefunc_t *erasefn = spi_get_erasefn_from_opcode_4ba_direct(opcode); + + if (erasefn == NULL) { + msg_cdbg("%s: invalid input, please report to " + "flashrom(a)flashrom.org\n", __func__); + return 1; + } + + for (i = 0; i < NUM_ERASEFUNCTIONS; i++) { + struct block_eraser *eraser = &chip->block_erasers[i]; + if (eraser->eraseblocks[0].size == 0) + break; + if (eraser->type != eraser_type) + continue; + + eraser->block_erase = erasefn; + msg_cdbg2(" Block eraser %d (type %d) changed to opcode " + "0x%02x\n", i, eraser_type, opcode); + return 0; + } + + msg_cspew("%s: Block Eraser type %d isn't found." + " Please report this at flashrom(a)flashrom.org\n", + __func__, eraser_type); + return 1; +} + +/* Parse of JEDEC SFDP Basic Flash Parameter Table */ +static int sfdp_fill_flash(struct flashchip *chip, uint8_t *buf, uint16_t len, int sfdp_rev_15) { uint8_t opcode_4k_erase = 0xFF; uint32_t tmp32; uint8_t tmp8; uint32_t total_size; /* in bytes */ uint32_t block_size; int j; msg_cdbg("Parsing JEDEC flash parameter table... "); - if (len != 9 * 4 && len != 4 * 4) { + if (len != 16 * 4 && len != 9 * 4 && len != 4 * 4) { msg_cdbg("%s: len out of spec\n", __func__); return 1; } msg_cdbg2("\n"); - + /* 1. double word */ tmp32 = ((unsigned int)buf[(4 * 0) + 0]); tmp32 |= ((unsigned int)buf[(4 * 0) + 1]) << 8; tmp32 |= ((unsigned int)buf[(4 * 0) + 2]) << 16; tmp32 |= ((unsigned int)buf[(4 * 0) + 3]) << 24; + chip->feature_bits = 0; + tmp8 = (tmp32 >> 17) & 0x3; switch (tmp8) { case 0x0: msg_cdbg2(" 3-Byte only addressing.\n"); break; case 0x1: msg_cdbg2(" 3-Byte (and optionally 4-Byte) addressing.\n"); +#ifndef FBA_USE_EXT_ADDR_REG_BY_DEFAULT + /* assuming that 4-bytes addressing mode can be entered + by CMD B7h preceded with WREN and all read, write and + erase commands will be able to receive 4-bytes address */ + chip->feature_bits |= ( FEATURE_FOUR_BYTE_ADDR | + FEATURE_NEED_ENTER_4BA_FOR_READ | + FEATURE_NEED_ENTER_4BA_FOR_WRITE | + FEATURE_NEED_ENTER_4BA_FOR_ERASE ); + chip->four_bytes_addr_funcs.enter_4ba = spi_enter_4ba_b7_we; + chip->four_bytes_addr_funcs.program_byte = spi_byte_program_4ba; + chip->four_bytes_addr_funcs.program_nbyte = spi_nbyte_program_4ba; + chip->four_bytes_addr_funcs.read_nbyte = spi_nbyte_read_4ba; +#else /* if FBA_USE_EXT_ADDR_REG_BY_DEFAULT defined */ + /* assuming that 4-bytes addressing is working using + extended address register which can be assigned + throught CMD C5h and then all commands will use + 3-bytes address as usual */ + chip->feature_bits |= ( FEATURE_FOUR_BYTE_ADDR | + FEATURE_NEED_USE_EXTENDED_ADDR_REG ); + chip->four_bytes_addr_funcs.enter_4ba = NULL; + chip->four_bytes_addr_funcs.program_byte = spi_byte_program_4ba_ereg; + chip->four_bytes_addr_funcs.program_nbyte = spi_nbyte_program_4ba_ereg; + chip->four_bytes_addr_funcs.read_nbyte = spi_nbyte_read_4ba_ereg; +#endif /* FBA_USE_EXT_ADDR_REG_BY_DEFAULT */ break; case 0x2: - msg_cdbg(" 4-Byte only addressing (not supported by " - "flashrom).\n"); - return 1; + msg_cdbg2(" 4-Byte only addressing.\n"); + chip->feature_bits |= ( FEATURE_FOUR_BYTE_ADDR | + FEATURE_FOUR_BYTE_ADDR_ONLY ); + chip->four_bytes_addr_funcs.enter_4ba = NULL; + chip->four_bytes_addr_funcs.program_byte = spi_byte_program_4ba; + chip->four_bytes_addr_funcs.program_nbyte = spi_nbyte_program_4ba; + chip->four_bytes_addr_funcs.read_nbyte = spi_nbyte_read_4ba; + break; default: msg_cdbg(" Required addressing mode (0x%x) not supported.\n", tmp8); return 1; } @@ -168,21 +254,21 @@ msg_cdbg2(" Status register is "); if (tmp32 & (1 << 3)) { msg_cdbg2("volatile and writes to the status register have to " "be enabled with "); if (tmp32 & (1 << 4)) { - chip->feature_bits = FEATURE_WRSR_WREN; + chip->feature_bits |= FEATURE_WRSR_WREN; msg_cdbg2("WREN (0x06).\n"); } else { - chip->feature_bits = FEATURE_WRSR_EWSR; + chip->feature_bits |= FEATURE_WRSR_EWSR; msg_cdbg2("EWSR (0x50).\n"); } } else { msg_cdbg2("non-volatile and the standard does not allow " "vendors to tell us whether EWSR/WREN is needed for " "status register writes - assuming EWSR.\n"); - chip->feature_bits = FEATURE_WRSR_EWSR; + chip->feature_bits |= FEATURE_WRSR_EWSR; } msg_cdbg2(" Write chunk size is "); if (tmp32 & (1 << 2)) { msg_cdbg2("at least 64 B.\n"); @@ -212,56 +298,306 @@ return 1; } total_size = ((tmp32 & 0x7FFFFFFF) + 1) / 8; chip->total_size = total_size / 1024; msg_cdbg2(" Flash chip size is %d kB.\n", chip->total_size); + if (total_size > (1 << 24)) { - msg_cdbg("Flash chip size is bigger than what 3-Byte addressing " - "can access.\n"); - return 1; + if(!sfdp_rev_15) { + msg_cdbg("Flash chip size is bigger than what 3-Byte addressing " + "can access but chip's SFDP revision is lower than 1.6 " + "(1.5).\nConsequently 4-bytes addressing can NOT be " + "properly configured using current SFDP information.\n"); +#ifndef FBA_USE_EXT_ADDR_REG_BY_DEFAULT + msg_cdbg("Assuming that 4-bytes addressing mode can be " + "entered by CMD B7h with WREN.\n"); +#else + msg_cdbg("Assuming that 4-bytes addressing is working via " + "an Extended Address Register which can be written " + "by CMD C5h.\n"); +#endif + } } - if (opcode_4k_erase != 0xFF) - sfdp_add_uniform_eraser(chip, opcode_4k_erase, 4 * 1024); - /* FIXME: double words 3-7 contain unused fast read information */ - if (len == 4 * 4) { + if (len < 9 * 4) { msg_cdbg(" It seems like this chip supports the preliminary " "Intel version of SFDP, skipping processing of double " "words 3-9.\n"); + + /* in the case if BFPT erasers array is not present + trying to add default 4k-eraser */ + if (opcode_4k_erase != 0xFF) + sfdp_add_uniform_eraser(chip, 0, opcode_4k_erase, 4 * 1024); + goto done; } - /* 8. double word */ + /* 8. double word & 9. double word */ + /* for by block eraser types, from Type 1 to Type 4 */ for (j = 0; j < 4; j++) { /* 7 double words from the start + 2 bytes for every eraser */ tmp8 = buf[(4 * 7) + (j * 2)]; - msg_cspew(" Erase Sector Type %d Size: 0x%02x\n", j + 1, - tmp8); + msg_cspew(" Erase Sector (Type %d) Size: 0x%02x\n", j + 1, tmp8); if (tmp8 == 0) { - msg_cspew(" Erase Sector Type %d is unused.\n", j); + msg_cspew(" Erase Sector (Type %d) is unused.\n", j + 1); continue; } if (tmp8 >= 31) { - msg_cdbg2(" Block size of erase Sector Type %d (2^%d) " - "is too big for flashrom.\n", j, tmp8); + msg_cdbg2(" Block size of erase Sector (Type %d): 2^%d " + "is too big for flashrom.\n", j + 1, tmp8); continue; } block_size = 1 << (tmp8); /* block_size = 2 ^ field */ tmp8 = buf[(4 * 7) + (j * 2) + 1]; - msg_cspew(" Erase Sector Type %d Opcode: 0x%02x\n", j + 1, - tmp8); - sfdp_add_uniform_eraser(chip, tmp8, block_size); + msg_cspew(" Erase Sector (Type %d) Opcode: 0x%02x\n", j + 1, tmp8); + sfdp_add_uniform_eraser(chip, j + 1, tmp8, block_size); + } + + /* Trying to adding the default 4k eraser after parsing erasers info. + In most cases this eraser has already been added before. */ + if (opcode_4k_erase != 0xFF) + sfdp_add_uniform_eraser(chip, 0, opcode_4k_erase, 4 * 1024); + + /* If the chip doesn't support 4-bytes addressing mode we don't have + to read and analyze 16th DWORD of Basic Flash Parameter Table */ + if (!(chip->feature_bits & FEATURE_FOUR_BYTE_ADDR)) + goto done; + + /* In the case if the chip is working in 4-bytes addressing mode ONLY we + don't have to read and analyze 16th DWORD of Basic Flash Parameter Table + because we don't have to know how to switch to 4-bytes mode and back + when we are already in 4-bytes mode permanently. */ + if (chip->feature_bits & FEATURE_FOUR_BYTE_ADDR_ONLY) + goto done; + + /* If the SFDP revision supported by the chip is lower that 1.6 (1.5) + we can not read and analyze 16th DWORD of Basic Flash Parameter Table. + Using defaults by FBA_USE_EXT_ADDR_REG_BY_DEFAULT define. */ + if(!sfdp_rev_15) + goto done; + + if (len < 16 * 4) { + msg_cdbg("%s: len of BFPT is out of spec\n", __func__); + msg_cerr("ERROR: Unable read 4-bytes addressing parameters.\n"); + return 1; + } + + /* 11. double word */ + tmp8 = buf[(4*10) + 0] >> 4; /* get upper nibble of LSB of 11th dword */ + chip->page_size = 1 << tmp8; /* page_size = 2 ^ N */ + msg_cdbg2(" Page size is %d B.\n", chip->page_size); + + /* 16. double word */ + tmp32 = ((unsigned int)buf[(4 * 15) + 0]); + tmp32 |= ((unsigned int)buf[(4 * 15) + 1]) << 8; + tmp32 |= ((unsigned int)buf[(4 * 15) + 2]) << 16; + tmp32 |= ((unsigned int)buf[(4 * 15) + 3]) << 24; + + /* Parsing 16th DWORD of Basic Flash Parameter Table according to JESD216B */ + + if(tmp32 & JEDEC_BFPT_DW16_ENTER_B7) { + msg_cdbg2(" Enter 4-bytes addressing mode by CMD B7h\n"); + chip->four_bytes_addr_funcs.enter_4ba = spi_enter_4ba_b7; + chip->four_bytes_addr_funcs.program_byte = spi_byte_program_4ba; + chip->four_bytes_addr_funcs.program_nbyte = spi_nbyte_program_4ba; + chip->four_bytes_addr_funcs.read_nbyte = spi_nbyte_read_4ba; + chip->feature_bits &= ~FEATURE_ENTER_4BA_ALL; // clear defaults + chip->feature_bits |= ( FEATURE_NEED_ENTER_4BA_FOR_READ | + FEATURE_NEED_ENTER_4BA_FOR_WRITE | + FEATURE_NEED_ENTER_4BA_FOR_ERASE ); + } + else if(tmp32 & JEDEC_BFPT_DW16_ENTER_B7_WE) { + msg_cdbg2(" Enter 4-bytes addressing mode by CMD B7h with WREN\n"); + chip->four_bytes_addr_funcs.enter_4ba = spi_enter_4ba_b7_we; + chip->four_bytes_addr_funcs.program_byte = spi_byte_program_4ba; + chip->four_bytes_addr_funcs.program_nbyte = spi_nbyte_program_4ba; + chip->four_bytes_addr_funcs.read_nbyte = spi_nbyte_read_4ba; + chip->feature_bits &= ~FEATURE_ENTER_4BA_ALL; // clear defaults + chip->feature_bits |= ( FEATURE_NEED_ENTER_4BA_FOR_READ | + FEATURE_NEED_ENTER_4BA_FOR_WRITE | + FEATURE_NEED_ENTER_4BA_FOR_ERASE ); + } + else if(tmp32 & JEDEC_BFPT_DW16_ENTER_EXTENDED_ADDR_REG) { + msg_cdbg2(" Extended Address Register used for 4-bytes addressing\n"); + chip->four_bytes_addr_funcs.program_byte = spi_byte_program_4ba_ereg; + chip->four_bytes_addr_funcs.program_nbyte = spi_nbyte_program_4ba_ereg; + chip->four_bytes_addr_funcs.read_nbyte = spi_nbyte_read_4ba_ereg; + chip->feature_bits &= ~FEATURE_ENTER_4BA_ALL; // clear defaults + /* this flag signals to all '*_selector' functions + to use Ext.Addr.Reg while erase operations */ + chip->feature_bits |= FEATURE_NEED_USE_EXTENDED_ADDR_REG; + } + else { + msg_cerr("ERROR: Unable to use 4-bytes addressing for this chip.\n" + " Please report this at flashrom(a)flashrom.org\n\n"); + return 1; } done: msg_cdbg("done.\n"); return 0; } +/* Parse of JEDEC SFDP 4-byte address instruction table. From SFDP revision 1.6 only. + This parsing shoukd be called after basic flash parameter table is parsed. */ +static int sfdp_parse_4ba_table(struct flashchip *chip, uint8_t *buf, uint16_t len) +{ + uint32_t tmp32; + uint8_t tmp8; + int j, direct_erasers; + int direct_count; + + msg_cdbg("Parsing JEDEC 4-byte address instuction table... "); + if (len != 2 * 4) { + msg_cdbg("%s: len out of spec\n", __func__); + return 1; + } + msg_cdbg2("\n"); + + /* 1. double word */ + tmp32 = ((unsigned int)buf[(4 * 0) + 0]); + tmp32 |= ((unsigned int)buf[(4 * 0) + 1]) << 8; + tmp32 |= ((unsigned int)buf[(4 * 0) + 2]) << 16; + tmp32 |= ((unsigned int)buf[(4 * 0) + 3]) << 24; + + direct_count = 0; + + if(tmp32 & JEDEC_4BAIT_READ_SUPPORT) { + msg_cdbg2(" Found Read CMD 13h with 4-bytes address\n"); + chip->four_bytes_addr_funcs.read_nbyte = spi_nbyte_read_4ba_direct; + /* read function has changed to direct 4-bytes function, + so entering 4-bytes mode isn't required for reading bytes */ + chip->feature_bits &= ~FEATURE_NEED_ENTER_4BA_FOR_READ; + direct_count++; + } + + if(tmp32 & JEDEC_4BAIT_PROGRAM_SUPPORT) { + msg_cdbg2(" Found Write CMD 12h with 4-bytes address\n"); + chip->four_bytes_addr_funcs.program_byte = spi_byte_program_4ba_direct; + chip->four_bytes_addr_funcs.program_nbyte = spi_nbyte_program_4ba_direct; + /* write (program) functions have changed to direct 4-bytes functions, + so entering 4-bytes mode isn't required for writing bytes */ + chip->feature_bits &= ~FEATURE_NEED_ENTER_4BA_FOR_WRITE; + direct_count++; + } + + direct_erasers = 0; + + /* 2. double word */ + for (j = 0; j < 4; j++) { + if(!(tmp32 & (JEDEC_4BAIT_ERASE_TYPE_1_SUPPORT << j))) + continue; + + tmp8 = buf[(4 * 1) + j]; + + msg_cdbg2(" Found Erase (type %d) CMD %02Xh with 4-bytes address\n", j + 1, tmp8); + + if(tmp8 == 0xFF) { + msg_cdbg("%s: Eraser (type %d) is supported, but opcode = 0xFF\n" + " Please report to flashrom(a)flashrom.org\n\n", __func__, j + 1); + continue; + } + + /* try of replacing the eraser with direct 4-bytes eraser */ + if(!sfdp_change_uniform_eraser_4ba_direct(chip, j + 1, tmp8)) + direct_erasers++; + } + + for (j = 0; j < NUM_ERASEFUNCTIONS; j++) { + if (chip->block_erasers[j].eraseblocks[0].size == 0) + break; + } + + if( j == direct_erasers ) { + /* if all erasers have been changed to direct 4-bytes ones, + then we don't have to enter 4-bytes mode for erase */ + chip->feature_bits &= ~FEATURE_NEED_ENTER_4BA_FOR_ERASE; + direct_count++; + msg_cspew("All erasers have changed to direct ones.\n"); + } + + if( direct_count == 3 ) { + /* if all read/write/erase functions are direct 4-bytes now, + then we don't have to use extended address register */ + chip->feature_bits &= ~FEATURE_NEED_USE_EXTENDED_ADDR_REG; + msg_cspew("All read/write/erase functions have changed to direct ones.\n"); + } + + msg_cdbg("done.\n"); + return 0; +} + +#ifdef JESD216B_SIMULATION +/* This simulation increases size of Basic Flash Parameter Table + to have 16 dwords size and fills 16th dword with fake information + that is required to test JESD216B compliance. */ +int sfdp_jesd216b_simulation_dw16(uint8_t** ptbuf, uint16_t* plen) +{ + uint8_t* tbufsim; + uint16_t lensim = 16 * 4; + + tbufsim = malloc(lensim); + if (tbufsim == NULL) { + msg_gerr("Out of memory!\n"); + return 1; + } + + msg_cdbg("\n=== SIMULATION of JESD216B 16th Dword of Basic Flash Parameter Table\n"); + + memset(tbufsim, 0, 16 * 4); + memcpy(tbufsim, *ptbuf, min(*plen, 15 * 4)); + + tbufsim[(4*10) + 0] = 8 << 4; /* page size = 256 */ + + *((uint32_t*)&tbufsim[15 * 4]) = /*JEDEC_BFPT_DW16_ENTER_B7 | */ + JEDEC_BFPT_DW16_ENTER_B7_WE | + JEDEC_BFPT_DW16_ENTER_EXTENDED_ADDR_REG /* | + JEDEC_BFPT_DW16_ENTER_BANK_ADDR_REG_EN_BIT | + JEDEC_BFPT_DW16_ENTER_NV_CONFIG_REG | + JEDEC_BFPT_DW16_VENDOR_SET | + JEDEC_BFPT_DW16_4_BYTES_ADDRESS_ONLY */ ; + + free(*ptbuf); + *ptbuf = tbufsim; + *plen = lensim; + return 0; +} + +/* This simulation created fake 4-bytes Address Instruction Table + with features information to test JESD216B compliance. */ +int sfdp_jesd216b_simulation_4bait(uint8_t** ptbuf, uint16_t* plen) +{ + uint8_t* tbufsim; + uint16_t lensim = 2 * 4; + + tbufsim = malloc(lensim); + if (tbufsim == NULL) { + msg_gerr("Out of memory!\n"); + return 1; + } + + msg_cdbg("\n=== SIMULATION of JESD216B 4-bytes Address Instruction Table\n"); + + *((uint32_t*)&tbufsim[0]) = JEDEC_4BAIT_READ_SUPPORT /*| + JEDEC_4BAIT_PROGRAM_SUPPORT | + JEDEC_4BAIT_ERASE_TYPE_1_SUPPORT | + JEDEC_4BAIT_ERASE_TYPE_2_SUPPORT | + JEDEC_4BAIT_ERASE_TYPE_3_SUPPORT | + JEDEC_4BAIT_ERASE_TYPE_4_SUPPORT */; + *((uint32_t*)&tbufsim[4]) = 0xFFFFFFFF; + /* *((uint32_t*)&tbufsim[4]) = 0xFFDC5C21; */ + + free(*ptbuf); + *ptbuf = tbufsim; + *plen = lensim; + return 0; +} +#endif + int probe_spi_sfdp(struct flashctx *flash) { int ret = 0; uint8_t buf[8]; uint32_t tmp32; @@ -269,10 +605,11 @@ /* need to limit the table loop by comparing i to uint8_t nph hence: */ uint16_t i; struct sfdp_tbl_hdr *hdrs; uint8_t *hbuf; uint8_t *tbuf; + int sfdp_rev_16 = 0, sfdp_rev_15 = 0; if (spi_sfdp_read_sfdp(flash, 0x00, buf, 4)) { msg_cdbg("Receiving SFDP signature failed.\n"); return 0; } @@ -296,10 +633,36 @@ if (buf[1] != 0x01) { msg_cdbg("The chip supports an unknown version of SFDP. " "Aborting SFDP probe!\n"); return 0; } + + /* JEDEC JESD216B defines SFDP revision 1.6 and includes: + 1) 16 dwords in Basic Flash Parameter Table + 2) 16th dword has information how to enter + and exit 4-bytes addressing mode + 3) 4-Bytes Address Instruction Table with ID 0xFF84 + + However we can see in the datasheet for Micron's + MT25Q 512Mb chip (MT25QL512AB/MT25QU512AB) that the + chip returnes SFDP revision 1.5 and has 16 dwords + in its Basic Flash Paramater Table. Also the information + about addressing mode switch is exist in the 16th dword. + But 4-Bytes Address Instruction Table is absent. + + So we will use 16th dword from SFDP revision 1.5 + but 4-Bytes Address Instruction Table from SFDP 1.6 only. + This assumption is made for better support of Micron + flash chips. + + FIXME: SFDP revisions compliance should be checked + more carefully after more information about JESD216B + SFDP tables will be known from real flash chips. + */ + sfdp_rev_16 = (buf[1] == 1 && buf[0] >= 6) || buf[1] > 1; + sfdp_rev_15 = (buf[1] == 1 && buf[0] >= 5) || buf[1] > 1; + nph = buf[2]; msg_cdbg2("SFDP number of parameter headers is %d (NPH = %d).\n", nph + 1, nph); /* Fetch all parameter headers, even if we don't use them all (yet). */ @@ -314,17 +677,18 @@ goto cleanup_hdrs; } for (i = 0; i <= nph; i++) { uint16_t len; - hdrs[i].id = hbuf[(8 * i) + 0]; + hdrs[i].id = hbuf[(8 * i) + 0]; /* ID LSB read */ hdrs[i].v_minor = hbuf[(8 * i) + 1]; hdrs[i].v_major = hbuf[(8 * i) + 2]; hdrs[i].len = hbuf[(8 * i) + 3]; hdrs[i].ptp = hbuf[(8 * i) + 4]; hdrs[i].ptp |= ((unsigned int)hbuf[(8 * i) + 5]) << 8; hdrs[i].ptp |= ((unsigned int)hbuf[(8 * i) + 6]) << 16; + hdrs[i].id |= ((uint16_t)hbuf[(8 * i) + 7]) << 8; /* ID MSB read */ msg_cdbg2("\nSFDP parameter table header %d/%d:\n", i, nph); msg_cdbg2(" ID 0x%02x, version %d.%d\n", hdrs[i].id, hdrs[i].v_major, hdrs[i].v_minor); len = hdrs[i].len * 4; tmp32 = hdrs[i].ptp; @@ -366,29 +730,51 @@ } } msg_cspew("\n"); if (i == 0) { /* Mandatory JEDEC SFDP parameter table */ - if (hdrs[i].id != 0) + if (hdrs[i].id != JEDEC_BFPT_ID) msg_cdbg("ID of the mandatory JEDEC SFDP " - "parameter table is not 0 as demanded " - "by JESD216 (warning only).\n"); - + "parameter table is not 0xFF00 as" + "demanded by JESD216 (warning only)." + "\n"); +#ifdef JESD216B_SIMULATION + if(!sfdp_jesd216b_simulation_dw16(&tbuf, &len)) + sfdp_rev_16 = sfdp_rev_15 = 1; /* pretend as SFDP rev 1.6 */ +#endif if (hdrs[i].v_major != 0x01) { msg_cdbg("The chip contains an unknown " "version of the JEDEC flash " "parameters table, skipping it.\n"); - } else if (len != 9 * 4 && len != 4 * 4) { + } else if (len != 16 * 4 && len != 9 * 4 && len != 4 * 4) { msg_cdbg("Length of the mandatory JEDEC SFDP " "parameter table is wrong (%d B), " "skipping it.\n", len); - } else if (sfdp_fill_flash(flash->chip, tbuf, len) == 0) + } else if (sfdp_fill_flash(flash->chip, tbuf, len, sfdp_rev_15) == 0) ret = 1; +#ifdef JESD216B_SIMULATION + if(ret == 1 && !sfdp_jesd216b_simulation_4bait(&tbuf, &len)) + sfdp_parse_4ba_table(flash->chip, tbuf, len); +#endif + } + /* JEDEC SFDP 4-byte address instruction table. From SFDP revision 1.6 only. + This parsing shoukd be called after basic flash parameter table is parsed. */ + else if(sfdp_rev_16 && hdrs[i].id == JEDEC_4BAIT_ID && ret == 1) { + if (hdrs[i].v_major != 0x01) { + msg_cdbg("The chip contains an unknown " + "version of the JEDEC 4-bytes " + "address instruction table, " + "skipping it.\n"); + } + else { /* no result check because this table is optional */ + sfdp_parse_4ba_table(flash->chip, tbuf, len); + } } free(tbuf); } cleanup_hdrs: free(hdrs); free(hbuf); return ret; } + diff -U 5 -N ./flashrom-0.9.7/spi25.c ./flashrom-0.9.7-4ba/spi25.c --- ./flashrom-0.9.7/spi25.c 2013-06-29 01:29:51.000000000 +0400 +++ ./flashrom-0.9.7-4ba/spi25.c 2015-01-07 16:02:57.000000000 +0300 @@ -26,10 +26,11 @@ #include "flash.h" #include "flashchips.h" #include "chipdrivers.h" #include "programmer.h" #include "spi.h" +#include "spi4ba.h" static int spi_rdid(struct flashctx *flash, unsigned char *readarr, int bytes) { static const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID }; int ret; @@ -339,11 +340,11 @@ .writecnt = 0, .writearr = NULL, .readcnt = 0, .readarr = NULL, }}; - + result = spi_send_multicommand(flash, cmds); if (result) { msg_cerr("%s failed during command execution\n", __func__); return result; @@ -376,11 +377,11 @@ .writecnt = 0, .writearr = NULL, .readcnt = 0, .readarr = NULL, }}; - + result = spi_send_multicommand(flash, cmds); if (result) { msg_cerr("%s failed during command execution\n", __func__); return result; @@ -947,11 +948,21 @@ unsigned int len, unsigned int chunksize) { int rc = 0; unsigned int i, j, starthere, lenhere, toread; unsigned int page_size = flash->chip->page_size; + int show_progress = 0; + unsigned int percent_last, percent_current; + /* progress visualizaion init */ + if(len >= MIN_LENGTH_TO_SHOW_READ_PROGRESS) { + msg_cinfo(" "); /* only this space will go to logfile but all strings with \b wont. */ + msg_cinfo("\b 0%%"); + percent_last = percent_current = 0; + show_progress = 1; /* enable progress visualizaion */ + } + /* Warning: This loop has a very unusual condition and body. * The loop needs to go through each page with at least one affected * byte. The lowest page number is (start / page_size) since that * division rounds down. The highest page number we want is the page * where the last byte of the range lives. That last byte has the @@ -965,18 +976,32 @@ starthere = max(start, i * page_size); /* Length of bytes in the range in this page. */ lenhere = min(start + len, (i + 1) * page_size) - starthere; for (j = 0; j < lenhere; j += chunksize) { toread = min(chunksize, lenhere - j); - rc = spi_nbyte_read(flash, starthere + j, buf + starthere - start + j, toread); + rc = (flash->chip->feature_bits & FEATURE_FOUR_BYTE_ADDR) == 0 + ? spi_nbyte_read(flash, starthere + j, buf + starthere - start + j, toread) + : flash->chip->four_bytes_addr_funcs.read_nbyte(flash, starthere + j, + buf + starthere - start + j, toread); if (rc) break; } if (rc) break; + + if(show_progress) { + percent_current = (unsigned int) ((unsigned long long)(starthere + lenhere - start) * 100 / len); + if(percent_current != percent_last) { + msg_cinfo("\b\b\b%2d%%", percent_current); + percent_last = percent_current; + } + } } + if(show_progress && !rc) + msg_cinfo("\b\b\b\b"); /* remove progress percents from the screen */ + return rc; } /* * Write a part of the flash chip. @@ -1010,11 +1035,14 @@ starthere = max(start, i * page_size); /* Length of bytes in the range in this page. */ lenhere = min(start + len, (i + 1) * page_size) - starthere; for (j = 0; j < lenhere; j += chunksize) { towrite = min(chunksize, lenhere - j); - rc = spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite); + rc = (flash->chip->feature_bits & FEATURE_FOUR_BYTE_ADDR) == 0 + ? spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite) + : flash->chip->four_bytes_addr_funcs.program_nbyte(flash, starthere + j, + buf + starthere - start + j, towrite); if (rc) break; while (spi_read_status_register(flash) & SPI_SR_WIP) programmer_delay(10); } @@ -1037,11 +1065,13 @@ { unsigned int i; int result = 0; for (i = start; i < start + len; i++) { - result = spi_byte_program(flash, i, buf[i - start]); + result = (flash->chip->feature_bits & FEATURE_FOUR_BYTE_ADDR) == 0 + ? spi_byte_program(flash, i, buf[i - start]) + : flash->chip->four_bytes_addr_funcs.program_byte(flash, i, buf[i - start]); if (result) return 1; while (spi_read_status_register(flash) & SPI_SR_WIP) programmer_delay(10); } diff -U 5 -N ./flashrom-0.9.7/spi4ba.c ./flashrom-0.9.7-4ba/spi4ba.c --- ./flashrom-0.9.7/spi4ba.c 1970-01-01 03:00:00.000000000 +0300 +++ ./flashrom-0.9.7-4ba/spi4ba.c 2015-01-08 12:20:50.000000000 +0300 @@ -0,0 +1,1020 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2014 Boris Baykov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * SPI chip driver functions for 4-bytes addressing + */ + +#include <string.h> +#include "flash.h" +#include "chipdrivers.h" +#include "spi.h" +#include "programmer.h" +#include "spi4ba.h" + +/* #define MSG_TRACE_4BA_FUNCS 1 */ + +#ifdef MSG_TRACE_4BA_FUNCS +#define msg_trace(...) print(MSG_DEBUG, __VA_ARGS__) +#else +#define msg_trace(...) +#endif + +/* Enter 4-bytes addressing mode (without sending WREN before) */ +int spi_enter_4ba_b7(struct flashctx *flash) +{ + const unsigned char cmd[JEDEC_ENTER_4_BYTE_ADDR_MODE_OUTSIZE] = { JEDEC_ENTER_4_BYTE_ADDR_MODE }; + + msg_trace("-> %s\n", __func__); + + /* Switch to 4-bytes addressing mode */ + return spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); +} + +/* Enter 4-bytes addressing mode with sending WREN before */ +int spi_enter_4ba_b7_we(struct flashctx *flash) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_ENTER_4_BYTE_ADDR_MODE_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_ENTER_4_BYTE_ADDR_MODE }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s\n", __func__); + + /* Switch to 4-bytes addressing mode */ + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution\n", __func__); + } + return result; +} + +/* Write Extended Address Register value */ +int spi_write_extended_address_register(struct flashctx *flash, uint8_t regdata) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_WRITE_EXT_ADDR_REG_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_WRITE_EXT_ADDR_REG, + regdata + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (%02X)\n", __func__, regdata); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution\n", __func__); + return result; + } + return 0; +} + +/* Assign required value of Extended Address Register. This function + keeps last value of the register and writes the register if the + value has to be changed only. */ +int set_extended_address_register(struct flashctx *flash, uint8_t data) +{ + static uint8_t ext_addr_reg_state; /* memory for last register state */ + static int ext_addr_reg_state_valid = 0; + int result; + + if (ext_addr_reg_state_valid == 0 || data != ext_addr_reg_state) { + result = spi_write_extended_address_register(flash, data); + if (result) { + ext_addr_reg_state_valid = 0; + return result; + } + ext_addr_reg_state = data; + ext_addr_reg_state_valid = 1; + } + return 0; +} + +/* Program one flash byte from 4-bytes addressing mode */ +int spi_byte_program_4ba(struct flashctx *flash, unsigned int addr, + uint8_t databyte) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE + 1, + .writearr = (const unsigned char[]){ + JEDEC_BYTE_PROGRAM, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff), + databyte + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X)\n", __func__, addr); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + } + return result; +} + +/* Program flash bytes from 4-bytes addressing mode */ +int spi_nbyte_program_4ba(struct flashctx *flash, unsigned int addr, + uint8_t *bytes, unsigned int len) +{ + int result; + unsigned char cmd[(JEDEC_BYTE_PROGRAM_OUTSIZE + 1) - 1 + 256] = { + JEDEC_BYTE_PROGRAM, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr >> 0) & 0xff + }; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = (JEDEC_BYTE_PROGRAM_OUTSIZE + 1) - 1 + len, + .writearr = cmd, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); + + if (!len) { + msg_cerr("%s called for zero-length write\n", __func__); + return 1; + } + if (len > 256) { + msg_cerr("%s called for too long a write\n", __func__); + return 1; + } + + memcpy(&cmd[(JEDEC_BYTE_PROGRAM_OUTSIZE + 1) - 1], bytes, len); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + } + return result; +} + +/* Read flash bytes from 4-bytes addressing mode */ +int spi_nbyte_read_4ba(struct flashctx *flash, unsigned int addr, + uint8_t *bytes, unsigned int len) +{ + const unsigned char cmd[JEDEC_READ_OUTSIZE + 1] = { + JEDEC_READ, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr >> 0) & 0xff + }; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); + + /* Send Read */ + return spi_send_command(flash, sizeof(cmd), len, cmd, bytes); +} + +/* Program one flash byte with 4-bytes address from ANY mode (3-bytes or 4-bytes) + JEDEC_BYTE_PROGRAM_4BA (12h) instruction is new for 4-bytes addressing flash chips. + The presence of this instruction for an exact chip should be checked + by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */ +int spi_byte_program_4ba_direct(struct flashctx *flash, unsigned int addr, + uint8_t databyte) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_4BA_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BYTE_PROGRAM_4BA, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff), + databyte + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X)\n", __func__, addr); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + } + return result; +} + +/* Program flash bytes with 4-bytes address from ANY mode (3-bytes or 4-bytes) + JEDEC_BYTE_PROGRAM_4BA (12h) instruction is new for 4-bytes addressing flash chips. + The presence of this instruction for an exact chip should be checked + by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */ +int spi_nbyte_program_4ba_direct(struct flashctx *flash, unsigned int addr, + uint8_t *bytes, unsigned int len) +{ + int result; + unsigned char cmd[JEDEC_BYTE_PROGRAM_4BA_OUTSIZE - 1 + 256] = { + JEDEC_BYTE_PROGRAM_4BA, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr >> 0) & 0xff + }; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_4BA_OUTSIZE - 1 + len, + .writearr = cmd, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); + + if (!len) { + msg_cerr("%s called for zero-length write\n", __func__); + return 1; + } + if (len > 256) { + msg_cerr("%s called for too long a write\n", __func__); + return 1; + } + + memcpy(&cmd[JEDEC_BYTE_PROGRAM_4BA_OUTSIZE - 1], bytes, len); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + } + return result; +} + +/* Read flash bytes with 4-bytes address from ANY mode (3-bytes or 4-bytes) + JEDEC_READ_4BA (13h) instruction is new for 4-bytes addressing flash chips. + The presence of this instruction for an exact chip should be checked + by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */ +int spi_nbyte_read_4ba_direct(struct flashctx *flash, unsigned int addr, + uint8_t *bytes, unsigned int len) +{ + const unsigned char cmd[JEDEC_READ_4BA_OUTSIZE] = { + JEDEC_READ_4BA, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr >> 0) & 0xff + }; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); + + /* Send Read */ + return spi_send_command(flash, sizeof(cmd), len, cmd, bytes); +} + +/* Program one flash byte using Extended Address Register + from 3-bytes addressing mode */ +int spi_byte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, + uint8_t databyte) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BYTE_PROGRAM, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff), + databyte + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X)\n", __func__, addr); + + result = set_extended_address_register(flash, (addr >> 24) & 0xff); + if (result) + return result; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + } + return result; +} + +/* Program flash bytes using Extended Address Register + from 3-bytes addressing mode */ +int spi_nbyte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, + uint8_t *bytes, unsigned int len) +{ + int result; + unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = { + JEDEC_BYTE_PROGRAM, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr >> 0) & 0xff + }; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + len, + .writearr = cmd, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); + + if (!len) { + msg_cerr("%s called for zero-length write\n", __func__); + return 1; + } + if (len > 256) { + msg_cerr("%s called for too long a write\n", __func__); + return 1; + } + + memcpy(&cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1], bytes, len); + + result = set_extended_address_register(flash, (addr >> 24) & 0xff); + if (result) + return result; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + } + return result; +} + +/* Read flash bytes using Extended Address Register + from 3-bytes addressing mode */ +int spi_nbyte_read_4ba_ereg(struct flashctx *flash, unsigned int addr, + uint8_t *bytes, unsigned int len) +{ + int result; + const unsigned char cmd[JEDEC_READ_OUTSIZE] = { + JEDEC_READ, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr >> 0) & 0xff + }; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); + + result = set_extended_address_register(flash, (addr >> 24) & 0xff); + if (result) + return result; + + /* Send Read */ + return spi_send_command(flash, sizeof(cmd), len, cmd, bytes); +} + +/* Chooser for erase function by instruction opcode for block eraser instructions + to work with 4-bytes addressing flash chips. This chooser is called from sfdp.c + during parse of 8th & 9th dwords of SFDP Basic Flash Parameter Table */ +erasefunc_t *spi_get_erasefn_from_opcode_4ba(uint8_t opcode) +{ + msg_trace("-> %s\n", __func__); + + switch(opcode){ + case 0xff: + case 0x00: + /* Not specified, assuming "not supported". */ + return NULL; + case 0x20: + return &spi_block_erase_20_4ba_selector; /* selector */ + case 0x52: + return &spi_block_erase_52_4ba_selector; /* selector */ + case 0x60: + return &spi_block_erase_60; + case 0x62: + return &spi_block_erase_62; + case 0xc7: + return &spi_block_erase_c7; + case 0xd8: + return &spi_block_erase_d8_4ba_selector; /* selector */ + case 0x50: + case 0x81: + case 0xc4: + case 0xd7: + case 0xdb: + msg_cinfo("%s: erase opcode (0x%02x) doesn't have its 4-bytes addressing version." + " Please report this at flashrom(a)flashrom.org\n", __func__, opcode); + return NULL; + default: + msg_cinfo("%s: unknown erase opcode (0x%02x). Please report " + "this at flashrom(a)flashrom.org\n", __func__, opcode); + return NULL; + } +} + +/* Selector for 4k eraser that chooses between 4-bytes addressing mode + and use of Extended Address Register from 3-bytes addressing mode */ +int spi_block_erase_20_4ba_selector(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + msg_trace("-> %s\n", __func__); + + return (flash->chip->feature_bits & FEATURE_NEED_USE_EXTENDED_ADDR_REG) ? + spi_block_erase_20_4ba_ereg(flash, addr, blocklen) : + spi_block_erase_20_4ba(flash, addr, blocklen); +} + +/* Erases 4 KB of flash from 4-bytes addressing mode */ +int spi_block_erase_20_4ba(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_SE_OUTSIZE + 1, + .writearr = (const unsigned char[]){ + JEDEC_SE, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 15-800 ms, so wait in 10 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(10 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Selector for 32k eraser that chooses between 4-bytes addressing mode + and use of Extended Address Register from 3-bytes addressing mode */ +int spi_block_erase_52_4ba_selector(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + msg_trace("-> %s\n", __func__); + + return (flash->chip->feature_bits & FEATURE_NEED_USE_EXTENDED_ADDR_REG) ? + spi_block_erase_52_4ba_ereg(flash, addr, blocklen) : + spi_block_erase_52_4ba(flash, addr, blocklen); +} + +/* Erases 32 KB of flash from 4-bytes addressing mode */ +int spi_block_erase_52_4ba(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_52_OUTSIZE + 1, + .writearr = (const unsigned char[]){ + JEDEC_BE_52, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(100 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Selector for 64k eraser that chooses between 4-bytes addressing mode + and use of Extended Address Register from 3-bytes addressing mode */ +int spi_block_erase_d8_4ba_selector(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + msg_trace("-> %s\n", __func__); + + return (flash->chip->feature_bits & FEATURE_NEED_USE_EXTENDED_ADDR_REG) ? + spi_block_erase_d8_4ba_ereg(flash, addr, blocklen) : + spi_block_erase_d8_4ba(flash, addr, blocklen); +} + +/* Erases 64 KB of flash from 4-bytes addressing mode */ +int spi_block_erase_d8_4ba(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_D8_OUTSIZE + 1, + .writearr = (const unsigned char[]){ + JEDEC_BE_D8, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(100 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Erases 4 KB of flash using Extended Address Register + from 3-bytes addressing mode */ +int spi_block_erase_20_4ba_ereg(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_SE_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_SE, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = set_extended_address_register(flash, (addr >> 24) & 0xff); + if (result) + return result; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 15-800 ms, so wait in 10 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(10 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Erases 32 KB of flash using Extended Address Register + from 3-bytes addressing mode */ +int spi_block_erase_52_4ba_ereg(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_52_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BE_52, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = set_extended_address_register(flash, (addr >> 24) & 0xff); + if (result) + return result; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(100 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Erases 64 KB of flash using Extended Address Register + from 3-bytes addressing mode */ +int spi_block_erase_d8_4ba_ereg(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_D8_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BE_D8, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = set_extended_address_register(flash, (addr >> 24) & 0xff); + if (result) + return result; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(100 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Chooser for erase function by instruction opcode for block eraser instructions + which can be used from ANY mode (3-bytes or 4-bytes). This chooser is called + from sfdp.c during parse of SFDP 4-Bytes Address Instruction Table (JESD216B) */ +erasefunc_t *spi_get_erasefn_from_opcode_4ba_direct(uint8_t opcode) +{ + msg_trace("-> %s\n", __func__); + + switch(opcode){ + case 0xff: + case 0x00: + /* Not specified, assuming "not supported". */ + return NULL; + case 0x21: + return &spi_block_erase_21_4ba_direct; /* direct */ + case 0x5C: + return &spi_block_erase_5c_4ba_direct; /* direct */ + case 0xdc: + return &spi_block_erase_dc_4ba_direct; /* direct */ + default: + msg_cinfo("%s: unknown erase opcode (0x%02x). Please report " + "this at flashrom(a)flashrom.org\n", __func__, opcode); + return NULL; + } +} + +/* Erase 4 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) + JEDEC_SE_4BA (21h) instruction is new for 4-bytes addressing flash chips. + The presence of this instruction for an exact chip should be checked + by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */ +int spi_block_erase_21_4ba_direct(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_SE_4BA_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_SE_4BA, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 15-800 ms, so wait in 10 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(10 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Erase 32 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) + JEDEC_BE_5C_4BA (5Ch) instruction is new for 4-bytes addressing flash chips. + The presence of this instruction for an exact chip should be checked + by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */ +int spi_block_erase_5c_4ba_direct(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_5C_4BA_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BE_5C_4BA, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(100 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Erase 64 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) + JEDEC_BE_DC_4BA (DCh) instruction is new for 4-bytes addressing flash chips. + The presence of this instruction for an exact chip should be checked + by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */ +int spi_block_erase_dc_4ba_direct(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_DC_4BA_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BE_DC_4BA, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(100 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} diff -U 5 -N ./flashrom-0.9.7/spi4ba.h ./flashrom-0.9.7-4ba/spi4ba.h --- ./flashrom-0.9.7/spi4ba.h 1970-01-01 03:00:00.000000000 +0300 +++ ./flashrom-0.9.7-4ba/spi4ba.h 2015-01-07 20:36:00.000000000 +0300 @@ -0,0 +1,158 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2014 Boris Baykov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +/* + * JEDEC flash chips instructions for 4-bytes addressing + * SPI chip driver functions for 4-bytes addressing + */ + +#ifndef __SPI_4BA_H__ +#define __SPI_4BA_H__ 1 + +/* Read the memory with 4-byte address + From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ +#define JEDEC_READ_4BA 0x13 +#define JEDEC_READ_4BA_OUTSIZE 0x05 +/* JEDEC_READ_4BA_INSIZE : any length */ + +/* Write memory byte with 4-byte address + From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ +#define JEDEC_BYTE_PROGRAM_4BA 0x12 +#define JEDEC_BYTE_PROGRAM_4BA_OUTSIZE 0x06 +#define JEDEC_BYTE_PROGRAM_4BA_INSIZE 0x00 + +/* Sector Erase 0x21 (with 4-byte address), usually 4k size. + From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ +#define JEDEC_SE_4BA 0x21 +#define JEDEC_SE_4BA_OUTSIZE 0x05 +#define JEDEC_SE_4BA_INSIZE 0x00 + +/* Block Erase 0x5C (with 4-byte address), usually 32k size. + From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ +#define JEDEC_BE_5C_4BA 0x5C +#define JEDEC_BE_5C_4BA_OUTSIZE 0x05 +#define JEDEC_BE_5C_4BA_INSIZE 0x00 + +/* Block Erase 0xDC (with 4-byte address), usually 64k size. + From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ +#define JEDEC_BE_DC_4BA 0xdc +#define JEDEC_BE_DC_4BA_OUTSIZE 0x05 +#define JEDEC_BE_DC_4BA_INSIZE 0x00 + +/* Enter 4-byte Address Mode */ +#define JEDEC_ENTER_4_BYTE_ADDR_MODE 0xB7 +#define JEDEC_ENTER_4_BYTE_ADDR_MODE_OUTSIZE 0x01 +#define JEDEC_ENTER_4_BYTE_ADDR_MODE_INSIZE 0x00 + +/* Exit 4-byte Address Mode */ +#define JEDEC_EXIT_4_BYTE_ADDR_MODE 0xE9 +#define JEDEC_EXIT_4_BYTE_ADDR_MODE_OUTSIZE 0x01 +#define JEDEC_EXIT_4_BYTE_ADDR_MODE_INSIZE 0x00 + +/* Write Extended Address Register */ +#define JEDEC_WRITE_EXT_ADDR_REG 0xC5 +#define JEDEC_WRITE_EXT_ADDR_REG_OUTSIZE 0x02 +#define JEDEC_WRITE_EXT_ADDR_REG_INSIZE 0x00 + +/* Read Extended Address Register */ +#define JEDEC_READ_EXT_ADDR_REG 0xC8 +#define JEDEC_READ_EXT_ADDR_REG_OUTSIZE 0x01 +#define JEDEC_READ_EXT_ADDR_REG_INSIZE 0x01 + + +/* JEDEC Basic Flash Parameters Table definition */ +#define JEDEC_BFPT_ID 0xFF00 + +/* JEDEC Basic Flash Parameters Table 16th dword according to JESD216B */ +/* 16th dword of BFPT, bits 24:31 (Enter 4-Byte Addressing) */ +#define JEDEC_BFPT_DW16_ENTER_B7 (1UL << 24) +#define JEDEC_BFPT_DW16_ENTER_B7_WE (1UL << 25) +#define JEDEC_BFPT_DW16_ENTER_EXTENDED_ADDR_REG (1UL << 26) +#define JEDEC_BFPT_DW16_ENTER_BANK_ADDR_REG_EN_BIT (1UL << 27) +#define JEDEC_BFPT_DW16_ENTER_NV_CONFIG_REG (1UL << 28) +#define JEDEC_BFPT_DW16_VENDOR_SET (1UL << 29) +#define JEDEC_BFPT_DW16_4_BYTES_ADDRESS_ONLY (1UL << 30) +#define JEDEC_BFPT_DW16_ENTER_RESERVED (1UL << 31) +/* 16th dword of BFPT, bits 14:23 (Exit 4-Byte Addressing) */ +#define JEDEC_BFPT_DW16_EXIT_E9 (1UL << 14) +#define JEDEC_BFPT_DW16_EXIT_E9_WE (1UL << 15) +#define JEDEC_BFPT_DW16_EXIT_EXTENDED_ADDR_REG (1UL << 16) +#define JEDEC_BFPT_DW16_EXIT_BANK_ADDR_REG_EN_BIT (1UL << 17) +#define JEDEC_BFPT_DW16_EXIT_NV_CONFIG_REG (1UL << 18) +#define JEDEC_BFPT_DW16_EXIT_HARD_RESET (1UL << 19) +#define JEDEC_BFPT_DW16_EXIT_SOFT_RESET (1UL << 20) +#define JEDEC_BFPT_DW16_EXIT_POWER_CYCLE (1UL << 21) +#define JEDEC_BFPT_DW16_EXIT_RESERVED_1 (1UL << 22) +#define JEDEC_BFPT_DW16_EXIT_RESERVED_2 (1UL << 23) + +/* JEDEC 4-Bytes Addressing Table 1st dword according to JESD216B */ +#define JEDEC_4BAIT_ID 0xFF84 +#define JEDEC_4BAIT_READ_SUPPORT (1UL << 0) +#define JEDEC_4BAIT_PROGRAM_SUPPORT (1UL << 6) +#define JEDEC_4BAIT_ERASE_TYPE_1_SUPPORT (1UL << 9) +#define JEDEC_4BAIT_ERASE_TYPE_2_SUPPORT (1UL << 10) +#define JEDEC_4BAIT_ERASE_TYPE_3_SUPPORT (1UL << 11) +#define JEDEC_4BAIT_ERASE_TYPE_4_SUPPORT (1UL << 12) + +/* read/write flash bytes in 4-bytes addressing mode */ +int spi_byte_program_4ba(struct flashctx *flash, unsigned int addr, uint8_t databyte); +int spi_nbyte_program_4ba(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); +int spi_nbyte_read_4ba(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); + +/* read/write flash bytes with 4-bytes address from any mode (3-byte or 4-byte) */ +int spi_byte_program_4ba_direct(struct flashctx *flash, unsigned int addr, uint8_t databyte); +int spi_nbyte_program_4ba_direct(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); +int spi_nbyte_read_4ba_direct(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); + +/* read/write flash bytes from 3-bytes addressing mode using extended address register */ +int spi_byte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, uint8_t databyte); +int spi_nbyte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); +int spi_nbyte_read_4ba_ereg(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); + +/* enter 4-bytes addressing mode */ +int spi_enter_4ba_b7(struct flashctx *flash); +int spi_enter_4ba_b7_we(struct flashctx *flash); + +/* erase functions choosers for 4-bytes addressing mode */ +erasefunc_t *spi_get_erasefn_from_opcode_4ba(uint8_t opcode); +erasefunc_t *spi_get_erasefn_from_opcode_4ba_direct(uint8_t opcode); + +/* erase flash bytes in 4-bytes addressing mode */ +int spi_block_erase_20_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_52_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_d8_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + +/* erase flash bytes from 3-bytes addressing mode using extended address register */ +int spi_block_erase_20_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_52_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_d8_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + +/* selection of erase function between 4-bytes addressing mode and use of extended address register */ +int spi_block_erase_20_4ba_selector(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_52_4ba_selector(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_d8_4ba_selector(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + +/* erase flash bytes with 4-bytes address from any mode (3-byte or 4-byte) */ +int spi_block_erase_21_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_5c_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_dc_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + + +#endif /* __SPI_4BA_H__ */ diff -U 5 -N ./flashrom-0.9.7/spi.c ./flashrom-0.9.7-4ba/spi.c --- ./flashrom-0.9.7/spi.c 2012-09-21 16:52:50.000000000 +0400 +++ ./flashrom-0.9.7-4ba/spi.c 2015-01-07 16:06:55.000000000 +0300 @@ -109,11 +109,15 @@ /* Check if the chip fits between lowest valid and highest possible * address. Highest possible address with the current SPI implementation * means 0xffffff, the highest unsigned 24bit number. */ addrbase = spi_get_valid_read_addr(flash); - if (addrbase + flash->chip->total_size * 1024 > (1 << 24)) { + + /* Show flash chip size warning if flash chip doesn't support + 4-Bytes Addressing mode and last address excedes 24 bits */ + if (!(flash->chip->feature_bits & FEATURE_FOUR_BYTE_ADDR) && + addrbase + flash->chip->total_size * 1024 > (1 << 24)) { msg_perr("Flash chip size exceeds the allowed access window. "); msg_perr("Read will probably fail.\n"); /* Try to get the best alignment subject to constraints. */ addrbase = (1 << 24) - flash->chip->total_size * 1024; }

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[PATCH 1/2] Read/erase/program 4-bytes addressing SPI flash chips 32MB+ for build 0.9.7-r1861
by Boris Baykov 09 Jan '15

09 Jan '15

Current patch is for the last 0.9.7-r1861 build taken by SVN from svn://flashrom.org. The patch is made by SVN diff. Two same patches for different builds (one patch per letter) ------------------------------------------------------------ [1/2] Patch for Flashrom 0.9.7 (build 1861) by SVN diff [2/2] Patch for last 0.9.7 release (build 1711) by Linux diff Brief description ----------------- This patch adds ability to read, write and erase flash chips which require 4-bytes (32-bit) addressing to access to them. These are 32MB (256Mb) and larger new flash chips. Flashrom with this patch can support and program all (or most of all) of them. Besides of manually definable chips in flashchips.c this patch adds compliance to new JEDEC JESD216B standard which describes SFDP revision 1.6 procedure to read flash chip 4-bytes addressing details. Full description ---------------- This patch includes code for three types of 4-byte addressing: 1. Flash chip can be switched to 4-bytes addressing mode and then all read/erase/program instructions will be switched from 3-bytes mode to 4-bytes mode. So, well known instructions like 03h (Read), 02h (Program) and 20h,52h,D8h (Erase) are becoming one byte longer and accept 4-bytes address instead of 3-bytes. 4-bytes addressing mode is entered by the instruction B7h with preceding Write Enable (WREN). This is default method. 2. Also Flash chip data with addresses more than 24-bit field can address may be accessed by use of Extended Address Register that has 1-byte size and stores high byte of 32-bit address. So, we read flash from old 3-bytes addressing mode and write high byte of address to special register. Then we have access to full memory of a chip. Some chips may support this method only. 3. Also some new commands avalable and implemented. Large size flash chips support special instructions to use 4-bytes address directly from 3-bytes addressing mode and without do switching to 4-bytes mode. There are 13h (4BA Read), 12h (4BA Program) and 21h,5Ch,DCh (4BA Erase), correspondingly. However not all these commands are supported by all large flash chips. Some chips support 13h only, some 13h,12h,21h and DCh, but not 5Ch. This depends on the manufacturer of the chip. The patch adds code for all 3 types of 4-bytes address access and the exact method should be choosen by person who will manage to add new large chips to flashchips.c source file. I've added one new flash chip: Winbond W25Q256FV (32MB) because this is the only chip I have now for testing. Besides of manual including of new chips to Flashrom we may use SFDP procedure to discover parameters of the exact flash chip. More than a year before JEDEC released new standard JESD216 (revision B) which describes in detail how to receive 4-bytes addressing settings from the chip. This patch provides new code to add compliance to JESD216B to Flashrom. This means that Flashrom now can automatically detect 4-bytes addressing features of large flash chips and use them to access data. However not all thing are so good. Unfortunately JESD216B had come to manufacturer's production lines just 2-3 months ago. So, we have many chips that have large size requires 32-bit addressing but their SFDP tables have revision lower than 1.6 (described in JESD216B standard). For example my W25Q256FV returns SFDP info with revision 1.0, first one :-) This situation leads us to requirement to try to work now without new SFDP info. And it's implemented in the patch too. To test my parser code for SFDP revision 1.6 (from JESD216B) I've added some simulation code to sfdp.c. This code builds fake SFDP 1.6 tables in memory and passes them to the SFDP parser. Surely this simulation code is switched off by default and can be activated via hidden define on the top of sfdp.c Also I've added progress visualization for read, erase and write operations. It's turned out that seeing progress is essential for reading and especially writing 32 MB оf data via SPI. The operation can take more then 10 minutes on 15 MHz frequency of SPI. So, it's good to see its progress. I've added percents and slightly modified cli_output.c to send percents to screen only but not to logfile. Testing results --------------- Both patches are tested with Winbond W25Q256FV flash chip using Olimex ARM-USB-OCD-H programmer. Read, Erase and Program functions are fully tested for 4-bytes addressing type 1 (4-bytes mode), type 2 (extended addr. register) and partially tested for type 3 (new 4-bytes instructions with 4-bytes address). My W25Q256FV has support for 4BA_Read (13h) only, but doesn't support 4BA_Program (12h) and 4BA_Erase instructions. So, direct 4BA program and erase should be tested after. Also I should make an excuse about testing of SFDP rev 1.6 parser. I've tested it as good as I can using the simulation code I described above but I'm not able to test it on real flash chips because I don't have a chip complied to JESD216B with SFDP 1.6 now. This should be tested later too. Patched files ------------- chipdrivers.h - added functions declarations for spi4ba.c cli_output.c - print() patched to skip strings which are starting from '\b' to prevent writing progress percents to logfile flash.h - feature definitions added - added set of 4-bytes address functions to flashchip structure definition - added type field to block_eraser structure - added some definitions for progress visialization flashchips.c - added definition for Winbond W25Q256BV/W25Q256FV chips flashrom.c - added switch to 4-bytes addressing more for chips which support it - added progress visualization for erase/write (essensial for 32MB+ chips) - changed in address print %06x to %08x to support 32MB+ chips - added line to the flashrom's banner about this patch (temporary) Makefile - added spi4ba.c serprog.c - added 4-bytes addressing spi_nbyte_read call to serprog_spi_read spi.c - fixed flash chip size check in spi_chip_read spi25.c - added 4-bytes addressing spi_nbyte_read call to spi_read_chunked - added 4-bytes addressing spi_nbyte_program call to spi_write_chunked - added 4-bytes addressing spi_byte_program call to spi_chip_write_1 - added progress visualization for read operation (essensial for 32MB+ chips) sfdp.c - added compliance to JEDEC JESD216B standard (SFDP revision 1.6) - added parse of SFDP 4-Bytes Addressing features (probe_spi_sfdp,sfdp_fill_flash) - added parse of SFDP 4-Bytes Addressing Instruction Table (sfdp_parse_4ba_table) - added choosing of block_erasers for 4-bytes addressing (sfdp_*_uniform_eraser*) - added exact flash page_size recognision from 11th dword in SFDP rev 1.6 - added fix for Micron chips to read 16th dword stating from SFDP revision 1.5 - added simulation of JESD216B for any flash chips (just for testing) Added files ----------- spi4ba.h - definitions for 4-bytes addressing JEDEC commands - definitions for 16th dword bits of SFDP Basic Flash Param Table (JESD216B) - definitions for SFDP 4-Bytes Addressing Instruction Table (JESD216B) - functions declarations from spi4ba.c (same as in chipdrivers.h, just to see) spi4ba.c - functions for enter 4-bytes addressing mode - functions for write Extended Address Register - functions for read/write/erase in 4-bytes addressing mode - functions for read/write/erase with Extended Address Register - functions for read/write/erase directly with 4-bytes address (from any mode) - functions to choose block_eraser by opcode for 4-bytes addressing for sfdp.c - functions to select proper block_eraser (ext.reg or 4-bytes addr) for sfdp.c Signed-off-by: Boris Baykov <dev(a)borisbaykov.com>, Russia, Jan 2014 --- Index: Makefile =================================================================== --- Makefile (revision 1861) +++ Makefile (working copy) @@ -355,11 +355,11 @@ ############################################################################### # Flash chip drivers and bus support infrastructure. CHIP_OBJS = jedec.o stm50.o w39.o w29ee011.o \ sst28sf040.o 82802ab.o \ - sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o spi25_statusreg.o \ + sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o spi25_statusreg.o spi4ba.o \ opaque.o sfdp.o en29lv640b.o at45db.o ############################################################################### # Library code. Index: chipdrivers.h =================================================================== --- chipdrivers.h (revision 1861) +++ chipdrivers.h (working copy) @@ -192,6 +192,33 @@ /* en29lv640b.c */ int probe_en29lv640b(struct flashctx *flash); int write_en29lv640b(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); +/* spi4ba.c */ +int spi_enter_4ba_b7(struct flashctx *flash); +int spi_enter_4ba_b7_we(struct flashctx *flash); +int spi_byte_program_4ba(struct flashctx *flash, unsigned int addr, uint8_t databyte); +int spi_nbyte_program_4ba(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len); +int spi_nbyte_read_4ba(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); +int spi_byte_program_4ba_direct(struct flashctx *flash, unsigned int addr, uint8_t databyte); +int spi_nbyte_program_4ba_direct(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len); +int spi_nbyte_read_4ba_direct(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); +int spi_byte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, uint8_t databyte); +int spi_nbyte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len); +int spi_nbyte_read_4ba_ereg(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); +erasefunc_t *spi_get_erasefn_from_opcode_4ba(uint8_t opcode); +erasefunc_t *spi_get_erasefn_from_opcode_4ba_direct(uint8_t opcode); +int spi_block_erase_20_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_20_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_20_4ba_selector(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_52_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_52_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_52_4ba_selector(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_d8_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_d8_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_d8_4ba_selector(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_21_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_5c_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_dc_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + #endif /* !__CHIPDRIVERS_H__ */ Index: cli_output.c =================================================================== --- cli_output.c (revision 1861) +++ cli_output.c (working copy) @@ -88,11 +88,12 @@ * time-critical operations. Don't slow them down by flushing. */ if (level != MSG_SPEW) fflush(output_type); } #ifndef STANDALONE - if ((level <= verbose_logfile) && logfile) { + /* skip of msgs starting from '\b' added to skip progress percents */ + if ((level <= verbose_logfile) && logfile && (!fmt || fmt[0] != '\b')) { va_start(ap, fmt); ret = vfprintf(logfile, fmt, ap); va_end(ap); if (level != MSG_SPEW) fflush(logfile); Index: flash.h =================================================================== --- flash.h (revision 1861) +++ flash.h (working copy) @@ -119,10 +119,18 @@ #define FEATURE_WRSR_EWSR (1 << 6) #define FEATURE_WRSR_WREN (1 << 7) #define FEATURE_WRSR_EITHER (FEATURE_WRSR_EWSR | FEATURE_WRSR_WREN) #define FEATURE_OTP (1 << 8) #define FEATURE_QPI (1 << 9) +/* Feature bits used for 4-bytes addressing mode */ +#define FEATURE_FOUR_BYTE_ADDR (1 << 10) +#define FEATURE_FOUR_BYTE_ADDR_ONLY (1 << 11) +#define FEATURE_NEED_ENTER_4BA_FOR_READ (1 << 12) +#define FEATURE_NEED_ENTER_4BA_FOR_WRITE (1 << 13) +#define FEATURE_NEED_ENTER_4BA_FOR_ERASE (1 << 14) +#define FEATURE_NEED_USE_EXTENDED_ADDR_REG (1 << 15) +#define FEATURE_ENTER_4BA_ALL (FEATURE_NEED_ENTER_4BA_FOR_READ | FEATURE_NEED_ENTER_4BA_FOR_WRITE | FEATURE_NEED_ENTER_4BA_FOR_ERASE | FEATURE_NEED_USE_EXTENDED_ADDR_REG) enum test_state { OK = 0, NT = 1, /* Not tested */ BAD, /* Known to not work */ @@ -163,10 +171,18 @@ unsigned int total_size; /* Chip page size in bytes */ unsigned int page_size; int feature_bits; + /* set of function pointers to use in 4-bytes addressing mode */ + struct four_bytes_addr_funcs_set { + int (*enter_4ba) (struct flashctx *flash); + int (*read_nbyte) (struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); + int (*program_byte) (struct flashctx *flash, unsigned int addr, const uint8_t databyte); + int (*program_nbyte) (struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len); + } four_bytes_addr_funcs; + /* Indicate how well flashrom supports different operations of this flash chip. */ struct tested { enum test_state probe; enum test_state read; enum test_state erase; @@ -186,10 +202,11 @@ * The first one that fits will be chosen. There is currently no way to * influence that behaviour. For testing just comment out the other * elements or set the function pointer to NULL. */ struct block_eraser { + int type; /* eraser type 1,2,3 or 4 */ struct eraseblock { unsigned int size; /* Eraseblock size in bytes */ unsigned int count; /* Number of contiguous blocks with that size */ } eraseblocks[NUM_ERASEREGIONS]; /* a block_erase function should try to erase one block of size @@ -337,10 +354,15 @@ #define msg_cdbg2(...) print(MSG_DEBUG2, __VA_ARGS__) /* chip debug2 */ #define msg_gspew(...) print(MSG_SPEW, __VA_ARGS__) /* general debug spew */ #define msg_pspew(...) print(MSG_SPEW, __VA_ARGS__) /* programmer debug spew */ #define msg_cspew(...) print(MSG_SPEW, __VA_ARGS__) /* chip debug spew */ +/* Read progress will be shown for reads more than 256KB */ +#define MIN_LENGTH_TO_SHOW_READ_PROGRESS 256 * 1024 +/* Read progress will be shown for erases and writes more than 64KB */ +#define MIN_LENGTH_TO_SHOW_ERASE_AND_WRITE_PROGRESS 64 * 1024 + /* layout.c */ int register_include_arg(char *name); int process_include_args(void); int read_romlayout(const char *name); int normalize_romentries(const struct flashctx *flash); Index: flashchips.c =================================================================== --- flashchips.c (revision 1861) +++ flashchips.c (working copy) @@ -13282,10 +13282,59 @@ .voltage = {2700, 3600}, }, { .vendor = "Winbond", + .name = "W25Q256.V", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q256_V, + .total_size = 32768, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_FOUR_BYTE_ADDR | + FEATURE_NEED_ENTER_4BA_FOR_ERASE | FEATURE_NEED_ENTER_4BA_FOR_WRITE, + .four_bytes_addr_funcs = + { + .enter_4ba = spi_enter_4ba_b7_we, /* enter 4-bytes addressing mode by CMD B7 + WREN */ + .read_nbyte = spi_nbyte_read_4ba_direct, /* read directly from any mode, no need to enter 4ba */ + .program_byte = spi_byte_program_4ba, /* write from 4-bytes addressing mode */ + .program_nbyte = spi_nbyte_program_4ba /* write from 4-bytes addressing mode */ + }, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20_4ba, /* erases 4k from 4-bytes addressing mode */ + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_52_4ba, /* erases 32k from 4-bytes addressing mode */ + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8_4ba, /* erases 64k from 4-bytes addressing mode */ + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "Winbond", .name = "W25Q20.W", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, .model_id = WINBOND_NEX_W25Q20_W, .total_size = 256, Index: flashrom.c =================================================================== --- flashrom.c (revision 1861) +++ flashrom.c (working copy) @@ -1366,12 +1366,12 @@ "non-empty erase function. Not an error.\n"); if (!done) continue; if (done != chip->total_size * 1024) { msg_gerr("ERROR: Flash chip %s erase function %i " - "region walking resulted in 0x%06x bytes total," - " expected 0x%06x bytes. Please report a bug at" + "region walking resulted in 0x%08x bytes total," + " expected 0x%08x bytes. Please report a bug at" " flashrom(a)flashrom.org\n", chip->name, k, done, chip->total_size * 1024); ret = 1; } if (!eraser.block_erase) @@ -1460,29 +1460,52 @@ { int i, j; unsigned int start = 0; unsigned int len; struct block_eraser eraser = flash->chip->block_erasers[erasefunction]; + int show_progress = 0; + unsigned int percent_last, percent_current; + unsigned long size = flash->chip->total_size * 1024; + + /* progress visualizaion init */ + if(size >= MIN_LENGTH_TO_SHOW_ERASE_AND_WRITE_PROGRESS) { + msg_cinfo(" "); /* only this space will go to logfile but all strings with \b wont. */ + msg_cinfo("\b 0%%"); + percent_last = percent_current = 0; + show_progress = 1; /* enable progress visualizaion */ + } for (i = 0; i < NUM_ERASEREGIONS; i++) { /* count==0 for all automatically initialized array * members so the loop below won't be executed for them. */ len = eraser.eraseblocks[i].size; for (j = 0; j < eraser.eraseblocks[i].count; j++) { /* Print this for every block except the first one. */ if (i || j) msg_cdbg(", "); - msg_cdbg("0x%06x-0x%06x", start, + msg_cdbg("0x%08x-0x%08x", start, start + len - 1); if (do_something(flash, start, len, param1, param2, eraser.block_erase)) { return 1; } start += len; + + if(show_progress) { + percent_current = (unsigned int) ((unsigned long long)start * 100 / size); + if(percent_current != percent_last) { + msg_cinfo("\b\b\b%2d%%", percent_current); + percent_last = percent_current; + } + } } } + + if(show_progress) + msg_cinfo("\b\b\b\b"); /* remove progress percents from the screen */ + msg_cdbg("\n"); return 0; } static int check_block_eraser(const struct flashctx *flash, int k, int log) @@ -1735,12 +1758,15 @@ } void print_version(void) { msg_ginfo("flashrom v%s", flashrom_version); + msg_ginfo("-4ba"); /* temporary to indicate that version is patched */ print_sysinfo(); msg_ginfo("\n"); + /* temporary to indicate that version is patched */ + msg_ginfo("with patch for support SPI flash chips with 4-bytes addressing\n"); } void print_banner(void) { msg_ginfo("flashrom is free software, get the source code at " @@ -1934,10 +1960,42 @@ * erase and write. */ if (flash->chip->unlock) flash->chip->unlock(flash); + if(flash->chip->feature_bits & FEATURE_FOUR_BYTE_ADDR) { + /* Switching to 4-Bytes Addressing mode if flash chip supports it + and selected operation requires 4-Bytes Addressing mode + (no need for direct and ext.addr.reg operation) */ + if(((read_it || verify_it) && (flash->chip->feature_bits & FEATURE_NEED_ENTER_4BA_FOR_READ)) || + ((erase_it || write_it) && (flash->chip->feature_bits & (FEATURE_NEED_ENTER_4BA_FOR_READ | + FEATURE_NEED_ENTER_4BA_FOR_WRITE | FEATURE_NEED_ENTER_4BA_FOR_ERASE))) ) { + + if (!flash->chip->four_bytes_addr_funcs.enter_4ba) { + msg_cerr("No function for Enter 4-bytes addressing mode for this flash chip.\n" + "Please report to flashrom(a)flashrom.org\n"); + return 1; + } + + if(flash->chip->four_bytes_addr_funcs.enter_4ba(flash)) { + msg_cerr("Switching to 4-bytes addressing mode failed!\n"); + return 1; + } + + msg_cdbg("Switched to 4-bytes addressing mode.\n"); + } + /* Do not switch to 4-Bytes Addressing mode if using Extended Address Register */ + else if(flash->chip->feature_bits & FEATURE_NEED_USE_EXTENDED_ADDR_REG) { + msg_cdbg("Using 4-bytes addressing with extended address register.\n"); + } + /* Do not switch to 4-Bytes Addressing mode if all instructions are direct-4BA + or if the flash chip is 4-Bytes Addressing Only and always in 4BA-mode */ + else { + msg_cdbg2("No need to switch to 4-bytes addressing mode.\n"); + } + } + if (read_it) { return read_flash_to_file(flash, filename); } oldcontents = malloc(size); Index: serprog.c =================================================================== --- serprog.c (revision 1861) +++ serprog.c (working copy) @@ -933,11 +933,14 @@ unsigned int i, cur_len; const unsigned int max_read = spi_master_serprog.max_data_read; for (i = 0; i < len; i += cur_len) { int ret; cur_len = min(max_read, (len - i)); - ret = spi_nbyte_read(flash, start + i, buf + i, cur_len); + ret = (flash->chip->feature_bits & FEATURE_FOUR_BYTE_ADDR) == 0 + ? spi_nbyte_read(flash, start + i, buf + i, cur_len) + : flash->chip->four_bytes_addr_funcs.read_nbyte(flash, + start + i, buf + i, cur_len); if (ret) return ret; } return 0; } Index: sfdp.c =================================================================== --- sfdp.c (revision 1861) +++ sfdp.c (working copy) @@ -1,9 +1,10 @@ /* * This file is part of the flashrom project. * * Copyright (C) 2011-2012 Stefan Tauner + * Copyright (C) 2014 Boris Baykov * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * @@ -15,17 +16,32 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* + * History of changes: + * 05/01/2014 Added compliance to JESD216B standard and SFDP revision 1.6 + * 07/01/2014 Modified to support SFDP revision 1.5 (for Micron flash chips) + */ + #include <stdint.h> #include <stdlib.h> #include <string.h> #include "flash.h" #include "spi.h" +#include "spi4ba.h" #include "chipdrivers.h" +/* Default four bytes addressing behavior: + 1) 4-Bytes Addressing Mode (FBA_USE_EXT_ADDR_REG_BY_DEFAULT not defined) + 2) 3-bytes mode with Ext.Addr.Register (FBA_USE_EXT_ADDR_REG_BY_DEFAULT defined) */ +/* #define FBA_USE_EXT_ADDR_REG_BY_DEFAULT 1 */ + +/* For testing purposes only. Tests JESD216B SFDP compliance without proper flash chip */ +/* #define JESD216B_SIMULATION 1 */ + static int spi_sfdp_read_sfdp_chunk(struct flashctx *flash, uint32_t address, uint8_t *buf, int len) { int i, ret; uint8_t *newbuf; const unsigned char cmd[JEDEC_SFDP_OUTSIZE] = { @@ -72,22 +88,25 @@ } return ret; } struct sfdp_tbl_hdr { - uint8_t id; + uint16_t id; uint8_t v_minor; uint8_t v_major; uint8_t len; uint32_t ptp; /* 24b pointer */ }; -static int sfdp_add_uniform_eraser(struct flashchip *chip, uint8_t opcode, uint32_t block_size) +static int sfdp_add_uniform_eraser(struct flashchip *chip, int eraser_type, uint8_t opcode, uint32_t block_size) { int i; uint32_t total_size = chip->total_size * 1024; - erasefunc_t *erasefn = spi_get_erasefn_from_opcode(opcode); + + /* choosing different eraser functions for 3-bytes and 4-bytes addressing */ + erasefunc_t *erasefn = (chip->feature_bits & FEATURE_FOUR_BYTE_ADDR) ? + spi_get_erasefn_from_opcode_4ba(opcode) : spi_get_erasefn_from_opcode(opcode); if (erasefn == NULL || total_size == 0 || block_size == 0 || total_size % block_size != 0) { msg_cdbg("%s: invalid input, please report to " "flashrom(a)flashrom.org\n", __func__); @@ -109,10 +128,11 @@ msg_cspew(" Block Eraser %d is already occupied.\n", i); continue; } + eraser->type = eraser_type; eraser->block_erase = erasefn; eraser->eraseblocks[0].size = block_size; eraser->eraseblocks[0].count = total_size/block_size; msg_cdbg2(" Block eraser %d: %d x %d B with opcode " "0x%02x\n", i, total_size/block_size, block_size, @@ -123,44 +143,110 @@ " Please report this at flashrom(a)flashrom.org\n", __func__, i); return 1; } -static int sfdp_fill_flash(struct flashchip *chip, uint8_t *buf, uint16_t len) +/* Try of replace exist erasers to new direct 4-bytes addressing erasers + which can be called from ANY addressing mode: 3-byte or 4-bytes. + These erasers opcodes defines in SFDP 4-byte address instruction table + from SFDP revision 1.6 that is defined by JESD216B standard. */ +static int sfdp_change_uniform_eraser_4ba_direct(struct flashchip *chip, int eraser_type, uint8_t opcode) +{ + int i; + erasefunc_t *erasefn = spi_get_erasefn_from_opcode_4ba_direct(opcode); + + if (erasefn == NULL) { + msg_cdbg("%s: invalid input, please report to " + "flashrom(a)flashrom.org\n", __func__); + return 1; + } + + for (i = 0; i < NUM_ERASEFUNCTIONS; i++) { + struct block_eraser *eraser = &chip->block_erasers[i]; + if (eraser->eraseblocks[0].size == 0) + break; + if (eraser->type != eraser_type) + continue; + + eraser->block_erase = erasefn; + msg_cdbg2(" Block eraser %d (type %d) changed to opcode " + "0x%02x\n", i, eraser_type, opcode); + return 0; + } + + msg_cspew("%s: Block Eraser type %d isn't found." + " Please report this at flashrom(a)flashrom.org\n", + __func__, eraser_type); + return 1; +} + +/* Parse of JEDEC SFDP Basic Flash Parameter Table */ +static int sfdp_fill_flash(struct flashchip *chip, uint8_t *buf, uint16_t len, int sfdp_rev_15) { uint8_t opcode_4k_erase = 0xFF; uint32_t tmp32; uint8_t tmp8; uint32_t total_size; /* in bytes */ uint32_t block_size; int j; msg_cdbg("Parsing JEDEC flash parameter table... "); - if (len != 9 * 4 && len != 4 * 4) { + if (len != 16 * 4 && len != 9 * 4 && len != 4 * 4) { msg_cdbg("%s: len out of spec\n", __func__); return 1; } msg_cdbg2("\n"); - + /* 1. double word */ tmp32 = ((unsigned int)buf[(4 * 0) + 0]); tmp32 |= ((unsigned int)buf[(4 * 0) + 1]) << 8; tmp32 |= ((unsigned int)buf[(4 * 0) + 2]) << 16; tmp32 |= ((unsigned int)buf[(4 * 0) + 3]) << 24; + chip->feature_bits = 0; + tmp8 = (tmp32 >> 17) & 0x3; switch (tmp8) { case 0x0: msg_cdbg2(" 3-Byte only addressing.\n"); break; case 0x1: msg_cdbg2(" 3-Byte (and optionally 4-Byte) addressing.\n"); +#ifndef FBA_USE_EXT_ADDR_REG_BY_DEFAULT + /* assuming that 4-bytes addressing mode can be entered + by CMD B7h preceded with WREN and all read, write and + erase commands will be able to receive 4-bytes address */ + chip->feature_bits |= ( FEATURE_FOUR_BYTE_ADDR | + FEATURE_NEED_ENTER_4BA_FOR_READ | + FEATURE_NEED_ENTER_4BA_FOR_WRITE | + FEATURE_NEED_ENTER_4BA_FOR_ERASE ); + chip->four_bytes_addr_funcs.enter_4ba = spi_enter_4ba_b7_we; + chip->four_bytes_addr_funcs.program_byte = spi_byte_program_4ba; + chip->four_bytes_addr_funcs.program_nbyte = spi_nbyte_program_4ba; + chip->four_bytes_addr_funcs.read_nbyte = spi_nbyte_read_4ba; +#else /* if FBA_USE_EXT_ADDR_REG_BY_DEFAULT defined */ + /* assuming that 4-bytes addressing is working using + extended address register which can be assigned + throught CMD C5h and then all commands will use + 3-bytes address as usual */ + chip->feature_bits |= ( FEATURE_FOUR_BYTE_ADDR | + FEATURE_NEED_USE_EXTENDED_ADDR_REG ); + chip->four_bytes_addr_funcs.enter_4ba = NULL; + chip->four_bytes_addr_funcs.program_byte = spi_byte_program_4ba_ereg; + chip->four_bytes_addr_funcs.program_nbyte = spi_nbyte_program_4ba_ereg; + chip->four_bytes_addr_funcs.read_nbyte = spi_nbyte_read_4ba_ereg; +#endif /* FBA_USE_EXT_ADDR_REG_BY_DEFAULT */ break; case 0x2: - msg_cdbg(" 4-Byte only addressing (not supported by " - "flashrom).\n"); - return 1; + msg_cdbg2(" 4-Byte only addressing.\n"); + chip->feature_bits |= ( FEATURE_FOUR_BYTE_ADDR | + FEATURE_FOUR_BYTE_ADDR_ONLY ); + chip->four_bytes_addr_funcs.enter_4ba = NULL; + chip->four_bytes_addr_funcs.program_byte = spi_byte_program_4ba; + chip->four_bytes_addr_funcs.program_nbyte = spi_nbyte_program_4ba; + chip->four_bytes_addr_funcs.read_nbyte = spi_nbyte_read_4ba; + break; default: msg_cdbg(" Required addressing mode (0x%x) not supported.\n", tmp8); return 1; } @@ -168,21 +254,21 @@ msg_cdbg2(" Status register is "); if (tmp32 & (1 << 3)) { msg_cdbg2("volatile and writes to the status register have to " "be enabled with "); if (tmp32 & (1 << 4)) { - chip->feature_bits = FEATURE_WRSR_WREN; + chip->feature_bits |= FEATURE_WRSR_WREN; msg_cdbg2("WREN (0x06).\n"); } else { - chip->feature_bits = FEATURE_WRSR_EWSR; + chip->feature_bits |= FEATURE_WRSR_EWSR; msg_cdbg2("EWSR (0x50).\n"); } } else { msg_cdbg2("non-volatile and the standard does not allow " "vendors to tell us whether EWSR/WREN is needed for " "status register writes - assuming EWSR.\n"); - chip->feature_bits = FEATURE_WRSR_EWSR; + chip->feature_bits |= FEATURE_WRSR_EWSR; } msg_cdbg2(" Write chunk size is "); if (tmp32 & (1 << 2)) { msg_cdbg2("at least 64 B.\n"); @@ -212,56 +298,306 @@ return 1; } total_size = ((tmp32 & 0x7FFFFFFF) + 1) / 8; chip->total_size = total_size / 1024; msg_cdbg2(" Flash chip size is %d kB.\n", chip->total_size); + if (total_size > (1 << 24)) { - msg_cdbg("Flash chip size is bigger than what 3-Byte addressing " - "can access.\n"); - return 1; + if(!sfdp_rev_15) { + msg_cdbg("Flash chip size is bigger than what 3-Byte addressing " + "can access but chip's SFDP revision is lower than 1.6 " + "(1.5).\nConsequently 4-bytes addressing can NOT be " + "properly configured using current SFDP information.\n"); +#ifndef FBA_USE_EXT_ADDR_REG_BY_DEFAULT + msg_cdbg("Assuming that 4-bytes addressing mode can be " + "entered by CMD B7h with WREN.\n"); +#else + msg_cdbg("Assuming that 4-bytes addressing is working via " + "an Extended Address Register which can be written " + "by CMD C5h.\n"); +#endif + } } - if (opcode_4k_erase != 0xFF) - sfdp_add_uniform_eraser(chip, opcode_4k_erase, 4 * 1024); - /* FIXME: double words 3-7 contain unused fast read information */ - if (len == 4 * 4) { + if (len < 9 * 4) { msg_cdbg(" It seems like this chip supports the preliminary " "Intel version of SFDP, skipping processing of double " "words 3-9.\n"); + + /* in the case if BFPT erasers array is not present + trying to add default 4k-eraser */ + if (opcode_4k_erase != 0xFF) + sfdp_add_uniform_eraser(chip, 0, opcode_4k_erase, 4 * 1024); + goto done; } - /* 8. double word */ + /* 8. double word & 9. double word */ + /* for by block eraser types, from Type 1 to Type 4 */ for (j = 0; j < 4; j++) { /* 7 double words from the start + 2 bytes for every eraser */ tmp8 = buf[(4 * 7) + (j * 2)]; - msg_cspew(" Erase Sector Type %d Size: 0x%02x\n", j + 1, - tmp8); + msg_cspew(" Erase Sector (Type %d) Size: 0x%02x\n", j + 1, tmp8); if (tmp8 == 0) { - msg_cspew(" Erase Sector Type %d is unused.\n", j); + msg_cspew(" Erase Sector (Type %d) is unused.\n", j + 1); continue; } if (tmp8 >= 31) { - msg_cdbg2(" Block size of erase Sector Type %d (2^%d) " - "is too big for flashrom.\n", j, tmp8); + msg_cdbg2(" Block size of erase Sector (Type %d): 2^%d " + "is too big for flashrom.\n", j + 1, tmp8); continue; } block_size = 1 << (tmp8); /* block_size = 2 ^ field */ tmp8 = buf[(4 * 7) + (j * 2) + 1]; - msg_cspew(" Erase Sector Type %d Opcode: 0x%02x\n", j + 1, - tmp8); - sfdp_add_uniform_eraser(chip, tmp8, block_size); + msg_cspew(" Erase Sector (Type %d) Opcode: 0x%02x\n", j + 1, tmp8); + sfdp_add_uniform_eraser(chip, j + 1, tmp8, block_size); + } + + /* Trying to adding the default 4k eraser after parsing erasers info. + In most cases this eraser has already been added before. */ + if (opcode_4k_erase != 0xFF) + sfdp_add_uniform_eraser(chip, 0, opcode_4k_erase, 4 * 1024); + + /* If the chip doesn't support 4-bytes addressing mode we don't have + to read and analyze 16th DWORD of Basic Flash Parameter Table */ + if (!(chip->feature_bits & FEATURE_FOUR_BYTE_ADDR)) + goto done; + + /* In the case if the chip is working in 4-bytes addressing mode ONLY we + don't have to read and analyze 16th DWORD of Basic Flash Parameter Table + because we don't have to know how to switch to 4-bytes mode and back + when we are already in 4-bytes mode permanently. */ + if (chip->feature_bits & FEATURE_FOUR_BYTE_ADDR_ONLY) + goto done; + + /* If the SFDP revision supported by the chip is lower that 1.6 (1.5) + we can not read and analyze 16th DWORD of Basic Flash Parameter Table. + Using defaults by FBA_USE_EXT_ADDR_REG_BY_DEFAULT define. */ + if(!sfdp_rev_15) + goto done; + + if (len < 16 * 4) { + msg_cdbg("%s: len of BFPT is out of spec\n", __func__); + msg_cerr("ERROR: Unable read 4-bytes addressing parameters.\n"); + return 1; + } + + /* 11. double word */ + tmp8 = buf[(4*10) + 0] >> 4; /* get upper nibble of LSB of 11th dword */ + chip->page_size = 1 << tmp8; /* page_size = 2 ^ N */ + msg_cdbg2(" Page size is %d B.\n", chip->page_size); + + /* 16. double word */ + tmp32 = ((unsigned int)buf[(4 * 15) + 0]); + tmp32 |= ((unsigned int)buf[(4 * 15) + 1]) << 8; + tmp32 |= ((unsigned int)buf[(4 * 15) + 2]) << 16; + tmp32 |= ((unsigned int)buf[(4 * 15) + 3]) << 24; + + /* Parsing 16th DWORD of Basic Flash Parameter Table according to JESD216B */ + + if(tmp32 & JEDEC_BFPT_DW16_ENTER_B7) { + msg_cdbg2(" Enter 4-bytes addressing mode by CMD B7h\n"); + chip->four_bytes_addr_funcs.enter_4ba = spi_enter_4ba_b7; + chip->four_bytes_addr_funcs.program_byte = spi_byte_program_4ba; + chip->four_bytes_addr_funcs.program_nbyte = spi_nbyte_program_4ba; + chip->four_bytes_addr_funcs.read_nbyte = spi_nbyte_read_4ba; + chip->feature_bits &= ~FEATURE_ENTER_4BA_ALL; // clear defaults + chip->feature_bits |= ( FEATURE_NEED_ENTER_4BA_FOR_READ | + FEATURE_NEED_ENTER_4BA_FOR_WRITE | + FEATURE_NEED_ENTER_4BA_FOR_ERASE ); + } + else if(tmp32 & JEDEC_BFPT_DW16_ENTER_B7_WE) { + msg_cdbg2(" Enter 4-bytes addressing mode by CMD B7h with WREN\n"); + chip->four_bytes_addr_funcs.enter_4ba = spi_enter_4ba_b7_we; + chip->four_bytes_addr_funcs.program_byte = spi_byte_program_4ba; + chip->four_bytes_addr_funcs.program_nbyte = spi_nbyte_program_4ba; + chip->four_bytes_addr_funcs.read_nbyte = spi_nbyte_read_4ba; + chip->feature_bits &= ~FEATURE_ENTER_4BA_ALL; // clear defaults + chip->feature_bits |= ( FEATURE_NEED_ENTER_4BA_FOR_READ | + FEATURE_NEED_ENTER_4BA_FOR_WRITE | + FEATURE_NEED_ENTER_4BA_FOR_ERASE ); + } + else if(tmp32 & JEDEC_BFPT_DW16_ENTER_EXTENDED_ADDR_REG) { + msg_cdbg2(" Extended Address Register used for 4-bytes addressing\n"); + chip->four_bytes_addr_funcs.program_byte = spi_byte_program_4ba_ereg; + chip->four_bytes_addr_funcs.program_nbyte = spi_nbyte_program_4ba_ereg; + chip->four_bytes_addr_funcs.read_nbyte = spi_nbyte_read_4ba_ereg; + chip->feature_bits &= ~FEATURE_ENTER_4BA_ALL; // clear defaults + /* this flag signals to all '*_selector' functions + to use Ext.Addr.Reg while erase operations */ + chip->feature_bits |= FEATURE_NEED_USE_EXTENDED_ADDR_REG; + } + else { + msg_cerr("ERROR: Unable to use 4-bytes addressing for this chip.\n" + " Please report this at flashrom(a)flashrom.org\n\n"); + return 1; } done: msg_cdbg("done.\n"); return 0; } +/* Parse of JEDEC SFDP 4-byte address instruction table. From SFDP revision 1.6 only. + This parsing shoukd be called after basic flash parameter table is parsed. */ +static int sfdp_parse_4ba_table(struct flashchip *chip, uint8_t *buf, uint16_t len) +{ + uint32_t tmp32; + uint8_t tmp8; + int j, direct_erasers; + int direct_count; + + msg_cdbg("Parsing JEDEC 4-byte address instuction table... "); + if (len != 2 * 4) { + msg_cdbg("%s: len out of spec\n", __func__); + return 1; + } + msg_cdbg2("\n"); + + /* 1. double word */ + tmp32 = ((unsigned int)buf[(4 * 0) + 0]); + tmp32 |= ((unsigned int)buf[(4 * 0) + 1]) << 8; + tmp32 |= ((unsigned int)buf[(4 * 0) + 2]) << 16; + tmp32 |= ((unsigned int)buf[(4 * 0) + 3]) << 24; + + direct_count = 0; + + if(tmp32 & JEDEC_4BAIT_READ_SUPPORT) { + msg_cdbg2(" Found Read CMD 13h with 4-bytes address\n"); + chip->four_bytes_addr_funcs.read_nbyte = spi_nbyte_read_4ba_direct; + /* read function has changed to direct 4-bytes function, + so entering 4-bytes mode isn't required for reading bytes */ + chip->feature_bits &= ~FEATURE_NEED_ENTER_4BA_FOR_READ; + direct_count++; + } + + if(tmp32 & JEDEC_4BAIT_PROGRAM_SUPPORT) { + msg_cdbg2(" Found Write CMD 12h with 4-bytes address\n"); + chip->four_bytes_addr_funcs.program_byte = spi_byte_program_4ba_direct; + chip->four_bytes_addr_funcs.program_nbyte = spi_nbyte_program_4ba_direct; + /* write (program) functions have changed to direct 4-bytes functions, + so entering 4-bytes mode isn't required for writing bytes */ + chip->feature_bits &= ~FEATURE_NEED_ENTER_4BA_FOR_WRITE; + direct_count++; + } + + direct_erasers = 0; + + /* 2. double word */ + for (j = 0; j < 4; j++) { + if(!(tmp32 & (JEDEC_4BAIT_ERASE_TYPE_1_SUPPORT << j))) + continue; + + tmp8 = buf[(4 * 1) + j]; + + msg_cdbg2(" Found Erase (type %d) CMD %02Xh with 4-bytes address\n", j + 1, tmp8); + + if(tmp8 == 0xFF) { + msg_cdbg("%s: Eraser (type %d) is supported, but opcode = 0xFF\n" + " Please report to flashrom(a)flashrom.org\n\n", __func__, j + 1); + continue; + } + + /* try of replacing the eraser with direct 4-bytes eraser */ + if(!sfdp_change_uniform_eraser_4ba_direct(chip, j + 1, tmp8)) + direct_erasers++; + } + + for (j = 0; j < NUM_ERASEFUNCTIONS; j++) { + if (chip->block_erasers[j].eraseblocks[0].size == 0) + break; + } + + if( j == direct_erasers ) { + /* if all erasers have been changed to direct 4-bytes ones, + then we don't have to enter 4-bytes mode for erase */ + chip->feature_bits &= ~FEATURE_NEED_ENTER_4BA_FOR_ERASE; + direct_count++; + msg_cspew("All erasers have changed to direct ones.\n"); + } + + if( direct_count == 3 ) { + /* if all read/write/erase functions are direct 4-bytes now, + then we don't have to use extended address register */ + chip->feature_bits &= ~FEATURE_NEED_USE_EXTENDED_ADDR_REG; + msg_cspew("All read/write/erase functions have changed to direct ones.\n"); + } + + msg_cdbg("done.\n"); + return 0; +} + +#ifdef JESD216B_SIMULATION +/* This simulation increases size of Basic Flash Parameter Table + to have 16 dwords size and fills 16th dword with fake information + that is required to test JESD216B compliance. */ +int sfdp_jesd216b_simulation_dw16(uint8_t** ptbuf, uint16_t* plen) +{ + uint8_t* tbufsim; + uint16_t lensim = 16 * 4; + + tbufsim = malloc(lensim); + if (tbufsim == NULL) { + msg_gerr("Out of memory!\n"); + return 1; + } + + msg_cdbg("\n=== SIMULATION of JESD216B 16th Dword of Basic Flash Parameter Table\n"); + + memset(tbufsim, 0, 16 * 4); + memcpy(tbufsim, *ptbuf, min(*plen, 15 * 4)); + + tbufsim[(4*10) + 0] = 8 << 4; /* page size = 256 */ + + *((uint32_t*)&tbufsim[15 * 4]) = /*JEDEC_BFPT_DW16_ENTER_B7 | */ + JEDEC_BFPT_DW16_ENTER_B7_WE | + JEDEC_BFPT_DW16_ENTER_EXTENDED_ADDR_REG /* | + JEDEC_BFPT_DW16_ENTER_BANK_ADDR_REG_EN_BIT | + JEDEC_BFPT_DW16_ENTER_NV_CONFIG_REG | + JEDEC_BFPT_DW16_VENDOR_SET | + JEDEC_BFPT_DW16_4_BYTES_ADDRESS_ONLY */ ; + + free(*ptbuf); + *ptbuf = tbufsim; + *plen = lensim; + return 0; +} + +/* This simulation created fake 4-bytes Address Instruction Table + with features information to test JESD216B compliance. */ +int sfdp_jesd216b_simulation_4bait(uint8_t** ptbuf, uint16_t* plen) +{ + uint8_t* tbufsim; + uint16_t lensim = 2 * 4; + + tbufsim = malloc(lensim); + if (tbufsim == NULL) { + msg_gerr("Out of memory!\n"); + return 1; + } + + msg_cdbg("\n=== SIMULATION of JESD216B 4-bytes Address Instruction Table\n"); + + *((uint32_t*)&tbufsim[0]) = JEDEC_4BAIT_READ_SUPPORT /*| + JEDEC_4BAIT_PROGRAM_SUPPORT | + JEDEC_4BAIT_ERASE_TYPE_1_SUPPORT | + JEDEC_4BAIT_ERASE_TYPE_2_SUPPORT | + JEDEC_4BAIT_ERASE_TYPE_3_SUPPORT | + JEDEC_4BAIT_ERASE_TYPE_4_SUPPORT */; + *((uint32_t*)&tbufsim[4]) = 0xFFFFFFFF; + /* *((uint32_t*)&tbufsim[4]) = 0xFFDC5C21; */ + + free(*ptbuf); + *ptbuf = tbufsim; + *plen = lensim; + return 0; +} +#endif + int probe_spi_sfdp(struct flashctx *flash) { int ret = 0; uint8_t buf[8]; uint32_t tmp32; @@ -269,10 +605,11 @@ /* need to limit the table loop by comparing i to uint8_t nph hence: */ uint16_t i; struct sfdp_tbl_hdr *hdrs; uint8_t *hbuf; uint8_t *tbuf; + int sfdp_rev_16 = 0, sfdp_rev_15 = 0; if (spi_sfdp_read_sfdp(flash, 0x00, buf, 4)) { msg_cdbg("Receiving SFDP signature failed.\n"); return 0; } @@ -296,10 +633,36 @@ if (buf[1] != 0x01) { msg_cdbg("The chip supports an unknown version of SFDP. " "Aborting SFDP probe!\n"); return 0; } + + /* JEDEC JESD216B defines SFDP revision 1.6 and includes: + 1) 16 dwords in Basic Flash Parameter Table + 2) 16th dword has information how to enter + and exit 4-bytes addressing mode + 3) 4-Bytes Address Instruction Table with ID 0xFF84 + + However we can see in the datasheet for Micron's + MT25Q 512Mb chip (MT25QL512AB/MT25QU512AB) that the + chip returnes SFDP revision 1.5 and has 16 dwords + in its Basic Flash Paramater Table. Also the information + about addressing mode switch is exist in the 16th dword. + But 4-Bytes Address Instruction Table is absent. + + So we will use 16th dword from SFDP revision 1.5 + but 4-Bytes Address Instruction Table from SFDP 1.6 only. + This assumption is made for better support of Micron + flash chips. + + FIXME: SFDP revisions compliance should be checked + more carefully after more information about JESD216B + SFDP tables will be known from real flash chips. + */ + sfdp_rev_16 = (buf[1] == 1 && buf[0] >= 6) || buf[1] > 1; + sfdp_rev_15 = (buf[1] == 1 && buf[0] >= 5) || buf[1] > 1; + nph = buf[2]; msg_cdbg2("SFDP number of parameter headers is %d (NPH = %d).\n", nph + 1, nph); /* Fetch all parameter headers, even if we don't use them all (yet). */ @@ -314,17 +677,18 @@ goto cleanup_hdrs; } for (i = 0; i <= nph; i++) { uint16_t len; - hdrs[i].id = hbuf[(8 * i) + 0]; + hdrs[i].id = hbuf[(8 * i) + 0]; /* ID LSB read */ hdrs[i].v_minor = hbuf[(8 * i) + 1]; hdrs[i].v_major = hbuf[(8 * i) + 2]; hdrs[i].len = hbuf[(8 * i) + 3]; hdrs[i].ptp = hbuf[(8 * i) + 4]; hdrs[i].ptp |= ((unsigned int)hbuf[(8 * i) + 5]) << 8; hdrs[i].ptp |= ((unsigned int)hbuf[(8 * i) + 6]) << 16; + hdrs[i].id |= ((uint16_t)hbuf[(8 * i) + 7]) << 8; /* ID MSB read */ msg_cdbg2("\nSFDP parameter table header %d/%d:\n", i, nph); msg_cdbg2(" ID 0x%02x, version %d.%d\n", hdrs[i].id, hdrs[i].v_major, hdrs[i].v_minor); len = hdrs[i].len * 4; tmp32 = hdrs[i].ptp; @@ -366,29 +730,51 @@ } } msg_cspew("\n"); if (i == 0) { /* Mandatory JEDEC SFDP parameter table */ - if (hdrs[i].id != 0) + if (hdrs[i].id != JEDEC_BFPT_ID) msg_cdbg("ID of the mandatory JEDEC SFDP " - "parameter table is not 0 as demanded " - "by JESD216 (warning only).\n"); - + "parameter table is not 0xFF00 as" + "demanded by JESD216 (warning only)." + "\n"); +#ifdef JESD216B_SIMULATION + if(!sfdp_jesd216b_simulation_dw16(&tbuf, &len)) + sfdp_rev_16 = sfdp_rev_15 = 1; /* pretend as SFDP rev 1.6 */ +#endif if (hdrs[i].v_major != 0x01) { msg_cdbg("The chip contains an unknown " "version of the JEDEC flash " "parameters table, skipping it.\n"); - } else if (len != 9 * 4 && len != 4 * 4) { + } else if (len != 16 * 4 && len != 9 * 4 && len != 4 * 4) { msg_cdbg("Length of the mandatory JEDEC SFDP " "parameter table is wrong (%d B), " "skipping it.\n", len); - } else if (sfdp_fill_flash(flash->chip, tbuf, len) == 0) + } else if (sfdp_fill_flash(flash->chip, tbuf, len, sfdp_rev_15) == 0) ret = 1; +#ifdef JESD216B_SIMULATION + if(ret == 1 && !sfdp_jesd216b_simulation_4bait(&tbuf, &len)) + sfdp_parse_4ba_table(flash->chip, tbuf, len); +#endif + } + /* JEDEC SFDP 4-byte address instruction table. From SFDP revision 1.6 only. + This parsing shoukd be called after basic flash parameter table is parsed. */ + else if(sfdp_rev_16 && hdrs[i].id == JEDEC_4BAIT_ID && ret == 1) { + if (hdrs[i].v_major != 0x01) { + msg_cdbg("The chip contains an unknown " + "version of the JEDEC 4-bytes " + "address instruction table, " + "skipping it.\n"); + } + else { /* no result check because this table is optional */ + sfdp_parse_4ba_table(flash->chip, tbuf, len); + } } free(tbuf); } cleanup_hdrs: free(hdrs); free(hbuf); return ret; } + Index: spi.c =================================================================== --- spi.c (revision 1861) +++ spi.c (working copy) @@ -108,11 +108,14 @@ /* Check if the chip fits between lowest valid and highest possible * address. Highest possible address with the current SPI implementation * means 0xffffff, the highest unsigned 24bit number. */ addrbase = spi_get_valid_read_addr(flash); - if (addrbase + flash->chip->total_size * 1024 > (1 << 24)) { + /* Show flash chip size warning if flash chip doesn't support + 4-Bytes Addressing mode and last address excedes 24 bits */ + if (!(flash->chip->feature_bits & FEATURE_FOUR_BYTE_ADDR) && + addrbase + flash->chip->total_size * 1024 > (1 << 24)) { msg_perr("Flash chip size exceeds the allowed access window. "); msg_perr("Read will probably fail.\n"); /* Try to get the best alignment subject to constraints. */ addrbase = (1 << 24) - flash->chip->total_size * 1024; } Index: spi25.c =================================================================== --- spi25.c (revision 1861) +++ spi25.c (working copy) @@ -26,10 +26,11 @@ #include "flash.h" #include "flashchips.h" #include "chipdrivers.h" #include "programmer.h" #include "spi.h" +#include "spi4ba.h" static int spi_rdid(struct flashctx *flash, unsigned char *readarr, int bytes) { static const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID }; int ret; @@ -946,10 +947,20 @@ unsigned int len, unsigned int chunksize) { int rc = 0; unsigned int i, j, starthere, lenhere, toread; unsigned int page_size = flash->chip->page_size; + int show_progress = 0; + unsigned int percent_last, percent_current; + + /* progress visualizaion init */ + if(len >= MIN_LENGTH_TO_SHOW_READ_PROGRESS) { + msg_cinfo(" "); /* only this space will go to logfile but all strings with \b wont. */ + msg_cinfo("\b 0%%"); + percent_last = percent_current = 0; + show_progress = 1; /* enable progress visualizaion */ + } /* Warning: This loop has a very unusual condition and body. * The loop needs to go through each page with at least one affected * byte. The lowest page number is (start / page_size) since that * division rounds down. The highest page number we want is the page @@ -964,18 +975,33 @@ starthere = max(start, i * page_size); /* Length of bytes in the range in this page. */ lenhere = min(start + len, (i + 1) * page_size) - starthere; for (j = 0; j < lenhere; j += chunksize) { toread = min(chunksize, lenhere - j); - rc = spi_nbyte_read(flash, starthere + j, buf + starthere - start + j, toread); + rc = (flash->chip->feature_bits & FEATURE_FOUR_BYTE_ADDR) == 0 + ? spi_nbyte_read(flash, starthere + j, buf + starthere - start + j, toread) + : flash->chip->four_bytes_addr_funcs.read_nbyte(flash, starthere + j, + buf + starthere - start + j, toread); if (rc) break; } if (rc) break; + + if(show_progress) { + percent_current = (unsigned int) ((unsigned long long)(starthere + + lenhere - start) * 100 / len); + if(percent_current != percent_last) { + msg_cinfo("\b\b\b%2d%%", percent_current); + percent_last = percent_current; + } + } } + if(show_progress && !rc) + msg_cinfo("\b\b\b\b"); /* remove progress percents from the screen */ + return rc; } /* * Write a part of the flash chip. @@ -1009,11 +1035,14 @@ starthere = max(start, i * page_size); /* Length of bytes in the range in this page. */ lenhere = min(start + len, (i + 1) * page_size) - starthere; for (j = 0; j < lenhere; j += chunksize) { towrite = min(chunksize, lenhere - j); - rc = spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite); + rc = (flash->chip->feature_bits & FEATURE_FOUR_BYTE_ADDR) == 0 + ? spi_nbyte_program(flash, starthere + j, buf + starthere - start + j, towrite) + : flash->chip->four_bytes_addr_funcs.program_nbyte(flash, starthere + j, + buf + starthere - start + j, towrite); if (rc) break; while (spi_read_status_register(flash) & SPI_SR_WIP) programmer_delay(10); } @@ -1035,11 +1064,13 @@ { unsigned int i; int result = 0; for (i = start; i < start + len; i++) { - result = spi_byte_program(flash, i, buf[i - start]); + result = (flash->chip->feature_bits & FEATURE_FOUR_BYTE_ADDR) == 0 + ? spi_byte_program(flash, i, buf[i - start]) + : flash->chip->four_bytes_addr_funcs.program_byte(flash, i, buf[i - start]); if (result) return 1; while (spi_read_status_register(flash) & SPI_SR_WIP) programmer_delay(10); } Index: spi4ba.c =================================================================== --- spi4ba.c (revision 0) +++ spi4ba.c (working copy) @@ -0,0 +1,1020 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2014 Boris Baykov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * SPI chip driver functions for 4-bytes addressing + */ + +#include <string.h> +#include "flash.h" +#include "chipdrivers.h" +#include "spi.h" +#include "programmer.h" +#include "spi4ba.h" + +/* #define MSG_TRACE_4BA_FUNCS 1 */ + +#ifdef MSG_TRACE_4BA_FUNCS +#define msg_trace(...) print(MSG_DEBUG, __VA_ARGS__) +#else +#define msg_trace(...) +#endif + +/* Enter 4-bytes addressing mode (without sending WREN before) */ +int spi_enter_4ba_b7(struct flashctx *flash) +{ + const unsigned char cmd[JEDEC_ENTER_4_BYTE_ADDR_MODE_OUTSIZE] = { JEDEC_ENTER_4_BYTE_ADDR_MODE }; + + msg_trace("-> %s\n", __func__); + + /* Switch to 4-bytes addressing mode */ + return spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); +} + +/* Enter 4-bytes addressing mode with sending WREN before */ +int spi_enter_4ba_b7_we(struct flashctx *flash) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_ENTER_4_BYTE_ADDR_MODE_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_ENTER_4_BYTE_ADDR_MODE }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s\n", __func__); + + /* Switch to 4-bytes addressing mode */ + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution\n", __func__); + } + return result; +} + +/* Write Extended Address Register value */ +int spi_write_extended_address_register(struct flashctx *flash, uint8_t regdata) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_WRITE_EXT_ADDR_REG_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_WRITE_EXT_ADDR_REG, + regdata + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (%02X)\n", __func__, regdata); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution\n", __func__); + return result; + } + return 0; +} + +/* Assign required value of Extended Address Register. This function + keeps last value of the register and writes the register if the + value has to be changed only. */ +int set_extended_address_register(struct flashctx *flash, uint8_t data) +{ + static uint8_t ext_addr_reg_state; /* memory for last register state */ + static int ext_addr_reg_state_valid = 0; + int result; + + if (ext_addr_reg_state_valid == 0 || data != ext_addr_reg_state) { + result = spi_write_extended_address_register(flash, data); + if (result) { + ext_addr_reg_state_valid = 0; + return result; + } + ext_addr_reg_state = data; + ext_addr_reg_state_valid = 1; + } + return 0; +} + +/* Program one flash byte from 4-bytes addressing mode */ +int spi_byte_program_4ba(struct flashctx *flash, unsigned int addr, + uint8_t databyte) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE + 1, + .writearr = (const unsigned char[]){ + JEDEC_BYTE_PROGRAM, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff), + databyte + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X)\n", __func__, addr); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + } + return result; +} + +/* Program flash bytes from 4-bytes addressing mode */ +int spi_nbyte_program_4ba(struct flashctx *flash, unsigned int addr, + const uint8_t *bytes, unsigned int len) +{ + int result; + unsigned char cmd[(JEDEC_BYTE_PROGRAM_OUTSIZE + 1) - 1 + 256] = { + JEDEC_BYTE_PROGRAM, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr >> 0) & 0xff + }; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = (JEDEC_BYTE_PROGRAM_OUTSIZE + 1) - 1 + len, + .writearr = cmd, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); + + if (!len) { + msg_cerr("%s called for zero-length write\n", __func__); + return 1; + } + if (len > 256) { + msg_cerr("%s called for too long a write\n", __func__); + return 1; + } + + memcpy(&cmd[(JEDEC_BYTE_PROGRAM_OUTSIZE + 1) - 1], bytes, len); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + } + return result; +} + +/* Read flash bytes from 4-bytes addressing mode */ +int spi_nbyte_read_4ba(struct flashctx *flash, unsigned int addr, + uint8_t *bytes, unsigned int len) +{ + const unsigned char cmd[JEDEC_READ_OUTSIZE + 1] = { + JEDEC_READ, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr >> 0) & 0xff + }; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); + + /* Send Read */ + return spi_send_command(flash, sizeof(cmd), len, cmd, bytes); +} + +/* Program one flash byte with 4-bytes address from ANY mode (3-bytes or 4-bytes) + JEDEC_BYTE_PROGRAM_4BA (12h) instruction is new for 4-bytes addressing flash chips. + The presence of this instruction for an exact chip should be checked + by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */ +int spi_byte_program_4ba_direct(struct flashctx *flash, unsigned int addr, + uint8_t databyte) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_4BA_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BYTE_PROGRAM_4BA, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff), + databyte + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X)\n", __func__, addr); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + } + return result; +} + +/* Program flash bytes with 4-bytes address from ANY mode (3-bytes or 4-bytes) + JEDEC_BYTE_PROGRAM_4BA (12h) instruction is new for 4-bytes addressing flash chips. + The presence of this instruction for an exact chip should be checked + by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */ +int spi_nbyte_program_4ba_direct(struct flashctx *flash, unsigned int addr, + const uint8_t *bytes, unsigned int len) +{ + int result; + unsigned char cmd[JEDEC_BYTE_PROGRAM_4BA_OUTSIZE - 1 + 256] = { + JEDEC_BYTE_PROGRAM_4BA, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr >> 0) & 0xff + }; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_4BA_OUTSIZE - 1 + len, + .writearr = cmd, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); + + if (!len) { + msg_cerr("%s called for zero-length write\n", __func__); + return 1; + } + if (len > 256) { + msg_cerr("%s called for too long a write\n", __func__); + return 1; + } + + memcpy(&cmd[JEDEC_BYTE_PROGRAM_4BA_OUTSIZE - 1], bytes, len); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + } + return result; +} + +/* Read flash bytes with 4-bytes address from ANY mode (3-bytes or 4-bytes) + JEDEC_READ_4BA (13h) instruction is new for 4-bytes addressing flash chips. + The presence of this instruction for an exact chip should be checked + by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */ +int spi_nbyte_read_4ba_direct(struct flashctx *flash, unsigned int addr, + uint8_t *bytes, unsigned int len) +{ + const unsigned char cmd[JEDEC_READ_4BA_OUTSIZE] = { + JEDEC_READ_4BA, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr >> 0) & 0xff + }; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); + + /* Send Read */ + return spi_send_command(flash, sizeof(cmd), len, cmd, bytes); +} + +/* Program one flash byte using Extended Address Register + from 3-bytes addressing mode */ +int spi_byte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, + uint8_t databyte) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BYTE_PROGRAM, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff), + databyte + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X)\n", __func__, addr); + + result = set_extended_address_register(flash, (addr >> 24) & 0xff); + if (result) + return result; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + } + return result; +} + +/* Program flash bytes using Extended Address Register + from 3-bytes addressing mode */ +int spi_nbyte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, + const uint8_t *bytes, unsigned int len) +{ + int result; + unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = { + JEDEC_BYTE_PROGRAM, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr >> 0) & 0xff + }; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + len, + .writearr = cmd, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); + + if (!len) { + msg_cerr("%s called for zero-length write\n", __func__); + return 1; + } + if (len > 256) { + msg_cerr("%s called for too long a write\n", __func__); + return 1; + } + + memcpy(&cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1], bytes, len); + + result = set_extended_address_register(flash, (addr >> 24) & 0xff); + if (result) + return result; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + } + return result; +} + +/* Read flash bytes using Extended Address Register + from 3-bytes addressing mode */ +int spi_nbyte_read_4ba_ereg(struct flashctx *flash, unsigned int addr, + uint8_t *bytes, unsigned int len) +{ + int result; + const unsigned char cmd[JEDEC_READ_OUTSIZE] = { + JEDEC_READ, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr >> 0) & 0xff + }; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); + + result = set_extended_address_register(flash, (addr >> 24) & 0xff); + if (result) + return result; + + /* Send Read */ + return spi_send_command(flash, sizeof(cmd), len, cmd, bytes); +} + +/* Chooser for erase function by instruction opcode for block eraser instructions + to work with 4-bytes addressing flash chips. This chooser is called from sfdp.c + during parse of 8th & 9th dwords of SFDP Basic Flash Parameter Table */ +erasefunc_t *spi_get_erasefn_from_opcode_4ba(uint8_t opcode) +{ + msg_trace("-> %s\n", __func__); + + switch(opcode){ + case 0xff: + case 0x00: + /* Not specified, assuming "not supported". */ + return NULL; + case 0x20: + return &spi_block_erase_20_4ba_selector; /* selector */ + case 0x52: + return &spi_block_erase_52_4ba_selector; /* selector */ + case 0x60: + return &spi_block_erase_60; + case 0x62: + return &spi_block_erase_62; + case 0xc7: + return &spi_block_erase_c7; + case 0xd8: + return &spi_block_erase_d8_4ba_selector; /* selector */ + case 0x50: + case 0x81: + case 0xc4: + case 0xd7: + case 0xdb: + msg_cinfo("%s: erase opcode (0x%02x) doesn't have its 4-bytes addressing version." + " Please report this at flashrom(a)flashrom.org\n", __func__, opcode); + return NULL; + default: + msg_cinfo("%s: unknown erase opcode (0x%02x). Please report " + "this at flashrom(a)flashrom.org\n", __func__, opcode); + return NULL; + } +} + +/* Selector for 4k eraser that chooses between 4-bytes addressing mode + and use of Extended Address Register from 3-bytes addressing mode */ +int spi_block_erase_20_4ba_selector(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + msg_trace("-> %s\n", __func__); + + return (flash->chip->feature_bits & FEATURE_NEED_USE_EXTENDED_ADDR_REG) ? + spi_block_erase_20_4ba_ereg(flash, addr, blocklen) : + spi_block_erase_20_4ba(flash, addr, blocklen); +} + +/* Erases 4 KB of flash from 4-bytes addressing mode */ +int spi_block_erase_20_4ba(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_SE_OUTSIZE + 1, + .writearr = (const unsigned char[]){ + JEDEC_SE, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 15-800 ms, so wait in 10 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(10 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Selector for 32k eraser that chooses between 4-bytes addressing mode + and use of Extended Address Register from 3-bytes addressing mode */ +int spi_block_erase_52_4ba_selector(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + msg_trace("-> %s\n", __func__); + + return (flash->chip->feature_bits & FEATURE_NEED_USE_EXTENDED_ADDR_REG) ? + spi_block_erase_52_4ba_ereg(flash, addr, blocklen) : + spi_block_erase_52_4ba(flash, addr, blocklen); +} + +/* Erases 32 KB of flash from 4-bytes addressing mode */ +int spi_block_erase_52_4ba(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_52_OUTSIZE + 1, + .writearr = (const unsigned char[]){ + JEDEC_BE_52, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(100 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Selector for 64k eraser that chooses between 4-bytes addressing mode + and use of Extended Address Register from 3-bytes addressing mode */ +int spi_block_erase_d8_4ba_selector(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + msg_trace("-> %s\n", __func__); + + return (flash->chip->feature_bits & FEATURE_NEED_USE_EXTENDED_ADDR_REG) ? + spi_block_erase_d8_4ba_ereg(flash, addr, blocklen) : + spi_block_erase_d8_4ba(flash, addr, blocklen); +} + +/* Erases 64 KB of flash from 4-bytes addressing mode */ +int spi_block_erase_d8_4ba(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_D8_OUTSIZE + 1, + .writearr = (const unsigned char[]){ + JEDEC_BE_D8, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(100 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Erases 4 KB of flash using Extended Address Register + from 3-bytes addressing mode */ +int spi_block_erase_20_4ba_ereg(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_SE_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_SE, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = set_extended_address_register(flash, (addr >> 24) & 0xff); + if (result) + return result; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 15-800 ms, so wait in 10 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(10 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Erases 32 KB of flash using Extended Address Register + from 3-bytes addressing mode */ +int spi_block_erase_52_4ba_ereg(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_52_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BE_52, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = set_extended_address_register(flash, (addr >> 24) & 0xff); + if (result) + return result; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(100 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Erases 64 KB of flash using Extended Address Register + from 3-bytes addressing mode */ +int spi_block_erase_d8_4ba_ereg(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_D8_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BE_D8, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = set_extended_address_register(flash, (addr >> 24) & 0xff); + if (result) + return result; + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(100 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Chooser for erase function by instruction opcode for block eraser instructions + which can be used from ANY mode (3-bytes or 4-bytes). This chooser is called + from sfdp.c during parse of SFDP 4-Bytes Address Instruction Table (JESD216B) */ +erasefunc_t *spi_get_erasefn_from_opcode_4ba_direct(uint8_t opcode) +{ + msg_trace("-> %s\n", __func__); + + switch(opcode){ + case 0xff: + case 0x00: + /* Not specified, assuming "not supported". */ + return NULL; + case 0x21: + return &spi_block_erase_21_4ba_direct; /* direct */ + case 0x5C: + return &spi_block_erase_5c_4ba_direct; /* direct */ + case 0xdc: + return &spi_block_erase_dc_4ba_direct; /* direct */ + default: + msg_cinfo("%s: unknown erase opcode (0x%02x). Please report " + "this at flashrom(a)flashrom.org\n", __func__, opcode); + return NULL; + } +} + +/* Erase 4 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) + JEDEC_SE_4BA (21h) instruction is new for 4-bytes addressing flash chips. + The presence of this instruction for an exact chip should be checked + by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */ +int spi_block_erase_21_4ba_direct(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_SE_4BA_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_SE_4BA, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 15-800 ms, so wait in 10 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(10 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Erase 32 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) + JEDEC_BE_5C_4BA (5Ch) instruction is new for 4-bytes addressing flash chips. + The presence of this instruction for an exact chip should be checked + by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */ +int spi_block_erase_5c_4ba_direct(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_5C_4BA_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BE_5C_4BA, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(100 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} + +/* Erase 64 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) + JEDEC_BE_DC_4BA (DCh) instruction is new for 4-bytes addressing flash chips. + The presence of this instruction for an exact chip should be checked + by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */ +int spi_block_erase_dc_4ba_direct(struct flashctx *flash, unsigned int addr, + unsigned int blocklen) +{ + int result; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_BE_DC_4BA_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_BE_DC_4BA, + (addr >> 24) & 0xff, + (addr >> 16) & 0xff, + (addr >> 8) & 0xff, + (addr & 0xff) + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; + + msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); + + result = spi_send_multicommand(flash, cmds); + if (result) { + msg_cerr("%s failed during command execution at address 0x%x\n", + __func__, addr); + return result; + } + /* Wait until the Write-In-Progress bit is cleared. + * This usually takes 100-4000 ms, so wait in 100 ms steps. + */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(100 * 1000); + /* FIXME: Check the status register for errors. */ + return 0; +} Property changes on: spi4ba.c ___________________________________________________________________ Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: spi4ba.h =================================================================== --- spi4ba.h (revision 0) +++ spi4ba.h (working copy) @@ -0,0 +1,158 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2014 Boris Baykov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +/* + * JEDEC flash chips instructions for 4-bytes addressing + * SPI chip driver functions for 4-bytes addressing + */ + +#ifndef __SPI_4BA_H__ +#define __SPI_4BA_H__ 1 + +/* Read the memory with 4-byte address + From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ +#define JEDEC_READ_4BA 0x13 +#define JEDEC_READ_4BA_OUTSIZE 0x05 +/* JEDEC_READ_4BA_INSIZE : any length */ + +/* Write memory byte with 4-byte address + From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ +#define JEDEC_BYTE_PROGRAM_4BA 0x12 +#define JEDEC_BYTE_PROGRAM_4BA_OUTSIZE 0x06 +#define JEDEC_BYTE_PROGRAM_4BA_INSIZE 0x00 + +/* Sector Erase 0x21 (with 4-byte address), usually 4k size. + From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ +#define JEDEC_SE_4BA 0x21 +#define JEDEC_SE_4BA_OUTSIZE 0x05 +#define JEDEC_SE_4BA_INSIZE 0x00 + +/* Block Erase 0x5C (with 4-byte address), usually 32k size. + From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ +#define JEDEC_BE_5C_4BA 0x5C +#define JEDEC_BE_5C_4BA_OUTSIZE 0x05 +#define JEDEC_BE_5C_4BA_INSIZE 0x00 + +/* Block Erase 0xDC (with 4-byte address), usually 64k size. + From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */ +#define JEDEC_BE_DC_4BA 0xdc +#define JEDEC_BE_DC_4BA_OUTSIZE 0x05 +#define JEDEC_BE_DC_4BA_INSIZE 0x00 + +/* Enter 4-byte Address Mode */ +#define JEDEC_ENTER_4_BYTE_ADDR_MODE 0xB7 +#define JEDEC_ENTER_4_BYTE_ADDR_MODE_OUTSIZE 0x01 +#define JEDEC_ENTER_4_BYTE_ADDR_MODE_INSIZE 0x00 + +/* Exit 4-byte Address Mode */ +#define JEDEC_EXIT_4_BYTE_ADDR_MODE 0xE9 +#define JEDEC_EXIT_4_BYTE_ADDR_MODE_OUTSIZE 0x01 +#define JEDEC_EXIT_4_BYTE_ADDR_MODE_INSIZE 0x00 + +/* Write Extended Address Register */ +#define JEDEC_WRITE_EXT_ADDR_REG 0xC5 +#define JEDEC_WRITE_EXT_ADDR_REG_OUTSIZE 0x02 +#define JEDEC_WRITE_EXT_ADDR_REG_INSIZE 0x00 + +/* Read Extended Address Register */ +#define JEDEC_READ_EXT_ADDR_REG 0xC8 +#define JEDEC_READ_EXT_ADDR_REG_OUTSIZE 0x01 +#define JEDEC_READ_EXT_ADDR_REG_INSIZE 0x01 + + +/* JEDEC Basic Flash Parameters Table definition */ +#define JEDEC_BFPT_ID 0xFF00 + +/* JEDEC Basic Flash Parameters Table 16th dword according to JESD216B */ +/* 16th dword of BFPT, bits 24:31 (Enter 4-Byte Addressing) */ +#define JEDEC_BFPT_DW16_ENTER_B7 (1UL << 24) +#define JEDEC_BFPT_DW16_ENTER_B7_WE (1UL << 25) +#define JEDEC_BFPT_DW16_ENTER_EXTENDED_ADDR_REG (1UL << 26) +#define JEDEC_BFPT_DW16_ENTER_BANK_ADDR_REG_EN_BIT (1UL << 27) +#define JEDEC_BFPT_DW16_ENTER_NV_CONFIG_REG (1UL << 28) +#define JEDEC_BFPT_DW16_VENDOR_SET (1UL << 29) +#define JEDEC_BFPT_DW16_4_BYTES_ADDRESS_ONLY (1UL << 30) +#define JEDEC_BFPT_DW16_ENTER_RESERVED (1UL << 31) +/* 16th dword of BFPT, bits 14:23 (Exit 4-Byte Addressing) */ +#define JEDEC_BFPT_DW16_EXIT_E9 (1UL << 14) +#define JEDEC_BFPT_DW16_EXIT_E9_WE (1UL << 15) +#define JEDEC_BFPT_DW16_EXIT_EXTENDED_ADDR_REG (1UL << 16) +#define JEDEC_BFPT_DW16_EXIT_BANK_ADDR_REG_EN_BIT (1UL << 17) +#define JEDEC_BFPT_DW16_EXIT_NV_CONFIG_REG (1UL << 18) +#define JEDEC_BFPT_DW16_EXIT_HARD_RESET (1UL << 19) +#define JEDEC_BFPT_DW16_EXIT_SOFT_RESET (1UL << 20) +#define JEDEC_BFPT_DW16_EXIT_POWER_CYCLE (1UL << 21) +#define JEDEC_BFPT_DW16_EXIT_RESERVED_1 (1UL << 22) +#define JEDEC_BFPT_DW16_EXIT_RESERVED_2 (1UL << 23) + +/* JEDEC 4-Bytes Addressing Table 1st dword according to JESD216B */ +#define JEDEC_4BAIT_ID 0xFF84 +#define JEDEC_4BAIT_READ_SUPPORT (1UL << 0) +#define JEDEC_4BAIT_PROGRAM_SUPPORT (1UL << 6) +#define JEDEC_4BAIT_ERASE_TYPE_1_SUPPORT (1UL << 9) +#define JEDEC_4BAIT_ERASE_TYPE_2_SUPPORT (1UL << 10) +#define JEDEC_4BAIT_ERASE_TYPE_3_SUPPORT (1UL << 11) +#define JEDEC_4BAIT_ERASE_TYPE_4_SUPPORT (1UL << 12) + +/* read/write flash bytes in 4-bytes addressing mode */ +int spi_byte_program_4ba(struct flashctx *flash, unsigned int addr, uint8_t databyte); +int spi_nbyte_program_4ba(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len); +int spi_nbyte_read_4ba(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); + +/* read/write flash bytes with 4-bytes address from any mode (3-byte or 4-byte) */ +int spi_byte_program_4ba_direct(struct flashctx *flash, unsigned int addr, uint8_t databyte); +int spi_nbyte_program_4ba_direct(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len); +int spi_nbyte_read_4ba_direct(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); + +/* read/write flash bytes from 3-bytes addressing mode using extended address register */ +int spi_byte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, uint8_t databyte); +int spi_nbyte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len); +int spi_nbyte_read_4ba_ereg(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); + +/* enter 4-bytes addressing mode */ +int spi_enter_4ba_b7(struct flashctx *flash); +int spi_enter_4ba_b7_we(struct flashctx *flash); + +/* erase functions choosers for 4-bytes addressing mode */ +erasefunc_t *spi_get_erasefn_from_opcode_4ba(uint8_t opcode); +erasefunc_t *spi_get_erasefn_from_opcode_4ba_direct(uint8_t opcode); + +/* erase flash bytes in 4-bytes addressing mode */ +int spi_block_erase_20_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_52_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_d8_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + +/* erase flash bytes from 3-bytes addressing mode using extended address register */ +int spi_block_erase_20_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_52_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_d8_4ba_ereg(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + +/* selection of erase function between 4-bytes addressing mode and use of extended address register */ +int spi_block_erase_20_4ba_selector(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_52_4ba_selector(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_d8_4ba_selector(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + +/* erase flash bytes with 4-bytes address from any mode (3-byte or 4-byte) */ +int spi_block_erase_21_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_5c_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_block_erase_dc_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); + + +#endif /* __SPI_4BA_H__ */ Property changes on: spi4ba.h ___________________________________________________________________ Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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about CH341A programmer
by novoagansk＠gmail.com 06 Jan '15

06 Jan '15

Здравствуйте, . Sorry, Please tell me about: how add support for this programmer in flashrom? If you can - please tell me "example" how USB device parallel add in flashrom. or other links to support any usb devices in flashrom.. CH341A usb chip: http://www.seekic.com/circuit_diagram/Basic_Circuit/USB_to_parallel_serial_… ebay CH341A programmer -- С уважением, Novoagansk mailto:novoagansk@gmail.com

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Re: [flashrom] Verbose Log
by Stefan Tauner 06 Jan '15

06 Jan '15

On Sun, 4 Jan 2015 23:35:09 +0100 Rainer Spillmann <rainerspillmann(a)googlemail.com> wrote: > Hello Flashrom, > > I could update a Fujitsu Esprimo E5625 (mainboard D2724-A1x) to a Esprimo > E5635 (mainboard D2904-A1x) to support AMD AM2/AM3 C3 revision processors. > I have used the official E5635 bios from the fujitsu website which normally > would say when trying to update that the bios does not match the system due > to it is a E5625. The only difference of the E5635 is a chassis lock on the > mainboard. It now works perfect. > > Normally the used Esprimo E5625 does only support due to missing microcode > and older AMD agesa rom up to AMD C2 prozessors witht the official E5625 > bios. > ( > http://en.wikipedia.org/wiki/List_of_AMD_Phenom_microprocessors#.22Rana.22_… > ) Hello Rainer, thank you for your report. The log file got mangled too much to be useful (you better should have used the -o option of flashrom I guess). Anyway, if I interpret your mail correctly apart from sharing your story you also want me to add the D2724-A1x to our list of tested boards. Is that correct? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

Report
by novoagansk＠gmail.com 06 Jan '15

06 Jan '15

Здравствуйте, Flashrom. I try read chip cFeon EN25P64 - 16 pins, through adapter SPI 16 to 8 but flashrom show two INVALID variants: #flashrom -p ft2232_spi:type=arm-usb-tiny-h flashrom v0.9.7-r1852 on Linux 3.2.66 (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found Eon flash chip "EN25B64" (8192 kB, SPI) on ft2232_spi. Found Eon flash chip "EN25B64T" (8192 kB, SPI) on ft2232_spi. Multiple flash chip definitions match the detected chip(s): "EN25B64", "EN25B64T" Please specify which chip definition to use with the -c <chipname> option. read normally: date flashrom -p ft2232_spi:type=arm-usb-tiny-h -c EN25B64 -r 234 date 1 min 5 sec write okey: flashrom -p ft2232_spi:type=arm-usb-tiny-h -c EN25B64 -w 3883 flashrom v0.9.7-r1852 on Linux 3.2.66 (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found Eon flash chip "EN25B64" (8192 kB, SPI) on ft2232_spi. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash chip. Please include the flashrom log file for all operations you tested (see the man page for details), and mention which mainboard or programmer you tested in the subject line. Thanks for your help! Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. my OS is debian 32bit, programmer ARM-USB-TINY-H i have tested other my chips - all ok: :~/spi# flashrom -p ft2232_spi:type=arm-usb-tiny-h -c "MX25L3205(A)" -r MX25L3205 flashrom v0.9.7-r1852 on Linux 3.2.66 (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found Macronix flash chip "MX25L3205(A)" (4096 kB, SPI) on ft2232_spi. Reading flash... done. :~/spi# flashrom -p ft2232_spi:type=arm-usb-tiny-h flashrom v0.9.7-r1852 on Linux 3.2.66 (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found Micron/Numonyx/ST flash chip "M25P64" (8192 kB, SPI) on ft2232_spi. No operations were specified. :~/spi# flashrom -p ft2232_spi:type=arm-usb-tiny-h -r M25P64 flashrom v0.9.7-r1852 on Linux 3.2.66 (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found Micron/Numonyx/ST flash chip "M25P64" (8192 kB, SPI) on ft2232_spi. Reading flash... done. :~/spi# flashrom -p ft2232_spi:type=arm-usb-tiny-h -r 25X32VF flashrom v0.9.7-r1852 on Linux 3.2.66 (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found Winbond flash chip "W25X32" (4096 kB, SPI) on ft2232_spi. Reading flash... done. :~/spi# flashrom -p ft2232_spi:type=arm-usb-tiny-h -r W25Q32BV flashrom v0.9.7-r1852 on Linux 3.2.66 (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found Winbond flash chip "W25Q32.V" (4096 kB, SPI) on ft2232_spi. Reading flash... done. :~/spi# flashrom -p ft2232_spi:type=arm-usb-tiny-h -r FL032 flashrom v0.9.7-r1852 on Linux 3.2.66 (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found Spansion flash chip "S25FL032A/P" (4096 kB, SPI) on ft2232_spi. Reading flash... done. :~/spi# flashrom -p ft2232_spi:type=arm-usb-tiny-h -r W25Q64BV flashrom v0.9.7-r1852 on Linux 3.2.66 (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found Winbond flash chip "W25Q64.V" (8192 kB, SPI) on ft2232_spi. Reading flash... done. :~/spi# flashrom -p ft2232_spi:type=arm-usb-tiny-h -r W25Q64FV flashrom v0.9.7-r1852 on Linux 3.2.66 (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found Winbond flash chip "W25Q64.V" (8192 kB, SPI) on ft2232_spi. Reading flash... done. -- С уважением, Novoagansk mailto:novoagansk@gmail.com

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flashrom success with GD25Q20(B)
by Gilles Auréjac 06 Jan '15

06 Jan '15

hi Just to let you know that flashrom v0.9.6.1-r1704did succesfully read and wrote to a GD25Q20(B° eeprom with a buspirate v.3.b hardware. Here is the flashrom -Vw output. best regards gilles

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W836xx: Lenovo ThinkPad W530: flashrom -V
by flipmess 06 Jan '15

06 Jan '15

flashrom v0.9.7-r1711 on Linux 3.17.6-1-ARCH (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.2.0, GCC 4.8.2, little endian Command line (3 args): flashrom -V -p internal Calibrating delay loop... OS timer resolution is 1 usecs, 3457M loops per second, 10 myus = 10 us, 100 myus = 124 us, 1000 myus = 1017 us, 10000 myus = 10210 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "LENOVO" DMI string system-product-name: "2441B32" DMI string system-version: "ThinkPad W530" DMI string baseboard-manufacturer: "LENOVO" DMI string baseboard-product-name: "2441B32" DMI string baseboard-version: "Not Defined" DMI string chassis-type: "Notebook" Laptop detected via DMI. W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 00. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. ======================================================================== WARNING! You seem to be running flashrom on an unsupported laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See the manpage and http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Aborting. Error: Programmer initialization failed.

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Re: [flashrom] [PATCH] Fix wrong density encoding on Intel Silvermont.
by Stefan Tauner 05 Jan '15

05 Jan '15

On Mon, 5 Jan 2015 15:41:13 +0800 "Tai-Hong (Type) Wu" <thwu(a)lunartoday.com> wrote: > Thanks for the review and remedy. > Certainly, I will again verify the patch once it being committed into > official svn-stream (Looks not in r1860 yet?) > and/or 0.9.8-release. OK, I normally prefer tests before committing anything, but I hope there won't be a problem here. I have committed the change in r1861. Thanks for your help! -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1861 - trunk
by repository service 05 Jan '15

05 Jan '15

Author: stefanct Date: Tue Jan 6 00:00:14 2015 New Revision: 1861 URL: http://flashrom.org/trac/flashrom/changeset/1861 Log: Fix wrong density encoding on Intel Silvermont. Silvermont (Bay Trail, Rangeley, Avoton) seems to still use the old density encoding with 3 bits per chip. Documentation is unavailable (held concealed by Intel) but thanks to the efforts of Tai-Hong (Type) Wu the layout is clear now. This patch is based on his one but solves the issue differently thus reducing the code complexity. Signed-off-by: Tai-Hong Wu <thwu(a)lunartoday.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/ich_descriptors.c trunk/ich_descriptors.h Modified: trunk/ich_descriptors.c ============================================================================== --- trunk/ich_descriptors.c Sat Dec 20 21:25:19 2014 (r1860) +++ trunk/ich_descriptors.c Tue Jan 6 00:00:14 2015 (r1861) @@ -127,27 +127,27 @@ case CHIPSET_ICH10: case CHIPSET_5_SERIES_IBEX_PEAK: case CHIPSET_6_SERIES_COUGAR_POINT: - case CHIPSET_7_SERIES_PANTHER_POINT: { + case CHIPSET_7_SERIES_PANTHER_POINT: + case CHIPSET_BAYTRAIL: { uint8_t size_enc; if (idx == 0) { - size_enc = desc->component.old.comp1_density; + size_enc = desc->component.dens_old.comp1_density; } else { - size_enc = desc->component.old.comp2_density; + size_enc = desc->component.dens_old.comp2_density; } if (size_enc > 5) return "reserved"; return size_str[size_enc]; } case CHIPSET_8_SERIES_LYNX_POINT: - case CHIPSET_BAYTRAIL: case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: case CHIPSET_9_SERIES_WILDCAT_POINT: { uint8_t size_enc; if (idx == 0) { - size_enc = desc->component.new.comp1_density; + size_enc = desc->component.dens_new.comp1_density; } else { - size_enc = desc->component.new.comp2_density; + size_enc = desc->component.dens_new.comp2_density; } if (size_enc > 7) return "reserved"; @@ -207,16 +207,16 @@ msg_pdbg2("Component 2 density: %s\n", pprint_density(cs, desc, 1)); else msg_pdbg2("Component 2 is not used.\n"); - msg_pdbg2("Read Clock Frequency: %s\n", pprint_freq(cs, desc->component.common.freq_read)); - msg_pdbg2("Read ID and Status Clock Freq.: %s\n", pprint_freq(cs, desc->component.common.freq_read_id)); - msg_pdbg2("Write and Erase Clock Freq.: %s\n", pprint_freq(cs, desc->component.common.freq_write)); - msg_pdbg2("Fast Read is %ssupported.\n", desc->component.common.fastread ? "" : "not "); - if (desc->component.common.fastread) + msg_pdbg2("Read Clock Frequency: %s\n", pprint_freq(cs, desc->component.modes.freq_read)); + msg_pdbg2("Read ID and Status Clock Freq.: %s\n", pprint_freq(cs, desc->component.modes.freq_read_id)); + msg_pdbg2("Write and Erase Clock Freq.: %s\n", pprint_freq(cs, desc->component.modes.freq_write)); + msg_pdbg2("Fast Read is %ssupported.\n", desc->component.modes.fastread ? "" : "not "); + if (desc->component.modes.fastread) msg_pdbg2("Fast Read Clock Frequency: %s\n", - pprint_freq(cs, desc->component.common.freq_fastread)); + pprint_freq(cs, desc->component.modes.freq_fastread)); if (cs > CHIPSET_6_SERIES_COUGAR_POINT) msg_pdbg2("Dual Output Fast Read Support: %sabled\n", - desc->component.new.dual_output ? "dis" : "en"); + desc->component.modes.dual_output ? "dis" : "en"); if (desc->component.FLILL == 0) msg_pdbg2("No forbidden opcodes.\n"); else { @@ -816,22 +816,22 @@ case CHIPSET_5_SERIES_IBEX_PEAK: case CHIPSET_6_SERIES_COUGAR_POINT: case CHIPSET_7_SERIES_PANTHER_POINT: + case CHIPSET_BAYTRAIL: if (idx == 0) { - size_enc = desc->component.old.comp1_density; + size_enc = desc->component.dens_old.comp1_density; } else { - size_enc = desc->component.old.comp2_density; + size_enc = desc->component.dens_old.comp2_density; } size_max = 5; break; case CHIPSET_8_SERIES_LYNX_POINT: - case CHIPSET_BAYTRAIL: case CHIPSET_8_SERIES_LYNX_POINT_LP: case CHIPSET_8_SERIES_WELLSBURG: case CHIPSET_9_SERIES_WILDCAT_POINT: if (idx == 0) { - size_enc = desc->component.new.comp1_density; + size_enc = desc->component.dens_new.comp1_density; } else { - size_enc = desc->component.new.comp2_density; + size_enc = desc->component.dens_new.comp2_density; } size_max = 7; break; @@ -842,7 +842,7 @@ } if (size_enc > size_max) { - msg_perr("Density of ICH SPI component with index %d is invalid." + msg_perr("Density of ICH SPI component with index %d is invalid.\n" "Encoded density is 0x%x while maximum allowed is 0x%x.\n", idx, size_enc, size_max); return -1; Modified: trunk/ich_descriptors.h ============================================================================== --- trunk/ich_descriptors.h Sat Dec 20 21:25:19 2014 (r1860) +++ trunk/ich_descriptors.h Tue Jan 6 00:00:14 2015 (r1861) @@ -123,23 +123,19 @@ freq_fastread :3, freq_write :3, freq_read_id :3, - :2; - } common; + dual_output :1, /* new since Cougar Point/6 */ + :1; + } modes; struct { uint32_t comp1_density :3, comp2_density :3, - :11, - :13, - :2; - } old; + :26; + } dens_old; struct { uint32_t comp1_density :4, /* new since Lynx Point/8 */ comp2_density :4, - :9, - :13, - dual_output :1, /* new since Cougar Point/6 */ - :1; - } new; + :24; + } dens_new; }; union { /* 0x04 */ uint32_t FLILL; /* Flash Invalid Instructions Register */

1 0

W836xx: Intel DP35DP: flashrom -V
by Александр Трубицын 05 Jan '15

05 Jan '15

best regards, Alexander.V.Trubitsyn

1 0

Re: [flashrom] [PATCH] Fix wrong density encoding on Intel Silvermont.
by Tai-Hong (Type) Wu 05 Jan '15

05 Jan '15

>> I will probably commit this patch before you get a chance to test it >> again because I want to do the 0.9.8 release soonish, but I'd >> appreciate a later test very much too if you want to do that. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Dear Stefan, Thanks for the review and remedy. Certainly, I will again verify the patch once it being committed into official svn-stream (Looks not in r1860 yet?) and/or 0.9.8-release. Thank you Tai-Hong Wu (T.H.Wu Type 2014-12-26 23:36 GMT+08:00 Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> : > Silvermont (Bay Trail, Rangeley, Avoton) seems to still use the old > density encoding with 3 bits per chip. Documentation is unavailable > (held concealed by Intel) but thanks to the efforts of Tai-Hong > (Type) Wu the layout is clear now. This patch is based on his one > but solves the issue differently reducing the code complexity. > > Signed-off-by: T.H.Wu Type <thwu(a)lunartoday.com> > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> > --- > > Hello Tai-Hong, > > thanks a lot for your patch! And sorry for the late reply. Now that > I got some time I have looked into your patch. Your solution seems > to work fine but I decided that I'd rather move the dual output > supported bit to the "common" bit field struct and rename all > involved structs accordingly. This gets rid of the rather unreadable > double ternary branch. > > I will probably commit this patch before you get a chance to test it > again because I want to do the 0.9.8 release soonish, but I'd > appreciate a later test very much too if you want to do that. > > ich_descriptors.c | 38 +++++++++++++++++++------------------- > ich_descriptors.h | 18 +++++++----------- > 2 files changed, 26 insertions(+), 30 deletions(-) > > diff --git a/ich_descriptors.c b/ich_descriptors.c > index 1966f66..90f70ee 100644 > --- a/ich_descriptors.c > +++ b/ich_descriptors.c > @@ -127,27 +127,27 @@ static const char *pprint_density(enum ich_chipset > cs, const struct ich_descript > case CHIPSET_ICH10: > case CHIPSET_5_SERIES_IBEX_PEAK: > case CHIPSET_6_SERIES_COUGAR_POINT: > - case CHIPSET_7_SERIES_PANTHER_POINT: { > + case CHIPSET_7_SERIES_PANTHER_POINT: > + case CHIPSET_BAYTRAIL: { > uint8_t size_enc; > if (idx == 0) { > - size_enc = desc->component.old.comp1_density; > + size_enc = desc->component.dens_old.comp1_density; > } else { > - size_enc = desc->component.old.comp2_density; > + size_enc = desc->component.dens_old.comp2_density; > } > if (size_enc > 5) > return "reserved"; > return size_str[size_enc]; > } > case CHIPSET_8_SERIES_LYNX_POINT: > - case CHIPSET_BAYTRAIL: > case CHIPSET_8_SERIES_LYNX_POINT_LP: > case CHIPSET_8_SERIES_WELLSBURG: > case CHIPSET_9_SERIES_WILDCAT_POINT: { > uint8_t size_enc; > if (idx == 0) { > - size_enc = desc->component.new.comp1_density; > + size_enc = desc->component.dens_new.comp1_density; > } else { > - size_enc = desc->component.new.comp2_density; > + size_enc = desc->component.dens_new.comp2_density; > } > if (size_enc > 7) > return "reserved"; > @@ -207,16 +207,16 @@ void prettyprint_ich_descriptor_component(enum > ich_chipset cs, const struct ich_ > msg_pdbg2("Component 2 density: %s\n", > pprint_density(cs, desc, 1)); > else > msg_pdbg2("Component 2 is not used.\n"); > - msg_pdbg2("Read Clock Frequency: %s\n", pprint_freq(cs, > desc->component.common.freq_read)); > - msg_pdbg2("Read ID and Status Clock Freq.: %s\n", pprint_freq(cs, > desc->component.common.freq_read_id)); > - msg_pdbg2("Write and Erase Clock Freq.: %s\n", pprint_freq(cs, > desc->component.common.freq_write)); > - msg_pdbg2("Fast Read is %ssupported.\n", > desc->component.common.fastread ? "" : "not "); > - if (desc->component.common.fastread) > + msg_pdbg2("Read Clock Frequency: %s\n", pprint_freq(cs, > desc->component.modes.freq_read)); > + msg_pdbg2("Read ID and Status Clock Freq.: %s\n", pprint_freq(cs, > desc->component.modes.freq_read_id)); > + msg_pdbg2("Write and Erase Clock Freq.: %s\n", pprint_freq(cs, > desc->component.modes.freq_write)); > + msg_pdbg2("Fast Read is %ssupported.\n", > desc->component.modes.fastread ? "" : "not "); > + if (desc->component.modes.fastread) > msg_pdbg2("Fast Read Clock Frequency: %s\n", > - pprint_freq(cs, > desc->component.common.freq_fastread)); > + pprint_freq(cs, > desc->component.modes.freq_fastread)); > if (cs > CHIPSET_6_SERIES_COUGAR_POINT) > msg_pdbg2("Dual Output Fast Read Support: %sabled\n", > - desc->component.new.dual_output ? "dis" : "en"); > + desc->component.modes.dual_output ? "dis" : > "en"); > if (desc->component.FLILL == 0) > msg_pdbg2("No forbidden opcodes.\n"); > else { > @@ -816,22 +816,22 @@ int getFCBA_component_density(enum ich_chipset cs, > const struct ich_descriptors > case CHIPSET_5_SERIES_IBEX_PEAK: > case CHIPSET_6_SERIES_COUGAR_POINT: > case CHIPSET_7_SERIES_PANTHER_POINT: > + case CHIPSET_BAYTRAIL: > if (idx == 0) { > - size_enc = desc->component.old.comp1_density; > + size_enc = desc->component.dens_old.comp1_density; > } else { > - size_enc = desc->component.old.comp2_density; > + size_enc = desc->component.dens_old.comp2_density; > } > size_max = 5; > break; > case CHIPSET_8_SERIES_LYNX_POINT: > - case CHIPSET_BAYTRAIL: > case CHIPSET_8_SERIES_LYNX_POINT_LP: > case CHIPSET_8_SERIES_WELLSBURG: > case CHIPSET_9_SERIES_WILDCAT_POINT: > if (idx == 0) { > - size_enc = desc->component.new.comp1_density; > + size_enc = desc->component.dens_new.comp1_density; > } else { > - size_enc = desc->component.new.comp2_density; > + size_enc = desc->component.dens_new.comp2_density; > } > size_max = 7; > break; > @@ -842,7 +842,7 @@ int getFCBA_component_density(enum ich_chipset cs, > const struct ich_descriptors > } > > if (size_enc > size_max) { > - msg_perr("Density of ICH SPI component with index %d is > invalid." > + msg_perr("Density of ICH SPI component with index %d is > invalid.\n" > "Encoded density is 0x%x while maximum allowed is > 0x%x.\n", > idx, size_enc, size_max); > return -1; > diff --git a/ich_descriptors.h b/ich_descriptors.h > index c41f9d9..2c21598 100644 > --- a/ich_descriptors.h > +++ b/ich_descriptors.h > @@ -123,23 +123,19 @@ struct ich_desc_component { > freq_fastread :3, > freq_write :3, > freq_read_id :3, > - :2; > - } common; > + dual_output :1, /* new since Cougar > Point/6 */ > + :1; > + } modes; > struct { > uint32_t comp1_density :3, > comp2_density :3, > - :11, > - :13, > - :2; > - } old; > + :26; > + } dens_old; > struct { > uint32_t comp1_density :4, /* new since Lynx > Point/8 */ > comp2_density :4, > - :9, > - :13, > - dual_output :1, /* new since Cougar > Point/6 */ > - :1; > - } new; > + :24; > + } dens_new; > }; > union { /* 0x04 */ > uint32_t FLILL; /* Flash Invalid Instructions Register */ > -- > Kind regards, Stefan Tauner > >

1 0

[PATCH 5/5] Refinements for DragonflyBSD.
by Stefan Tauner 04 Jan '15

04 Jan '15

- /usr/include/cpu/param.h defines PAGE_MASK already, hence use another name for the respective macro in nicintel_eeprom.c. - Since DragonflyBSD 3.6 DPorts is used as the default package manager. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- Makefile | 6 +++--- README | 8 ++------ hwaccess.h | 2 +- nicintel_eeprom.c | 10 +++++----- 4 files changed, 11 insertions(+), 15 deletions(-) diff --git a/Makefile b/Makefile index 201dd07..8cb39ed 100644 --- a/Makefile +++ b/Makefile @@ -111,8 +111,8 @@ LDFLAGS += -L/usr/pkg/lib endif ifeq ($(TARGET_OS), DragonFlyBSD) -CPPFLAGS += -I/usr/pkg/include -LDFLAGS += -L/usr/pkg/lib +CPPFLAGS += -I/usr/local/include +LDFLAGS += -L/usr/local/lib endif ifeq ($(TARGET_OS), DOS) @@ -815,7 +815,7 @@ endif define LIBPCI_TEST /* Avoid a failing test due to libpci header symbol shadowing breakage */ #define index shadow_workaround_index -#if !defined __NetBSD__ && !defined __DragonFly__ +#if !defined __NetBSD__ #include <pci/pci.h> #else #include <pciutils/pci.h> diff --git a/README b/README index b8dec83..b29784c 100644 --- a/README +++ b/README @@ -68,7 +68,7 @@ To compile on Linux, use: make -To compile on FreeBSD, use: +To compile on FreeBSD, OpenBSD or DragonFly BSD, use: gmake @@ -80,11 +80,7 @@ To compile on Solaris, use: gmake LDFLAGS="-L$pathtolibpci" CC="gcc -I$pathtopciheaders" CFLAGS=-O2 -To compile on NetBSD or DragonFly BSD (with pciutils, libftdi, libusb installed in /usr/pkg/), use: - - gmake - -To compile on OpenBSD, use: +To compile on NetBSD (with pciutils, libftdi, libusb installed in /usr/pkg/), use: gmake diff --git a/hwaccess.h b/hwaccess.h index f2b14df..a4fd502 100644 --- a/hwaccess.h +++ b/hwaccess.h @@ -40,7 +40,7 @@ */ #define index shadow_workaround_index -#if !defined (__NetBSD__) && !defined (__DragonFly__) +#if !defined (__NetBSD__) #include <pci/pci.h> #else #include <pciutils/pci.h> diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c index 44bc773..7597cca 100644 --- a/nicintel_eeprom.c +++ b/nicintel_eeprom.c @@ -57,7 +57,7 @@ #define EERD_DATA 16 #define BIT(x) (1<<x) -#define PAGE_MASK 0x3f +#define EE_PAGE_MASK 0x3f static uint8_t *nicintel_eebar; static struct pci_dev *nicintel_pci; @@ -94,11 +94,11 @@ static int nicintel_ee_probe(struct flashctx *flash) } } - flash->chip->page_size = PAGE_MASK + 1; + flash->chip->page_size = EE_PAGE_MASK + 1; flash->chip->tested = TEST_OK_PREW; flash->chip->gran = write_gran_1byte_implicit_erase; - flash->chip->block_erasers->eraseblocks[0].size = (PAGE_MASK + 1); - flash->chip->block_erasers->eraseblocks[0].count = (flash->chip->total_size * 1024) / (PAGE_MASK + 1); + flash->chip->block_erasers->eraseblocks[0].size = (EE_PAGE_MASK + 1); + flash->chip->block_erasers->eraseblocks[0].count = (flash->chip->total_size * 1024) / (EE_PAGE_MASK + 1); return 1; } @@ -249,7 +249,7 @@ static int nicintel_ee_write(struct flashctx *flash, const uint8_t *buf, unsigne nicintel_ee_bitbang((buf) ? *buf++ : 0xff, NULL); len--; addr++; - if (!(addr & PAGE_MASK)) + if (!(addr & EE_PAGE_MASK)) break; } nicintel_ee_bitset(EEC, EE_CS, 1); -- Kind regards, Stefan Tauner

1 0

[PATCH 4/5] Remove defaults for CC and AR.
by Stefan Tauner 04 Jan '15

04 Jan '15

AR defaults to "ar" anyway in GNU make and instead of gcc it is probably a better idea to use just cc. The latter allows to build on freebsd 10 without overriding CC or doing symlink tricks (because it uses clang as cc, provides multiple gcc packages but only versioned binaries without any actual "gcc" command name in the path). Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- Makefile | 2 -- 1 file changed, 2 deletions(-) diff --git a/Makefile b/Makefile index 96a51a3..201dd07 100644 --- a/Makefile +++ b/Makefile @@ -29,7 +29,6 @@ PROGRAM = flashrom # # Note for anyone editing this Makefile: gnumake will happily ignore any # changes in this Makefile to variables set on the command line. -CC ?= gcc STRIP ?= strip INSTALL = install DIFF = diff @@ -37,7 +36,6 @@ PREFIX ?= /usr/local MANDIR ?= $(PREFIX)/share/man CFLAGS ?= -Os -Wall -Wshadow EXPORTDIR ?= . -AR ?= ar RANLIB ?= ranlib LIBS_BASE ?= .. -- Kind regards, Stefan Tauner

1 0

[PATCH 3/5] Unify target OS and CPU architecture checks.
by Stefan Tauner 04 Jan '15

04 Jan '15

We do CPU architecture checks once for the makefile in arch.h and once for HW access abstraction in hwaccess.c. This patch unifies related files so that they can share the checks to improve maintainability and reduce the chance of inconsistencies. Furthermore, it refines some of the definitions, which - adds "support" for AARCH64 and PPC64, - adds big-endian handling on arm as well as LE handling on PPC64, - fixes compilation of internal.c on AARCH64 and PPC64. Additionally, this patch continues to unify all OS checks in flashrom by adding a new helper macro IS_WINDOWS. The old header file for architecture checking is renamed to platform.h to reflect its broader scope and all new macros are add in there. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- Makefile | 2 +- arch.h | 33 --------- archtest.c | 2 + flash.h | 4 +- flashrom.c | 2 +- hwaccess.c | 20 ++---- hwaccess.h | 87 +++++++++++++++--------- internal.c | 16 ++--- os.h | 2 + platform.h | 54 +++++++++++++++ programmer.h | 2 +- serial.c | 40 +++++------ serprog.c | 10 +-- udelay.c | 2 +- util/ich_descriptors_tool/ich_descriptors_tool.c | 2 +- 15 files changed, 163 insertions(+), 115 deletions(-) delete mode 100644 arch.h create mode 100644 archtest.c create mode 100644 platform.h diff --git a/Makefile b/Makefile index 7d3da08..96a51a3 100644 --- a/Makefile +++ b/Makefile @@ -316,7 +316,7 @@ endif # IMPORTANT: The following line must be placed before ARCH is ever used # (of course), but should come after any lines setting CC because the line # below uses CC itself. -override ARCH := $(strip $(shell LC_ALL=C $(CC) $(CPPFLAGS) -E arch.h 2>/dev/null | grep -v '^\#' | grep '"' | cut -f 2 -d'"')) +override ARCH := $(strip $(shell LC_ALL=C $(CC) $(CPPFLAGS) -E archtest.c 2>/dev/null | grep -v '^\#' | grep '"' | cut -f 2 -d'"')) # PCI port I/O support is unimplemented on PPC/MIPS and unavailable on ARM. # Right now this means the drivers below only work on x86. diff --git a/arch.h b/arch.h deleted file mode 100644 index f3f3b0d..0000000 --- a/arch.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the flashrom project. - * - * Copyright (C) 2011 Carl-Daniel Hailfinger - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* - * Header file for CPU architecture checking. - */ - -#if defined (__i386__) || defined (__x86_64__) -#define __FLASHROM_ARCH__ "x86" -#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) -#define __FLASHROM_ARCH__ "mips" -#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) -#define __FLASHROM_ARCH__ "ppc" -#elif defined(__arm__) -#define __FLASHROM_ARCH__ "arm" -#endif -__FLASHROM_ARCH__ diff --git a/archtest.c b/archtest.c new file mode 100644 index 0000000..791f1a3 --- /dev/null +++ b/archtest.c @@ -0,0 +1,2 @@ +#include "platform.h" +__FLASHROM_ARCH__ diff --git a/flash.h b/flash.h index 81fd61b..56d9e4b 100644 --- a/flash.h +++ b/flash.h @@ -24,12 +24,14 @@ #ifndef __FLASH_H__ #define __FLASH_H__ 1 +#include "platform.h" + #include <inttypes.h> #include <stdio.h> #include <stdint.h> #include <stddef.h> #include <stdbool.h> -#ifdef _WIN32 +#if IS_WINDOWS #include <windows.h> #undef min #undef max diff --git a/flashrom.c b/flashrom.c index 104ecb8..9df1478 100644 --- a/flashrom.c +++ b/flashrom.c @@ -1661,7 +1661,7 @@ void list_programmers_linebreak(int startcol, int cols, int paren) void print_sysinfo(void) { -#ifdef _WIN32 +#if IS_WINDOWS SYSTEM_INFO si; OSVERSIONINFOEX osvi; diff --git a/hwaccess.c b/hwaccess.c index 5b18c32..c90490b 100644 --- a/hwaccess.c +++ b/hwaccess.c @@ -18,19 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define IS_X86 (defined(__i386__) || defined(__x86_64__) || defined(__amd64__)) -#define IS_MIPS (defined (__mips) || defined (__mips__) || defined (__MIPS__) || defined (mips)) -#define IS_PPC (defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__)) -#define IS_ARM (defined (__arm__) || defined (_ARM)) -#if !(IS_X86 || IS_MIPS || IS_PPC || IS_ARM) -#error Unknown architecture -#endif - -#define IS_LINUX (defined(__gnu_linux__) || defined(__linux__)) -#define IS_MACOSX (defined(__APPLE__) && defined(__MACH__)) -#if !(IS_LINUX || IS_MACOSX || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__DJGPP__) || defined(__LIBPAYLOAD__) || defined(__sun)) -#error "Unknown operating system" -#endif +#include "platform.h" #include <stdint.h> #include <string.h> @@ -45,6 +33,10 @@ #include "flash.h" #include "hwaccess.h" +#if !(IS_LINUX || IS_MACOSX || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__DJGPP__) || defined(__LIBPAYLOAD__) || defined(__sun)) +#error "Unknown operating system" +#endif + #define USE_IOPL (IS_LINUX || IS_MACOSX || defined(__NetBSD__) || defined(__OpenBSD__)) #define USE_DEV_IO (defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)) @@ -62,7 +54,7 @@ static inline void sync_primitive(void) * - MIPS uses uncached accesses in mode 2 on /dev/mem which has also a strongly ordered memory model * - ARM uses a strongly ordered memory model for device memories. */ -#if IS_PPC +#if IS_PPC // cf. http://lxr.free-electrons.com/source/arch/powerpc/include/asm/barrier.h asm("eieio" : : : "memory"); #endif } diff --git a/hwaccess.h b/hwaccess.h index 83f349e..f2b14df 100644 --- a/hwaccess.h +++ b/hwaccess.h @@ -24,7 +24,9 @@ #ifndef __HWACCESS_H__ #define __HWACCESS_H__ 1 -#if defined (__i386__) || defined (__x86_64__) +#include "platform.h" + +#if IS_X86 #if defined(__GLIBC__) #include <sys/io.h> #endif @@ -45,14 +47,22 @@ #endif #undef index +#endif /* NEED_PCI == 1 */ + + +/* The next big hunk tries to guess endianess from various preprocessor macros */ +/* First some error checking in case some weird header has defines both. + * NB: OpenBSD always defines _BIG_ENDIAN and _LITTLE_ENDIAN. */ +#if defined (__LITTLE_ENDIAN__) && defined (__BIG_ENDIAN__) +#error Conflicting endianness #define #endif -#if defined (__i386__) || defined (__x86_64__) +#if IS_X86 /* All x86 is little-endian. */ #define __FLASHROM_LITTLE_ENDIAN__ 1 -#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) +#elif IS_MIPS /* MIPS can be either endian. */ #if defined (__MIPSEL) || defined (__MIPSEL__) || defined (_MIPSEL) || defined (MIPSEL) @@ -61,29 +71,45 @@ #define __FLASHROM_BIG_ENDIAN__ 1 #endif -#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) +#elif IS_PPC /* PowerPC can be either endian. */ #if defined (_BIG_ENDIAN) || defined (__BIG_ENDIAN__) #define __FLASHROM_BIG_ENDIAN__ 1 -/* Error checking in case some weird header has #defines for LE as well. */ -#if defined (_LITTLE_ENDIAN) || defined (__LITTLE_ENDIAN__) -#error Conflicting endianness #define -#endif -#else -#error Little-endian PowerPC #defines are unknown +#elif defined (_LITTLE_ENDIAN) || defined (__LITTLE_ENDIAN__) +#define __FLASHROM_LITTLE_ENDIAN__ 1 #endif -#elif defined (__arm__) -#if defined (__ARMEL__) +#elif IS_ARM + +/* ARM can be either endian. */ +#if defined (__ARMEB__) +#define __FLASHROM_BIG_ENDIAN__ 1 +#elif defined (__ARMEL__) #define __FLASHROM_LITTLE_ENDIAN__ 1 -#else -#error Big-endian ARM #defines are unknown #endif +#endif /* IS_? */ + +#if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__) + +/* If architecture-specific approaches fail try generic variants. First: BSD (works about everywhere). */ +#if !IS_WINDOWS +#include <sys/param.h> + +#if defined (__BYTE_ORDER) +#if __BYTE_ORDER == __LITTLE_ENDIAN +#define __FLASHROM_LITTLE_ENDIAN__ +#elif __BYTE_ORDER == __BIG_ENDIAN +#define __FLASHROM_BIG_ENDIAN__ +#else +#error Unknown byte order! #endif +#endif /* defined __BYTE_ORDER */ +#endif /* !IS_WINDOWS */ #if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__) + /* Nonstandard libc-specific macros for determining endianness. */ #if defined(__GLIBC__) #include <endian.h> @@ -95,8 +121,10 @@ #endif #endif +#endif + #if !defined (__FLASHROM_BIG_ENDIAN__) && !defined (__FLASHROM_LITTLE_ENDIAN__) -#error Unable to determine endianness. Please add support for your arch or libc. +#error Unable to determine endianness. #endif #define ___constant_swab8(x) ((uint8_t) ( \ @@ -158,11 +186,7 @@ cpu_to_be(64) #define cpu_to_le32 #define cpu_to_le64 -#else - -#error Could not determine endianness. - -#endif +#endif /* __FLASHROM_BIG_ENDIAN__ / __FLASHROM_LITTLE_ENDIAN__ */ #define be_to_cpu8 cpu_to_be8 #define be_to_cpu16 cpu_to_be16 @@ -174,12 +198,12 @@ cpu_to_be(64) #define le_to_cpu64 cpu_to_le64 #if NEED_PCI == 1 -#if defined (__i386__) || defined (__x86_64__) +#if IS_X86 #define __FLASHROM_HAVE_OUTB__ 1 /* for iopl and outb under Solaris */ -#if defined (__sun) && (defined(__i386) || defined(__amd64)) +#if defined (__sun) #include <sys/sysi86.h> #include <sys/psw.h> #include <asm/sunddi.h> @@ -202,11 +226,13 @@ cpu_to_be(64) #define INW(x) __extension__ ({ u_int inw_tmp = (x); inw(inw_tmp); }) #define INL(x) __extension__ ({ u_int inl_tmp = (x); inl(inl_tmp); }) #else + #if defined(__MACH__) && defined(__APPLE__) /* Header is part of the DirectHW library. */ #include <DirectHW/DirectHW.h> -#endif -#if defined (__sun) && (defined(__i386) || defined(__amd64)) +#else + +#if defined (__sun) /* Note different order for outb */ #define OUTB(x,y) outb(y, x) #define OUTW(x,y) outw(y, x) @@ -236,9 +262,8 @@ cpu_to_be(64) #define INB inb #define INW inw #define INL inl - #endif - +#endif #endif #endif @@ -324,15 +349,15 @@ int libpayload_wrmsr(int addr, msr_t msr); #define wrmsr libpayload_wrmsr #endif -#elif defined(__powerpc__) || defined(__powerpc64__) || defined(__ppc__) || defined(__ppc64__) +#elif IS_PPC /* PCI port I/O is not yet implemented on PowerPC. */ -#elif defined (__mips) || defined (__mips__) || defined (_mips) || defined (mips) +#elif IS_MIPS /* PCI port I/O is not yet implemented on MIPS. */ -#elif defined(__arm__) +#elif IS_ARM /* Non memory mapped I/O is not supported on ARM. */ @@ -340,7 +365,7 @@ int libpayload_wrmsr(int addr, msr_t msr); #error Unknown architecture, please check if it supports PCI port IO. -#endif -#endif +#endif /* IS_* */ +#endif /* NEED_PCI == 1 */ #endif /* !__HWACCESS_H__ */ diff --git a/internal.c b/internal.c index e646ca8..f6146d1 100644 --- a/internal.c +++ b/internal.c @@ -160,14 +160,14 @@ enum chipbustype internal_buses_supported = BUS_NONE; int internal_init(void) { -#if __FLASHROM_LITTLE_ENDIAN__ +#if defined __FLASHROM_LITTLE_ENDIAN__ int ret = 0; #endif int force_laptop = 0; int not_a_laptop = 0; const char *board_vendor = NULL; const char *board_model = NULL; -#if defined (__i386__) || defined (__x86_64__) || defined (__arm__) +#if IS_X86 || IS_ARM const char *cb_vendor = NULL; const char *cb_model = NULL; #endif @@ -249,7 +249,7 @@ int internal_init(void) return 1; } -#if defined(__i386__) || defined(__x86_64__) || defined (__arm__) +#if IS_X86 || IS_ARM if ((cb_parse_table(&cb_vendor, &cb_model) == 0) && (board_vendor != NULL) && (board_model != NULL)) { if (strcasecmp(board_vendor, cb_vendor) || strcasecmp(board_model, cb_model)) { msg_pwarn("Warning: The mainboard IDs set by -p internal:mainboard (%s:%s) do not\n" @@ -262,7 +262,7 @@ int internal_init(void) } #endif -#if defined(__i386__) || defined(__x86_64__) +#if IS_X86 dmi_init(); /* In case Super I/O probing would cause pretty explosions. */ @@ -312,7 +312,7 @@ int internal_init(void) } } -#if __FLASHROM_LITTLE_ENDIAN__ +#ifdef __FLASHROM_LITTLE_ENDIAN__ /* try to enable it. Failure IS an option, since not all motherboards * really need this to be done, etc., etc. */ @@ -323,18 +323,18 @@ int internal_init(void) } else if (ret == ERROR_FATAL) return ret; -#if defined(__i386__) || defined(__x86_64__) +#if IS_X86 /* Probe unconditionally for ITE Super I/O chips. This enables LPC->SPI translation on IT87* and * parallel writes on IT8705F. Also, this handles the manual chip select for Gigabyte's DualBIOS. */ init_superio_ite(); -#endif if (board_flash_enable(board_vendor, board_model, cb_vendor, cb_model)) { msg_perr("Aborting to be safe.\n"); return 1; } +#endif -#if defined(__i386__) || defined(__x86_64__) || defined (__mips) +#if IS_X86 || IS_MIPS register_par_master(&par_master_internal, internal_buses_supported); return 0; #else diff --git a/os.h b/os.h index f1b366f..2e6dbaa 100644 --- a/os.h +++ b/os.h @@ -21,6 +21,8 @@ * Header file for OS checking. */ +#include "platform.h" + // Solaris #if defined (__sun) && (defined(__i386) || defined(__amd64)) #define __FLASHROM_OS__ "SunOS" diff --git a/platform.h b/platform.h new file mode 100644 index 0000000..f57fd12 --- /dev/null +++ b/platform.h @@ -0,0 +1,54 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2011 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Header file to determine target OS and CPU architecture. + */ + +#ifndef __PLATFORM_H__ +#define __PLATFORM_H__ 1 + +// Helper defines for operating systems +#define IS_LINUX (defined(__gnu_linux__) || defined(__linux__)) +#define IS_MACOSX (defined(__APPLE__) && defined(__MACH__)) /* yes, both. */ +#define IS_WINDOWS (defined(_WIN32) || defined(_WIN64) || defined(__WIN32__) || defined(__WINDOWS__)) + +// Likewise for target architectures +#if defined (__i386__) || defined (__x86_64__) || defined(__amd64__) + #define __FLASHROM_ARCH__ "x86" + #define IS_X86 1 +#elif defined (__mips) || defined (__mips__) || defined (__MIPS__) || defined (mips) + #define __FLASHROM_ARCH__ "mips" + #define IS_MIPS 1 +#elif defined(__powerpc) || defined(__powerpc__) || defined(__powerpc64__) || defined(__POWERPC__) || \ + defined(__ppc__) || defined(__ppc64__) || defined(_M_PPC) || defined(_ARCH_PPC) || \ + defined(_ARCH_PPC64) || defined(__ppc) + #define __FLASHROM_ARCH__ "ppc" + #define IS_PPC 1 +#elif defined(__arm__) || defined(__TARGET_ARCH_ARM) || defined(_ARM) || defined(_M_ARM) || defined(__arm) || \ + defined(__aarch64__) + #define __FLASHROM_ARCH__ "arm" + #define IS_ARM 1 +#endif + +#if !(IS_X86 || IS_MIPS || IS_PPC || IS_ARM) +#error Unknown architecture +#endif + +#endif /* !__PLATFORM_H__ */ diff --git a/programmer.h b/programmer.h index d6e06cb..f82e950 100644 --- a/programmer.h +++ b/programmer.h @@ -700,7 +700,7 @@ void serprog_delay(unsigned int usecs); #endif /* serial.c */ -#ifdef _WIN32 +#if IS_WINDOWS typedef HANDLE fdtype; #define SER_INV_FD INVALID_HANDLE_VALUE #else diff --git a/serial.c b/serial.c index e4e911d..94f9b7d 100644 --- a/serial.c +++ b/serial.c @@ -19,6 +19,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "platform.h" + #include <stdio.h> #include <stdlib.h> #include <unistd.h> @@ -28,7 +30,7 @@ #include <sys/stat.h> #include <errno.h> #include <inttypes.h> -#ifdef _WIN32 +#if IS_WINDOWS #include <conio.h> #else #include <termios.h> @@ -41,7 +43,7 @@ fdtype sp_fd = SER_INV_FD; -#ifdef _WIN32 +#if IS_WINDOWS struct baudentry { DWORD flag; unsigned int baud; @@ -137,7 +139,7 @@ const struct baudentry *round_baud(unsigned int baud) static void msg_perr_strerror(const char *msg) { msg_perr("Error: %s", msg); -#ifdef _WIN32 +#if IS_WINDOWS char *lpMsgBuf; DWORD nErr = GetLastError(); FormatMessage(FORMAT_MESSAGE_ALLOCATE_BUFFER | FORMAT_MESSAGE_FROM_SYSTEM, NULL, nErr, @@ -159,7 +161,7 @@ int serialport_config(fdtype fd, unsigned int baud) return 1; } -#ifdef _WIN32 +#if IS_WINDOWS DCB dcb; if (!GetCommState(fd, &dcb)) { msg_perr_strerror("Could not fetch original serial port configuration: "); @@ -224,7 +226,7 @@ int serialport_config(fdtype fd, unsigned int baud) fdtype sp_openserport(char *dev, unsigned int baud) { fdtype fd; -#ifdef _WIN32 +#if IS_WINDOWS char *dev2 = dev; if ((strlen(dev) > 3) && (tolower((unsigned char)dev[0]) == 'c') && @@ -266,7 +268,7 @@ fdtype sp_openserport(char *dev, unsigned int baud) } void sp_set_pin(enum SP_PIN pin, int val) { -#ifdef _WIN32 +#if IS_WINDOWS DWORD ctl; if(pin == PIN_TXD) { @@ -302,7 +304,7 @@ void sp_set_pin(enum SP_PIN pin, int val) { int sp_get_pin(enum SP_PIN pin) { int s; -#ifdef _WIN32 +#if IS_WINDOWS DWORD ctl; s = (pin == PIN_CTS) ? MS_CTS_ON : MS_DSR_ON; @@ -319,7 +321,7 @@ int sp_get_pin(enum SP_PIN pin) { void sp_flush_incoming(void) { -#ifdef _WIN32 +#if IS_WINDOWS PurgeComm(sp_fd, PURGE_RXCLEAR); #else /* FIXME: error handling */ @@ -330,7 +332,7 @@ void sp_flush_incoming(void) int serialport_shutdown(void *data) { -#ifdef _WIN32 +#if IS_WINDOWS CloseHandle(sp_fd); #else close(sp_fd); @@ -340,7 +342,7 @@ int serialport_shutdown(void *data) int serialport_write(const unsigned char *buf, unsigned int writecnt) { -#ifdef _WIN32 +#if IS_WINDOWS DWORD tmp = 0; #else ssize_t tmp = 0; @@ -348,7 +350,7 @@ int serialport_write(const unsigned char *buf, unsigned int writecnt) unsigned int empty_writes = 250; /* results in a ca. 125ms timeout */ while (writecnt > 0) { -#ifdef _WIN32 +#if IS_WINDOWS WriteFile(sp_fd, buf, writecnt, &tmp, NULL); #else tmp = write(sp_fd, buf, writecnt); @@ -375,14 +377,14 @@ int serialport_write(const unsigned char *buf, unsigned int writecnt) int serialport_read(unsigned char *buf, unsigned int readcnt) { -#ifdef _WIN32 +#if IS_WINDOWS DWORD tmp = 0; #else ssize_t tmp = 0; #endif while (readcnt > 0) { -#ifdef _WIN32 +#if IS_WINDOWS ReadFile(sp_fd, buf, readcnt, &tmp, NULL); #else tmp = read(sp_fd, buf, readcnt); @@ -407,7 +409,7 @@ int serialport_read_nonblock(unsigned char *c, unsigned int readcnt, unsigned in { int ret = 1; /* disable blocked i/o and declare platform-specific variables */ -#ifdef _WIN32 +#if IS_WINDOWS DWORD rv; COMMTIMEOUTS oldTimeout; COMMTIMEOUTS newTimeout = { @@ -442,7 +444,7 @@ int serialport_read_nonblock(unsigned char *c, unsigned int readcnt, unsigned in int rd_bytes = 0; for (i = 0; i < timeout; i++) { msg_pspew("readcnt %d rd_bytes %d\n", readcnt, rd_bytes); -#ifdef _WIN32 +#if IS_WINDOWS ReadFile(sp_fd, c + rd_bytes, readcnt - rd_bytes, &rv, NULL); msg_pspew("read %lu bytes\n", rv); #else @@ -466,7 +468,7 @@ int serialport_read_nonblock(unsigned char *c, unsigned int readcnt, unsigned in *really_read = rd_bytes; /* restore original blocking behavior */ -#ifdef _WIN32 +#if IS_WINDOWS if (!SetCommTimeouts(sp_fd, &oldTimeout)) { msg_perr_strerror("Could not restore serial port timeout settings: "); ret = -1; @@ -487,7 +489,7 @@ int serialport_write_nonblock(const unsigned char *buf, unsigned int writecnt, u { int ret = 1; /* disable blocked i/o and declare platform-specific variables */ -#ifdef _WIN32 +#if IS_WINDOWS DWORD rv; COMMTIMEOUTS oldTimeout; COMMTIMEOUTS newTimeout = { @@ -522,7 +524,7 @@ int serialport_write_nonblock(const unsigned char *buf, unsigned int writecnt, u int wr_bytes = 0; for (i = 0; i < timeout; i++) { msg_pspew("writecnt %d wr_bytes %d\n", writecnt, wr_bytes); -#ifdef _WIN32 +#if IS_WINDOWS WriteFile(sp_fd, buf + wr_bytes, writecnt - wr_bytes, &rv, NULL); msg_pspew("wrote %lu bytes\n", rv); #else @@ -548,7 +550,7 @@ int serialport_write_nonblock(const unsigned char *buf, unsigned int writecnt, u *really_wrote = wr_bytes; /* restore original blocking behavior */ -#ifdef _WIN32 +#if IS_WINDOWS if (!SetCommTimeouts(sp_fd, &oldTimeout)) { msg_perr_strerror("Could not restore serial port timeout settings: "); return -1; diff --git a/serprog.c b/serprog.c index e52c994..3de0182 100644 --- a/serprog.c +++ b/serprog.c @@ -19,8 +19,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "platform.h" + #include <stdio.h> -#ifndef _WIN32 /* stuff (presumably) needed for sockets only */ +#if ! IS_WINDOWS /* stuff (presumably) needed for sockets only */ #include <stdlib.h> #include <unistd.h> #include <fcntl.h> @@ -30,7 +32,7 @@ #include <netinet/tcp.h> #include <netdb.h> #endif -#ifdef _WIN32 +#if IS_WINDOWS #include <conio.h> #else #include <termios.h> @@ -83,7 +85,7 @@ static int sp_opbuf_usage = 0; whether the command is supported before doing it */ static int sp_check_avail_automatic = 0; -#ifndef WIN32 +#if ! IS_WINDOWS static int sp_opensocket(char *ip, unsigned int port) { int flag = 1; @@ -375,7 +377,7 @@ int serprog_init(void) } free(device); -#ifndef _WIN32 +#if !IS_WINDOWS device = extract_programmer_param("ip"); if (have_device && device) { msg_perr("Error: Both host and device specified.\n" diff --git a/udelay.c b/udelay.c index ee858b8..c03bcc4 100644 --- a/udelay.c +++ b/udelay.c @@ -172,7 +172,7 @@ recalibrate: /* Not very precise sleep. */ void internal_sleep(unsigned int usecs) { -#ifdef _WIN32 +#if IS_WINDOWS Sleep((usecs + 999) / 1000); #else sleep(usecs / 1000000); diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index b6c1b12..c3d9ba1 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -35,7 +35,7 @@ /* Some DJGPP builds define __unix__ although they don't support mmap(). * Cygwin defines __unix__ and supports mmap(), but it does not work well. */ -#if !defined(__MSDOS__) && !defined(_WIN32) && (defined(unix) || defined(__unix__) || defined(__unix)) || (defined(__MACH__) && defined(__APPLE__)) +#if !defined(__MSDOS__) && !IS_WINDOWS && (defined(unix) || defined(__unix__) || defined(__unix)) || (defined(__MACH__) && defined(__APPLE__)) #define HAVE_MMAP 1 #include <sys/mman.h> #endif -- Kind regards, Stefan Tauner

1 0

[PATCH 2/5] Allow to easily set a global path prefix for libraries and include files.
by Stefan Tauner 04 Jan '15

04 Jan '15

Gets rid of a few DOS-specific Makefile hacks. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- Makefile | 18 +++++++----------- README | 4 ++-- 2 files changed, 9 insertions(+), 13 deletions(-) diff --git a/Makefile b/Makefile index 1bbc4e6..7d3da08 100644 --- a/Makefile +++ b/Makefile @@ -39,7 +39,8 @@ CFLAGS ?= -Os -Wall -Wshadow EXPORTDIR ?= . AR ?= ar RANLIB ?= ranlib -DOSLIBS_BASE ?= .. +LIBS_BASE ?= .. + # The following parameter changes the default programmer that will be used if there is no -p/--programmer # argument given when running flashrom. The predefined setting does not enable any default so that every # user has to declare the programmer he wants to use on every run. The rationale for this to be not set @@ -66,6 +67,9 @@ ifeq ($(WARNERROR), yes) CFLAGS += -Werror endif +CPPFLAGS += -I$(LIBS_BASE)/include +LDFLAGS += -L$(LIBS_BASE)/lib + ############################################################################### # General OS-specific settings. # 1. Prepare for later by gathering information about host and target OS @@ -115,12 +119,9 @@ endif ifeq ($(TARGET_OS), DOS) EXEC_SUFFIX := .exe -CPPFLAGS += -I$(DOSLIBS_BASE)/libgetopt # DJGPP has odd uint*_t definitions which cause lots of format string warnings. CFLAGS += -Wno-format -# FIXME Check if we can achieve the same effect with -L../libgetopt -lgetopt LIBS += -lgetopt -LDFLAGS += -L$(DOSLIBS_BASE)/libgetopt/ # Bus Pirate, Serprog and PonyProg are not supported under DOS (missing serial support). ifeq ($(CONFIG_BUSPIRATE_SPI), yes) UNSUPPORTED_FEATURES += CONFIG_BUSPIRATE_SPI=yes @@ -710,12 +711,9 @@ PCILIBS += -lpciutils -lpci # For (i386|x86_64)_iopl(2). PCILIBS += -l$(shell uname -p) else -ifeq ($(TARGET_OS), DOS) -CPPFLAGS += -I$(DOSLIBS_BASE)/libpci/include -LDFLAGS += -L$(DOSLIBS_BASE)/libpci/lib/ -PCILIBS += -lpci -else + PCILIBS += -lpci + ifeq ($(TARGET_OS), OpenBSD) # For (i386|amd64)_iopl(2). PCILIBS += -l$(shell uname -m) @@ -723,8 +721,6 @@ else ifeq ($(TARGET_OS), Darwin) # DirectHW framework can be found in the DirectHW library. PCILIBS += -framework IOKit -framework DirectHW -else -endif endif endif endif diff --git a/README b/README index b3e50a6..b8dec83 100644 --- a/README +++ b/README @@ -106,9 +106,9 @@ To cross-compile on Linux for DOS: You will need the following library source trees containing their compiled static libraries either in the parent directory of the flashrom source or - specify the base folder on compile time with the DOSLIBS_BASE parameter. + specify the base folder on compile time with the LIBS_BASE parameter. The default as described above is equal to calling - 'make djgpp-dos DOSLIBS_BASE=..' + 'make djgpp-dos LIBS_BASE=..' To get and build said libraries... Download pciutils 3.1.5 and apply http://flashrom.org/File:Pciutils.patch.gz -- Kind regards, Stefan Tauner

1 0

[PATCH 1/5] Refine revision handling.
by Stefan Tauner 04 Jan '15

04 Jan '15

Up to now, when compiling flashrom outside a VCS it would print two warnings that are not very clear to the user. This patch adds a new auxilary function to getrevision.sh and uses it in the makefile to print a single and more meaningful message to the user while hiding the warnings from getrevision.sh. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- Makefile | 9 +++++++-- util/getrevision.sh | 10 ++++++++++ 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index a59a8f1..1bbc4e6 100644 --- a/Makefile +++ b/Makefile @@ -373,7 +373,7 @@ CLI_OBJS = cli_classic.o cli_output.o cli_common.o print.o # Set the flashrom version string from the highest revision number of the checked out flashrom files. # Note to packagers: Any tree exported with "make export" or "make tarball" # will not require subversion. The downloadable snapshots are already exported. -SVNVERSION := $(shell ./util/getrevision.sh -u) +SVNVERSION := $(shell ./util/getrevision.sh -u 2>/dev/null ) RELEASE := 0.9.7 VERSION := $(RELEASE)-$(SVNVERSION) @@ -381,6 +381,11 @@ RELEASENAME ?= $(VERSION) SVNDEF := -D'FLASHROM_VERSION="$(VERSION)"' +# Inform user if there is no meaningful version string. If there is version information from a VCS print +# something anyway because $(info...) will print a line break in any case which would look suspicious. +$(info $(shell ./util/getrevision.sh -c 2>/dev/null || echo "Files don't seem to be under version control." ; \ + echo "Replacing all version templates with $(VERSION)." )) + ############################################################################### # Default settings of CONFIG_* variables. @@ -992,7 +997,7 @@ endif @rm -f .featuretest.c .featuretest$(EXEC_SUFFIX) $(PROGRAM).8: $(PROGRAM).8.tmpl - @sed -e '1 s#".*".*#"$(shell ./util/getrevision.sh -d $(PROGRAM).8.tmpl)" "$(VERSION)"#' <$< >$@ + @sed -e '1 s#".*".*#"$(shell ./util/getrevision.sh -d $(PROGRAM).8.tmpl 2>/dev/null)" "$(VERSION)"#' <$< >$@ install: $(PROGRAM)$(EXEC_SUFFIX) $(PROGRAM).8 mkdir -p $(DESTDIR)$(PREFIX)/sbin diff --git a/util/getrevision.sh b/util/getrevision.sh index e50db75..1012058 100755 --- a/util/getrevision.sh +++ b/util/getrevision.sh @@ -215,6 +215,10 @@ upstream_revision() { echo "${r}" } +is_tracked() { + is_file_tracked "$1" +} + show_help() { echo "Usage: ${0} <command> [path] @@ -222,6 +226,8 @@ show_help() { Commands -h or --help this message + -c or --check + test if path is under version control at all -l or --local local revision information including an indicator for uncommitted changes -u or --upstream @@ -274,6 +280,10 @@ main() { check_action $1 action="timestamp +%Y-%m-%dT%H:%M:%SZ" # There is only one valid time format! ISO 8601 shift;; + -c|--check) + check_action=$1 + action="is_tracked" + shift;; -*) show_help; echo "Error: Invalid option: ${1}" -- Kind regards, Stefan Tauner

1 0

[PATCH 0/5] Cross Compilation Refinements
by Stefan Tauner 04 Jan '15

04 Jan '15

I have created some cross compilation fixes while working on the buildbot. Most of them are compile-tested apart from the following platforms: - Solaris (I could not get any variant to install in VirtualBox on ESXi in a timely manner). - MIPS no cross compiler binary package available at buildbot host - SPARC is currently also untested. No intended changes there though. The part of 2/5 that introduces relative default library and include paths may be a bad idea...? 4/5 might break some setups but I'd declare those broken. Everything else is pretty straight forward and since it is almost completely compile-tested I don't expect many surprises and will commit them soonish... followed by a 0.9.8-rc1 tag. So *if* you want to comment on these do so quickly, thanks. Stefan Tauner (5): Refine revision handling. Allow to easily set a global path prefix for libraries and include files. Unify target OS and CPU architecture checks. Remove defaults for CC and AR. Refinements for DragonflyBSD. Makefile | 37 +++++----- README | 12 ++-- arch.h | 33 --------- archtest.c | 2 + flash.h | 4 +- flashrom.c | 2 +- hwaccess.c | 20 ++---- hwaccess.h | 89 +++++++++++++++--------- internal.c | 16 ++--- nicintel_eeprom.c | 10 +-- os.h | 2 + platform.h | 54 ++++++++++++++ programmer.h | 2 +- serial.c | 40 ++++++----- serprog.c | 10 +-- udelay.c | 2 +- util/getrevision.sh | 10 +++ util/ich_descriptors_tool/ich_descriptors_tool.c | 2 +- 18 files changed, 200 insertions(+), 147 deletions(-) delete mode 100644 arch.h create mode 100644 archtest.c create mode 100644 platform.h -- Kind regards, Stefan Tauner

1 0

Verbose Log
by Rainer Spillmann 04 Jan '15

04 Jan '15

Hello Flashrom, I could update a Fujitsu Esprimo E5625 (mainboard D2724-A1x) to a Esprimo E5635 (mainboard D2904-A1x) to support AMD AM2/AM3 C3 revision processors. I have used the official E5635 bios from the fujitsu website which normally would say when trying to update that the bios does not match the system due to it is a E5625. The only difference of the E5635 is a chassis lock on the mainboard. It now works perfect. Normally the used Esprimo E5625 does only support due to missing microcode and older AMD agesa rom up to AMD C2 prozessors witht the official E5625 bios. ( http://en.wikipedia.org/wiki/List_of_AMD_Phenom_microprocessors#.22Rana.22_… ) Regards Rainer

1 0

W836xx: Lenovo U530: flashrom -V
by Sean McCully 03 Jan '15

03 Jan '15

flashrom v0.9.7-r1860 on Linux 3.17.6-1-ARCH (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.3.0, GCC 4.9.2 20141224 (prerelease), little endian Command line (3 args): ./flashrom -V -p internal Calibrating delay loop... OS timer resolution is 1 usecs, 2388M loops per second, delay more than 10% too short (got 87% of expected delay), recalculating... 2855M loops per second, 10 myus = 9 us, 100 myus = 92 us, 1000 myus = 937 us, 10000 myus = 9612 us, 4 myus = 3 us, OK. Initializing internal programmer No coreboot table found. Using Internal DMI decoder. No DMI table found. W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 85. Please send the output of "flashrom -V -p internal" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. Found ITE EC, ID 0x8587, Rev 0x06 on port 0x2e. Found chipset "Intel Lynx Point LP Premium" with PCI ID 8086:9c43. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... Root Complex Register Block address = 0xfed1c000 GCS = 0x21: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x0 (SPI) Top Swap: enabled (A16(+) inverted) 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode enabled 0xff600000/0xff200000 FWH decode enabled 0xff500000/0xff100000 FWH decode enabled 0xff400000/0xff000000 FWH decode enabled Maximum FWH chip size: 0x100000 bytes SPI Read Configuration: prefetching disabled, caching enabled, BIOS_CNTL = 0x02: BIOS Lock Enable: enabled, BIOS Write Enable: disabled SPIBAR = 0x00007f40a1449000 + 0x3800 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 Reading OPCODES... done 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x50: 0x00004a4b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x4a, BRRA 0x4b 0x54: 0x00000000 0x58: 0x07ff0180 FREG1: BIOS region (0x00180000-0x007fffff) is read-write. 0x5C: 0x017f0001 0x74: 0x87ff0700 0x78: 0x86a101d2 Writes have been disabled for safety reasons. You can enforce write support with the ich_spi_force programmer option, but you will most likely harm your hardware! If you force flashrom you will get no support if something breaks. On a few mainboards it is possible to enable write access by setting a jumper (see its documentation or the board itself). 0x90: 0xc4 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xf84200 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=2, SME=0, SCF=0 0x94: 0x0606 (PREOP) 0x96: 0xf27c (OPTYPE) 0x98: 0x0102209f (OPMENU) 0x9C: 0x00000503 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x80802025 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xC8: 0x00002025 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20 0xD0: 0x50444653 (FPB) PROBLEMS, continuing anyway The following protocols are supported: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25LQ16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25LQ032/A25LQ32A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25LQ64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DL081, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DL161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25F512, 64 kB: Invalid OPCODE 0x15, will not execute. Probing for Atmel AT25F512A, 64 kB: Invalid OPCODE 0x15, will not execute. Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25F1024(A), 128 kB: Invalid OPCODE 0x15, will not execute. Probing for Atmel AT25F2048, 256 kB: Invalid OPCODE 0x15, will not execute. Probing for Atmel AT25F4096, 512 kB: Invalid OPCODE 0x15, will not execute. Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB321E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ESMT F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ESMT F25L32PA, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25QH32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25QH64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25QH128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25LQ32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q20(B), 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q40(B), 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q80(B), 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q16(B), 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q32(B), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q64(B), 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q128B, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25T80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F160S33B8, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F160S33T8, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F320S33B8, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F320S33T8, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F640S33B8, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F640S33T8, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX23L1654, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX23L3254, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX23L6454, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX23L12854, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L512(E)/MX25V512(C), 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1005(C)/MX25L1006E, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L2005(C), 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L4005(A/C), 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L8005/MX25V8005, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1605A/MX25L1606E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1605D/MX25L1608D/MX25L1673E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L3205(A), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L3205D/MX25L3208D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L3206E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L3273E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L6405(D), 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L6406E/MX25L6436E, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L6445E/MX25L6473E, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L12805(D), 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25U1635E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25U3235E/F, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25U6435E/F, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25U12835F, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P05, 64 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P10, 128 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P20-old, 256 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PX80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M45PE10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M45PE20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M45PE40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M45PE80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M45PE16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q032..1E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q032..3E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q064..1E, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q064..3E, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q128..1E, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q128..3E, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Nantronics N25S10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Nantronics N25S20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Nantronics N25S40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Nantronics N25S80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Nantronics N25S16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LD256C, 32 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LD512(C), 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LD010(C), 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LD020(C), 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LD040(C), 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV512(A), 64 kB: Invalid OPCODE 0xab, will not execute. Probing for PMC Pm25LV010, 128 kB: Invalid OPCODE 0xab, will not execute. Probing for PMC Pm25LV010A, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Sanyo LE25FW106, 128 kB: Invalid OPCODE 0xab, will not execute. Probing for Sanyo LE25FW406A, 512 kB: Invalid OPCODE 0xab, will not execute. Probing for Sanyo LE25FU406B, 512 kB: Invalid OPCODE 0xab, will not execute. Probing for Sanyo LE25FW203A, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Sanyo LE25FW403A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Sanyo LE25FW418A, 512 kB: Invalid OPCODE 0xab, will not execute. Probing for Sanyo LE25FW806, 1024 kB: Invalid OPCODE 0xab, will not execute. Probing for Sanyo LE25FW808, 1024 kB: Invalid OPCODE 0xab, will not execute. Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL032A/P, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL064A/P, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL204K, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL208K, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL116K/S25FL216K, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL132K, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL164K, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL127S-64kB, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL127S-256kB, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL128P......0, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL128P......1, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL128S......0, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL128S......1, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL129P......0, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL129P......1, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25LF020A, 256 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25LF040A, 512 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25LF080(A), 1024 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25VF512(A), 64 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF010(A), 128 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF020, 256 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF020B, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF040, 512 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF040B.REMS, 512 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25WF512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25WF010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25WF020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25WF040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25WF080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q40.V, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q80.V, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q16.V, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q32.V, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q64.V, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Found Winbond flash chip "W25Q64.V" (8192 kB, SPI) mapped at physical address 0x00000000ff800000. Chip status register is 0x02. Probing for Winbond W25Q128.V, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q20.W, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q40.W, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q80.W, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q16.W, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q32.W, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q64.W, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Unknown SFDP-capable chip, 0 kB: Invalid OPCODE 0x5a, will not execute. Receiving SFDP signature failed. Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond unknown Winbond (ex Nexcom) SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Generic unknown SPI chip (REMS), 0 kB: Invalid OPCODE 0x90, will not execute. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49LH00B4, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49LH004, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Found Winbond flash chip "W25Q64.V" (8192 kB, SPI). This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). No operations were specified. Restoring MMIO space at 0x7f40a144c8a0 Restoring PCI config space for 00:1f:0 reg 0xdc

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W836xx: (Lenovo U530) : flashrom -V
by Sean McCully 03 Jan '15

03 Jan '15

Unsure of the Motherboard, http://download.lenovo.com/consumer/mobiles_pub/ideapad_u530touch_hmm.pdf

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Re: [flashrom] Intel 28F001BN/BX-T erase/write operation verified on 3C905B-TXNM
by Lu Xie 03 Jan '15

03 Jan '15

Hi, I performed another erase and 5 write operations on that chip with the same network adapter. Hopefully it has some useful data here. I flashed the chip with different BIOS's and they work on their desired boards. Lu On Wed, Dec 31, 2014 at 7:14 AM, Lu Xie <lxie1(a)andrew.cmu.edu> wrote: > Yes. There is another flash between the two. The chip is > bootblock-protected unless PIN30 is pulled up to 12V. I forgot that and > flashrom failed to complete flashing. I flashed again with that PIN wired > to 12V and send you the log of the successful flash. So I guess flashrom > only flashed bootblock this time. > On Dec 30, 2014 11:15 AM, "Stefan Tauner" < > stefan.tauner(a)alumni.tuwien.ac.at> wrote: > >> On Sat, 13 Dec 2014 05:42:33 +0800 >> Lu Xie <firexl(a)gmail.com> wrote: >> >> > Hi, >> > >> > I tried programming Intel 28F001BN/BX-T on 3C905B-TXNM but it failed at >> > erase/write. I checked that chip's datasheet and it says PIN 1 and 30 >> must >> > be pulled to 12V to accept erase/write operation, but the card can only >> > offer 5V at PIN 1 and NC at PIN 30. So I wired 12V to the two pins and >> then >> > flashrom erased/wrote the chip successfully. Please check the attached >> > output files for the two attempts. >> >> Hello Lu, >> >> Thanks for report! The successful log does not correspond 100% with the >> first one: the failure happens at the very beginning of the flash >> address space while the successful write does skip the first blocks and >> does only erase and write the last one. This can easily happen >> depending on the existing data and the image provided to flashrom. Just >> to make sure... can you please elaborate what happened between the two >> attempts that could explain what I wrote above? >> -- >> Kind regards/Mit freundlichen Grüßen, Stefan Tauner >> >

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Re: [flashrom] FAILED: wolf
by John Lewis 31 Dec '14

31 Dec '14

So, you are manually flashing a Dell Chromebook and you're wondering if this error is significant?On 30 Dec 2014 21:36, Nick Long <vieuphoria(a)gmail.com> wrote: > > Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0 > Verifiying flash... VERIFY FAILED at 0x00000062! Expected 0xff, Read=0x0b, failed byte count from 0x00000000-0x007fffff: 0x4 > Your flash chip is in an unknown state.

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