flashrom

flashrom@flashrom.org

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[commit] r645 - trunk
by svn＠flashrom.org 10 Jul '09

10 Jul '09

Author: hailfinger Date: 2009-07-10 23:08:55 +0200 (Fri, 10 Jul 2009) New Revision: 645 Modified: trunk/dummyflasher.c trunk/flash.h trunk/ft2232_spi.c trunk/ichspi.c trunk/it87spi.c trunk/sb600spi.c trunk/spi.c trunk/wbsio_spi.c Log: Add SPI multicommand infrastructure. Some SPI opcodes need to be sent in direct succession after each other without any chip deselect happening in between. A prominent example is WREN (Write Enable) directly before PP (Page Program). Intel calls the first opcode in such a row "preopcode". Right now, we ignore the direct succession requirement completely and it works pretty well because most onboard SPI masters have a timing or heuristics which make the problem disappear. The FT2232 SPI flasher is different. Since it is an external flasher, timing is very different to what we can expect from onboard flashers and this leads to failure at slow speeds. This patch allows any function to submit multiple SPI commands in a stream to any flasher. Support in the individual flashers isn't implemented yet, so there is one generic function which passes the each command in the stream one-by-one to the command functions of the selected SPI flash driver. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Jakob Bornecrantz <wallbraker(a)gmail.com> Tested-by: Jakob Bornecrantz <wallbraker(a)gmail.com> Modified: trunk/dummyflasher.c =================================================================== --- trunk/dummyflasher.c 2009-07-10 20:19:48 UTC (rev 644) +++ trunk/dummyflasher.c 2009-07-10 21:08:55 UTC (rev 645) @@ -141,7 +141,7 @@ return; } -int dummy_spi_command(unsigned int writecnt, unsigned int readcnt, +int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i; Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-07-10 20:19:48 UTC (rev 644) +++ trunk/flash.h 2009-07-10 21:08:55 UTC (rev 645) @@ -350,7 +350,7 @@ uint16_t dummy_chip_readw(const chipaddr addr); uint32_t dummy_chip_readl(const chipaddr addr); void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); -int dummy_spi_command(unsigned int writecnt, unsigned int readcnt, +int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); /* nic3com.c */ @@ -372,7 +372,7 @@ #define FTDI_FT4232H 0x6011 extern char *ft2232spi_param; int ft2232_spi_init(void); -int ft2232_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); +int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int ft2232_spi_write1(struct flashchip *flash, uint8_t *buf); int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf); @@ -414,14 +414,22 @@ SPI_CONTROLLER_FT2232, SPI_CONTROLLER_DUMMY, }; +struct spi_command { + unsigned int writecnt; + unsigned int readcnt; + const unsigned char *writearr; + unsigned char *readarr; +}; + extern enum spi_controller spi_controller; extern void *spibar; int probe_spi_rdid(struct flashchip *flash); int probe_spi_rdid4(struct flashchip *flash); int probe_spi_rems(struct flashchip *flash); int probe_spi_res(struct flashchip *flash); -int spi_command(unsigned int writecnt, unsigned int readcnt, +int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); +int spi_send_multicommand(struct spi_command *spicommands); int spi_write_enable(void); int spi_write_disable(void); int spi_chip_erase_60(struct flashchip *flash); @@ -465,7 +473,7 @@ /* ichspi.c */ int ich_init_opcodes(void); -int ich_spi_command(unsigned int writecnt, unsigned int readcnt, +int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int ich_spi_write_256(struct flashchip *flash, uint8_t * buf); @@ -476,14 +484,14 @@ void exit_conf_mode_ite(uint16_t port); int it87spi_init(void); int it87xx_probe_spi_flash(const char *name); -int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt, +int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); int it8716f_spi_chip_write_1(struct flashchip *flash, uint8_t *buf); int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf); /* sb600spi.c */ -int sb600_spi_command(unsigned int writecnt, unsigned int readcnt, +int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int sb600_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf); @@ -582,7 +590,7 @@ /* wbsio_spi.c */ int wbsio_check_for_spi(const char *name); -int wbsio_spi_command(unsigned int writecnt, unsigned int readcnt, +int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int wbsio_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int wbsio_spi_write_1(struct flashchip *flash, uint8_t *buf); Modified: trunk/ft2232_spi.c =================================================================== --- trunk/ft2232_spi.c 2009-07-10 20:19:48 UTC (rev 644) +++ trunk/ft2232_spi.c 2009-07-10 21:08:55 UTC (rev 645) @@ -193,7 +193,7 @@ return 0; } -int ft2232_spi_command(unsigned int writecnt, unsigned int readcnt, +int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { struct ftdi_context *ftdic = &ftdic_context; @@ -298,7 +298,7 @@ exit(1); } -int ft2232_spi_command(unsigned int writecnt, unsigned int readcnt, +int ft2232_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { fprintf(stderr, "FT2232 SPI support was not compiled in\n"); Modified: trunk/ichspi.c =================================================================== --- trunk/ichspi.c 2009-07-10 20:19:48 UTC (rev 644) +++ trunk/ichspi.c 2009-07-10 21:08:55 UTC (rev 645) @@ -682,7 +682,7 @@ return rc; } -int ich_spi_command(unsigned int writecnt, unsigned int readcnt, +int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int a; Modified: trunk/it87spi.c =================================================================== --- trunk/it87spi.c 2009-07-10 20:19:48 UTC (rev 644) +++ trunk/it87spi.c 2009-07-10 21:08:55 UTC (rev 645) @@ -141,7 +141,7 @@ * commands with the address in inverse wire order. That's why the register * ordering in case 4 and 5 may seem strange. */ -int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt, +int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { uint8_t busy, writeenc; Modified: trunk/sb600spi.c =================================================================== --- trunk/sb600spi.c 2009-07-10 20:19:48 UTC (rev 644) +++ trunk/sb600spi.c 2009-07-10 21:08:55 UTC (rev 645) @@ -52,7 +52,7 @@ unsigned char readarr[JEDEC_RDSR_INSIZE]; /* Read Status Register */ - spi_command(sizeof(cmd), sizeof(readarr), cmd, readarr); + spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr); return readarr[0]; } @@ -103,7 +103,7 @@ ; } -int sb600_spi_command(unsigned int writecnt, unsigned int readcnt, +int sb600_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int count; Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-07-10 20:19:48 UTC (rev 644) +++ trunk/spi.c 2009-07-10 21:08:55 UTC (rev 645) @@ -32,25 +32,25 @@ void spi_prettyprint_status_register(struct flashchip *flash); -int spi_command(unsigned int writecnt, unsigned int readcnt, +int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { switch (spi_controller) { case SPI_CONTROLLER_IT87XX: - return it8716f_spi_command(writecnt, readcnt, writearr, + return it8716f_spi_send_command(writecnt, readcnt, writearr, readarr); case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_ICH9: case SPI_CONTROLLER_VIA: - return ich_spi_command(writecnt, readcnt, writearr, readarr); + return ich_spi_send_command(writecnt, readcnt, writearr, readarr); case SPI_CONTROLLER_SB600: - return sb600_spi_command(writecnt, readcnt, writearr, readarr); + return sb600_spi_send_command(writecnt, readcnt, writearr, readarr); case SPI_CONTROLLER_WBSIO: - return wbsio_spi_command(writecnt, readcnt, writearr, readarr); + return wbsio_spi_send_command(writecnt, readcnt, writearr, readarr); case SPI_CONTROLLER_FT2232: - return ft2232_spi_command(writecnt, readcnt, writearr, readarr); + return ft2232_spi_send_command(writecnt, readcnt, writearr, readarr); case SPI_CONTROLLER_DUMMY: - return dummy_spi_command(writecnt, readcnt, writearr, readarr); + return dummy_spi_send_command(writecnt, readcnt, writearr, readarr); default: printf_debug ("%s called, but no SPI chipset/strapping detected\n", @@ -59,13 +59,23 @@ return 1; } +int spi_send_multicommand(struct spi_command *spicommands) +{ + int res = 0; + while ((spicommands->writecnt || spicommands->readcnt) && !res) { + res = spi_send_command(spicommands->writecnt, spicommands->readcnt, + spicommands->writearr, spicommands->readarr); + } + return res; +} + static int spi_rdid(unsigned char *readarr, int bytes) { const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID }; int ret; int i; - ret = spi_command(sizeof(cmd), bytes, cmd, readarr); + ret = spi_send_command(sizeof(cmd), bytes, cmd, readarr); if (ret) return ret; printf_debug("RDID returned"); @@ -81,14 +91,14 @@ uint32_t readaddr; int ret; - ret = spi_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); + ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); if (ret == SPI_INVALID_ADDRESS) { /* Find the lowest even address allowed for reads. */ readaddr = (spi_get_valid_read_addr() + 1) & ~1; cmd[1] = (readaddr >> 16) & 0xff, cmd[2] = (readaddr >> 8) & 0xff, cmd[3] = (readaddr >> 0) & 0xff, - ret = spi_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); + ret = spi_send_command(sizeof(cmd), JEDEC_REMS_INSIZE, cmd, readarr); } if (ret) return ret; @@ -102,14 +112,14 @@ uint32_t readaddr; int ret; - ret = spi_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); + ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); if (ret == SPI_INVALID_ADDRESS) { /* Find the lowest even address allowed for reads. */ readaddr = (spi_get_valid_read_addr() + 1) & ~1; cmd[1] = (readaddr >> 16) & 0xff, cmd[2] = (readaddr >> 8) & 0xff, cmd[3] = (readaddr >> 0) & 0xff, - ret = spi_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); + ret = spi_send_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr); } if (ret) return ret; @@ -123,7 +133,7 @@ int result; /* Send WREN (Write Enable) */ - result = spi_command(sizeof(cmd), 0, cmd, NULL); + result = spi_send_command(sizeof(cmd), 0, cmd, NULL); if (result) printf_debug("%s failed", __func__); @@ -150,7 +160,7 @@ const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI }; /* Send WRDI (Write Disable) */ - return spi_command(sizeof(cmd), 0, cmd, NULL); + return spi_send_command(sizeof(cmd), 0, cmd, NULL); } static int probe_spi_rdid_generic(struct flashchip *flash, int bytes) @@ -292,7 +302,7 @@ /* SB600 uses a different way to read status register. */ return sb600_read_status_register(); } else { - ret = spi_command(sizeof(cmd), sizeof(readarr), cmd, readarr); + ret = spi_send_command(sizeof(cmd), sizeof(readarr), cmd, readarr); if (ret) printf_debug("RDSR failed!\n"); } @@ -419,7 +429,7 @@ if (result) return result; /* Send CE (Chip Erase) */ - result = spi_command(sizeof(cmd), 0, cmd, NULL); + result = spi_send_command(sizeof(cmd), 0, cmd, NULL); if (result) { printf_debug("spi_chip_erase_60 failed sending erase\n"); return result; @@ -451,7 +461,7 @@ if (result) return result; /* Send CE (Chip Erase) */ - result = spi_command(sizeof(cmd), 0, cmd, NULL); + result = spi_send_command(sizeof(cmd), 0, cmd, NULL); if (result) { printf_debug("spi_chip_erase_60 failed sending erase\n"); return result; @@ -492,7 +502,7 @@ if (result) return result; /* Send BE (Block Erase) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + spi_send_command(sizeof(cmd), 0, cmd, NULL); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ @@ -522,7 +532,7 @@ if (result) return result; /* Send BE (Block Erase) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + spi_send_command(sizeof(cmd), 0, cmd, NULL); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 100-4000 ms, so wait in 100 ms steps. */ @@ -572,7 +582,7 @@ if (result) return result; /* Send SE (Sector Erase) */ - spi_command(sizeof(cmd), 0, cmd, NULL); + spi_send_command(sizeof(cmd), 0, cmd, NULL); /* Wait until the Write-In-Progress bit is cleared. * This usually takes 15-800 ms, so wait in 10 ms steps. */ @@ -609,7 +619,7 @@ int result; /* Send EWSR (Enable Write Status Register). */ - result = spi_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL); + result = spi_send_command(sizeof(cmd), JEDEC_EWSR_INSIZE, cmd, NULL); if (result) printf_debug("%s failed", __func__); @@ -641,7 +651,7 @@ { JEDEC_WRSR, (unsigned char)status }; /* Send WRSR (Write Status Register) */ - return spi_command(sizeof(cmd), 0, cmd, NULL); + return spi_send_command(sizeof(cmd), 0, cmd, NULL); } void spi_byte_program(int address, uint8_t byte) @@ -655,7 +665,7 @@ }; /* Send Byte-Program */ - spi_command(sizeof(cmd), 0, cmd, NULL); + spi_send_command(sizeof(cmd), 0, cmd, NULL); } int spi_nbyte_program(int address, uint8_t *bytes, int len) @@ -676,7 +686,7 @@ memcpy(&cmd[4], bytes, len); /* Send Byte-Program */ - return spi_command(4 + len, 0, cmd, NULL); + return spi_send_command(4 + len, 0, cmd, NULL); } int spi_disable_blockprotect(void) @@ -712,7 +722,7 @@ }; /* Send Read */ - return spi_command(sizeof(cmd), len, cmd, bytes); + return spi_send_command(sizeof(cmd), len, cmd, bytes); } /* @@ -855,13 +865,13 @@ result = spi_write_enable(); if (result) return result; - spi_command(6, 0, w, NULL); + spi_send_command(6, 0, w, NULL); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) programmer_delay(5); /* SST25VF040B Tbp is max 10us */ while (pos < size) { w[1] = buf[pos++]; w[2] = buf[pos++]; - spi_command(3, 0, w, NULL); + spi_send_command(3, 0, w, NULL); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) programmer_delay(5); /* SST25VF040B Tbp is max 10us */ } Modified: trunk/wbsio_spi.c =================================================================== --- trunk/wbsio_spi.c 2009-07-10 20:19:48 UTC (rev 644) +++ trunk/wbsio_spi.c 2009-07-10 21:08:55 UTC (rev 645) @@ -90,7 +90,7 @@ * Would one more byte of RAM in the chip (to get all 24 bits) really make * such a big difference? */ -int wbsio_spi_command(unsigned int writecnt, unsigned int readcnt, +int wbsio_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { int i;

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[commit] r644 - trunk
by svn＠flashrom.org 10 Jul '09

10 Jul '09

Author: hailfinger Date: 2009-07-10 22:19:48 +0200 (Fri, 10 Jul 2009) New Revision: 644 Modified: trunk/Makefile Log: Change tarball compression from gzip to bzip2. Set the user and group of all files to root for tar versions which support it. Add explanatory comments for supporting that feature with other tar versions. Use LC_ALL instead of LANG everywhere. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/Makefile =================================================================== --- trunk/Makefile 2009-07-08 14:50:36 UTC (rev 643) +++ trunk/Makefile 2009-07-10 20:19:48 UTC (rev 644) @@ -58,7 +58,7 @@ # of the checked out flashrom files. # Note to packagers: Any tree exported with "make export" or "make tarball" # will not require subversion. The downloadable snapshots are already exported. -SVNVERSION := $(shell LANG=C svnversion -cn . | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/" | grep "[0-9]" || echo unknown) +SVNVERSION := $(shell LC_ALL=C svnversion -cn . | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/" | grep "[0-9]" || echo unknown) VERSION := 0.9.0-r$(SVNVERSION) @@ -67,10 +67,15 @@ $(PROGRAM): $(OBJS) $(CC) $(LDFLAGS) -o $(PROGRAM) $(OBJS) $(LIBS) $(FEATURE_LIBS) -FEATURE_CFLAGS = $(shell LANG=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-D'FT2232_SPI_SUPPORT=1'") +FEATURE_CFLAGS = $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-D'FT2232_SPI_SUPPORT=1'") -FEATURE_LIBS = $(shell LANG=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-lftdi") +FEATURE_LIBS = $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-lftdi") +# TAROPTIONS reduces information leakage from the packager's system. +# If other tar programs support command line arguments for setting uid/gid of +# stored files, they can be handled here as well. +TAROPTIONS = $(shell LC_ALL=C tar --version|grep -q GNU && echo "--owner=root --group=root") + %.o: %.c .features $(CC) $(CFLAGS) $(CPPFLAGS) $(FEATURE_CFLAGS) $(SVNDEF) -o $@ -c $< @@ -137,9 +142,9 @@ @echo Exported $(EXPORTDIR)/flashrom-$(VERSION)/ tarball: export - @tar cfz $(EXPORTDIR)/flashrom-$(VERSION).tar.gz -C $(EXPORTDIR)/ flashrom-$(VERSION)/ + @tar cjf $(EXPORTDIR)/flashrom-$(VERSION).tar.bz2 -C $(EXPORTDIR)/ $(TAROPTIONS) flashrom-$(VERSION)/ @rm -rf $(EXPORTDIR)/flashrom-$(VERSION) - @echo Created $(EXPORTDIR)/flashrom-$(VERSION).tar.gz + @echo Created $(EXPORTDIR)/flashrom-$(VERSION).tar.bz2 .PHONY: all clean distclean dep compiler pciutils features export tarball

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Re: [flashrom] [Patch] superiotool: Add IT8703F support.
by Glenn Mueller 09 Jul '09

09 Jul '09

here it is. > Date: Thu, 9 Jul 2009 18:36:59 +0200 > To: coreboot(a)coreboot.org > CC: mechwarrior5(a)hotmail.com > Subject: [Patch] superiotool: Add IT8703F support. > From: libv(a)skynet.be > > Glenn, can you run this on your Asus A7V8X and attach the output? > > Thanks, > > Luc Verhaegen. _________________________________________________________________ Lauren found her dream laptop. Find the PC that’s right for you. http://www.microsoft.com/windows/choosepc/?ocid=ftp_val_wl_290

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[Patch] Flag bad read/write on W39V040B.
by Luc Verhaegen 08 Jul '09

08 Jul '09

I found an extra chip on a k8m890 board i got off of ebay which was completely fubar. If there's a taker in euroland who wants to spend time on this, just give me a holler. Luc Verhaegen.

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[commit] r643 - trunk
by svn＠flashrom.org 08 Jul '09

08 Jul '09

Author: libv Date: 2009-07-08 16:50:36 +0200 (Wed, 08 Jul 2009) New Revision: 643 Modified: trunk/flashchips.c Log: W39V040B: Flag Erase/Write as bad. Chip has now been properly tested in both my Jetway J7F5M and my EPIA-SP (known good board). Erase and write fail. Mark these operations as bad until i or someone else have time to fix this. Reported by Arvid Brodin <arvidb(a)kth.se>. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> M flashchips.c Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-07-06 22:58:46 UTC (rev 642) +++ trunk/flashchips.c 2009-07-08 14:50:36 UTC (rev 643) @@ -2881,7 +2881,7 @@ .model_id = W_39V040B, .total_size = 512, .page_size = 64*1024, - .tested = TEST_OK_PREW, + .tested = TEST_OK_PR | TEST_BAD_ERASE | TEST_BAD_WRITE, .probe = probe_jedec, .probe_timing = 10, .erase = erase_chip_jedec,

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Flashrom does not work with J7F5M
by Arvid Brodin 07 Jul '09

07 Jul '09

Hi. I tested flashrom on my Jetway J7F5M motherboard. # flashrom Calibrating delay loop... OK. No coreboot table found. Found chipset "VIA CX700", enabling flash write... OK. Found chip "Winbond W39V040B" (512 KB) at physical address 0xfff80000. No operations were specified. So probing seems to work ok, as do reading. Writing, however, does not work - the image on the flash chip remains unchanged (had a sweaty moment after the FAILED message before I had read the chip again and diffed it against the backed-up original image!). The "Protect flash part" option in BIOS is set to Disabled (I also tried Enabled, just to be sure). Is there any hope on getting flashrom support for this card? The AWDFLASH.EXE utility recommended for flashing by Jetway is "only" some sixty thousand bytes - any hints on reverse engineering this? The computer is head-, FD- and CDR-less and runs linux, so it's a chore to flash it with the d**n DOS utility... -- Arvid

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https://www.ohloh.net/p/flashrom
by Luc Verhaegen 07 Jul '09

07 Jul '09

Go claim your contributions :) Luc Verhaegen.

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Re: [flashrom] Abit IP35 needs board enable.
by Luc Verhaegen 06 Jul '09

06 Jul '09

On Mon, Jul 06, 2009 at 08:18:32PM +0100, Richie Ward wrote: > Oh and I hope i used right program :) Is this ok? > > > Found Winbond W83627DHG (id=0xa0, rev=0x23) at 0x2e > > Register dump: > > idx 02 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f > > val ff a0 23 ff 00 4c 00 00 ff 50 00 7c c0 0a 01 00 ff > > def 00 a0 NA ff 00 MM 00 MM RR 50 00 00 RR e2 21 00 00 > > LDN 0x00 (Floppy) > > idx 30 60 61 70 74 f0 f1 f2 f4 f5 > > val 00 00 00 00 04 0e 00 ff 00 00 > > def 01 03 f0 06 02 8e 00 ff 00 00 > > LDN 0x01 (Parallel port) > > idx 30 60 61 70 74 f0 > > val 00 00 00 00 04 38 > > def 01 03 78 07 04 3f > > LDN 0x02 (COM1) > > idx 30 60 61 70 f0 > > val 00 00 00 00 00 > > def 01 03 f8 04 00 > > LDN 0x03 (COM2) > > idx 30 60 61 70 f0 f1 > > val 00 00 00 00 00 00 > > def 01 02 f8 03 00 00 > > LDN 0x05 (Keyboard) > > idx 30 60 61 62 63 70 72 f0 > > val 01 00 60 00 64 01 0c 80 > > def 01 00 60 00 64 01 0c 83 > > LDN 0x06 (Serial peripheral interface) > > idx 30 62 63 > > val 00 ff ff > > def 00 00 00 > > LDN 0x07 (GPIO 6) > > idx 30 f4 f5 f6 f7 > > val 07 ff ff ff ff > > def 00 ff 00 00 00 > > LDN 0x08 (WDTO#, PLED) > > idx 30 f5 f6 f7 > > val 00 ff 00 ff > > def 00 00 00 00 > > LDN 0x09 (GPIO 2, GPIO 3, GPIO 4, GPIO 5) > > idx 30 e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 f0 f1 f2 f3 f4 f5 f6 f7 fe > > val 0e ff 01 00 ff ff ff ff e3 ff 01 ff e3 00 00 c0 ff 20 00 00 > > def 00 ff 00 00 ff 00 00 00 00 00 00 ff 00 00 00 ff 00 00 00 00 > > LDN 0x0a (ACPI) > > idx 30 70 e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 f2 f3 f4 f6 f7 fe > > val 00 00 00 00 f0 04 00 00 1c 10 09 00 7d 00 00 00 08 00 > > def 00 00 01 00 ff 08 00 RR 1c 00 RR RR 7c 00 00 00 00 00 > > LDN 0x0b (Hardware monitor) > > idx 30 60 61 70 f0 f1 f2 > > val 01 02 90 02 81 ff 81 > > def 00 00 00 00 81 00 00 > > LDN 0x0c (PECI, SST) > > idx e0 e1 e2 e3 e4 e5 e8 f1 fe ff > > val 10 52 48 48 48 00 01 48 00 00 > > def 00 48 48 48 48 00 00 48 00 00 Yeah, looking through this now. Luc Verhaegen.

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[commit] r642 - trunk
by svn＠flashrom.org 06 Jul '09

06 Jul '09

Author: libv Date: 2009-07-07 00:58:46 +0200 (Tue, 07 Jul 2009) New Revision: 642 Modified: trunk/board_enable.c Log: Board enable for Abit IP35. Raise GPIO 16 on ICH9R LPC Interface. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Richie Ward <RichieS(a)GMail.com> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-07-04 15:10:41 UTC (rev 641) +++ trunk/board_enable.c 2009-07-06 22:58:46 UTC (rev 642) @@ -806,6 +806,32 @@ } /** + * Suited for Abit IP35: Intel P35 + ICH9R. + */ +static int board_abit_ip35(const char *name) +{ + struct pci_dev *dev; + uint16_t base; + uint8_t tmp; + + dev = pci_dev_find(0x8086, 0x2916); /* Intel ICH9R LPC Interface */ + if (!dev) { + fprintf(stderr, "\nERROR: Intel ICH9R LPC not found.\n"); + return -1; + } + + /* get LPC GPIO base */ + base = pci_read_long(dev, 0x48) & 0x0000FFC0; + + /* Raise GPIO 16 */ + tmp = INB(base + 0x0E); + tmp |= 0x01; + OUTB(tmp, base + 0x0E); + + return 0; +} + +/** * We use 2 sets of IDs here, you're free to choose which is which. This * is to provide a very high degree of certainty when matching a board on * the basis of subsystem/card IDs. As not every vendor handles @@ -828,6 +854,7 @@ /* Please keep this list alphabetically ordered by vendor/board name. */ struct board_pciid_enable board_pciid_enables[] = { /* first pci-id set [4], second pci-id set [4], coreboot id [2], vendor name board name flash enable */ + {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, "Abit", "IP35", board_abit_ip35}, {0x8086, 0x1130, 0, 0, 0x105a, 0x0d30, 0x105a, 0x4d33, "acorp", "6a815epd", "Acorp", "6A815EPD", board_acorp_6a815epd}, {0x1022, 0x746B, 0x1022, 0x36C0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A*", board_epox_ep_8k5a2},

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Abit IP35 needs board enable.
by Luc Verhaegen 06 Jul '09

06 Jul '09

Thanks to uwe for having the foresight of asking RichW on irc what his email was. lspci -vnn attached. Suggested matches: 2 port sata controller: 0x8086, 0x2926, 0x147b, 0x1084 marvell gigabit ethernet: 0x11ab, 0x4364, 0x147b, 0x1084 Board enable requires: a gpio line on the superio to be altered. logical device: 0x06 0xF0, 0xF1, 0xF2 then all get &= ~0x02 Richard, please provide the output of: superio -Vd so we can identify your superio completely and correctly. Luc Verhaegen.

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