flashrom

flashrom@flashrom.org

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9188 discussions

Patchwork update script
by Carl-Daniel Hailfinger 21 Sep '09

21 Sep '09

Hi, here's the script I'm using to set the status of flashrom patches in patchwork to "Accepted". The web interface only allows you to set the status, but it does not allow you to set a commit ID. With pwclient (part of patchwork) you can do that. My script simply retrieves a patch (-p0) for a given numeric commit ID (without leading r), hashes it with the special patchwork hash (which is somewhat tolerant of context and order changes), then uses pwclient to set the patch status for that hash to "Accepted" and the commit ID to "r$1". If the patch (-p0) can't be found, it retrieves a patch (-p1) for the commit ID. Usage: update-patchwork 1234 You might want to adjust a few paths for coreboot usage and for your local installation. Requirements for this script: - A local patchwork source (or installation) - ~/.pwclientrc (downloaded from the patchwork web interface) Where can you get .pwclientrc? Go to http://patchwork.coreboot.org/project/ and log in. Then click on your preferred project, then click on "project info". There you find: "Sample patchwork client configuration for this project: .pwclientrc." Download .pwclientrc and fill in your patchwork password, then store it in your $HOME. I hope this helps others reduce patchwork maintenance efforts. Regards, Carl-Daniel #!/bin/bash # Install this script as update-patchwork in your $PATH # and call it with the revision number as parameter. test -z "$1" && { echo "No revision provided."; exit 1; } revision="$1" hashcand=$(svn diff -c $revision svn://coreboot.org/flashrom/trunk/|python /sources/tmptrees/patchwork/apps/patchwork/parser.py --hash) /sources/tmptrees/patchwork/apps/patchwork/bin/pwclient update -s Accepted -c r$revision -h $hashcand && { echo "done"; exit 0; } echo hashcand=$(svn diff -c $revision svn://coreboot.org/flashrom/|python /sources/tmptrees/patchwork/apps/patchwork/parser.py --hash) /sources/tmptrees/patchwork/apps/patchwork/bin/pwclient update -s Accepted -c r$revision -h $hashcand && { echo "done"; exit 0; } echo "No matching patch in patchwork found." exit 1 -- http://www.hailfinger.org/

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[PATCH] Fix flashrom memory leaks
by Carl-Daniel Hailfinger 19 Sep '09

19 Sep '09

The pattern of foo = realloc(foo, size); causes a memory leak if realloc fails because realloc does not free foo in case of failure, but foo will be NULL after a failure, so there is no way to access or free the original foo. Fix unchecked [mc]alloc return values as well. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-memleak/flash.h =================================================================== --- flashrom-memleak/flash.h (Revision 725) +++ flashrom-memleak/flash.h (Arbeitskopie) @@ -323,7 +323,7 @@ void print_supported_chipsets(void); void print_supported_boards(void); void print_supported_pcidevs(struct pcidev_status *devs); -void print_wiki_tables(void); +int print_wiki_tables(void); /* board_enable.c */ void w836xx_ext_enter(uint16_t port); Index: flashrom-memleak/ft2232_spi.c =================================================================== --- flashrom-memleak/ft2232_spi.c (Revision 725) +++ flashrom-memleak/ft2232_spi.c (Arbeitskopie) @@ -193,14 +193,17 @@ { struct ftdi_context *ftdic = &ftdic_context; static unsigned char *buf = NULL; + unsigned char *newbuf = NULL; int i, ret = 0; if (writecnt > 65536 || readcnt > 65536) return SPI_INVALID_LENGTH; - buf = realloc(buf, writecnt + readcnt + 100); - if (!buf) { + newbuf = realloc(buf, writecnt + readcnt + 100); + if (!newbuf) { fprintf(stderr, "Out of memory!\n"); + free(buf); + buf = NULL; exit(1); } Index: flashrom-memleak/flashrom.c =================================================================== --- flashrom-memleak/flashrom.c (Revision 725) +++ flashrom-memleak/flashrom.c (Arbeitskopie) @@ -282,9 +282,12 @@ char *strcat_realloc(char *dest, const char *src) { - dest = realloc(dest, strlen(dest) + strlen(src) + 1); - if (!dest) + char *newdest = realloc(dest, strlen(dest) + strlen(src) + 1); + if (!newdest) { + free(dest); + fprintf(stderr, "Could not allocate memory!\n"); return NULL; + } strcat(dest, src); return dest; } @@ -459,6 +462,10 @@ printf("Error: No filename specified.\n"); return 1; } + if (!buf) { + fprintf(stderr, "Could not allocate memory!\n"); + exit(1); + } if ((image = fopen(filename, "w")) == NULL) { perror(filename); exit(1); @@ -829,7 +836,8 @@ #if CONFIG_PRINT_WIKI == 1 if (list_supported_wiki) { - print_wiki_tables(); + if (print_wiki_tables()) + exit(1); exit(0); } #endif @@ -944,6 +952,10 @@ size = flash->total_size * 1024; buf = (uint8_t *) calloc(size, sizeof(char)); + if (!buf) { + fprintf(stderr, "Could not allocate memory!\n"); + exit(1); + } if (erase_it) { if (flash->tested & TEST_BAD_ERASE) { Index: flashrom-memleak/print_wiki.c =================================================================== --- flashrom-memleak/print_wiki.c (Revision 725) +++ flashrom-memleak/print_wiki.c (Arbeitskopie) @@ -353,7 +353,7 @@ printf("\n|}\n\n|}\n"); } -static void wiki_helper(const char *heading, const char *status, +static int wiki_helper(const char *heading, const char *status, int cols, const struct board_info boards[]) { int i, j, k, c, boardcount = 0, color = 1, num_notes = 0; @@ -362,6 +362,10 @@ char *notes = calloc(1, 1); char tmp[900 + 1]; + if (!notes) { + fprintf(stderr, "Could not allocate memory!\n"); + return 1; + } for (b = boards; b->vendor != NULL; b++) boardcount++; @@ -388,6 +392,10 @@ snprintf((char *)&tmp, 900, "%d %s \n", 1 + num_notes++, boards_notes[c].note); notes = strcat_realloc(notes, (char *)&tmp); + if (!notes) { + return 1; + } + } else { printf("\n"); } @@ -404,6 +412,8 @@ if (num_notes > 0) printf("\n\n%s\n", notes); free(notes); + + return 0; } static void wiki_helper2(const char *heading, int cols) @@ -447,16 +457,21 @@ printf("\n|}\n\n|}\n"); } -void print_supported_boards_wiki(void) +int print_supported_boards_wiki(void) { printf("%s", board_intro); - wiki_helper("Known good (worked out of the box)", "OK", 3, boards_ok); + if (wiki_helper("Known good (worked out of the box)", "OK", 3, boards_ok)) + return 1; wiki_helper2("Known good (with write-enable code in flashrom)", 3); - wiki_helper("Not supported (yet)", "No", 3, boards_bad); + if (wiki_helper("Not supported (yet)", "No", 3, boards_bad)) + return 1; printf("%s", laptop_intro); - wiki_helper("Known good (worked out of the box)", "OK", 1, laptops_ok); - wiki_helper("Not supported (yet)", "No", 1, laptops_bad); + if (wiki_helper("Known good (worked out of the box)", "OK", 1, laptops_ok)) + return 1; + if (wiki_helper("Not supported (yet)", "No", 1, laptops_bad)) + return 1; + return 0; } void print_supported_chips_wiki(void) @@ -524,14 +539,15 @@ } } -void print_wiki_tables(void) +int print_wiki_tables(void) { time_t t = time(NULL); printf(wiki_header, ctime(&t), flashrom_version); print_supported_chips_wiki(); print_supported_chipsets_wiki(); - print_supported_boards_wiki(); + if (print_supported_boards_wiki()) + return 1; printf("%s", programmer_section); #if NIC3COM_SUPPORT == 1 print_supported_pcidevs_wiki(nics_3com); @@ -543,5 +559,6 @@ print_supported_pcidevs_wiki(satas_sii); #endif printf("\n|}\n"); + return 0; } Index: flashrom-memleak/print.c =================================================================== --- flashrom-memleak/print.c (Revision 725) +++ flashrom-memleak/print.c (Arbeitskopie) @@ -31,25 +31,48 @@ char *flashbuses_to_text(enum chipbustype bustype) { char *ret = calloc(1, 1); + if (!ret) { + fprintf(stderr, "Could not allocate memory!\n"); + return NULL; + } if (bustype == CHIP_BUSTYPE_UNKNOWN) { ret = strcat_realloc(ret, "Unknown,"); + if (!ret) + return NULL; /* * FIXME: Once all chipsets and flash chips have been updated, NONSPI * will cease to exist and should be eliminated here as well. */ } else if (bustype == CHIP_BUSTYPE_NONSPI) { ret = strcat_realloc(ret, "Non-SPI,"); + if (!ret) + return NULL; } else { - if (bustype & CHIP_BUSTYPE_PARALLEL) + if (bustype & CHIP_BUSTYPE_PARALLEL) { ret = strcat_realloc(ret, "Parallel,"); - if (bustype & CHIP_BUSTYPE_LPC) + if (!ret) + return NULL; + } + if (bustype & CHIP_BUSTYPE_LPC) { ret = strcat_realloc(ret, "LPC,"); - if (bustype & CHIP_BUSTYPE_FWH) + if (!ret) + return NULL; + } + if (bustype & CHIP_BUSTYPE_FWH) { ret = strcat_realloc(ret, "FWH,"); - if (bustype & CHIP_BUSTYPE_SPI) + if (!ret) + return NULL; + } + if (bustype & CHIP_BUSTYPE_SPI) { ret = strcat_realloc(ret, "SPI,"); - if (bustype == CHIP_BUSTYPE_NONE) + if (!ret) + return NULL; + } + if (bustype == CHIP_BUSTYPE_NONE) { ret = strcat_realloc(ret, "None,"); + if (!ret) + return NULL; + } } /* Kill last comma. */ ret[strlen(ret) - 1] = '\0'; -- http://www.hailfinger.org/

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Re: [flashrom] Trial of ARIMA:HDAMA Motherboard
by Carl-Daniel Hailfinger 18 Sep '09

18 Sep '09

Hi Mike, On 18.09.2009 18:55, Spangler, Mike T wrote: > I've corrected my email and am now sending to the group. > Thanks. >> Of course I'd prefer it if you tried to flash coreboot (new name of >> LinuxBIOS) to these boards, but that's your choice. Anyway, you said you >> have the factory BIOS around somewhere. Is it the one at >> http://flextronics.com/arima/Server/Download/Download/HDAMA189.zip ? >> > > I can't use flash coreboot (LinuxBIOS) because our cluster management tools require pxeboot. We've transitioned away from it. > That's unfortunate. Did you know that coreboot+SeaBIOS works fine with gPXE? We coreboot/flashrom developers are always interested in helping people update coreboot to the latest and greatest. So if you need PXE booting, there's no need to move back to the factory BIOS, a simple coreboot update should suffice. > So, the bios zip file above is correct, but I'm not using it. It will not work for flashing a chip with LinuxBios. The way I do this is to do a "flashrom -r" on a system with factory bios and then take that newly created flashrom file and do a "flashrom -w" with it on a board with LinuxBios. That's one option. The other option would be to extract the BIOS from the .ROM file. That looks reasonably easy. No guarantees, though. dd if=something.ROM of=bios.bin bs=1k count=512 > This is the method we used with the old bios_copy software from Linux Networx, but that was extremely unreliable. > flashrom strives to be the most reliable flashing tool out there. The current version has builtin verification for every step it does. >> Hmm ok. I think we have enough docs to iterate through all possible >> board enables. How many of these boards do you have (in case we trash >> the ROM of one of them)? >> > > The ROM is removeable, so we only potentially trash a PLCC chip. I have a half dozen or so spares. > Great. And with hotplugging/hotflashing it should be possible to reflash a trashed chip in another board. Can you supply the output of "lspci -nnvvvxxx" as root? That will allow me to dig further. I'd like to limit the search to a reasonable subset of options. Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] Trial of ARIMA:HDAMA Motherboard
by ron minnich 18 Sep '09

18 Sep '09

Note that you could still use coreboot + seabios + gpxe, which works very well here at sandia. That said, an "arima HDAMA" is a changing thing. I suppose they might have added a write enable GPIO at some point. You could use the note I sent to this list recently about how to probe the GPIOs for a write enable. ron

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[RFC] Output and progress bars
by Carl-Daniel Hailfinger 18 Sep '09

18 Sep '09

To librarize flashrom, we have to move away from printf to generic printing functions. I'd like to classify messages into four severity levels: * Error (out of memory, write failed, ...) * Warning (chipset init incomplete, ...) * Notice (chip detected, flashing successful) * Debug I also would like to differentiate between controller related and flashchip related messages. E.g. one might be interested in verbose probing output, but not in full SB600 SPI debugging for every command sent. Since all messages above debug level are shown anyway, this differentiation makes most sense if only applied to debug messages. Suggested set of message functions (all with printk syntax): msg_err msg_warn msg_notice msg_debug_controller msg_debug_flash Progress printing is done with dots, equals, numbers, sometimes with, sometimes without backspace for beautification. Some focus on percentage, others focus on addresses. With a maxval parameter, we can handle policy on a case-by-case basis. Suggested progress bar function: progressbar(int curval, int maxval) Comments appreciated. Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] Trial of ARIMA:HDAMA Motherboard
by Carl-Daniel Hailfinger 18 Sep '09

18 Sep '09

[bouncing to list] On 18.09.2009 13:47, Carl-Daniel Hailfinger wrote: > Hi Mike, > > was it intentional that you only sent the data to me? It would be great > to have that data on the list. If possible, please forward your mail to > the list so other developers can help as well. > > On 18.09.2009 07:26, Spangler, Mike T wrote: > >> Thanks for getting back to me. David Hendricks has been giving me some >> direction also, but has kind of exhausted his ideas. He suggested that >> I try something around revision 2000, because he thought that he was >> able to flash an ARIMA board successfully with that version. I also >> tried revision 2341 which had references in the Changelog to ARIMA. >> Turns out the results were identical. The results of rev 2000/2341 is >> that it flashes about 99% of the locations on the PLCC correctly. >> Below I will give you some output from the flashrom -w command. Also, >> I've included a comparison between the file I used to write to the >> flash chip and a new file that I reread from the flashed chip. >> > > I analyzed the output and the only difference is that the new flashrom > version detects the problem and the old version ignores it... > > >> First I will give you what you wanted to know. The chip was originally >> factory bios. It was either flashed to LinuxBios with lbflash or with >> a standalone benchtop flasher. I'm trying to flash the chip back to >> factory bios. >> > > Of course I'd prefer it if you tried to flash coreboot (new name of > LinuxBIOS) to these boards, but that's your choice. Anyway, you said you > have the factory BIOS around somewhere. Is it the one at > http://flextronics.com/arima/Server/Download/Download/HDAMA189.zip ? > > >> Output from superiotool -dV >> >> Node20:~/coreboot-v2-4645/util/superiotool # ./superiotool -dV >> superiotool r >> Found NSC PC87360 (sid=0xe1, srid=0x0f) at 0x2e >> Register dump: >> LDN 0x07 (GPIO) >> idx 30 60 61 70 71 74 75 f0 f1 f2 >> val 00 00 00 00 03 04 04 00 44 01 >> def 00 00 00 00 03 04 04 00 00 00 >> > > Hmm ok. I think we have enough docs to iterate through all possible > board enables. How many of these boards do you have (in case we trash > the ROM of one of them)? > > Regards, > Carl-Daniel > > -- http://www.hailfinger.org/

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Re: [flashrom] Trial of ARIMA:HDAMA Motherboard
by Spangler, Mike T 18 Sep '09

18 Sep '09

Carl - I've corrected my email and am now sending to the group. > Of course I'd prefer it if you tried to flash coreboot (new name of > LinuxBIOS) to these boards, but that's your choice. Anyway, you said you > have the factory BIOS around somewhere. Is it the one at > http://flextronics.com/arima/Server/Download/Download/HDAMA189.zip ? I can't use flash coreboot (LinuxBIOS) because our cluster management tools require pxeboot. We've transitioned away from it. So, the bios zip file above is correct, but I'm not using it. It will not work for flashing a chip with LinuxBios. The way I do this is to do a "flashrom -r" on a system with factory bios and then take that newly created flashrom file and do a "flashrom -w" with it on a board with LinuxBios. This is the method we used with the old bios_copy software from Linux Networx, but that was extremely unreliable. > Hmm ok. I think we have enough docs to iterate through all possible > board enables. How many of these boards do you have (in case we trash > the ROM of one of them)? The ROM is removeable, so we only potentially trash a PLCC chip. I have a half dozen or so spares. Mike -----Original Message----- From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006@gmx.net] Sent: Friday, September 18, 2009 4:47 AM To: Spangler, Mike T Subject: Re: [flashrom] Trial of ARIMA:HDAMA Motherboard Hi Mike, was it intentional that you only sent the data to me? It would be great to have that data on the list. If possible, please forward your mail to the list so other developers can help as well. On 18.09.2009 07:26, Spangler, Mike T wrote: > Thanks for getting back to me. David Hendricks has been giving me some > direction also, but has kind of exhausted his ideas. He suggested that > I try something around revision 2000, because he thought that he was > able to flash an ARIMA board successfully with that version. I also > tried revision 2341 which had references in the Changelog to ARIMA. > Turns out the results were identical. The results of rev 2000/2341 is > that it flashes about 99% of the locations on the PLCC correctly. > Below I will give you some output from the flashrom -w command. Also, > I've included a comparison between the file I used to write to the > flash chip and a new file that I reread from the flashed chip. I analyzed the output and the only difference is that the new flashrom version detects the problem and the old version ignores it... > First I will give you what you wanted to know. The chip was originally > factory bios. It was either flashed to LinuxBios with lbflash or with > a standalone benchtop flasher. I'm trying to flash the chip back to > factory bios. Of course I'd prefer it if you tried to flash coreboot (new name of LinuxBIOS) to these boards, but that's your choice. Anyway, you said you have the factory BIOS around somewhere. Is it the one at http://flextronics.com/arima/Server/Download/Download/HDAMA189.zip ? > Output from superiotool -dV > > Node20:~/coreboot-v2-4645/util/superiotool # ./superiotool -dV > superiotool r > Found NSC PC87360 (sid=0xe1, srid=0x0f) at 0x2e > Register dump: > LDN 0x07 (GPIO) > idx 30 60 61 70 71 74 75 f0 f1 f2 > val 00 00 00 00 03 04 04 00 44 01 > def 00 00 00 00 03 04 04 00 00 00 Hmm ok. I think we have enough docs to iterate through all possible board enables. How many of these boards do you have (in case we trash the ROM of one of them)? Regards, Carl-Daniel

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Re: [flashrom] Trial of ARIMA:HDAMA Motherboard
by Spangler, Mike T 18 Sep '09

18 Sep '09

Carl-Daniel - Thanks for getting back to me. David Hendricks has been giving me some direction also, but has kind of exhausted his ideas. He suggested that I try something around revision 2000, because he thought that he was able to flash an ARIMA board successfully with that version. I also tried revision 2341 which had references in the Changelog to ARIMA. Turns out the results were identical. The results of rev 2000/2341 is that it flashes about 99% of the locations on the PLCC correctly. Below I will give you some output from the flashrom -w command. Also, I've included a comparison between the file I used to write to the flash chip and a new file that I reread from the flashed chip. First I will give you what you wanted to know. The chip was originally factory bios. It was either flashed to LinuxBios with lbflash or with a standalone benchtop flasher. I'm trying to flash the chip back to factory bios. Output from superiotool -dV Node20:~/coreboot-v2-4645/util/superiotool # ./superiotool -dV superiotool r Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x0003, id=0x11e1 Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0xe111, rev=0x0 Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xe111, rev=0x0 Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xe111, rev=0x0 Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xe111, rev=0x0 Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Found NSC PC87360 (sid=0xe1, srid=0x0f) at 0x2e Register dump: idx 20 21 22 23 24 25 26 27 28 2a 2b 2c 2d 2e val e1 11 00 03 00 00 00 0f 00 00 10 00 58 00 def e1 11 00 03 00 00 00 NA 00 MM 00 00 00 RR LDN 0x00 (Floppy) idx 30 60 61 70 71 74 75 f0 f1 val 00 03 f2 06 03 02 04 24 00 def 00 03 f2 06 03 02 04 24 00 LDN 0x01 (Parallel port) idx 30 60 61 70 71 74 75 f0 val 00 02 78 07 02 04 04 f2 def 00 02 78 07 02 04 04 f2 LDN 0x02 (COM2) idx 30 60 61 70 71 74 75 f0 val 00 02 f8 03 03 04 04 02 def 00 02 f8 03 03 04 04 02 LDN 0x03 (COM1) idx 30 60 61 70 71 74 75 f0 val 01 03 f8 04 03 04 04 02 def 00 03 f8 04 03 04 04 02 LDN 0x04 (System wake-up control (SWC)) idx 30 60 61 70 71 74 75 val 00 00 00 00 03 04 04 def 00 00 00 00 03 04 04 LDN 0x05 (Mouse) idx 30 70 71 74 75 val 00 0c 02 04 04 def 00 0c 02 04 04 LDN 0x06 (Keyboard) idx 30 60 61 62 63 70 71 74 75 f0 val 01 00 60 00 64 01 02 04 04 40 def 01 00 60 00 64 01 02 04 04 40 LDN 0x07 (GPIO) idx 30 60 61 70 71 74 75 f0 f1 f2 val 00 00 00 00 03 04 04 00 44 01 def 00 00 00 00 03 04 04 00 00 00 LDN 0x08 (ACCESS.bus (ACB)) idx 30 60 61 70 71 74 75 f0 val 00 00 00 00 03 04 04 00 def 00 00 00 00 03 04 04 00 LDN 0x09 (Fan speed control and monitor (FSCM)) idx 30 60 61 70 71 74 75 f0 val 00 00 00 00 03 04 04 00 def 00 00 00 00 03 04 04 00 LDN 0x0a (Watchdog timer) idx 30 60 61 70 71 74 75 f0 val 00 00 00 00 03 04 04 02 def 00 00 00 00 03 04 04 02 Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xe1, rev=0x11 Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xe1/0x00, rev=0x11 Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xe1/0x00, rev=0x11 Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xe1/0x00, rev=0x11 Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xe1/0x00, rev=0x11 Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Output from rev 2341: Node20:~/coreboot-v2/util/flashrom # ./flashrom -w /root/arima.flash Calibrating delay loop... ok Found LinuxBIOS table at: 00000500 vendor id: ARIMA part id: HDAMA Enabling flash write on AMD8111...OK SST49LF004A/B found at physical address: 0xfff80000 Flash part is SST49LF004A/B Flash image seems to be a legacy BIOS. Disabling checks. Programming Page: 0007 at address: 0x00070000 Node20:~/coreboot-v2/util/flashrom # Flash file comparison: Column 1 Byte # in Flash file Column 2 Data read from flash after flashing Column 3 Data from the file used to flash, ie, /root/arima.flash from above command. Note: From flashrom version 0.9.1 we get this error - ERASE FAILED at 0x0007f000! Expected=0xff, Read=0x00, failed byte count from 0x00070000-0x0007ffff: 0x1000 This corresponds to 520192(x7f000) location, which is close to 520193 below. 21846 252 377 520193 0 272 520194 0 377 520198 0 17 520199 0 60 520200 0 376 520201 0 301 520202 0 146 520203 0 45 520204 0 377 520205 0 367 520206 0 377 520207 0 377 520208 0 146 520209 0 367 520210 0 330 520211 0 146 520212 0 3 520213 0 370 520214 0 353 520215 0 271 520216 0 377 520217 0 343 520218 0 17 520219 0 176 520220 0 330 520221 0 213 520222 0 303 520223 0 17 520224 0 156 520225 0 330 520226 0 17 520227 0 156 520228 0 355 520229 0 17 520230 0 176 520231 0 310 520232 0 17 520233 0 156 520234 0 360 520235 0 146 520236 0 201 520237 0 371 520238 0 16 520239 0 2 520242 0 167 520243 0 156 520244 0 146 520245 0 321 520246 0 345 520247 0 146 520248 0 213 520249 0 335 520250 0 146 520251 0 207 520252 0 361 520253 0 17 520254 0 176 520255 0 310 520256 0 146 520257 0 17 520258 0 275 520259 0 310 520260 0 164 520261 0 120 520262 0 146 520263 0 17 520264 0 263 520265 0 310 520266 0 17 520267 0 156 520268 0 310 520269 0 146 520270 0 203 520271 0 301 520272 0 1 520273 0 146 520274 0 63 520275 0 377 520276 0 146 520277 0 17 520278 0 253 520279 0 317 520280 0 146 520281 0 3 520282 0 337 520283 0 146 520284 0 367 520285 0 337 520286 0 146 520287 0 207 520288 0 361 520289 0 146 520290 0 213 520291 0 305 520292 0 146 520293 0 213 520294 0 325 520295 0 146 520296 0 301 520297 0 340 520298 0 10 520299 0 146 520300 0 301 520301 0 352 520302 0 30 520303 0 14 520304 0 6 520305 0 17 520306 0 60 520307 0 376 520308 0 301 520309 0 146 520310 0 213 520311 0 307 520312 0 146 520313 0 213 520314 0 327 520315 0 146 520316 0 301 520317 0 340 520318 0 10 520319 0 146 520320 0 301 520321 0 352 520322 0 30 520323 0 17 520324 0 272 520325 0 350 520326 0 13 520327 0 17 520328 0 60 520329 0 146 520330 0 213 520331 0 353 520332 0 376 520333 0 301 520334 0 200 520335 0 371 520336 0 16 520337 0 166 520338 0 247 520339 0 146 520340 0 207 520341 0 361 520342 0 146 520343 0 207 520344 0 361 520345 0 17 520346 0 176 520347 0 310 520348 0 146 520349 0 13 520350 0 300 520351 0 370 520352 0 164 520353 0 1 520354 0 371 520355 0 17 520356 0 176 520357 0 363 520358 0 17 520359 0 156 520360 0 313 520361 0 17 520362 0 176 520363 0 355 520364 0 17 520365 0 176 520366 0 333 520367 0 377 520368 0 343 520369 0 146 520370 0 17 520371 0 313 520372 0 17 520373 0 156 520374 0 333 520375 0 146 520376 0 270 520380 0 340 520381 0 17 520382 0 156 520383 0 320 520384 0 146 520385 0 271 520386 0 20 520388 0 1 520389 0 300 520390 0 17 520391 0 62 520392 0 146 520393 0 45 520394 0 377 520395 0 377 520396 0 343 520397 0 377 520398 0 146 520399 0 15 520402 0 10 520404 0 17 520405 0 60 520406 0 146 520407 0 271 520408 0 377 520409 0 2 520412 0 146 520413 0 63 520414 0 300 520415 0 146 520416 0 63 520417 0 322 520418 0 264 520419 0 14 520420 0 17 520421 0 60 520422 0 62 520423 0 344 520424 0 261 520426 0 17 520427 0 60 520428 0 376 520429 0 301 520430 0 200 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520518 0 63 520519 0 311 520520 0 216 520521 0 341 520522 0 214 520523 0 341 520524 0 301 520525 0 301 520526 0 13 520527 0 201 520528 0 301 520529 0 104 520530 0 301 520531 0 273 520532 0 130 520533 0 361 520534 0 351 520535 0 75 520536 0 2 520537 0 270 520538 0 377 520539 0 377 520540 0 146 520541 0 100 520542 0 146 520543 0 321 520544 0 350 520545 0 17 520546 0 156 520547 0 340 520548 0 146 520549 0 203 520550 0 370 520552 0 164 520553 0 36 520554 0 146 520555 0 271 520558 0 200 520560 0 146 520561 0 73 520562 0 301 520563 0 167 520564 0 23 520565 0 146 520566 0 17 520567 0 272 520568 0 344 520569 0 6 520570 0 163 520571 0 4 520572 0 146 520573 0 301 520574 0 341 520575 0 4 520576 0 17 520577 0 176 520578 0 302 520579 0 146 520580 0 73 520581 0 321 520582 0 166 520583 0 12 520584 0 146 520585 0 17 520586 0 272 520587 0 364 520588 0 5 520589 0 146 520590 0 17 520591 0 272 520592 0 364 520593 0 6 520594 0 146 520595 0 17 520596 0 272 520597 0 344 520598 0 5 520599 0 163 520600 0 177 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273 520771 0 107 520772 0 362 520773 0 351 520774 0 206 520775 0 375 520776 0 146 520777 0 213 520778 0 306 520779 0 146 520780 0 213 520781 0 320 520782 0 146 520783 0 301 520784 0 340 520785 0 11 520786 0 146 520787 0 301 520788 0 352 520789 0 27 520790 0 146 520791 0 271 520792 0 32 520794 0 1 520795 0 300 520796 0 17 520797 0 60 520798 0 17 520799 0 176 520800 0 300 520801 0 146 520802 0 275 520805 0 200 520807 0 146 520808 0 73 520809 0 305 520810 0 166 520811 0 42 520812 0 146 520813 0 213 520814 0 320 520815 0 146 520816 0 301 520817 0 340 520818 0 11 520819 0 146 520820 0 301 520821 0 352 520822 0 27 520823 0 146 520824 0 271 520825 0 35 520827 0 1 520828 0 300 520829 0 17 520830 0 60 520831 0 146 520832 0 271 520833 0 20 520835 0 1 520836 0 300 520837 0 17 520838 0 62 520839 0 146 520840 0 17 520841 0 272 520842 0 350 520843 0 25 520844 0 17 520845 0 60 520846 0 17 520847 0 176 520848 0 333 520849 0 146 520850 0 17 520851 0 313 520852 0 377 520853 0 343 520854 0 17 520855 0 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302 524047 0 2 524048 0 212 524049 0 301 524050 0 356 524051 0 200 524052 0 352 524053 0 6 524054 0 260 524055 0 12 524056 0 356 524057 0 200 524058 0 352 524059 0 2 524060 0 354 524061 0 44 524062 0 67 524063 0 12 524064 0 300 524065 0 164 524066 0 371 524067 0 300 524068 0 340 524069 0 4 524070 0 163 524071 0 7 524072 0 146 524073 0 301 524074 0 310 524075 0 20 524076 0 370 524077 0 377 524078 0 343 524079 0 146 524080 0 301 524081 0 310 524082 0 20 524083 0 371 524084 0 377 524085 0 343 524086 0 206 524087 0 304 524088 0 346 524089 0 162 524090 0 206 524091 0 304 524092 0 346 524093 0 163 524094 0 377 524095 0 343 524096 0 212 524097 0 304 524098 0 346 524099 0 162 524100 0 344 524101 0 163 524102 0 377 524103 0 343 524104 0 213 524105 0 372 524106 0 146 524107 0 17 524108 0 317 524109 0 213 524110 0 370 524111 0 212 524112 0 304 524113 0 264 524114 0 200 524115 0 146 524116 0 17 524117 0 310 524118 0 270 524119 0 300 524121 0 146 524122 0 301 524123 0 300 524124 0 10 524125 0 44 524126 0 374 524127 0 272 524128 0 370 524129 0 14 524130 0 146 524131 0 357 524132 0 346 524133 0 355 524134 0 272 524135 0 374 524136 0 14 524137 0 213 524138 0 307 524139 0 200 524140 0 344 524141 0 3 524142 0 2 524143 0 324 524144 0 213 524145 0 307 524146 0 354 524147 0 146 524148 0 17 524149 0 317 524150 0 213 524151 0 327 524152 0 377 524153 0 343 524154 0 213 524155 0 372 524156 0 146 524157 0 17 524158 0 317 524159 0 213 524160 0 370 524161 0 212 524162 0 304 524163 0 264 524164 0 200 524165 0 146 524166 0 17 524167 0 310 524168 0 270 524169 0 300 524171 0 146 524172 0 301 524173 0 300 524174 0 10 524175 0 44 524176 0 374 524177 0 272 524178 0 370 524179 0 14 524180 0 146 524181 0 357 524182 0 346 524183 0 355 524184 0 272 524185 0 374 524186 0 14 524187 0 213 524188 0 307 524189 0 200 524190 0 344 524191 0 3 524192 0 2 524193 0 324 524194 0 213 524195 0 307 524196 0 356 524197 0 146 524198 0 17 524199 0 317 524200 0 213 524201 0 327 524202 0 377 524203 0 343 524204 0 44 524205 0 374 524206 0 272 524207 0 370 524208 0 14 524209 0 146 524210 0 357 524211 0 346 524212 0 355 524213 0 272 524214 0 374 524215 0 14 524216 0 146 524217 0 213 524218 0 370 524219 0 146 524220 0 355 524221 0 146 524222 0 213 524223 0 320 524224 0 146 524225 0 213 524226 0 307 524227 0 377 524228 0 343 524229 0 146 524230 0 213 524231 0 372 524232 0 44 524233 0 374 524234 0 272 524235 0 370 524236 0 14 524237 0 146 524238 0 357 524239 0 346 524240 0 355 524241 0 272 524242 0 374 524243 0 14 524244 0 146 524245 0 227 524246 0 146 524247 0 357 524248 0 146 524249 0 213 524250 0 320 524251 0 146 524252 0 213 524253 0 307 524254 0 377 524255 0 343 524257 0 42 524258 0 20 524259 0 144 524260 0 164 524261 0 377 524262 0 377 524267 0 60 524268 0 276 524273 0 351 524274 0 42 524275 0 325 524281 0 352 524282 0 202 524283 0 325 524285 0 360 -----Original Message----- From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006@gmx.net] Sent: Thursday, September 17, 2009 8:16 AM To: Spangler, Mike T Cc: flashrom Subject: Re: [flashrom] Trial of ARIMA:HDAMA Motherboard Hi Mike, I edit the low below for brevity. On 10.09.2009 08:16, Spangler, Mike T wrote: > Tried 0.9.1-r710. Looks like its different, but it probably trashed the chip. No big deal.... > > node0:~ # flashrom -V -w arima.flash > flashrom v0.9.1-r710 > Found candidate at: 00000500-00000db0 > Found coreboot table at 0x00000500. > coreboot table found at 0x500. > coreboot header(24) checksum: bbc7 table(2224) checksum: a9cd entries: 13 > Vendor ID: ARIMA, part ID: HDAMA > Found chipset "AMD AMD8111", enabling flash write... OK. > This chipset supports the following protocols: Non-SPI. > Calibrating delay loop... 654M loops per second, 100 myus = 194 us. OK. > Probing for SST SST49LF004A/B, 512 KB: probe_jedec: id1 0xbf, id2 0x60 > Lock status for 0x000000 (size 0x010000) is 00, full access > Lock status for 0x010000 (size 0x010000) is 00, full access > Lock status for 0x020000 (size 0x010000) is 00, full access > Lock status for 0x030000 (size 0x010000) is 00, full access > Lock status for 0x040000 (size 0x010000) is 00, full access > Lock status for 0x050000 (size 0x010000) is 00, full access > Lock status for 0x060000 (size 0x010000) is 00, full access > Lock status for 0x070000 (size 0x010000) is 00, full access > Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. > Flash image seems to be a legacy BIOS. Disabling checks. > Writing flash chip... Lock status for 0x000000 (size 0x010000) is 00, full access > Lock status for 0x010000 (size 0x010000) is 00, full access > Lock status for 0x020000 (size 0x010000) is 00, full access > Lock status for 0x030000 (size 0x010000) is 00, full access > Lock status for 0x040000 (size 0x010000) is 00, full access > Lock status for 0x050000 (size 0x010000) is 00, full access > Lock status for 0x060000 (size 0x010000) is 00, full access > Lock status for 0x070000 (size 0x010000) is 00, full access > ERASE FAILED at 0x0007f000! Expected=0xff, Read=0x00, failed byte count from 0x00070000-0x0007ffff: 0x1000 > The issue you're facing is simple, but you might have to do a bit of work to fix it. You need special handling code for the flash boot block write protection on your board, commonly called board_enable. Don't worry, we can help you with that. First, do you know how the ROM image was flashed in the first place? flashrom? flash_and_burn? lbflash? /dev/bios? That will help us find any existing source code and save us the trouble of toggling loads of GPIOs. The output of "superiotool -dV" will be useful as well. Regards, Carl-Daniel -- http://www.hailfinger.org/

1 0

[PATCH] ICH SPI Preop handling
by Carl-Daniel Hailfinger 18 Sep '09

18 Sep '09

The current ICH SPI preop handling is a hack which spews lots of warnings, but still yields correct results. With the multicommand infrastructure I introduced in r645, it became possible to integrate ICH SPI preopcodes cleanly into the flashrom design. The new code checks for every opcode in a multicommand array if it is a preopcode. If yes, it checks if the next opcode is associated with that preopcode and in that case it simply runs the opcode because the correct preopcode will be run automatically before the opcode. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-ich9_multicommand_preop/ichspi.c =================================================================== --- flashrom-ich9_multicommand_preop/ichspi.c (Revision 725) +++ flashrom-ich9_multicommand_preop/ichspi.c (Arbeitskopie) @@ -745,18 +745,25 @@ int ich_spi_send_multicommand(struct spi_command *spicommands) { int ret = 0; + int oppos, preoppos; while ((spicommands->writecnt || spicommands->readcnt) && !ret) { + /* Will the next loop iteration be taken? */ + if ((spicommands + 1)->writecnt || (spicommands + 1)->readcnt) { + preoppos = find_preop(curopcodes, spicommands->writearr[0]); + oppos = find_opcode(curopcodes, (spicommands + 1)->writearr[0]); + /* Is the current op a preop for the next op? */ + if ((oppos != -1) && (preoppos != -1) && + (curopcodes->opcode[oppos].atomic == preoppos)) { + printf_debug("opcode 0x%02x will be run as PREOP\n", + spicommands->writearr[0]); + ret = 0; + spicommands++; + continue; + } + } + ret = ich_spi_send_command(spicommands->writecnt, spicommands->readcnt, spicommands->writearr, spicommands->readarr); - /* This awful hack needs to be smarter. - */ - if ((ret == SPI_INVALID_OPCODE) && - ((spicommands->writearr[0] == JEDEC_WREN) || - (spicommands->writearr[0] == JEDEC_EWSR))) { - printf_debug(" due to SPI master limitation, ignoring" - " and hoping it will be run as PREOP\n"); - ret = 0; - } spicommands++; } return ret; -- http://www.hailfinger.org/

2 9

[commit] r727 - trunk
by svn＠flashrom.org 18 Sep '09

18 Sep '09

Author: hailfinger Date: 2009-09-18 17:50:56 +0200 (Fri, 18 Sep 2009) New Revision: 727 Modified: trunk/flash.h trunk/ichspi.c trunk/spi.c Log: The current ICH SPI preop handling is a hack which spews lots of warnings, but still yields correct results. With the multicommand infrastructure I introduced in r645, it became possible to integrate ICH SPI preopcodes cleanly into the flashrom design. The new code checks for every opcode in a multicommand array if it is a preopcode. If yes, it checks if the next opcode is associated with that preopcode and in that case it simply runs the opcode because the correct preopcode will be run automatically before the opcode. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: FENG Yu Ning <fengyuning1984(a)gmail.com> Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-09-18 13:38:14 UTC (rev 726) +++ trunk/flash.h 2009-09-18 15:50:56 UTC (rev 727) @@ -498,7 +498,7 @@ struct spi_programmer { int (*command)(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); - int (*multicommand)(struct spi_command *spicommands); + int (*multicommand)(struct spi_command *cmds); /* Optimized functions for this programmer */ int (*read)(struct flashchip *flash, uint8_t *buf, int start, int len); @@ -514,7 +514,7 @@ int probe_spi_res(struct flashchip *flash); int spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int spi_send_multicommand(struct spi_command *spicommands); +int spi_send_multicommand(struct spi_command *cmds); int spi_write_enable(void); int spi_write_disable(void); int spi_chip_erase_60(struct flashchip *flash); @@ -539,7 +539,7 @@ uint32_t spi_get_valid_read_addr(void); int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -int default_spi_send_multicommand(struct spi_command *spicommands); +int default_spi_send_multicommand(struct spi_command *cmds); /* 82802ab.c */ int probe_82802ab(struct flashchip *flash); @@ -565,7 +565,7 @@ const unsigned char *writearr, unsigned char *readarr); int ich_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); int ich_spi_write_256(struct flashchip *flash, uint8_t * buf); -int ich_spi_send_multicommand(struct spi_command *spicommands); +int ich_spi_send_multicommand(struct spi_command *cmds); /* it87spi.c */ extern uint16_t it8716f_flashport; Modified: trunk/ichspi.c =================================================================== --- trunk/ichspi.c 2009-09-18 13:38:14 UTC (rev 726) +++ trunk/ichspi.c 2009-09-18 15:50:56 UTC (rev 727) @@ -742,22 +742,29 @@ return result; } -int ich_spi_send_multicommand(struct spi_command *spicommands) +int ich_spi_send_multicommand(struct spi_command *cmds) { int ret = 0; - while ((spicommands->writecnt || spicommands->readcnt) && !ret) { - ret = ich_spi_send_command(spicommands->writecnt, spicommands->readcnt, - spicommands->writearr, spicommands->readarr); - /* This awful hack needs to be smarter. - */ - if ((ret == SPI_INVALID_OPCODE) && - ((spicommands->writearr[0] == JEDEC_WREN) || - (spicommands->writearr[0] == JEDEC_EWSR))) { - printf_debug(" due to SPI master limitation, ignoring" - " and hoping it will be run as PREOP\n"); - ret = 0; - } - spicommands++; + int oppos, preoppos; + for (; (cmds->writecnt || cmds->readcnt) && !ret; cmds++) { + /* Is the next command valid or a terminator? */ + if ((cmds + 1)->writecnt || (cmds + 1)->readcnt) { + preoppos = find_preop(curopcodes, cmds->writearr[0]); + oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]); + /* Is the opcode of the current command listed in the + * ICH struct OPCODES as associated preopcode for the + * opcode of the next command? + */ + if ((oppos != -1) && (preoppos != -1) && + (curopcodes->opcode[oppos].atomic - 1 == preoppos)) { + printf_debug("opcode 0x%02x will be run as PREOP\n", + cmds->writearr[0]); + continue; + } + } + + ret = ich_spi_send_command(cmds->writecnt, cmds->readcnt, + cmds->writearr, cmds->readarr); } return ret; } Modified: trunk/spi.c =================================================================== --- trunk/spi.c 2009-09-18 13:38:14 UTC (rev 726) +++ trunk/spi.c 2009-09-18 15:50:56 UTC (rev 727) @@ -118,7 +118,7 @@ writearr, readarr); } -int spi_send_multicommand(struct spi_command *spicommands) +int spi_send_multicommand(struct spi_command *cmds) { if (!spi_programmer[spi_controller].multicommand) { fprintf(stderr, "%s called, but SPI is unsupported on this " @@ -126,7 +126,7 @@ return 1; } - return spi_programmer[spi_controller].multicommand(spicommands); + return spi_programmer[spi_controller].multicommand(cmds); } int default_spi_send_command(unsigned int writecnt, unsigned int readcnt, @@ -148,13 +148,12 @@ return spi_send_multicommand(cmd); } -int default_spi_send_multicommand(struct spi_command *spicommands) +int default_spi_send_multicommand(struct spi_command *cmds) { int result = 0; - while ((spicommands->writecnt || spicommands->readcnt) && !result) { - result = spi_send_command(spicommands->writecnt, spicommands->readcnt, - spicommands->writearr, spicommands->readarr); - spicommands++; + for (; (cmds->writecnt || cmds->readcnt) && !result; cmds++) { + result = spi_send_command(cmds->writecnt, cmds->readcnt, + cmds->writearr, cmds->readarr); } return result; } @@ -494,7 +493,7 @@ int spi_chip_erase_60(struct flashchip *flash) { int result; - struct spi_command spicommands[] = { + struct spi_command cmds[] = { { .writecnt = JEDEC_WREN_OUTSIZE, .writearr = (const unsigned char[]){ JEDEC_WREN }, @@ -518,7 +517,7 @@ return result; } - result = spi_send_multicommand(spicommands); + result = spi_send_multicommand(cmds); if (result) { fprintf(stderr, "%s failed during command execution\n", __func__); @@ -540,7 +539,7 @@ int spi_chip_erase_c7(struct flashchip *flash) { int result; - struct spi_command spicommands[] = { + struct spi_command cmds[] = { { .writecnt = JEDEC_WREN_OUTSIZE, .writearr = (const unsigned char[]){ JEDEC_WREN }, @@ -564,7 +563,7 @@ return result; } - result = spi_send_multicommand(spicommands); + result = spi_send_multicommand(cmds); if (result) { fprintf(stderr, "%s failed during command execution\n", __func__); return result; @@ -596,7 +595,7 @@ int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen) { int result; - struct spi_command spicommands[] = { + struct spi_command cmds[] = { { .writecnt = JEDEC_WREN_OUTSIZE, .writearr = (const unsigned char[]){ JEDEC_WREN }, @@ -614,7 +613,7 @@ .readarr = NULL, }}; - result = spi_send_multicommand(spicommands); + result = spi_send_multicommand(cmds); if (result) { fprintf(stderr, "%s failed during command execution\n", __func__); @@ -640,7 +639,7 @@ int spi_block_erase_d8(struct flashchip *flash, unsigned int addr, unsigned int blocklen) { int result; - struct spi_command spicommands[] = { + struct spi_command cmds[] = { { .writecnt = JEDEC_WREN_OUTSIZE, .writearr = (const unsigned char[]){ JEDEC_WREN }, @@ -658,7 +657,7 @@ .readarr = NULL, }}; - result = spi_send_multicommand(spicommands); + result = spi_send_multicommand(cmds); if (result) { fprintf(stderr, "%s failed during command execution\n", __func__); return result; @@ -702,7 +701,7 @@ int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen) { int result; - struct spi_command spicommands[] = { + struct spi_command cmds[] = { { .writecnt = JEDEC_WREN_OUTSIZE, .writearr = (const unsigned char[]){ JEDEC_WREN }, @@ -720,7 +719,7 @@ .readarr = NULL, }}; - result = spi_send_multicommand(spicommands); + result = spi_send_multicommand(cmds); if (result) { fprintf(stderr, "%s failed during command execution\n", __func__); @@ -779,7 +778,7 @@ int spi_write_status_register(int status) { int result; - struct spi_command spicommands[] = { + struct spi_command cmds[] = { { .writecnt = JEDEC_EWSR_OUTSIZE, .writearr = (const unsigned char[]){ JEDEC_EWSR }, @@ -797,7 +796,7 @@ .readarr = NULL, }}; - result = spi_send_multicommand(spicommands); + result = spi_send_multicommand(cmds); if (result) { fprintf(stderr, "%s failed during command execution\n", __func__); @@ -808,7 +807,7 @@ int spi_byte_program(int addr, uint8_t byte) { int result; - struct spi_command spicommands[] = { + struct spi_command cmds[] = { { .writecnt = JEDEC_WREN_OUTSIZE, .writearr = (const unsigned char[]){ JEDEC_WREN }, @@ -826,7 +825,7 @@ .readarr = NULL, }}; - result = spi_send_multicommand(spicommands); + result = spi_send_multicommand(cmds); if (result) { fprintf(stderr, "%s failed during command execution\n", __func__); @@ -844,7 +843,7 @@ (address >> 8) & 0xff, (address >> 0) & 0xff, }; - struct spi_command spicommands[] = { + struct spi_command cmds[] = { { .writecnt = JEDEC_WREN_OUTSIZE, .writearr = (const unsigned char[]){ JEDEC_WREN }, @@ -873,7 +872,7 @@ memcpy(&cmd[4], bytes, len); - result = spi_send_multicommand(spicommands); + result = spi_send_multicommand(cmds); if (result) { fprintf(stderr, "%s failed during command execution\n", __func__);

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