flashrom

flashrom@flashrom.org

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9188 discussions

[commit] r757 - trunk
by svn＠flashrom.org 14 Nov '09

14 Nov '09

Author: hailfinger Date: 2009-11-14 04:48:33 +0100 (Sat, 14 Nov 2009) New Revision: 757 Modified: trunk/flashchips.c trunk/jedec.c Log: The automatic retry in write_page_write_jedec didn't retry flashing the correct range, essentially rendering the functionality useless. This patch simplifies the code and fixes the bug. Thanks to Luke Dashjr for testing. Mark Winbond W29C040P as supported. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Luke Dashjr <luke_coreboot(a)dashjr.org> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-11-06 18:09:42 UTC (rev 756) +++ trunk/flashchips.c 2009-11-14 03:48:33 UTC (rev 757) @@ -3060,7 +3060,7 @@ .model_id = W_29C040P, .total_size = 512, .page_size = 256, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 10, .erase = erase_chip_jedec, Modified: trunk/jedec.c =================================================================== --- trunk/jedec.c 2009-11-06 18:09:42 UTC (rev 756) +++ trunk/jedec.c 2009-11-14 03:48:33 UTC (rev 757) @@ -262,7 +262,7 @@ int write_page_write_jedec(struct flashchip *flash, uint8_t *src, int start, int page_size) { - int i, tried = 0, start_index = 0, ok; + int i, tried = 0, ok; uint8_t *s = src; chipaddr bios = flash->virtual_memory; chipaddr dst = bios + start; @@ -275,7 +275,7 @@ chip_writeb(0xA0, bios + 0x5555); /* transfer data from source to destination */ - for (i = start_index; i < page_size; i++) { + for (i = 0; i < page_size; i++) { /* If the data is 0xFF, don't program it */ if (*src != 0xFF) chip_writeb(*src, dst); @@ -290,7 +290,7 @@ ok = !verify_range(flash, src, start, page_size, NULL); if (!ok && tried++ < MAX_REFLASH_TRIES) { - start_index = i; + fprintf(stderr, "retrying.\n"); goto retry; } if (!ok) {

1 0

Fix write_page_write_jedec retry, mark W29C040P as OK
by Carl-Daniel Hailfinger 14 Nov '09

14 Nov '09

The automatic retry in write_page_write_jedec didn't retry flashing the correct range, essentially rendering the functionality useless. This patch simplifies the code and fixes the bug. Mark Winbond W29C040P as supported. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-write_page_write_jedec_retry/jedec.c =================================================================== --- flashrom-write_page_write_jedec_retry/jedec.c (Revision 756) +++ flashrom-write_page_write_jedec_retry/jedec.c (Arbeitskopie) @@ -262,7 +262,7 @@ int write_page_write_jedec(struct flashchip *flash, uint8_t *src, int start, int page_size) { - int i, tried = 0, start_index = 0, ok; + int i, tried = 0, ok; uint8_t *s = src; chipaddr bios = flash->virtual_memory; chipaddr dst = bios + start; @@ -275,7 +275,7 @@ chip_writeb(0xA0, bios + 0x5555); /* transfer data from source to destination */ - for (i = start_index; i < page_size; i++) { + for (i = 0; i < page_size; i++) { /* If the data is 0xFF, don't program it */ if (*src != 0xFF) chip_writeb(*src, dst); @@ -290,7 +290,7 @@ ok = !verify_range(flash, src, start, page_size, NULL); if (!ok && tried++ < MAX_REFLASH_TRIES) { - start_index = i; + fprintf(stderr, "retrying.\n"); goto retry; } if (!ok) { Index: flashrom-write_page_write_jedec_retry/flashchips.c =================================================================== --- flashrom-write_page_write_jedec_retry/flashchips.c (Revision 756) +++ flashrom-write_page_write_jedec_retry/flashchips.c (Arbeitskopie) @@ -3060,7 +3060,7 @@ .model_id = W_29C040P, .total_size = 512, .page_size = 256, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_jedec, .probe_timing = 10, .erase = erase_chip_jedec, -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers."

2 2

Help: DO NOT REBOOT OR POWEROFF!
by NotLim 10 Nov '09

10 Nov '09

Hi there. I'm at #flashrom at freenode, but no one responds... so... can you give me a hand? Here's the problem: http://pastebin.com/m11614dbc Thanks!

4 3

[commit] r756 - trunk
by svn＠flashrom.org 06 Nov '09

06 Nov '09

Author: hailfinger Date: 2009-11-06 18:09:42 +0000 (Fri, 06 Nov 2009) New Revision: 756 Modified: trunk/flashchips.c Log: Fix incorrect comment in SST49LF004A/B description. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashchips.c =================================================================== --- trunk/flashchips.c 2009-10-31 01:53:09 UTC (rev 755) +++ trunk/flashchips.c 2009-11-06 18:09:42 UTC (rev 756) @@ -2236,7 +2236,7 @@ .block_erase = erase_sector_jedec, /* missing unlock */ }, { .eraseblocks = { {64 * 1024, 8} }, - .block_erase = erase_sst_fwhub_block, /* same as erase_sector_block, but with unlock */ + .block_erase = erase_sst_fwhub_block, /* same as erase_block_jedec, but with unlock */ }, { .eraseblocks = { {512 * 1024, 1} }, .block_erase = NULL, /* AA 55 80 AA 55 10, only in PP mode */

1 0

Remarks on flashing ASUS M2N-E
by Adrian Glaubitz 06 Nov '09

06 Nov '09

Hi guys, I have used flashrom (version 0.9.1+r736-1 from Debian testing) to program the latest BIOS into my ASUS M2N-E mainboard. According to flashrom, erasing and programming the BIOS chip was successful. However, after rebooting the machine wouldn't fire up again. It powered up but there was no sync signal on the VGA/DVI connector, also no reaction to keyboard input. Fortunately, I could restore normal operation by resetting the CMOS settings. The computer worked fine again except that the hardware network address had changed to an arbitrary value so that I couldn't connect to my local network at first anymore. I think, however, that the MAC can be restored with the AWDFLASH.EXE flash utility which has an option called "/MAC:" (haven't tried yet, network works fine after matching the MAC on our local DHCP servers). Thus, it would be nice if you could update the entry in the flashrom wiki with two footnotes on the ASUS M2N-E: [1] If the machine doesn't come up again after flashing, try resetting the CMOS. [2] Hardware address of the onboard network card might change to an arbitrary value. Especially [1] should be put as a footnote because despite the fact that it is *always* recommended to reset your CMOS settings after flashing a new BIOS version, the machine usually still comes up again after flashing, prompting with something like "CMOS checksum error or invalid settings". I just want to provide flashrom users with as much information on possible caveats as possible. Regards, Adrian

1 0

ECS P4VXASD2+
by Kyle Kienapfel 03 Nov '09

03 Nov '09

I've got a supported chipset and according to flashrom -L, a supported flash chip, but flashrom isn't detecting the flash chip. I verified that the read is accurate when I force it. Exact part number on the flash is W49F002U-12B I'd like to get this to work as the amiflash tool rebooted without warning making it scary to use. root@Console:~# /root/flashrom -r /tmp/fij2 flashrom v0.9.1-r710 No coreboot table found. Found chipset "VIA VT8235", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically. root@Console:~# root@Console:~# /root/flashrom -c W49F002U -r /tmp/fij2 -f flashrom v0.9.1-r710 No coreboot table found. Found chipset "VIA VT8235", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. No EEPROM/flash device found. Force read (-f -r -c) requested, forcing chip probe success: Found chip "Winbond W49F002U" (256 KB, Parallel) at physical address 0xfffc0000 Please note that forced reads most likely contain garbage. Reading flash... done. root@Console:~# root@Console:~# /root/flashrom -V |grep W49F002U Probing for Winbond W49F002U, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content root@Console:~# root@Console:~# lspci -vvnnxxx 00:00.0 Host bridge [0600]: VIA Technologies, Inc. VT8753 [P4X266 AGP] [1106:3128] (rev 01) Subsystem: VIA Technologies, Inc. Device [1106:0000] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR+ INTx- Latency: 8 Region 0: Memory at e0000000 (32-bit, prefetchable) [size=64M] Capabilities: [a0] AGP version 2.0 Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW- AGP3- Rate=x1,x2,x4 Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW- Rate=<none> Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel modules: via-agp, ipmi_si 00: 06 11 28 31 06 00 30 a2 01 00 00 06 00 08 00 00 10: 08 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40: 00 18 88 80 82 44 00 00 99 99 88 80 82 44 00 00 50: e8 be e7 88 6e 85 20 20 0e 00 00 00 10 20 20 20 60: 08 aa 00 20 20 d9 00 20 f9 29 32 50 40 04 00 00 70: 02 c8 00 01 31 01 10 00 01 00 00 00 00 00 00 00 80: 0f 61 00 00 c0 b0 88 00 02 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 02 c0 20 00 07 02 00 1f 00 00 00 00 2d 92 04 00 b0: 78 9b 10 9b 40 00 00 00 a8 00 00 00 00 00 00 00 c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 71 38 74 00 e0: 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 11 00 00 00 00 00 00 00 00 00 00:01.0 PCI bridge [0604]: VIA Technologies, Inc. VT8633 [Apollo Pro266 AGP] [1106:b091] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx- Latency: 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 Memory behind bridge: dde00000-dfefffff Prefetchable memory behind bridge: cdc00000-ddcfffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA+ MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel modules: ipmi_si, shpchp 00: 06 11 91 b0 07 01 30 22 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 f0 00 00 00 20: e0 dd e0 df c0 cd c0 dd 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 0c 00 40: 83 c7 00 44 24 72 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 01 00 02 02 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0b.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ [10ec:8139] (rev 10) !!! Invalid class 0200 for header type 02 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR+ INTx- Latency: 32 Interrupt: pin A routed to IRQ 11 Region 0: I/O ports at ec00 [size=256] Bus: primary=00, secondary=00, subordinate=02, sec-latency=0 Secondary status: SERR BridgeCtl: Parity- SERR+ ISA- VGA- MAbort+ >Reset- 16bInt- PostWrite- Kernel driver in use: 8139too Kernel modules: ipmi_si, 8139cp, 8139too 00: ec 10 3b 81 07 01 92 82 10 00 02 02 00 20 02 00 10: 01 ec 02 00 00 ff ff df 00 00 02 00 00 00 02 00 20: 00 00 02 00 00 00 02 00 00 00 02 00 ec 10 3b 81 30: 00 00 02 00 50 00 02 00 00 00 02 00 0b 01 22 40 40: 00 00 02 00 00 00 02 00 00 00 02 00 00 00 02 00 50: 01 00 c2 f7 00 00 02 00 00 00 02 00 00 00 02 00 60: 00 00 02 00 00 00 02 00 00 00 02 00 00 00 02 00 70: 00 00 02 00 00 00 02 00 00 00 02 00 00 00 02 00 80: 00 00 02 00 00 00 02 00 00 00 02 00 00 00 02 00 90: 00 00 02 00 00 00 02 00 00 00 02 00 00 00 02 00 a0: 00 00 02 00 00 00 02 00 00 00 02 00 00 00 02 00 b0: 00 00 02 00 00 00 02 00 00 00 02 00 00 00 02 00 c0: 00 00 02 00 00 00 02 00 00 00 02 00 00 00 02 00 d0: 00 00 02 00 00 00 02 00 00 00 02 00 00 00 02 00 e0: 00 00 02 00 00 00 02 00 00 00 02 00 00 00 02 00 f0: 00 00 02 00 00 00 02 00 00 00 02 00 00 00 02 00 00:10.0 USB Controller [0c03]: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] (rev 80) (prog-if 00 [UHCI]) Subsystem: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32, Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 5 Region 4: I/O ports at e000 [size=32] Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: uhci_hcd Kernel modules: ipmi_si, uhci-hcd 00: 06 11 38 30 17 00 10 02 80 00 03 0c 08 20 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 e0 00 00 00 00 00 00 00 00 00 00 06 11 38 30 30: 00 00 00 00 80 00 00 00 00 00 00 00 05 01 00 00 40: 40 12 03 00 00 00 00 00 00 0b 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 01 00 c2 ff 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00:10.1 USB Controller [0c03]: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] (rev 80) (prog-if 00 [UHCI]) Subsystem: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32, Cache Line Size: 32 bytes Interrupt: pin B routed to IRQ 5 Region 4: I/O ports at e400 [size=32] Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: uhci_hcd Kernel modules: ipmi_si, uhci-hcd 00: 06 11 38 30 17 00 10 02 80 00 03 0c 08 20 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 e4 00 00 00 00 00 00 00 00 00 00 06 11 38 30 30: 00 00 00 00 80 00 00 00 00 00 00 00 05 02 00 00 40: 40 12 03 00 00 00 00 00 00 0b 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 01 00 c2 ff 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00:10.2 USB Controller [0c03]: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] (rev 80) (prog-if 00 [UHCI]) Subsystem: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller [1106:3038] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32, Cache Line Size: 32 bytes Interrupt: pin C routed to IRQ 5 Region 4: I/O ports at e800 [size=32] Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: uhci_hcd Kernel modules: ipmi_si, uhci-hcd 00: 06 11 38 30 17 00 10 02 80 00 03 0c 08 20 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 e8 00 00 00 00 00 00 00 00 00 00 06 11 38 30 30: 00 00 00 00 80 00 00 00 00 00 00 00 05 03 00 00 40: 40 12 03 00 00 00 00 00 00 0b 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 01 00 c2 ff 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00:10.3 USB Controller [0c03]: VIA Technologies, Inc. USB 2.0 [1106:3104] (rev 82) (prog-if 20 [EHCI]) Subsystem: VIA Technologies, Inc. USB 2.0 [1106:3104] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32, Cache Line Size: 128 bytes Interrupt: pin D routed to IRQ 11 Region 0: Memory at dffffe00 (32-bit, non-prefetchable) [size=256] Capabilities: [80] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: ehci_hcd Kernel modules: ipmi_si, ehci-hcd 00: 06 11 04 31 17 00 10 02 82 20 03 0c 20 20 00 00 10: 00 fe ff df 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 04 31 30: 00 00 00 00 80 00 00 00 00 00 00 00 0b 04 00 00 40: 00 00 03 00 00 00 00 00 a0 20 00 09 00 00 00 00 50: 00 5a 00 80 00 00 00 00 04 0b 88 88 53 88 00 00 60: 20 20 01 00 00 00 00 00 01 00 00 00 00 00 08 c0 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 01 00 c2 ff 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00:11.0 ISA bridge [0601]: VIA Technologies, Inc. VT8235 ISA Bridge [1106:3177] Subsystem: VIA Technologies, Inc. KT4AV motherboard [1106:0000] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel modules: ipmi_si, i2c-viapro, via-ircc 00: 06 11 77 31 87 00 10 02 00 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 00 00 30: 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 40: 44 00 f8 00 00 00 00 00 0c 20 00 00 44 00 08 08 50: 81 1d 09 00 00 50 55 b0 23 80 ff 00 00 00 04 08 60: 00 00 00 00 10 00 02 04 00 00 00 00 00 00 00 00 70: 06 11 00 00 00 00 00 00 00 00 00 00 20 00 00 00 80: 20 84 59 00 9a 10 00 00 01 08 00 00 00 18 00 00 90: 00 02 f3 00 b0 c4 00 00 10 a9 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 01 04 01 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 04 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 05 00 00 00 00 00 00 00 00 00 00:11.1 IDE interface [0101]: VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE [1106:0571] (rev 06) (prog-if 8a [Master SecP PriP]) Subsystem: VIA Technologies, Inc. VT82C586/B/VT82C686/A/B/VT8233/A/C/VT8235 PIPC Bus Master IDE [1106:0571] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 Interrupt: pin A routed to IRQ 255 Region 4: I/O ports at fc00 [size=16] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: VIA_IDE Kernel modules: via82cxxx 00: 06 11 71 05 07 00 90 02 06 8a 01 01 00 20 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 fc 00 00 00 00 00 00 00 00 00 00 06 11 71 05 30: 00 00 00 00 c0 00 00 00 00 00 00 00 ff 01 00 00 40: 0b f2 09 35 18 1c c0 00 a8 a8 a8 20 ff 00 b6 20 50: 07 07 07 07 0c 00 00 00 a8 a8 a8 a8 00 00 00 00 60: 00 02 00 00 00 00 00 00 00 02 00 00 00 00 00 00 70: 42 01 00 00 00 00 00 00 82 01 00 00 00 00 00 00 80: 00 70 15 1f 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 06 00 71 05 06 11 71 05 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 07 00 00 00 00 00 00 00 00 00 00:11.5 Multimedia audio controller [0401]: VIA Technologies, Inc. VT8233/A/8235/8237 AC97 Audio Controller [1106:3059] (rev 50) Subsystem: Elitegroup Computer Systems Device [1019:0a83] Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin C routed to IRQ 5 Region 0: I/O ports at dc00 [size=256] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel modules: ipmi_si, via82cxxx_audio, snd-via82xx 00: 06 11 59 30 01 00 10 02 50 00 01 04 00 00 00 00 10: 01 dc 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 19 10 83 0a 30: 00 00 00 00 c0 00 00 00 00 00 00 00 05 03 00 00 40: 01 c8 00 00 00 00 00 00 00 00 00 00 3f 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 00 02 06 00 00 00 00 00 00 00 00 00 00 00 00 d0: 01 00 02 06 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:12.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6102 [Rhine-II] [1106:3065] (rev 74) Subsystem: VIA Technologies, Inc. VT6102 [Rhine II] Embeded Ethernet Controller on VT8235 [1106:0102] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (750ns min, 2000ns max), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 5 Region 0: I/O ports at d800 [size=256] Region 1: Memory at dffffd00 (32-bit, non-prefetchable) [size=256] Capabilities: [40] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: via-rhine Kernel modules: ipmi_si, via-rhine 00: 06 11 65 30 17 01 10 02 74 00 00 02 08 20 00 00 10: 01 d8 00 00 00 fd ff df 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 02 01 30: 00 00 00 00 40 00 00 00 00 00 00 00 05 01 03 08 40: 01 00 02 fe 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:00.0 VGA compatible controller [0300]: nVidia Corporation NV34 [GeForce FX 5500] [10de:0326] (rev a1) (prog-if 00 [VGA controller]) Subsystem: Chaintech Computer Co. Ltd Device [270f:1954] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (1250ns min, 250ns max) Interrupt: pin A routed to IRQ 5 Region 0: Memory at de000000 (32-bit, non-prefetchable) [size=16M] Region 1: Memory at d0000000 (32-bit, prefetchable) [size=128M] Expansion ROM at dfee0000 [disabled] [size=128K] Capabilities: [60] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [44] AGP version 3.0 Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW+ AGP3- Rate=x1,x2,x4 Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW- Rate=<none> Kernel modules: ipmi_si, nvidiafb 00: de 10 26 03 07 00 b0 02 a1 00 00 03 00 20 00 00 10: 00 00 00 de 08 00 00 d0 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 0f 27 54 19 30: 00 00 ee df 60 00 00 00 00 00 00 00 05 01 05 01 40: 0f 27 54 19 02 00 30 00 17 02 00 1f 00 00 00 00 50: 01 00 00 00 01 00 00 00 ce d6 23 00 0f 00 00 00 60: 01 44 02 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

1 0

Try on Lenovo TP T400s
by Ariel Garcia 01 Nov '09

01 Nov '09

Hello, i've tried flashrom on a Lenovo ThinkPad T400s laptop running kernel 2.6.31 (package version 2.6.31-trunk-amd64, Debian testing). See attached file pci.txt for the output of lspci Reading the ROM *seems* to work when run with -r, but complains Transaction error! run OPCODE 0x03 failed when run with -rV (see attached file flash.txt) The flash output file is also attached, although of a big size it seems to be empty because it compresses to 200 bytes :-( Let me know if i can test further. Best regards, Ariel

1 0

Re: [flashrom] Trial of ARIMA:HDAMA Motherboard
by Spangler, Mike T 31 Oct '09

31 Oct '09

Carl-Daniel - I can tell everyone's very busy. Just wanted to make sure that I haven't been forgotten. The system is still up and ready for testing. Mike -----Original Message----- From: Spangler, Mike T Sent: Friday, September 18, 2009 4:48 PM To: 'Carl-Daniel Hailfinger' Cc: flashrom(a)flashrom.org Subject: RE: [flashrom] Trial of ARIMA:HDAMA Motherboard Carl-Daniel - Yes, we are stuck with factory bios for now and a lot of it's due to our reliance on HP hardware and their maintenance requirements. We do have legacy Linux Networx gear that I could run coreboot on with gPXE. I'll have to investigate that solution at a later date. Also, the good thing about my method of reading the bios and flashing what I read is that it moves my bios settings with the flash. If you pull the flash off of the factory distribution, you have to redo the bios settings for every node one at a time. Below is the lspci output per your request: 0000:00:18.0 Class 0600: 1022:1100 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Capabilities: [80] #08 [2101] Capabilities: [a0] #08 [2101] Capabilities: [c0] #08 [2101] 00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 01 01 05 00 04 04 01 00 01 01 01 00 01 01 01 00 50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 60: 10 00 01 00 e4 00 00 00 00 c8 00 0f 74 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 a0 01 21 20 00 11 11 22 04 75 80 02 00 00 00 90: 56 04 51 02 00 01 04 00 07 00 00 00 00 00 00 00 a0: 08 c0 01 21 20 00 11 11 22 05 75 80 02 00 00 00 b0: 13 56 13 04 00 00 00 00 03 00 00 00 00 00 00 00 c0: 08 00 01 21 d0 00 11 77 22 00 75 80 02 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:00:18.1 Class 0600: 1022:1101 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 03 00 00 00 00 00 ff 00 03 00 00 01 01 00 ff 01 50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00 60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00 70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 03 00 f8 00 00 1f fb 00 c0: 03 10 00 00 00 20 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 03 00 01 04 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:00:18.2 Class 0600: 1022:1102 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 00 00 00 01 10 00 00 01 20 00 00 01 30 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 ce e0 0f 00 ce e0 0f 00 ce e0 0f 00 ce e0 0f 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 44 00 00 00 00 00 00 00 35 33 72 13 20 0a 10 00 90: 00 8c 33 08 08 0b 5b 0e 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: fd 2f 13 bf d0 00 00 00 d7 ff 5e 81 d0 87 9f 90 c0: 00 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 05 12 57 44 8d 44 e0 76 fe 8e 08 60 6d c8 54 69 e0: 14 44 63 6b e5 42 f3 db 33 8e 62 1c f4 4c b9 3a f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:00:18.3 Class 0600: 1022:1103 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 03 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: ff 3b 00 00 40 00 c0 02 00 00 00 00 00 00 00 00 50: 08 86 bb c0 60 00 00 00 16 16 16 00 40 d7 be 22 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 11 01 02 51 11 80 00 50 00 38 00 08 1b 22 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 03 00 00 00 7a 00 00 00 00 dd ef 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 3c 00 00 80 db e5 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 07 07 e2 04 00 00 00 00 00 25 00 00 e0: 00 00 00 00 20 0c 57 00 1b 01 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:00:19.0 Class 0600: 1022:1100 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- Capabilities: [80] #08 [2101] Capabilities: [a0] #08 [2101] Capabilities: [c0] #08 [2101] 00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 04 04 01 00 01 01 05 00 01 01 01 00 01 01 01 00 50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 60: 11 00 01 00 e4 00 00 00 00 c8 00 0f 7c 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 a0 01 21 d0 00 11 77 22 00 75 80 02 00 00 00 90: 56 04 51 02 00 00 00 00 00 00 00 00 00 00 00 00 a0: 08 c0 01 21 20 00 11 11 22 05 75 80 02 00 00 00 b0: 13 56 13 04 00 00 00 00 03 00 00 00 00 00 00 00 c0: 08 00 01 21 d0 00 11 77 22 00 75 80 02 00 00 00 d0: 0c 34 01 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:00:19.1 Class 0600: 1022:1101 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 03 00 00 00 00 00 ff 00 03 00 00 01 01 00 ff 01 50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00 60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00 70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 03 00 f8 00 00 1f fb 00 c0: 03 10 00 00 00 20 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 03 00 01 04 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:00:19.2 Class 0600: 1022:1102 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 00 00 00 01 10 00 00 01 20 00 00 01 30 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 ce e0 0f 00 ce e0 0f 00 ce e0 0f 00 ce e0 0f 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 44 00 00 00 00 00 00 00 35 33 72 13 20 0a 10 00 90: 00 8c 33 08 08 0b 5b 0e 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 6f 68 15 bf d0 00 00 00 50 3e 50 02 c0 a1 42 d4 c0: 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 58 6f ff 13 b4 43 27 ba b5 7f 19 9f 74 7f eb bb e0: f9 f6 cf bb 95 cd f3 bc 7d dc 8d af fd 99 ce a3 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:00:19.3 Class 0600: 1022:1103 Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 03 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: ff 3b 00 00 40 00 c0 02 00 00 00 00 00 00 00 00 50: 88 71 e6 db 21 00 00 00 16 16 16 00 c0 d3 be 22 60: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 11 01 02 51 11 80 00 50 00 38 00 08 1b 22 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 03 00 00 00 7a 00 00 00 00 dd ef 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 36 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 07 07 e2 04 00 00 00 00 00 25 00 00 e0: 00 00 00 00 20 10 55 00 1b 01 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:01:01.0 Class 0604: 1022:7450 (rev 12) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 Bus: primary=01, secondary=02, subordinate=02, sec-latency=64 I/O behind bridge: 00002000-00001fff Memory behind bridge: fb000000-fb0fffff Prefetchable memory behind bridge: 00000000fb100000-00000000fb000000 BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- Capabilities: [a0] Capabilities: [b8] #08 [8000] Capabilities: [c0] #08 [0041] 00: 22 10 50 74 57 01 30 02 12 00 04 06 00 40 81 00 10: 00 00 00 00 00 00 00 00 01 02 02 40 21 11 20 22 20: 00 fb 00 fb 11 fb 01 fb 00 00 00 00 00 00 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 ff 00 03 00 40: 07 00 1f 00 00 00 00 00 02 0c 00 00 01 2c 00 00 50: 00 00 03 00 00 00 05 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 07 b8 03 00 08 01 03 00 0e 00 0e 00 02 00 02 00 b0: 00 00 00 00 00 00 00 00 08 c0 00 80 00 00 00 03 c0: 08 00 41 00 22 00 11 11 22 00 00 00 22 04 35 00 d0: 02 00 35 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 04 04 10 00 04 04 0d 00 04 04 16 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:01:01.1 Class 0800: 1022:7451 (rev 01) (prog-if 10) Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Region 0: Memory at fb100000 (64-bit, non-prefetchable) 00: 22 10 51 74 02 00 00 02 01 10 00 08 00 00 00 00 10: 04 00 10 fb 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 03 00 00 00 04 00 10 fb 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:01:02.0 Class 0604: 1022:7450 (rev 12) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 Bus: primary=01, secondary=03, subordinate=03, sec-latency=64 I/O behind bridge: 00002000-00001fff Memory behind bridge: fb100000-fb0fffff Prefetchable memory behind bridge: 00000000fa000000-00000000faf00000 BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- Capabilities: [a0] Capabilities: [b8] #08 [8000] 00: 22 10 50 74 57 01 30 02 12 00 04 06 00 40 81 00 10: 00 00 00 00 00 00 00 00 01 03 03 40 21 11 20 a3 20: 10 fb 00 fb 01 fa f1 fa 00 00 00 00 00 00 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 ff 00 03 00 40: 05 00 1f 00 00 00 00 00 00 00 00 00 01 2c 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 07 b8 c3 00 10 01 03 00 0e 00 0e 00 02 00 02 00 b0: 00 00 00 00 00 00 00 00 08 00 00 80 00 00 00 04 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:01:02.1 Class 0800: 1022:7451 (rev 01) (prog-if 10) Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Region 0: Memory at fb101000 (64-bit, non-prefetchable) 00: 22 10 51 74 02 00 00 02 01 10 00 08 00 00 00 00 10: 04 10 10 fb 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 03 00 00 00 04 10 10 fb 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:01:03.0 Class 0604: 1022:7460 (rev 07) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 Bus: primary=01, secondary=04, subordinate=04, sec-latency=64 I/O behind bridge: 00001000-00001fff Memory behind bridge: f8000000-f90fffff Prefetchable memory behind bridge: fb100000-fb0fffff Expansion ROM at 00001000 [disabled] [size=4K] BridgeCtl: Parity+ SERR+ NoISA+ VGA+ MAbort- >Reset- FastB2B- Capabilities: [c0] #08 [0083] Capabilities: [f0] #08 [8000] 00: 22 10 60 74 47 01 30 02 07 00 04 06 00 40 01 00 10: 00 00 00 00 00 00 00 00 01 04 04 40 10 10 00 22 20: 00 f8 00 f9 10 fb 00 fb 00 00 00 00 00 00 00 00 30: 00 00 00 00 c0 00 00 00 00 00 00 00 ff 00 0f 08 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 04 06 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 08 f0 83 00 22 00 00 00 d0 00 00 00 22 00 01 00 d0: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 08 00 0f 00 08 00 11 00 0f 00 17 00 00 00 00 00 f0: 08 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 0000:01:04.0 Class 0601: 1022:7468 (rev 05) Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 0 00: 22 10 68 74 0f 00 20 02 05 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 30 07 c0 01 00 00 02 9f fd 00 01 00 00 00 c0 50: 00 00 00 00 85 01 00 00 44 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 de 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:01:04.1 Class 0101: 1022:7469 (rev 03) (prog-if 8a [Master SecP PriP]) Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 Region 4: I/O ports at 0f00 [size=16] 00: 22 10 69 74 05 00 00 02 03 8a 01 01 00 40 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 00 00 40: 43 f0 0f 00 00 00 00 00 5e 5e 5e 20 2a 00 ff 20 50: 03 03 03 c6 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:01:04.2 Class 0c05: 1022:746a (rev 02) Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin D routed to IRQ 0 Region 0: I/O ports at 2400 00: 22 10 6a 74 01 00 00 02 02 00 05 0c 00 40 00 00 10: 01 24 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 00 40: 02 00 05 0c 00 00 00 00 06 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:01:04.3 Class 0000: 1022:746b (rev 05) Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- 00: 22 10 6b 74 00 00 80 02 05 00 00 00 00 40 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 d1 00 04 00 00 00 00 20 14 10 00 00 00 00 00 50: 00 80 00 00 0f 00 00 00 01 20 00 00 00 00 00 00 60: 00 00 00 00 13 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 54 ac 76 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:02:03.0 Class 0200: 14e4:16a6 (rev 02) Subsystem: 14e4:000c Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 (16000ns min), cache line size 10 Interrupt: pin A routed to IRQ 19 Region 0: Memory at fb000000 (64-bit, non-prefetchable) [size=1026M] Expansion ROM at 00010000 [disabled] Capabilities: [40] PCI-X non-bridge device. Command: DPERE- ERO- RBC=0 OST=0 Status: Bus=255 Dev=31 Func=1 64bit+ 133MHz+ SCD- USC-, DC=simple, DMMRBC=2, DMOST=0, DMCRS=1, RSCEM- Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=1 PME- Capabilities: [50] Vital Product Data Capabilities: [58] Message Signalled Interrupts: 64bit+ Queue=0/3 Enable- Address: fcfb626b00cc0528 Data: 0109 00: e4 14 a6 16 46 01 b0 02 02 00 00 02 10 40 00 00 10: 04 00 00 fb 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 e4 14 0c 00 30: 00 00 20 40 40 00 00 00 00 00 00 00 00 01 40 00 40: 07 48 00 00 f9 ff 43 04 01 50 02 c0 00 20 00 64 50: 03 58 00 00 0a 80 a0 22 05 00 86 00 28 05 cc 00 60: 6b 62 fb fc 09 01 00 00 98 02 02 10 00 00 3f 76 70: fe 10 00 00 df 00 00 80 4c 5b 03 00 00 00 00 00 80: 00 00 00 00 9f 13 88 f6 34 00 13 04 82 10 08 00 90: 09 92 00 01 83 01 00 00 00 00 00 00 83 01 00 00 a0: 00 00 00 00 bb 00 00 00 00 00 00 00 cd 01 00 00 b0: 00 00 00 00 00 00 00 f6 00 00 00 00 00 00 00 f6 c0: 00 00 00 00 00 00 00 f6 00 00 00 00 00 00 00 f6 d0: 00 00 00 00 00 00 00 f6 00 00 00 00 00 00 00 f6 e0: 00 00 00 00 00 00 00 f6 00 00 00 00 00 00 00 f6 f0: 00 00 00 00 00 00 00 f6 00 00 00 00 00 00 00 f6 0000:02:04.0 Class 0200: 14e4:16a6 (rev 02) Subsystem: 14e4:000c Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Latency: 64 (16000ns min), cache line size 10 Interrupt: pin A routed to IRQ 19 Region 0: Memory at fb010000 (64-bit, non-prefetchable) [size=106M] Expansion ROM at 00010000 [disabled] Capabilities: [40] PCI-X non-bridge device. Command: DPERE- ERO+ RBC=0 OST=0 Status: Bus=255 Dev=31 Func=1 64bit+ 133MHz+ SCD- USC-, DC=simple, DMMRBC=2, DMOST=0, DMCRS=1, RSCEM- Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=1 PME- Capabilities: [50] Vital Product Data Capabilities: [58] Message Signalled Interrupts: 64bit+ Queue=0/3 Enable- Address: fcfd56ebfbf37f4c Data: eff5 00: e4 14 a6 16 46 01 b0 02 02 00 00 02 10 40 00 00 10: 04 00 01 fb 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 e4 14 0c 00 30: 00 00 ad 06 40 00 00 00 00 00 00 00 00 01 40 00 40: 07 48 02 00 f9 ff 43 04 01 50 02 c0 00 20 00 64 50: 03 58 b8 00 f7 e5 fe 79 05 00 86 00 4c 7f f3 fb 60: eb 56 fd fc f5 ef 00 00 9a 02 02 10 00 00 3f 76 70: be 12 00 00 df 00 00 00 50 00 00 00 00 00 00 00 80: 03 58 b8 00 5f bf f5 eb 34 00 00 00 fe 10 08 00 90: 01 02 00 01 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:03:01.0 Class 0280: 14c1:8043 (rev 04) Subsystem: 14c1:8043 Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR- FastB2B- Status: Cap+ 66Mhz+ UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR+ Interrupt: pin A routed to IRQ 17 Region 0: Memory at fa000000 (64-bit, prefetchable) Capabilities: [44] Message Signalled Interrupts: 64bit+ Queue=0/0 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [54] PCI-X non-bridge device. Command: DPERE- ERO- RBC=0 OST=0 Status: Bus=3 Dev=1 Func=0 64bit+ 133MHz+ SCD- USC-, DC=simple, DMMRBC=3, DMOST=0, DMCRS=2, RSCEM-00: c1 14 43 80 42 00 30 80 04 00 80 02 10 40 00 00 10: 0c 00 00 fa 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 c1 14 43 80 30: 00 00 00 00 44 00 00 00 00 00 00 00 00 01 00 00 40: 00 00 00 55 05 54 80 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 07 00 00 00 08 03 63 08 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 ac 00 60 dd 48 b1 80 0000:04:00.0 Class 0c03: 1022:7464 (rev 0b) (prog-if 10) Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin D routed to IRQ 0 Region 0: Memory at f9000000 (32-bit, non-prefetchable) 00: 22 10 64 74 02 01 80 02 0b 10 03 0c 00 40 80 00 10: 00 00 00 f9 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 50 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:04:00.1 Class 0c03: 1022:7464 (rev 0b) (prog-if 10) Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin D routed to IRQ 0 Region 0: Memory at f9001000 (32-bit, non-prefetchable) 00: 22 10 64 74 02 01 80 02 0b 10 03 0c 00 40 00 00 10: 00 10 00 f9 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 04 00 50 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:04:00.2 Class 0c03: 1022:7463 (rev 02) (prog-if 20) Subsystem: 1022:7463 Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin D routed to IRQ 0 Region 0: Memory at f9003000 (32-bit, non-prefetchable) Region 1: Memory at f9004000 (32-bit, non-prefetchable) [size=32] Capabilities: [80] #0a [4000] Capabilities: [88] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=100mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 22 10 63 74 02 00 10 02 02 20 03 0c 00 40 00 00 10: 00 30 00 f9 00 40 00 f9 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 63 74 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 04 00 00 40: 01 00 00 00 00 00 00 c0 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 01 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 22 10 63 74 01 00 00 00 40 30 00 01 00 00 00 00 80: 0a 88 00 40 00 00 00 00 01 00 82 fe 00 00 00 00 90: 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0000:04:06.0 Class 0300: 1002:4752 (rev 27) Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- Interrupt: pin A routed to IRQ 0 Region 0: Memory at f8000000 (32-bit, non-prefetchable) Region 1: I/O ports at 1000 [size=256] Region 2: Memory at f9002000 (32-bit, non-prefetchable) [size=4K] Capabilities: [5c] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- 00: 02 10 52 47 83 00 90 02 27 00 00 03 10 40 00 00 10: 00 00 00 f8 01 10 00 00 00 20 00 f9 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 5c 00 00 00 00 00 00 00 00 01 08 00 40: 0c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 02 5c 10 00 01 00 00 ff 00 00 00 00 01 00 02 06 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -----Original Message----- From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006@gmx.net] Sent: Friday, September 18, 2009 3:18 PM To: Spangler, Mike T Cc: flashrom(a)flashrom.org Subject: Re: [flashrom] Trial of ARIMA:HDAMA Motherboard Hi Mike, On 18.09.2009 18:55, Spangler, Mike T wrote: > I've corrected my email and am now sending to the group. > Thanks. >> Of course I'd prefer it if you tried to flash coreboot (new name of >> LinuxBIOS) to these boards, but that's your choice. Anyway, you said you >> have the factory BIOS around somewhere. Is it the one at >> http://flextronics.com/arima/Server/Download/Download/HDAMA189.zip ? >> > > I can't use flash coreboot (LinuxBIOS) because our cluster management tools require pxeboot. We've transitioned away from it. > That's unfortunate. Did you know that coreboot+SeaBIOS works fine with gPXE? We coreboot/flashrom developers are always interested in helping people update coreboot to the latest and greatest. So if you need PXE booting, there's no need to move back to the factory BIOS, a simple coreboot update should suffice. > So, the bios zip file above is correct, but I'm not using it. It will not work for flashing a chip with LinuxBios. The way I do this is to do a "flashrom -r" on a system with factory bios and then take that newly created flashrom file and do a "flashrom -w" with it on a board with LinuxBios. That's one option. The other option would be to extract the BIOS from the .ROM file. That looks reasonably easy. No guarantees, though. dd if=something.ROM of=bios.bin bs=1k count=512 > This is the method we used with the old bios_copy software from Linux Networx, but that was extremely unreliable. > flashrom strives to be the most reliable flashing tool out there. The current version has builtin verification for every step it does. >> Hmm ok. I think we have enough docs to iterate through all possible >> board enables. How many of these boards do you have (in case we trash >> the ROM of one of them)? >> > > The ROM is removeable, so we only potentially trash a PLCC chip. I have a half dozen or so spares. > Great. And with hotplugging/hotflashing it should be possible to reflash a trashed chip in another board. Can you supply the output of "lspci -nnvvvxxx" as root? That will allow me to dig further. I'd like to limit the search to a reasonable subset of options. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[commit] r755 - trunk
by svn＠flashrom.org 31 Oct '09

31 Oct '09

Author: hailfinger Date: 2009-10-31 02:53:09 +0100 (Sat, 31 Oct 2009) New Revision: 755 Modified: trunk/chipset_enable.c trunk/flash.h trunk/flashrom.c Log: Add infrastructure to check and report to the user the maximum supported decode size for chipsets and tested mainboards. The rationale is to warn users when they, for example, try to flash a 512KB parallel flash chip but their chipset only supports 256KB, or they try to flash 512KB and the chipset _does_ theoretically support 512KB but their special board doesn't wire all address lines and thus supports only 256 KB ROM chips at maximum. This has cost Uwe hours of debugging on some board already, until he figured out what was going on. We should try warn our users where possible about this. The chipset and the chip may have more than one bus in common (e.g. SB600 and Pm49* can both speak LPC+FWH) and on SB600/SB7x0/SB8x0 there are different limits for LPC and FWH. The only way to tell the user about the exact circumstances is to spew error messages per bus. The code will issue a warning during probe (which does fail for some chips if the size is too big) and abort before the first real read/write/erase action. If no action is specified, the warning is printed anyway. That way, a user can find out why probe might not have worked, and will be stopped before he/she gets incorrect results. Add a bitcount function to the infrastructure. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/chipset_enable.c =================================================================== --- trunk/chipset_enable.c 2009-10-30 21:12:39 UTC (rev 754) +++ trunk/chipset_enable.c 2009-10-31 01:53:09 UTC (rev 755) @@ -42,6 +42,17 @@ enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI; +/** + * Programmers supporting multiple buses can have differing size limits on + * each bus. Store the limits for each bus in a common struct. + */ +struct decode_sizes max_rom_decode = { + .parallel = 0xffffffff, + .lpc = 0xffffffff, + .fwh = 0xffffffff, + .spi = 0xffffffff +}; + extern int ichspi_lock; static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) Modified: trunk/flash.h =================================================================== --- trunk/flash.h 2009-10-30 21:12:39 UTC (rev 754) +++ trunk/flash.h 2009-10-31 01:53:09 UTC (rev 755) @@ -352,9 +352,17 @@ void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask); int board_flash_enable(const char *vendor, const char *part); +struct decode_sizes { + uint32_t parallel; + uint32_t lpc; + uint32_t fwh; + uint32_t spi; +}; + /* chipset_enable.c */ extern enum chipbustype buses_supported; int chipset_flash_enable(void); +extern struct decode_sizes max_rom_decode; extern unsigned long flashbase; Modified: trunk/flashrom.c =================================================================== --- trunk/flashrom.c 2009-10-30 21:12:39 UTC (rev 754) +++ trunk/flashrom.c 2009-10-31 01:53:09 UTC (rev 755) @@ -299,6 +299,15 @@ return (a > b) ? a : b; } +int bitcount(unsigned long a) +{ + int i = 0; + for (; a != 0; a >>= 1) + if (a & 1) + i++; + return i; +} + char *strcat_realloc(char *dest, const char *src) { dest = realloc(dest, strlen(dest) + strlen(src) + 1); @@ -398,10 +407,60 @@ return ret; } +int check_max_decode(enum chipbustype buses, uint32_t size) +{ + int limitexceeded = 0; + if ((buses & CHIP_BUSTYPE_PARALLEL) && + (max_rom_decode.parallel < size)) { + limitexceeded++; + printf_debug("Chip size %u kB is bigger than supported " + "size %u kB of chipset/board/programmer " + "for %s interface, " + "probe/read/erase/write may fail. ", size / 1024, + max_rom_decode.parallel / 1024, "Parallel"); + } + if ((buses & CHIP_BUSTYPE_LPC) && (max_rom_decode.lpc < size)) { + limitexceeded++; + printf_debug("Chip size %u kB is bigger than supported " + "size %u kB of chipset/board/programmer " + "for %s interface, " + "probe/read/erase/write may fail. ", size / 1024, + max_rom_decode.lpc / 1024, "LPC"); + } + if ((buses & CHIP_BUSTYPE_FWH) && (max_rom_decode.fwh < size)) { + limitexceeded++; + printf_debug("Chip size %u kB is bigger than supported " + "size %u kB of chipset/board/programmer " + "for %s interface, " + "probe/read/erase/write may fail. ", size / 1024, + max_rom_decode.fwh / 1024, "FWH"); + } + if ((buses & CHIP_BUSTYPE_SPI) && (max_rom_decode.spi < size)) { + limitexceeded++; + printf_debug("Chip size %u kB is bigger than supported " + "size %u kB of chipset/board/programmer " + "for %s interface, " + "probe/read/erase/write may fail. ", size / 1024, + max_rom_decode.spi / 1024, "SPI"); + } + if (!limitexceeded) + return 0; + /* Sometimes chip and programmer have more than one bus in common, + * and the limit is not exceeded on all buses. Tell the user. + */ + if (bitcount(buses) > limitexceeded) + printf_debug("There is at least one common chip/programmer " + "interface which can support a chip of this size. " + "You can try --force at your own risk.\n"); + return 1; +} + struct flashchip *probe_flash(struct flashchip *first_flash, int force) { struct flashchip *flash; - unsigned long base = 0, size; + unsigned long base = 0; + uint32_t size; + enum chipbustype buses_common; char *tmp; for (flash = first_flash; flash && flash->name; flash++) { @@ -413,7 +472,8 @@ printf_debug("failed! flashrom has no probe function for this flash chip.\n"); continue; } - if (!(buses_supported & flash->bustype)) { + buses_common = buses_supported & flash->bustype; + if (!buses_common) { tmp = flashbuses_to_text(buses_supported); printf_debug("skipped. Host bus type %s ", tmp); free(tmp); @@ -424,6 +484,7 @@ } size = flash->total_size * 1024; + check_max_decode(buses_common, size); base = flashbase ? flashbase : (0xffffffff - size + 1); flash->virtual_memory = (chipaddr)programmer_map_flash_region("flash chip", base, size); @@ -956,6 +1017,15 @@ "mainboard you tested. Thanks for your help!\n===\n"); } + size = flash->total_size * 1024; + if (check_max_decode((buses_supported & flash->bustype), size) && + (!force)) { + fprintf(stderr, "Chip is too big for this programmer " + "(-V gives details). Use --force to override.\n"); + programmer_shutdown(); + return 1; + } + if (!(read_it | write_it | verify_it | erase_it)) { printf("No operations were specified.\n"); // FIXME: flash writes stay enabled! @@ -974,7 +1044,6 @@ if (write_it && !dont_verify_it) verify_it = 1; - size = flash->total_size * 1024; buf = (uint8_t *) calloc(size, sizeof(char)); if (erase_it) {

1 0

[commit] r754 - trunk
by svn＠flashrom.org 30 Oct '09

30 Oct '09

Author: hailfinger Date: 2009-10-30 22:12:39 +0100 (Fri, 30 Oct 2009) New Revision: 754 Modified: trunk/pcidev.c Log: Adjust a help text for external PCI programmers to the new parameter scheme. Pointed out by Maciej Pijanka. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/pcidev.c =================================================================== --- trunk/pcidev.c 2009-10-22 15:07:30 UTC (rev 753) +++ trunk/pcidev.c 2009-10-30 21:12:39 UTC (rev 754) @@ -100,7 +100,7 @@ exit(1); } else if (found > 1) { fprintf(stderr, "Error: Multiple supported PCI devices found. " - "Use 'flashrom -p xxxx=bb:dd.f' \n" + "Use 'flashrom -p xxxx:bb:dd.f' \n" "to explicitly select the card with the given BDF " "(PCI bus, device, function).\n"); exit(1);

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