flashrom

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9189 discussions

#4: rKdcRzWWisJHafAk
by flashrom 15 Dec '09

15 Dec '09

#4: rKdcRzWWisJHafAk ---------------------------------+------------------------------------------ Reporter: soeqjvpr | Owner: hailfinger Type: defect | Status: new Priority: major | Milestone: flashrom 0.9.2 Component: flashrom | Version: pre-0.9.0 Keywords: XBQOtXfRZNxW | Dependencies: IpMeRHXaRGCyFwkuP Patchstatus: there is no patch | ---------------------------------+------------------------------------------ GADS9k <a href="http://ryonxwovdvli.com/">ryonxwovdvli</a>, [url=http://xfljdwyyyrvj.com/]xfljdwyyyrvj[/url], [link=http://jaagzzjtesui.com/]jaagzzjtesui[/link], http://gnbcygbbgttk.com/ -- Ticket URL: <http://www.flashrom.org/trac/flashrom/ticket/4> flashrom <http://www.flashrom.org/>

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[Patch] Board: Acorp 6A815EPD autodetectable (v2).
by Luc Verhaegen 14 Dec '09

14 Dec '09

Hi Jonathan, I've swapped both id blocks around, so it could actually work this time :) Luc Verhaegen.

3 3

[PATCH] Chipset/Board: vt8237: Set All mem cycles to LPC in chipset enable.
by Luc Verhaegen 14 Dec '09

14 Dec '09

Only done for VT8237R (possibly needed for VT8237 too), VT8235 does not need this (even if the original bios does so: Asus A7V8X-MX SE, MSI KT4V were verified). This then opens a floodgate of cleanups in the board enables. * EPIA SP board enable vanishes, taking EPIA CN match with it. * Asus A7V8X-MX/Tyan S2498 board enable then equals w836xx_memw_enable_2e * AOpen vKM400Am-S board enable then equals it8705_rom_write_enable * Epia M board enable becomes via_vt823x_gpio15_raise * Epia N board enable becomes via_vt823x_gpio9_raise * Asus M2V-MX board enable becomes via_vt823x_gpio5_raise * vt823x_gpio_set becomes via_vt823x_gpio_set, and now detects ISA bridge itself, in concordance with intel ich and nvidia mcp gpio. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> --- board_enable.c | 205 ++++++++++++++---------------------------------------- chipset_enable.c | 7 ++ 2 files changed, 60 insertions(+), 152 deletions(-) diff --git a/board_enable.c b/board_enable.c index 35972ab..19a77e9 100644 --- a/board_enable.c +++ b/board_enable.c @@ -162,26 +162,41 @@ static void w836xx_memw_enable(uint16_t port) } /** - * Common routine for several VT823x based boards. + * Suited for: + * - EPoX EP-8K5A2: VIA KT333 + VT8235. + * - Albatron PM266A Pro: VIA P4M266A + VT8235. + * - Shuttle AK31 (all versions): VIA KT266 + VT8233. + * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235 + * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237. */ -static void vt823x_set_all_writes_to_lpc(struct pci_dev *dev) +static int w836xx_memw_enable_2e(const char *name) { - uint8_t val; + w836xx_memw_enable(0x2E); - /* All memory cycles, not just ROM ones, go to LPC. */ - val = pci_read_byte(dev, 0x59); - val &= ~0x80; - pci_write_byte(dev, 0x59, val); + return 0; } + /** * VT823x: Set one of the GPIO pins. */ -static void vt823x_gpio_set(struct pci_dev *dev, uint8_t gpio, int raise) +static int via_vt823x_gpio_set(uint8_t gpio, int raise) { + struct pci_dev *dev; uint16_t base; uint8_t val, bit, offset; + dev = pci_dev_find_vendorclass(0x1106, 0x0601); + switch (dev->device_id) { + case 0x3177: /* VT8235 */ + case 0x3227: /* VT8237R */ + case 0x3337: /* VT8237A */ + break; + default: + fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n"); + return -1; + } + if ((gpio >= 12) && (gpio <= 15)) { /* GPIO12-15 -> output */ val = pci_read_byte(dev, 0xE4); @@ -199,7 +214,7 @@ static void vt823x_gpio_set(struct pci_dev *dev, uint8_t gpio, int raise) } else { fprintf(stderr, "\nERROR: " "VT823x GPIO%02d is not implemented.\n", gpio); - return; + return -1; } /* We need the I/O Base Address for this board's flash enable. */ @@ -214,103 +229,53 @@ static void vt823x_gpio_set(struct pci_dev *dev, uint8_t gpio, int raise) else val &= ~bit; OUTB(val, base + offset); -} - -/** - * Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs. - * - * We don't need to do this when using coreboot, GPIO15 is never lowered there. - */ -static int board_via_epia_m(const char *name) -{ - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT8235 ISA bridge not found.\n"); - return -1; - } - - /* GPIO15 is connected to write protect. */ - vt823x_gpio_set(dev, 15, 1); return 0; } /** - * Suited for: - * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235 - * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237. + * Suited for Asus M2V-MX: VIA K8M890 + VT8237A + IT8716F */ -static int board_asus_a7v8x_mx(const char *name) +static int via_vt823x_gpio5_raise(const char *name) { - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */ - if (!dev) - dev = pci_dev_find(0x1106, 0x3227); /* VT8237 ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n"); - return -1; - } - - vt823x_set_all_writes_to_lpc(dev); - w836xx_memw_enable(0x2E); - - return 0; + /* On M2V-MX: GPO5 is connected to WP# and TBL#. */ + return via_vt823x_gpio_set(5, 1); } /** - * Suited for VIAs EPIA SP and EPIA CN. + * Suited for VIAs EPIA N & NL. */ -static int board_via_epia_sp(const char *name) +static int via_vt823x_gpio9_raise(const char *name) { - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3227); /* VT8237R ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT8237R ISA bridge not found.\n"); - return -1; - } - - vt823x_set_all_writes_to_lpc(dev); - - return 0; + return via_vt823x_gpio_set(9, 1); } /** - * Suited for VIAs EPIA N & NL. + * Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs. + * + * We don't need to do this for EPIA M when using coreboot, GPIO15 is never + * lowered there. */ -static int board_via_epia_n(const char *name) +static int via_vt823x_gpio15_raise(const char *name) { - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3227); /* VT8237R ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT8237R ISA bridge not found.\n"); - return -1; - } - - /* All memory cycles, not just ROM ones, go to LPC */ - vt823x_set_all_writes_to_lpc(dev); - - /* GPIO9 -> output */ - vt823x_gpio_set(dev, 9, 1); - - return 0; + return via_vt823x_gpio_set(15, 1); } /** + * Winbond W83697HF Super I/O + VIA VT8235 southbridge + * * Suited for: - * - EPoX EP-8K5A2: VIA KT333 + VT8235. - * - Albatron PM266A Pro: VIA P4M266A + VT8235. - * - Shuttle AK31 (all versions): VIA KT266 + VT8233. + * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235 + * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235 */ -static int w836xx_memw_enable_2e(const char *name) +static int board_msi_kt4v(const char *name) { + int ret; + + ret = via_vt823x_gpio_set(12, 1); w836xx_memw_enable(0x2E); - return 0; + return ret; } /** @@ -880,6 +845,7 @@ static int board_kontron_986lcd_m(const char *name) * Suited for: * - Biostar P4M80-M4: VIA P4M800 + VT8237 + IT8705AF * - GIGABYTE GA-7VT600: VIA KT600 + VT8237 + IT8705 + * - AOpen vKM400Am-S: VIA KM400 + VT8237 + IT8705F. * * SIS950 superio probably requires the same flash write enable. */ @@ -903,49 +869,6 @@ static int it8705_rom_write_enable(const char *name) } /** - * Suited for AOpen vKM400Am-S: VIA KM400 + VT8237 + IT8705F. - */ -static int board_aopen_vkm400(const char *name) -{ - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3227); /* VT8237 ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT8237 ISA bridge not found.\n"); - return -1; - } - - vt823x_set_all_writes_to_lpc(dev); - - return it8705_rom_write_enable(name); -} - -/** - * Winbond W83697HF Super I/O + VIA VT8235 southbridge - * - * Suited for: - * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235 - * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235 - */ -static int board_msi_kt4v(const char *name) -{ - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3177); /* VT8235 ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n"); - return -1; - } - - vt823x_set_all_writes_to_lpc(dev); - - vt823x_gpio_set(dev, 12, 1); - w836xx_memw_enable(0x2E); - - return 0; -} - -/** * Suited for Soyo SY-7VCA: Pro133A + VT82C686. */ static int board_soyo_sy_7vca(const char *name) @@ -1166,26 +1089,6 @@ static int board_asus_a7v600x(const char *name) } /** - * Suited for Asus M2V-MX: VIA K8M890 + VT8237A + IT8716F - */ -static int board_asus_m2v_mx(const char *name) -{ - struct pci_dev *dev; - - dev = pci_dev_find(0x1106, 0x3337); /* VT8237A ISA bridge */ - if (!dev) { - fprintf(stderr, "\nERROR: VT8237A ISA bridge not found.\n"); - return -1; - } - - /* GPO5 is connected to WP# and TBL#. */ - vt823x_gpio_set(dev, 5, 1); - - return 0; -} - - -/** * Below is the list of boards which need a special "board enable" code in * flashrom before their ROM chip can be accessed/written to. * @@ -1219,13 +1122,13 @@ struct board_pciid_enable board_pciid_enables[] = { {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, "ASRock", "P4i65GV", intel_ich_gpio23_raise}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, "AGAMI", "ARUMA", "agami", "Aruma", w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, "Albatron", "PM266A", w836xx_memw_enable_2e}, - {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, "AOpen", "vKM400Am-S", board_aopen_vkm400}, + {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, "AOpen", "vKM400Am-S", it8705_rom_write_enable}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe61", "Artec Group", "DBE61", board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, "artecgroup", "dbe62", "Artec Group", "DBE62", board_artecgroup_dbe6x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, "ASUS", "A7V600-X", board_asus_a7v600x}, {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, "ASUS", "A7V8X", board_asus_a7v8x}, - {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8X-MX SE", board_asus_a7v8x_mx}, - {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, "ASUS", "M2V-MX", board_asus_m2v_mx}, + {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, "ASUS", "A7V8X-MX SE", w836xx_memw_enable_2e}, + {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, "ASUS", "M2V-MX", via_vt823x_gpio5_raise}, {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, "ASUS", "P4B266", intel_ich_gpio22_raise}, {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, "ASUS", "P4B266-LM", intel_ich_gpio21_raise}, {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, "ASUS", "P4P800-E Deluxe", intel_ich_gpio21_raise}, @@ -1260,11 +1163,9 @@ struct board_pciid_enable board_pciid_enables[] = { {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, "Shuttle", "FN25", board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, "Soyo", "SY-7VCA", board_soyo_sy_7vca}, - {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", board_asus_a7v8x_mx}, - {0x1106, 0x0314, 0x1106, 0xaa08, 0x1106, 0x3227, 0x1106, 0xAA08, NULL, NULL, "VIA", "EPIA-CN", board_via_epia_sp}, - {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA M/MII/...", board_via_epia_m}, - {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, "VIA", "EPIA-N/NL", board_via_epia_n}, - {0x1106, 0x3227, 0x1106, 0xAA01, 0x1106, 0x0259, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA SP", board_via_epia_sp}, + {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", w836xx_memw_enable_2e}, + {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, "VIA", "EPIA M/MII/...", via_vt823x_gpio15_raise}, + {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, "VIA", "EPIA-N/NL", via_vt823x_gpio9_raise}, {0x1106, 0x5337, 0x1458, 0xb003, 0x1106, 0x287e, 0x1106, 0x337e, NULL, NULL, "VIA", "PC3500G", it87xx_probe_spi_flash}, { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL}, /* end marker */ diff --git a/chipset_enable.c b/chipset_enable.c index 333d79d..4372872 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -603,6 +603,13 @@ static int enable_flash_vt823x(struct pci_dev *dev, const char *name) return -1; } + if (dev->device_id == 0x3227) { /* VT8237 */ + /* All memory cycles, not just ROM ones, go to LPC. */ + val = pci_read_byte(dev, 0x59); + val &= ~0x80; + pci_write_byte(dev, 0x59, val); + } + return 0; } -- 1.6.0.2 --gBBFr7Ir9EOA20Yy--

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[patch] add intel_piix4_gpo_set()
by Luc Verhaegen 14 Dec '09

14 Dec '09

This is code from a an old board enable that i sent in 3 weeks ago. This board enable was not necessary (as flashing worked just fine without it too). But this function was also used to clean up the board enable for the epox ep bx3. I have tracked down the person for whom i wrote this board enable 2 years ago: irc user nyu, aka Robert Millan. Robert, can you verify that this code is not a regression for you? Uwe, in the original mail thread (http://www.coreboot.org/pipermail/coreboot/2009-June/049789.html) you had several suggestions. I have taken over unsigned int and the bitshift, but i do mot like to put "PIIX4{,E,M}" everywhere. "PIIX4{,E,M}" all over clutters up the place, and i fear that printing this to the user will generate more confusion than it will ever remove. Instead i have adjusted the initial function comment to mention this so that developers can rest assured in future that this will also be valid for their future board enables. Luc Verhaegen.

3 9

[commit] r803 - trunk
by svn＠flashrom.org 14 Dec '09

14 Dec '09

Author: libv Date: 2009-12-14 11:41:58 +0100 (Mon, 14 Dec 2009) New Revision: 803 Modified: trunk/board_enable.c Log: Boards: Formalize intel piix4 gpo setting. The function intel_piix4_gpo_set includes proper gpo pin checking, and gpo pin enables when necessary. This is a leftover from soyo SY-6BA+III code that turned out to be unnecessary, but still used for the epox ep-bx3 board enable which it cleans up and clarifies. Difference to old code: * typical bios delay io port 0xEB now never gets touched. * pci config byte 0xB0 was not altered before. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-12-14 04:24:42 UTC (rev 802) +++ trunk/board_enable.c 2009-12-14 10:41:58 UTC (rev 803) @@ -494,25 +494,6 @@ } /** - * Suited for EPoX EP-BX3, and maybe some other Intel 440BX based boards. - */ -static int board_epox_ep_bx3(const char *name) -{ - uint8_t tmp; - - /* Raise GPIO22. */ - tmp = INB(0x4036); - OUTB(tmp, 0xEB); - - tmp |= 0x40; - - OUTB(tmp, 0x4036); - OUTB(tmp, 0xEB); - - return 0; -} - -/** * Suited for Artec Group DBE61 and DBE62. */ static int board_artecgroup_dbe6x(const char *name) @@ -554,6 +535,83 @@ } /** + * Helper function to raise/drop a given gpo line on intel PIIX4{,E,M} + */ +static int intel_piix4_gpo_set(unsigned int gpo, int raise) +{ + struct pci_dev *dev; + uint32_t tmp, base; + + dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */ + if (!dev) { + fprintf(stderr, "\nERROR: Intel PIIX4 ISA bridge not found.\n"); + return -1; + } + + /* sanity check */ + if (gpo > 30) { + fprintf(stderr, "\nERROR: Intel PIIX4 has no GPO%d.\n", gpo); + return -1; + } + + /* these are dual function pins which are most likely in use already */ + if (((gpo >= 1) && (gpo <= 7)) || + ((gpo >= 9) && (gpo <= 21)) || (gpo == 29)) { + fprintf(stderr, "\nERROR: Unsupported PIIX4 GPO%d.\n", gpo); + return -1; + } + + /* dual function that need special enable. */ + if ((gpo >= 22) && (gpo <= 26)) { + tmp = pci_read_long(dev, 0xB0); /* GENCFG */ + switch (gpo) { + case 22: /* XBUS: XDIR#/GPO22 */ + case 23: /* XBUS: XOE#/GPO23 */ + tmp |= 1 << 28; + break; + case 24: /* RTCSS#/GPO24 */ + tmp |= 1 << 29; + break; + case 25: /* RTCALE/GPO25 */ + tmp |= 1 << 30; + break; + case 26: /* KBCSS#/GPO26 */ + tmp |= 1 << 31; + break; + } + pci_write_long(dev, 0xB0, tmp); + } + + /* GPO {0,8,27,28,30} are always available. */ + + dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */ + if (!dev) { + fprintf(stderr, "\nERROR: Intel PIIX4 PM not found.\n"); + return -1; + } + + /* PM IO base */ + base = pci_read_long(dev, 0x40) & 0x0000FFC0; + + tmp = INL(base + 0x34); /* GPO register */ + if (raise) + tmp |= 0x01 << gpo; + else + tmp |= ~(0x01 << gpo); + OUTL(tmp, base + 0x34); + + return 0; +} + +/** + * Suited for EPoX EP-BX3, and maybe some other Intel 440BX based boards. + */ +static int board_epox_ep_bx3(const char *name) +{ + return intel_piix4_gpo_set(22, 1); +} + +/** * Set a GPIO line on a given intel ICH LPC controller. */ static int intel_ich_gpio_set(int gpio, int raise)

1 0

[patch] use pci_fill_info()
by Jonathan A. Kollasch 14 Dec '09

14 Dec '09

Use pci_fill_info() so device_class is valid. This is needed on NetBSD and probably other non-Linux platforms. Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> ---

2 1

[commit] r802 - trunk
by svn＠flashrom.org 14 Dec '09

14 Dec '09

Author: hailfinger Date: 2009-12-14 05:24:42 +0100 (Mon, 14 Dec 2009) New Revision: 802 Modified: trunk/board_enable.c Log: Use pci_fill_info() so device_class is valid. This is needed on NetBSD and probably other non-Linux platforms. Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-12-14 04:11:12 UTC (rev 801) +++ trunk/board_enable.c 2009-12-14 04:24:42 UTC (rev 802) @@ -605,7 +605,8 @@ int i, allowed; /* First, look for a known LPC bridge */ - for (dev = pacc->devices; dev; dev = dev->next) + for (dev = pacc->devices; dev; dev = dev->next) { + pci_fill_info(dev, PCI_FILL_CLASS); if ((dev->vendor_id == 0x8086) && (dev->device_class == 0x0601)) { /* ISA Bridge */ /* Is this device in our list? */ @@ -616,6 +617,7 @@ if (intel_ich_gpio_table[i].id) break; } + } if (!dev) { fprintf(stderr, "\nERROR: No Known Intel LPC Bridge found.\n");

1 0

ASRock M3A790GXH/128M success
by Zachary Dillard 14 Dec '09

14 Dec '09

BIOS flash successful on this motherboard ASRock M3A790GXH/128M.

3 4

[commit] r801 - trunk
by svn＠flashrom.org 14 Dec '09

14 Dec '09

Author: hailfinger Date: 2009-12-14 05:11:12 +0100 (Mon, 14 Dec 2009) New Revision: 801 Modified: trunk/print.c trunk/print_wiki.c Log: Mark ASRock M3A790GXH/128M as supported, no board enable needed. Signed-off-by: Zachary O Dillard <teathief(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/print.c =================================================================== --- trunk/print.c 2009-12-14 04:04:18 UTC (rev 800) +++ trunk/print.c 2009-12-14 04:11:12 UTC (rev 801) @@ -260,6 +260,7 @@ { "ASI", "MB-5BLMP", }, { "ASRock", "A770CrossFire", }, { "ASRock", "K8S8X", }, + { "ASRock", "M3A790GXH/128M" }, { "ASUS", "A7N8X Deluxe", }, { "ASUS", "A7N8X-E Deluxe", }, { "ASUS", "A7V400-MX", }, Modified: trunk/print_wiki.c =================================================================== --- trunk/print_wiki.c 2009-12-14 04:04:18 UTC (rev 800) +++ trunk/print_wiki.c 2009-12-14 04:11:12 UTC (rev 801) @@ -105,6 +105,7 @@ { "ASI", "MB-5BLMP", "http://www.hojerteknik.com/winnet.htm" }, { "ASRock", "A770CrossFire", "http://www.asrock.com/mb/overview.asp?Model=A770CrossFire&s=AM2\%2b" }, { "ASRock", "K8S8X", "http://www.asrock.com/mb/overview.asp?Model=K8S8X" }, + { "ASRock", "M3A790GXH/128M" "http://www.asrock.com/MB/overview.asp?Model=M3A790GXH/128M" }, { "ASUS", "A7N8X Deluxe", "http://www.asus.com/Product.aspx?P_ID=wAsRYm41KTp78MFC" }, { "ASUS", "A7N8X-E Deluxe", "http://www.asus.com/products.aspx?l1=3&l2=13&l3=56&l4=0&model=217&modelmenu…" }, { "ASUS", "A7V400-MX", "http://www.asus.com.tw/products.aspx?l1=3&l2=13&l3=63&l4=0&model=228&modelm…" },

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[PATCH] Fix eraseblock walking
by Carl-Daniel Hailfinger 14 Dec '09

14 Dec '09

Fix eraseblock walking and add a few more checks to make sure such bugs get caught in the future. I found this bug during a code review. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-blockerase_walk_fix/flashrom.c =================================================================== --- flashrom-blockerase_walk_fix/flashrom.c (Revision 769) +++ flashrom-blockerase_walk_fix/flashrom.c (Arbeitskopie) @@ -563,10 +563,11 @@ int erase_flash(struct flashchip *flash) { int i, j, k, ret = 0, found = 0; + unsigned int start, len; printf("Erasing flash chip... "); for (k = 0; k < NUM_ERASEFUNCTIONS; k++) { - unsigned long done = 0; + unsigned int done = 0; struct block_eraser eraser = flash->block_erasers[k]; printf_debug("Looking at blockwise erase function %i... ", k); @@ -594,13 +595,23 @@ * members so the loop below won't be executed for them. */ for (j = 0; j < eraser.eraseblocks[i].count; j++) { - ret = eraser.block_erase(flash, done + eraser.eraseblocks[i].size * j, eraser.eraseblocks[i].size); + start = done + eraser.eraseblocks[i].size * j; + len = eraser.eraseblocks[i].size; + printf_debug("0x%06x-0x%06x, ", start, len); + ret = eraser.block_erase(flash, start, len); if (ret) break; } if (ret) break; + done += eraser.eraseblocks[i].count * + eraser.eraseblocks[i].size; } + printf_debug("\n"); + if (done != flash->total_size * 1024) + fprintf(stderr, "ERROR: Erase region walking erased " + "0x%06x bytes total, expected 0x%06x bytes.", + done, flash->total_size * 1024); /* If everything is OK, don't try another erase function. */ if (!ret) break; -- Developer quote of the month: "We are juggling too many chainsaws and flaming arrows and tigers."

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