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Re: [flashrom] [PATCH 2/8] ichspi: disable writes when locked or read-only regions are detected
by Carl-Daniel Hailfinger 17 Sep '11

17 Sep '11

Am 20.08.2011 12:39 schrieb Stefan Tauner: > Until we are able to unlock regions or at least understand better what > consequences writing single regions have, disable writing completely > whenever a non-writeable region is detected. > > NB: the registers might not always reflect the real access status. > http://www.flashrom.org/pipermail/flashrom/2011-April/006309.html > (this is the sole such report i can remember) > --- > Might not be the best location to do this, but currently i don't recognize a better > one. The warnings are repeated for each non-writeable region. We could > surpress it by checking if programmer_may_write is already 0 before printing. > the output on my thinkpad is: > […] > Proceeding anyway because user specified laptop=force_I_want_a_brick > Found chipset "Intel QS57". Enabling flash write... WARNING: SPI Configuration Lockdown activated. > WARNING: Flash Descriptor region is read-only. Disabling writes. > WARNING: Management Engine region is locked. Disabling writes. > OK. > This chipset supports the following protocols: FWH, SPI. > Found Winbond flash chip "W25X64" (8192 kB, SPI) at physical address 0xff800000. > […] > > verbose output is: > […] > 0x54: 0x00000000 (FREG0: Flash Descriptor) > 0x00000000-0x00000fff is read-only > WARNING: Flash Descriptor region is read-only. Disabling writes. > 0x58: 0x07ff0500 (FREG1: BIOS) > 0x00500000-0x007fffff is read-write > 0x5C: 0x04ff0003 (FREG2: Management Engine) > 0x00003000-0x004fffff is locked > WARNING: Management Engine region is locked. Disabling writes. > 0x60: 0x00020001 (FREG3: Gigabit Ethernet) > 0x00001000-0x00002fff is read-write > 0x64: 0x00000fff (FREG4: Platform Data) > Platform Data region is unused. > […] > > i think that is ok. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> with two comments, see below. > diff --git a/ichspi.c b/ichspi.c > index 09af2b3..343a0af 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -1168,6 +1168,15 @@ static void do_ich9_spi_frap(uint32_t frap, int i) > > msg_pdbg("0x%08x-0x%08x is %s\n", base, (limit | 0x0fff), > access_names[rwperms]); > + if (rwperms <= 0x1) { > Please make sure that this doesn't trigger for unused regions. > + msg_pinfo("WARNING: %s region is %s. Disabling writes.\n", > + region_names[i], access_names[rwperms]); > + /* FIXME: This needs some refinement when we know how unlocking > + * of region works. > + */ > + programmer_may_write = 0; > + } > + > } > > static const struct spi_programmer spi_programmer_ich7 = { > How do we handle chips where a part of the chip is not part of any region? What does the hardware enforce in that situation? Regards, Carl-Daniel -- http://www.hailfinger.org/

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Silicon Image SiI 3124 PCI-X SATA Ctrl
by Patrick Welche 16 Sep '11

16 Sep '11

I have two SiI3124 SATALink based PCI cards, which are essentially the same except one is older than the other. The cards are both Found "Silicon Image SiI 3124 PCI-X SATA Ctrl" (1095:3124, BDF 02:0a.0) the old one, which I will call 649 because of its firmware revision 6.4.09 has a Found PMC flash chip "Pm39LV010" (128 kB, Parallel) on satasii. This flash part has status UNTESTED for operations: WRITE The new one, which I will call 660 because of its firmware revision 6.6.0 has a Found PMC flash chip "Pm39LV040" (512 kB, Parallel) on satasii. This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE I just successfully read 660, compared it the file I downloaded from the manufacturer (b6600.bin in SiI3124__6600.zip), and wrote said file to 649 successfully. (and disks plugged in can be read) logs attached: read.649 (reading from 649) read.660 (reading from 660) write (writing to 649) Cheers, Patrick

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Re: [flashrom] [PATCH] ichspi: add ICH/PCH flash descriptor decoding via FDOC/FDOD
by Carl-Daniel Hailfinger 16 Sep '11

16 Sep '11

Am 15.09.2011 00:53 schrieb Stefan Tauner: > based on the work of Matthias 'mazzoo' Wenzel this patch adds pretty > printing of those ICH/PCH flash descriptor sections that are > cached/mapped by the chipset (and which are therefore reachable via > FDOC/FDOD registers). > > this includes the following: > - content section: > describes the image and some generic properties (number of > sections, offset of sections, PCH/ICH and MCH/PROC strap > offsets and lengths) > - component section: > identify the different SPI flash chips and their capabilities. > - region section > similarly to a partition table this describes the different regions. > the content of FLREG* is derived from this section. > - master section > defines SPI master (host, ME, GbE) access rights of the > individual regions. the content of PR* is derived from this section. > > this is only a part of the data included in the descriptor. other > information can be retrieved from a complete binary dump of the > descriptor region only. > > this patch also adds macros and pretty printing for "Vendor Specific > Component Capabilities" registers: there are two of them: lower and > upper. they describe the properties of the address space divided by > FPBA (which allows to use multiple flash chips or partitions with > different properties). the properties of all supported flash chips > (together with their RDIDs) are stored in the same format in table > in a descriptor section (which is used by the ME apparently). a > later patch will use the macros outside of ichspi.c which is the > reason why the prettyprinting function and the register bit macros > are not defined in ichspi.c but ich_descriptors.h (else they would > be moved in the follow-up patch). > > because this patch relies on (compiler) implementation-specific > layouting of bit-fields, it checks for correct layout before taking > any action on runtime. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Get it in! Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> with small comments. > this is the version without the compile-time checks as requested by carldani. > > Makefile | 3 +- > ich_descriptors.c | 286 +++++++++++++++++++++++++++++++++++++++++++++++++++++ > ich_descriptors.h | 259 ++++++++++++++++++++++++++++++++++++++++++++++++ > ichspi.c | 58 +++++++++-- > 4 files changed, 594 insertions(+), 12 deletions(-) > create mode 100644 ich_descriptors.c > create mode 100644 ich_descriptors.h > > diff --git a/Makefile b/Makefile > index 6407e6b..4a8dc2c 100644 > --- a/Makefile > +++ b/Makefile > @@ -349,7 +349,8 @@ ifeq ($(CONFIG_INTERNAL), yes) > FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' > PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o > ifeq ($(ARCH),"x86") > -PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o > +PROGRAMMER_OBJS += it87spi.o it85spi.o sb600spi.o wbsio_spi.o mcp6x_spi.o > +PROGRAMMER_OBJS += ichspi.o ich_descriptors.o > else > endif > NEED_PCI := yes > diff --git a/ich_descriptors.c b/ich_descriptors.c > new file mode 100644 > index 0000000..4ab2602 > --- /dev/null > +++ b/ich_descriptors.c > @@ -0,0 +1,286 @@ > +/* > + * This file is part of the flashrom project. > + * > + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> > + * Copyright (c) 2011 Stefan Tauner > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + */ > + > +#if defined(__i386__) || defined(__x86_64__) > + > +#include "ich_descriptors.h" > +#include "flash.h" /* for msg_* */ > +#include "programmer.h" > + > +void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity) > +{ > + print(verbosity, "BES=0x%x, ", (reg_val & VSCC_BES) >> VSCC_BES_OFF); > + print(verbosity, "WG=%d, ", (reg_val & VSCC_WG) >> VSCC_WG_OFF); > + print(verbosity, "WSR=%d, ", (reg_val & VSCC_WSR) >> VSCC_WSR_OFF); > + print(verbosity, "WEWS=%d, ", (reg_val & VSCC_WEWS) >> VSCC_WEWS_OFF); > + print(verbosity, "EO=0x%x, ", (reg_val & VSCC_EO) >> VSCC_EO_OFF); > + print(verbosity, "VCL=%d\n", (reg_val & VSCC_VCL) >> VSCC_VCL_OFF); > +} > + > +#define getFCBA(cont) (((cont)->FLMAP0 << 4) & 0x00000ff0) > +#define getFRBA(cont) (((cont)->FLMAP0 >> 12) & 0x00000ff0) > +#define getFMBA(cont) (((cont)->FLMAP1 << 4) & 0x00000ff0) > +#define getFISBA(cont) (((cont)->FLMAP1 >> 12) & 0x00000ff0) > +#define getFMSBA(cont) (((cont)->FLMAP2 << 4) & 0x00000ff0) > + > +void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc) > +{ > + prettyprint_ich_descriptor_content(&desc->content); > + prettyprint_ich_descriptor_component(desc); > + prettyprint_ich_descriptor_region(desc); > + prettyprint_ich_descriptor_master(&desc->master); > +} > + > +void prettyprint_ich_descriptor_content(const struct ich_desc_content *cont) > +{ > + msg_pdbg2("=== Content Section ===\n"); > + msg_pdbg2("FLVALSIG 0x%08x\n", cont->FLVALSIG); > + msg_pdbg2("FLMAP0 0x%08x\n", cont->FLMAP0); > + msg_pdbg2("FLMAP1 0x%08x\n", cont->FLMAP1); > + msg_pdbg2("FLMAP2 0x%08x\n", cont->FLMAP2); > + msg_pdbg2("\n"); > + > + msg_pdbg2("--- Details ---\n"); > + msg_pdbg2("NR (Number of Regions): %5d\n", > + cont->NR + 1); > + msg_pdbg2("FRBA (Flash Region Base Address): 0x%03x\n", > + getFRBA(cont)); > + msg_pdbg2("NC (Number of Components): %5d\n", > + cont->NC + 1); > + msg_pdbg2("FCBA (Flash Component Base Address): 0x%03x\n", > + getFCBA(cont)); > + msg_pdbg2("ISL (ICH/PCH Strap Length): %5d\n", > + cont->ISL); > + msg_pdbg2("FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x%03x\n", > + getFISBA(cont)); > + msg_pdbg2("NM (Number of Masters): %5d\n", > + cont->NM + 1); > + msg_pdbg2("FMBA (Flash Master Base Address): 0x%03x\n", > + getFMBA(cont)); > + msg_pdbg2("MSL/PSL (MCH/PROC Strap Length): %5d\n", > + cont->MSL); > + msg_pdbg2("FMSBA (Flash MCH/PROC Strap Base Address): 0x%03x\n", > + getFMSBA(cont)); > + msg_pdbg2("\n"); > +} > + > +void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc) > +{ > + static const char * const str_freq[8] = { maybe freq_name or freq_str? > + "20 MHz", /* 000 */ > + "33 MHz", /* 001 */ > + "reserved", /* 010 */ > + "reserved", /* 011 */ > + "50 MHz", /* 100 */ > + "reserved", /* 101 */ > + "reserved", /* 110 */ > + "reserved" /* 111 */ > + }; > + static const char * const str_mem[8] = { Maybe size_name or size_str? > + "512 kB", /* 000 */ > + " 1 MB", /* 001 */ > + " 2 MB", /* 010 */ > + " 4 MB", /* 011 */ > + " 8 MB", /* 100 */ > + " 16 MB", /* 101 */ > + "reserved", /* 110 */ > + "reserved", /* 111 */ > + }; > + > + msg_pdbg2("=== Component Section ===\n"); > + msg_pdbg2("FLCOMP 0x%08x\n", desc->component.FLCOMP); > + msg_pdbg2("FLILL 0x%08x\n", desc->component.FLILL ); > + msg_pdbg2("\n"); > + > + msg_pdbg2("--- Details ---\n"); > + msg_pdbg2("Component 1 density: %s\n", > + str_mem[desc->component.comp1_density]); > + if (desc->content.NC) > + msg_pdbg2("Component 2 density: %s\n", > + str_mem[desc->component.comp2_density]); > + else > + msg_pdbg2("Component 2 is not used.\n"); > + msg_pdbg2("Read Clock Frequency: %s\n", > + str_freq[desc->component.freq_read]); > + msg_pdbg2("Read ID and Status Clock Freq.: %s\n", > + str_freq[desc->component.freq_read_id]); > + msg_pdbg2("Write and Erase Clock Freq.: %s\n", > + str_freq[desc->component.freq_write]); > + msg_pdbg2("Fast Read is %ssupported.\n", > + desc->component.fastread ? "" : "not "); Not something you have to change, but maybe we should store that information about fast read capability somewhere. > + if (desc->component.fastread) > + msg_pdbg2("Fast Read Clock Frequency: %s\n", > + str_freq[desc->component.freq_fastread]); > + if (desc->component.FLILL == 0) > + msg_pdbg2("No forbidden opcodes.\n"); > + else { > + msg_pdbg2("Invalid instruction 0: 0x%02x\n", > + desc->component.invalid_instr0); > + msg_pdbg2("Invalid instruction 1: 0x%02x\n", > + desc->component.invalid_instr1); > + msg_pdbg2("Invalid instruction 2: 0x%02x\n", > + desc->component.invalid_instr2); > + msg_pdbg2("Invalid instruction 3: 0x%02x\n", > + desc->component.invalid_instr3); > + } > + msg_pdbg2("\n"); > +} > + > +static void pprint_freg(const struct ich_desc_region *reg, uint32_t i) > +{ > + static const char *const region_names[5] = { > + "Descr.", "BIOS", "ME", "GbE", "Platf." > + }; > + if (i >= 5) { > + msg_pdbg2("%s: region index too high.\n", __func__); > + return; > + } > + uint32_t base = ICH_FREG_BASE(reg->FLREGs[i]); > + uint32_t limit = ICH_FREG_LIMIT(reg->FLREGs[i]); > + msg_pdbg2("Region %d (%-6s) ", i, region_names[i]); > + if (base > limit) > + msg_pdbg2("is unused.\n"); > + else > + msg_pdbg2("0x%08x - 0x%08x\n", base, limit | 0x0fff); > +} > + > +void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc) > +{ > + uint8_t i; > + uint8_t nr = desc->content.NR + 1; > + msg_pdbg2("=== Region Section ===\n"); > + if (nr >= 5) { > + msg_pdbg2("%s: number of regions too high (%d).\n", __func__, > + nr); > + return; > + } > + for (i = 0; i <= nr; i++) > + msg_pdbg2("FLREG%d 0x%08x\n", i, desc->region.FLREGs[i]); > + msg_pdbg2("\n"); > + > + msg_pdbg2("--- Details ---\n"); > + for (i = 0; i <= nr; i++) > + pprint_freg(&desc->region, i); > + msg_pdbg2("\n"); > +} > + > +void prettyprint_ich_descriptor_master(const struct ich_desc_master *mstr) > +{ > + msg_pdbg2("=== Master Section ===\n"); > + msg_pdbg2("FLMSTR1 0x%08x\n", mstr->FLMSTR1); > + msg_pdbg2("FLMSTR2 0x%08x\n", mstr->FLMSTR2); > + msg_pdbg2("FLMSTR3 0x%08x\n", mstr->FLMSTR3); > + msg_pdbg2("\n"); > + > + msg_pdbg2("--- Details ---\n"); > + msg_pdbg2(" Descr. BIOS ME GbE Platf.\n"); > + msg_pdbg2("BIOS %c%c %c%c %c%c %c%c %c%c\n", > + (mstr->BIOS_descr_r) ?'r':' ', (mstr->BIOS_descr_w) ?'w':' ', > + (mstr->BIOS_BIOS_r) ?'r':' ', (mstr->BIOS_BIOS_w) ?'w':' ', > + (mstr->BIOS_ME_r) ?'r':' ', (mstr->BIOS_ME_w) ?'w':' ', > + (mstr->BIOS_GbE_r) ?'r':' ', (mstr->BIOS_GbE_w) ?'w':' ', > + (mstr->BIOS_plat_r) ?'r':' ', (mstr->BIOS_plat_w) ?'w':' '); > + msg_pdbg2("ME %c%c %c%c %c%c %c%c %c%c\n", > + (mstr->ME_descr_r) ?'r':' ', (mstr->ME_descr_w) ?'w':' ', > + (mstr->ME_BIOS_r) ?'r':' ', (mstr->ME_BIOS_w) ?'w':' ', > + (mstr->ME_ME_r) ?'r':' ', (mstr->ME_ME_w) ?'w':' ', > + (mstr->ME_GbE_r) ?'r':' ', (mstr->ME_GbE_w) ?'w':' ', > + (mstr->ME_plat_r) ?'r':' ', (mstr->ME_plat_w) ?'w':' '); > + msg_pdbg2("GbE %c%c %c%c %c%c %c%c %c%c\n", > + (mstr->GbE_descr_r) ?'r':' ', (mstr->GbE_descr_w) ?'w':' ', > + (mstr->GbE_BIOS_r) ?'r':' ', (mstr->GbE_BIOS_w) ?'w':' ', > + (mstr->GbE_ME_r) ?'r':' ', (mstr->GbE_ME_w) ?'w':' ', > + (mstr->GbE_GbE_r) ?'r':' ', (mstr->GbE_GbE_w) ?'w':' ', > + (mstr->GbE_plat_r) ?'r':' ', (mstr->GbE_plat_w) ?'w':' '); > + msg_pdbg2("\n"); > +} > + > +static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) > +{ > + uint32_t control = 0; > + control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS; > + control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI; > + mmio_le_writel(control, spibar + ICH9_REG_FDOC); > + return mmio_le_readl(spibar + ICH9_REG_FDOD); > +} > + > +int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc) > +{ > + uint8_t i; > + uint8_t nr; > + struct ich_desc_region *r = &desc->region; > + > + /* Test if bit-fields are working as expected */ > + for (i = 0; i < 4; i++) > + desc->region.FLREGs[i] = 0x5A << (i * 8); > + if (r->reg0_base != 0x005A || r->reg0_limit != 0x0000 || > + r->reg1_base != 0x1A00 || r->reg1_limit != 0x0000 || > + r->reg2_base != 0x0000 || r->reg2_limit != 0x005A || > + r->reg3_base != 0x0000 || r->reg3_limit != 0x1A00) { > + msg_pdbg("The combination of compiler and CPU architecture used" > + "does not lay out bit-fields as expected, sorry.\n"); > + msg_pspew("r->reg0_base = 0x%04X (0x005A)\n", r->reg0_base); > + msg_pspew("r->reg0_limit = 0x%04X (0x0000)\n", r->reg0_limit); > + msg_pspew("r->reg1_base = 0x%04X (0x1A00)\n", r->reg1_base); > + msg_pspew("r->reg1_limit = 0x%04X (0x0000)\n", r->reg1_limit); > + msg_pspew("r->reg2_base = 0x%04X (0x0000)\n", r->reg2_base); > + msg_pspew("r->reg2_limit = 0x%04X (0x005A)\n", r->reg2_limit); > + msg_pspew("r->reg3_base = 0x%04X (0x0000)\n", r->reg3_base); > + msg_pspew("r->reg3_limit = 0x%04X (0x1A00)\n", r->reg3_limit); > + return RET_ERR; > + } Hm. Having the block above in a separate function would be nice, but if you add a short /* FIXME: Replace this with dynamic bitfield fixup */ comment, that would be totally OK for me (and the pending patch queue would be a lot shorter). > + > + msg_pdbg2("Reading flash descriptors " > + "mapped by the chipset via FDOC/FDOD..."); > + /* content section */ > + desc->content.FLVALSIG = read_descriptor_reg(0, 0, spibar); > + desc->content.FLMAP0 = read_descriptor_reg(0, 1, spibar); > + desc->content.FLMAP1 = read_descriptor_reg(0, 2, spibar); > + desc->content.FLMAP2 = read_descriptor_reg(0, 3, spibar); > + > + /* component section */ > + desc->component.FLCOMP = read_descriptor_reg(1, 0, spibar); > + desc->component.FLILL = read_descriptor_reg(1, 1, spibar); > + desc->component.FLPB = read_descriptor_reg(1, 2, spibar); > + > + /* region section */ > + nr = desc->content.NR + 1; > + if (nr >= 5) { > + msg_pdbg2("%s: number of regions too high (%d) - failed\n", > + __func__, nr); > + return RET_ERR; > + } > + for (i = 0; i <= nr; i++) > + desc->region.FLREGs[i] = read_descriptor_reg(2, i, spibar); > + > + /* master section */ > + desc->master.FLMSTR1 = read_descriptor_reg(3, 0, spibar); > + desc->master.FLMSTR2 = read_descriptor_reg(3, 1, spibar); > + desc->master.FLMSTR3 = read_descriptor_reg(3, 2, spibar); > + > + /* Accessing the strap section via FDOC/D is only possible on ICH8 and > + * reading the upper map is impossible on all chipsets, so don't bother. Interesting. So Intel removed that capability on ICH9 and later? > + */ > + > + msg_pdbg2(" done.\n"); > + return RET_OK; > +} > +#endif /* defined(__i386__) || defined(__x86_64__) */ > diff --git a/ich_descriptors.h b/ich_descriptors.h > new file mode 100644 > index 0000000..098d3cd > --- /dev/null > +++ b/ich_descriptors.h > @@ -0,0 +1,259 @@ > +/* > + * This file is part of the flashrom project. > + * > + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> > + * Copyright (c) 2011 Stefan Tauner > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + */ > + > +#if defined(__i386__) || defined(__x86_64__) > +#ifndef __ICH_DESCRIPTORS_H__ > +#define __ICH_DESCRIPTORS_H__ 1 > + > +#include <stdint.h> > + > +#define RET_OK 0 > +#define RET_ERR -1 > +#define RET_WARN -2 > +#define RET_PARAM -3 > +#define RET_OOB -4 Argl... If you add a comment /* FIXME: Replace with generic return codes */ that's OK for me now. > + > +#define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */ > + /* 0-1: reserved */ > +#define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */ > +#define FDOC_FDSI (0x3f << FDOC_FDSI_OFF) > +#define FDOC_FDSS_OFF 12 /* 12-14: Flash Descriptor Section Select */ > +#define FDOC_FDSS (0x3 << FDOC_FDSS_OFF) > + /* 15-31: reserved */ > + > +#define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */ > + > +/* Field locations and semantics for LVSCC, UVSCC and related words in the flash > + * descriptor are equal therefore they all share the same macros below. */ > +#define VSCC_BES_OFF 0 /* 0-1: Block/Sector Erase Size */ > +#define VSCC_BES (0x3 << VSCC_BES_OFF) > +#define VSCC_WG_OFF 2 /* 2: Write Granularity */ > +#define VSCC_WG (0x1 << VSCC_WG_OFF) > +#define VSCC_WSR_OFF 3 /* 3: Write Status Required */ > +#define VSCC_WSR (0x1 << VSCC_WSR_OFF) > +#define VSCC_WEWS_OFF 4 /* 4: Write Enable on Write Status */ > +#define VSCC_WEWS (0x1 << VSCC_WEWS_OFF) > + /* 5-7: reserved */ > +#define VSCC_EO_OFF 8 /* 8-15: Erase Opcode */ > +#define VSCC_EO (0xff << VSCC_EO_OFF) > + /* 16-22: reserved */ > +#define VSCC_VCL_OFF 23 /* 23: Vendor Component Lock */ > +#define VSCC_VCL (0x1 << VSCC_VCL_OFF) > + /* 24-31: reserved */ > + > +#define ICH_FREG_BASE(flreg) (((flreg) << 12) & 0x01fff000) > +#define ICH_FREG_LIMIT(flreg) (((flreg) >> 4) & 0x01fff000) Are you sure all users of ICH_FREG_{BASE,LIMIT} have been adjusted to the new definition, especially in ichspi.c and elsewhere? > + > +/* Used to select the right descriptor printing function. > + * Currently only ICH8 and Ibex Peak are supported. > + */ > +enum ich_chipset { > + CHIPSET_ICH_UNKNOWN, > + CHIPSET_ICH7 = 7, > + CHIPSET_ICH8, > + CHIPSET_ICH9, > + CHIPSET_ICH10, > + CHIPSET_5_SERIES_IBEX_PEAK, > + CHIPSET_6_SERIES_COUGAR_POINT, > + CHIPSET_7_SERIES_PANTHER_POINT > +}; > + > +void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity); > + > +struct ich_desc_content { > + uint32_t FLVALSIG; /* 0x00 */ > + union { /* 0x04 */ > + uint32_t FLMAP0; > + struct { > + uint32_t FCBA :8, /* Flash Component Base Address */ > + NC :2, /* Number Of Components */ > + :6, > + FRBA :8, /* Flash Region Base Address */ > + NR :3, /* Number Of Regions */ > + :5; > + }; > + }; > + union { /* 0x08 */ > + uint32_t FLMAP1; > + struct { > + uint32_t FMBA :8, /* Flash Master Base Address */ > + NM :3, /* Number Of Masters */ > + :5, > + FISBA :8, /* Flash ICH Strap Base Address */ > + ISL :8; /* ICH Strap Length */ > + }; > + }; > + union { /* 0x0c */ > + uint32_t FLMAP2; > + struct { > + uint32_t FMSBA :8, /* Flash (G)MCH Strap Base Addr. */ > + MSL :8, /* MCH Strap Length */ > + :16; > + }; > + }; > +}; > + > +struct ich_desc_component { > + union { /* 0x00 */ > + uint32_t FLCOMP; /* Flash Components Register */ > + struct { > + uint32_t comp1_density :3, > + comp2_density :3, > + :11, > + freq_read :3, > + fastread :1, > + freq_fastread :3, > + freq_write :3, > + freq_read_id :3, > + :2; > + }; > + }; > + union { /* 0x04 */ > + uint32_t FLILL; /* Flash Invalid Instructions Register */ > + struct { > + uint32_t invalid_instr0 :8, > + invalid_instr1 :8, > + invalid_instr2 :8, > + invalid_instr3 :8; > + }; > + }; > + union { /* 0x08 */ > + uint32_t FLPB; /* Flash Partition Boundary Register */ > + struct { > + uint32_t FPBA :13, /* Flash Partition Boundary Addr */ > + :19; > + }; > + }; > +}; > + > +struct ich_desc_region { > + union { > + uint32_t FLREGs[5]; > + struct { > + struct { /* FLREG0 Flash Descriptor */ > + uint32_t reg0_base :13, > + :3, > + reg0_limit :13, > + :3; > + }; > + struct { /* FLREG1 BIOS */ > + uint32_t reg1_base :13, > + :3, > + reg1_limit :13, > + :3; > + }; > + struct { /* FLREG2 ME */ > + uint32_t reg2_base :13, > + :3, > + reg2_limit :13, > + :3; > + }; > + struct { /* FLREG3 GbE */ > + uint32_t reg3_base :13, > + :3, > + reg3_limit :13, > + :3; > + }; > + struct { /* FLREG4 Platform */ > + uint32_t reg4_base :13, > + :3, > + reg4_limit :13, > + :3; > + }; > + }; > + }; > +}; > + > +struct ich_desc_master { > + union { > + uint32_t FLMSTR1; > + struct { > + uint32_t BIOS_req_ID :16, > + BIOS_descr_r :1, > + BIOS_BIOS_r :1, > + BIOS_ME_r :1, > + BIOS_GbE_r :1, > + BIOS_plat_r :1, > + :3, > + BIOS_descr_w :1, > + BIOS_BIOS_w :1, > + BIOS_ME_w :1, > + BIOS_GbE_w :1, > + BIOS_plat_w :1, > + :3; > + }; > + }; > + union { > + uint32_t FLMSTR2; > + struct { > + uint32_t ME_req_ID :16, > + ME_descr_r :1, > + ME_BIOS_r :1, > + ME_ME_r :1, > + ME_GbE_r :1, > + ME_plat_r :1, > + :3, > + ME_descr_w :1, > + ME_BIOS_w :1, > + ME_ME_w :1, > + ME_GbE_w :1, > + ME_plat_w :1, > + :3; > + }; > + }; > + union { > + uint32_t FLMSTR3; > + struct { > + uint32_t GbE_req_ID :16, > + GbE_descr_r :1, > + GbE_BIOS_r :1, > + GbE_ME_r :1, > + GbE_GbE_r :1, > + GbE_plat_r :1, > + :3, > + GbE_descr_w :1, > + GbE_BIOS_w :1, > + GbE_ME_w :1, > + GbE_GbE_w :1, > + GbE_plat_w :1, > + :3; > + }; > + }; > +}; I once complained about the size of one of the bitfields in this file, but I don't remember if you fixed that. Can you verify? > + > +struct ich_descriptors { > + struct ich_desc_content content; > + struct ich_desc_component component; > + struct ich_desc_region region; > + struct ich_desc_master master; > +}; > + > +void prettyprint_ich_descriptors(enum ich_chipset, const struct ich_descriptors *desc); > + > +void prettyprint_ich_descriptor_content(const struct ich_desc_content *content); > +void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc); > +void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc); > +void prettyprint_ich_descriptor_master(const struct ich_desc_master *master); > + > +int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc); > + > +#endif /* __ICH_DESCRIPTORS_H__ */ > +#endif /* defined(__i386__) || defined(__x86_64__) */ > diff --git a/ichspi.c b/ichspi.c > index 8b4210e..ad0b536 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -29,6 +29,7 @@ > #include "flash.h" > #include "programmer.h" > #include "spi.h" > +#include "ich_descriptors.h" > > /* ICH9 controller register definition */ > #define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ > @@ -119,6 +120,16 @@ > #define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */ > #define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */ > > +#define ICH8_REG_VSCC 0xC1 /* 32 Bits Vendor Specific Component Capabilities */ > +#define ICH9_REG_LVSCC 0xC4 /* 32 Bits Host Lower Vendor Specific Component Capabilities */ > +#define ICH9_REG_UVSCC 0xC8 /* 32 Bits Host Upper Vendor Specific Component Capabilities */ > +/* The individual fields of the VSCC registers are defined in the file > + * ich_descriptors.h. The reason is that the same layout is also used in the > + * flash descriptor to define the properties of the different flash chips > + * supported. The BIOS (or the ME?) is responsible to populate the ICH registers > + * with the information from the descriptor on startup depending on the actual > + * chip(s) detected. */ > + > #define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */ > #define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */ > #define FPB_FPBA (0x1FFF << FPB_FPBA_OFF) > @@ -1129,9 +1140,6 @@ static int ich_spi_send_multicommand(struct spi_command *cmds) > #define ICH_BRWA(x) ((x >> 8) & 0xff) > #define ICH_BRRA(x) ((x >> 0) & 0xff) > > -#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff) > -#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff) > - > static void do_ich9_spi_frap(uint32_t frap, int i) > { > static const char *const access_names[4] = { > @@ -1158,9 +1166,8 @@ static void do_ich9_spi_frap(uint32_t frap, int i) > return; > } > > - msg_pdbg("0x%08x-0x%08x is %s\n", > - (base << 12), (limit << 12) | 0x0fff, > - access_names[rwperms]); > + msg_pdbg("0x%08x-0x%08x is %s\n", base, (limit | 0x0fff), > + access_names[rwperms]); Can you recheck this change? Looks odd. > } > > static const struct spi_programmer spi_programmer_ich7 = { > @@ -1190,6 +1197,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > uint8_t old, new; > uint16_t spibar_offset, tmp2; > uint32_t tmp; > + int ichspi_desc = 0; > > switch (ich_generation) { > case 7: > @@ -1261,6 +1269,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); > ichspi_lock = 1; > } > + if (tmp2 & HSFS_FDV) > + ichspi_desc = 1; > > tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); > msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); > @@ -1308,12 +1318,38 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > mmio_readl(ich_spibar + ICH9_REG_OPMENU)); > msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", > mmio_readl(ich_spibar + ICH9_REG_OPMENU + 4)); > - ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); > - msg_pdbg("0xA0: 0x%08x (BBAR)\n", > - ichspi_bbar); > - tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); > - msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); > + if (ich_generation == 8) { > + tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC); > + msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp); > + msg_pdbg("VSCC: "); > + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); > + } else { > + ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); > + msg_pdbg("0xA0: 0x%08x (BBAR)\n", > + ichspi_bbar); > + > + tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); > + msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); > + msg_pdbg("LVSCC: "); > + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); > + > + tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); > + msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); > + msg_pdbg("UVSCC: "); > + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); > + > + tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); > + msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); > + } Didn't see that flash descriptor override is printed anywhere... you once described its effect in detail and that description would be really nice to have in ichspi.c, maybe even with a flag which tells flashrom about the effect (access control disabled or whatever it was). > > + msg_pdbg("\n"); > + if (ichspi_desc) { > + struct ich_descriptors desc = {{ 0 }}; > + if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == > + RET_OK) > + prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, > + &desc); > + } > ich_init_opcodes(); > break; > default: Thanks a lot for reworking this patch so often! Regards, Carl-Daniel -- http://www.hailfinger.org/

2 2

[commit] r1443 - trunk
by repository service 16 Sep '11

16 Sep '11

Author: stefanct Date: Fri Sep 16 01:52:55 2011 New Revision: 1443 URL: http://flashrom.org/trac/flashrom/changeset/1443 Log: ichspi: add ICH/PCH flash descriptor decoding via FDOC/FDOD based on the work of Matthias 'mazzoo' Wenzel this patch adds pretty printing of those ICH/PCH flash descriptor sections that are cached/mapped by the chipset (and which are therefore reachable via FDOC/FDOD registers). this includes the following: - content section: describes the image and some generic properties (number of sections, offset of sections, PCH/ICH and MCH/PROC strap offsets and lengths) - component section: identify the different SPI flash chips and their capabilities. - region section similarly to a partition table this describes the different regions. the content of FLREG* is derived from this section. - master section defines SPI master (host, ME, GbE) access rights of the individual regions. the content of PR* is derived from this section. this is only a part of the data included in the descriptor. other information can be retrieved from a complete binary dump of the descriptor region only. this patch also adds macros and pretty printing for "Vendor Specific Component Capabilities" registers: there are two of them: lower and upper. they describe the properties of the address space divided by FPBA (which allows to use multiple flash chips or partitions with different properties). the properties of all supported flash chips (together with their RDIDs) are stored in the same format in table in a descriptor section (which is used by the ME apparently). a later patch will use the macros outside of ichspi.c which is the reason why the prettyprinting function and the register bit macros are not defined in ichspi.c but ich_descriptors.h (else they would be moved in the follow-up patch). because this patch relies on (compiler) implementation-specific layouting of bit-fields, it checks for correct layout before taking any action on runtime. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Added: trunk/ich_descriptors.c (contents, props changed) trunk/ich_descriptors.h (contents, props changed) Modified: trunk/Makefile trunk/ichspi.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Fri Sep 16 01:38:14 2011 (r1442) +++ trunk/Makefile Fri Sep 16 01:52:55 2011 (r1443) @@ -349,7 +349,8 @@ FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o ifeq ($(ARCH),"x86") -PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += it87spi.o it85spi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += ichspi.o ich_descriptors.o else endif NEED_PCI := yes Added: trunk/ich_descriptors.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/ich_descriptors.c Fri Sep 16 01:52:55 2011 (r1443) @@ -0,0 +1,288 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (c) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if defined(__i386__) || defined(__x86_64__) + +#include "ich_descriptors.h" +#include "flash.h" /* for msg_* */ +#include "programmer.h" + +void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity) +{ + print(verbosity, "BES=0x%x, ", (reg_val & VSCC_BES) >> VSCC_BES_OFF); + print(verbosity, "WG=%d, ", (reg_val & VSCC_WG) >> VSCC_WG_OFF); + print(verbosity, "WSR=%d, ", (reg_val & VSCC_WSR) >> VSCC_WSR_OFF); + print(verbosity, "WEWS=%d, ", (reg_val & VSCC_WEWS) >> VSCC_WEWS_OFF); + print(verbosity, "EO=0x%x, ", (reg_val & VSCC_EO) >> VSCC_EO_OFF); + print(verbosity, "VCL=%d\n", (reg_val & VSCC_VCL) >> VSCC_VCL_OFF); +} + +#define getFCBA(cont) (((cont)->FLMAP0 << 4) & 0x00000ff0) +#define getFRBA(cont) (((cont)->FLMAP0 >> 12) & 0x00000ff0) +#define getFMBA(cont) (((cont)->FLMAP1 << 4) & 0x00000ff0) +#define getFISBA(cont) (((cont)->FLMAP1 >> 12) & 0x00000ff0) +#define getFMSBA(cont) (((cont)->FLMAP2 << 4) & 0x00000ff0) + +void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc) +{ + prettyprint_ich_descriptor_content(&desc->content); + prettyprint_ich_descriptor_component(desc); + prettyprint_ich_descriptor_region(desc); + prettyprint_ich_descriptor_master(&desc->master); +} + +void prettyprint_ich_descriptor_content(const struct ich_desc_content *cont) +{ + msg_pdbg2("=== Content Section ===\n"); + msg_pdbg2("FLVALSIG 0x%08x\n", cont->FLVALSIG); + msg_pdbg2("FLMAP0 0x%08x\n", cont->FLMAP0); + msg_pdbg2("FLMAP1 0x%08x\n", cont->FLMAP1); + msg_pdbg2("FLMAP2 0x%08x\n", cont->FLMAP2); + msg_pdbg2("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2("NR (Number of Regions): %5d\n", + cont->NR + 1); + msg_pdbg2("FRBA (Flash Region Base Address): 0x%03x\n", + getFRBA(cont)); + msg_pdbg2("NC (Number of Components): %5d\n", + cont->NC + 1); + msg_pdbg2("FCBA (Flash Component Base Address): 0x%03x\n", + getFCBA(cont)); + msg_pdbg2("ISL (ICH/PCH Strap Length): %5d\n", + cont->ISL); + msg_pdbg2("FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x%03x\n", + getFISBA(cont)); + msg_pdbg2("NM (Number of Masters): %5d\n", + cont->NM + 1); + msg_pdbg2("FMBA (Flash Master Base Address): 0x%03x\n", + getFMBA(cont)); + msg_pdbg2("MSL/PSL (MCH/PROC Strap Length): %5d\n", + cont->MSL); + msg_pdbg2("FMSBA (Flash MCH/PROC Strap Base Address): 0x%03x\n", + getFMSBA(cont)); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc) +{ + static const char * const freq_str[8] = { + "20 MHz", /* 000 */ + "33 MHz", /* 001 */ + "reserved", /* 010 */ + "reserved", /* 011 */ + "50 MHz", /* 100 */ + "reserved", /* 101 */ + "reserved", /* 110 */ + "reserved" /* 111 */ + }; + static const char * const size_str[8] = { + "512 kB", /* 000 */ + " 1 MB", /* 001 */ + " 2 MB", /* 010 */ + " 4 MB", /* 011 */ + " 8 MB", /* 100 */ + " 16 MB", /* 101 */ + "reserved", /* 110 */ + "reserved", /* 111 */ + }; + + msg_pdbg2("=== Component Section ===\n"); + msg_pdbg2("FLCOMP 0x%08x\n", desc->component.FLCOMP); + msg_pdbg2("FLILL 0x%08x\n", desc->component.FLILL ); + msg_pdbg2("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2("Component 1 density: %s\n", + size_str[desc->component.comp1_density]); + if (desc->content.NC) + msg_pdbg2("Component 2 density: %s\n", + size_str[desc->component.comp2_density]); + else + msg_pdbg2("Component 2 is not used.\n"); + msg_pdbg2("Read Clock Frequency: %s\n", + freq_str[desc->component.freq_read]); + msg_pdbg2("Read ID and Status Clock Freq.: %s\n", + freq_str[desc->component.freq_read_id]); + msg_pdbg2("Write and Erase Clock Freq.: %s\n", + freq_str[desc->component.freq_write]); + msg_pdbg2("Fast Read is %ssupported.\n", + desc->component.fastread ? "" : "not "); + if (desc->component.fastread) + msg_pdbg2("Fast Read Clock Frequency: %s\n", + freq_str[desc->component.freq_fastread]); + if (desc->component.FLILL == 0) + msg_pdbg2("No forbidden opcodes.\n"); + else { + msg_pdbg2("Invalid instruction 0: 0x%02x\n", + desc->component.invalid_instr0); + msg_pdbg2("Invalid instruction 1: 0x%02x\n", + desc->component.invalid_instr1); + msg_pdbg2("Invalid instruction 2: 0x%02x\n", + desc->component.invalid_instr2); + msg_pdbg2("Invalid instruction 3: 0x%02x\n", + desc->component.invalid_instr3); + } + msg_pdbg2("\n"); +} + +static void pprint_freg(const struct ich_desc_region *reg, uint32_t i) +{ + static const char *const region_names[5] = { + "Descr.", "BIOS", "ME", "GbE", "Platf." + }; + if (i >= 5) { + msg_pdbg2("%s: region index too high.\n", __func__); + return; + } + uint32_t base = ICH_FREG_BASE(reg->FLREGs[i]); + uint32_t limit = ICH_FREG_LIMIT(reg->FLREGs[i]); + msg_pdbg2("Region %d (%-6s) ", i, region_names[i]); + if (base > limit) + msg_pdbg2("is unused.\n"); + else + msg_pdbg2("0x%08x - 0x%08x\n", base, limit | 0x0fff); +} + +void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc) +{ + uint8_t i; + uint8_t nr = desc->content.NR + 1; + msg_pdbg2("=== Region Section ===\n"); + if (nr >= 5) { + msg_pdbg2("%s: number of regions too high (%d).\n", __func__, + nr); + return; + } + for (i = 0; i <= nr; i++) + msg_pdbg2("FLREG%d 0x%08x\n", i, desc->region.FLREGs[i]); + msg_pdbg2("\n"); + + msg_pdbg2("--- Details ---\n"); + for (i = 0; i <= nr; i++) + pprint_freg(&desc->region, i); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_master(const struct ich_desc_master *mstr) +{ + msg_pdbg2("=== Master Section ===\n"); + msg_pdbg2("FLMSTR1 0x%08x\n", mstr->FLMSTR1); + msg_pdbg2("FLMSTR2 0x%08x\n", mstr->FLMSTR2); + msg_pdbg2("FLMSTR3 0x%08x\n", mstr->FLMSTR3); + msg_pdbg2("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2(" Descr. BIOS ME GbE Platf.\n"); + msg_pdbg2("BIOS %c%c %c%c %c%c %c%c %c%c\n", + (mstr->BIOS_descr_r) ?'r':' ', (mstr->BIOS_descr_w) ?'w':' ', + (mstr->BIOS_BIOS_r) ?'r':' ', (mstr->BIOS_BIOS_w) ?'w':' ', + (mstr->BIOS_ME_r) ?'r':' ', (mstr->BIOS_ME_w) ?'w':' ', + (mstr->BIOS_GbE_r) ?'r':' ', (mstr->BIOS_GbE_w) ?'w':' ', + (mstr->BIOS_plat_r) ?'r':' ', (mstr->BIOS_plat_w) ?'w':' '); + msg_pdbg2("ME %c%c %c%c %c%c %c%c %c%c\n", + (mstr->ME_descr_r) ?'r':' ', (mstr->ME_descr_w) ?'w':' ', + (mstr->ME_BIOS_r) ?'r':' ', (mstr->ME_BIOS_w) ?'w':' ', + (mstr->ME_ME_r) ?'r':' ', (mstr->ME_ME_w) ?'w':' ', + (mstr->ME_GbE_r) ?'r':' ', (mstr->ME_GbE_w) ?'w':' ', + (mstr->ME_plat_r) ?'r':' ', (mstr->ME_plat_w) ?'w':' '); + msg_pdbg2("GbE %c%c %c%c %c%c %c%c %c%c\n", + (mstr->GbE_descr_r) ?'r':' ', (mstr->GbE_descr_w) ?'w':' ', + (mstr->GbE_BIOS_r) ?'r':' ', (mstr->GbE_BIOS_w) ?'w':' ', + (mstr->GbE_ME_r) ?'r':' ', (mstr->GbE_ME_w) ?'w':' ', + (mstr->GbE_GbE_r) ?'r':' ', (mstr->GbE_GbE_w) ?'w':' ', + (mstr->GbE_plat_r) ?'r':' ', (mstr->GbE_plat_w) ?'w':' '); + msg_pdbg2("\n"); +} + +static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) +{ + uint32_t control = 0; + control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS; + control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI; + mmio_le_writel(control, spibar + ICH9_REG_FDOC); + return mmio_le_readl(spibar + ICH9_REG_FDOD); +} + +int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc) +{ + uint8_t i; + uint8_t nr; + struct ich_desc_region *r = &desc->region; + + /* Test if bit-fields are working as expected. + * FIXME: Replace this with dynamic bitfield fixup + */ + for (i = 0; i < 4; i++) + desc->region.FLREGs[i] = 0x5A << (i * 8); + if (r->reg0_base != 0x005A || r->reg0_limit != 0x0000 || + r->reg1_base != 0x1A00 || r->reg1_limit != 0x0000 || + r->reg2_base != 0x0000 || r->reg2_limit != 0x005A || + r->reg3_base != 0x0000 || r->reg3_limit != 0x1A00) { + msg_pdbg("The combination of compiler and CPU architecture used" + "does not lay out bit-fields as expected, sorry.\n"); + msg_pspew("r->reg0_base = 0x%04X (0x005A)\n", r->reg0_base); + msg_pspew("r->reg0_limit = 0x%04X (0x0000)\n", r->reg0_limit); + msg_pspew("r->reg1_base = 0x%04X (0x1A00)\n", r->reg1_base); + msg_pspew("r->reg1_limit = 0x%04X (0x0000)\n", r->reg1_limit); + msg_pspew("r->reg2_base = 0x%04X (0x0000)\n", r->reg2_base); + msg_pspew("r->reg2_limit = 0x%04X (0x005A)\n", r->reg2_limit); + msg_pspew("r->reg3_base = 0x%04X (0x0000)\n", r->reg3_base); + msg_pspew("r->reg3_limit = 0x%04X (0x1A00)\n", r->reg3_limit); + return ICH_RET_ERR; + } + + msg_pdbg2("Reading flash descriptors " + "mapped by the chipset via FDOC/FDOD..."); + /* content section */ + desc->content.FLVALSIG = read_descriptor_reg(0, 0, spibar); + desc->content.FLMAP0 = read_descriptor_reg(0, 1, spibar); + desc->content.FLMAP1 = read_descriptor_reg(0, 2, spibar); + desc->content.FLMAP2 = read_descriptor_reg(0, 3, spibar); + + /* component section */ + desc->component.FLCOMP = read_descriptor_reg(1, 0, spibar); + desc->component.FLILL = read_descriptor_reg(1, 1, spibar); + desc->component.FLPB = read_descriptor_reg(1, 2, spibar); + + /* region section */ + nr = desc->content.NR + 1; + if (nr >= 5) { + msg_pdbg2("%s: number of regions too high (%d) - failed\n", + __func__, nr); + return ICH_RET_ERR; + } + for (i = 0; i <= nr; i++) + desc->region.FLREGs[i] = read_descriptor_reg(2, i, spibar); + + /* master section */ + desc->master.FLMSTR1 = read_descriptor_reg(3, 0, spibar); + desc->master.FLMSTR2 = read_descriptor_reg(3, 1, spibar); + desc->master.FLMSTR3 = read_descriptor_reg(3, 2, spibar); + + /* Accessing the strap section via FDOC/D is only possible on ICH8 and + * reading the upper map is impossible on all chipsets, so don't bother. + */ + + msg_pdbg2(" done.\n"); + return ICH_RET_OK; +} +#endif /* defined(__i386__) || defined(__x86_64__) */ Added: trunk/ich_descriptors.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/ich_descriptors.h Fri Sep 16 01:52:55 2011 (r1443) @@ -0,0 +1,260 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (c) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if defined(__i386__) || defined(__x86_64__) +#ifndef __ICH_DESCRIPTORS_H__ +#define __ICH_DESCRIPTORS_H__ 1 + +#include <stdint.h> + +/* FIXME: Replace with generic return codes */ +#define ICH_RET_OK 0 +#define ICH_RET_ERR -1 +#define ICH_RET_WARN -2 +#define ICH_RET_PARAM -3 +#define ICH_RET_OOB -4 + +#define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */ + /* 0-1: reserved */ +#define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */ +#define FDOC_FDSI (0x3f << FDOC_FDSI_OFF) +#define FDOC_FDSS_OFF 12 /* 12-14: Flash Descriptor Section Select */ +#define FDOC_FDSS (0x3 << FDOC_FDSS_OFF) + /* 15-31: reserved */ + +#define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */ + +/* Field locations and semantics for LVSCC, UVSCC and related words in the flash + * descriptor are equal therefore they all share the same macros below. */ +#define VSCC_BES_OFF 0 /* 0-1: Block/Sector Erase Size */ +#define VSCC_BES (0x3 << VSCC_BES_OFF) +#define VSCC_WG_OFF 2 /* 2: Write Granularity */ +#define VSCC_WG (0x1 << VSCC_WG_OFF) +#define VSCC_WSR_OFF 3 /* 3: Write Status Required */ +#define VSCC_WSR (0x1 << VSCC_WSR_OFF) +#define VSCC_WEWS_OFF 4 /* 4: Write Enable on Write Status */ +#define VSCC_WEWS (0x1 << VSCC_WEWS_OFF) + /* 5-7: reserved */ +#define VSCC_EO_OFF 8 /* 8-15: Erase Opcode */ +#define VSCC_EO (0xff << VSCC_EO_OFF) + /* 16-22: reserved */ +#define VSCC_VCL_OFF 23 /* 23: Vendor Component Lock */ +#define VSCC_VCL (0x1 << VSCC_VCL_OFF) + /* 24-31: reserved */ + +#define ICH_FREG_BASE(flreg) (((flreg) << 12) & 0x01fff000) +#define ICH_FREG_LIMIT(flreg) (((flreg) >> 4) & 0x01fff000) + +/* Used to select the right descriptor printing function. + * Currently only ICH8 and Ibex Peak are supported. + */ +enum ich_chipset { + CHIPSET_ICH_UNKNOWN, + CHIPSET_ICH7 = 7, + CHIPSET_ICH8, + CHIPSET_ICH9, + CHIPSET_ICH10, + CHIPSET_5_SERIES_IBEX_PEAK, + CHIPSET_6_SERIES_COUGAR_POINT, + CHIPSET_7_SERIES_PANTHER_POINT +}; + +void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity); + +struct ich_desc_content { + uint32_t FLVALSIG; /* 0x00 */ + union { /* 0x04 */ + uint32_t FLMAP0; + struct { + uint32_t FCBA :8, /* Flash Component Base Address */ + NC :2, /* Number Of Components */ + :6, + FRBA :8, /* Flash Region Base Address */ + NR :3, /* Number Of Regions */ + :5; + }; + }; + union { /* 0x08 */ + uint32_t FLMAP1; + struct { + uint32_t FMBA :8, /* Flash Master Base Address */ + NM :3, /* Number Of Masters */ + :5, + FISBA :8, /* Flash ICH Strap Base Address */ + ISL :8; /* ICH Strap Length */ + }; + }; + union { /* 0x0c */ + uint32_t FLMAP2; + struct { + uint32_t FMSBA :8, /* Flash (G)MCH Strap Base Addr. */ + MSL :8, /* MCH Strap Length */ + :16; + }; + }; +}; + +struct ich_desc_component { + union { /* 0x00 */ + uint32_t FLCOMP; /* Flash Components Register */ + struct { + uint32_t comp1_density :3, + comp2_density :3, + :11, + freq_read :3, + fastread :1, + freq_fastread :3, + freq_write :3, + freq_read_id :3, + :2; + }; + }; + union { /* 0x04 */ + uint32_t FLILL; /* Flash Invalid Instructions Register */ + struct { + uint32_t invalid_instr0 :8, + invalid_instr1 :8, + invalid_instr2 :8, + invalid_instr3 :8; + }; + }; + union { /* 0x08 */ + uint32_t FLPB; /* Flash Partition Boundary Register */ + struct { + uint32_t FPBA :13, /* Flash Partition Boundary Addr */ + :19; + }; + }; +}; + +struct ich_desc_region { + union { + uint32_t FLREGs[5]; + struct { + struct { /* FLREG0 Flash Descriptor */ + uint32_t reg0_base :13, + :3, + reg0_limit :13, + :3; + }; + struct { /* FLREG1 BIOS */ + uint32_t reg1_base :13, + :3, + reg1_limit :13, + :3; + }; + struct { /* FLREG2 ME */ + uint32_t reg2_base :13, + :3, + reg2_limit :13, + :3; + }; + struct { /* FLREG3 GbE */ + uint32_t reg3_base :13, + :3, + reg3_limit :13, + :3; + }; + struct { /* FLREG4 Platform */ + uint32_t reg4_base :13, + :3, + reg4_limit :13, + :3; + }; + }; + }; +}; + +struct ich_desc_master { + union { + uint32_t FLMSTR1; + struct { + uint32_t BIOS_req_ID :16, + BIOS_descr_r :1, + BIOS_BIOS_r :1, + BIOS_ME_r :1, + BIOS_GbE_r :1, + BIOS_plat_r :1, + :3, + BIOS_descr_w :1, + BIOS_BIOS_w :1, + BIOS_ME_w :1, + BIOS_GbE_w :1, + BIOS_plat_w :1, + :3; + }; + }; + union { + uint32_t FLMSTR2; + struct { + uint32_t ME_req_ID :16, + ME_descr_r :1, + ME_BIOS_r :1, + ME_ME_r :1, + ME_GbE_r :1, + ME_plat_r :1, + :3, + ME_descr_w :1, + ME_BIOS_w :1, + ME_ME_w :1, + ME_GbE_w :1, + ME_plat_w :1, + :3; + }; + }; + union { + uint32_t FLMSTR3; + struct { + uint32_t GbE_req_ID :16, + GbE_descr_r :1, + GbE_BIOS_r :1, + GbE_ME_r :1, + GbE_GbE_r :1, + GbE_plat_r :1, + :3, + GbE_descr_w :1, + GbE_BIOS_w :1, + GbE_ME_w :1, + GbE_GbE_w :1, + GbE_plat_w :1, + :3; + }; + }; +}; + +struct ich_descriptors { + struct ich_desc_content content; + struct ich_desc_component component; + struct ich_desc_region region; + struct ich_desc_master master; +}; + +void prettyprint_ich_descriptors(enum ich_chipset, const struct ich_descriptors *desc); + +void prettyprint_ich_descriptor_content(const struct ich_desc_content *content); +void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc); +void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc); +void prettyprint_ich_descriptor_master(const struct ich_desc_master *master); + +int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc); + +#endif /* __ICH_DESCRIPTORS_H__ */ +#endif /* defined(__i386__) || defined(__x86_64__) */ Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Fri Sep 16 01:38:14 2011 (r1442) +++ trunk/ichspi.c Fri Sep 16 01:52:55 2011 (r1443) @@ -29,6 +29,7 @@ #include "flash.h" #include "programmer.h" #include "spi.h" +#include "ich_descriptors.h" /* ICH9 controller register definition */ #define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ @@ -119,6 +120,16 @@ #define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */ #define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */ +#define ICH8_REG_VSCC 0xC1 /* 32 Bits Vendor Specific Component Capabilities */ +#define ICH9_REG_LVSCC 0xC4 /* 32 Bits Host Lower Vendor Specific Component Capabilities */ +#define ICH9_REG_UVSCC 0xC8 /* 32 Bits Host Upper Vendor Specific Component Capabilities */ +/* The individual fields of the VSCC registers are defined in the file + * ich_descriptors.h. The reason is that the same layout is also used in the + * flash descriptor to define the properties of the different flash chips + * supported. The BIOS (or the ME?) is responsible to populate the ICH registers + * with the information from the descriptor on startup depending on the actual + * chip(s) detected. */ + #define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */ #define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */ #define FPB_FPBA (0x1FFF << FPB_FPBA_OFF) @@ -1129,9 +1140,6 @@ #define ICH_BRWA(x) ((x >> 8) & 0xff) #define ICH_BRRA(x) ((x >> 0) & 0xff) -#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff) -#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff) - static void do_ich9_spi_frap(uint32_t frap, int i) { static const char *const access_names[4] = { @@ -1158,9 +1166,8 @@ return; } - msg_pdbg("0x%08x-0x%08x is %s\n", - (base << 12), (limit << 12) | 0x0fff, - access_names[rwperms]); + msg_pdbg("0x%08x-0x%08x is %s\n", base, (limit | 0x0fff), + access_names[rwperms]); } static const struct spi_programmer spi_programmer_ich7 = { @@ -1190,6 +1197,7 @@ uint8_t old, new; uint16_t spibar_offset, tmp2; uint32_t tmp; + int ichspi_desc = 0; switch (ich_generation) { case 7: @@ -1261,6 +1269,8 @@ msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } + if (tmp2 & HSFS_FDV) + ichspi_desc = 1; tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); @@ -1308,12 +1318,38 @@ mmio_readl(ich_spibar + ICH9_REG_OPMENU)); msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + ICH9_REG_OPMENU + 4)); - ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); - msg_pdbg("0xA0: 0x%08x (BBAR)\n", - ichspi_bbar); - tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); - msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + if (ich_generation == 8) { + tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC); + msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp); + msg_pdbg("VSCC: "); + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); + } else { + ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); + msg_pdbg("0xA0: 0x%08x (BBAR)\n", + ichspi_bbar); + + tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); + msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); + msg_pdbg("LVSCC: "); + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); + + tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); + msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); + msg_pdbg("UVSCC: "); + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); + tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); + msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + } + + msg_pdbg("\n"); + if (ichspi_desc) { + struct ich_descriptors desc = {{ 0 }}; + if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == + ICH_RET_OK) + prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, + &desc); + } ich_init_opcodes(); break; default:

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[commit] r1442 - trunk
by repository service 16 Sep '11

16 Sep '11

Author: stefanct Date: Fri Sep 16 01:38:14 2011 New Revision: 1442 URL: http://flashrom.org/trac/flashrom/changeset/1442 Log: serprog: add SPI support Adds a new opcode (0x13) that just relays SPI bytes and wires it up to be usable within serprog.c. Checks for mandatory opcodes are moved around and changed a bit, but non-SPI programmers should not be harmed by this patch. Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/programmer.h trunk/serprog-protocol.txt trunk/serprog.c Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Thu Sep 15 00:09:48 2011 (r1441) +++ trunk/programmer.h Fri Sep 16 01:38:14 2011 (r1442) @@ -545,6 +545,9 @@ #if CONFIG_LINUX_SPI == 1 SPI_CONTROLLER_LINUX, #endif +#if CONFIG_SERPROG == 1 + SPI_CONTROLLER_SERPROG, +#endif }; extern const int spi_programmer_count; @@ -605,6 +608,9 @@ uint8_t serprog_chip_readb(const chipaddr addr); void serprog_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); void serprog_delay(int delay); +int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, unsigned char *readarr); +int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); #endif /* serial.c */ Modified: trunk/serprog-protocol.txt ============================================================================== --- trunk/serprog-protocol.txt Thu Sep 15 00:09:48 2011 (r1441) +++ trunk/serprog-protocol.txt Fri Sep 16 01:38:14 2011 (r1442) @@ -31,6 +31,8 @@ 0x10 Sync NOP none NAK + ACK (for synchronization) 0x11 Query maximum read-n length none ACK + 24-bit length (0==2^24) / NAK 0x12 Set used bustype 8-bit flags (as with 0x05) ACK / NAK +0x13 Perform SPI operation 24-bit slen + 24-bit rlen ACK + rlen bytes of data / NAK + + slen bytes of data 0x?? unimplemented command - invalid. @@ -50,7 +52,7 @@ it should return a big bogus value - eg 0xFFFF. 0x05 (Q_BUSTYPE): The bit's are defined as follows: - bit 0: PARALLEL, bit 1: LPC, bit 2: FWH, bit 3: SPI (if ever supported). + bit 0: PARALLEL, bit 1: LPC, bit 2: FWH, bit 3: SPI. 0x06 (Q_CHIPSIZE): Only applicable to parallel programmers. An LPC/FWH/SPI-programmer can report this as not supported in the command bitmap. @@ -66,6 +68,11 @@ Set's the used bustype if the programmer can support more than one flash protocol. Sending a byte with more than 1 bit set will make the programmer decide among them on it's own. Bit values as with Q_BUSTYPE. + 0x13 (O_SPIOP): + Send and receive bytes via SPI. + Maximum slen is Q_WRNMAXLEN in case Q_BUSTYPE returns SPI only or S_BUSTYPE was used + to set SPI exclusively before. Same for rlen and Q_RDNMAXLEN. + This operation is immediate, meaning it doesnt use the operation buffer. About mandatory commands: The only truly mandatory commands for any device are 0x00, 0x01, 0x02 and 0x10, but one can't really do anything with these commands. @@ -99,3 +106,4 @@ #define S_CMD_SYNCNOP 0x10 /* Special no-operation that returns NAK+ACK */ #define S_CMD_Q_RDNMAXLEN 0x11 /* Query read-n maximum length */ #define S_CMD_S_BUSTYPE 0x12 /* Set used bustype(s). */ +#define S_CMD_O_SPIOP 0x13 /* Perform SPI operation. */ Modified: trunk/serprog.c ============================================================================== --- trunk/serprog.c Thu Sep 15 00:09:48 2011 (r1441) +++ trunk/serprog.c Fri Sep 16 01:38:14 2011 (r1442) @@ -1,7 +1,7 @@ /* * This file is part of the flashrom project. * - * Copyright (C) 2009 Urja Rannikko <urjaman(a)gmail.com> + * Copyright (C) 2009, 2011 Urja Rannikko <urjaman(a)gmail.com> * Copyright (C) 2009 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify @@ -36,6 +36,7 @@ #include <termios.h> #include "flash.h" #include "programmer.h" +#include "chipdrivers.h" #define MSGHEADER "serprog:" @@ -67,6 +68,7 @@ #define S_CMD_SYNCNOP 0x10 /* Special no-operation that returns NAK+ACK */ #define S_CMD_Q_RDNMAXLEN 0x11 /* Query read-n maximum length */ #define S_CMD_S_BUSTYPE 0x12 /* Set used bustype(s). */ +#define S_CMD_O_SPIOP 0x13 /* Perform SPI operation. */ static uint16_t sp_device_serbuf_size = 16; static uint16_t sp_device_opbuf_size = 300; @@ -302,6 +304,16 @@ return 0; } +static struct spi_programmer spi_programmer_serprog = { + .type = SPI_CONTROLLER_SERPROG, + .max_data_read = MAX_DATA_READ_UNLIMITED, + .max_data_write = MAX_DATA_WRITE_UNLIMITED, + .command = serprog_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = serprog_spi_read, + .write_256 = default_spi_write_256, +}; + int serprog_init(void) { uint16_t iface; @@ -325,7 +337,7 @@ msg_perr("Error: No baudrate specified.\n" "Use flashrom -p serprog:dev=/dev/device:baud\n"); free(device); - return 1; + return 1; } if (strlen(device)) { sp_fd = sp_openserport(device, atoi(baudport)); @@ -358,7 +370,7 @@ msg_perr("Error: No port specified.\n" "Use flashrom -p serprog:ip=ipaddr:port\n"); free(device); - return 1; + return 1; } if (strlen(device)) { sp_fd = sp_opensocket(device, atoi(baudport)); @@ -410,35 +422,115 @@ sp_check_avail_automatic = 1; - /* Check for the minimum operational set of commands */ - if (sp_check_commandavail(S_CMD_R_BYTE) == 0) { - msg_perr("Error: Single byte read not supported\n"); - exit(1); - } - /* This could be translated to single byte reads (if missing), * - * but now we dont support that. */ - if (sp_check_commandavail(S_CMD_R_NBYTES) == 0) { - msg_perr("Error: Read n bytes not supported\n"); - exit(1); - } - /* In the future one could switch to read-only mode if these * - * are not available. */ - if (sp_check_commandavail(S_CMD_O_INIT) == 0) { - msg_perr("Error: Initialize operation buffer not supported\n"); - exit(1); - } - if (sp_check_commandavail(S_CMD_O_WRITEB) == 0) { - msg_perr("Error: Write to opbuf: write byte not supported\n"); - exit(1); + + if (sp_docommand(S_CMD_Q_BUSTYPE, 0, NULL, 1, &c)) { + msg_perr("Warning: NAK to query supported buses\n"); + c = BUS_NONSPI; /* A reasonable default for now. */ } - if (sp_check_commandavail(S_CMD_O_DELAY) == 0) { - msg_perr("Error: Write to opbuf: delay not supported\n"); - exit(1); + buses_supported = c; + /* Check for the minimum operational set of commands. */ + if (buses_supported & BUS_SPI) { + uint8_t bt = BUS_SPI; + if (sp_check_commandavail(S_CMD_O_SPIOP) == 0) { + msg_perr("Error: SPI operation not supported while the " + "bustype is SPI\n"); + exit(1); + } + /* Success of any of these commands is optional. We don't need + the programmer to tell us its limits, but if it doesn't, we + will assume stuff, so it's in the programmers best interest + to tell us. */ + sp_docommand(S_CMD_S_BUSTYPE, 1, &bt, 0, NULL); + if (!sp_docommand(S_CMD_Q_WRNMAXLEN, 0, NULL, 3, rbuf)) { + uint32_t v; + v = ((unsigned int)(rbuf[0]) << 0); + v |= ((unsigned int)(rbuf[1]) << 8); + v |= ((unsigned int)(rbuf[2]) << 16); + if (v == 0) + v = (1 << 24) - 1; /* SPI-op maximum. */ + spi_programmer_serprog.max_data_write = v; + msg_pdbg(MSGHEADER "Maximum write-n length is %d\n", v); + } + if (!sp_docommand(S_CMD_Q_RDNMAXLEN, 0, NULL, 3, rbuf)) { + uint32_t v; + v = ((unsigned int)(rbuf[0]) << 0); + v |= ((unsigned int)(rbuf[1]) << 8); + v |= ((unsigned int)(rbuf[2]) << 16); + if (v == 0) + v = (1 << 24) - 1; /* SPI-op maximum. */ + spi_programmer_serprog.max_data_read = v; + msg_pdbg(MSGHEADER "Maximum read-n length is %d\n", v); + } + bt = buses_supported; + sp_docommand(S_CMD_S_BUSTYPE, 1, &bt, 0, NULL); + register_spi_programmer(&spi_programmer_serprog); } - if (sp_check_commandavail(S_CMD_O_EXEC) == 0) { - msg_perr( - "Error: Execute operation buffer not supported\n"); - exit(1); + + if (buses_supported & BUS_NONSPI) { + if (sp_check_commandavail(S_CMD_O_INIT) == 0) { + msg_perr("Error: Initialize operation buffer " + "not supported\n"); + exit(1); + } + + if (sp_check_commandavail(S_CMD_O_DELAY) == 0) { + msg_perr("Error: Write to opbuf: " + "delay not supported\n"); + exit(1); + } + + /* S_CMD_O_EXEC availability checked later. */ + + if (sp_check_commandavail(S_CMD_R_BYTE) == 0) { + msg_perr("Error: Single byte read not supported\n"); + exit(1); + } + /* This could be translated to single byte reads (if missing), + * but now we don't support that. */ + if (sp_check_commandavail(S_CMD_R_NBYTES) == 0) { + msg_perr("Error: Read n bytes not supported\n"); + exit(1); + } + if (sp_check_commandavail(S_CMD_O_WRITEB) == 0) { + msg_perr("Error: Write to opbuf: " + "write byte not supported\n"); + exit(1); + } + + if (sp_docommand(S_CMD_Q_WRNMAXLEN, 0, NULL, 3, rbuf)) { + msg_pdbg(MSGHEADER "Write-n not supported"); + sp_max_write_n = 0; + } else { + sp_max_write_n = ((unsigned int)(rbuf[0]) << 0); + sp_max_write_n |= ((unsigned int)(rbuf[1]) << 8); + sp_max_write_n |= ((unsigned int)(rbuf[2]) << 16); + if (!sp_max_write_n) { + sp_max_write_n = (1 << 24); + } + msg_pdbg(MSGHEADER "Maximum write-n length is %d\n", + sp_max_write_n); + sp_write_n_buf = malloc(sp_max_write_n); + if (!sp_write_n_buf) { + msg_perr("Error: cannot allocate memory for " + "Write-n buffer\n"); + exit(1); + } + sp_write_n_bytes = 0; + } + + if (sp_check_commandavail(S_CMD_Q_RDNMAXLEN) && + (sp_docommand(S_CMD_Q_RDNMAXLEN, 0, NULL, 3, rbuf) == 0)) { + sp_max_read_n = ((unsigned int)(rbuf[0]) << 0); + sp_max_read_n |= ((unsigned int)(rbuf[1]) << 8); + sp_max_read_n |= ((unsigned int)(rbuf[2]) << 16); + msg_pdbg(MSGHEADER "Maximum read-n length is %d\n", + sp_max_read_n ? sp_max_read_n : (1 << 24)); + } else { + msg_pdbg(MSGHEADER "Maximum read-n length " + "not reported\n"); + sp_max_read_n = 0; + } + } if (sp_docommand(S_CMD_Q_PGMNAME, 0, NULL, 16, pgmname)) { @@ -454,51 +546,27 @@ msg_pdbg(MSGHEADER "serial buffer size %d\n", sp_device_serbuf_size); - if (sp_docommand(S_CMD_Q_OPBUF, 0, NULL, 2, &sp_device_opbuf_size)) { - msg_perr("Warning: NAK to query operation buffer size\n"); - } - msg_pdbg(MSGHEADER "operation buffer size %d\n", - sp_device_opbuf_size); - - if (sp_docommand(S_CMD_Q_BUSTYPE, 0, NULL, 1, &c)) { - msg_perr("Warning: NAK to query supported buses\n"); - c = BUS_NONSPI; /* A reasonable default for now. */ - } - buses_supported = c; - - if (sp_docommand(S_CMD_O_INIT, 0, NULL, 0, NULL)) { - msg_perr("Error: NAK to initialize operation buffer\n"); - exit(1); - } + if (sp_check_commandavail(S_CMD_O_INIT)) { + /* This would be inconsistent. */ + if (sp_check_commandavail(S_CMD_O_EXEC) == 0) { + msg_perr("Error: Execute operation buffer not " + "supported\n"); + exit(1); + } - if (sp_docommand(S_CMD_Q_WRNMAXLEN, 0, NULL, 3, rbuf)) { - msg_pdbg(MSGHEADER "Write-n not supported"); - sp_max_write_n = 0; - } else { - sp_max_write_n = ((unsigned int)(rbuf[0]) << 0); - sp_max_write_n |= ((unsigned int)(rbuf[1]) << 8); - sp_max_write_n |= ((unsigned int)(rbuf[2]) << 16); - msg_pdbg(MSGHEADER "Maximum write-n length %d\n", - sp_max_write_n); - sp_write_n_buf = malloc(sp_max_write_n); - if (!sp_write_n_buf) { - msg_perr("Error: cannot allocate memory for Write-n buffer\n"); + if (sp_docommand(S_CMD_O_INIT, 0, NULL, 0, NULL)) { + msg_perr("Error: NAK to initialize operation buffer\n"); exit(1); } - sp_write_n_bytes = 0; - } - - if ((sp_check_commandavail(S_CMD_Q_RDNMAXLEN)) - &&((sp_docommand(S_CMD_Q_RDNMAXLEN,0,NULL, 3, rbuf) == 0))) { - sp_max_read_n = ((unsigned int)(rbuf[0]) << 0); - sp_max_read_n |= ((unsigned int)(rbuf[1]) << 8); - sp_max_read_n |= ((unsigned int)(rbuf[2]) << 16); - msg_pdbg(MSGHEADER "Maximum read-n length %d\n", - sp_max_read_n ? sp_max_read_n : (1<<24)); - } else { - msg_pdbg(MSGHEADER "Maximum read-n length not reported\n"); - sp_max_read_n = 0; - } + + if (sp_docommand(S_CMD_Q_OPBUF, 0, NULL, 2, + &sp_device_opbuf_size)) { + msg_perr("Warning: NAK to query operation buffer " + "size\n"); + } + msg_pdbg(MSGHEADER "operation buffer size %d\n", + sp_device_opbuf_size); + } sp_prev_was_write = 0; sp_streamed_transmit_ops = 0; @@ -679,6 +747,12 @@ { unsigned char buf[4]; msg_pspew("%s\n", __func__); + if (!sp_check_commandavail(S_CMD_O_DELAY)) { + internal_delay(delay); + msg_pdbg("Note: serprog_delay used, but the programmer doesn't " + "support delay\n"); + return; + } if ((sp_max_write_n) && (sp_write_n_bytes)) sp_pass_writen(); sp_check_opbuf_usage(5); @@ -690,3 +764,48 @@ sp_opbuf_usage += 5; sp_prev_was_write = 0; } + +int serprog_spi_send_command(unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + unsigned char *parmbuf; + int ret; + msg_pspew("%s, writecnt=%i, readcnt=%i\n", __func__, writecnt, readcnt); + if ((sp_opbuf_usage) || (sp_max_write_n && sp_write_n_bytes)) + sp_execute_opbuf(); + parmbuf = malloc(writecnt + 6); + if (!parmbuf) + sp_die("Error: cannot malloc SPI send param buffer"); + parmbuf[0] = (writecnt >> 0) & 0xFF; + parmbuf[1] = (writecnt >> 8) & 0xFF; + parmbuf[2] = (writecnt >> 16) & 0xFF; + parmbuf[3] = (readcnt >> 0) & 0xFF; + parmbuf[4] = (readcnt >> 8) & 0xFF; + parmbuf[5] = (readcnt >> 16) & 0xFF; + memcpy(parmbuf + 6, writearr, writecnt); + ret = sp_docommand(S_CMD_O_SPIOP, writecnt + 6, parmbuf, readcnt, + readarr); + free(parmbuf); + return ret; +} + +/* FIXME: This function is optimized so that it does not split each transaction + * into chip page_size long blocks unnecessarily like spi_read_chunked. This has + * the advantage that it is much faster for most chips, but breaks those with + * non-contiguous address space (like AT45DB161D). When spi_read_chunked is + * fixed this method can be removed. */ +int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + int i; + int cur_len; + const int max_read = spi_programmer_serprog.max_data_read; + for (i = 0; i < len; i += cur_len) { + int ret; + cur_len = min(max_read, (len - i)); + ret = spi_nbyte_read(start + i, buf + i, cur_len); + if (ret) + return ret; + } + return 0; +}

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Re: [flashrom] [PATCH 1/3] serprog: add SPI support
by Uwe Hermann 16 Sep '11

16 Sep '11

On Thu, Sep 08, 2011 at 12:56:21AM +0200, Stefan Tauner wrote: > + 0x13 (O_SPIOP): > + Send and receive bytes via SPI. > + Maximum slen is Q_WRNMAXLEN result after Q_BUSTYPE returns ^ Full stop. > + only SPI or S_BUSTYPE == SPI is used. Same for rlen and Q_RDNMAXLEN. ^ Capitalize > +static struct spi_programmer spi_programmer_serprog = { > + .type = SPI_CONTROLLER_SERPROG, > + .max_data_read = MAX_DATA_READ_UNLIMITED, > + .max_data_write = MAX_DATA_WRITE_UNLIMITED, > + .command = serprog_spi_send_command, > + .multicommand = default_spi_send_multicommand, > + .read = serprog_spi_read, > + .write_256 = default_spi_write_256, > +}; Please use the "aligned" style using tabs, see e.g. "static const struct spi_programmer spi_programmer_linux" in linux_spi.c. > + if (sp_docommand(S_CMD_Q_BUSTYPE, 0, NULL, 1, &c)) { > + msg_perr("Warning: NAK to query supported buses\n"); perr and "Warning" doesn't sound consistent, but can be fixed in another patch. > + /* Success of any of these commands is optional. We dont need dont -> don't > + the programmer to tell us it's limits, but if it doesnt, we it's -> its doesnt -> doesn't > + if (!sp_docommand(S_CMD_Q_RDNMAXLEN, 0, NULL, 3, rbuf)) { > + uint32_t v; > + v = ((unsigned int)(rbuf[0]) << 0); > + v |= ((unsigned int)(rbuf[1]) << 8); > + v |= ((unsigned int)(rbuf[2]) << 16); Why (unsigned int) and not (uint32_t)? This is done in multiple places. > + /* This could be translated to single byte reads (if missing), > + * but now we dont support that. */ dont -> don't > + if (!sp_check_commandavail(S_CMD_O_DELAY)) { > + internal_delay(delay); > + msg_pdbg("Note: serprog_delay used, but the programmer doesnt support delay\n"); doesnt -> doesn't > + for(i = 0; i < len; ) { ^ missing space Otherwise Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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Re: [flashrom] [PATCH 1/3] serprog: add SPI support
by Carl-Daniel Hailfinger 16 Sep '11

16 Sep '11

Am 08.09.2011 00:56 schrieb Stefan Tauner: > +/* FIXME: This function is optimized so that it does not split each > + * transaction into chip page_size long blocks unnecessarily like > + * spi_read_chunked. When spi_read_chunked is fixed this method can be > + * removed. */ That "fix" would break all chips with a non-contiguous address space, i.e. all chips with a page size which is not a power of two. This shortcut here means that serprog will never work with those chips. Please add a FIXME comment which mentions this. > +int serprog_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) > +{ > + int i; > + const int max_read = spi_programmer_serprog.max_data_read; > + for(i = 0; i < len; ) { Space after for. You could indeed move the i+=cur_len into the for AFAICS. > + int ret; > + int cur_len = min(max_read, (len - i)); > + ret = spi_nbyte_read(start + i, buf + i, cur_len); > + if (ret) > + return ret; > + i += cur_len; > + } > + return 0; > +} Regards, Carl-Daniel -- http://www.hailfinger.org/

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[PATCH] ichspi: add ICH/PCH flash descriptor decoding via FDOC/FDOD
by Stefan Tauner 15 Sep '11

15 Sep '11

based on the work of Matthias 'mazzoo' Wenzel this patch adds pretty printing of those ICH/PCH flash descriptor sections that are cached/mapped by the chipset (and which are therefore reachable via FDOC/FDOD registers). this includes the following: - content section: describes the image and some generic properties (number of sections, offset of sections, PCH/ICH and MCH/PROC strap offsets and lengths) - component section: identify the different SPI flash chips and their capabilities. - region section similarly to a partition table this describes the different regions. the content of FLREG* is derived from this section. - master section defines SPI master (host, ME, GbE) access rights of the individual regions. the content of PR* is derived from this section. this is only a part of the data included in the descriptor. other information can be retrieved from a complete binary dump of the descriptor region only. this patch also adds macros and pretty printing for "Vendor Specific Component Capabilities" registers: there are two of them: lower and upper. they describe the properties of the address space divided by FPBA (which allows to use multiple flash chips or partitions with different properties). the properties of all supported flash chips (together with their RDIDs) are stored in the same format in table in a descriptor section (which is used by the ME apparently). a later patch will use the macros outside of ichspi.c which is the reason why the prettyprinting function and the register bit macros are not defined in ichspi.c but ich_descriptors.h (else they would be moved in the follow-up patch). because this patch relies on (compiler) implementation-specific layouting of bit-fields, it checks for correct layout before taking any action on runtime. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- this is the version without the compile-time checks as requested by carldani. Makefile | 3 +- ich_descriptors.c | 286 +++++++++++++++++++++++++++++++++++++++++++++++++++++ ich_descriptors.h | 259 ++++++++++++++++++++++++++++++++++++++++++++++++ ichspi.c | 58 +++++++++-- 4 files changed, 594 insertions(+), 12 deletions(-) create mode 100644 ich_descriptors.c create mode 100644 ich_descriptors.h diff --git a/Makefile b/Makefile index 6407e6b..4a8dc2c 100644 --- a/Makefile +++ b/Makefile @@ -349,7 +349,8 @@ ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o ifeq ($(ARCH),"x86") -PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += it87spi.o it85spi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += ichspi.o ich_descriptors.o else endif NEED_PCI := yes diff --git a/ich_descriptors.c b/ich_descriptors.c new file mode 100644 index 0000000..4ab2602 --- /dev/null +++ b/ich_descriptors.c @@ -0,0 +1,286 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (c) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if defined(__i386__) || defined(__x86_64__) + +#include "ich_descriptors.h" +#include "flash.h" /* for msg_* */ +#include "programmer.h" + +void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity) +{ + print(verbosity, "BES=0x%x, ", (reg_val & VSCC_BES) >> VSCC_BES_OFF); + print(verbosity, "WG=%d, ", (reg_val & VSCC_WG) >> VSCC_WG_OFF); + print(verbosity, "WSR=%d, ", (reg_val & VSCC_WSR) >> VSCC_WSR_OFF); + print(verbosity, "WEWS=%d, ", (reg_val & VSCC_WEWS) >> VSCC_WEWS_OFF); + print(verbosity, "EO=0x%x, ", (reg_val & VSCC_EO) >> VSCC_EO_OFF); + print(verbosity, "VCL=%d\n", (reg_val & VSCC_VCL) >> VSCC_VCL_OFF); +} + +#define getFCBA(cont) (((cont)->FLMAP0 << 4) & 0x00000ff0) +#define getFRBA(cont) (((cont)->FLMAP0 >> 12) & 0x00000ff0) +#define getFMBA(cont) (((cont)->FLMAP1 << 4) & 0x00000ff0) +#define getFISBA(cont) (((cont)->FLMAP1 >> 12) & 0x00000ff0) +#define getFMSBA(cont) (((cont)->FLMAP2 << 4) & 0x00000ff0) + +void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc) +{ + prettyprint_ich_descriptor_content(&desc->content); + prettyprint_ich_descriptor_component(desc); + prettyprint_ich_descriptor_region(desc); + prettyprint_ich_descriptor_master(&desc->master); +} + +void prettyprint_ich_descriptor_content(const struct ich_desc_content *cont) +{ + msg_pdbg2("=== Content Section ===\n"); + msg_pdbg2("FLVALSIG 0x%08x\n", cont->FLVALSIG); + msg_pdbg2("FLMAP0 0x%08x\n", cont->FLMAP0); + msg_pdbg2("FLMAP1 0x%08x\n", cont->FLMAP1); + msg_pdbg2("FLMAP2 0x%08x\n", cont->FLMAP2); + msg_pdbg2("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2("NR (Number of Regions): %5d\n", + cont->NR + 1); + msg_pdbg2("FRBA (Flash Region Base Address): 0x%03x\n", + getFRBA(cont)); + msg_pdbg2("NC (Number of Components): %5d\n", + cont->NC + 1); + msg_pdbg2("FCBA (Flash Component Base Address): 0x%03x\n", + getFCBA(cont)); + msg_pdbg2("ISL (ICH/PCH Strap Length): %5d\n", + cont->ISL); + msg_pdbg2("FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x%03x\n", + getFISBA(cont)); + msg_pdbg2("NM (Number of Masters): %5d\n", + cont->NM + 1); + msg_pdbg2("FMBA (Flash Master Base Address): 0x%03x\n", + getFMBA(cont)); + msg_pdbg2("MSL/PSL (MCH/PROC Strap Length): %5d\n", + cont->MSL); + msg_pdbg2("FMSBA (Flash MCH/PROC Strap Base Address): 0x%03x\n", + getFMSBA(cont)); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc) +{ + static const char * const str_freq[8] = { + "20 MHz", /* 000 */ + "33 MHz", /* 001 */ + "reserved", /* 010 */ + "reserved", /* 011 */ + "50 MHz", /* 100 */ + "reserved", /* 101 */ + "reserved", /* 110 */ + "reserved" /* 111 */ + }; + static const char * const str_mem[8] = { + "512 kB", /* 000 */ + " 1 MB", /* 001 */ + " 2 MB", /* 010 */ + " 4 MB", /* 011 */ + " 8 MB", /* 100 */ + " 16 MB", /* 101 */ + "reserved", /* 110 */ + "reserved", /* 111 */ + }; + + msg_pdbg2("=== Component Section ===\n"); + msg_pdbg2("FLCOMP 0x%08x\n", desc->component.FLCOMP); + msg_pdbg2("FLILL 0x%08x\n", desc->component.FLILL ); + msg_pdbg2("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2("Component 1 density: %s\n", + str_mem[desc->component.comp1_density]); + if (desc->content.NC) + msg_pdbg2("Component 2 density: %s\n", + str_mem[desc->component.comp2_density]); + else + msg_pdbg2("Component 2 is not used.\n"); + msg_pdbg2("Read Clock Frequency: %s\n", + str_freq[desc->component.freq_read]); + msg_pdbg2("Read ID and Status Clock Freq.: %s\n", + str_freq[desc->component.freq_read_id]); + msg_pdbg2("Write and Erase Clock Freq.: %s\n", + str_freq[desc->component.freq_write]); + msg_pdbg2("Fast Read is %ssupported.\n", + desc->component.fastread ? "" : "not "); + if (desc->component.fastread) + msg_pdbg2("Fast Read Clock Frequency: %s\n", + str_freq[desc->component.freq_fastread]); + if (desc->component.FLILL == 0) + msg_pdbg2("No forbidden opcodes.\n"); + else { + msg_pdbg2("Invalid instruction 0: 0x%02x\n", + desc->component.invalid_instr0); + msg_pdbg2("Invalid instruction 1: 0x%02x\n", + desc->component.invalid_instr1); + msg_pdbg2("Invalid instruction 2: 0x%02x\n", + desc->component.invalid_instr2); + msg_pdbg2("Invalid instruction 3: 0x%02x\n", + desc->component.invalid_instr3); + } + msg_pdbg2("\n"); +} + +static void pprint_freg(const struct ich_desc_region *reg, uint32_t i) +{ + static const char *const region_names[5] = { + "Descr.", "BIOS", "ME", "GbE", "Platf." + }; + if (i >= 5) { + msg_pdbg2("%s: region index too high.\n", __func__); + return; + } + uint32_t base = ICH_FREG_BASE(reg->FLREGs[i]); + uint32_t limit = ICH_FREG_LIMIT(reg->FLREGs[i]); + msg_pdbg2("Region %d (%-6s) ", i, region_names[i]); + if (base > limit) + msg_pdbg2("is unused.\n"); + else + msg_pdbg2("0x%08x - 0x%08x\n", base, limit | 0x0fff); +} + +void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc) +{ + uint8_t i; + uint8_t nr = desc->content.NR + 1; + msg_pdbg2("=== Region Section ===\n"); + if (nr >= 5) { + msg_pdbg2("%s: number of regions too high (%d).\n", __func__, + nr); + return; + } + for (i = 0; i <= nr; i++) + msg_pdbg2("FLREG%d 0x%08x\n", i, desc->region.FLREGs[i]); + msg_pdbg2("\n"); + + msg_pdbg2("--- Details ---\n"); + for (i = 0; i <= nr; i++) + pprint_freg(&desc->region, i); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_master(const struct ich_desc_master *mstr) +{ + msg_pdbg2("=== Master Section ===\n"); + msg_pdbg2("FLMSTR1 0x%08x\n", mstr->FLMSTR1); + msg_pdbg2("FLMSTR2 0x%08x\n", mstr->FLMSTR2); + msg_pdbg2("FLMSTR3 0x%08x\n", mstr->FLMSTR3); + msg_pdbg2("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2(" Descr. BIOS ME GbE Platf.\n"); + msg_pdbg2("BIOS %c%c %c%c %c%c %c%c %c%c\n", + (mstr->BIOS_descr_r) ?'r':' ', (mstr->BIOS_descr_w) ?'w':' ', + (mstr->BIOS_BIOS_r) ?'r':' ', (mstr->BIOS_BIOS_w) ?'w':' ', + (mstr->BIOS_ME_r) ?'r':' ', (mstr->BIOS_ME_w) ?'w':' ', + (mstr->BIOS_GbE_r) ?'r':' ', (mstr->BIOS_GbE_w) ?'w':' ', + (mstr->BIOS_plat_r) ?'r':' ', (mstr->BIOS_plat_w) ?'w':' '); + msg_pdbg2("ME %c%c %c%c %c%c %c%c %c%c\n", + (mstr->ME_descr_r) ?'r':' ', (mstr->ME_descr_w) ?'w':' ', + (mstr->ME_BIOS_r) ?'r':' ', (mstr->ME_BIOS_w) ?'w':' ', + (mstr->ME_ME_r) ?'r':' ', (mstr->ME_ME_w) ?'w':' ', + (mstr->ME_GbE_r) ?'r':' ', (mstr->ME_GbE_w) ?'w':' ', + (mstr->ME_plat_r) ?'r':' ', (mstr->ME_plat_w) ?'w':' '); + msg_pdbg2("GbE %c%c %c%c %c%c %c%c %c%c\n", + (mstr->GbE_descr_r) ?'r':' ', (mstr->GbE_descr_w) ?'w':' ', + (mstr->GbE_BIOS_r) ?'r':' ', (mstr->GbE_BIOS_w) ?'w':' ', + (mstr->GbE_ME_r) ?'r':' ', (mstr->GbE_ME_w) ?'w':' ', + (mstr->GbE_GbE_r) ?'r':' ', (mstr->GbE_GbE_w) ?'w':' ', + (mstr->GbE_plat_r) ?'r':' ', (mstr->GbE_plat_w) ?'w':' '); + msg_pdbg2("\n"); +} + +static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) +{ + uint32_t control = 0; + control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS; + control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI; + mmio_le_writel(control, spibar + ICH9_REG_FDOC); + return mmio_le_readl(spibar + ICH9_REG_FDOD); +} + +int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc) +{ + uint8_t i; + uint8_t nr; + struct ich_desc_region *r = &desc->region; + + /* Test if bit-fields are working as expected */ + for (i = 0; i < 4; i++) + desc->region.FLREGs[i] = 0x5A << (i * 8); + if (r->reg0_base != 0x005A || r->reg0_limit != 0x0000 || + r->reg1_base != 0x1A00 || r->reg1_limit != 0x0000 || + r->reg2_base != 0x0000 || r->reg2_limit != 0x005A || + r->reg3_base != 0x0000 || r->reg3_limit != 0x1A00) { + msg_pdbg("The combination of compiler and CPU architecture used" + "does not lay out bit-fields as expected, sorry.\n"); + msg_pspew("r->reg0_base = 0x%04X (0x005A)\n", r->reg0_base); + msg_pspew("r->reg0_limit = 0x%04X (0x0000)\n", r->reg0_limit); + msg_pspew("r->reg1_base = 0x%04X (0x1A00)\n", r->reg1_base); + msg_pspew("r->reg1_limit = 0x%04X (0x0000)\n", r->reg1_limit); + msg_pspew("r->reg2_base = 0x%04X (0x0000)\n", r->reg2_base); + msg_pspew("r->reg2_limit = 0x%04X (0x005A)\n", r->reg2_limit); + msg_pspew("r->reg3_base = 0x%04X (0x0000)\n", r->reg3_base); + msg_pspew("r->reg3_limit = 0x%04X (0x1A00)\n", r->reg3_limit); + return RET_ERR; + } + + msg_pdbg2("Reading flash descriptors " + "mapped by the chipset via FDOC/FDOD..."); + /* content section */ + desc->content.FLVALSIG = read_descriptor_reg(0, 0, spibar); + desc->content.FLMAP0 = read_descriptor_reg(0, 1, spibar); + desc->content.FLMAP1 = read_descriptor_reg(0, 2, spibar); + desc->content.FLMAP2 = read_descriptor_reg(0, 3, spibar); + + /* component section */ + desc->component.FLCOMP = read_descriptor_reg(1, 0, spibar); + desc->component.FLILL = read_descriptor_reg(1, 1, spibar); + desc->component.FLPB = read_descriptor_reg(1, 2, spibar); + + /* region section */ + nr = desc->content.NR + 1; + if (nr >= 5) { + msg_pdbg2("%s: number of regions too high (%d) - failed\n", + __func__, nr); + return RET_ERR; + } + for (i = 0; i <= nr; i++) + desc->region.FLREGs[i] = read_descriptor_reg(2, i, spibar); + + /* master section */ + desc->master.FLMSTR1 = read_descriptor_reg(3, 0, spibar); + desc->master.FLMSTR2 = read_descriptor_reg(3, 1, spibar); + desc->master.FLMSTR3 = read_descriptor_reg(3, 2, spibar); + + /* Accessing the strap section via FDOC/D is only possible on ICH8 and + * reading the upper map is impossible on all chipsets, so don't bother. + */ + + msg_pdbg2(" done.\n"); + return RET_OK; +} +#endif /* defined(__i386__) || defined(__x86_64__) */ diff --git a/ich_descriptors.h b/ich_descriptors.h new file mode 100644 index 0000000..098d3cd --- /dev/null +++ b/ich_descriptors.h @@ -0,0 +1,259 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (c) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if defined(__i386__) || defined(__x86_64__) +#ifndef __ICH_DESCRIPTORS_H__ +#define __ICH_DESCRIPTORS_H__ 1 + +#include <stdint.h> + +#define RET_OK 0 +#define RET_ERR -1 +#define RET_WARN -2 +#define RET_PARAM -3 +#define RET_OOB -4 + +#define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */ + /* 0-1: reserved */ +#define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */ +#define FDOC_FDSI (0x3f << FDOC_FDSI_OFF) +#define FDOC_FDSS_OFF 12 /* 12-14: Flash Descriptor Section Select */ +#define FDOC_FDSS (0x3 << FDOC_FDSS_OFF) + /* 15-31: reserved */ + +#define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */ + +/* Field locations and semantics for LVSCC, UVSCC and related words in the flash + * descriptor are equal therefore they all share the same macros below. */ +#define VSCC_BES_OFF 0 /* 0-1: Block/Sector Erase Size */ +#define VSCC_BES (0x3 << VSCC_BES_OFF) +#define VSCC_WG_OFF 2 /* 2: Write Granularity */ +#define VSCC_WG (0x1 << VSCC_WG_OFF) +#define VSCC_WSR_OFF 3 /* 3: Write Status Required */ +#define VSCC_WSR (0x1 << VSCC_WSR_OFF) +#define VSCC_WEWS_OFF 4 /* 4: Write Enable on Write Status */ +#define VSCC_WEWS (0x1 << VSCC_WEWS_OFF) + /* 5-7: reserved */ +#define VSCC_EO_OFF 8 /* 8-15: Erase Opcode */ +#define VSCC_EO (0xff << VSCC_EO_OFF) + /* 16-22: reserved */ +#define VSCC_VCL_OFF 23 /* 23: Vendor Component Lock */ +#define VSCC_VCL (0x1 << VSCC_VCL_OFF) + /* 24-31: reserved */ + +#define ICH_FREG_BASE(flreg) (((flreg) << 12) & 0x01fff000) +#define ICH_FREG_LIMIT(flreg) (((flreg) >> 4) & 0x01fff000) + +/* Used to select the right descriptor printing function. + * Currently only ICH8 and Ibex Peak are supported. + */ +enum ich_chipset { + CHIPSET_ICH_UNKNOWN, + CHIPSET_ICH7 = 7, + CHIPSET_ICH8, + CHIPSET_ICH9, + CHIPSET_ICH10, + CHIPSET_5_SERIES_IBEX_PEAK, + CHIPSET_6_SERIES_COUGAR_POINT, + CHIPSET_7_SERIES_PANTHER_POINT +}; + +void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity); + +struct ich_desc_content { + uint32_t FLVALSIG; /* 0x00 */ + union { /* 0x04 */ + uint32_t FLMAP0; + struct { + uint32_t FCBA :8, /* Flash Component Base Address */ + NC :2, /* Number Of Components */ + :6, + FRBA :8, /* Flash Region Base Address */ + NR :3, /* Number Of Regions */ + :5; + }; + }; + union { /* 0x08 */ + uint32_t FLMAP1; + struct { + uint32_t FMBA :8, /* Flash Master Base Address */ + NM :3, /* Number Of Masters */ + :5, + FISBA :8, /* Flash ICH Strap Base Address */ + ISL :8; /* ICH Strap Length */ + }; + }; + union { /* 0x0c */ + uint32_t FLMAP2; + struct { + uint32_t FMSBA :8, /* Flash (G)MCH Strap Base Addr. */ + MSL :8, /* MCH Strap Length */ + :16; + }; + }; +}; + +struct ich_desc_component { + union { /* 0x00 */ + uint32_t FLCOMP; /* Flash Components Register */ + struct { + uint32_t comp1_density :3, + comp2_density :3, + :11, + freq_read :3, + fastread :1, + freq_fastread :3, + freq_write :3, + freq_read_id :3, + :2; + }; + }; + union { /* 0x04 */ + uint32_t FLILL; /* Flash Invalid Instructions Register */ + struct { + uint32_t invalid_instr0 :8, + invalid_instr1 :8, + invalid_instr2 :8, + invalid_instr3 :8; + }; + }; + union { /* 0x08 */ + uint32_t FLPB; /* Flash Partition Boundary Register */ + struct { + uint32_t FPBA :13, /* Flash Partition Boundary Addr */ + :19; + }; + }; +}; + +struct ich_desc_region { + union { + uint32_t FLREGs[5]; + struct { + struct { /* FLREG0 Flash Descriptor */ + uint32_t reg0_base :13, + :3, + reg0_limit :13, + :3; + }; + struct { /* FLREG1 BIOS */ + uint32_t reg1_base :13, + :3, + reg1_limit :13, + :3; + }; + struct { /* FLREG2 ME */ + uint32_t reg2_base :13, + :3, + reg2_limit :13, + :3; + }; + struct { /* FLREG3 GbE */ + uint32_t reg3_base :13, + :3, + reg3_limit :13, + :3; + }; + struct { /* FLREG4 Platform */ + uint32_t reg4_base :13, + :3, + reg4_limit :13, + :3; + }; + }; + }; +}; + +struct ich_desc_master { + union { + uint32_t FLMSTR1; + struct { + uint32_t BIOS_req_ID :16, + BIOS_descr_r :1, + BIOS_BIOS_r :1, + BIOS_ME_r :1, + BIOS_GbE_r :1, + BIOS_plat_r :1, + :3, + BIOS_descr_w :1, + BIOS_BIOS_w :1, + BIOS_ME_w :1, + BIOS_GbE_w :1, + BIOS_plat_w :1, + :3; + }; + }; + union { + uint32_t FLMSTR2; + struct { + uint32_t ME_req_ID :16, + ME_descr_r :1, + ME_BIOS_r :1, + ME_ME_r :1, + ME_GbE_r :1, + ME_plat_r :1, + :3, + ME_descr_w :1, + ME_BIOS_w :1, + ME_ME_w :1, + ME_GbE_w :1, + ME_plat_w :1, + :3; + }; + }; + union { + uint32_t FLMSTR3; + struct { + uint32_t GbE_req_ID :16, + GbE_descr_r :1, + GbE_BIOS_r :1, + GbE_ME_r :1, + GbE_GbE_r :1, + GbE_plat_r :1, + :3, + GbE_descr_w :1, + GbE_BIOS_w :1, + GbE_ME_w :1, + GbE_GbE_w :1, + GbE_plat_w :1, + :3; + }; + }; +}; + +struct ich_descriptors { + struct ich_desc_content content; + struct ich_desc_component component; + struct ich_desc_region region; + struct ich_desc_master master; +}; + +void prettyprint_ich_descriptors(enum ich_chipset, const struct ich_descriptors *desc); + +void prettyprint_ich_descriptor_content(const struct ich_desc_content *content); +void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc); +void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc); +void prettyprint_ich_descriptor_master(const struct ich_desc_master *master); + +int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc); + +#endif /* __ICH_DESCRIPTORS_H__ */ +#endif /* defined(__i386__) || defined(__x86_64__) */ diff --git a/ichspi.c b/ichspi.c index 8b4210e..ad0b536 100644 --- a/ichspi.c +++ b/ichspi.c @@ -29,6 +29,7 @@ #include "flash.h" #include "programmer.h" #include "spi.h" +#include "ich_descriptors.h" /* ICH9 controller register definition */ #define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ @@ -119,6 +120,16 @@ #define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */ #define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */ +#define ICH8_REG_VSCC 0xC1 /* 32 Bits Vendor Specific Component Capabilities */ +#define ICH9_REG_LVSCC 0xC4 /* 32 Bits Host Lower Vendor Specific Component Capabilities */ +#define ICH9_REG_UVSCC 0xC8 /* 32 Bits Host Upper Vendor Specific Component Capabilities */ +/* The individual fields of the VSCC registers are defined in the file + * ich_descriptors.h. The reason is that the same layout is also used in the + * flash descriptor to define the properties of the different flash chips + * supported. The BIOS (or the ME?) is responsible to populate the ICH registers + * with the information from the descriptor on startup depending on the actual + * chip(s) detected. */ + #define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */ #define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */ #define FPB_FPBA (0x1FFF << FPB_FPBA_OFF) @@ -1129,9 +1140,6 @@ static int ich_spi_send_multicommand(struct spi_command *cmds) #define ICH_BRWA(x) ((x >> 8) & 0xff) #define ICH_BRRA(x) ((x >> 0) & 0xff) -#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff) -#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff) - static void do_ich9_spi_frap(uint32_t frap, int i) { static const char *const access_names[4] = { @@ -1158,9 +1166,8 @@ static void do_ich9_spi_frap(uint32_t frap, int i) return; } - msg_pdbg("0x%08x-0x%08x is %s\n", - (base << 12), (limit << 12) | 0x0fff, - access_names[rwperms]); + msg_pdbg("0x%08x-0x%08x is %s\n", base, (limit | 0x0fff), + access_names[rwperms]); } static const struct spi_programmer spi_programmer_ich7 = { @@ -1190,6 +1197,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, uint8_t old, new; uint16_t spibar_offset, tmp2; uint32_t tmp; + int ichspi_desc = 0; switch (ich_generation) { case 7: @@ -1261,6 +1269,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } + if (tmp2 & HSFS_FDV) + ichspi_desc = 1; tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); @@ -1308,12 +1318,38 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, mmio_readl(ich_spibar + ICH9_REG_OPMENU)); msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + ICH9_REG_OPMENU + 4)); - ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); - msg_pdbg("0xA0: 0x%08x (BBAR)\n", - ichspi_bbar); - tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); - msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + if (ich_generation == 8) { + tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC); + msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp); + msg_pdbg("VSCC: "); + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); + } else { + ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); + msg_pdbg("0xA0: 0x%08x (BBAR)\n", + ichspi_bbar); + + tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); + msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); + msg_pdbg("LVSCC: "); + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); + + tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); + msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); + msg_pdbg("UVSCC: "); + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); + + tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); + msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + } + msg_pdbg("\n"); + if (ichspi_desc) { + struct ich_descriptors desc = {{ 0 }}; + if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == + RET_OK) + prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, + &desc); + } ich_init_opcodes(); break; default: -- 1.7.1

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[commit] r1441 - trunk
by repository service 15 Sep '11

15 Sep '11

Author: stefanct Date: Thu Sep 15 00:09:48 2011 New Revision: 1441 URL: http://flashrom.org/trac/flashrom/changeset/1441 Log: Add printing of chip voltage ranges to print_wiki.c - add voltage ranges - center some headers (test values OK, No, ? are centered via wiki templates) - fix style error in header (align:right -> text-align:right) Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/print_wiki.c Modified: trunk/print_wiki.c ============================================================================== --- trunk/print_wiki.c Wed Sep 14 01:14:25 2011 (r1440) +++ trunk/print_wiki.c Thu Sep 15 00:09:48 2011 (r1441) @@ -29,7 +29,8 @@ static const char wiki_header[] = "= Supported devices =\n\n\ <div style=\"margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; \ -background-color:#eeeeee; align:right; border:1px solid #aabbcc;\"><small>\n\ +background-color:#eeeeee; text-align:right; border:1px solid #aabbcc;\">\ +<small>\n\ Please do '''not''' edit these tables in the wiki directly, they are \ generated by pasting '''flashrom -z''' output.<br />\ '''Last update:''' %s(generated by flashrom %s)\n</small></div>\n"; @@ -37,12 +38,13 @@ #if CONFIG_INTERNAL == 1 static const char chipset_th[] = "{| border=\"0\" style=\"font-size: smaller\"\n\ |- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ -! align=\"left\" | Southbridge\n! align=\"left\" | PCI IDs\n\ -! align=\"left\" | Status\n\n"; +! align=\"left\" | Southbridge\n! align=\"center\" | PCI IDs\n\ +! align=\"center\" | Status\n\n"; static const char board_th[] = "{| border=\"0\" style=\"font-size: smaller\" \ valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ -! align=\"left\" | Mainboard\n! align=\"left\" | Required option\n! align=\"left\" | Status\n\n"; +! align=\"left\" | Mainboard\n! align=\"left\" | Required option\n\ +! align=\"center\" | Status\n\n"; static const char board_intro[] = "\ \n== Supported mainboards ==\n\n\ @@ -57,20 +59,26 @@ further verified mainboards on the [[Mailinglist|mailing list]].\n"; #endif -static const char chip_th[] = "{| border=\"0\" style=\"font-size: smaller\" \ -valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ -! align=\"left\" | Device\n! align=\"left\" | Size / kB\n\ -! align=\"left\" | Type\n! align=\"left\" colspan=\"4\" | Status\n\n\ +static const char chip_th[] = "{\ +| border=\"0\" style=\"font-size: smaller\" valign=\"top\"\n\ +|- bgcolor=\"#6699dd\"\n\ +! align=\"left\" | Vendor\n\ +! align=\"left\" | Device\n\ +! align=\"center\" | Size [kB]\n\ +! align=\"center\" | Type\n\ +! align=\"center\" colspan=\"4\" | Status\n\ +! align=\"center\" colspan=\"2\" | Voltage [V]\n\n\ |- bgcolor=\"#6699ff\"\n| colspan=\"4\" |  \n\ -| Probe\n| Read\n| Erase\n| Write\n\n"; +| Probe\n| Read\n| Erase\n| Write\n\ +| align=\"center\" | min \n| align=\"center\" | max\n\n"; static const char programmer_section[] = "\ \n== Supported programmers ==\n\nThis is a list \ of supported PCI devices flashrom can use as programmer:\n\n{| border=\"0\" \ valign=\"top\"\n| valign=\"top\"|\n\n{| border=\"0\" style=\"font-size: \ smaller\" valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ -! align=\"left\" | Device\n! align=\"left\" | PCI IDs\n\ -! align=\"left\" | Status\n\n"; +! align=\"left\" | Device\n! align=\"center\" | PCI IDs\n\ +! align=\"center\" | Status\n\n"; #if CONFIG_INTERNAL == 1 static const char laptop_intro[] = "\n== Supported laptops/notebooks ==\n\n\ @@ -204,6 +212,8 @@ const struct flashchip *f, *old = NULL; uint32_t t; char *s; + char vmax[6]; + char vmin[6]; for (f = flashchips; f->name != NULL; f++) { /* Don't count "unknown XXXX SPI chip" entries. */ @@ -227,8 +237,13 @@ t = f->tested; s = flashbuses_to_text(f->bustype); - printf("|- bgcolor=\"#%s\"\n| %s || %s || %d " - "|| %s || {{%s}} || {{%s}} || {{%s}} || {{%s}}\n", + sprintf(vmin, "%0.03f", f->voltage.min / (double)1000); + sprintf(vmax, "%0.03f", f->voltage.max / (double)1000); + /* '{{%s}}' is used in combination with 'OK', 'No' and '?3' to + * select special formatting templates for the bg color. */ + printf("|- bgcolor=\"#%s\"\n| %s || %s || align=\"right\" | %d " + "|| %s || {{%s}} || {{%s}} || {{%s}} || {{%s}}" + "|| %s || %s \n", (c == 1) ? "eeeeee" : "dddddd", f->vendor, f->name, f->total_size, s, (t & TEST_OK_PROBE) ? "OK" : @@ -238,7 +253,9 @@ (t & TEST_OK_ERASE) ? "OK" : (t & TEST_BAD_ERASE) ? "No" : "?3", (t & TEST_OK_WRITE) ? "OK" : - (t & TEST_BAD_WRITE) ? "No" : "?3"); + (t & TEST_BAD_WRITE) ? "No" : "?3", + f->voltage.min ? vmin : "N/A", + f->voltage.min ? vmax : "N/A"); free(s); /* Split table into 'cols' columns. */

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Re: [flashrom] [PATCH 2/2] add printing of chip voltage ranges to print_wiki.c
by Uwe Hermann 14 Sep '11

14 Sep '11

On Mon, Jun 27, 2011 at 06:30:14AM +0200, Stefan Tauner wrote: > static const char wiki_header[] = "= Supported devices =\n\n\ > <div style=\"margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; \ > -background-color:#eeeeee; align:right; border:1px solid #aabbcc;\"><small>\n\ > +background-color:#eeeeee; text-align:right; border:1px solid #aabbcc;\">\ > +<small>\n\ Correct, but not sure if this was supposed to be right-aligned anyway. The output looks different with the patch, but it's nice too :) > -static const char chip_th[] = "{| border=\"0\" style=\"font-size: smaller\" \ > -valign=\"top\"\n|- bgcolor=\"#6699dd\"\n! align=\"left\" | Vendor\n\ > -! align=\"left\" | Device\n! align=\"left\" | Size / kB\n\ > -! align=\"left\" | Type\n! align=\"left\" colspan=\"4\" | Status\n\n\ > +static const char chip_th[] = "{\ > +| border=\"0\" style=\"font-size: smaller\"valign=\"top\"\n\ ^ Missing space, this screws up the output. > +|- bgcolor=\"#6699dd\"\n\ > +! align=\"left\" | Vendor\n\ > +! align=\"left\" | Device\n\ > +! align=\"center\" | Size [kB]\n\ ^ Please replace the space with " " here. > +! align=\"center\" | Type\n\ > +! align=\"center\" colspan=\"4\" | Status\n\ > +! align=\"center\" colspan=\"2\" | Voltage [V]\n\n\ ^ Ditto. > |- bgcolor=\"#6699ff\"\n| colspan=\"4\" |  \n\ > -| Probe\n| Read\n| Erase\n| Write\n\n"; > +| Probe\n| Read\n| Erase\n| Write\n\ > +| align=\"center\" | min \n| align=\"center\" | max\n\n"; Maybe "Min" and "Max", but lower-case is fine too, I guess. > + const char *na = "N/A"; > > for (f = flashchips; f->name != NULL; f++) > chipcount++; > @@ -223,8 +234,13 @@ static void print_supported_chips_wiki(int cols) > > t = f->tested; > s = flashbuses_to_text(f->bustype); > - printf("|- bgcolor=\"#%s\"\n| %s || %s || %d " > - "|| %s || {{%s}} || {{%s}} || {{%s}} || {{%s}}\n", > + sprintf(vmin, "%0.03f", f->voltage.min/(double)1000); > + sprintf(vmax, "%0.03f", f->voltage.max/(double)1000); Missing spaces before and after the "/". > + f->voltage.min ? vmin : na, > + f->voltage.min ? vmax : na); Hm, the 'na' variable is not really needed or useful I think, just write "N/A" twice. Otherwise the patch is Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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