Hi!
I tried to write something fancy into those DMI lines (they currently say "to be filled by O.E.M.")...
but flashrom doesnt seem to support my main board (verbose output is attached)...
is there a trick to change those lines?
thx.
Bye
Arne
Am 01.05.2012 01:28 schrieb Michael Karcher:
> Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de>
Thanks for the documentation patch.
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>
Regards,
Carl-Daniel
--
http://www.hailfinger.org/
Author: mkarcher
Date: Sat May 5 22:53:59 2012
New Revision: 1530
URL: http://flashrom.org/trac/flashrom/changeset/1530
Log:
Add manpage entry for pony_spi
Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>
Modified:
trunk/flashrom.8
Modified: trunk/flashrom.8
==============================================================================
--- trunk/flashrom.8 Sat May 5 22:43:42 2012 (r1529)
+++ trunk/flashrom.8 Sat May 5 22:53:59 2012 (r1530)
@@ -201,6 +201,9 @@
.BR "* rayer_spi" " (for SPI flash ROMs attached to a RayeR parport "
or Xilinx DLC5 compatible cable)
.sp
+.BR "* pony_spi" " (for SPI flash ROMs attached to a SI-Prog serial port "
+bitbanging adapter)
+.sp
.BR "* nicintel_spi" " (for SPI flash ROMs on Intel Gigabit network cards)"
.sp
.BR "* ogp_spi" " (for SPI flash ROMs on Open Graphics Project graphics card)"
@@ -614,6 +617,26 @@
The schematic of the Xilinx DLC 5 was published at
.BR "http://www.xilinx.com/itp/xilinx4/data/docs/pac/appendixb.html " .
.SS
+.BR "pony_spi " programmer
+The serial port (like /dev/ttyS0, /dev/ttyUSB0 on Linux or COM3 on windows) is
+specified using the mandatory
+.B dev
+parameter. The adapter type is selectable between SI-Prog (used for
+SPI devices with PonyProg 2000) or a custom made serial bitbanging programmer
+named "serbang". The optional
+.B type
+parameter accepts the values "si_prog" (default) or "serbang".
+.sp
+Information about the SI-Prog adapter can be found at
+.BR "http://www.lancos.com/siprogsch.html " .
+.sp
+An example call to flashrom is
+.sp
+.B " flashrom \-p pony_spi:dev=/dev/ttyS0,type=serbang"
+.sp
+Please note that while USB-to-serial adapters work under certain circumstances,
+this slows down operation considerably.
+.SS
.BR "ogp_spi " programmer
The flash ROM chip to access must be specified with the
.B rom
Adds a function to enable the flash interface on w83697xx superio's.
Still needs to be hooked up to the superio detection framework though.
Signed-off-by: David Borg <borg.db(a)gmail.com>
Author: hailfinger
Date: Sat May 5 22:43:42 2012
New Revision: 1529
URL: http://flashrom.org/trac/flashrom/changeset/1529
Log:
Function to enable the flash interface on w83697 family SuperIO chips.
Not hooked up to the superio detection framework yet.
Signed-off-by: David Borg <borg.db(a)gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>
Modified:
trunk/board_enable.c
Modified: trunk/board_enable.c
==============================================================================
--- trunk/board_enable.c Wed May 2 22:08:01 2012 (r1528)
+++ trunk/board_enable.c Sat May 5 22:43:42 2012 (r1529)
@@ -380,6 +380,39 @@
w836xx_ext_leave(port);
}
+/**
+ * Enable MEMW# and set ROM size to max.
+ * Supported chips:
+ * W83697HF/F/HG, W83697SF/UF/UG
+ */
+void w83697xx_memw_enable(uint16_t port)
+{
+ w836xx_ext_enter(port);
+ if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
+ if((sio_read(port, 0x2A) & 0xF0) == 0xF0) {
+
+ /* CR24 Bits 7 & 2 must be set to 0 enable the flash ROM */
+ /* address segments 000E0000h ~ 000FFFFFh on W83697SF/UF/UG */
+ /* These bits are reserved on W83697HF/F/HG */
+ /* Shouldn't be needed though. */
+
+ /* CR28 Bit3 must be set to 1 to enable flash access to */
+ /* FFE80000h ~ FFEFFFFFh on W83697SF/UF/UG. */
+ /* This bit is reserved on W83697HF/F/HG which default to 0 */
+ sio_mask(port, 0x28, 0x08, 0x08);
+
+ /* Enable MEMW# and set ROM size select to max. (4M)*/
+ sio_mask(port, 0x24, 0x28, 0x38);
+
+ } else {
+ msg_perr("WARNING: Flash interface in use by GPIO!\n");
+ }
+ } else {
+ msg_pinfo("BIOS ROM is disabled\n");
+ }
+ w836xx_ext_leave(port);
+}
+
/*
* Suited for:
* - EPoX EP-8K5A2: VIA KT333 + VT8235
Hi,
coreboot has a requirement to store some data in flash to get some
chipsets to work well. There are multiple ways to achieve this:
1. Write flashing code from scratch. Pointless.
2. Use parts of the flashrom codebase or libflashrom. Advantages:
coreboot and flashrom developers often work on both projects, enabling
better cooperation. flashrom has the best chipset/flash support out there.
3. Use parts of the U-Boot codebase (which has drivers derived from
flashrom). Advantages: The codebase is designed with firmware
constraints in mind. http://review.coreboot.org/997 seems to implement this.
As a flashrom developer, I would like to see flashrom code used in
coreboot, and I'm very interested in finding and fixing any obstacles to
that goal.
Patrick, I think you worked on the coreboot patch mentioned above. Could
you tell us about your reasons for choosing option 3, and how we can
make option 2 viable?
Regards,
Carl-Daniel
--
http://www.hailfinger.org/