flashrom

flashrom@flashrom.org

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9188 discussions

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by claude 19 May '12

19 May '12

MSI P6NGM motherboard claude@claude-MS-7366:~$ sudo flashrom -V flashrom v0.9.5.2-r1517 on Linux 3.2.0-24-generic (x86_64), built with libpci 3.1.8, GCC 4.6.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1972M loops per second, 10 myus = 10 us, 100 myus = 97 us, 1000 myus = 965 us, 10000 myus = 11415 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "MSI" DMI string system-product-name: "MS-7366" DMI string system-version: "1.0" DMI string baseboard-manufacturer: "MSI" DMI string baseboard-product-name: "MS-7366" DMI string baseboard-version: "1.0" DMI string chassis-type: "Desktop" Found chipset "NVIDIA MCP73" with PCI ID 10de:07d7. Enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 Flash bus type is LPC Found SMBus device 10de:07d8 at 00:03:1 MCP SPI BAR is at 0xfeb80000 Strange. MCP SPI BAR is valid, but chipset apparently doesn't have SPI enabled. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. The following protocols are supported: LPC. Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xd7, id2 0x99, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xd7, id2 0x99, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xd7, id2 0x99, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xd7, id2 0x99, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xd7, id2 0x99, id1 parity violation, id1 is normal flash content, id2 is normal flash content No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. Restoring PCI config space for 00:03:0 reg 0x6d Restoring PCI config space for 00:03:0 reg 0x90 Restoring PCI config space for 00:03:0 reg 0x8c Restoring PCI config space for 00:03:0 reg 0x88 claude@claude-MS-7366:~$

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Re: [flashrom] PONY_SPI, patch to support a new programmer (AJAWe)
by Stefan Tauner 18 May '12

18 May '12

On Fri, 11 May 2012 14:50:17 +0200 Virgil-Adrian Teaca <darkstarlinux(a)gmail.com> wrote: > There is a new patch for pony_spi, to add support for a new serial > programmer, produced by AJAWe. i asked them for a sample to test or someone that might be able to test it on their hardware. they replied quickly, but are not interested at all. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] DQ965GF
by Stefan Tauner 17 May '12

17 May '12

On Tue, 15 May 2012 03:19:53 +0300 gabris <gabris.t(a)gmail.com> wrote: > Hello, as written in flashrom I'm sending verbose log which is from Intel > DQ965GF motherboard running Q965, Mandriva 2010.2 as OS. it has SST25VF016B > Bioschip. > Hello gabris, thanks for your report! I have added the board to our list of (un)supported boards (with an appropriate note) and will commit that later together with other small changes. It wont change anything regarding support of the board, but i would like to see the output of flashrom -VV -r image.tmp It will try to read the whole flash chip and will fail and i want to know where. This test is safe. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH] Remove sharplhf00l04.c
by Carl-Daniel Hailfinger 15 May '12

15 May '12

Am 20.06.2011 01:13 schrieb Michael Karcher: > The currently unreferenced function in sharplhf00l04.c does a standard > FWH block protection reset (writes 0 to the protection register) and a > standard FWH block erase. > > The locking blocks of the FWH block lock cover 128KB areas, and thats > the only thing page_size is used for in the functions referenced in the > LHF00L04 entry. > My datasheet talks about 8 kB sectors and 64 kB blocks in "Figure 3. Memory Map", but "Table 8. FWH Flash Registers Configuration Map" only mentions registers for the 8 kB sectors in the top 64 kB block explicitly. "Table 8" also mentions "XX002H Whole Block Lock Register" as generic placeholder, and AFAICS those two X mean you have one block lock register for each of the 15 bottom 64 kB blocks and one for each of the 8 top 8 kB sectors. That also means the 82802ab unlocking as is can't be used. I was unable to find any 128 kB reference in my datasheet, so I'm going to Nack that part. > Finally, this adds a comment that there are non-volatile (flash memory) > lock bits for 8 sectors in the last 64KB. They are write-only and clearable > at once. Readback seems unsupported. > I have a slightly different interpretation of the datasheet (see above), so I'm not sure how to proceed. > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > Killing sharplhf00l04.c is a good thing, though, so that part is Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

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[commit] r1538 - trunk
by repository service 15 May '12

15 May '12

Author: stefanct Date: Wed May 16 02:15:53 2012 New Revision: 1538 URL: http://flashrom.org/trac/flashrom/changeset/1538 Log: Remove sharplhf00l04.c. The currently unreferenced function in sharplhf00l04.c does a standard FWH block protection reset (writes 0 to the protection register) and a standard FWH block erase. Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Deleted: trunk/sharplhf00l04.c Modified: trunk/Makefile Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Wed May 16 00:58:19 2012 (r1537) +++ trunk/Makefile Wed May 16 02:15:53 2012 (r1538) @@ -260,7 +260,7 @@ CHIP_OBJS = jedec.o stm50flw0x0x.o w39.o w29ee011.o \ sst28sf040.o m29f400bt.o 82802ab.o pm49fl00x.o \ - sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o sharplhf00l04.o \ + sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o \ a25.o at25.o opaque.o sfdp.o en29lv640b.o LIB_OBJS = layout.o

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Re: [flashrom] [PATCH] ft2232_spi.c: add frequency divider parameter.
by Samir Ibradžić 15 May '12

15 May '12

On 2012年02月28日 10:48, Stefan Tauner wrote: > This adds an extra argument when using the ft2232_spi programmer to set > the frequency divider. The valid values for the divider is any even integer > between 2 and 131072. > > Signed-off-by: Samir Ibradžić<sibradzic(a)gmail.com> > Signed-off-by: Stefan Tauner<stefan.tauner(a)student.tuwien.ac.at> > > --- > this was totally broken even without Samir's version of the patch applied. > it might be a better idea to let the user specify the actual frequency instead of > the divisor like some other programmers do (serprog and buspirate). Well, it may be more clear to specify exact frequencies, but we may end up with weird set of frequencies for all these large dividers. Maybe it would be better to support a limited set of "standard" dividers and their corresponding frequencies, like: divider | freq --------+-------- 2 | 30MHz 4 | 15MHz 6 | 10MHz 8 | 7.5MHz 10 | 6MHz 12 | 5MHz 20 | 3MHz 30 | 2MHz 60 | 1MHz 80 | 750KHz 100 | 600KHz 120 | 500KHz 150 | 400KHz 200 | 300KHz 300 | 200KHz 600 | 100KHz 800 | 75KHz 1000 | 60KHz 1200 | 50KHz 1500 | 40KHz 2000 | 30KHz 3000 | 20KHz 6000 | 10KHz 8000 | 7.5KHz (and so on) But i vote for supporting specific divider after all, one can never know if there is some obscure device out there in the wild that supports only 6365372Hz. > TODO: man page > --- > ft2232_spi.c | 54 +++++++++++++++++++++++++++++++++++++----------------- > 1 files changed, 37 insertions(+), 17 deletions(-) > > diff --git a/ft2232_spi.c b/ft2232_spi.c > index 122866f..7d598b1 100644 > --- a/ft2232_spi.c > +++ b/ft2232_spi.c > @@ -64,17 +64,8 @@ const struct usbdev_status devs_ft2232spi[] = { > {}, > }; > > -/* > - * The 'H' chips can run internally at either 12MHz or 60MHz. > - * The non-H chips can only run at 12MHz. > - */ > -static uint8_t clock_5x = 1; > > -/* > - * In either case, the divisor is a simple integer clock divider. > - * If clock_5x is set, this divisor divides 30MHz, else it divides 6MHz. > - */ > -#define DIVIDE_BY 3 /* e.g. '3' will give either 10MHz or 2MHz SPI clock. */ > +#define DEFAULT_DIVISOR 2 > > #define BITMODE_BITBANG_NORMAL 1 > #define BITMODE_BITBANG_SPI 2 > @@ -162,12 +153,28 @@ static const struct spi_programmer spi_programmer_ft2232 = { > /* Returns 0 upon success, a negative number upon errors. */ > int ft2232_spi_init(void) > { > - int f, ret = 0; > + int ret = 0; > struct ftdi_context *ftdic =&ftdic_context; > unsigned char buf[512]; > int ft2232_vid = FTDI_VID; > int ft2232_type = FTDI_FT4232H_PID; > enum ftdi_interface ft2232_interface = INTERFACE_B; > + /* > + * The 'H' chips can run with an internal clock of either 12 MHz or 60 MHz, > + * but the non-H chips can only run at 12 MHz. We enable the divide-by-5 > + * prescaler on the former to run on the same speed. > + */ > + uint8_t clock_5x = 1; > + /* In addition to the prescaler mentioned above there is also another > + * configurable one on all versions of the chips. Its divisor div can be > + * set by a 16 bit value x according to the following formula: > + * div = (1 + x) * 2<-> x = div / 2 - 1 > + * Hence the expressible divisors are all even numbers between 2 and > + * 2^17 (=131072) resulting in SCK frequencies of 2 MHz down to about > + * 92 Hz for 12 MHz inputs. > + */ > + uint32_t divisor = DEFAULT_DIVISOR; > + int f; > char *arg; > double mpsse_clk; > > @@ -243,6 +250,21 @@ int ft2232_spi_init(void) > } > } > free(arg); > + arg = extract_programmer_param("divisor"); > + if (arg&& strlen(arg)) { > + unsigned int temp = 0; > + char *endptr; > + temp = strtoul(arg,&endptr, 10); > + if (*endptr || temp< 2 || temp> 131072 || temp& 0x1) { > + msg_perr("Error: Invalid SPI frequency divisor specified: \"%s\".\n" > + "Valid are even values between 2 and 131072.\n", arg); > + free(arg); > + return -2; > + } else { > + divisor = (uint32_t)temp; > + } > + } > + free(arg); > msg_pdbg("Using device type %s %s ", > get_ft2232_vendorname(ft2232_vid, ft2232_type), > get_ft2232_devicename(ft2232_vid, ft2232_type)); > @@ -303,17 +325,15 @@ int ft2232_spi_init(void) > > msg_pdbg("Set clock divisor\n"); > buf[0] = 0x86; /* command "set divisor" */ > - /* valueL/valueH are (desired_divisor - 1) */ > - buf[1] = (DIVIDE_BY - 1)& 0xff; > - buf[2] = ((DIVIDE_BY - 1)>> 8)& 0xff; > if (send_buf(ftdic, buf, 3)) { > ret = -6; > goto ftdi_err; > } > + buf[1] = (divisor / 2 - 1)& 0xff; > + buf[2] = ((divisor / 2 - 1)>> 8)& 0xff; > > - msg_pdbg("MPSSE clock: %f MHz divisor: %d " > - "SPI clock: %f MHz\n", mpsse_clk, DIVIDE_BY, > - (double)(mpsse_clk / (((DIVIDE_BY - 1) + 1) * 2))); > + msg_pdbg("MPSSE clock: %f MHz, divisor: %u, SPI clock: %f MHz\n", > + mpsse_clk, divisor, (double)(mpsse_clk / divisor)); > > /* Disconnect TDI/DO to TDO/DI for loopback. */ > msg_pdbg("No loopback of TDI/DO TDO/DI\n");

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[commit] r1537 - trunk
by repository service 15 May '12

15 May '12

Author: stefanct Date: Wed May 16 00:58:19 2012 New Revision: 1537 URL: http://flashrom.org/trac/flashrom/changeset/1537 Log: ft2232_spi.c: add frequency divisor parameter. This adds an optional argument when using the ft2232_spi programmer to set the frequency divisor. The valid values for the divisor is any even integer between 2 and 131072. Signed-off-by: Samir Ibradžić <sibradzic(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/flashrom.8 trunk/ft2232_spi.c Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Tue May 15 00:54:58 2012 (r1536) +++ trunk/flashrom.8 Wed May 16 00:58:19 2012 (r1537) @@ -549,6 +549,17 @@ .B 4232H and the default interface is .BR B . +.sp +All models supported by the ft2232_spi driver can configure the SPI clock rate by setting a divisor. The +expressible divisors are all even numbers between 2 and 2^17 (=131072) resulting in SPI clock frequencies of +6 MHz down to about 92 Hz for 12 MHz inputs. The default divisor is set to 2, but you can use another one by +specifying the optional +.B divisor +parameter with the +.sp +.B " flashrom \-p ft2232_spi:divisor=div" +.sp +syntax. .SS .BR "serprog " programmer A mandatory parameter specifies either a serial Modified: trunk/ft2232_spi.c ============================================================================== --- trunk/ft2232_spi.c Tue May 15 00:54:58 2012 (r1536) +++ trunk/ft2232_spi.c Wed May 16 00:58:19 2012 (r1537) @@ -64,17 +64,8 @@ {}, }; -/* - * The 'H' chips can run internally at either 12MHz or 60MHz. - * The non-H chips can only run at 12MHz. - */ -static uint8_t clock_5x = 1; -/* - * In either case, the divisor is a simple integer clock divider. - * If clock_5x is set, this divisor divides 30MHz, else it divides 6MHz. - */ -#define DIVIDE_BY 3 /* e.g. '3' will give either 10MHz or 2MHz SPI clock. */ +#define DEFAULT_DIVISOR 2 #define BITMODE_BITBANG_NORMAL 1 #define BITMODE_BITBANG_SPI 2 @@ -162,12 +153,28 @@ /* Returns 0 upon success, a negative number upon errors. */ int ft2232_spi_init(void) { - int f, ret = 0; + int ret = 0; struct ftdi_context *ftdic = &ftdic_context; unsigned char buf[512]; int ft2232_vid = FTDI_VID; int ft2232_type = FTDI_FT4232H_PID; enum ftdi_interface ft2232_interface = INTERFACE_B; + /* + * The 'H' chips can run with an internal clock of either 12 MHz or 60 MHz, + * but the non-H chips can only run at 12 MHz. We enable the divide-by-5 + * prescaler on the former to run on the same speed. + */ + uint8_t clock_5x = 1; + /* In addition to the prescaler mentioned above there is also another + * configurable one on all versions of the chips. Its divisor div can be + * set by a 16 bit value x according to the following formula: + * div = (1 + x) * 2 <-> x = div / 2 - 1 + * Hence the expressible divisors are all even numbers between 2 and + * 2^17 (=131072) resulting in SCK frequencies of 6 MHz down to about + * 92 Hz for 12 MHz inputs. + */ + uint32_t divisor = DEFAULT_DIVISOR; + int f; char *arg; double mpsse_clk; @@ -243,6 +250,21 @@ } } free(arg); + arg = extract_programmer_param("divisor"); + if (arg && strlen(arg)) { + unsigned int temp = 0; + char *endptr; + temp = strtoul(arg, &endptr, 10); + if (*endptr || temp < 2 || temp > 131072 || temp & 0x1) { + msg_perr("Error: Invalid SPI frequency divisor specified: \"%s\".\n" + "Valid are even values between 2 and 131072.\n", arg); + free(arg); + return -2; + } else { + divisor = (uint32_t)temp; + } + } + free(arg); msg_pdbg("Using device type %s %s ", get_ft2232_vendorname(ft2232_vid, ft2232_type), get_ft2232_devicename(ft2232_vid, ft2232_type)); @@ -303,17 +325,15 @@ msg_pdbg("Set clock divisor\n"); buf[0] = 0x86; /* command "set divisor" */ - /* valueL/valueH are (desired_divisor - 1) */ - buf[1] = (DIVIDE_BY - 1) & 0xff; - buf[2] = ((DIVIDE_BY - 1) >> 8) & 0xff; if (send_buf(ftdic, buf, 3)) { ret = -6; goto ftdi_err; } + buf[1] = (divisor / 2 - 1) & 0xff; + buf[2] = ((divisor / 2 - 1) >> 8) & 0xff; - msg_pdbg("MPSSE clock: %f MHz divisor: %d " - "SPI clock: %f MHz\n", mpsse_clk, DIVIDE_BY, - (double)(mpsse_clk / (((DIVIDE_BY - 1) + 1) * 2))); + msg_pdbg("MPSSE clock: %f MHz, divisor: %u, SPI clock: %f MHz\n", + mpsse_clk, divisor, (double)(mpsse_clk / divisor)); /* Disconnect TDI/DO to TDO/DI for loopback. */ msg_pdbg("No loopback of TDI/DO TDO/DI\n");

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Chipset A49LF040A : Alix 1D --- Warning report and lspci report
by Joao Bonina 15 May '12

15 May '12

Alix 1D Url: http://pcengines.ch/alix1d.htm root@nst100:/boot# flashrom -p internal:laptop=this_is_not_a_laptop flashrom v0.9.5.2-r1517 on Linux 2.6.38-bpo.2-486 (i586), built with libpci 3.1.9, GCC 4.6.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... delay loop is unreliable, trying to continue OK. ======================================================================== WARNING! You may be running flashrom on an unsupported laptop. We could not detect this for sure because your vendor has not setup the SMBIOS tables correctly. You can enforce execution by adding '-p internal:laptop=this_is_not_a_laptop' to the command line, but please read the following warning if you are not sure. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Proceeding anyway because user forced us to. Found chipset "AMD CS5536". Enabling flash write... OK. WARNING: unexpected second chipset match: "AMD CS5536" ignoring, please report lspci and board URL to flashrom(a)flashrom.org with 'CHIPSET: your board name' in the subject line. Found AMIC flash chip "A49LF040A" (512 kB, LPC) at physical address 0xfff80000. No operations were specified. root@nst100:/boot# lspci 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 33) 00:01.1 VGA compatible controller: Advanced Micro Devices [AMD] Geode LX Video 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block 00:0c.0 Multimedia audio controller: VIA Technologies Inc. VT1720/24 [Envy24PT/HT] PCI Multi-Channel Audio Controller (rev 01) 00:0d.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96) 00:0f.0 ISA bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA (rev 03) 00:0f.2 IDE interface: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE (rev 01) 00:0f.4 USB controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02) 00:0f.5 USB controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02)

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Re: [flashrom] Test report Biostar M7VIQ - Chip now detected, reading works
by Carl-Daniel Hailfinger 15 May '12

15 May '12

Am 15.05.2012 01:53 schrieb Gurken Papst: > On Mon, May 7, 2012 at 2:52 AM, Stefan Tauner > <stefan.tauner(a)student.tuwien.ac.at> wrote: >> > if you like please test the current svn HEAD flashrom on all boards with >> > a winbond superio and send us the usual flashrom -V output, thanks! > Ok, here is the new result. I suppose the line "Found Winbond Super > I/O, id 60" is telling me detection is working as expected? > > flashrom v0.9.5.2-r1534 on Linux 3.2.0-23-generic-pae (i686), built > with libpci 3.0.0, GCC 4.4.3, little endian > Calibrating delay loop... OS timer resolution is 1 usecs, 820M loops > per second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 985 us, > 10000 myus = 9857 us, 4 myus = 4 us, OK. > Initializing internal programmer > DMI string baseboard-product-name: "KM266-8235" > DMI string baseboard-version: " " > DMI string chassis-type: "Desktop" > Found Winbond Super I/O, id 60 Excellent, I can work with that. Expect an updated patch in the next few days. Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] Using flashrom with EliteGroup ECS GF8200A motherboard
by Stefan Tauner 14 May '12

14 May '12

On Sun, 6 May 2012 21:46:07 -0300 Denilson Figueiredo de Sá <denilsonsa(a)gmail.com> wrote: > Today I updated the BIOS of my EliteGroup ECS GF8200A motherboard. > […] > Following help from carldani and twice11, I tried flashing again the > new firmware. This time it worked and gave me no errors. The output is > also attached. thanks for the mail. since flashrom works in general on that board i have added it to our list of supported boards. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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