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Numonyx N25Q064 (second try)
by David Hendricks 25 Jul '12

25 Jul '12

This patch differentiates between the N25Q064 1.8V version and 3.0V version which have different JEDEC IDs. It extends the chip name to include the first few characters in the part number. The first two of those characters indicate the process technology (65nm) and feature set, neither of which matter for Flashrom. The third and fourth characters specify voltage and block/sector size and uniformity, which are important. To abstract the irrelevant portions of the part number leading up to the characters we care about, dots are used. This helps prevent unwanted changes in chip name that can break fragile scripts and confuse people. More about this schema here: http://www.flashrom.org/pipermail/flashrom/2012-July/009595.html Signed-off-by: David Hendricks <dhendrix(a)google.com> Index: flashchips.c =================================================================== --- flashchips.c (revision 1553) +++ flashchips.c (working copy) @@ -5425,12 +5425,16 @@ { .vendor = "Numonyx", - .name = "N25Q064", + /* ..1E = 1.8V, uniform 64KB/4KB blocks/sectors */ + .name = "N25Q064..1E", .bustype = BUS_SPI, .manufacture_id = ST_ID, - .model_id = ST_N25Q064, + .model_id = ST_N25Q064__1E, .total_size = 8192, .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -5450,9 +5454,44 @@ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, + .voltage = {1700, 2000}, }, { + .vendor = "Numonyx", + /* ..3E = 3V, uniform 64KB/4KB blocks/sectors */ + .name = "N25Q064..3E", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q064__3E, + .total_size = 8192, + .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048 } }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { .vendor = "PMC", .name = "Pm25LV010", .bustype = BUS_SPI, Index: flashchips.h =================================================================== --- flashchips.h (revision 1553) +++ flashchips.h (working copy) @@ -586,7 +586,8 @@ #define ST_M29W010B 0x23 #define ST_M29W040B 0xE3 #define ST_M29W512B 0x27 -#define ST_N25Q064 0xBA17 +#define ST_N25Q064__3E 0xBA17 /* N25Q064, 3V, 64KB/4KB blocks/sectors */ +#define ST_N25Q064__1E 0xBB17 /* N25Q064, 1.8V, 64KB/4KB blocks/sectors */ #define SYNCMOS_MVC_ID 0x40 /* SyncMOS (SM) and Mosel Vitelic Corporation (MVC) */ #define MVC_V29C51000T 0x00 -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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Re: [flashrom] How to suffix similar-but-different parts?
by Stefan Tauner 25 Jul '12

25 Jul '12

On Wed, 25 Jul 2012 14:49:38 -0700 David Hendricks <dhendrix(a)google.com> wrote: > > alternatively we could just ignore that problem (it is a future problem > > after all) and use N25Q064A11 and N25Q064A13. > > > > Please let's not do that :-) It causes headaches if the information > presented falls out of date or shows up incorrect. we cant predict what vendors do. if they decide to give N25Q064B13 another id the .. representation is not correct too. we cant save the world just make it as good as we can :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] How to suffix similar-but-different parts?
by Stefan Tauner 25 Jul '12

25 Jul '12

On Wed, 25 Jul 2012 12:14:33 -0700 David Hendricks <dhendrix(a)google.com> wrote: > There's a SPI chip named "N25Q064" with 1.8V and 3V variants N25Q064A11 and > N25Q064A13, respectively. The 1.8V has A11 suffixed, and the 3V version has > A13 suffixed. The 'A' indicates the process technology which is likely to > change without a change of device ID, so it's likely that we'll see > something like N25Q064B11 or N25Q064B13 in the future. > > Fortunately, the two variants have different JEDEC IDs (0xBA17 and 0xBB17). > So at least we can tell them apart via probing. > > stefanct and I were discussing how to name this chip couldn't really come > up with a good solution. I am thinking that "N25Q064" is sufficient and > that we should just re-use the same .name for two chip entries with > different .voltage parameters. > > Thoughts? > datasheets for the devices in question: <dhendrix> 3V version: http://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/S… <dhendrix> 1.8V version: http://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/S… david: you dont give a rationale why you think that N25Q064 is enough. my argumnt why it is not enough: the .name is used to distinguish what flashrom defines as individual chips when presenting them to the user. so it is not enough that flashrom can distinguish the chips by their IDs but also the user must be able to tell the difference hence there must be no duplicative names. fwiw: i think we need a place holder for "any character" in model names and propose "." so in this case: N25Q064..1 N25Q064..3 rationale: easily understandable, regex semantic, not part of actual chip names, non-distracting. alternatively we could just ignore that problem (it is a future problem after all) and use N25Q064A11 and N25Q064A13. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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How to suffix similar-but-different parts?
by David Hendricks 25 Jul '12

25 Jul '12

There's a SPI chip named "N25Q064" with 1.8V and 3V variants N25Q064A11 and N25Q064A13, respectively. The 1.8V has A11 suffixed, and the 3V version has A13 suffixed. The 'A' indicates the process technology which is likely to change without a change of device ID, so it's likely that we'll see something like N25Q064B11 or N25Q064B13 in the future. Fortunately, the two variants have different JEDEC IDs (0xBA17 and 0xBB17). So at least we can tell them apart via probing. stefanct and I were discussing how to name this chip couldn't really come up with a good solution. I am thinking that "N25Q064" is sufficient and that we should just re-use the same .name for two chip entries with different .voltage parameters. Thoughts? -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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Re: [flashrom] Flashrom on stock X60(s)
by Stefan Tauner 24 Jul '12

24 Jul '12

On Tue, 10 Jul 2012 19:24:21 +0200 Tomasz Ostaszewski <tomasz.ostaszewski(a)interia.pl> wrote: > Hi all. > I want to flash on of my X60s with a coreboot using flashrom. I did > search the flashrom list archive, and I found the "FAILED: MX25L1605 > on Thinkpad X60s" (http://bit.ly/NetLop) and related "Lenovo T60 Type > 8743-GZU - RAM Support? 3Gb or 4Gb" (http://bit.ly/Mfhi1W) threads. > Despite what the heading says, those threads do treat about a > successful flashing of a stock X60s with flahshrom utility. There is > is almost a complete descripton of what to do, and what to use. > However, for me there's one piece of the puzzle missing - the patch. > Peter writes: > > "[..]You need the flashrom source, a small patch, and my bucts utility > from http://git.stuge.se/?p=bucts.git" > > The flashrom is readily available from SVN, the bucts from git, but > what are the patches and where to get them from? > And, if worst comes to the worst and I brick my X60s, would I be able > to resurrect it using a programmer and a SOIC-8 clip > (http://bit.ly/Nj8Sdx)? Or rather (de)soldering would be necessary? the patch(es) and bucts are needed because the chipset is locked down by the vendor bios so much that vanilla flashrom can not cope with it (and modifying it so that it does is neither worth it nor trivial). please ask the coreboot guys about the details of the procedure. afaik desoldering is not necessary but an external programmer. if you already know the complete procedure please ask for a coreboot wiki account and create an article about it. it is recurring regularly here and on the coreboot ml (and obviously no one cares to document it fully). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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EN25QH16 (2MiB) READ/PROBE success
by andrew＠ncrmnt.org 24 Jul '12

24 Jul '12

Hello, Just reporting a chip marked as UNTESTED as working. Checked: Probe, Read. Write untested, read produced good bootable results. Used buspirate_spi programmer. Log attached. Regards, Andrew.

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Re: [flashrom] annotate Numonyx/Micron N25Q064
by Stefan Tauner 24 Jul '12

24 Jul '12

On Tue, 24 Jul 2012 15:17:02 -0700 David Hendricks <dhendrix(a)google.com> wrote: > This adds the following: > - missing feature_bits to indicate WREN required before WRSR and the > presence of OTP bytes > - a comment mentioning SFDP support > - voltage range > > Signed-off-by: David Hendricks <dhendrix(a)google.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Thanks for that! i'll commit it in my tested_stuff branch (soon-ish). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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annotate Numonyx/Micron N25Q064
by David Hendricks 24 Jul '12

24 Jul '12

This adds the following: - missing feature_bits to indicate WREN required before WRSR and the presence of OTP bytes - a comment mentioning SFDP support - voltage range Signed-off-by: David Hendricks <dhendrix(a)google.com> Index: flashchips.c =================================================================== --- flashchips.c (revision 1553) +++ flashchips.c (working copy) @@ -5431,6 +5431,9 @@ .model_id = ST_N25Q064, .total_size = 8192, .page_size = 256, + /* supports SFDP */ + /* OTP: 64B total; read 0x4B, write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -5450,6 +5453,7 @@ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, + .voltage = {2700, 3600}, }, { -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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Re: [flashrom] [PATCH] Intel QM77
by Stefan Tauner 24 Jul '12

24 Jul '12

On Tue, 24 Jul 2012 10:19:29 +0200 "Wagner, Helge (GE Germany)" <Helge.Wagner(a)ge.com> wrote: > Hi all, > > Please find attached our changes for the QM77 chipset. I looked at the > datasheet to be sure that the strap names (SPI, PCI, LPC) are the same > as on the series 5 and 6 chipsets. > > Signed-off-by: Helge Wagner <Helge.Wagner(a)ge.com> Thanks for your patch, committed in r1553 without a code change. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1553 - trunk
by repository service 24 Jul '12

24 Jul '12

Author: stefanct Date: Tue Jul 24 18:33:55 2012 New Revision: 1553 URL: http://flashrom.org/trac/flashrom/changeset/1553 Log: Intel 7 Series fixes (addition of QM77, fixed straps printing). I looked at the datasheet to be sure that the strap names (SPI, PCI, LPC) are the same as on the series 5 and 6 chipsets. Signed-off-by: Helge Wagner <Helge.Wagner(a)ge.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/chipset_enable.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Sun Jul 22 14:01:43 2012 (r1552) +++ trunk/chipset_enable.c Tue Jul 24 18:33:55 2012 (r1553) @@ -526,7 +526,7 @@ static const char *const straps_names_EP80579[] = { "SPI", "reserved", "reserved", "LPC" }; static const char *const straps_names_ich7_nm10[] = { "reserved", "SPI", "PCI", "LPC" }; static const char *const straps_names_ich8910[] = { "SPI", "SPI", "PCI", "LPC" }; - static const char *const straps_names_pch56[] = { "LPC", "reserved", "PCI", "SPI" }; + static const char *const straps_names_pch567[] = { "LPC", "reserved", "PCI", "SPI" }; static const char *const straps_names_unknown[] = { "unknown", "unknown", "unknown", "unknown" }; switch (ich_generation) { @@ -546,7 +546,8 @@ break; case CHIPSET_5_SERIES_IBEX_PEAK: case CHIPSET_6_SERIES_COUGAR_POINT: - straps_names = straps_names_pch56; + case CHIPSET_7_SERIES_PANTHER_POINT: + straps_names = straps_names_pch567; break; default: msg_gerr("%s: unknown ICH generation. Please report!\n", @@ -1298,6 +1299,7 @@ {0x8086, 0x1e46, NT, "Intel", "Z75", enable_flash_pch7}, {0x8086, 0x1e49, NT, "Intel", "B75", enable_flash_pch7}, {0x8086, 0x1e4a, NT, "Intel", "H77", enable_flash_pch7}, + {0x8086, 0x1e55, OK, "Intel", "QM77", enable_flash_pch7}, {0x8086, 0x1e57, NT, "Intel", "HM77", enable_flash_pch7}, {0x8086, 0x1e58, NT, "Intel", "UM77", enable_flash_pch7}, {0x8086, 0x1e59, NT, "Intel", "HM76", enable_flash_pch7},

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