flashrom

flashrom@flashrom.org

1 participants
9187 discussions

help
by 杜新雷 07 Jan '13

07 Jan '13

hello, Os :fedora 14 Linux 2.6.35.6-45.fc14.i686 (i686) Flashrom version : v0.9.4-r1455 #flashrom -r sysbios.bin error: mainboards information Flash chip VendorSouthbridgePCI IDsStatus intelHM658086:1c49? embedded controller mode SIO chip： IT8782 vendor :ITE mainboards VendormainboardsRequired Status topstarTEB-H8100 Hope to be able to make support topstar motherboard of TEB - H8100 flashrom program to ease of use, thank you! David Best regard！

2 1

flashrom -p gfxnvidia detect my atheros ath9k wifi card
by Denis 'GNUtoo' Carikli 07 Jan '13

07 Jan '13

Hi, Here are the logs: # ./flashrom -p gfxnvidia -VVV flashrom v0.9.5.2-r1546 on Linux 3.0.0-19-generic-pae (i686) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.7, GCC 4.6.1, little endian Command line (3 args): ./flashrom -p gfxnvidia -VVV Calibrating delay loop... OS timer resolution is 1 usecs, 1503M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1000 us, 10000 myus = 10007 us, 4 myus = 4 us, OK. Initializing gfxnvidia programmer Found "NVIDIA RIVA TNT2 Ultra" (168c:0029, BDF 03:06.0). PCI header type 0x00 Requested BAR is MEM, 32bit, not prefetchable === This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output to flashrom(a)flashrom.org if it works for you. Please add the name of your PCI device to the subject. Thank you for your help! === Detected NVIDIA I/O base address: 0xd8600000. The following protocols are supported: Parallel. Probing for AMD Am29F010A/B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BB, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BT, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BB, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BB, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BT, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BB, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BT, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C512, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C010A, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C040A, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49BV512, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49F002(N), 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49F002(N)T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49F020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49F040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Catalyst CAT28F512, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Bright BM29F040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for EMST F49B002UA, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29LV640B, 8192 kB: probe_en29lv640b: id1 0xffff, id2 0x00ff Probing for Fujitsu MBM29F004BC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Fujitsu MBM29F400TC, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Hyundai HY29F002T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Hyundai HY29F002B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Hyundai HY29F040A, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BN/BX-B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BN/BX-T, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F002BC/BL/BV/BX-T, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F008S3/S5/SC, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-T, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-T, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002(N)B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002(N)T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51000B, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51000T, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51400B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51400T, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29LC51000, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29LC51001, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29LC51002, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002T, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV512, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LH28F008BJT-BTLZ1, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST28SF040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29LE010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE020A, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29LE020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF512, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF010A, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF020A, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF512, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF080, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BB, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29F400BT, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29W010B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RB, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012-old, 128 kB: Old Winbond W29* probe method disabled because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29C010(M)/W29C011A/W29EE011/W29EE012-old' if you have a board with such a chip. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C020(C)/W29C022, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C040/P, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39L040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U/N, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. Restoring PCI config space for 03:06:0 reg 0x50 # lspci -n 00:00.0 0600: 1022:9601 00:01.0 0604: 1022:9602 00:0a.0 0604: 1022:9609 00:11.0 0106: 1002:4390 00:12.0 0c03: 1002:4397 00:12.1 0c03: 1002:4398 00:12.2 0c03: 1002:4396 00:13.0 0c03: 1002:4397 00:13.1 0c03: 1002:4398 00:13.2 0c03: 1002:4396 00:14.0 0c05: 1002:4385 (rev 3c) 00:14.1 0101: 1002:439c 00:14.2 0403: 1002:4383 00:14.3 0601: 1002:439d 00:14.4 0604: 1002:4384 00:14.5 0c03: 1002:4399 00:18.0 0600: 1022:1200 00:18.1 0600: 1022:1201 00:18.2 0600: 1022:1202 00:18.3 0600: 1022:1203 00:18.4 0600: 1022:1204 01:05.0 0300: 1002:9710 01:05.1 0403: 1002:970f 02:00.0 0200: 10ec:8168 (rev 03) 03:06.0 0280: 168c:0029 (rev 01) # lspci 00:00.0 Host bridge: Advanced Micro Devices [AMD] RS880 Host Bridge 00:01.0 PCI bridge: Advanced Micro Devices [AMD] RS780/RS880 PCI to PCI bridge (int gfx) 00:0a.0 PCI bridge: Advanced Micro Devices [AMD] RS780/RS880 PCI to PCI bridge (PCIE port 5) 00:11.0 SATA controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 SATA Controller [IDE mode] 00:12.0 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI0 Controller 00:12.1 USB Controller: ATI Technologies Inc SB7x0 USB OHCI1 Controller 00:12.2 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB EHCI Controller 00:13.0 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI0 Controller 00:13.1 USB Controller: ATI Technologies Inc SB7x0 USB OHCI1 Controller 00:13.2 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB EHCI Controller 00:14.0 SMBus: ATI Technologies Inc SBx00 SMBus Controller (rev 3c) 00:14.1 IDE interface: ATI Technologies Inc SB7x0/SB8x0/SB9x0 IDE Controller 00:14.2 Audio device: ATI Technologies Inc SBx00 Azalia (Intel HDA) 00:14.3 ISA bridge: ATI Technologies Inc SB7x0/SB8x0/SB9x0 LPC host controller 00:14.4 PCI bridge: ATI Technologies Inc SBx00 PCI to PCI Bridge 00:14.5 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 00:18.0 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor HyperTransport Configuration 00:18.1 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Address Map 00:18.2 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Miscellaneous Control 00:18.4 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Link Control 01:05.0 VGA compatible controller: ATI Technologies Inc RS880 [Radeon HD 4200] 01:05.1 Audio device: ATI Technologies Inc RS880 Audio Device [Radeon HD 4200] 02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller (rev 03) 03:06.0 Network controller: Atheros Communications Inc. AR922X Wireless Network Adapter (rev 01) Denis.

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(no subject)
by Andrei Slavoiu 06 Jan '13

06 Jan '13

http://www.theleak.co.uk/wp-content/themes/twentyten/dwncst.php?jqcw=jqcw

1 0

[PATCH] remove exit call from pcidev_init
by Niklas Söderlund 06 Jan '13

06 Jan '13

If the function fails it returns 0. All callers have been made aware of this and are prepared to handle it. Signed-off-by: Niklas Söderlund <niso(a)kth.se> --- atahpt.c | 2 ++ drkaiser.c | 2 ++ gfxnvidia.c | 2 ++ nic3com.c | 2 ++ nicintel.c | 7 +++---- nicintel_spi.c | 2 ++ nicnatsemi.c | 2 ++ nicrealtek.c | 2 ++ ogp_spi.c | 2 ++ pcidev.c | 6 +++--- satamv.c | 5 ++--- satasii.c | 3 ++- 12 files changed, 26 insertions(+), 11 deletions(-) diff --git a/atahpt.c b/atahpt.c index b692b88..4c1b13e 100644 --- a/atahpt.c +++ b/atahpt.c @@ -71,6 +71,8 @@ int atahpt_init(void) return 1; io_base_addr = pcidev_init(PCI_BASE_ADDRESS_4, ata_hpt); + if (!io_base_addr) + return 1; /* Enable flash access. */ reg32 = pci_read_long(pcidev_dev, REG_FLASH_ACCESS); diff --git a/drkaiser.c b/drkaiser.c index d4b6120..ffabf9b 100644 --- a/drkaiser.c +++ b/drkaiser.c @@ -71,6 +71,8 @@ int drkaiser_init(void) return 1; addr = pcidev_init(PCI_BASE_ADDRESS_2, drkaiser_pcidev); + if (!addr) + return 1; /* Write magic register to enable flash write. */ rpci_write_word(pcidev_dev, PCI_MAGIC_DRKAISER_ADDR, diff --git a/gfxnvidia.c b/gfxnvidia.c index 457172d..fe2362a 100644 --- a/gfxnvidia.c +++ b/gfxnvidia.c @@ -95,6 +95,8 @@ int gfxnvidia_init(void) return 1; io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, gfx_nvidia); + if (!io_base_addr) + return 1; io_base_addr += 0x300000; msg_pinfo("Detected NVIDIA I/O base address: 0x%x.\n", io_base_addr); diff --git a/nic3com.c b/nic3com.c index 4df720f..27d9506 100644 --- a/nic3com.c +++ b/nic3com.c @@ -91,6 +91,8 @@ int nic3com_init(void) return 1; io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_3com); + if (!io_base_addr) + return 1; id = pcidev_dev->device_id; diff --git a/nicintel.c b/nicintel.c index f2d4529..7d6fa94 100644 --- a/nicintel.c +++ b/nicintel.c @@ -77,11 +77,10 @@ int nicintel_init(void) if (get_io_perms()) return 1; - /* No need to check for errors, pcidev_init() will not return in case - * of errors. - * FIXME: BAR2 is not available if the device uses the CardBus function. - */ + /* FIXME: BAR2 is not available if the device uses the CardBus function. */ addr = pcidev_init(PCI_BASE_ADDRESS_2, nics_intel); + if (!addr) + return 1; nicintel_bar = physmap("Intel NIC flash", addr, NICINTEL_MEMMAP_SIZE); if (nicintel_bar == ERROR_PTR) diff --git a/nicintel_spi.c b/nicintel_spi.c index 7eb3af3..af7347b 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -171,6 +171,8 @@ int nicintel_spi_init(void) return 1; io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_intel_spi); + if (!io_base_addr) + return 1; nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, 4096); diff --git a/nicnatsemi.c b/nicnatsemi.c index c39637a..d16984d 100644 --- a/nicnatsemi.c +++ b/nicnatsemi.c @@ -63,6 +63,8 @@ int nicnatsemi_init(void) return 1; io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_natsemi); + if (!io_base_addr) + return 1; if (register_shutdown(nicnatsemi_shutdown, NULL)) return 1; diff --git a/nicrealtek.c b/nicrealtek.c index f808e06..17a3172 100644 --- a/nicrealtek.c +++ b/nicrealtek.c @@ -65,6 +65,8 @@ int nicrealtek_init(void) return 1; io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_realtek); + if (!io_base_addr) + return 1; if (register_shutdown(nicrealtek_shutdown, NULL)) return 1; diff --git a/ogp_spi.c b/ogp_spi.c index 8502847..dc62d7d 100644 --- a/ogp_spi.c +++ b/ogp_spi.c @@ -132,6 +132,8 @@ int ogp_spi_init(void) return 1; io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, ogp_spi); + if (!io_base_addr) + return 1; ogp_spibar = physmap("OGP registers", io_base_addr, 4096); diff --git a/pcidev.c b/pcidev.c index e8b4dc1..c32027c 100644 --- a/pcidev.c +++ b/pcidev.c @@ -207,7 +207,7 @@ uintptr_t pcidev_init(int bar, const struct pcidev_status *devs) if (pcidev_bdf != NULL) { if ((msg = pci_filter_parse_slot(&filter, pcidev_bdf))) { msg_perr("Error: %s\n", msg); - exit(1); + return 0; } } free(pcidev_bdf); @@ -228,13 +228,13 @@ uintptr_t pcidev_init(int bar, const struct pcidev_status *devs) /* Only continue if exactly one supported PCI dev has been found. */ if (found == 0) { msg_perr("Error: No supported PCI device found.\n"); - exit(1); + return 0; } else if (found > 1) { msg_perr("Error: Multiple supported PCI devices found. " "Use 'flashrom -p xxxx:pci=bb:dd.f' \n" "to explicitly select the card with the given BDF " "(PCI bus, device, function).\n"); - exit(1); + return 0; } return curaddr; diff --git a/satamv.c b/satamv.c index 0b83a14..f23af3b 100644 --- a/satamv.c +++ b/satamv.c @@ -89,10 +89,9 @@ int satamv_init(void) return 1; /* BAR0 has all internal registers memory mapped. */ - /* No need to check for errors, pcidev_init() will not return in case - * of errors. - */ addr = pcidev_init(PCI_BASE_ADDRESS_0, satas_mv); + if (!addr) + return 1; mv_bar = physmap("Marvell 88SX7042 registers", addr, 0x20000); if (mv_bar == ERROR_PTR) diff --git a/satasii.c b/satasii.c index 75378be..ac70129 100644 --- a/satasii.c +++ b/satasii.c @@ -73,7 +73,8 @@ int satasii_init(void) if (get_io_perms()) return 1; - pcidev_init(PCI_BASE_ADDRESS_0, satas_sii); + if (!pcidev_init(PCI_BASE_ADDRESS_0, satas_sii)) + return 1; id = pcidev_dev->device_id; -- 1.7.11.1

2 1

[commit] r1644 - trunk
by repository service 06 Jan '13

06 Jan '13

Author: hailfinger Date: Sun Jan 6 00:52:45 2013 New Revision: 1644 URL: http://flashrom.org/trac/flashrom/changeset/1644 Log: Decouple BAR reading from pci device init, handle errors gracefully. pcidev_init() now returns struct pci_device * instead of a BAR stored in PCI config space. This allows for real error checking instead of having exit(1) everywhere in pcidev.c. Thanks to Niklas Söderlund for coming up with the original error handling patch which was slightly modified and folded into this patch. Move the declaration of struct pci_device in programmer.h before the first user. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/atahpt.c trunk/drkaiser.c trunk/gfxnvidia.c trunk/nic3com.c trunk/nicintel.c trunk/nicintel_spi.c trunk/nicnatsemi.c trunk/nicrealtek.c trunk/ogp_spi.c trunk/pcidev.c trunk/programmer.h trunk/satamv.c trunk/satasii.c Modified: trunk/atahpt.c ============================================================================== --- trunk/atahpt.c Fri Jan 4 23:54:07 2013 (r1643) +++ trunk/atahpt.c Sun Jan 6 00:52:45 2013 (r1644) @@ -58,17 +58,22 @@ int atahpt_init(void) { + struct pci_dev *dev = NULL; uint32_t reg32; if (rget_io_perms()) return 1; - io_base_addr = pcidev_init(PCI_BASE_ADDRESS_4, ata_hpt); + dev = pcidev_init(ata_hpt, PCI_BASE_ADDRESS_4); + if (!dev) + return 1; + + io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_4); /* Enable flash access. */ - reg32 = pci_read_long(pcidev_dev, REG_FLASH_ACCESS); + reg32 = pci_read_long(dev, REG_FLASH_ACCESS); reg32 |= (1 << 24); - rpci_write_long(pcidev_dev, REG_FLASH_ACCESS, reg32); + rpci_write_long(dev, REG_FLASH_ACCESS, reg32); register_par_programmer(&par_programmer_atahpt, BUS_PARALLEL); Modified: trunk/drkaiser.c ============================================================================== --- trunk/drkaiser.c Fri Jan 4 23:54:07 2013 (r1643) +++ trunk/drkaiser.c Sun Jan 6 00:52:45 2013 (r1644) @@ -64,17 +64,20 @@ int drkaiser_init(void) { + struct pci_dev *dev = NULL; uint32_t addr; if (rget_io_perms()) return 1; - /* No need to check for errors, pcidev_init() will not return in case of errors. */ - addr = pcidev_init(PCI_BASE_ADDRESS_2, drkaiser_pcidev); + dev = pcidev_init(drkaiser_pcidev, PCI_BASE_ADDRESS_2); + if (!dev) + return 1; + + addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_2); /* Write magic register to enable flash write. */ - rpci_write_word(pcidev_dev, PCI_MAGIC_DRKAISER_ADDR, - PCI_MAGIC_DRKAISER_VALUE); + rpci_write_word(dev, PCI_MAGIC_DRKAISER_ADDR, PCI_MAGIC_DRKAISER_VALUE); /* Map 128kB flash memory window. */ drkaiser_bar = physmap("Dr. Kaiser PC-Waechter flash memory", Modified: trunk/gfxnvidia.c ============================================================================== --- trunk/gfxnvidia.c Fri Jan 4 23:54:07 2013 (r1643) +++ trunk/gfxnvidia.c Sun Jan 6 00:52:45 2013 (r1644) @@ -85,14 +85,17 @@ int gfxnvidia_init(void) { + struct pci_dev *dev = NULL; uint32_t reg32; if (rget_io_perms()) return 1; - /* No need to check for errors, pcidev_init() will not return in case of errors. */ - io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, gfx_nvidia); + dev = pcidev_init(gfx_nvidia, PCI_BASE_ADDRESS_0); + if (!dev) + return 1; + io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); io_base_addr += 0x300000; msg_pinfo("Detected NVIDIA I/O base address: 0x%x.\n", io_base_addr); @@ -102,9 +105,9 @@ return 1; /* Allow access to flash interface (will disable screen). */ - reg32 = pci_read_long(pcidev_dev, 0x50); + reg32 = pci_read_long(dev, 0x50); reg32 &= ~(1 << 0); - rpci_write_long(pcidev_dev, 0x50, reg32); + rpci_write_long(dev, 0x50, reg32); /* Write/erase doesn't work. */ programmer_may_write = 0; Modified: trunk/nic3com.c ============================================================================== --- trunk/nic3com.c Fri Jan 4 23:54:07 2013 (r1643) +++ trunk/nic3com.c Sun Jan 6 00:52:45 2013 (r1644) @@ -86,13 +86,18 @@ int nic3com_init(void) { + struct pci_dev *dev = NULL; + if (rget_io_perms()) return 1; - /* No need to check for errors, pcidev_init() will not return in case of errors. */ - io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_3com); + dev = pcidev_init(nics_3com, PCI_BASE_ADDRESS_0); + if (!dev) + return 1; + + io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); - id = pcidev_dev->device_id; + id = dev->device_id; /* 3COM 3C90xB cards need a special fixup. */ if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005 Modified: trunk/nicintel.c ============================================================================== --- trunk/nicintel.c Fri Jan 4 23:54:07 2013 (r1643) +++ trunk/nicintel.c Sun Jan 6 00:52:45 2013 (r1644) @@ -68,6 +68,7 @@ int nicintel_init(void) { + struct pci_dev *dev = NULL; uintptr_t addr; /* Needed only for PCI accesses on some platforms. @@ -76,17 +77,17 @@ if (rget_io_perms()) return 1; - /* No need to check for errors, pcidev_init() will not return in case of errors. - * FIXME: BAR2 is not available if the device uses the CardBus function. - */ - addr = pcidev_init(PCI_BASE_ADDRESS_2, nics_intel); + /* FIXME: BAR2 is not available if the device uses the CardBus function. */ + dev = pcidev_init(nics_intel, PCI_BASE_ADDRESS_2); + if (!dev) + return 1; + addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_2); nicintel_bar = physmap("Intel NIC flash", addr, NICINTEL_MEMMAP_SIZE); if (nicintel_bar == ERROR_PTR) goto error_out_unmap; - /* FIXME: Using pcidev_dev _will_ cause pretty explosions in the future. */ - addr = pcidev_readbar(pcidev_dev, PCI_BASE_ADDRESS_0); + addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); /* FIXME: This is not an aligned mapping. Use 4k? */ nicintel_control_bar = physmap("Intel NIC control/status reg", addr, NICINTEL_CONTROL_MEMMAP_SIZE); Modified: trunk/nicintel_spi.c ============================================================================== --- trunk/nicintel_spi.c Fri Jan 4 23:54:07 2013 (r1643) +++ trunk/nicintel_spi.c Sun Jan 6 00:52:45 2013 (r1644) @@ -166,14 +166,17 @@ int nicintel_spi_init(void) { + struct pci_dev *dev = NULL; uint32_t tmp; if (rget_io_perms()) return 1; - /* No need to check for errors, pcidev_init() will not return in case of errors. */ - io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_intel_spi); + dev = pcidev_init(nics_intel_spi, PCI_BASE_ADDRESS_0); + if (!dev) + return 1; + io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, MEMMAP_SIZE); /* Automatic restore of EECD on shutdown is not possible because EECD Modified: trunk/nicnatsemi.c ============================================================================== --- trunk/nicnatsemi.c Fri Jan 4 23:54:07 2013 (r1643) +++ trunk/nicnatsemi.c Sun Jan 6 00:52:45 2013 (r1644) @@ -52,22 +52,19 @@ .chip_writen = fallback_chip_writen, }; -static int nicnatsemi_shutdown(void *data) -{ - pci_cleanup(pacc); - return 0; -} - int nicnatsemi_init(void) { + struct pci_dev *dev = NULL; + if (rget_io_perms()) return 1; - io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_natsemi); - - if (register_shutdown(nicnatsemi_shutdown, NULL)) + dev = pcidev_init(nics_natsemi, PCI_BASE_ADDRESS_0); + if (!dev) return 1; + io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + /* The datasheet shows address lines MA0-MA16 in one place and MA0-MA15 * in another. My NIC has MA16 connected to A16 on the boot ROM socket * so I'm assuming it is accessible. If not then next line wants to be Modified: trunk/nicrealtek.c ============================================================================== --- trunk/nicrealtek.c Fri Jan 4 23:54:07 2013 (r1643) +++ trunk/nicrealtek.c Sun Jan 6 00:52:45 2013 (r1644) @@ -59,16 +59,19 @@ int nicrealtek_init(void) { + struct pci_dev *dev = NULL; + if (rget_io_perms()) return 1; - /* No need to check for errors, pcidev_init() will not return in case of errors. */ - io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_realtek); - if (register_shutdown(nicrealtek_shutdown, NULL)) + dev = pcidev_init(nics_realtek, PCI_BASE_ADDRESS_0); + if (!dev) return 1; + io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); + /* Beware, this ignores the vendor ID! */ - switch (pcidev_dev->device_id) { + switch (dev->device_id) { case 0x8139: /* RTL8139 */ case 0x1211: /* SMC 1211TX */ default: @@ -81,6 +84,9 @@ break; } + if (register_shutdown(nicrealtek_shutdown, NULL)) + return 1; + register_par_programmer(&par_programmer_nicrealtek, BUS_PARALLEL); return 0; Modified: trunk/ogp_spi.c ============================================================================== --- trunk/ogp_spi.c Fri Jan 4 23:54:07 2013 (r1643) +++ trunk/ogp_spi.c Sun Jan 6 00:52:45 2013 (r1644) @@ -105,6 +105,7 @@ int ogp_spi_init(void) { + struct pci_dev *dev = NULL; char *type; type = extract_programmer_param("rom"); @@ -131,8 +132,11 @@ if (rget_io_perms()) return 1; - io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, ogp_spi); + dev = pcidev_init(ogp_spi, PCI_BASE_ADDRESS_0); + if (!dev) + return 1; + io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); ogp_spibar = physmap("OGP registers", io_base_addr, 4096); if (register_shutdown(ogp_spi_shutdown, NULL)) Modified: trunk/pcidev.c ============================================================================== --- trunk/pcidev.c Fri Jan 4 23:54:07 2013 (r1643) +++ trunk/pcidev.c Sun Jan 6 00:52:45 2013 (r1644) @@ -27,7 +27,6 @@ uint32_t io_base_addr; struct pci_access *pacc; -struct pci_dev *pcidev_dev = NULL; enum pci_bartype { TYPE_MEMBAR, @@ -156,7 +155,6 @@ static int pcidev_shutdown(void *data) { - pcidev_dev = NULL; if (pacc == NULL) { msg_perr("%s: Tried to cleanup an invalid PCI context!\n" "Please report a bug at flashrom(a)flashrom.org\n", __func__); @@ -181,18 +179,24 @@ return 0; } -uintptr_t pcidev_init(int bar, const struct dev_entry *devs) +/* pcidev_init gets an array of allowed PCI device IDs and returns a pointer to struct pci_dev iff exactly one + * match was found. If the "pci=bb:dd.f" programmer parameter was specified, a match is only considered if it + * also matches the specified bus:device.function. + * For convenience, this function also registers its own undo handlers. + */ +struct pci_dev *pcidev_init(const struct dev_entry *devs, int bar) { struct pci_dev *dev; + struct pci_dev *found_dev = NULL; struct pci_filter filter; char *pcidev_bdf; char *msg = NULL; int found = 0; int i; - uintptr_t addr = 0, curaddr = 0; + uintptr_t addr = 0; - if(pci_init_common() != 0) - return 1; + if (pci_init_common() != 0) + return NULL; pci_filter_init(pacc, &filter); /* Filter by bb:dd.f (if supplied by the user). */ @@ -200,7 +204,7 @@ if (pcidev_bdf != NULL) { if ((msg = pci_filter_parse_slot(&filter, pcidev_bdf))) { msg_perr("Error: %s\n", msg); - exit(1); + return NULL; } } free(pcidev_bdf); @@ -230,8 +234,7 @@ * just those with a valid BAR. */ if ((addr = pcidev_readbar(dev, bar)) != 0) { - curaddr = addr; - pcidev_dev = dev; + found_dev = dev; found++; } } @@ -240,14 +243,14 @@ /* Only continue if exactly one supported PCI dev has been found. */ if (found == 0) { msg_perr("Error: No supported PCI device found.\n"); - exit(1); + return NULL; } else if (found > 1) { msg_perr("Error: Multiple supported PCI devices found. Use 'flashrom -p xxxx:pci=bb:dd.f' \n" "to explicitly select the card with the given BDF (PCI bus, device, function).\n"); - exit(1); + return NULL; } - return curaddr; + return found_dev; } enum pci_write_type { Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Fri Jan 4 23:54:07 2013 (r1643) +++ trunk/programmer.h Sun Jan 6 00:52:45 2013 (r1644) @@ -160,8 +160,25 @@ unsigned int half_period; }; -#if CONFIG_INTERNAL == 1 +#if NEED_PCI == 1 struct pci_dev; + +/* pcidev.c */ +// FIXME: These need to be local, not global +extern uint32_t io_base_addr; +extern struct pci_access *pacc; +int pci_init_common(void); +uintptr_t pcidev_readbar(struct pci_dev *dev, int bar); +struct pci_dev *pcidev_init(const struct dev_entry *devs, int bar); +/* rpci_write_* are reversible writes. The original PCI config space register + * contents will be restored on shutdown. + */ +int rpci_write_byte(struct pci_dev *dev, int reg, uint8_t data); +int rpci_write_word(struct pci_dev *dev, int reg, uint16_t data); +int rpci_write_long(struct pci_dev *dev, int reg, uint32_t data); +#endif + +#if CONFIG_INTERNAL == 1 struct penable { uint16_t vendor_id; uint16_t device_id; @@ -232,23 +249,6 @@ void myusec_calibrate_delay(void); void internal_delay(int usecs); -#if NEED_PCI == 1 -/* pcidev.c */ -// FIXME: These need to be local, not global -extern uint32_t io_base_addr; -extern struct pci_access *pacc; -extern struct pci_dev *pcidev_dev; -int pci_init_common(void); -uintptr_t pcidev_readbar(struct pci_dev *dev, int bar); -uintptr_t pcidev_init(int bar, const struct dev_entry *devs); -/* rpci_write_* are reversible writes. The original PCI config space register - * contents will be restored on shutdown. - */ -int rpci_write_byte(struct pci_dev *dev, int reg, uint8_t data); -int rpci_write_word(struct pci_dev *dev, int reg, uint16_t data); -int rpci_write_long(struct pci_dev *dev, int reg, uint32_t data); -#endif - #if CONFIG_INTERNAL == 1 /* board_enable.c */ int board_parse_parameter(const char *boardstring, const char **vendor, const char **model); Modified: trunk/satamv.c ============================================================================== --- trunk/satamv.c Fri Jan 4 23:54:07 2013 (r1643) +++ trunk/satamv.c Sun Jan 6 00:52:45 2013 (r1644) @@ -81,6 +81,7 @@ */ int satamv_init(void) { + struct pci_dev *dev = NULL; uintptr_t addr; uint32_t tmp; @@ -88,11 +89,11 @@ return 1; /* BAR0 has all internal registers memory mapped. */ - /* No need to check for errors, pcidev_init() will not return in case - * of errors. - */ - addr = pcidev_init(PCI_BASE_ADDRESS_0, satas_mv); + dev = pcidev_init(satas_mv, PCI_BASE_ADDRESS_0); + if (!dev) + return 1; + addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); mv_bar = physmap("Marvell 88SX7042 registers", addr, 0x20000); if (mv_bar == ERROR_PTR) return 1; @@ -143,8 +144,7 @@ pci_rmmio_writel(tmp, mv_bar + GPIO_PORT_CONTROL); /* Get I/O BAR location. */ - tmp = pci_read_long(pcidev_dev, PCI_BASE_ADDRESS_2) & - PCI_BASE_ADDRESS_IO_MASK; + tmp = pcidev_readbar(dev, PCI_BASE_ADDRESS_2); /* Truncate to reachable range. * FIXME: Check if the I/O BAR is actually reachable. * This is an arch specific check. Modified: trunk/satasii.c ============================================================================== --- trunk/satasii.c Fri Jan 4 23:54:07 2013 (r1643) +++ trunk/satasii.c Sun Jan 6 00:52:45 2013 (r1644) @@ -76,21 +76,24 @@ int satasii_init(void) { + struct pci_dev *dev = NULL; uint32_t addr; uint16_t reg_offset; if (rget_io_perms()) return 1; - pcidev_init(PCI_BASE_ADDRESS_0, satas_sii); + dev = pcidev_init(satas_sii, PCI_BASE_ADDRESS_0); + if (!dev) + return 1; - id = pcidev_dev->device_id; + id = dev->device_id; if ((id == 0x3132) || (id == 0x3124)) { - addr = pci_read_long(pcidev_dev, PCI_BASE_ADDRESS_0) & ~0x07; + addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); reg_offset = 0x70; } else { - addr = pci_read_long(pcidev_dev, PCI_BASE_ADDRESS_5) & ~0x07; + addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_5); reg_offset = 0x50; }

1 0

Report: Intel DQ77KB KBQ7710H.86A.0046.2012.1122.1629 read
by dpcimanager＠users.sourceforge.net 05 Jan '13

05 Jan '13

flashrom v0.9.6.1-r1622 on Darwin 12.2.0 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.9, LLVM Clang 4.1 ((tags/Apple/clang-421.11.66)), little endian Command line (5 args): ~/Desktop/DPCIManager.app/Contents/MacOS/flashrom -VV -r ~/Downloads/Intel DQ77KB KBQ7710H.86A.0046.2012.1122.1629.rom -p internal Calibrating delay loop... OS timer resolution is 1 usecs, Jan 4 20:28:57 Melanies-Mac-Pro kernel[0]: DirectHW: Driver v1.3 (compiled on Dec 4 2012) loaded. Visit http://www.coresystems.de/ for more information. 470M loops per second, 10 myus = 11 us, 100 myus = 107 us, 1000 myus = 1078 us, 10000 myus = 10432 us, 4 myus = 5 us, OK. Initializing internal programmer Mapping low megabyte at 0x00000400, unaligned size 0xffc00. Mapping low megabyte, 0xffc00 bytes at unaligned 0x00000400. No coreboot table found. DMI string system-manufacturer: " " DMI string system-product-name: " " DMI string system-version: " " DMI string baseboard-manufacturer: "Intel Corporation" DMI string baseboard-product-name: "DQ77KB" DMI string baseboard-version: "AAG40294-401" DMI string chassis-type: "Desktop" Found chipset "Intel Q77" with PCI ID 8086:1e47. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode enabled 0xff600000/0xff200000 FWH decode enabled 0xff500000/0xff100000 FWH decode enabled 0xff400000/0xff000000 FWH decode enabled Maximum FWH chip size: 0x100000 bytes BIOS_CNTL = 0x2a: BIOS Lock Enable: enabled, BIOS Write Enable: disabled WARNING: BIOS region SMM protection is enabled! WARNING: Setting Bios Control at 0xdc from 0x2a to 0x0b on Q77 failed. New value is 0x2a. Root Complex Register Block address = 0xfed1c000 GCS = 0xc61: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 WARNING: SPI Configuration Lockdown activated. Reading OPCODES... done OP Type Pre-OP op[0]: 0x02, write w/ addr, none op[1]: 0x03, read w/ addr, none op[2]: 0x20, write w/ addr, none op[3]: 0x05, read w/o addr, none op[4]: 0x9f, read w/o addr, none op[5]: 0x01, write w/o addr, none op[6]: 0x00, read w/o addr, none op[7]: 0x00, read w/o addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x00 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x005dc0f0 (FADDR) 0x50: 0x00000a0b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b 0x54: 0x00000000 FREG0: WARNING: Flash Descriptor region (0x00000000-0x00000fff) is read-only. 0x58: 0x0bff05c0 FREG1: BIOS region (0x005c0000-0x00bfffff) is read-write. 0x5C: 0x05bf0003 FREG2: WARNING: Management Engine region (0x00003000-0x005bffff) is locked. 0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write. 0x64: 0x00001fff FREG4: Platform Data region is unused. 0x74: 0x00000000 (PR0 is unused) 0x78: 0x00000000 (PR1 is unused) 0x7C: 0x00000000 (PR2 is unused) 0x80: 0x00000000 (PR3 is unused) 0x84: 0x00000000 (PR4 is unused) Please send a verbose log to flashrom(a)flashrom.org if this board is not listed on http://flashrom.org/Supported_hardware#Supported_mainboards yet. Writes have been disabled for safety reasons. You can enforce write support with the ich_spi_force programmer option, but you will most likely harm your hardware! If you force flashrom you will get no support if something breaks. On a few mainboards it is possible to enable write access by setting a jumper (see its documentation or the board itself). 0x90: 0x80 (SSFS) SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 0x91: 0xf94010 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=0, SME=0, SCF=1 0x94: 0x0006 (PREOP) 0x96: 0x043b (OPTYPE) 0x98: 0x05200302 (OPMENU) 0x9C: 0x0000019f (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x00802005 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xC8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 0xD0: 0x00000000 (FPB) Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. === Content Section === FLVALSIG 0x0ff0a55a FLMAP0 0x03040103 FLMAP1 0x12100206 FLMAP2 0x00210120 --- Details --- NR (Number of Regions): 4 FRBA (Flash Region Base Address): 0x040 NC (Number of Components): 2 FCBA (Flash Component Base Address): 0x030 ISL (ICH/PCH Strap Length): 18 FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100 NM (Number of Masters): 3 FMBA (Flash Master Base Address): 0x060 MSL/PSL (MCH/PROC Strap Length): 1 FMSBA (Flash MCH/PROC Strap Base Address): 0x200 === Component Section === FLCOMP 0x0930001c FLILL 0x00000000 --- Details --- Component 1 density: 8 MB Component 2 density: 4 MB Read Clock Frequency: 20 MHz Read ID and Status Clock Freq.: 33 MHz Write and Erase Clock Freq.: 33 MHz Fast Read is supported. Fast Read Clock Frequency: 33 MHz No forbidden opcodes. === Region Section === FLREG0 0x00000000 FLREG1 0x0bff05c0 FLREG2 0x05bf0003 FLREG3 0x00020001 FLREG4 0x00001fff --- Details --- Region 0 (Descr.) 0x00000000 - 0x00000fff Region 1 (BIOS ) 0x005c0000 - 0x00bfffff Region 2 (ME ) 0x00003000 - 0x005bffff Region 3 (GbE ) 0x00001000 - 0x00002fff Region 4 (Platf.) is unused. === Master Section === FLMSTR1 0x0a0b0000 FLMSTR2 0x0c0d0000 FLMSTR3 0x08080118 --- Details --- Descr. BIOS ME GbE Platf. BIOS r rw rw ME r rw rw GbE rw Enabling hardware sequencing due to multiple flash chips detected. SPI Read Configuration: prefetching enabled, caching enabled, PROBLEMS, continuing anyway The following protocols are supported: FWH, Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Found 2 attached SPI flash chips with a combined density of 12288 kB. There is only one partition containing the whole address space (0x000000 - 0xbfffff). There are 3072 erase blocks with 4096 B each. Found Programmer flash chip "Opaque flash chip" (12288 kB, Programmer-specific) at physical address 0x0. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Found Programmer flash chip "Opaque flash chip" (12288 kB, Programmer-specific). Reading flash... Reading 12582912 bytes starting at 0x000000. Transaction error between offset 0x00003000 and 0x0000303f (= 0x00003000 + 63)! Read operation failed!

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Re: [flashrom] [PATCH] Introduce msg_*warn.
by Stefan Tauner 04 Jan '13

04 Jan '13

On Fri, 4 Jan 2013 17:49:45 +0100 Idwer Vollering <vidwer(a)gmail.com> wrote: > 2013/1/4 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at>: > > Also, unify all outputs of "Warning:" and "Error:" to use normal > > capitalization instead of mixing it with all capitals. > > > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > … > Replace 'toss' with 'discard' (as you are going to do), then this is > Acked-by: Idwer Vollering <vidwer(a)gmail.com> Thanks. Adjusted as discussed, fixed the indention problem Carl-Daniel mentioned and committed in r1643. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1643 - trunk
by repository service 04 Jan '13

04 Jan '13

Author: stefanct Date: Fri Jan 4 23:54:07 2013 New Revision: 1643 URL: http://flashrom.org/trac/flashrom/changeset/1643 Log: Introduce msg_*warn. Also, unify all outputs of "Warning:" and "Error:" to use normal capitalization instead of mixing it with all capitals. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Idwer Vollering <vidwer(a)gmail.com> Modified: trunk/board_enable.c trunk/cbtable.c trunk/chipset_enable.c trunk/cli_output.c trunk/dmi.c trunk/flash.h trunk/ichspi.c trunk/internal.c trunk/satasii.c trunk/serprog.c trunk/sst_fwhub.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Fri Jan 4 23:24:58 2013 (r1642) +++ trunk/board_enable.c Fri Jan 4 23:54:07 2013 (r1643) @@ -546,7 +546,7 @@ sio_mask(port, 0x24, 0x28, 0x38); } else { - msg_perr("WARNING: Flash interface in use by GPIO!\n"); + msg_pwarn("Warning: Flash interface in use by GPIO!\n"); } } else { msg_pinfo("BIOS ROM is disabled\n"); @@ -2556,8 +2556,8 @@ if (board->dmi_pattern) { if (!has_dmi_support) { - msg_perr("WARNING: Can't autodetect %s %s, DMI info unavailable.\n", - board->vendor_name, board->board_name); + msg_pwarn("Warning: Can't autodetect %s %s, DMI info unavailable.\n", + board->vendor_name, board->board_name); msg_pinfo("Please supply the board vendor and model name with the " "-p internal:mainboard=<vendor>:<model> option.\n"); continue; @@ -2582,14 +2582,14 @@ return 0; if (!force_boardenable) { - msg_pinfo("WARNING: The mainboard-specific code for %s %s has not been tested,\n" + msg_pwarn("Warning: The mainboard-specific code for %s %s has not been tested,\n" "and thus will not be executed by default. Depending on your hardware,\n" "erasing, writing or even probing can fail without running this code.\n\n" "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n" "\"internal programmer\") for details.\n", board->vendor_name, board->board_name); return 1; } - msg_pinfo("NOTE: Running an untested board enable procedure.\n" + msg_pwarn("NOTE: Running an untested board enable procedure.\n" "Please report success/failure to flashrom(a)flashrom.org.\n"); return 0; } Modified: trunk/cbtable.c ============================================================================== --- trunk/cbtable.c Fri Jan 4 23:24:58 2013 (r1642) +++ trunk/cbtable.c Fri Jan 4 23:54:07 2013 (r1643) @@ -96,9 +96,9 @@ if (!strcasecmp(image_vendor, cb_vendor) && !strcasecmp(image_model, cb_model)) { msg_pdbg2("This coreboot image matches this mainboard.\n"); } else { - msg_pinfo("WARNING: This coreboot image (%s:%s) does not appear to\n" - " be correct for the detected mainboard (%s:%s).\n", - image_vendor, image_model, cb_vendor, cb_model); + msg_perr("This coreboot image (%s:%s) does not appear to\n" + "be correct for the detected mainboard (%s:%s).\n", + image_vendor, image_model, cb_vendor, cb_model); return -1; } Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Fri Jan 4 23:24:58 2013 (r1642) +++ trunk/chipset_enable.c Fri Jan 4 23:54:07 2013 (r1643) @@ -300,11 +300,11 @@ msg_pdbg("BIOS Lock Enable: %sabled, ", (new & (1 << 1)) ? "en" : "dis"); msg_pdbg("BIOS Write Enable: %sabled\n", (new & (1 << 0)) ? "en" : "dis"); if (new & (1 << 5)) - msg_pinfo("WARNING: BIOS region SMM protection is enabled!\n"); + msg_pwarn("Warning: BIOS region SMM protection is enabled!\n"); if (new != wanted) - msg_pinfo("WARNING: Setting Bios Control at 0x%x from 0x%02x to 0x%02x on %s failed.\n" + msg_pwarn("Warning: Setting Bios Control at 0x%x from 0x%02x to 0x%02x on %s failed.\n" "New value is 0x%02x.\n", bios_cntl, old, wanted, name, new); /* Return an error if we could not set the write enable */ @@ -661,7 +661,7 @@ rpci_write_byte(dev, 0x40, val); if (pci_read_byte(dev, 0x40) != val) { - msg_pinfo("\nWARNING: Failed to enable flash write on \"%s\"\n", name); + msg_pwarn("\nWarning: Failed to enable flash write on \"%s\"\n", name); return -1; } @@ -1516,7 +1516,7 @@ if (!dev) continue; if (ret != -2) { - msg_pinfo("WARNING: unexpected second chipset match: " + msg_pwarn("Warning: unexpected second chipset match: " "\"%s %s\"\n" "ignoring, please report lspci and board URL " "to flashrom(a)flashrom.org\n" Modified: trunk/cli_output.c ============================================================================== --- trunk/cli_output.c Fri Jan 4 23:24:58 2013 (r1642) +++ trunk/cli_output.c Fri Jan 4 23:54:07 2013 (r1643) @@ -74,16 +74,15 @@ int ret = 0; FILE *output_type = stdout; - if (level == MSG_ERROR) + if (level < MSG_INFO) output_type = stderr; if (level <= verbose_screen) { va_start(ap, fmt); ret = vfprintf(output_type, fmt, ap); va_end(ap); - /* msg_*spew usually happens inside chip accessors in possibly - * time-critical operations. Don't slow them down by flushing. - */ + /* msg_*spew often happens inside chip accessors in possibly + * time-critical operations. Don't slow them down by flushing. */ if (level != MSG_SPEW) fflush(output_type); } Modified: trunk/dmi.c ============================================================================== --- trunk/dmi.c Fri Jan 4 23:24:58 2013 (r1642) +++ trunk/dmi.c Fri Jan 4 23:54:07 2013 (r1643) @@ -105,7 +105,7 @@ "%s -s %s", dmidecode_command, string_name); dmidecode_pipe = popen(commandline, "r"); if (!dmidecode_pipe) { - msg_perr("DMI pipe open error\n"); + msg_perr("Opening DMI pipe failed!\n"); return NULL; } @@ -127,13 +127,11 @@ } } while (answerbuf[0] == '#'); - /* Toss all output above DMI_MAX_ANSWER_LEN away to prevent - deadlock on pclose. */ + /* Discard all output exceeding DMI_MAX_ANSWER_LEN to prevent deadlock on pclose. */ while (!feof(dmidecode_pipe)) getc(dmidecode_pipe); if (pclose(dmidecode_pipe) != 0) { - msg_pinfo("dmidecode execution unsuccessful - continuing " - "without DMI info\n"); + msg_pwarn("dmidecode execution unsuccessful - continuing without DMI info\n"); return NULL; } @@ -144,7 +142,7 @@ result = strdup(answerbuf); if (!result) - msg_perr("WARNING: Out of memory - DMI support fails"); + msg_pwarn("Warning: Out of memory - DMI support fails"); return result; } Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Fri Jan 4 23:24:58 2013 (r1642) +++ trunk/flash.h Fri Jan 4 23:54:07 2013 (r1643) @@ -271,16 +271,20 @@ #endif enum msglevel { MSG_ERROR = 0, - MSG_INFO = 1, - MSG_DEBUG = 2, - MSG_DEBUG2 = 3, - MSG_SPEW = 4, + MSG_WARN = 1, + MSG_INFO = 2, + MSG_DEBUG = 3, + MSG_DEBUG2 = 4, + MSG_SPEW = 5, }; /* Let gcc and clang check for correct printf-style format strings. */ int print(enum msglevel level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); #define msg_gerr(...) print(MSG_ERROR, __VA_ARGS__) /* general errors */ #define msg_perr(...) print(MSG_ERROR, __VA_ARGS__) /* programmer errors */ #define msg_cerr(...) print(MSG_ERROR, __VA_ARGS__) /* chip errors */ +#define msg_gwarn(...) print(MSG_WARN, __VA_ARGS__) /* general warnings */ +#define msg_pwarn(...) print(MSG_WARN, __VA_ARGS__) /* programmer warnings */ +#define msg_cwarn(...) print(MSG_WARN, __VA_ARGS__) /* chip warnings */ #define msg_ginfo(...) print(MSG_INFO, __VA_ARGS__) /* general info */ #define msg_pinfo(...) print(MSG_INFO, __VA_ARGS__) /* programmer info */ #define msg_cinfo(...) print(MSG_INFO, __VA_ARGS__) /* chip info */ Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Fri Jan 4 23:24:58 2013 (r1642) +++ trunk/ichspi.c Fri Jan 4 23:54:07 2013 (r1643) @@ -1455,7 +1455,7 @@ return 0; } - msg_pinfo("FREG%i: WARNING: %s region (0x%08x-0x%08x) is %s.\n", i, + msg_pwarn("FREG%i: Warning: %s region (0x%08x-0x%08x) is %s.\n", i, region_names[i], base, (limit | 0x0fff), access_names[rwperms]); return 1; @@ -1486,7 +1486,7 @@ } msg_pdbg("0x%02X: 0x%08x ", off, pr); - msg_pinfo("PR%u: WARNING: 0x%08x-0x%08x is %s.\n", i, ICH_FREG_BASE(pr), + msg_pwarn("PR%u: Warning: 0x%08x-0x%08x is %s.\n", i, ICH_FREG_BASE(pr), ICH_FREG_LIMIT(pr) | 0x0fff, access_names[rwperms]); return 1; } @@ -1618,7 +1618,7 @@ mmio_readl(ich_spibar + offs), i); } if (mmio_readw(ich_spibar) & (1 << 15)) { - msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); + msg_pwarn("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } ich_init_opcodes(); @@ -1669,7 +1669,7 @@ msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); prettyprint_ich9_reg_hsfs(tmp2); if (tmp2 & HSFS_FLOCKDN) { - msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); + msg_pwarn("Warning: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } if (tmp2 & HSFS_FDV) @@ -1879,7 +1879,7 @@ msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n", mmio_readw(ich_spibar + 0x6c)); if (mmio_readw(ich_spibar) & (1 << 15)) { - msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); + msg_pwarn("Warning: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } Modified: trunk/internal.c ============================================================================== --- trunk/internal.c Fri Jan 4 23:24:58 2013 (r1642) +++ trunk/internal.c Fri Jan 4 23:54:07 2013 (r1643) @@ -257,7 +257,7 @@ #if defined(__i386__) || defined(__x86_64__) if ((cb_parse_table(&cb_vendor, &cb_model) == 0) && (board_vendor != NULL) && (board_model != NULL)) { if (strcasecmp(board_vendor, cb_vendor) || strcasecmp(board_model, cb_model)) { - msg_pinfo("WARNING: The mainboard IDs set by -p internal:mainboard (%s:%s) do not\n" + msg_pwarn("Warning: The mainboard IDs set by -p internal:mainboard (%s:%s) do not\n" " match the current coreboot IDs of the mainboard (%s:%s).\n", board_vendor, board_model, cb_vendor, cb_model); if (!force_boardmismatch) Modified: trunk/satasii.c ============================================================================== --- trunk/satasii.c Fri Jan 4 23:24:58 2013 (r1642) +++ trunk/satasii.c Fri Jan 4 23:54:07 2013 (r1643) @@ -98,7 +98,7 @@ /* Check if ROM cycle are OK. */ if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26)))) - msg_pinfo("Warning: Flash seems unconnected.\n"); + msg_pwarn("Warning: Flash seems unconnected.\n"); if (register_shutdown(satasii_shutdown, NULL)) return 1; Modified: trunk/serprog.c ============================================================================== --- trunk/serprog.c Fri Jan 4 23:24:58 2013 (r1642) +++ trunk/serprog.c Fri Jan 4 23:54:07 2013 (r1643) @@ -467,7 +467,7 @@ * in a single byte. */ if (sp_docommand(S_CMD_Q_BUSTYPE, 0, NULL, 1, &c)) { - msg_perr("Warning: NAK to query supported buses\n"); + msg_pwarn("Warning: NAK to query supported buses\n"); c = BUS_NONSPI; /* A reasonable default for now. */ } serprog_buses_supported = c; @@ -547,9 +547,8 @@ buf[3] = (f_spi_req >> (3 * 8)) & 0xFF; if (sp_check_commandavail(S_CMD_S_SPI_FREQ) == 0) - msg_perr(MSGHEADER "Warning: Setting the SPI clock rate is not supported!\n"); - else if (sp_docommand(S_CMD_S_SPI_FREQ, 4, buf, 4, buf) - == 0) { + msg_pwarn(MSGHEADER "Warning: Setting the SPI clock rate is not supported!\n"); + else if (sp_docommand(S_CMD_S_SPI_FREQ, 4, buf, 4, buf) == 0) { f_spi = buf[0]; f_spi |= buf[1] << (1 * 8); f_spi |= buf[2] << (2 * 8); @@ -557,7 +556,7 @@ msg_pdbg(MSGHEADER "Requested to set SPI clock frequency to %u Hz. " "It was actually set to %u Hz\n", f_spi_req, f_spi); } else - msg_pdbg(MSGHEADER "Setting SPI clock rate to %u Hz failed!\n", f_spi_req); + msg_pwarn(MSGHEADER "Setting SPI clock rate to %u Hz failed!\n", f_spi_req); } free(spispeed); bt = serprog_buses_supported; @@ -633,14 +632,14 @@ } if (sp_docommand(S_CMD_Q_PGMNAME, 0, NULL, 16, pgmname)) { - msg_perr("Warning: NAK to query programmer name\n"); + msg_pwarn("Warning: NAK to query programmer name\n"); strcpy((char *)pgmname, "(unknown)"); } pgmname[16] = 0; msg_pinfo(MSGHEADER "Programmer name is \"%s\"\n", pgmname); if (sp_docommand(S_CMD_Q_SERBUF, 0, NULL, 2, &sp_device_serbuf_size)) { - msg_perr("Warning: NAK to query serial buffer size\n"); + msg_pwarn("Warning: NAK to query serial buffer size\n"); } msg_pdbg(MSGHEADER "Serial buffer size is %d\n", sp_device_serbuf_size); @@ -660,8 +659,7 @@ if (sp_docommand(S_CMD_Q_OPBUF, 0, NULL, 2, &sp_device_opbuf_size)) { - msg_perr("Warning: NAK to query operation buffer " - "size\n"); + msg_pwarn("Warning: NAK to query operation buffer size\n"); } msg_pdbg(MSGHEADER "operation buffer size is %d\n", sp_device_opbuf_size); @@ -755,7 +753,7 @@ if (sp_docommand(S_CMD_S_PIN_STATE, 1, &dis, 0, NULL) == 0) msg_pdbg(MSGHEADER "Output drivers disabled\n"); else - msg_perr(MSGHEADER "%s: Warning: could not disable output buffers\n", __func__); + msg_pwarn(MSGHEADER "%s: Warning: could not disable output buffers\n", __func__); } /* FIXME: fix sockets on windows(?), especially closing */ serialport_shutdown(&sp_fd); Modified: trunk/sst_fwhub.c ============================================================================== --- trunk/sst_fwhub.c Fri Jan 4 23:24:58 2013 (r1642) +++ trunk/sst_fwhub.c Fri Jan 4 23:54:07 2013 (r1643) @@ -86,7 +86,7 @@ { if (clear_sst_fwhub_block_lock(flash, i)) { - msg_cdbg("Warning: Unlock Failed for block 0x%06x\n", i); + msg_cwarn("Warning: Unlock Failed for block 0x%06x\n", i); ret++; } }

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Re: [flashrom] [PATCH] Unify PCI init and let pcidev clean itself up.
by Carl-Daniel Hailfinger 04 Jan '13

04 Jan '13

Am 02.01.2013 15:43 schrieb Stefan Tauner: > Previously the internal programmer used its own code to initialize pcilib. > This patch extracts the common code from the internal programmer and > pcidev_init() into pcidev_init_common(). > This fixes the non-existent PCI cleanup of the internal programmer and adds > an additional safety by checking for an already existing PCI context. > > We got a nice shutdown function registration infrastructure, but did not use it > very wisely. Instead we added shutdown functions to a myriad of programmers > unnecessarily. In this patch we get rid of those that do only call pci_cleanup(pacc) > by adding a shutdown function the pcidev.c itself that gets registered by > pcidev_init(). > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Great work! Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

[commit] r1642 - trunk
by repository service 04 Jan '13

04 Jan '13

Author: stefanct Date: Fri Jan 4 23:24:58 2013 New Revision: 1642 URL: http://flashrom.org/trac/flashrom/changeset/1642 Log: Unify PCI init and let pcidev clean itself up. Previously the internal programmer used its own code to initialize pcilib. This patch extracts the common code from the internal programmer and pcidev_init() into pcidev_init_common(). This fixes the non-existent PCI cleanup of the internal programmer and adds an additional safety by checking for an already existing PCI context. We got a nice shutdown function registration infrastructure, but did not use it very wisely. Instead we added shutdown functions to a myriad of programmers unnecessarily. In this patch we get rid of those that do only call pci_cleanup(pacc) by adding a shutdown function the pcidev.c itself that gets registered by pcidev_init(). Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/atahpt.c trunk/drkaiser.c trunk/gfxnvidia.c trunk/internal.c trunk/nic3com.c trunk/nicintel.c trunk/nicintel_spi.c trunk/nicrealtek.c trunk/ogp_spi.c trunk/pcidev.c trunk/programmer.h trunk/satamv.c trunk/satasii.c Modified: trunk/atahpt.c ============================================================================== --- trunk/atahpt.c Thu Jan 3 21:44:30 2013 (r1641) +++ trunk/atahpt.c Fri Jan 4 23:24:58 2013 (r1642) @@ -56,13 +56,6 @@ .chip_writen = fallback_chip_writen, }; -static int atahpt_shutdown(void *data) -{ - /* Flash access is disabled automatically by PCI restore. */ - pci_cleanup(pacc); - return 0; -} - int atahpt_init(void) { uint32_t reg32; @@ -72,9 +65,6 @@ io_base_addr = pcidev_init(PCI_BASE_ADDRESS_4, ata_hpt); - if (register_shutdown(atahpt_shutdown, NULL)) - return 1; - /* Enable flash access. */ reg32 = pci_read_long(pcidev_dev, REG_FLASH_ACCESS); reg32 |= (1 << 24); Modified: trunk/drkaiser.c ============================================================================== --- trunk/drkaiser.c Thu Jan 3 21:44:30 2013 (r1641) +++ trunk/drkaiser.c Fri Jan 4 23:24:58 2013 (r1642) @@ -59,8 +59,6 @@ static int drkaiser_shutdown(void *data) { physunmap(drkaiser_bar, DRKAISER_MEMMAP_SIZE); - /* Flash write is disabled automatically by PCI restore. */ - pci_cleanup(pacc); return 0; } @@ -71,6 +69,7 @@ if (rget_io_perms()) return 1; + /* No need to check for errors, pcidev_init() will not return in case of errors. */ addr = pcidev_init(PCI_BASE_ADDRESS_2, drkaiser_pcidev); /* Write magic register to enable flash write. */ Modified: trunk/gfxnvidia.c ============================================================================== --- trunk/gfxnvidia.c Thu Jan 3 21:44:30 2013 (r1641) +++ trunk/gfxnvidia.c Fri Jan 4 23:24:58 2013 (r1642) @@ -80,10 +80,6 @@ static int gfxnvidia_shutdown(void *data) { physunmap(nvidia_bar, GFXNVIDIA_MEMMAP_SIZE); - /* Flash interface access is disabled (and screen enabled) automatically - * by PCI restore. - */ - pci_cleanup(pacc); return 0; } @@ -94,6 +90,7 @@ if (rget_io_perms()) return 1; + /* No need to check for errors, pcidev_init() will not return in case of errors. */ io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, gfx_nvidia); io_base_addr += 0x300000; @@ -101,7 +98,6 @@ nvidia_bar = physmap("NVIDIA", io_base_addr, GFXNVIDIA_MEMMAP_SIZE); - /* Must be done before rpci calls. */ if (register_shutdown(gfxnvidia_shutdown, NULL)) return 1; Modified: trunk/internal.c ============================================================================== --- trunk/internal.c Thu Jan 3 21:44:30 2013 (r1641) +++ trunk/internal.c Fri Jan 4 23:24:58 2013 (r1642) @@ -245,10 +245,8 @@ internal_buses_supported = BUS_NONSPI; /* Initialize PCI access for flash enables */ - pacc = pci_alloc(); /* Get the pci_access structure */ - /* Set all options you want -- here we stick with the defaults */ - pci_init(pacc); /* Initialize the PCI library */ - pci_scan_bus(pacc); /* We want to get the list of devices */ + if (pci_init_common() != 0) + return 1; if (processor_flash_enable()) { msg_perr("Processor detection/init failed.\n" Modified: trunk/nic3com.c ============================================================================== --- trunk/nic3com.c Thu Jan 3 21:44:30 2013 (r1641) +++ trunk/nic3com.c Fri Jan 4 23:24:58 2013 (r1642) @@ -81,7 +81,6 @@ OUTL(internal_conf, io_base_addr + INTERNAL_CONFIG); } - pci_cleanup(pacc); return 0; } @@ -90,6 +89,7 @@ if (rget_io_perms()) return 1; + /* No need to check for errors, pcidev_init() will not return in case of errors. */ io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_3com); id = pcidev_dev->device_id; Modified: trunk/nicintel.c ============================================================================== --- trunk/nicintel.c Thu Jan 3 21:44:30 2013 (r1641) +++ trunk/nicintel.c Fri Jan 4 23:24:58 2013 (r1642) @@ -63,7 +63,6 @@ { physunmap(nicintel_control_bar, NICINTEL_CONTROL_MEMMAP_SIZE); physunmap(nicintel_bar, NICINTEL_MEMMAP_SIZE); - pci_cleanup(pacc); return 0; } @@ -77,8 +76,7 @@ if (rget_io_perms()) return 1; - /* No need to check for errors, pcidev_init() will not return in case - * of errors. + /* No need to check for errors, pcidev_init() will not return in case of errors. * FIXME: BAR2 is not available if the device uses the CardBus function. */ addr = pcidev_init(PCI_BASE_ADDRESS_2, nics_intel); @@ -117,7 +115,6 @@ error_out_unmap: physunmap(nicintel_bar, NICINTEL_MEMMAP_SIZE); error_out: - pci_cleanup(pacc); return 1; } Modified: trunk/nicintel_spi.c ============================================================================== --- trunk/nicintel_spi.c Thu Jan 3 21:44:30 2013 (r1641) +++ trunk/nicintel_spi.c Fri Jan 4 23:24:58 2013 (r1642) @@ -160,7 +160,6 @@ pci_mmio_writel(tmp, nicintel_spibar + EECD); physunmap(nicintel_spibar, MEMMAP_SIZE); - pci_cleanup(pacc); return 0; } @@ -172,6 +171,7 @@ if (rget_io_perms()) return 1; + /* No need to check for errors, pcidev_init() will not return in case of errors. */ io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_intel_spi); nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash", Modified: trunk/nicrealtek.c ============================================================================== --- trunk/nicrealtek.c Thu Jan 3 21:44:30 2013 (r1641) +++ trunk/nicrealtek.c Fri Jan 4 23:24:58 2013 (r1642) @@ -54,7 +54,6 @@ static int nicrealtek_shutdown(void *data) { /* FIXME: We forgot to disable software access again. */ - pci_cleanup(pacc); return 0; } @@ -63,8 +62,8 @@ if (rget_io_perms()) return 1; + /* No need to check for errors, pcidev_init() will not return in case of errors. */ io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_realtek); - if (register_shutdown(nicrealtek_shutdown, NULL)) return 1; Modified: trunk/ogp_spi.c ============================================================================== --- trunk/ogp_spi.c Thu Jan 3 21:44:30 2013 (r1641) +++ trunk/ogp_spi.c Fri Jan 4 23:24:58 2013 (r1642) @@ -100,8 +100,6 @@ static int ogp_spi_shutdown(void *data) { physunmap(ogp_spibar, 4096); - pci_cleanup(pacc); - return 0; } Modified: trunk/pcidev.c ============================================================================== --- trunk/pcidev.c Thu Jan 3 21:44:30 2013 (r1641) +++ trunk/pcidev.c Fri Jan 4 23:24:58 2013 (r1642) @@ -154,6 +154,33 @@ return (uintptr_t)addr; } +static int pcidev_shutdown(void *data) +{ + pcidev_dev = NULL; + if (pacc == NULL) { + msg_perr("%s: Tried to cleanup an invalid PCI context!\n" + "Please report a bug at flashrom(a)flashrom.org\n", __func__); + return 1; + } + pci_cleanup(pacc); + return 0; +} + +int pci_init_common(void) +{ + if (pacc != NULL) { + msg_perr("%s: Tried to allocate a new PCI context, but there is still an old one!\n" + "Please report a bug at flashrom(a)flashrom.org\n", __func__); + return 1; + } + pacc = pci_alloc(); /* Get the pci_access structure */ + pci_init(pacc); /* Initialize the PCI library */ + if (register_shutdown(pcidev_shutdown, NULL)) + return 1; + pci_scan_bus(pacc); /* We want to get the list of devices */ + return 0; +} + uintptr_t pcidev_init(int bar, const struct dev_entry *devs) { struct pci_dev *dev; @@ -164,9 +191,8 @@ int i; uintptr_t addr = 0, curaddr = 0; - pacc = pci_alloc(); /* Get the pci_access structure */ - pci_init(pacc); /* Initialize the PCI library */ - pci_scan_bus(pacc); /* We want to get the list of devices */ + if(pci_init_common() != 0) + return 1; pci_filter_init(pacc, &filter); /* Filter by bb:dd.f (if supplied by the user). */ @@ -244,6 +270,11 @@ int undo_pci_write(void *p) { struct undo_pci_write_data *data = p; + if (pacc == NULL) { + msg_perr("%s: Tried to undo PCI writes without a valid PCI context!\n" + "Please report a bug at flashrom(a)flashrom.org\n", __func__); + return 1; + } msg_pdbg("Restoring PCI config space for %02x:%02x:%01x reg 0x%02x\n", data->dev.bus, data->dev.dev, data->dev.func, data->reg); switch (data->type) { Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Thu Jan 3 21:44:30 2013 (r1641) +++ trunk/programmer.h Fri Jan 4 23:24:58 2013 (r1642) @@ -238,6 +238,7 @@ extern uint32_t io_base_addr; extern struct pci_access *pacc; extern struct pci_dev *pcidev_dev; +int pci_init_common(void); uintptr_t pcidev_readbar(struct pci_dev *dev, int bar); uintptr_t pcidev_init(int bar, const struct dev_entry *devs); /* rpci_write_* are reversible writes. The original PCI config space register Modified: trunk/satamv.c ============================================================================== --- trunk/satamv.c Thu Jan 3 21:44:30 2013 (r1641) +++ trunk/satamv.c Fri Jan 4 23:24:58 2013 (r1642) @@ -60,7 +60,6 @@ static int satamv_shutdown(void *data) { physunmap(mv_bar, 0x20000); - pci_cleanup(pacc); return 0; } @@ -96,7 +95,7 @@ mv_bar = physmap("Marvell 88SX7042 registers", addr, 0x20000); if (mv_bar == ERROR_PTR) - goto error_out; + return 1; if (register_shutdown(satamv_shutdown, NULL)) return 1; @@ -159,10 +158,6 @@ register_par_programmer(&par_programmer_satamv, BUS_PARALLEL); return 0; - -error_out: - pci_cleanup(pacc); - return 1; } /* BAR2 (MEM) can map NVRAM and flash. We set it to flash in the init function. Modified: trunk/satasii.c ============================================================================== --- trunk/satasii.c Thu Jan 3 21:44:30 2013 (r1641) +++ trunk/satasii.c Fri Jan 4 23:24:58 2013 (r1642) @@ -57,7 +57,6 @@ static int satasii_shutdown(void *data) { physunmap(sii_bar, SATASII_MEMMAP_SIZE); - pci_cleanup(pacc); return 0; }

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