flashrom

flashrom@flashrom.org

3 participants
9189 discussions

Something else is accessing the flash chip, what are the usual suspects?
by Wei Hu 26 Apr '13

26 Apr '13

Hello, I'm running Ubuntu 12.10 and the latest flashrom from subversion. I'm getting this warning and would like to know how to find the driver/program that's accessing the flash chip? Thanks! # ./flashrom --programmer internal -r /tmp/k -VVV flashrom v0.9.6.1-r1671 on Linux 3.5.0-25-generic (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.9, GCC 4.7.2, little endian ... Found chipset "AMD Hudson" with PCI ID 1022:780e. Enabling flash write... SPI base address is at 0xfec10000 AltSpiCSEnable=0, SpiRomEnable=1, AbortEnable=0 PrefetchEnSPIFromIMC=0, PrefetchEnSPIFromHost=1, SpiOpEnInLpcMode=1 SpiArbEnable=1, SpiAccessMacRomEn=1, SpiHostAccessRomEn=1, ArbWaitCount=7, SpiBridgeDisable=1, DropOneClkOnRd=0 NormSpeed is Reserved MHz GPIO11 used for SPI_DO GPIO12 used for SPI_DI GPIO31 used for SPI_HOLD GPIO32 used for SPI_CS GPIO47 used for SPI_CLK SB700 IMC is not active. ROM strap override is not active OK. The following protocols are supported: LPC, FWH, SPI. Probing for AMIC A25L05PT, 64 kB: sb600_spi_send_command, cmd=9f, writecnt=0, readcnt=4 Writing: SB600 FIFO pointer is 0, wanted 0 Executing: SB600 FIFO pointer corruption! Pointer is 3, wanted 4 Something else is accessing the flash chip and causes random corruption. Please stop all applications and drivers and IPMI which access the flash chip.

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flashrom schedule 2013 (includes my GSoC proposal mostly :)
by Stefan Tauner 24 Apr '13

24 Apr '13

If mentors agree I would rather not set all project details in stone. My previous project of unlocking the ME had a very distinct goal but the outcome was something completely different but probably more useful to the project than if I would have succeeded IMHO :) Also, progress on single points might be delayed due to missing feedback or reviewing. Main coding period is from 2013-06-17 till 2013-09-23. Until then I would like to tag another stable release (0.9.6 was released in August 2012) and merge the larger chunks of the patch pile. While this might create intermittent problems without proper review it will guarantee that there wont be too many conflicts with the code to come and it will merge stuff that should have been merged way earlier... If there will be others working on flashrom (panic room, serialice or even "native" flashrom project(s)), this is even more important. Here is the list of the most important things I want to merge shortly after tagging the next stable: mine: - Layout patches - Automatic unmapping and rounding of physmaps - Internal DMI decoder others: - any makefile-related changes and patches that are waiting on makefile changes only if possible (e.g. libusb stuff) - rayer_spi/lpt_spi (if they do not make it into the stable) Please suggest other stuff that you think is ready (I probably forgot about some)! My goals for the actual coding season are (in planned chronological order): - integrate Nico's libflashrom patches - refine and merge check_trans patch(es). They will be very useful/required for the following goals to be implemented (safely). - add support for multiple write operations * similar to erasers but maybe using distinct enter/exit function pointers - add support for multiple read operations (like writes), allowing to: - add support for 4B-addressing (needed for chips >= 16MB) I have received sample chips from Spansion and Macronix (S25FL256, S25FL512, MX25L25635), but I need to adapt my programmer to work with SOIC16 packages. - improve SPI probing. Something long overdue IMHO. There are less than a dozen ways to identify SPI flash chips. Nevertheless flashrom uses no more than 3 and even those in a rather awkward way. * Determine the best way to allow for multiple probing results/matches per chip and/or how to separate SPI probing from the rest. Possibly split struct flashchip into a generic part and a more specific Non-SPI/SPI union. * Design a method to rank the received results and match the chip- * Implement probing accordingly. * Add more/generify probing methods (EDI). * Mark chips still not distinguishable (on permissive programmers/safely) as evil twins. Somewhere inbetween I will probably have to create a unified and distinct type for on-chip addresses, and possibly address ranges too (and functions to operate on those as if they were sets (union, intersection, difference)). If there is still time I could do other infrastructure improvements like automatic recovery if something fails etc. or reduce my TODO list (which is essentially the same thing). If there is a lot more time I would work on the locking interface that and/or improvements regarding the "Internal programmer improvements for complex systems" project. If everything works out as planned I would like to release another stable (or at least release candidate) a few months after the big changes have been merged, certainly before 2014. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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flashrom issues on our X86 blades.
by Andrew Zhao 24 Apr '13

24 Apr '13

Hi flashrom experts: When I run "flashrom" on our X86 blades, there are some WARNING info , I am very appreciated if you can take a look Into it and give some comments. Attachments are the output when I run the commands with "-V" option. When I run "flashrom -p internal" , the output is: ================================== root@ATCA-46XX@0-0-5:~# flashrom -p internal flashrom v0.9.6.1-r1564 on Linux 2.6.32-131.0.15.el6.x86_64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "Intel X79". This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... FREG0: WARNING: Flash Descriptor region (0x00000000-0x0000ffff) is read-only. FREG2: WARNING: Management Engine region (0x00020000-0x007fffff) is locked. Please send a verbose log to flashrom(a)flashrom.org if this board is not listed on http://flashrom.org/Supported_hardware#Supported_mainboards yet. Writes have been disabled. You can enforce write support with the ich_spi_force programmer option, but it will most likely harm your hardware! If you force flashrom you will get no support if something breaks. Enabling hardware sequencing due to multiple flash chips detected. OK. Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific) at physical address 0x0. No operations were specified. =================================== When I run "flashrom -p internal -r bios.bin" , the output is: =================================== root@ATCA-46XX@0-0-5:~# flashrom -p internal flashrom v0.9.6.1-r1564 on Linux 2.6.32-131.0.15.el6.x86_64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "Intel X79". This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... FREG0: WARNING: Flash Descriptor region (0x00000000-0x0000ffff) is read-only. FREG2: WARNING: Management Engine region (0x00020000-0x007fffff) is locked. Please send a verbose log to flashrom(a)flashrom.org if this board is not listed on http://flashrom.org/Supported_hardware#Supported_mainboards yet. Writes have been disabled. You can enforce write support with the ich_spi_force programmer option, but it will most likely harm your hardware! If you force flashrom you will get no support if something breaks. Enabling hardware sequencing due to multiple flash chips detected. OK. Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific) at physical address 0x0. No operations were specified. root@ATCA-46XX@0-0-5:~# flashrom -p internal -r bios.bin flashrom v0.9.6.1-r1564 on Linux 2.6.32-131.0.15.el6.x86_64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "Intel X79". This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... FREG0: WARNING: Flash Descriptor region (0x00000000-0x0000ffff) is read-only. FREG2: WARNING: Management Engine region (0x00020000-0x007fffff) is locked. Please send a verbose log to flashrom(a)flashrom.org if this board is not listed on http://flashrom.org/Supported_hardware#Supported_mainboards yet. Writes have been disabled. You can enforce write support with the ich_spi_force programmer option, but it will most likely harm your hardware! If you force flashrom you will get no support if something breaks. Enabling hardware sequencing due to multiple flash chips detected. OK. Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific) at physical address 0x0. Reading flash... Transaction error between offset 0x00020000 and 0x0002003f (= 0x00020000 + 63)! Read operation failed! FAILED. =================================================

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[PATCH] Fix hwaccess (again).
by Stefan Tauner 23 Apr '13

23 Apr '13

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- hwaccess.c | 32 +++++++++++++++++++------------- 1 file changed, 19 insertions(+), 13 deletions(-) diff --git a/hwaccess.c b/hwaccess.c index 598aa67..bad08d4 100644 --- a/hwaccess.c +++ b/hwaccess.c @@ -26,10 +26,9 @@ #error Unknown architecture #endif -#define IS_BSD (defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__OpenBSD__)) #define IS_LINUX (defined(__gnu_linux__) || defined(__linux__)) #define IS_MACOSX (defined(__APPLE__) && defined(__MACH__)) -#if !(IS_BSD || IS_LINUX || IS_MACOSX || defined(__DJGPP__) || defined(__LIBPAYLOAD__) || defined(__sun)) +#if !(IS_LINUX || IS_MACOSX || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__DJGPP__) || defined(__LIBPAYLOAD__) || defined(__sun)) #error "Unknown operating system" #endif @@ -47,7 +46,10 @@ #include "flash.h" #include "hwaccess.h" -#if IS_X86 && IS_BSD +#define USE_IOPL (IS_LINUX || IS_MACOSX || defined(__NetBSD__) || defined(__OpenBSD__)) +#define USE_DEV_IO (defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)) + +#if IS_X86 && USE_DEV_IO int io_fd; #endif @@ -71,9 +73,9 @@ static int release_io_perms(void *p) { #if defined (__sun) sysi86(SI86V86, V86SC_IOPL, 0); -#elif IS_BSD +#elif USE_DEV_IO close(io_fd); -#elif IS_LINUX || IS_MACOSX +#elif USE_IOPL iopl(0); #endif return 0; @@ -86,17 +88,21 @@ int rget_io_perms(void) #if IS_X86 && !(defined(__DJGPP__) || defined(__LIBPAYLOAD__)) #if defined (__sun) if (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) != 0) { -#elif IS_BSD +#elif USE_DEV_IO if ((io_fd = open("/dev/io", O_RDWR)) < 0) { -#elif IS_LINUX || IS_MACOSX +#elif USE_IOPL if (iopl(3) != 0) { #endif - msg_perr("ERROR: Could not get I/O privileges (%s).\n" - "You need to be root.\n", strerror(errno)); -#if defined (__OpenBSD__) - msg_perr("Please set securelevel=-1 in /etc/rc.securelevel and reboot, or reboot into \n"); - msg_perr("single user mode.\n"); -#endif + msg_perr("ERROR: Could not get I/O privileges (%s).\n", strerror(errno)); + msg_perr("You need to be root.\n"); +if defined (__OpenBSD__) + msg_perr("If you are root already please set securelevel=-1 in /etc/rc.securelevel and reboot\n" + "or reboot into single user mode.\n"); +#if defined(__NetBSD__) + msg_perr("If you are root already please set securelevel=-1 in /etc/rc.conf and reboot,\n" + "or reboot into single user mode, or check that your kernel configuration has" + "the option INSECURE enabled.\n"); +#el#endif return 1; } else { register_shutdown(release_io_perms, NULL); -- Kind regards, Stefan Tauner

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Re: [flashrom] Multichip support for a dediprog SF100
by Marc Jones 23 Apr '13

23 Apr '13

Joshua, I ran into the same thing. I think that the flashrom dediprog support needs a flag to switch the chipselect. Marc On Tue, Apr 23, 2013 at 9:21 AM, Joshua Zarr <joshuazarr(a)gmail.com> wrote: > Hi All, > > I am using a dediprog SF100 to program the two flash chips (AT25DF321) on an > intel Stargo CRB. Does flashrom support programming each chip individually? > > Thanks, > Joshua Zarr > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom -- http://se-eng.com

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Multichip support for a dediprog SF100
by Joshua Zarr 23 Apr '13

23 Apr '13

Hi All, I am using a dediprog SF100 to program the two flash chips (AT25DF321) on an intel Stargo CRB. Does flashrom support programming each chip individually? Thanks, Joshua Zarr

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Re: [flashrom] "MX25L12805(D)
by Stefan Tauner 23 Apr '13

23 Apr '13

On Mon, 22 Apr 2013 13:24:44 -0700 Skip WB6YMH <wb6ymh(a)gfrn.org> wrote: > I'd like to let you know that I successfully programmed the above > chip using a ft2232 based "TUMPA" interface card. I've programmed > two chips on two separate boards, but worked fine and booted > Linux. > > I did get one "get_buf failed: 1 > ftdi_write_data: -19, usb bulk write failed > send_buf failed at end: 1 > FAILED." > > Error, but that probably has nothing to do with the MX25L12805(D) chip. > > Thanks for the code ! > > Skip Hello Skip, thanks for your report! I have marked the flash chip as fully tested and will commit that later together with other small changes. Please include the complete log in future reports (and an additional one with verbose output (-V) if the normal run did not include that). That's especially interesting for error cases such as the one you mentioned. Do you remember when the error occurred exactly? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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"MX25L12805(D)
by Skip WB6YMH 22 Apr '13

22 Apr '13

I'd like to let you know that I successfully programmed the above chip using a ft2232 based "TUMPA" interface card. I've programmed two chips on two separate boards, but worked fine and booted Linux. I did get one "get_buf failed: 1 ftdi_write_data: -19, usb bulk write failed send_buf failed at end: 1 FAILED." Error, but that probably has nothing to do with the MX25L12805(D) chip. Thanks for the code ! Skip

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Report: Intel DQ77MK
by g_ml2000-x＠yahoo.de 20 Apr '13

20 Apr '13

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report for ASUS P8B75M LE
by guido 20 Apr '13

20 Apr '13

root@sysresccd /root % flashrom -p internal -VV flashrom v0.9.6.1-runknown on Linux 3.4.35-std342-amd64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.7, GCC 4.6.0 20110428 (Red Hat 4.6.0-6), little endian Command line (3 args): flashrom -p internal -VV Calibrating delay loop... OS timer resolution is 1 usecs, 3876M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1000 us, 10000 myus = 10003 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK COMPUTER INC." DMI string baseboard-product-name: "P8B75-M LE" DMI string baseboard-version: "Rev X.0x" DMI string chassis-type: "Desktop" Found chipset "Intel B75" with PCI ID 8086:1e49. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode enabled 0xff600000/0xff200000 FWH decode enabled 0xff500000/0xff100000 FWH decode enabled 0xff400000/0xff000000 FWH decode enabled Maximum FWH chip size: 0x100000 bytes BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled Root Complex Register Block address = 0xfed1c000 GCS = 0xc65: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 Warning: SPI Configuration Lockdown activated. Reading OPCODES... done OP Type Pre-OP op[0]: 0x02, write w/ addr, none op[1]: 0x03, read w/ addr, none op[2]: 0x20, write w/ addr, none op[3]: 0x05, read w/o addr, none op[4]: 0x9f, read w/o addr, none op[5]: 0x01, write w/o addr, none op[6]: 0x00, read w/o addr, none op[7]: 0x00, read w/o addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x00 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00000000 (FADDR) 0x50: 0x00000a0b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b 0x54: 0x00000000 FREG0: Warning: Flash Descriptor region (0x00000000-0x00000fff) is read-only. 0x58: 0x0fff0800 FREG1: BIOS region (0x00800000-0x00ffffff) is read-write. 0x5C: 0x07ff0001 FREG2: Warning: Management Engine region (0x00001000-0x007fffff) is locked. 0x60: 0x00001fff FREG3: Gigabit Ethernet region is unused. 0x64: 0x00001fff FREG4: Platform Data region is unused. 0x74: 0x00000000 (PR0 is unused) 0x78: 0x00000000 (PR1 is unused) 0x7C: 0x00000000 (PR2 is unused) 0x80: 0x00000000 (PR3 is unused) 0x84: 0x00000000 (PR4 is unused) Please send a verbose log to flashrom(a)flashrom.org if this board is not listed on http://flashrom.org/Supported_hardware#Supported_mainboards yet. Writes have been disabled for safety reasons. You can enforce write support with the ich_spi_force programmer option, but you will most likely harm your hardware! If you force flashrom you will get no support if something breaks. On a few mainboards it is possible to enable write access by setting a jumper (see its documentation or the board itself). 0x90: 0x80 (SSFS) SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 0x91: 0xf94010 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=0, SME=0, SCF=1 0x94: 0x0006 (PREOP) 0x96: 0x043b (OPTYPE) 0x98: 0x05200302 (OPMENU) 0x9C: 0x0000019f (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x00802005 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xC8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 0xD0: 0x00000000 (FPB) Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. === Content Section === FLVALSIG 0x0ff0a55a FLMAP0 0x02040103 FLMAP1 0x12100206 FLMAP2 0x00210120 --- Details --- NR (Number of Regions): 3 FRBA (Flash Region Base Address): 0x040 NC (Number of Components): 2 FCBA (Flash Component Base Address): 0x030 ISL (ICH/PCH Strap Length): 18 FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100 NM (Number of Masters): 3 FMBA (Flash Master Base Address): 0x060 MSL/PSL (MCH/PROC Strap Length): 1 FMSBA (Flash MCH/PROC Strap Base Address): 0x200 === Component Section === FLCOMP 0x09300024 FLILL 0x00000000 --- Details --- Component 1 density: 8 MB Component 2 density: 8 MB Read Clock Frequency: 20 MHz Read ID and Status Clock Freq.: 33 MHz Write and Erase Clock Freq.: 33 MHz Fast Read is supported. Fast Read Clock Frequency: 33 MHz No forbidden opcodes. === Region Section === FLREG0 0x00000000 FLREG1 0x0fff0800 FLREG2 0x07ff0001 FLREG3 0x00001fff --- Details --- Region 0 (Descr.) 0x00000000 - 0x00000fff Region 1 (BIOS ) 0x00800000 - 0x00ffffff Region 2 (ME ) 0x00001000 - 0x007fffff Region 3 (GbE ) is unused. === Master Section === FLMSTR1 0x0a0b0000 FLMSTR2 0x0c0d0000 FLMSTR3 0x08080118 --- Details --- Descr. BIOS ME GbE Platf. BIOS r rw rw ME r rw rw GbE rw Enabling hardware sequencing due to multiple flash chips detected. SPI Read Configuration: prefetching enabled, caching enabled, OK. The following protocols are supported: FWH, Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Found 2 attached SPI flash chips with a combined density of 16384 kB. There is only one partition containing the whole address space (0x000000 - 0xffffff). There are 4096 erase blocks with 4096 B each. Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific) at physical address 0x0. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x00, id2 0x10, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0x00, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xea, id2 0xd0, id1 is normal flash content, id2 is normal flash content Found Programmer flash chip "Opaque flash chip" (16384 kB, Programmer-specific). No operations were specified. Restoring MMIO space at 0xf77af8a0 Restoring PCI config space for 00:1f:0 reg 0xdc root@sysresccd /root %

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