flashrom

flashrom@flashrom.org

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9187 discussions

Status of Meson support, where are we? (was Re: Build systems and `uinstall` option)
by Nico Huber 14 Nov '22

14 Nov '22

Hi all, it feels like this deserves its own thread. I was a little surprised by the news that we are already ready to deprecate Make. Hopefully, I'm just not up to date and this is the case! If I'm horribly off track, please ignore the following. IIRC, we said this would be the case if we can do everything with Meson what we can do with Make (due to lack of knowing what the latter can, we made a list of target environments that we need to support at least) and Meson produces the same binaries as Make. Are we there yet? My last state wrt. the more special target environments like lib- payload was that it seems feasible, but I haven't seen a PoC yet. On 10.11.22 17:43, Felix Singer wrote: > The Make build system is going to be deprecated with the next release > and it is going to be dropped with the release after that. "next release" being the one that just started or the next after that? iow. does this mean deprecate with flashrom 1.3 and drop in 1.4? > We discussed the Make build system in many meetings now and we all > agreed that we won't add any more features to it. That means its > current feature state is frozen and it doesn't get any additional > functionality, just bug fixes, refactorings or adjustments as far as > they are really necessary. Was this ever discussed on / announced to the ML? My status was that this was of the "nobody objected during some meeting" decision kind. Nico

5 7

Build systems and `uinstall` option
by Joursoir 14 Nov '22

14 Nov '22

Hello everyone, I wonder why there is no 'uninstall' option in the flashrom's Makefile? Is it just an oversight? Or do we have a reason for that? The same question is related to the meson script. -- Joursoir

5 12

Future development and release process
by Nico Huber 11 Nov '22

11 Nov '22

Hi flashrom fellows, some of us have picked a new release process for flashrom 1.3 that ignores the problems of the master branch but will attend to them on a separate branch. This leaves us without a strategy to get future releases done with less hassle. It also feels quite frustrating be- cause I fear it takes incentive away to fix the master branch. And hence increases the incentive for myself to abandon said branch. During a phone call with Felix, I explained the options I see roughly as follows. There are probably more options, feel free to discuss others as well. These just came to my head. 1. Full reset: Branch off 1.2.x before the master branch started to make trouble. Also reset the Gerrit privileges to a state where only people got merge rights after they earned trust by the pre- existing maintainers (people with those rights); to prevent that history repeats itself. So far this seemed to be unacceptable by the Google team. The rest of this email will assume that we won't be doing this. If it turns out I'm wrong, this would be my preferred solution and we won't have to discuss anything below. 2. Try harder: Keep working on the current master branch. Try to fix the process as we go along. This is unacceptable to me. We have tried this already and I have not seen things getting better. Building up on a broken state is most often harder than rewinding to a good state and starting new things from scratch. Working on this branch has not been fun since flashrom 1.2. Beside that, the master branch hasn't provided any- thing that I could use in my day job for years (not as a develop- ment tool and definitely not in our products). 3. Compromise: The current situation evolved due to a highly dynamic development process that is roughly the opposite of what we had before we tried to converge upstream and chromium development. Also, adding many new developers that are used to a very different process requires a lot of communication (IMO) which didn't happen. We could accept these different development strategies and work on two branches. Not(!) competing branches but branches that complement each other. Something like this was actually proposed before [1]. The rough idea: we could have a 'stable' branch and a more dynamic one. Back then we called the latter 'staging'. Merging commits to the 'stable' branch would be limited to maintainers who know flash- rom well enough and trust each other. To be honest, I wouldn't care much what happens on the 'staging' branch, who gets to merge etc. There were often reservations if this could work without diverging the branches. But there are strategies to avoid it. For instance, a regular `git merge` onto the 'staging' branch could avoid that. To give it a good start, I would also suggest to base a 'stable' branch on 1.2.x. 4. Divide: If we don't find a compromise, I'll have to continue my work on a new branch. I wouldn't care then if things diverge. Details depend mostly on who would like to join the effort. It would likely start on 1.2.x with things added from the current master branch (might get things through review again, or also cherry pick real cherries directly without going through Gerrit). Quite unappealing because it would push contributors to choose a branch. And we would have to discuss how to deal with future releases. You may notice that most of my ideas suggest rewinding to 1.2.x. Beside easing further development on a reasonable code base, there is one more thing driving me: The master branch contains many commits that caused awkward feelings. I think it would help working together if we wouldn't be reminded of them all the time. Nico [1] https://www.flashrom.org/index.php?title=Development_Guidelines&oldid=2252#…

1 0

Documenting flashrom's guts
by Angel Pons 08 Nov '22

08 Nov '22

Hi list, There's several things regarding flashrom's structure that seem to be underdocumented (or *are* documented, but the information is extremely hard to find). It would be very helpful to have this information available somewhere easy to find, such as the Wiki. Some things that would greatly benefit from being documented are: - flashrom's layers: which layers there are, and how they interact with each other. - flashrom's structures: which structures there are, how they interact with each other, and how they "map" to layers. Surely there are more things that would benefit from being documented. Let's not discuss *who* is going to do what for now; first, let's collect information about these parts of flashrom. Best regards, Angel

3 2

Branch 1.3.x is being prepared for release candidate
by Anastasia Klimchuk 07 Nov '22

07 Nov '22

Good Day Flashrom community, We’ve got good news about the upcoming release v1.3. Branch 1.3.x is officially opened and being prepared for release candidate. The branch has been fast-forwarded to head as of Friday last week. We are now going through the list of what is critical to do for the release and patching 1.3.x accordingly. You can see the patches for 1.3.x by this link: https://review.coreboot.org/q/project:flashrom+branch:1.3.x The next step will be to put an RC1 tag for the branch (when ready for that) and write another announcement. If you know of any bugs, please report to us, and thank you! In any case, bugs will be reported in the bugtracker. And then we can decide what’s the urgency and whether the bug is blocking the release or not. Meanwhile, development continues on master branch. Specifically, there are few ongoing projects in various stages of development: all of that continues. And hopefully, could be included in the next release. Thanks everyone! -- Anastasia.

1 0

Re: [review] WP documentation for flashrom users
by Anastasia Klimchuk 04 Nov '22

04 Nov '22

I only noticed now that the mailing list got lost from the last two messages. I apologise for that, it was completely unintentional! Re-sending again, and now including the mailing list. Text below. On Wed, Nov 2, 2022 at 12:17 AM Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> wrote: > > On Tue, Nov 01, 2022 at 09:32:27AM +1100, Anastasia Klimchuk wrote: > > Sergii, you mentioned in the earlier thread, you can convert the text > > to mediawiki format? That would be great! > > Also, would you be able to update the wiki page by yourself? We can > > create an account for you. > > Then you can preview/correct the text , until the result looks good to you. > > > > As we agreed in the earlier thread, this should go to > > https://www.flashrom.org/Documentation#Using_flashrom section. > > > > Thank you so much for your contributions! > > Yes, I can deal with MediaWiki and handle formatting issues myself if > I'll get an account. > > Just for information, it's trivial to convert to Wiki automatically: > > pandoc -w mediawiki bootblock-protection.md -o bootblock-protection.wiki > > The important thing is to have empty lines before lists in Markdown, > pandoc doesn't recognize lists otherwise. There can be other minor > differences. -- Anastasia.

2 1

[review] WP documentation for flashrom users
by Sergii Dmytruk 27 Oct '22

27 Oct '22

Hi again, As previously discussed on this ML, posting documentation inline for review. ================================================================================ # Firmware updates vs. SPI write-protection Enabling write-protection of any kind is meant to obstruct changing data, but it also limits what you can do to the part of firmware that's still writable. This document is meant to cover some of the origins of such limitations and situations which might arise after part of a flash chip has been protected. ## Firmware updates after locking bootblock This section is primarily concerned with `coreboot`, but similar problems can happen for any kind of firmware. ### Risks of partial updates Partial updates can produce an unbootable image if an old bootblock doesn't work with a more recent version of `coreboot`. This can be manifested in various ways ranging from an old bootblock not being able to find new romstage to system booting successfully but data in `coreboot` tables being mangled or incomplete. The incompatibilities might happen when switching version of firmware or even when using the same version with a slightly different configuration. Another thing that can potentially cause trouble is CBFS layout. When bootblock is part of CBFS, it doesn't necessarily have a fixed address, moreover it can change location as well if it depends on file size (when bootblock's last byte must be the last byte of the image, which is the case on x86). If newer bootblock is smaller such that an old WP range now covers bootblock and some other file, this file won't be fully updated due to write-protection, potentially resulting in a corrupt image. Luckily, when bootblock is the last file it's normally preceded by a significant amount of empty space, which won't let this situation to occur. On top of that, last 4 bytes of the image contain offset to the master header of CBFS. Depending on the coreboot version this offset might be crucial for the loading of romstage, in which case moving CBFS within the image without updating the offset (when it's locked by WP) can also prevent the system from booting. ### Recovering from a broken state Since broken flash won't let the system to boot, the way to fix it is to flash the chip externally by connecting it to a different device. A possible alternative could be to have a backup flash created beforehand and swapping it for the broken one (mainly applicable if swapping doesn't require soldering). ## Flashing whole firmware image The function of the hardware protection mechanism (`W#` or `W/` pin of flash chips) is to lock state of software protection thus preventing it from being disabled. After the chip is physically unlocked by changing the state of the pin, the state of the write protection doesn't change. However, in this state the protection can be easily turned off programmatically, which is what `flashrom` tries to do before performing an operation on a chip. In other words, changing state of the WP pin might be enough to be able to flash the chip in full. If `flashrom` errors or you don't want to rely on the automatic behaviour, you can try to explicitly disable the protection by running `flashrom` like this: ``` flashrom --wp-disable ``` If you need to pass extra parameters to flash your chip (e.g., programmer or chip name), add them to the above command (order of such parameters shouldn't matter). Mind that in `flashrom` the code for disabling protection automatically is different from the code which handles `--wp-disable`. This means that they can sometimes produce different results, this is why you should be aware of both code paths that affect WP. ================================================================================ # Example of partial write-protection This document provides demonstration of how one can protect part of a flash chip from writing using `flashrom` and its support for manipulating SPI write protection (WP). This kind of protection requires changing connection of WP pin of the chip to prevent any attempt of disabling the protection by software alone. **Not to be confused** with protection by flash controller of your motherboard (PCH protection). ## `flashrom` version At the time of writing (11 October 2022) there hasn't been a `flashrom` release that includes WP manipulation facilities. You might have to build one from scratch (assuming you've already installed build dependencies): ``` git clone --depth 1 https://github.com/flashrom/flashrom cd flashrom # the simplest case of building using GNU make make # flashrom executable will appear in current directory ``` ## Programmer support of WP Not all programmers support manipulating WP configuration. A suitable programmer must either provide a dedicated API for working with WP or give sufficiently comprehensive access to the interface of the flash chip. In particular, on Intel platforms *internal* programmer might allow only limited access to WP feature of chips or effectively deny it. Read "Intel chipsets" section of `flashrom`'s manpage for details on how you can try choosing sequencing type to possibly make WP work for you. In some cases external flashing might be the only option and you need to unscrew your device, find the chip, connect it to another device through a suitable adapter and finally be able to configure it as you wish. ## Chip support in `flashrom` There is a great variety of chips with some not supporting write protection at all and others doing it in their own peculiar way of which `flashrom` has no idea. So the first thing to do is to make sure that `flashrom` knows how WP works for your chip and chipset doesn't get in the way. Run a command like (adjust this and similar commands below if you're not using *internal* programmer or need to specify other options): ``` flashrom --programmer internal --wp-status ``` Seeing this output line would mean that `flashrom` doesn't know how to use WP feature of the chip you have: ``` Failed to get WP status: WP operations are not implemented for this chip ``` Otherwise the output might contain something similar to this: ``` Protection range: start=0x00000000 length=0x00000000 (none) Protection mode: disabled ``` If so, you can continue with the rest of the instructions. ## Collecting information about the range You need to know where the area you want to protect starts and ends. The example below assumes you're trying to protect bootblock stored in CBFS at the end of some `coreboot` firmware. In other cases it might be a separate file which is put at the beginning of a chip. You need to have an idea of what you're doing here or have some reliable instructions to follow. In this case `cbfstool` can be used to list information about bootblock like this: ``` $ cbfstool rom print | sed -n '2p; /bootblock/p' Name Offset Type Size Comp bootblock 0x3ef100 bootblock 36544 none ``` However, the offset is relative to the start of CBFS region, so we also need to find out offset of CBFS: ``` $ cbfstool rom layout | grep CBFS 'COREBOOT' (CBFS, size 4161536, offset 12615680) ``` Now we can calculate: * start offset (CBFS offset + 64 + bootblock offset): \ `12615680 + 64 + 0x3ef100 = 0xff7140` \ (`printf "%#x\n" $(( 12615680 + 64 + 0x3ef100 ))`) * end offset (start offset + bootblock size - 1): \ `0xff7140 + 36544 - 1 = 0xffffff` \ (`printf "%#x\n" $(( 0xff7140 + 36544 - 1 ))`) Thus we need to write-protect the smallest area that covers the range from `0xff7140` to `0xffffff` (both bounds are inclusive). "64" in the computation of start offset is offset of booblock data. Unfortunately, current tooling doesn't provide a reliable way of determining actual offset, but 64 is the typical "extra offset" one needs to add to account for file metadata of CBFS (otherwise it can be its multiple 128 or bigger). Bootblock should normally end at the last byte of ROM on x86 systems, giving you a way to test the result of computations. ## Finding a matching range In most chips the list of supported ranges is fixed and you can't specify an arbitrary one. Some others allow more fine-grained control, but that feature is not supported by `flashrom` as of now. Obtain list of supported ranges from which we'll pick the best match: ``` $ flashrom --programmer internal --wp-list ... Available protection ranges: start=0x00000000 length=0x00000000 (none) start=0x00000000 length=0x00001000 (lower 1/4096) start=0x00fff000 length=0x00001000 (upper 1/4096) start=0x00000000 length=0x00002000 (lower 1/2048) start=0x00ffe000 length=0x00002000 (upper 1/2048) start=0x00000000 length=0x00004000 (lower 1/1024) start=0x00ffc000 length=0x00004000 (upper 1/1024) start=0x00000000 length=0x00008000 (lower 1/512) start=0x00ff8000 length=0x00008000 (upper 1/512) start=0x00000000 length=0x00040000 (lower 1/64) start=0x00fc0000 length=0x00040000 (upper 1/64) start=0x00000000 length=0x00080000 (lower 1/32) start=0x00f80000 length=0x00080000 (upper 1/32) start=0x00000000 length=0x00100000 (lower 1/16) start=0x00f00000 length=0x00100000 (upper 1/16) start=0x00000000 length=0x00200000 (lower 1/8) start=0x00e00000 length=0x00200000 (upper 1/8) start=0x00000000 length=0x00400000 (lower 1/4) start=0x00c00000 length=0x00400000 (upper 1/4) start=0x00000000 length=0x00800000 (lower 1/2) start=0x00800000 length=0x00800000 (upper 1/2) start=0x00000000 length=0x00c00000 (lower 3/4) start=0x00400000 length=0x00c00000 (upper 3/4) start=0x00000000 length=0x00e00000 (lower 7/8) start=0x00200000 length=0x00e00000 (upper 7/8) start=0x00000000 length=0x00f00000 (lower 15/16) start=0x00100000 length=0x00f00000 (upper 15/16) start=0x00000000 length=0x00f80000 (lower 31/32) start=0x00080000 length=0x00f80000 (upper 31/32) start=0x00000000 length=0x00fc0000 (lower 63/64) start=0x00040000 length=0x00fc0000 (upper 63/64) start=0x00000000 length=0x00ff8000 (lower 511/512) start=0x00008000 length=0x00ff8000 (upper 511/512) start=0x00000000 length=0x00ffc000 (lower 1023/1024) start=0x00004000 length=0x00ffc000 (upper 1023/1024) start=0x00000000 length=0x00ffe000 (lower 2047/2048) start=0x00002000 length=0x00ffe000 (upper 2047/2048) start=0x00000000 length=0x00fff000 (lower 4095/4096) start=0x00001000 length=0x00fff000 (upper 4095/4096) start=0x00000000 length=0x01000000 (all) ``` Pick a range by scanning the list in the top down order (because the smaller ranges come first): - if bootblock is at the start of a chip, look for the first lower range whose length is greater than the end offset - if bootblock is at the end of a chip, look for the first upper range which starts before or at the start offset - mind that you're unlikely to find an ideal match and will probably protect more than you need; this is fine if that's just an empty space, but can cause troubles with future updates if that's some data or metadata which changes with every release This is the first upper range starting before `0xff7140`: ``` start=0x00fc0000 length=0x00040000 (upper 1/64) ``` It covers `0x00fc0000 -- 0x00ffffff` which includes our bootblock. This area takes up 256 KiB, about 7 times bigger than our bootblock, but there is no better choice in this case and output of `cbfstool rom layout` shows that we additionally include a part of 876 KiB empty space which will hopefully remain there in future firmware versions (it's a good idea to check before a firmware update). ## Protection setup The following command sets the range and enables WP at the same time, the values are taken from the chosen range above: ``` flashrom --programmer internal --wp-range=0x00fc0000,0x00040000 --wp-enable ``` You can set the range and change WP status independently as well if needed (just specify one `--wp-*` option at a time). Make sure that hardware protection is off (state of `W#`/`W/` pin of the chip) or you won't be able to change WP configuration. On success, the output of the above command will include such lines: ``` Enabled hardware protection Activated protection range: start=0x00fc0000 length=0x00040000 (upper 1/64) ``` **Caveat**: `flashrom` automatically tries to disable WP before any operation on a chip (read, write, erase, verify), so double-check status of WP before changing state of WP pin on your chip! ## Verifying hardware protection Once you've happy with the configuration and changed state of WP pin, you can try disabling WP using `flashrom` to make sure that it fails now. ================================================================================ Regards, Sergii

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Adding dev meeting info on flashrom wiki Contact page
by Anastasia Klimchuk 27 Oct '22

27 Oct '22

Hello Everyone, Around two months ago we decided to add information about dev meeting on the Contact page on the website (https://www.flashrom.org/Contact). Many apologies for the delay, but good news is that I finally got to this. So me and Felix composed the text for the Contact page (below). This information is not new, it reflects what’s already happening - the meeting runs since March and keeps going. However, the info was scattered in different places (various posts on the mailing list), so the goal is to document it and put it in a place that everyone knows where it is. Let us know if there is any feedback on the text. I plan to update Contact page around the end of week, but of course we can do amendments any time later if needed. === # Dev meeting Flashrom developers community runs an online meeting every two weeks. The main purpose of the meeting is to discuss development plans, ideas, current ongoing projects, pending patches, and sometimes organisational questions. Note this meeting is NOT: * troubleshooting session * tech support forum * user training session For questions above, please use [IRC](https://www.flashrom.org/Contact#IRC) or the [mailing list](https://www.flashrom.org/Contact#Mailing_List). ## Time of meeting It runs once every two weeks. IMPORTANT: please calculate meeting time for your local timezone. ### Between November and March (inclusive): **Wednesday 21:00-22:00 UTC+0** also known as * Wednesday 13.00-14.00 Pacific Standard Time UTC-8 * Wednesday 22.00-23.00 Central European Time UTC+1 * Thursday 8.00-9.00am Australian Eastern Daylight Time UTC+11 ### Between April and September (inclusive): **Thursday 6.00-7.00am UTC+0** also known as * Wednesday 11pm-midnight Pacific Daylight Time UTC-7 * Thursday 8.00-9.00am Central European Summer Time UTC+2 * Thursday 16.00-17.00 Australian Eastern Standard Time UTC+10 ### The last week of March and 4 weeks of October there are no meetings This is because daylight saving time changes are happening on different dates in different locations, and setting up meeting time becomes too complicated. ## FAQ ### When is the next meeting? Look into the meeting notes [document](https://docs.google.com/document/d/18qKvEbfPszjsJJGJhwi8kRVDUG3GZ…. The top entry, on the first page, with the date in the future, and empty list of attendees - is the next meeting. ### How to join the meeting? In the meeting notes [document](https://docs.google.com/document/d/18qKvEbfPszjsJJGJhwi8kRVDUG3GZ… , on the top it says “to join, click the link”, click the link. ### Do I need an invitation to join the meeting? No, just join. ### Do I need to create an account anywhere? No, you can join without an account, and view/comment on the meeting doc without an account. ### How do I add a topic to the agenda? Add comments/suggestions on the meeting doc, and they will be accepted shortly after. -- Anastasia.

1 0

Unsupported flash chip - EON (cFeon) EN25QX128A
by Olaf Drab 26 Oct '22

26 Oct '22

Hi, As you asked here is the output of flashrom -VV -p ch341a_spi >> EN25QX128A.txt. Maybe this will help you adding support for this chip. Best regards Olaf

1 0

Fwd: Gigabyte TRX40 Aorus Xtreme rev 1.0
by Aurélien Plancher 25 Oct '22

25 Oct '22

Hi, I'm trying to backup by BIOS from Linux (motherboard: Gigabyte TRX40 Aorus Xtreme rev 1.0) but I get an error. Any help appreciated. Here are the logs: *sudo flashrom -V -p internal* Flashrom v1.2 on Linux 5.13.0-39-generic (x86_64) flashrom is free software, get the source code at https://flashrom.org flashrom was built with libpci 3.6.4, GCC 9.2.1 20200304, little endian Command line (3 args): flashrom -V -p internal Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Initializing internal programmer /sys/class/mtd/mtd0 does not exist No coreboot table found. Using Internal DMI decoder. No DMI table found. Found ITE Super I/O, ID 0x8688 on port 0x2e Found chipset "AMD FP4" with PCI ID 1022:790e. Enabling flash write... SPI base address is at 0xfec10000 FCH device found but SMBus revision 0x61 does not match known values. Please report this to flashrom(a)flashrom.org and include this log and the output of lspci -nnvx, thanks!. Could not determine chipset generation.ROM strap override is not active PROBLEMS, continuing anyway *lspci -nnvx* 00:00.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Root Complex [1022:1480] Subsystem: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Root Complex [1022:1480] Flags: fast devsel 00: 22 10 80 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 80 14 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:00.2 IOMMU [0806]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse IOMMU [1022:1481] Subsystem: Advanced Micro Devices, Inc. [AMD] Starship/Matisse IOMMU [1022:1481] Flags: fast devsel Capabilities: <access denied> 00: 22 10 81 14 40 00 10 00 00 00 06 08 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 81 14 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 00:01.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482] Flags: fast devsel 00: 22 10 82 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:01.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse GPP Bridge [1022:1483] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 33 Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: d2000000-d21fffff [size=2M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 83 14 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 f1 01 00 20 20: 00 d2 10 d2 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 12 00 00:01.2 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse GPP Bridge [1022:1483] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 34 Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: d4200000-d42fffff [size=1M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 83 14 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 02 02 00 f1 01 00 20 20: 20 d4 20 d4 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 12 00 00:02.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482] Flags: fast devsel 00: 22 10 82 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:03.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482] Flags: fast devsel 00: 22 10 82 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:04.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482] Flags: fast devsel 00: 22 10 82 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:05.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482] Flags: fast devsel 00: 22 10 82 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:07.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482] Flags: fast devsel 00: 22 10 82 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:07.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Internal PCIe GPP Bridge 0 to bus[E:B] [1022:1484] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 36 Bus: primary=00, secondary=03, subordinate=03, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: [disabled] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 84 14 07 04 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 03 03 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 12 00 00:08.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482] Flags: fast devsel 00: 22 10 82 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:08.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Internal PCIe GPP Bridge 0 to bus[E:B] [1022:1484] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 37 Bus: primary=00, secondary=04, subordinate=04, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: d4100000-d41fffff [size=1M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 84 14 07 04 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 04 04 00 f1 01 00 00 20: 10 d4 10 d4 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 12 00 00:14.0 SMBus [0c05]: Advanced Micro Devices, Inc. [AMD] FCH SMBus Controller [1022:790b] (rev 61) Subsystem: Gigabyte Technology Co., Ltd FCH SMBus Controller [1458:5001] Flags: 66MHz, medium devsel Kernel modules: i2c_piix4, sp5100_tco 00: 22 10 0b 79 03 04 20 02 61 00 05 0c 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 58 14 01 50 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.3 ISA bridge [0601]: Advanced Micro Devices, Inc. [AMD] FCH LPC Bridge [1022:790e] (rev 51) Subsystem: Gigabyte Technology Co., Ltd FCH LPC Bridge [1458:5001] Flags: bus master, 66MHz, medium devsel, latency 0 00: 22 10 0e 79 0f 00 20 02 51 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 58 14 01 50 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship Device 24; Function 0 [1022:1490] Flags: fast devsel 00: 22 10 90 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.1 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship Device 24; Function 1 [1022:1491] Flags: fast devsel 00: 22 10 91 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.2 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship Device 24; Function 2 [1022:1492] Flags: fast devsel 00: 22 10 92 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.3 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship Device 24; Function 3 [1022:1493] Flags: fast devsel Kernel driver in use: k10temp Kernel modules: k10temp 00: 22 10 93 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.4 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship Device 24; Function 4 [1022:1494] Flags: fast devsel 00: 22 10 94 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.5 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship Device 24; Function 5 [1022:1495] Flags: fast devsel 00: 22 10 95 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.6 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship Device 24; Function 6 [1022:1496] Flags: fast devsel 00: 22 10 96 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.7 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship Device 24; Function 7 [1022:1497] Flags: fast devsel 00: 22 10 97 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:00.0 Non-Volatile memory controller [0108]: Samsung Electronics Co Ltd NVMe SSD Controller PM173X [144d:a824] (prog-if 02 [NVM Express]) Subsystem: Samsung Electronics Co Ltd NVMe SSD Controller PM173X [144d:a801] Flags: bus master, fast devsel, latency 0, IRQ 78, NUMA node 0 Memory at d2010000 (64-bit, non-prefetchable) [size=32K] Expansion ROM at d2000000 [disabled] [size=64K] Capabilities: <access denied> Kernel driver in use: nvme Kernel modules: nvme 00: 4d 14 24 a8 06 04 10 00 00 02 08 01 00 00 00 00 10: 04 00 01 d2 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 4d 14 01 a8 30: 00 00 30 d4 40 00 00 00 00 00 00 00 ff 01 00 00 02:00.0 Non-Volatile memory controller [0108]: Micron Technology Inc Device [1344:51b1] (rev 02) (prog-if 02 [NVM Express]) Subsystem: Micron Technology Inc Device [1344:6000] Flags: bus master, fast devsel, latency 0, IRQ 80, NUMA node 0 Memory at d4220000 (64-bit, non-prefetchable) [size=16K] Expansion ROM at d4200000 [disabled] [size=128K] Capabilities: <access denied> Kernel driver in use: nvme Kernel modules: nvme 00: 44 13 b1 51 06 04 10 00 02 02 08 01 00 00 00 00 10: 04 00 22 d4 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 44 13 00 60 30: 00 00 20 d4 c0 00 00 00 00 00 00 00 ff 01 00 00 03:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Function [1022:148a] Subsystem: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Function [1022:148a] Flags: fast devsel Capabilities: <access denied> 00: 22 10 8a 14 00 00 10 00 00 00 00 13 10 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 8a 14 30: 00 00 00 00 48 00 00 00 00 00 00 00 ff 00 00 00 04:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Reserved SPP [1022:1485] Subsystem: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Reserved SPP [1022:1485] Flags: fast devsel Capabilities: <access denied> 00: 22 10 85 14 00 00 10 00 00 00 00 13 10 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 85 14 30: 00 00 00 00 48 00 00 00 00 00 00 00 ff 00 00 00 04:00.3 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] Starship USB 3.0 Host Controller [1022:148c] (prog-if 30 [XHCI]) Subsystem: Gigabyte Technology Co., Ltd Starship USB 3.0 Host Controller [1458:5007] Flags: bus master, fast devsel, latency 0, IRQ 69 Memory at d4100000 (64-bit, non-prefetchable) [size=1M] Capabilities: <access denied> Kernel driver in use: xhci_hcd Kernel modules: xhci_pci 00: 22 10 8c 14 07 04 10 00 00 30 03 0c 10 00 80 00 10: 04 00 10 d4 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 58 14 07 50 30: 00 00 00 00 48 00 00 00 00 00 00 00 ff 03 00 00 20:00.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Root Complex [1022:1480] Subsystem: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Root Complex [1022:1480] Flags: fast devsel 00: 22 10 80 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 80 14 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20:00.2 IOMMU [0806]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse IOMMU [1022:1481] Subsystem: Advanced Micro Devices, Inc. [AMD] Starship/Matisse IOMMU [1022:1481] Flags: fast devsel Capabilities: <access denied> 00: 22 10 81 14 40 00 10 00 00 00 06 08 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 81 14 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 20:01.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482] Flags: fast devsel 00: 22 10 82 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20:02.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482] Flags: fast devsel 00: 22 10 82 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20:03.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482] Flags: fast devsel 00: 22 10 82 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20:03.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse GPP Bridge [1022:1483] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 38 Bus: primary=20, secondary=21, subordinate=21, sec-latency=0 I/O behind bridge: 00006000-00006fff [size=4K] Memory behind bridge: b2000000-b30fffff [size=17M] Prefetchable memory behind bridge: 0000009000000000-0000009801ffffff [size=32800M] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 83 14 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 20 21 21 00 61 61 00 20 20: 00 b2 00 b3 01 00 f1 01 90 00 00 00 98 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 12 00 20:04.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482] Flags: fast devsel 00: 22 10 82 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20:05.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482] Flags: fast devsel 00: 22 10 82 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20:07.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482] Flags: fast devsel 00: 22 10 82 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20:07.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Internal PCIe GPP Bridge 0 to bus[E:B] [1022:1484] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 40 Bus: primary=20, secondary=22, subordinate=22, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: [disabled] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 84 14 07 04 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 20 22 22 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 12 00 20:08.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482] Flags: fast devsel 00: 22 10 82 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20:08.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Internal PCIe GPP Bridge 0 to bus[E:B] [1022:1484] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 41 Bus: primary=20, secondary=23, subordinate=23, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: b3200000-b34fffff [size=3M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 84 14 07 04 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 20 23 23 00 f1 01 00 00 20: 20 b3 40 b3 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 12 00 21:00.0 VGA compatible controller [0300]: NVIDIA Corporation Device [10de:2684] (rev a1) (prog-if 00 [VGA controller]) Subsystem: CardExpert Technology Device [10b0:f297] Flags: bus master, fast devsel, latency 0, IRQ 629 Memory at b2000000 (32-bit, non-prefetchable) [size=16M] Memory at 9000000000 (64-bit, prefetchable) [size=32G] Memory at 9800000000 (64-bit, prefetchable) [size=32M] I/O ports at 6000 [size=128] Expansion ROM at b3000000 [virtual] [disabled] [size=512K] Capabilities: <access denied> Kernel driver in use: nvidia Kernel modules: nvidiafb, nouveau, nvidia_drm, nvidia 00: de 10 84 26 07 04 10 00 a1 00 00 03 00 00 80 00 10: 00 00 00 b2 0c 00 00 00 90 00 00 00 0c 00 00 00 20: 98 00 00 00 01 60 00 00 00 00 00 00 b0 10 97 f2 30: 00 00 00 00 60 00 00 00 00 00 00 00 ff 01 00 00 22:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Function [1022:148a] Subsystem: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Function [1022:148a] Flags: fast devsel Capabilities: <access denied> 00: 22 10 8a 14 00 00 10 00 00 00 00 13 10 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 8a 14 30: 00 00 00 00 48 00 00 00 00 00 00 00 ff 00 00 00 23:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Reserved SPP [1022:1485] Subsystem: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Reserved SPP [1022:1485] Flags: fast devsel Capabilities: <access denied> 00: 22 10 85 14 00 00 10 00 00 00 00 13 10 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 85 14 30: 00 00 00 00 48 00 00 00 00 00 00 00 ff 00 00 00 23:00.1 Encryption controller [1080]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Cryptographic Coprocessor PSPCPP [1022:1486] Subsystem: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Cryptographic Coprocessor PSPCPP [1022:1486] Flags: bus master, fast devsel, latency 0, IRQ 609 Memory at b3300000 (32-bit, non-prefetchable) [size=1M] Memory at b3400000 (32-bit, non-prefetchable) [size=8K] Capabilities: <access denied> Kernel driver in use: ccp Kernel modules: ccp 00: 22 10 86 14 06 04 10 00 00 00 80 10 10 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 30 b3 00 00 00 00 20: 00 00 00 00 00 00 40 b3 00 00 00 00 22 10 86 14 30: 00 00 00 00 48 00 00 00 00 00 00 00 ff 01 00 00 23:00.3 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] Starship USB 3.0 Host Controller [1022:148c] (prog-if 30 [XHCI]) Subsystem: Gigabyte Technology Co., Ltd Starship USB 3.0 Host Controller [1458:5007] Flags: bus master, fast devsel, latency 0, IRQ 100 Memory at b3200000 (64-bit, non-prefetchable) [size=1M] Capabilities: <access denied> Kernel driver in use: xhci_hcd Kernel modules: xhci_pci 00: 22 10 8c 14 07 04 10 00 00 30 03 0c 10 00 80 00 10: 04 00 20 b3 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 58 14 07 50 30: 00 00 00 00 48 00 00 00 00 00 00 00 ff 03 00 00 40:00.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Root Complex [1022:1480] Subsystem: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Root Complex [1022:1480] Flags: fast devsel 00: 22 10 80 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 80 14 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40:00.2 IOMMU [0806]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse IOMMU [1022:1481] Subsystem: Advanced Micro Devices, Inc. [AMD] Starship/Matisse IOMMU [1022:1481] Flags: fast devsel Capabilities: <access denied> 00: 22 10 81 14 40 00 10 00 00 00 06 08 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 81 14 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 40:01.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482] Flags: fast devsel 00: 22 10 82 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40:01.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse GPP Bridge [1022:1483] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 42 Bus: primary=40, secondary=41, subordinate=4a, sec-latency=0 I/O behind bridge: 00009000-00009fff [size=4K] Memory behind bridge: b6000000-b70fffff [size=17M] Prefetchable memory behind bridge: 00000000b8000000-00000000b88fffff [size=9M] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 83 14 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 40 41 4a 00 91 91 00 20 20: 00 b6 00 b7 01 b8 81 b8 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 12 00 40:01.3 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse GPP Bridge [1022:1483] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 43 Bus: primary=40, secondary=4b, subordinate=4b, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: cd700000-cd7fffff [size=1M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 83 14 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 40 4b 4b 00 f1 01 00 20 20: 70 cd 70 cd f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 12 00 40:02.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482] Flags: fast devsel 00: 22 10 82 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40:03.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482] Flags: fast devsel 00: 22 10 82 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40:03.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse GPP Bridge [1022:1483] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 44 Bus: primary=40, secondary=4c, subordinate=5d, sec-latency=0 I/O behind bridge: 00007000-00008fff [size=8K] Memory behind bridge: bcc00000-ccdfffff [size=258M] Prefetchable memory behind bridge: 00000000b8a00000-00000000bc9fffff [size=64M] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 83 14 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 40 4c 5d 00 71 81 00 20 20: c0 bc d0 cc a1 b8 91 bc 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 12 00 40:04.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482] Flags: fast devsel 00: 22 10 82 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40:05.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482] Flags: fast devsel 00: 22 10 82 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40:07.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482] Flags: fast devsel 00: 22 10 82 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40:07.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Internal PCIe GPP Bridge 0 to bus[E:B] [1022:1484] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 46 Bus: primary=40, secondary=5e, subordinate=5e, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: [disabled] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 84 14 07 04 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 40 5e 5e 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 12 00 40:08.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482] Flags: fast devsel 00: 22 10 82 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40:08.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Internal PCIe GPP Bridge 0 to bus[E:B] [1022:1484] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 48 Bus: primary=40, secondary=5f, subordinate=5f, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: [disabled] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 84 14 07 04 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 40 5f 5f 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 12 00 41:00.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Matisse Switch Upstream [1022:57ad] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 26 Bus: primary=41, secondary=42, subordinate=4a, sec-latency=0 I/O behind bridge: 00009000-00009fff [size=4K] Memory behind bridge: b6000000-b70fffff [size=17M] Prefetchable memory behind bridge: 00000000b8000000-00000000b88fffff [size=9M] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 ad 57 07 00 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 41 42 4a 00 91 91 00 00 20: 00 b6 00 b7 01 b8 81 b8 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 12 00 42:01.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Matisse PCIe GPP Bridge [1022:57a3] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 49 Bus: primary=42, secondary=43, subordinate=43, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: b6000000-b60fffff [size=1M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 a3 57 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 42 43 43 00 f1 01 00 00 20: 00 b6 00 b6 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 12 00 42:02.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Matisse PCIe GPP Bridge [1022:57a3] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 50 Bus: primary=42, secondary=44, subordinate=44, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: b6100000-b69fffff [size=9M] Prefetchable memory behind bridge: 00000000b8000000-00000000b88fffff [size=9M] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 a3 57 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 42 44 44 00 f1 01 00 20 20: 10 b6 90 b6 01 b8 81 b8 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 12 00 42:03.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Matisse PCIe GPP Bridge [1022:57a3] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 51 Bus: primary=42, secondary=45, subordinate=45, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: b6a00000-b6afffff [size=1M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 a3 57 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 42 45 45 00 f1 01 00 00 20: a0 b6 a0 b6 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 12 00 42:04.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Matisse PCIe GPP Bridge [1022:57a3] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 52 Bus: primary=42, secondary=46, subordinate=46, sec-latency=0 I/O behind bridge: 00009000-00009fff [size=4K] Memory behind bridge: b6b00000-b6bfffff [size=1M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 a3 57 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 42 46 46 00 91 91 00 20 20: b0 b6 b0 b6 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 12 00 42:05.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Matisse PCIe GPP Bridge [1022:57a3] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 53 Bus: primary=42, secondary=47, subordinate=47, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: b6c00000-b6cfffff [size=1M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 a3 57 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 42 47 47 00 f1 01 00 00 20: c0 b6 c0 b6 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 12 00 42:08.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Matisse PCIe GPP Bridge [1022:57a4] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 54 Bus: primary=42, secondary=48, subordinate=48, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: b6d00000-b6efffff [size=2M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 a4 57 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 42 48 48 00 f1 01 00 00 20: d0 b6 e0 b6 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 12 00 42:09.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Matisse PCIe GPP Bridge [1022:57a4] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 56 Bus: primary=42, secondary=49, subordinate=49, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: b6f00000-b6ffffff [size=1M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 a4 57 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 42 49 49 00 f1 01 00 00 20: f0 b6 f0 b6 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 12 00 42:0a.0 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Matisse PCIe GPP Bridge [1022:57a4] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 58 Bus: primary=42, secondary=4a, subordinate=4a, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: b7000000-b70fffff [size=1M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 a4 57 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 42 4a 4a 00 f1 01 00 00 20: 00 b7 00 b7 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 12 00 43:00.0 Non-Volatile memory controller [0108]: Micron Technology Inc Device [1344:51b1] (rev 02) (prog-if 02 [NVM Express]) Subsystem: Micron Technology Inc Device [1344:6000] Flags: bus master, fast devsel, latency 0, IRQ 55, NUMA node 0 Memory at b6000000 (64-bit, non-prefetchable) [size=16K] Expansion ROM at <ignored> [disabled] Capabilities: <access denied> Kernel driver in use: nvme Kernel modules: nvme 00: 44 13 b1 51 06 04 10 00 02 02 08 01 00 00 00 00 10: 04 00 00 b6 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 44 13 00 60 30: 00 00 60 cd c0 00 00 00 00 00 00 00 ff 01 00 00 44:00.0 Ethernet controller [0200]: Intel Corporation Ethernet Controller 10G X550T [8086:1563] (rev 01) Subsystem: Gigabyte Technology Co., Ltd Ethernet Controller 10G X550T [1458:e000] Flags: bus master, fast devsel, latency 0, IRQ 57 Memory at b8400000 (64-bit, prefetchable) [size=4M] Memory at b8804000 (64-bit, prefetchable) [size=16K] Expansion ROM at b8880000 [disabled] [size=512K] Capabilities: <access denied> Kernel driver in use: ixgbe Kernel modules: ixgbe 00: 86 80 63 15 06 04 10 00 01 00 00 02 00 00 80 00 10: 0c 00 40 b8 00 00 00 00 00 00 00 00 00 00 00 00 20: 0c 40 80 b8 00 00 00 00 00 00 00 00 58 14 00 e0 30: 00 00 58 cd 40 00 00 00 00 00 00 00 ff 01 00 00 44:00.1 Ethernet controller [0200]: Intel Corporation Ethernet Controller 10G X550T [8086:1563] (rev 01) Subsystem: Gigabyte Technology Co., Ltd Ethernet Controller 10G X550T [1458:e000] Flags: bus master, fast devsel, latency 0, IRQ 204 Memory at b8000000 (64-bit, prefetchable) [size=4M] Memory at b8800000 (64-bit, prefetchable) [size=16K] Expansion ROM at <ignored> [disabled] Capabilities: <access denied> Kernel driver in use: ixgbe Kernel modules: ixgbe 00: 86 80 63 15 06 04 10 00 01 00 00 02 10 00 80 00 10: 0c 00 00 b8 00 00 00 00 00 00 00 00 00 00 00 00 20: 0c 00 80 b8 00 00 00 00 00 00 00 00 58 14 00 e0 30: 00 00 50 cd 40 00 00 00 00 00 00 00 ff 02 00 00 45:00.0 USB controller [0c03]: ASMedia Technology Inc. ASM2142 USB 3.1 Host Controller [1b21:2142] (prog-if 30 [XHCI]) Subsystem: Gigabyte Technology Co., Ltd ASM2142 USB 3.1 Host Controller [1458:5007] Flags: bus master, fast devsel, latency 0, IRQ 204 Memory at b6a00000 (64-bit, non-prefetchable) [size=32K] Capabilities: <access denied> Kernel driver in use: xhci_hcd Kernel modules: xhci_pci 00: 21 1b 42 21 06 04 10 00 00 30 03 0c 10 00 00 00 10: 04 00 a0 b6 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 58 14 07 50 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 00 00 46:00.0 SATA controller [0106]: ASMedia Technology Inc. ASM1062 Serial ATA Controller [1b21:0612] (rev 02) (prog-if 01 [AHCI 1.0]) DeviceName: Onboard LAN RTL8111 Subsystem: ASMedia Technology Inc. ASM1062 Serial ATA Controller [1b21:1060] Flags: bus master, fast devsel, latency 0, IRQ 88 I/O ports at 9050 [size=8] I/O ports at 9040 [size=4] I/O ports at 9030 [size=8] I/O ports at 9020 [size=4] I/O ports at 9000 [size=32] Memory at b6b00000 (32-bit, non-prefetchable) [size=512] Capabilities: <access denied> Kernel driver in use: ahci Kernel modules: ahci 00: 21 1b 12 06 07 04 10 00 02 01 06 01 00 00 00 00 10: 51 90 00 00 41 90 00 00 31 90 00 00 21 90 00 00 20: 01 90 00 00 00 00 b0 b6 00 00 00 00 21 1b 60 10 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 00 00 47:00.0 Network controller [0280]: Intel Corporation Wi-Fi 6 AX200 [8086:2723] (rev 1a) Subsystem: Intel Corporation Wi-Fi 6 AX200 [8086:0084] Flags: bus master, fast devsel, latency 0, IRQ 55 Memory at b6c00000 (64-bit, non-prefetchable) [size=16K] Capabilities: <access denied> Kernel driver in use: iwlwifi Kernel modules: iwlwifi 00: 86 80 23 27 06 04 10 00 1a 00 80 02 10 00 00 00 10: 04 00 c0 b6 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 84 00 30: 00 00 00 00 c8 00 00 00 00 00 00 00 ff 01 00 00 48:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Reserved SPP [1022:1485] Subsystem: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Reserved SPP [1022:1485] Flags: fast devsel Capabilities: <access denied> 00: 22 10 85 14 00 00 10 00 00 00 00 13 10 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 85 14 30: 00 00 00 00 48 00 00 00 00 00 00 00 ff 00 00 00 48:00.1 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] Matisse USB 3.0 Host Controller [1022:149c] (prog-if 30 [XHCI]) Subsystem: Advanced Micro Devices, Inc. [AMD] Matisse USB 3.0 Host Controller [1022:1486] Flags: bus master, fast devsel, latency 0, IRQ 213 Memory at b6d00000 (64-bit, non-prefetchable) [size=1M] Capabilities: <access denied> Kernel driver in use: xhci_hcd Kernel modules: xhci_pci 00: 22 10 9c 14 07 04 10 00 00 30 03 0c 10 00 80 00 10: 04 00 d0 b6 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 86 14 30: 00 00 00 00 48 00 00 00 00 00 00 00 ff 01 00 00 48:00.3 USB controller [0c03]: Advanced Micro Devices, Inc. [AMD] Matisse USB 3.0 Host Controller [1022:149c] (prog-if 30 [XHCI]) Subsystem: Advanced Micro Devices, Inc. [AMD] Matisse USB 3.0 Host Controller [1022:148c] Flags: bus master, fast devsel, latency 0, IRQ 57 Memory at b6e00000 (64-bit, non-prefetchable) [size=1M] Capabilities: <access denied> Kernel driver in use: xhci_hcd Kernel modules: xhci_pci 00: 22 10 9c 14 07 04 10 00 00 30 03 0c 10 00 80 00 10: 04 00 e0 b6 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 8c 14 30: 00 00 00 00 48 00 00 00 00 00 00 00 ff 03 00 00 49:00.0 SATA controller [0106]: Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI mode] [1022:7901] (rev 51) (prog-if 01 [AHCI 1.0]) DeviceName: X570/590 SATA0 Subsystem: Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI mode] [1022:7901] Flags: bus master, fast devsel, latency 0, IRQ 109 Memory at b6f00000 (32-bit, non-prefetchable) [size=2K] Capabilities: <access denied> Kernel driver in use: ahci Kernel modules: ahci 00: 22 10 01 79 07 04 10 00 51 01 06 01 10 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 f0 b6 00 00 00 00 22 10 01 79 30: 00 00 00 00 48 00 00 00 00 00 00 00 ff 01 00 00 4a:00.0 SATA controller [0106]: Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI mode] [1022:7901] (rev 51) (prog-if 01 [AHCI 1.0]) DeviceName: X570/590 SATA1 Subsystem: Advanced Micro Devices, Inc. [AMD] FCH SATA Controller [AHCI mode] [1022:7901] Flags: bus master, fast devsel, latency 0, IRQ 188 Memory at b7000000 (32-bit, non-prefetchable) [size=2K] Capabilities: <access denied> Kernel driver in use: ahci Kernel modules: ahci 00: 22 10 01 79 07 04 10 00 51 01 06 01 10 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 b7 00 00 00 00 22 10 01 79 30: 00 00 00 00 48 00 00 00 00 00 00 00 ff 01 00 00 4b:00.0 Multimedia video controller [0400]: Blackmagic Design DeckLink 4K Extreme 12G [bdbd:a136] Subsystem: Blackmagic Design DeckLink 4K Extreme 12G [bdbd:a136] Flags: bus master, fast devsel, latency 0, IRQ 608 Memory at cd700000 (64-bit, non-prefetchable) [size=1M] Capabilities: <access denied> Kernel driver in use: blackmagic-io Kernel modules: blackmagic_io 00: bd bd 36 a1 06 04 10 00 00 00 00 04 00 00 00 00 10: 04 00 70 cd 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 bd bd 36 a1 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 01 00 00 4c:00.0 PCI bridge [0604]: Intel Corporation JHL7540 Thunderbolt 3 Bridge [Titan Ridge 4C 2018] [8086:15ea] (rev 06) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 59 Bus: primary=4c, secondary=4d, subordinate=5d, sec-latency=0 I/O behind bridge: 00007000-00008fff [size=8K] Memory behind bridge: bcc00000-ccdfffff [size=258M] Prefetchable memory behind bridge: 00000000b8a00000-00000000bc9fffff [size=64M] Capabilities: <access denied> Kernel driver in use: pcieport 00: 86 80 ea 15 07 04 10 00 06 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 4c 4d 5d 00 71 81 00 00 20: c0 bc d0 cc a1 b8 91 bc 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 ff 01 02 00 4d:00.0 PCI bridge [0604]: Intel Corporation JHL7540 Thunderbolt 3 Bridge [Titan Ridge 4C 2018] [8086:15ea] (rev 06) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 60 Bus: primary=4d, secondary=4e, subordinate=4e, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: ccd00000-ccdfffff [size=1M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 86 80 ea 15 07 04 10 00 06 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 4d 4e 4e 00 f1 01 00 00 20: d0 cc d0 cc f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 ff 01 02 00 4d:01.0 PCI bridge [0604]: Intel Corporation JHL7540 Thunderbolt 3 Bridge [Titan Ridge 4C 2018] [8086:15ea] (rev 06) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 62 Bus: primary=4d, secondary=4f, subordinate=55, sec-latency=0 I/O behind bridge: 00007000-00007fff [size=4K] Memory behind bridge: c4c00000-ccbfffff [size=128M] Prefetchable memory behind bridge: 00000000baa00000-00000000bc9fffff [size=32M] Capabilities: <access denied> Kernel driver in use: pcieport 00: 86 80 ea 15 07 04 10 00 06 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 4d 4f 55 00 71 71 00 00 20: c0 c4 b0 cc a1 ba 91 bc 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 ff 01 02 00 4d:02.0 PCI bridge [0604]: Intel Corporation JHL7540 Thunderbolt 3 Bridge [Titan Ridge 4C 2018] [8086:15ea] (rev 06) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 63 Bus: primary=4d, secondary=56, subordinate=56, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: ccc00000-cccfffff [size=1M] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 86 80 ea 15 07 04 10 00 06 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 4d 56 56 00 f1 01 00 00 20: c0 cc c0 cc f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 ff 01 02 00 4d:04.0 PCI bridge [0604]: Intel Corporation JHL7540 Thunderbolt 3 Bridge [Titan Ridge 4C 2018] [8086:15ea] (rev 06) (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 64 Bus: primary=4d, secondary=57, subordinate=5d, sec-latency=0 I/O behind bridge: 00008000-00008fff [size=4K] Memory behind bridge: bcc00000-c4bfffff [size=128M] Prefetchable memory behind bridge: 00000000b8a00000-00000000ba9fffff [size=32M] Capabilities: <access denied> Kernel driver in use: pcieport 00: 86 80 ea 15 07 04 10 00 06 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 4d 57 5d 00 81 81 00 00 20: c0 bc b0 c4 a1 b8 91 ba 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 ff 01 02 00 4e:00.0 System peripheral [0880]: Intel Corporation JHL7540 Thunderbolt 3 NHI [Titan Ridge 4C 2018] [8086:15eb] (rev 06) Subsystem: Gigabyte Technology Co., Ltd JHL7540 Thunderbolt 3 NHI [Titan Ridge 4C 2018] [1458:a207] Flags: bus master, fast devsel, latency 0, IRQ 27 Memory at ccd00000 (32-bit, non-prefetchable) [size=256K] Memory at ccd40000 (32-bit, non-prefetchable) [size=4K] Capabilities: <access denied> Kernel driver in use: thunderbolt Kernel modules: thunderbolt 00: 86 80 eb 15 07 04 10 00 06 00 80 08 10 00 00 00 10: 00 00 d0 cc 00 00 d4 cc 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 58 14 07 a2 30: 00 00 00 00 80 00 00 00 00 00 00 00 ff 01 00 00 56:00.0 USB controller [0c03]: Intel Corporation JHL7540 Thunderbolt 3 USB Controller [Titan Ridge 4C 2018] [8086:15ec] (rev 06) (prog-if 30 [XHCI]) Subsystem: Gigabyte Technology Co., Ltd JHL7540 Thunderbolt 3 USB Controller [Titan Ridge 4C 2018] [1458:a207] Flags: fast devsel, IRQ 222 Memory at ccc00000 (32-bit, non-prefetchable) [size=64K] Capabilities: <access denied> Kernel driver in use: xhci_hcd Kernel modules: xhci_pci 00: 86 80 ec 15 03 04 10 00 06 30 03 0c 10 00 00 00 10: 00 00 c0 cc 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 58 14 07 a2 30: 00 00 00 00 80 00 00 00 00 00 00 00 ff 01 00 00 5e:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Function [1022:148a] Subsystem: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Function [1022:148a] Flags: fast devsel Capabilities: <access denied> 00: 22 10 8a 14 00 00 10 00 00 00 00 13 10 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 8a 14 30: 00 00 00 00 48 00 00 00 00 00 00 00 ff 00 00 00 5f:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Reserved SPP [1022:1485] Subsystem: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Reserved SPP [1022:1485] Flags: fast devsel Capabilities: <access denied> 00: 22 10 85 14 00 00 10 00 00 00 00 13 10 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 85 14 30: 00 00 00 00 48 00 00 00 00 00 00 00 ff 00 00 00 60:00.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Root Complex [1022:1480] Subsystem: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Root Complex [1022:1480] Flags: fast devsel 00: 22 10 80 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 80 14 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60:00.2 IOMMU [0806]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse IOMMU [1022:1481] Subsystem: Advanced Micro Devices, Inc. [AMD] Starship/Matisse IOMMU [1022:1481] Flags: fast devsel Capabilities: <access denied> 00: 22 10 81 14 40 00 10 00 00 00 06 08 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 81 14 30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 00 00 00 60:01.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482] Flags: fast devsel 00: 22 10 82 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60:02.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482] Flags: fast devsel 00: 22 10 82 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60:03.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482] Flags: fast devsel 00: 22 10 82 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60:04.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482] Flags: fast devsel 00: 22 10 82 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60:05.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482] Flags: fast devsel 00: 22 10 82 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60:07.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482] Flags: fast devsel 00: 22 10 82 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60:07.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Internal PCIe GPP Bridge 0 to bus[E:B] [1022:1484] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 66 Bus: primary=60, secondary=61, subordinate=61, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: [disabled] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 84 14 07 04 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 60 61 61 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 12 00 60:08.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Host Bridge [1022:1482] Flags: fast devsel 00: 22 10 82 14 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60:08.1 PCI bridge [0604]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Internal PCIe GPP Bridge 0 to bus[E:B] [1022:1484] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0, IRQ 68 Bus: primary=60, secondary=62, subordinate=62, sec-latency=0 I/O behind bridge: [disabled] Memory behind bridge: [disabled] Prefetchable memory behind bridge: [disabled] Capabilities: <access denied> Kernel driver in use: pcieport 00: 22 10 84 14 07 04 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 60 62 62 00 f1 01 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 12 00 61:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Function [1022:148a] Subsystem: Advanced Micro Devices, Inc. [AMD] Starship/Matisse PCIe Dummy Function [1022:148a] Flags: fast devsel Capabilities: <access denied> 00: 22 10 8a 14 00 00 10 00 00 00 00 13 10 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 8a 14 30: 00 00 00 00 48 00 00 00 00 00 00 00 ff 00 00 00 62:00.0 Non-Essential Instrumentation [1300]: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Reserved SPP [1022:1485] Subsystem: Advanced Micro Devices, Inc. [AMD] Starship/Matisse Reserved SPP [1022:1485] Flags: fast devsel Capabilities: <access denied> 00: 22 10 85 14 00 00 10 00 00 00 00 13 10 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 85 14 30: 00 00 00 00 48 00 00 00 00 00 00 00 ff 00 00 00

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