flashrom March 2023

flashrom@flashrom.org

21 participants
27 discussions

Release schedule
by Anastasia Klimchuk 06 Mar '23

06 Mar '23

Good Day flashrom, We had an important decision about flashrom release schedule recently, and it went to the mailing list as a part of dev meeting notes (22.02.2023). However, the topic is big enough to have a dedicated thread on the mailing list. We decided to make releases twice a year: one in spring/autumn, and another one in autumn/spring. The idea is that no one has to make a release in summer. Specifically, the plan is to have two release windows per year, the duration of a window is 3-4 weeks (4 weeks max hard limit): end of April-May end of September-October What is happening during release window: #1 No new features merged #2 Active testing and bug fixing #3 Bug fixes patches are really welcome, and are merged #3 If the bug is critical and release blocking, it either needs to be fixed or code needs to be reverted. Just to be clear: release window meant to be fixed (3-4 weeks) and not extended, because that will be effectively a "feature freeze" window. At the end of the window, we put a release candidate tag and make a release branch. If later a point release is needed, it goes to the branch. Specifically, what does it mean for this year: if you are planning to contribute a patch/feature/bugfix, you have time until mid-April to get into 1.4 release. If not, then you have time until mid-September to get into 1.5. Having said that, this is the first year we are trying to have a release schedule and it is possible that during this first year we will learn some lessons and then adjust and improve :) Also, there is a page on the website about the release process, but it is out of date at the moment. It will be updated later with all the info. -- Anastasia.

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FAILED: <Acer Spin 713 -2W-36LN (comet lake)>
by orico orico 05 Mar '23

05 Mar '23

Hi, I tried your script and the flashing has failed on my chromebook spin 713. I am stucked and can not turn my chromebook off or reboot. Please help!!! Best regards Dan. Here are the details: flashrom bc6a1b93 on Linux 4.19.268-14368-gaeea1ff85784 (x86_64)Hardware sequencing reports 1 attached SPI flash chip with a density of 16384 kB.There is only one partition containing the whole address space (0x000000 - 0xffffff).There are 4096 erase blocks with 4096 B each.Added layout entry 00000000 - 00ffffff named complete flashFound Winbond flash chip "W25Q128.V..M" (16384 kB, Programmer-specific) on internal.Found Winbond flash chip "W25Q128.V..M" (16384 kB, Programmer-specific).This chip may contain one-time programmable memory. flashrom cannot readand may never be able to write it, hence it may not be able to completelyclone the contents of this chip (see man page for details).Reading Status registerHSFC: FGO=1, FCYCLE=8, WET=0, FDBC=0, SME=0Block protection is disabled.Reading ich descriptor... read_flash: Flash Descriptor region (00000000..0x000fff) is readable, reading range (00000000..0x000fff).Reading 4096 bytes starting at 0x000000.HSFC: FGO=1, FCYCLE=0, WET=0, FDBC=63, SME=0HSFC: FGO=1, FCYCLE=0, WET=0, FDBC=63, SME=0HSFC: FGO=1, FCYCLE=0, WET=0, FDBC=63, SME=0 ... HSFC: FGO=1, FCYCLE=0, WET=0, FDBC=63, SME=0HSFC: FGO=1, FCYCLE=0, WET=0, FDBC=63, SME=0HSFC: FGO=1, FCYCLE=0, WET=0, FDBC=63, SME=0HSFC: FGO=1, FCYCLE=0, WET=0, FDBC=63, SME=0HSFC: FGO=1, FCYCLE=0, WET=0, FDBC=63, SME=0HSFC: FGO=1, FCYCLE=0, WET=0, FDBC=63, SME=0HSFC: FGO=1, FCYCLE=0, WET=0, FDBC=63, SME=0HSFC: FGO=1, FCYCLE=0, WET=0, FDBC=63, SME=0HSFC: FGO=1, FCYCLE=0, WET=0, FDBC=63, SME=0HSFC: FGO=1, FCYCLE=0, WET=0, FDBC=63, SME=0HSFC: FGO=1, FCYCLE=0, WET=0, FDBC=63, SME=0HSFC: FGO=1, FCYCLE=0, WET=0, FDBC=63, SME=0HSFC: FGO=1, FCYCLE=0, WET=0, FDBC=63, SME=0HSFC: FGO=1, FCYCLE=0, WET=0, FDBC=63, SME=0 ... done.Assuming chipset '300 series Cannon Point'.Added layout entry 00000000 - 00000fff named fdAdded layout entry 00400000 - 00ffffff named biosAdded layout entry 00001000 - 003fffff named merestore_power_management: Re-enabling power management.Using region: "bios".Flash image seems to be a legacy BIOS. Disabling coreboot-related checks.disable_power_management: Disabling power management.Reading Status registerHSFC: FGO=1, FCYCLE=8, WET=0, FDBC=0, SME=0Block protection is disabled.Reading old flash chip contents... read_flash: BIOS region (0x400000..0xffffff) is readable, reading range (0x400000..0xffffff).Reading 12582912 bytes starting at 0x400000.HSFC: FGO=1, FCYCLE=0, WET=0, FDBC=63, SME=0 ... HSFC: FGO=1, FCYCLE=0, WET=0, FDBC=63, SME=0done.fix_erasers_if_needed: kept eraser at 0fill_sorted_erasers: found 1 valid erasersad0000..ad1fff 1000 x 2 eraser 0ae0000..ae1fff 1000 x 2 eraser 0af0000..af0fff 1000 x 1 eraser 0af4000..af5fff 1000 x 2 eraser 0af8000..af8fff 1000 x 1 eraser 0afa000..afafff 1000 x 1 eraser 0b00000..bfafff 1000 x 251 eraser 0bff000..bfffff 1000 x 1 eraser 0c04000..d09fff 1000 x 262 eraser 0d0e000..e1cfff 1000 x 271 eraser 0ff3000..ffffff 1000 x 13 eraser 0Erasing and writing flash chip... 0xad0000-0xad0fff: EErasing 4096 bytes starting at 0xad0000.HSFC: FGO=1, FCYCLE=3, WET=0, FDBC=0, SME=0Transaction error between offset 0x00ad0000 and 0x00ad0000 (= 0x00ad0000 + 0)!HSFS: FDONE=1, FCERR=1, AEL=0, SCIP=0, PRR34_LOCKDN=0, WRSDIS=0, FDOPSS=1, FDV=1, FLOCKDN=1HSFC: FGO=0, FCYCLE=3, WET=0, FDBC=0, SME=0 ERASE_FAILEDFAILED!Uh oh. Erase/write failed. Your flash chip is in an unknown state.Get help on IRC (see https://www.flashrom.org/Contact) or mailflashrom(a)flashrom.org with the subject "FAILED: <your board name>"!-------------------------------------------------------------------------------DO NOT REBOOT OR POWEROFF!restore_power_management: Re-enabling power management.FAILEDRestoring PCI config space for 00:1f:5 reg 0xdcAn error occurred flashing the Full ROM firmware. DO NOT REBOOT!

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AM29LV040B writes work fine
by Alex Perez 04 Mar '23

04 Mar '23

Hi there, I'd like to report that, when flashing the AM29LV040B with -p satasii (attached to a PCI SATA card) writes work fine. Write Protect does NOT work.

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Optimized Erase Function Selection Algorithm
by Aarya Chaumal 03 Mar '23

03 Mar '23

Hi everyone, I am excited to announce that we've added the optimized erase function selection algorithm to the master branch. It will optimally select the erase functions according to the flash region to erase/write. This should make using our application quicker and more convenient. Please ensure you have the latest source code to test the new feature. Do the following change to the flashrom.c file : ``` -static bool use_legacy_erase_path = true; +static bool use_legacy_erase_path = false; ``` and build flashrom using make or meson. Makefile: ``` $ make clean && make ``` Meson: ``` $ meson setup out $ ninja -C out ``` This feature offers the following: - Lesser flash erase/write times (upto 80 times less on tests done so far) On the long term, we plan to enable feature by default. For now, you need to enable it manually and rebuild from source code. We would love to hear your feedback! Please let us know if you have any questions or encounter any issues. -Aarya

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Flashrom experimental chip support report
by Sadoon Albader 01 Mar '23

01 Mar '23

Hi, I just flashed a firmware image to a "XM25QH64C" which is labeled experimental, the flash was successful with default options on a ch341a_spi clone, here is the log. Sorry I couldn't get the debug output. Reading and writing worked just fine. Thanks a lot for maintaining this awesome software! I used the git master branch version as of today.

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W25Q32FVSIG
by verithas＠danwin1210.de 01 Mar '23

01 Mar '23

Hello, i have a problem. I build coreboot rom and write it with option in menu security: Boot media protection mechanism < Lock boot media using the chip Chip is W25Q32JVSIG After this option I can't erase the chip, log says: root@devuan:/home/user/Documents/flashrom-v1.3.0# ./flashrom --programmer ch341a_spi -E flashrom v1.3.0 on Linux 5.15.41-hardened1 (x86_64) flashrom is free software, get the source code at https://flashrom.org Calibrating delay loop... OK. Found Winbond flash chip "W25Q32.V" (4096 kB, SPI) on ch341a_spi. === This flash part has status UNTESTED for operations: WP The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash chip. Please include the flashrom log file for all operations you tested (see the man page for details), and mention which mainboard or programmer you tested in the subject line. Thanks for your help! Erasing and writing flash chip... FAILED at 0x00300000! Expected=0xff, Found=0x5f, failed byte count from 0x00300000-0x00300fff: 0xddf ERASE FAILED! Looking for another erase function. FAILED at 0x00300000! Expected=0xff, Found=0x5f, failed byte count from 0x00300000-0x00307fff: 0x7883 ERASE FAILED! Looking for another erase function. FAILED at 0x00300000! Expected=0xff, Found=0x5f, failed byte count from 0x00300000-0x0030ffff: 0xf6c5 ERASE FAILED! Looking for another erase function. Option with --wp-disable is not work for W25Q32FVSIG I have a W25Q128FVSIG chip, and option --wp-disable is work. Datasheets with chips is same, different in memory size. I hope the problem will be fixed soon Thanks for attention. Regards.

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Successfully read an XM25QH256C with a CH341a based programmer.
by James Russell 01 Mar '23

01 Mar '23

Hi, I just did a backup of the BIOS chip of a new laptop I got. in case something happened to be able to restore it all to sane defaults. Freshly built Flashrom snapshot on a live Arch (Manjaro) environment, the chip is an XM25QH256C[XIQ] in a WSON8 package (6x8), I didn't want to desolder the chip and I noticed some exposed solder where the contacts would be so I did the dump using a pogo pin contraption attached to the CH341a. It is an old programmer I've had for years (I don't think there's any cheap-ish alternative using at least USB 2.0 that is supported by Flashrom, so... it was slow), both Vcc and the data lines ran at 3.3-ish volts. After the message that appeared during the read I thought "damn, I didn't enable verbose output nor was I logging the operation", so I did a verify operation afterwards which is essentially the same. Log is attached and if you need the contents of the ROM I can attach them too (32MiB). I didn't do much in-depth analysis of the ROM but it seems correct, at least I can see UEFI and ME structures in there. Sadly, I don't plan on writing to that chip anytime soon, at least not until I get a replacement because the setup is not very stable and I don't want to risk the connection getting interrupted. These XMC chips are hard to come by in my area, but Mouser sells an equivalent Winbond that is also supported and is greenlit to be used in this laptop; so I had ordered one of those to have at hand. Anyway, I digress haha, you have the Verify log attached to this email (I thought there'd be more data there). Regards, James. PS. I think it's not implemented, but perhaps adding a progress indicator (since the flash chip's size is known) to read/write operations would be handy, if it weren't for an indicator LED on my programmer board I wouldn't really know if it was progressing or not.

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flashrom March 2023