September 2017 - flashrom - mail.coreboot.org

Re: [flashrom] read BIOS settings
by Nico Huber Sept. 16, 2017

Sept. 16, 2017

Hi Adam, On 14.09.2017 11:43, Adam Makkos wrote: > Hi, > > Can you please tell if flashrom is able to also read bios settings? that depends, of course, where the settings are stored and that varies from device to device (modern PCs usually store them in the BIOS flash). Though, even if they happen to be stored in a flash readable by flash- rom, it will never decode BIOS settings. Flashrom simply dumps the plain data and will never understand the storage format of BIOS settings. > I need to check a lot of linux computers if sata is set to ahci, and pxe > boot is disabled. > Can I use flashrom for it? Only if you know how to decode the data yourself. If your systems run UEFI firmware and you run your Linux in EFI mode, you might have better chances to get that information through EFI services. I don't know about the usual "BIOS" settings, but EFI has a concept of runtime variables that are readable from the OS, see e.g. [1]. Hope that helps, Nico [1] https://firmware.intel.com/blog/accessing-uefi-variables-linux

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read BIOS settings
by Adam Makkos Sept. 14, 2017

Sept. 14, 2017

Hi, Can you please tell if flashrom is able to also read bios settings? I need to check a lot of linux computers if sata is set to ahci, and pxe boot is disabled. Can I use flashrom for it? I did not find that info in FAQ and man. Adam

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modifying the BIOS of an Acer C720 from within FreeBSD CURRENT
by Matthias Apitz Sept. 12, 2017

Sept. 12, 2017

Hello, This is with flashrom of FreeBSD CURRENT amd64. The background: To be able to install and boot FreeBSD on an Acer C720 Chromebook, one must tweak some bits in the BIOS and enable a so called LEGACY BIOS mode (after removing the hardware write protection of the BIOS). To do so, there are some tools within ChromeOS which allow this procedure, but after this you can not boot ChromeOS anymore (from the saved SSD) and so you can't use these tools within ChromeOS to switch the bits back. The tools to use are simple: # flashrom -p internal -i GBB -r bios.bin # futility gbb -s --flags=$flags bios.bin # flashrom -p host -i GBB --fast-verify -w bios.bin Flashrom we have in the FreeBSD ports as sysutils/flashrom and it seems to works: $ flashrom -R flashrom v0.9.9-r1955 on FreeBSD 12.0-CURRENT (amd64) flashrom is free software, get the source code at https://flashrom.org $ flashrom -L | egrep -i 'acer|720|chro' Acer V75-M OK Acer EM61SM/EM61PM OK GIGABYTE GA-M720-US3 OK MSI MS-7207 (K8NGM2-L) OK (autodetected) Acer Aspire 1520 OK Acer Aspire One BAD $ flashrom -p internal -i GBB -r bios.bin flashrom v0.9.9-r1955 on FreeBSD 12.0-CURRENT (amd64) flashrom is free software, get the source code at https://flashrom.org Region requested (with -i "GBB"), but no layout data is available. What does this error message mean? Thanks matthias -- Matthias Apitz, ✉ guru(a)unixarea.de, ⌂ http://www.unixarea.de/ ☎ +49-176-38902045 Public GnuPG key: http://www.unixarea.de/key.pub

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Re: [flashrom] Qflashrom or other GUI
by Richard Hughes Sept. 7, 2017

Sept. 7, 2017

On 7 September 2017 at 12:26, The_Raven Raven <originalraven(a)hotmail.com> wrote: > I have no problems with CLI, but i think a lot of users like to have a GUI. Completely off topic for this list, and feel free to tell me I'm crazy, but for Fedora and RHEL my stock answer is that users should be using fwupd rather than the low level tools like flashrom and dfu-util directly. In the GNOME desktop the Software Center automatically downloads updates and shows them in the GUI for users to apply with just one click, and it would be pretty simple to design a "power-user" GUI around fwupd if you wanted more control over the flashing process or to see what upgrades and downgrades are available for each device. The downside is you have to worry about matching devices to compatible firmwares if you just want to flash a .bin (it's really just one GUID string that has to match) but I think it's so much more powerful and much safer for users. If this is something that sounds interesting to anyone please let me know and I can ask the GNOME UX designers to start thinking about designs. Richard

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Qflashrom or other GUI
by The_Raven Raven Sept. 7, 2017

Sept. 7, 2017

Hi all It is very bad that qflashrom (or any other GUI) was not developed anymore. I have no problems with CLI, but i think a lot of users like to have a GUI. Is it not possible to adapt qflashrom to new versions? Or ship it with stable builds maybe? Greetings

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Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?
by Sandy Zhang Sept. 5, 2017

Sept. 5, 2017

Hi David, I can't paste the log in https://paste.flashrom.org/. it prompts 'Wrong captcha'. The attachment is log file, The fail is same as before. I'm not sure if it's related to ichspi.c num_freg = 12. In our image, we used the last region(No. 15), when reading this region, failed. 2017-09-02 4:47 GMT+08:00 David Hendricks <dhendricks(a)fb.com>: > Hi Sandy, > > I updated the flashrom code to better take into account differences with > Lewisburg, including the number of FREG registers as you point out: > https://review.coreboot.org/#/c/20922/ > > > When you have a chance, please and try again (using -V). You can > copy+paste your result here for convenience: https://paste.flashrom.org/. > Flashrom -- File upload serivce <https://paste.flashrom.org/> > paste.flashrom.org > Welcome to flashrom's file upload service Please post only > flashrom/coreboot/seabios or other firmware related contents. Post a new > paste You can either post text ... > > ------------------------------ > *From:* flashrom <flashrom-bounces(a)flashrom.org> on behalf of Sandy Zhang > <sanzhang(a)celestica.com> > *Sent:* Monday, August 14, 2017 4:36:00 AM > *To:* David Hendricks > *Cc:* flashrom(a)flashrom.org > *Subject:* Re: [flashrom] When flashrom support Intel Purley platform > Lewisburg PCH? > > Hi David, > > Lewisburg PCH defines sixty SPI regions, but from the code in ichspi.c, I > find it defines only 10 regions, is this the reason about only 10 regions > was described in the log file? > > code as below: (num_freg define the spi regions) > > int ich_init_spi(void *spibar, enum ich_chipset ich_gen) > { > ... > ... > ... > /* Moving registers / bits */ > if (ich_generation == CHIPSET_100_SERIES_SUNRISE_POINT) { > num_freg = 10; > num_pr = 6; > reg_pr0 = PCH100_REG_FPR0; > swseq_data.reg_ssfsc = PCH100_REG_SSFSC; > swseq_data.reg_preop = PCH100_REG_PREOP; > swseq_data.reg_optype = PCH100_REG_OPTYPE; > swseq_data.reg_opmenu = PCH100_REG_OPMENU; > hwseq_data.addr_mask = PCH100_FADDR_FLA; > hwseq_data.only_4k = true; > hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE; > } > > 2017-08-14 14:23 GMT+08:00 David Hendricks <david.hendricks(a)gmail.com>: > >> On Sun, Aug 13, 2017 at 6:26 PM, Sandy Zhang <sanzhang(a)celestica.com> >> wrote: >> >>> Hi David, >>> >>> I'm inline. >>> >> >> I don't see your responses. Did you intend to reply to my comments? >> >> >>> >>> 2017-08-14 9:17 GMT+08:00 David Hendricks <david.hendricks(a)gmail.com>: >>> >>>> Hi Sandy, >>>> >>>> Responses in-line. >>>> >>>> On Fri, Aug 11, 2017 at 1:38 AM, Sandy Zhang <sanzhang(a)celestica.com> >>>> wrote: >>>> >>>>> Hi David, >>>>> >>>>> Sorry, I have a doubt about the range outside, from the binary >>>>> map, we can find the Spare 3 Region size is 0x00FFFFFF - 0xFF0000 + 1 = >>>>> 0x10000, and the binary size map to this range is also 0x10000, they are >>>>> equal, why outside was happened? and can you tell me how to update the >>>>> binary region's range defined in the flash description? >>>>> >>>>> Start (hex) End (hex) Length (hex) Area Name >>>>> ----------- --------- ------------ --------- >>>>> ... >>>>> ... >>>>> .... >>>>> 00FF0000 00FFFFFF 00010000 Spare 3 Region >>>>> 01000000 01FFFFFF 01000000 BIOS Region >>>>> >>>> >>>> The Flash Region registers (BIOS_FREGn) define the boundaries of each >>>> region. I don't see where 0xa36000-0xffffff is covered: >>>> 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) >>>> is read-write. >>>> 0x58: 0x1fff1000 FREG1: BIOS region (0x01000000-0x01ffffff) is >>>> read-write. >>>> 0x5C: 0x0a250003 FREG2: Management Engine region >>>> (0x00003000-0x00a25fff) is read-write. >>>> 0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) >>>> is read-write. >>>> 0x64: 0x00007fff FREG4: Platform Data region is unused. >>>> 0x68: 0x0a350a26 FREG5: unknown region (0x00a26000-0x00a35fff) is >>>> read-write. >>>> 0x6C: 0x00007fff FREG6: unknown region is unused. >>>> 0x70: 0x00007fff FREG7: unknown region is unused. >>>> 0x74: 0x00007fff FREG8: unknown region is unused. >>>> 0x78: 0x00007fff FREG9: unknown region is unused. >>>> >>>> You might also need to set permissions for the "BIOS" master (i.e. >>>> flashrom running on the CPU) via BRWA and BRRA in the FRACC register. >>>> >>>> In addition, from flash log file(please see attachment >>>>> "Lewisburg_W25Q256.log"), it shows: >>>>> Found Programmer flash chip "Opaque flash chip" (32768 kB, >>>>> Programmer-specific) mapped at physical address 0x0000000000000000. >>>>> but, my flash chip is "Winbond flash chip", what do you think about >>>>> this? >>>>> >>>> >>>> This is OK. Intel hardware sequencing is an "opaque" programmer >>>> interface since flashrom does not directly send NOR flash commands via a >>>> raw SPI interface. For hardware sequencing we use the FCYCLE field as our >>>> command interface to the SPI flash. >>>> >>>> >>> >>> >>> -- >>> >>> *Best Regard!* >>> >>> *Sandy Zhang (* 张立康*)* >>> *BIOS Engineer* >>> *Global Design Service* >>> *Celestica(Shanghai) R&D Center, China* >>> *Mail: sanzhang(a)celestica.com <viterzho(a)celestica.com>* >>> *Mobile: (+86)15965353952 <+86%20159%206535%203952>* >>> *Phone: (+86)021-61006028-7623* >>> >> >> > > > -- > > *Best Regard!* > > *Sandy Zhang (* 张立康*)* > *BIOS Engineer* > *Global Design Service* > *Celestica(Shanghai) R&D Center, China* > *Mail: sanzhang(a)celestica.com <viterzho(a)celestica.com>* > *Mobile: (+86)15965353952 <+86%20159%206535%203952>* > *Phone: (+86)021-61006028-7623* > -- *Best Regard!* *Sandy Zhang (* 张立康*)* *BIOS Engineer* *Global Design Service* *Celestica(Shanghai) R&D Center, China* *Mail: sanzhang(a)celestica.com <viterzho(a)celestica.com>* *Mobile: (+86)15965353952* *Phone: (+86)021-61006028-7623*

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Erase failure on Sapphire Pure Platinum H61 with coreboot
by Nicola Corna Sept. 5, 2017

Sept. 5, 2017

Hi, I have a Sapphire Pure Platinum H61 with coreboot and flashrom fails to erase the flash chip (corrupting the image); attached you can find the log. Before coreboot's commit d533b16 the internal flashing worked after a fresh start, while after a S3 resume it failed with the same error. Starting from this commit, the internal flashing doesn't work at all. As suggested by Nico Huber, I tried with `-p internal:ich_spi_mode=hwseq`, without success (log attached). The flash chip on this board is socketed, so I can easily reprogram it in case of brick. Thanks for your help, Nicola Corna

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Patch to flashrom for Macronix M25U12835F flash support and write protection bug fix
by alexlu6＠mxic.com.tw Sept. 4, 2017

Sept. 4, 2017

Dear Sir, I am from Macronix (Taiwan), here I send you the source patch that could fix the write protection error on Chromebook project which came form Quatun Computer. I hope you can help patching into the Flashrom project (branch: master). Thanks a lot ! Alex Lu Macronix , FAE Dept. CONFIDENTIALITY NOTE: This e-mail and any attachments may contain confidential information and/or personal data, which is protected by applicable laws. Please be reminded that duplication, disclosure, distribution, or use of this e-mail (and/or its attachments) or any part thereof is prohibited. If you receive this e-mail in error, please notify us immediately and delete this mail as well as its attachment(s) from your system. In addition, please be informed that collection, processing, and/or use of personal data is prohibited unless expressly permitted by personal data protection laws. Thank you for your attention and cooperation. Macronix International Co., Ltd. ===================================================================== CONFIDENTIALITY NOTE: This e-mail and any attachments may contain confidential information and/or personal data, which is protected by applicable laws. Please be reminded that duplication, disclosure, distribution, or use of this e-mail (and/or its attachments) or any part thereof is prohibited. If you receive this e-mail in error, please notify us immediately and delete this mail as well as its attachment(s) from your system. In addition, please be informed that collection, processing, and/or use of personal data is prohibited unless expressly permitted by personal data protection laws. Thank you for your attention and cooperation. Macronix International Co., Ltd. ===================================================================== ============================================================================ CONFIDENTIALITY NOTE: This e-mail and any attachments may contain confidential information and/or personal data, which is protected by applicable laws. Please be reminded that duplication, disclosure, distribution, or use of this e-mail (and/or its attachments) or any part thereof is prohibited. If you receive this e-mail in error, please notify us immediately and delete this mail as well as its attachment(s) from your system. In addition, please be informed that collection, processing, and/or use of personal data is prohibited unless expressly permitted by personal data protection laws. Thank you for your attention and cooperation. Macronix International Co., Ltd. =====================================================================

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Atmel AT25F512B successfully tested with Bus Pirate v3.a (fw 6.1)
by Torben Nielsen Sept. 3, 2017

Sept. 3, 2017

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Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH?
by David Hendricks Sept. 1, 2017

Sept. 1, 2017

Hi Sandy, I updated the flashrom code to better take into account differences with Lewisburg, including the number of FREG registers as you point out: https://review.coreboot.org/#/c/20922/ When you have a chance, please and try again (using -V). You can copy+paste your result here for convenience: https://paste.flashrom.org/. Flashrom -- File upload serivce<https://paste.flashrom.org/> paste.flashrom.org Welcome to flashrom's file upload service Please post only flashrom/coreboot/seabios or other firmware related contents. Post a new paste You can either post text ... ________________________________ From: flashrom <flashrom-bounces(a)flashrom.org> on behalf of Sandy Zhang <sanzhang(a)celestica.com> Sent: Monday, August 14, 2017 4:36:00 AM To: David Hendricks Cc: flashrom(a)flashrom.org Subject: Re: [flashrom] When flashrom support Intel Purley platform Lewisburg PCH? Hi David, Lewisburg PCH defines sixty SPI regions, but from the code in ichspi.c, I find it defines only 10 regions, is this the reason about only 10 regions was described in the log file? code as below: (num_freg define the spi regions) int ich_init_spi(void *spibar, enum ich_chipset ich_gen) { ... ... ... /* Moving registers / bits */ if (ich_generation == CHIPSET_100_SERIES_SUNRISE_POINT) { num_freg = 10; num_pr = 6; reg_pr0 = PCH100_REG_FPR0; swseq_data.reg_ssfsc = PCH100_REG_SSFSC; swseq_data.reg_preop = PCH100_REG_PREOP; swseq_data.reg_optype = PCH100_REG_OPTYPE; swseq_data.reg_opmenu = PCH100_REG_OPMENU; hwseq_data.addr_mask = PCH100_FADDR_FLA; hwseq_data.only_4k = true; hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE; } 2017-08-14 14:23 GMT+08:00 David Hendricks <david.hendricks(a)gmail.com<mailto:david.hendricks@gmail.com>>: On Sun, Aug 13, 2017 at 6:26 PM, Sandy Zhang <sanzhang(a)celestica.com<mailto:sanzhang@celestica.com>> wrote: Hi David, I'm inline. I don't see your responses. Did you intend to reply to my comments? 2017-08-14 9:17 GMT+08:00 David Hendricks <david.hendricks(a)gmail.com<mailto:david.hendricks@gmail.com>>: Hi Sandy, Responses in-line. On Fri, Aug 11, 2017 at 1:38 AM, Sandy Zhang <sanzhang(a)celestica.com<mailto:sanzhang@celestica.com>> wrote: Hi David, Sorry, I have a doubt about the range outside, from the binary map, we can find the Spare 3 Region size is 0x00FFFFFF - 0xFF0000 + 1 = 0x10000, and the binary size map to this range is also 0x10000, they are equal, why outside was happened? and can you tell me how to update the binary region's range defined in the flash description? Start (hex) End (hex) Length (hex) Area Name ----------- --------- ------------ --------- ... ... .... 00FF0000 00FFFFFF 00010000 Spare 3 Region 01000000 01FFFFFF 01000000 BIOS Region The Flash Region registers (BIOS_FREGn) define the boundaries of each region. I don't see where 0xa36000-0xffffff is covered: 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-write. 0x58: 0x1fff1000 FREG1: BIOS region (0x01000000-0x01ffffff) is read-write. 0x5C: 0x0a250003 FREG2: Management Engine region (0x00003000-0x00a25fff) is read-write. 0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write. 0x64: 0x00007fff FREG4: Platform Data region is unused. 0x68: 0x0a350a26 FREG5: unknown region (0x00a26000-0x00a35fff) is read-write. 0x6C: 0x00007fff FREG6: unknown region is unused. 0x70: 0x00007fff FREG7: unknown region is unused. 0x74: 0x00007fff FREG8: unknown region is unused. 0x78: 0x00007fff FREG9: unknown region is unused. You might also need to set permissions for the "BIOS" master (i.e. flashrom running on the CPU) via BRWA and BRRA in the FRACC register. In addition, from flash log file(please see attachment "Lewisburg_W25Q256.log"), it shows: Found Programmer flash chip "Opaque flash chip" (32768 kB, Programmer-specific) mapped at physical address 0x0000000000000000. but, my flash chip is "Winbond flash chip", what do you think about this? This is OK. Intel hardware sequencing is an "opaque" programmer interface since flashrom does not directly send NOR flash commands via a raw SPI interface. For hardware sequencing we use the FCYCLE field as our command interface to the SPI flash. -- Best Regard! Sandy Zhang ( 张立康) BIOS Engineer Global Design Service Celestica(Shanghai) R&D Center, China Mail: sanzhang(a)celestica.com<mailto:viterzho@celestica.com> Mobile: (+86)15965353952<tel:+86%20159%206535%203952> Phone: (+86)021-61006028-7623 -- Best Regard! Sandy Zhang ( 张立康) BIOS Engineer Global Design Service Celestica(Shanghai) R&D Center, China Mail: sanzhang(a)celestica.com<mailto:viterzho@celestica.com> Mobile: (+86)15965353952 Phone: (+86)021-61006028-7623

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