flashrom May 2016

flashrom@flashrom.org

20 participants
23 discussions

Failed coreboot flash on pixel2
by Richard Weerasinghe 24 May '16

24 May '16

Here is the output: chronos@localhost /tmp $ sudo flashrom -w coreboot-seabios-samus-20160324-coolstar.rom flashrom v0.9.4 : df00e76 : Mar 22 2016 19:53:33 UTC on Linux 3.14.0 (x86_64), built with libpci 3.1.10, GCC 4.9.x-google 20150123 (prerelease), little endian Erasing and writing flash chip... Transaction error! spi_block_erase_20 failed during command execution at address 0x3e0000 ERASE FAILED! Reading current flash chip contents... spi_block_erase_52 failed during command execution at address 0x3e0000 ERASE FAILED! Reading current flash chip contents... Transaction error! spi_block_erase_d8 failed during command execution at address 0x3e0000 ERASE FAILED! Reading current flash chip contents... spi_chip_erase_60 failed during command execution ERASE FAILED! Reading current flash chip contents... spi_chip_erase_c7 failed during command execution ERASE FAILED! FAILED! Uh oh. Erase/write failed. Checking if anything changed. Good. It seems nothing was changed. Writing to the flash chip apparently didn't do anything. This means we have to add special support for your board, programmer or flash chip. Please report this on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- You may now reboot or simply leave the machine running. FAILED If you need more info, please let me know. cheers Richard ᐧ

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ft2232_spi JTAGkey OE disabled for CS high
by Ulrich Holeschak 20 May '16

20 May '16

Hello, when using the ft2232_spi driver with Amontec JTAGkey, the OE signal (bit 4) is disabled when de-asserting CS: msg_pspew("De-assert CS#\n"); buf[i++] = SET_BITS_LOW; buf[i++] = cs_bits; buf[i++] = pindir; This means that the CS high signal is floating and the voltage level is unstable. Filtering the OE bit fixes this issue: msg_pspew("De-assert CS#\n"); buf[i++] = SET_BITS_LOW; buf[i++] = cs_bits & 0x0F; // keep OE active buf[i++] = pindir; Regards, Ulrich

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T420 internal flashing: Transactions Error
by Arian Sanusi 18 May '16

18 May '16

Hi All, I'm trying to re-flash coreboot on a T420 that already runs coreboot - the same image that's currently flashed actually. According to coreboot wiki, that should be possible. [1] I think I enabled write-lock of the ME region in coreboot, but I can't find the option, nor the .config line anymore. flashrom: flashrom v0.9.9-r1954 on Linux 4.3.0-1-amd64 (x86_64) coreboot: * master 831d65d intel/apollolake: Fix logic error Can anyone help? Thank you Arian Attached: flashrom output, coreboot .config

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Results for board: MSI MS-7528 G31M3(-F)
by callmeclean 16 May '16

16 May '16

I've successfully read from & written updated BIOS to this motherboard, both verified. The modelling is a bit confusing, there are a few revisions of the board. I can't say for certain, but it seems G31M3 and G31M3-F are the same board. BIOS images from G31M3-F product page work on my board missing the -F (which I can't find any official mention of). Attached are the output of flashrom -p internal -V, lspci -nnvvxxx and superiotool -deV in results1.txt, results2.txt and results3.txt respectively. Please tell me if attachments are not acceptable and I will reply with the full text (the outputs are very long!).

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Re: [flashrom] ENE KB9012 Programming with flashrom
by Joerg Albert 16 May '16

16 May '16

On 01.05.2016 10:37, Paul Kocialkowski wrote: > Hi, > > could you CC the flashrom mailing list in your future responses? This will > probably interest others! I wasn't aware of this mailing lists, thanks! > Le dimanche 24 avril 2016 à 23:15 +0200, Joerg Albert a écrit : >> I'll try to program the internal SPI of a KB9012 (inside a Thinkpad S531) - as >> soon as I've found the correct image and soldered the necessary wires. > The KB9012 chips has an internal flash memory that is distinct from the BIOS' > SPI flash, so beware not to confuse both! I'm aware of this. The S531 manual says, that the system indicator LED shall flash three times when the power supply gets connected (without switching the notebook on). As I don't see this and the voltage at the KB9012 is correct I guess that the EC is not working properly. Flashing the BIOS SPI may be the second step ;-) >> Found your patch here: >> >> http://patchwork.coreboot.org/patch/4325/ >> >> Why couldn't I use FlashDirectAccess? Is this meant to program external SPI >> flash only? > Yes, that's my understanding of it too. It just makes a bridge between the BIOS' > SPI flash and the KB9012 pads. This is because it's often easier to reflash it > using the keyboard connector, that is often available without fully opening the > device. > > What you want if you need to reflash the EC is not FlashDirectAccess, but EDI. > Note that some firmwares explicitly disable it, so you have to ground pin 42 to > enter "test mode", where the 8051 is not running. > > Note that the EDI pins are often exported on the keyboard connector, which makes > soldering more doable. > The keyboard connector of the S531 has a pitch of 0.5mm, too close for my soldering experience. I couldn't find a flex cable matching the connector either, so I went for soldering wires to some vias/testpoints instead. Connected a RaspberryPi and had some problems with the detection of the KB9012. It seemed to detect the KB9012 on every second trial only: -------------- pi@raspberrypi ~ $ flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=1024 -c "KB9012 (EDI)" -V flashrom v0.9.9-r1954 on Linux 3.18.11+ (armv6l) flashrom is free software, get the source code at https://flashrom.org flashrom was built with libpci 3.1.9, GCC 4.6.3, little endian Command line (5 args): flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=1024 -c KB9012 (EDI) -V Calibrating delay loop... OS timer resolution is 5 usecs, 229M loops per second, 10 myus = 11 us, 100 myus = 103 us, 1000 myus = 994 us, 10000 myus = 10064 us, 20 myus = 26 us, OK. Initializing linux_spi programmer Using device /dev/spidev0.0 Using 1024 kHz clock The following protocols are supported: SPI. Probing for ENE KB9012 (EDI), 128 kB: probing for EDI EDI: found hw version 195 EDI id 4 Found ENE flash chip "KB9012 (EDI)" (128 kB, SPI) on linux_spi. No operations were specified. pi@raspberrypi ~ $ flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=1024 -c "KB9012 (EDI)" -V flashrom v0.9.9-r1954 on Linux 3.18.11+ (armv6l) flashrom is free software, get the source code at https://flashrom.org flashrom was built with libpci 3.1.9, GCC 4.6.3, little endian Command line (5 args): flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=1024 -c KB9012 (EDI) -V Calibrating delay loop... OS timer resolution is 4 usecs, 226M loops per second, 10 myus = 11 us, 100 myus = 102 us, 1000 myus = 1839 us, 10000 myus = 10424 us, 16 myus = 21 us, OK. Initializing linux_spi programmer Using device /dev/spidev0.0 Using 1024 kHz clock The following protocols are supported: SPI. Probing for ENE KB9012 (EDI), 128 kB: probing for EDI EDI: failed to read hw version (-1) No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. pi@raspberrypi ~ $ flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=1024 -c "KB9012 (EDI)" -V flashrom v0.9.9-r1954 on Linux 3.18.11+ (armv6l) flashrom is free software, get the source code at https://flashrom.org flashrom was built with libpci 3.1.9, GCC 4.6.3, little endian Command line (5 args): flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=1024 -c KB9012 (EDI) -V Calibrating delay loop... OS timer resolution is 5 usecs, 229M loops per second, 10 myus = 11 us, 100 myus = 102 us, 1000 myus = 994 us, 10000 myus = 10061 us, 20 myus = 22 us, OK. Initializing linux_spi programmer Using device /dev/spidev0.0 Using 1024 kHz clock The following protocols are supported: SPI. Probing for ENE KB9012 (EDI), 128 kB: probing for EDI EDI: found hw version 195 EDI id 4 Found ENE flash chip "KB9012 (EDI)" (128 kB, SPI) on linux_spi. No operations were specified. -------- I've also tried with "speed=2048" (as the KB9012 manual states a minimum clock of 1MHz) - same problem. / /I've added some error/debug printouts and it seems like the KB9012 answers with all-zeros on each second start of the probe. If the buffer content is correct everything else afterwards works fine. So I've added a quick workaround in edi_read_byte() and edi_read() to re-do any read if the buffer contains zero at the first byte. See the patches attached. No idea why it behaves that way, maybe the SPI detection on these pins is a bit shaky? Pin 42 was grounded and the KB9012 remained powered during the whole session. Cheers, Joerg

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BIOS image write and safety
by Nicolas Clerc 13 May '16

13 May '16

Hi guys, I need for a specific project to change BIOS Settings on many computers. So far, I used flashrom to read out the flash memory of my BIOS. Flashrom successfully detects the Winbond W25Q32.V flash, and I can dump the whole 32Mbits. With your experience, do you know if it is *generally* quite safe to write an image that has been dumped (both using flashrom ofc) ? I have been doing several memory dumps of this BIOS flash, each one separated by a reboot, and can see a modification between each dump. I suspect there's a kind of event log or journal that is kept by the BIOS, but I can't find a way to read it (neither BIOS menu nor external software). The BIOS is from AMI. Any advice is welcome, Cheers Nicolas

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SST26VF032B support
by Peter Hall 10 May '16

10 May '16

Hi, I got the flashrom working on a BeagleBone programming a SST26VF032B with some modifications to 0.9.9. Do you want me to upload the modifications? I mostly copied the changes from another post, but I can't remember where that was from and I made some tweaks myself. These changes definitely work, I've test this multiple times on multiple boards. Let me know if you want the source Regards Peter Hall Software Development Manager Raster Vision Ltd. Tel: 01892 722228 / +44 1892 722228. www.rvl.co.uk <http://www.rvl.co.uk/> Raster Vision Ltd is a company registered in England and Wales, number: 02753356. Registered office: Unit 1, Crundalls, Gedges Hill, Matfield, Tonbridge, Kent, TN12 7EA, UK. C2- Restricted

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Re: [flashrom] New SPI NOR Flash product Support
by Victor Lim 10 May '16

10 May '16

Thanks, David, For Gigadevice part numbers, we do keep ID, read, erase, write opcodes, sector protection, and architecture the same. I am wondering if Flashrom program needs to call out the new part numbers so that users know which part number to choose from. Regards, Victor From: David Hendricks [mailto:dhendrix@google.com] Sent: Sunday, May 8, 2016 7:43 PM To: Victor Lim <vlim(a)gigadevice.com> Cc: Hatim Kanchwala <hatim(a)hatimak.me>; flashrom <flashrom(a)flashrom.org>; Katherine (GigaDevice//US) <ksong(a)gigadevice.com> Subject: Re: [flashrom] New SPI NOR Flash product Support Hello Victor, Chips with same ID and read, erase, and write opcodes are supported. For ChromeOS platforms it is also important that new revision chips have identical block protection capabilities as the older parts (I've had difficulties with other vendors regarding this...). On Fri, May 6, 2016 at 4:55 PM, Victor Lim <vlim(a)gigadevice.com <mailto:vlim@gigadevice.com> > wrote: Hi, Hatim, We have new revision chips that share the same ID as the previous revision, will they be considered supported because they share the same basic Erase and program command. New part # GD25LQ64C: manufacturer ID: 0x6017 Currently supported part # GD25LQ64: manufacturer ID: 0x6017 New part # GD25LQ128C: manufacturer ID: 0x6018 Currently supported part # GD25LQ128: manufacturer ID: 0x6018 Do you need new samples for verification? We do keep the same ID for new revision release, so the SW should work for new revision parts. Regards, Victor -----Original Message----- From: Hatim Kanchwala [mailto:hatim@hatimak.me <mailto:hatim@hatimak.me> ] Sent: Friday, March 25, 2016 1:27 PM To: Victor Lim <vlim(a)gigadevice.com <mailto:vlim@gigadevice.com> > Cc: flashrom(a)flashrom.org <mailto:flashrom@flashrom.org> ; ksong(a)gigadevice.com <mailto:ksong@gigadevice.com> Subject: Re: [flashrom] New SPI NOR Flash product Support Hello Victor, I am doing fine, thanks :) The following chips have been tested successfully - GD25D05B/10B, GD25LQ10B/20B/40B/80B, GD25Q21B/41B and GD25VQ41B (reported by David Hendrix). Test logs for the first 8 of these chips can be found here - https://www.flashrom.org/pipermail/flashrom/2016-March/014537.html. The patches for all these chips and additionally GD25Q80C/16C have been sent and are waiting for further review. I have ordered some IC clips, so I will test the remaining chips as soon as those arrive. Unfortunately, one of the chips you explicitly requested support for, GD25Q128C was not included in the samples so was not tested. But support for it has already been added ;) Apologies for the late reply. :) On Tuesday 22 March 2016 01:20 AM, Victor Lim wrote: > Hi, Hatim, > > How are you doing? Hope all the sample test results are good. > Can you please update the status so that I can ask customer to try out. > > Regards, > > Victor > > > > -----Original Message----- > From: Hatim Kanchwala [mailto:hatim@hatimak.me <mailto:hatim@hatimak.me> ] > Sent: Wednesday, February 24, 2016 9:02 AM > To: Victor Lim <vlim(a)gigadevice.com <mailto:vlim@gigadevice.com> > > Cc: flashrom(a)flashrom.org <mailto:flashrom@flashrom.org> ; ksong(a)gigadevice.com <mailto:ksong@gigadevice.com> > Subject: Re: [flashrom] New SPI NOR Flash product Support > > Hello Victor, > > Support for two chips you requested was added some time ago in r1937 > (look here https://tracker.coreboot.org/trac/flashrom/changeset/1937). > I am waiting for samples to perform tests. FedEx was in touch > regarding documents for customs clearance, so delivery should be in a > day or two. In the meanwhile I am working on support for other > GigaDevice chips (http://www.gigadevice.com/product-series/12.html). > > On Wednesday 24 February 2016 04:47 AM, Victor Lim wrote: >> Hi, Hatim, >> >> How is the new program to include these two part #? >> I have sent the samples to you, but they are held up at the Fedex >> facility at New Delhi. >> Can you please give Fedex the instruction for delivery? >> The tracking # is 806824856677 >> >> Regards, >> >> Victor >> >> >> >> >> -----Original Message----- >> From: Victor Lim [mailto:vlim@gigadevice.com <mailto:vlim@gigadevice.com> ] >> Sent: Tuesday, February 9, 2016 3:02 PM >> To: 'Hatim Kanchwala' <hatim(a)hatimak.me <mailto:hatim@hatimak.me> > >> Cc: 'flashrom(a)flashrom.org <mailto:flashrom@flashrom.org> ' <flashrom(a)flashrom.org <mailto:flashrom@flashrom.org> > >> Subject: RE: [flashrom] New SPI NOR Flash product Support >> >> Thanks, Hatim, >> >> Please help me on these two part #s, datasheets are attached. >> 1) GD25VQ41B >> 2) GD25Q128C >> >> Can you provide the ship to address, I will send you same samples. >> What package type do you prefer? >> >> Regards, >> >> Victor >> >> >> >> -----Original Message----- >> From: Hatim Kanchwala [mailto:hatim@hatimak.me <mailto:hatim@hatimak.me> ] >> Sent: Tuesday, February 9, 2016 12:27 PM >> To: Victor Lim <vlim(a)gigadevice.com <mailto:vlim@gigadevice.com> > >> Cc: flashrom(a)flashrom.org <mailto:flashrom@flashrom.org> >> Subject: Re: [flashrom] New SPI NOR Flash product Support >> >> Hello Victor, >> >> I have recently started looking at flashrom and have contributed by >> adding a few SPI flashchip definitions. I would be glad to add >> support for the SPI chips. Usually datasheets are sufficient for >> adding flashchip support (as long as datasheets convey full >> information on functionality). However, the chips remain untested. I >> would be glad to test them as well if you are willing to provide >> samples (I am at a University, so I have access to a lab with equipment for testing). >> >> On Wednesday 10 February 2016 12:18 AM, Victor Lim wrote: >>> Hi, Flashrom team, >>> >>> >>> >>> I am the FAE manager for Gigadevice and would like to know how I can >>> work >> with you to add our part # to your support list. >>> >>> A customer of mine is looking to program our GD25VQ41B with your >>> tool and >> found that it is not supported by your tools. >>> >>> It would like grateful if you can support our entire SPI NOR portfolio. >>> >>> >>> >>> Regards, >>> >>> >>> >>> Victor Lim(Gigadevice/MK IV/FAE Manager) >>> >>> >>> >>> Gigadevice Semiconductor Inc. >>> >>> Tel: 408-855-8336 <tel:408-855-8336> >>> Mobile: 408-883-3856 <tel:408-883-3856> >>> >>> Website: www.gigadevice.com <http://www.gigadevice.com> <http://www.gigadevice.com/> >>> >>> 2975 Bowers Ave,Suite 323 >>> >>> Santa Clara, CA 95051, USA >>> >>> >>> >>> This email was sent to you by GigaDevice, A Global Innovative Memory >> Architect >>> >>> >> --------------------------------------------------------------------- >> - >> ------ >> --------------------------------------------------------------------- >> - >> ------ >> --------------------------------------------------------------------- >> - >> ------ >> --------------------------------------------------------------------- >> - >> ------ >> --------------------------------------------------------------------- >> - >> ------ >> --------------------------------------------------------------------- >> - >> ------ >> --------------------------------------------------------------------- >> - >> ------ >> --------------------------------------------------------------------- >> - >> ------ >> --------------------------------------------------------------------- >> - >> ------ >> --------------------------------------------------------------------- >> - >> ------ >> --------------------------------------------------------------------- >> - >> ------ >> --------------------------------------------------------------------- >> - >> ------ >> --------------------------------------------------------------------- >> - >> ------ >> -- >>> >>> The information contained in this e-mail message (and any attachment >> transmitted herewith) is privileged and confidential and is intended >> for the exclusive use of the addressee(s). If you are not an intended >> addressee, any disclosure, reproduction, distribution or other >> dissemination or use of this communication is strictly prohibited. If >> you have received this communication in error, please delete this >> communication and contact us by replying to this e-mail immediately. >>> >>> >>> >>> >>> >>> _______________________________________________ >>> flashrom mailing list >>> flashrom(a)flashrom.org <mailto:flashrom@flashrom.org> >>> http://www.flashrom.org/mailman/listinfo/flashrom >>> >> > > -- > Kind Regards, > Hatim Kanchwala > http://hatimak.me > B. Tech. Electrical Engineering > Indian Institute of Technology Patna > > -- Kind Regards, Hatim Kanchwala http://hatimak.me B. Tech. Electrical Engineering Indian Institute of Technology Patna _______________________________________________ flashrom mailing list flashrom(a)flashrom.org <mailto:flashrom@flashrom.org> https://www.flashrom.org/mailman/listinfo/flashrom -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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New SPI NOR Flash product Support
by Victor Lim 09 May '16

09 May '16

Hi, Flashrom team, I am the FAE manager for Gigadevice and would like to know how I can work with you to add our part # to your support list. A customer of mine is looking to program our GD25VQ41B with your tool and found that it is not supported by your tools. It would like grateful if you can support our entire SPI NOR portfolio. Regards, Victor Lim(Gigadevice/MK IV/FAE Manager) Gigadevice Semiconductor Inc. Tel: 408-855-8336 Mobile: 408-883-3856 Website: <http://www.gigadevice.com/> www.gigadevice.com 2975 Bowers Ave,Suite 323 Santa Clara, CA 95051, USA This email was sent to you by GigaDevice, A Global Innovative Memory Architect _____ The information contained in this e-mail message (and any attachment transmitted herewith) is privileged and confidential and is intended for the exclusive use of the addressee(s). If you are not an intended addressee, any disclosure, reproduction, distribution or other dissemination or use of this communication is strictly prohibited. If you have received this communication in error, please delete this communication and contact us by replying to this e-mail immediately.

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Support
by Pera Peric 08 May '16

08 May '16

As instructed, I'm sending an email with verbose parameter included. The chip in question is w25q64fvsig. Also, please advise if something can be done about flashing with the descriptor locked (other than using an external programmer). Best

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