flashrom December 2016

flashrom@flashrom.org

23 participants
27 discussions

Re: [flashrom] New SPI NOR Flash product Support
by Stefan Tauner 15 Aug '19

15 Aug '19

On Mon, 9 May 2016 20:46:18 -0700 David Hendricks <dhendrix(a)google.com> wrote: > Hi Victor, > From Flashrom's software perspective all chips with the same ID are > indistinguishable. > > Part number often includes characteristics such as package and thermal > tolerance which do not affect software compatibility. However, we will add the new names to the in-program (and hence wiki) database so that this new information becomes public. Thanks for the heads up, Victor. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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80/100/132 column line width policy
by Carl-Daniel Hailfinger 14 Dec '18

14 Dec '18

Hi, we're hitting the 80 column limit in our code in ways which actually reduce readability for the code. Examples are various multiline messages and complicated nested code where refactoring to a separate function doesn't make sense. Keeping the old 80 column limit is not really an option anymore. Standard terminal sizes have one of 80, 100 or 132 columns. Given the monitor resolutions many people have nowadays, I think it is safe to say that you can fit two xterms with 100 columns horizonally next to each other. 100 columns should also be sufficient for a msg_p* of roughly 80 columns of text. 132 columns provide more leeway, but IMHO that would be too wide for good readability (and my screen can't fit two xterms side-by-side anymore). Of course some files have sections where any column limit is not acceptable (board lists etc.), but the column limit violations should be limited to the affected file sections, not whole files. Comments? I'd like to get this decided today or tomorrow so we know where we need line breaks in Stefan Tauner's new struct flashchip patch. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[PATCH] Fix undefined behavior in OS defines
by Stefan Tauner 11 Oct '17

11 Oct '17

Found by clang (warning introduced in r258128), reported by Idwer. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- platform.h | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/platform.h b/platform.h index c5a52ef..b58c303 100644 --- a/platform.h +++ b/platform.h @@ -24,10 +24,24 @@ #ifndef __PLATFORM_H__ #define __PLATFORM_H__ 1 -// Helper defines for operating systems -#define IS_LINUX (defined(__gnu_linux__) || defined(__linux__)) -#define IS_MACOSX (defined(__APPLE__) && defined(__MACH__)) /* yes, both. */ -#define IS_WINDOWS (defined(_WIN32) || defined(_WIN64) || defined(__WIN32__) || defined(__WINDOWS__)) +/* Helper defines for operating systems. + * This may seem complicated but the following would be undefined behavior: + * #define IS_LINUX (defined(__gnu_linux__) || defined(__linux__)) */ +#if defined(__gnu_linux__) || defined(__linux__) + #define IS_LINUX (1) +#else + #define IS_LINUX (0) +#endif +#if defined(__APPLE__) && defined(__MACH__) /* yes, both. */ + #define IS_MACOSX (1) +#else + #define IS_MACOSX (0) +#endif +#if defined(_WIN32) || defined(_WIN64) || defined(__WIN32__) || defined(__WINDOWS__) + #define IS_WINDOWS (1) +#else + #define IS_WINDOWS (0) +#endif // Likewise for target architectures #if defined (__i386__) || defined (__x86_64__) || defined(__amd64__) -- Kind regards, Stefan Tauner

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Spansion S25FL128P......X
by The Raven 24 Apr '17

24 Apr '17

I have a spansion S25FL128P......X chip and can do some tests. The "problem" is that i don't know if its an 0 or an 1. On the chip i see only "FL128PIF" and one line lower i see "00299012 C". Probing works (id1 0x01, id2 0x2018): Calibrating delay loop... OK. serprog: Programmer name is "serprog-duino" Found Spansion flash chip "S25FL128P......0" (16384 kB, SPI) on serprog. Found Spansion flash chip "S25FL128P......1" (16384 kB, SPI) on serprog. Found Spansion flash chip "S25FL128S......0" (16384 kB, SPI) on serprog. Found Spansion flash chip "S25FL128S......1" (16384 kB, SPI) on serprog. Found Spansion flash chip "S25FL129P......0" (16384 kB, SPI) on serprog. Found Spansion flash chip "S25FL129P......1" (16384 kB, SPI) on serprog. Multiple flash chip definitions match the detected chip(s): "S25FL128P......0", "S25FL128P......1", "S25FL128S......0", "S25FL128S......1", "S25FL129P......0", "S25FL129P......1" Please specify which chip definition to use with the -c <chipname> option. BTW: Chip was fund on a Dell-Systemboard.

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Verifying flash... FAILED
by Joe Lee 25 Dec '16

25 Dec '16

I flashed a ThinkPad T500 and got this message. > Verifying flash... FAILED at 0x0004c001! Expected=0x3e, Found=0xc7, failed byte count from 0x00000000-0x007fffff: 0x6 > Your flash chip is in an unknown state. Cheers!

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Re: [flashrom] FAILED: GA-B75M-D3V
by Nico Huber 24 Dec '16

24 Dec '16

On 23.12.2016 08:19, David Hendricks wrote: > Looks like it failed to overwrite the descriptor region (Intel ME-related > headache): https://www.flashrom.org/ME According to the log, the descriptor is writeable. Also the error occurs right behind it. When I looked through it first, I thought there might be a board speci- fic write-protection. But now that David pointed me to the 0x1000 here: >> 0x000000-0x00ffff:EFAILED at 0x00001000! Expected=0xff, Found=0x20, I think you just selected the wrong chip. MX25L6405 uses a 64KiB erase- block size by default, but only 4KiB (i.e. everything before 0x1000) got erased. So it's likely one of the other chips flashrom proposed (it can't know by itself, since the chip vendors reuse their IDs...). MX25L6405D seems to be a good choice if you don't know for sure which chip you have. It uses a subset of the functions the other chips use. Hope that helps, Nico > > You can target regions more carefully using a layout file. It appears the > other regions (ME, BIOS, GbE) are unlocked, so you can try creating a > layout that includes only those regions. > > On Mon, Dec 19, 2016 at 7:54 PM, Shawn <citypw(a)gmail.com> wrote: > >> Hi flashrom maintainers, >> >> I failed to write a modified ROM to the flash via internal. Maybe this >> chipset can only be writable via external programmer? >> >> root@sysresccd /root % flashrom -p internal >> flashrom v0.9.8-r1888 on Linux 4.4.28-std490-amd64 (x86_64) >> flashrom is free software, get the source code at http://www.flashrom.org >> >> Calibrating delay loop... OK. >> Found chipset "Intel B75". >> Enabling flash write... Warning: SPI Configuration Lockdown activated. >> OK. >> Found Macronix flash chip "MX25L6405" (8192 kB, SPI) mapped at >> physical address 0xff800000. >> Found Macronix flash chip "MX25L6405D" (8192 kB, SPI) mapped at >> physical address 0xff800000. >> Found Macronix flash chip "MX25L6406E/MX25L6408E" (8192 kB, SPI) >> mapped at physical address 0xff800000. >> Found Macronix flash chip >> "MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E" (8192 kB, SPI) mapped at >> physical address 0xff800000. >> Multiple flash chip definitions match the detected chip(s): >> "MX25L6405", "MX25L6405D", "MX25L6406E/MX25L6408E", >> "MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E" >> Please specify which chip definition to use with the -c <chipname> option. >> >> >> root@sysresccd /root % flashrom -VV -p internal -c MX25L6405 -w >> factory_giga1.bin.new.new >> flashrom v0.9.8-r1888 on Linux 4.4.28-std490-amd64 (x86_64) >> flashrom is free software, get the source code at http://www.flashrom.org >> >> flashrom was built with libpci 3.4.1, GCC 4.8.5, little endian >> Command line (7 args): flashrom -VV -p internal -c MX25L6405 -w >> factory_giga1.bin.new.new >> Calibrating delay loop... OS timer resolution is 1 usecs, 1944M loops >> per second, 10 myus = 10 us, 100 myus = 117 us, 1000 myus = 1021 us, >> 10000 myus = 10021 us, 4 myus = 4 us, OK. >> Initializing internal programmer >> No coreboot table found. >> Using Internal DMI decoder. >> DMI string chassis-type: "Desktop" >> DMI string system-manufacturer: "Gigabyte Technology Co., Ltd." >> DMI string system-product-name: "To be filled by O.E.M." >> DMI string system-version: "To be filled by O.E.M." >> DMI string baseboard-manufacturer: "Gigabyte Technology Co., Ltd." >> DMI string baseboard-product-name: "B75M-D3V" >> DMI string baseboard-version: "To be filled by O.E.M." >> Found ITE Super I/O, ID 0x8728 on port 0x2e >> Found chipset "Intel B75" with PCI ID 8086:1e49. >> Enabling flash write... Root Complex Register Block address = 0xfed1c000 >> GCS = 0xc64: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x3 >> (SPI) >> Top Swap: enabled (A16(+) inverted) >> 0xfff80000/0xffb80000 FWH IDSEL: 0x0 >> 0xfff00000/0xffb00000 FWH IDSEL: 0x0 >> 0xffe80000/0xffa80000 FWH IDSEL: 0x1 >> 0xffe00000/0xffa00000 FWH IDSEL: 0x1 >> 0xffd80000/0xff980000 FWH IDSEL: 0x2 >> 0xffd00000/0xff900000 FWH IDSEL: 0x2 >> 0xffc80000/0xff880000 FWH IDSEL: 0x3 >> 0xffc00000/0xff800000 FWH IDSEL: 0x3 >> 0xff700000/0xff300000 FWH IDSEL: 0x4 >> 0xff600000/0xff200000 FWH IDSEL: 0x5 >> 0xff500000/0xff100000 FWH IDSEL: 0x6 >> 0xff400000/0xff000000 FWH IDSEL: 0x7 >> 0xfff80000/0xffb80000 FWH decode enabled >> 0xfff00000/0xffb00000 FWH decode enabled >> 0xffe80000/0xffa80000 FWH decode enabled >> 0xffe00000/0xffa00000 FWH decode enabled >> 0xffd80000/0xff980000 FWH decode enabled >> 0xffd00000/0xff900000 FWH decode enabled >> 0xffc80000/0xff880000 FWH decode enabled >> 0xffc00000/0xff800000 FWH decode enabled >> 0xff700000/0xff300000 FWH decode enabled >> 0xff600000/0xff200000 FWH decode enabled >> 0xff500000/0xff100000 FWH decode enabled >> 0xff400000/0xff000000 FWH decode enabled >> Maximum FWH chip size: 0x100000 bytes >> SPI Read Configuration: prefetching enabled, caching enabled, >> BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled >> SPIBAR = 0xf7795000 + 0x3800 >> 0x04: 0xe008 (HSFS) >> HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 >> Warning: SPI Configuration Lockdown activated. >> Reading OPCODES... done >> OP Type Pre-OP >> op[0]: 0x02, write w/ addr, none >> op[1]: 0x03, read w/ addr, none >> op[2]: 0x20, write w/ addr, none >> op[3]: 0x05, read w/o addr, none >> op[4]: 0x9f, read w/o addr, none >> op[5]: 0x01, write w/o addr, none >> op[6]: 0x00, read w/o addr, none >> op[7]: 0x00, read w/o addr, none >> Pre-OP 0: 0x06, Pre-OP 1: 0x00 >> 0x06: 0x0000 (HSFC) >> HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 >> 0x08: 0x00000000 (FADDR) >> 0x50: 0x0000ffff (FRAP) >> BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff >> 0x54: 0x00000000 FREG0: Flash Descriptor region >> (0x00000000-0x00000fff) is read-write. >> 0x58: 0x07ff0000 FREG1: BIOS region (0x00000000-0x007fffff) is read-write. >> 0x5C: 0x04ff0001 FREG2: Management Engine region >> (0x00001000-0x004fffff) is read-write. >> 0x60: 0x00001fff FREG3: Gigabit Ethernet region is unused. >> 0x64: 0x00001fff FREG4: Platform Data region is unused. >> 0x74: 0x00000000 (PR0 is unused) >> 0x78: 0x00000000 (PR1 is unused) >> 0x7C: 0x00000000 (PR2 is unused) >> 0x80: 0x00000000 (PR3 is unused) >> 0x84: 0x00000000 (PR4 is unused) >> 0x90: 0x84 (SSFS) >> SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 >> 0x91: 0xf94240 (SSFC) >> SSFC: SCGO=0, ACS=0, SPOP=0, COP=4, DBC=2, SME=0, SCF=1 >> 0x94: 0x0006 (PREOP) >> 0x96: 0x043b (OPTYPE) >> 0x98: 0x05200302 (OPMENU) >> 0x9C: 0x0000019f (OPMENU+4) >> 0xA0: 0x00000000 (BBAR) >> 0xC4: 0x00802005 (LVSCC) >> LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 >> 0xC8: 0x00002005 (UVSCC) >> UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20 >> 0xD0: 0x00000000 (FPB) >> Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. >> === Content Section === >> FLVALSIG 0x0ff0a55a >> FLMAP0 0x02040003 >> FLMAP1 0x12100206 >> FLMAP2 0x00210120 >> >> --- Details --- >> NR (Number of Regions): 3 >> FRBA (Flash Region Base Address): 0x040 >> NC (Number of Components): 1 >> FCBA (Flash Component Base Address): 0x030 >> ISL (ICH/PCH Strap Length): 18 >> FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100 >> NM (Number of Masters): 3 >> FMBA (Flash Master Base Address): 0x060 >> MSL/PSL (MCH/PROC Strap Length): 1 >> FMSBA (Flash MCH/PROC Strap Base Address): 0x200 >> >> === Component Section === >> FLCOMP 0x09300024 >> FLILL 0x00000000 >> >> --- Details --- >> Component 1 density: 8 MB >> Component 2 is not used. >> Read Clock Frequency: 20 MHz >> Read ID and Status Clock Freq.: 33 MHz >> Write and Erase Clock Freq.: 33 MHz >> Fast Read is supported. >> Fast Read Clock Frequency: 33 MHz >> Dual Output Fast Read Support: enabled >> No forbidden opcodes. >> >> === Region Section === >> FLREG0 0x00000000 >> FLREG1 0x07ff0000 >> FLREG2 0x04ff0001 >> FLREG3 0x00001fff >> FLREG4 0x00001fff >> >> --- Details --- >> Region 0 (Descr.) 0x00000000 - 0x00000fff >> Region 1 (BIOS ) 0x00000000 - 0x007fffff >> Region 2 (ME ) 0x00001000 - 0x004fffff >> Region 3 (GbE ) is unused. >> Region 4 (Platf.) is unused. >> >> === Master Section === >> FLMSTR1 0xffff0000 >> FLMSTR2 0xffff0000 >> FLMSTR3 0xffff0118 >> >> --- Details --- >> Descr. BIOS ME GbE Platf. >> BIOS rw rw rw rw rw >> ME rw rw rw rw rw >> GbE rw rw rw rw rw >> >> OK. >> No IT87* serial flash segment enabled. >> The following protocols are supported: FWH, SPI. >> Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 >> 0xc2, id2 0x2017 >> Found Macronix flash chip "MX25L6405" (8192 kB, SPI) mapped at >> physical address 0xff800000. >> Chip status register is 0x00. >> Chip status register: Status Register Write Disable (SRWD, SRP, ...) is >> not set >> Chip status register: Bit 6 is not set >> Chip status register: Block Protect 3 (BP3) is not set >> Chip status register: Block Protect 2 (BP2) is not set >> Chip status register: Block Protect 1 (BP1) is not set >> Chip status register: Block Protect 0 (BP0) is not set >> Chip status register: Write Enable Latch (WEL) is not set >> Chip status register: Write In Progress (WIP/BUSY) is not set >> Block protection is disabled. >> Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. >> Reading old flash chip contents... done. >> Erasing and writing flash chip... Trying erase function 0... >> 0x000000-0x00ffff:EFAILED at 0x00001000! Expected=0xff, Found=0x20, >> failed byte count from 0x00000000-0x0000ffff: 0xb55d >> ERASE FAILED! >> Reading current flash chip contents... done. Looking for another erase >> function. >> Trying erase function 1... 0x000000-0x00ffff:EInvalid OPCODE 0x06, >> will not execute. >> spi_block_erase_d8 failed during command execution at address 0x0 >> Reading current flash chip contents... done. Looking for another erase >> function. >> Trying erase function 2... 0x000000-0x7fffff:EInvalid OPCODE 0x06, >> will not execute. >> spi_chip_erase_60 failed during command execution >> Reading current flash chip contents... done. Looking for another erase >> function. >> Trying erase function 3... 0x000000-0x7fffff:EInvalid OPCODE 0x06, >> will not execute. >> spi_chip_erase_c7 failed during command execution >> Looking for another erase function. >> No usable erase functions left. >> FAILED! >> Uh oh. Erase/write failed. Checking if anything has changed. >> Reading current flash chip contents... done. >> Apparently at least some data has changed. >> Your flash chip is in an unknown state. >> Get help on IRC at chat.freenode.net (channel #flashrom) or >> mail flashrom(a)flashrom.org with the subject "FAILED: <your board name>"! >> ------------------------------------------------------------ >> ------------------- >> DO NOT REBOOT OR POWEROFF! >> Restoring MMIO space at 0xf77988a0 >> Restoring PCI config space for 00:1f:0 reg 0xdc >> >> >> -- >> GNU powered it... >> GPL protect it... >> God blessing it... >> >> regards >> Shawn >> >> _______________________________________________ >> flashrom mailing list >> flashrom(a)flashrom.org >> https://www.flashrom.org/mailman/listinfo/flashrom >> > > > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > https://www.flashrom.org/mailman/listinfo/flashrom >

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Re: [flashrom] FAILED: GA-B75M-D3V
by David Hendricks 23 Dec '16

23 Dec '16

Looks like it failed to overwrite the descriptor region (Intel ME-related headache): https://www.flashrom.org/ME You can target regions more carefully using a layout file. It appears the other regions (ME, BIOS, GbE) are unlocked, so you can try creating a layout that includes only those regions. On Mon, Dec 19, 2016 at 7:54 PM, Shawn <citypw(a)gmail.com> wrote: > Hi flashrom maintainers, > > I failed to write a modified ROM to the flash via internal. Maybe this > chipset can only be writable via external programmer? > > root@sysresccd /root % flashrom -p internal > flashrom v0.9.8-r1888 on Linux 4.4.28-std490-amd64 (x86_64) > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > Found chipset "Intel B75". > Enabling flash write... Warning: SPI Configuration Lockdown activated. > OK. > Found Macronix flash chip "MX25L6405" (8192 kB, SPI) mapped at > physical address 0xff800000. > Found Macronix flash chip "MX25L6405D" (8192 kB, SPI) mapped at > physical address 0xff800000. > Found Macronix flash chip "MX25L6406E/MX25L6408E" (8192 kB, SPI) > mapped at physical address 0xff800000. > Found Macronix flash chip > "MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E" (8192 kB, SPI) mapped at > physical address 0xff800000. > Multiple flash chip definitions match the detected chip(s): > "MX25L6405", "MX25L6405D", "MX25L6406E/MX25L6408E", > "MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E" > Please specify which chip definition to use with the -c <chipname> option. > > > root@sysresccd /root % flashrom -VV -p internal -c MX25L6405 -w > factory_giga1.bin.new.new > flashrom v0.9.8-r1888 on Linux 4.4.28-std490-amd64 (x86_64) > flashrom is free software, get the source code at http://www.flashrom.org > > flashrom was built with libpci 3.4.1, GCC 4.8.5, little endian > Command line (7 args): flashrom -VV -p internal -c MX25L6405 -w > factory_giga1.bin.new.new > Calibrating delay loop... OS timer resolution is 1 usecs, 1944M loops > per second, 10 myus = 10 us, 100 myus = 117 us, 1000 myus = 1021 us, > 10000 myus = 10021 us, 4 myus = 4 us, OK. > Initializing internal programmer > No coreboot table found. > Using Internal DMI decoder. > DMI string chassis-type: "Desktop" > DMI string system-manufacturer: "Gigabyte Technology Co., Ltd." > DMI string system-product-name: "To be filled by O.E.M." > DMI string system-version: "To be filled by O.E.M." > DMI string baseboard-manufacturer: "Gigabyte Technology Co., Ltd." > DMI string baseboard-product-name: "B75M-D3V" > DMI string baseboard-version: "To be filled by O.E.M." > Found ITE Super I/O, ID 0x8728 on port 0x2e > Found chipset "Intel B75" with PCI ID 8086:1e49. > Enabling flash write... Root Complex Register Block address = 0xfed1c000 > GCS = 0xc64: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x3 > (SPI) > Top Swap: enabled (A16(+) inverted) > 0xfff80000/0xffb80000 FWH IDSEL: 0x0 > 0xfff00000/0xffb00000 FWH IDSEL: 0x0 > 0xffe80000/0xffa80000 FWH IDSEL: 0x1 > 0xffe00000/0xffa00000 FWH IDSEL: 0x1 > 0xffd80000/0xff980000 FWH IDSEL: 0x2 > 0xffd00000/0xff900000 FWH IDSEL: 0x2 > 0xffc80000/0xff880000 FWH IDSEL: 0x3 > 0xffc00000/0xff800000 FWH IDSEL: 0x3 > 0xff700000/0xff300000 FWH IDSEL: 0x4 > 0xff600000/0xff200000 FWH IDSEL: 0x5 > 0xff500000/0xff100000 FWH IDSEL: 0x6 > 0xff400000/0xff000000 FWH IDSEL: 0x7 > 0xfff80000/0xffb80000 FWH decode enabled > 0xfff00000/0xffb00000 FWH decode enabled > 0xffe80000/0xffa80000 FWH decode enabled > 0xffe00000/0xffa00000 FWH decode enabled > 0xffd80000/0xff980000 FWH decode enabled > 0xffd00000/0xff900000 FWH decode enabled > 0xffc80000/0xff880000 FWH decode enabled > 0xffc00000/0xff800000 FWH decode enabled > 0xff700000/0xff300000 FWH decode enabled > 0xff600000/0xff200000 FWH decode enabled > 0xff500000/0xff100000 FWH decode enabled > 0xff400000/0xff000000 FWH decode enabled > Maximum FWH chip size: 0x100000 bytes > SPI Read Configuration: prefetching enabled, caching enabled, > BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled > SPIBAR = 0xf7795000 + 0x3800 > 0x04: 0xe008 (HSFS) > HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 > Warning: SPI Configuration Lockdown activated. > Reading OPCODES... done > OP Type Pre-OP > op[0]: 0x02, write w/ addr, none > op[1]: 0x03, read w/ addr, none > op[2]: 0x20, write w/ addr, none > op[3]: 0x05, read w/o addr, none > op[4]: 0x9f, read w/o addr, none > op[5]: 0x01, write w/o addr, none > op[6]: 0x00, read w/o addr, none > op[7]: 0x00, read w/o addr, none > Pre-OP 0: 0x06, Pre-OP 1: 0x00 > 0x06: 0x0000 (HSFC) > HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 > 0x08: 0x00000000 (FADDR) > 0x50: 0x0000ffff (FRAP) > BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff > 0x54: 0x00000000 FREG0: Flash Descriptor region > (0x00000000-0x00000fff) is read-write. > 0x58: 0x07ff0000 FREG1: BIOS region (0x00000000-0x007fffff) is read-write. > 0x5C: 0x04ff0001 FREG2: Management Engine region > (0x00001000-0x004fffff) is read-write. > 0x60: 0x00001fff FREG3: Gigabit Ethernet region is unused. > 0x64: 0x00001fff FREG4: Platform Data region is unused. > 0x74: 0x00000000 (PR0 is unused) > 0x78: 0x00000000 (PR1 is unused) > 0x7C: 0x00000000 (PR2 is unused) > 0x80: 0x00000000 (PR3 is unused) > 0x84: 0x00000000 (PR4 is unused) > 0x90: 0x84 (SSFS) > SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 > 0x91: 0xf94240 (SSFC) > SSFC: SCGO=0, ACS=0, SPOP=0, COP=4, DBC=2, SME=0, SCF=1 > 0x94: 0x0006 (PREOP) > 0x96: 0x043b (OPTYPE) > 0x98: 0x05200302 (OPMENU) > 0x9C: 0x0000019f (OPMENU+4) > 0xA0: 0x00000000 (BBAR) > 0xC4: 0x00802005 (LVSCC) > LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 > 0xC8: 0x00002005 (UVSCC) > UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20 > 0xD0: 0x00000000 (FPB) > Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. > === Content Section === > FLVALSIG 0x0ff0a55a > FLMAP0 0x02040003 > FLMAP1 0x12100206 > FLMAP2 0x00210120 > > --- Details --- > NR (Number of Regions): 3 > FRBA (Flash Region Base Address): 0x040 > NC (Number of Components): 1 > FCBA (Flash Component Base Address): 0x030 > ISL (ICH/PCH Strap Length): 18 > FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100 > NM (Number of Masters): 3 > FMBA (Flash Master Base Address): 0x060 > MSL/PSL (MCH/PROC Strap Length): 1 > FMSBA (Flash MCH/PROC Strap Base Address): 0x200 > > === Component Section === > FLCOMP 0x09300024 > FLILL 0x00000000 > > --- Details --- > Component 1 density: 8 MB > Component 2 is not used. > Read Clock Frequency: 20 MHz > Read ID and Status Clock Freq.: 33 MHz > Write and Erase Clock Freq.: 33 MHz > Fast Read is supported. > Fast Read Clock Frequency: 33 MHz > Dual Output Fast Read Support: enabled > No forbidden opcodes. > > === Region Section === > FLREG0 0x00000000 > FLREG1 0x07ff0000 > FLREG2 0x04ff0001 > FLREG3 0x00001fff > FLREG4 0x00001fff > > --- Details --- > Region 0 (Descr.) 0x00000000 - 0x00000fff > Region 1 (BIOS ) 0x00000000 - 0x007fffff > Region 2 (ME ) 0x00001000 - 0x004fffff > Region 3 (GbE ) is unused. > Region 4 (Platf.) is unused. > > === Master Section === > FLMSTR1 0xffff0000 > FLMSTR2 0xffff0000 > FLMSTR3 0xffff0118 > > --- Details --- > Descr. BIOS ME GbE Platf. > BIOS rw rw rw rw rw > ME rw rw rw rw rw > GbE rw rw rw rw rw > > OK. > No IT87* serial flash segment enabled. > The following protocols are supported: FWH, SPI. > Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 > 0xc2, id2 0x2017 > Found Macronix flash chip "MX25L6405" (8192 kB, SPI) mapped at > physical address 0xff800000. > Chip status register is 0x00. > Chip status register: Status Register Write Disable (SRWD, SRP, ...) is > not set > Chip status register: Bit 6 is not set > Chip status register: Block Protect 3 (BP3) is not set > Chip status register: Block Protect 2 (BP2) is not set > Chip status register: Block Protect 1 (BP1) is not set > Chip status register: Block Protect 0 (BP0) is not set > Chip status register: Write Enable Latch (WEL) is not set > Chip status register: Write In Progress (WIP/BUSY) is not set > Block protection is disabled. > Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. > Reading old flash chip contents... done. > Erasing and writing flash chip... Trying erase function 0... > 0x000000-0x00ffff:EFAILED at 0x00001000! Expected=0xff, Found=0x20, > failed byte count from 0x00000000-0x0000ffff: 0xb55d > ERASE FAILED! > Reading current flash chip contents... done. Looking for another erase > function. > Trying erase function 1... 0x000000-0x00ffff:EInvalid OPCODE 0x06, > will not execute. > spi_block_erase_d8 failed during command execution at address 0x0 > Reading current flash chip contents... done. Looking for another erase > function. > Trying erase function 2... 0x000000-0x7fffff:EInvalid OPCODE 0x06, > will not execute. > spi_chip_erase_60 failed during command execution > Reading current flash chip contents... done. Looking for another erase > function. > Trying erase function 3... 0x000000-0x7fffff:EInvalid OPCODE 0x06, > will not execute. > spi_chip_erase_c7 failed during command execution > Looking for another erase function. > No usable erase functions left. > FAILED! > Uh oh. Erase/write failed. Checking if anything has changed. > Reading current flash chip contents... done. > Apparently at least some data has changed. > Your flash chip is in an unknown state. > Get help on IRC at chat.freenode.net (channel #flashrom) or > mail flashrom(a)flashrom.org with the subject "FAILED: <your board name>"! > ------------------------------------------------------------ > ------------------- > DO NOT REBOOT OR POWEROFF! > Restoring MMIO space at 0xf77988a0 > Restoring PCI config space for 00:1f:0 reg 0xdc > > > -- > GNU powered it... > GPL protect it... > God blessing it... > > regards > Shawn > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > https://www.flashrom.org/mailman/listinfo/flashrom >

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FAILED: GA-B75M-D3V
by Shawn 20 Dec '16

20 Dec '16

Hi flashrom maintainers, I failed to write a modified ROM to the flash via internal. Maybe this chipset can only be writable via external programmer? root@sysresccd /root % flashrom -p internal flashrom v0.9.8-r1888 on Linux 4.4.28-std490-amd64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "Intel B75". Enabling flash write... Warning: SPI Configuration Lockdown activated. OK. Found Macronix flash chip "MX25L6405" (8192 kB, SPI) mapped at physical address 0xff800000. Found Macronix flash chip "MX25L6405D" (8192 kB, SPI) mapped at physical address 0xff800000. Found Macronix flash chip "MX25L6406E/MX25L6408E" (8192 kB, SPI) mapped at physical address 0xff800000. Found Macronix flash chip "MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E" (8192 kB, SPI) mapped at physical address 0xff800000. Multiple flash chip definitions match the detected chip(s): "MX25L6405", "MX25L6405D", "MX25L6406E/MX25L6408E", "MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E" Please specify which chip definition to use with the -c <chipname> option. root@sysresccd /root % flashrom -VV -p internal -c MX25L6405 -w factory_giga1.bin.new.new flashrom v0.9.8-r1888 on Linux 4.4.28-std490-amd64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.4.1, GCC 4.8.5, little endian Command line (7 args): flashrom -VV -p internal -c MX25L6405 -w factory_giga1.bin.new.new Calibrating delay loop... OS timer resolution is 1 usecs, 1944M loops per second, 10 myus = 10 us, 100 myus = 117 us, 1000 myus = 1021 us, 10000 myus = 10021 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. Using Internal DMI decoder. DMI string chassis-type: "Desktop" DMI string system-manufacturer: "Gigabyte Technology Co., Ltd." DMI string system-product-name: "To be filled by O.E.M." DMI string system-version: "To be filled by O.E.M." DMI string baseboard-manufacturer: "Gigabyte Technology Co., Ltd." DMI string baseboard-product-name: "B75M-D3V" DMI string baseboard-version: "To be filled by O.E.M." Found ITE Super I/O, ID 0x8728 on port 0x2e Found chipset "Intel B75" with PCI ID 8086:1e49. Enabling flash write... Root Complex Register Block address = 0xfed1c000 GCS = 0xc64: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x3 (SPI) Top Swap: enabled (A16(+) inverted) 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode enabled 0xff600000/0xff200000 FWH decode enabled 0xff500000/0xff100000 FWH decode enabled 0xff400000/0xff000000 FWH decode enabled Maximum FWH chip size: 0x100000 bytes SPI Read Configuration: prefetching enabled, caching enabled, BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled SPIBAR = 0xf7795000 + 0x3800 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 Warning: SPI Configuration Lockdown activated. Reading OPCODES... done OP Type Pre-OP op[0]: 0x02, write w/ addr, none op[1]: 0x03, read w/ addr, none op[2]: 0x20, write w/ addr, none op[3]: 0x05, read w/o addr, none op[4]: 0x9f, read w/o addr, none op[5]: 0x01, write w/o addr, none op[6]: 0x00, read w/o addr, none op[7]: 0x00, read w/o addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x00 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00000000 (FADDR) 0x50: 0x0000ffff (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-write. 0x58: 0x07ff0000 FREG1: BIOS region (0x00000000-0x007fffff) is read-write. 0x5C: 0x04ff0001 FREG2: Management Engine region (0x00001000-0x004fffff) is read-write. 0x60: 0x00001fff FREG3: Gigabit Ethernet region is unused. 0x64: 0x00001fff FREG4: Platform Data region is unused. 0x74: 0x00000000 (PR0 is unused) 0x78: 0x00000000 (PR1 is unused) 0x7C: 0x00000000 (PR2 is unused) 0x80: 0x00000000 (PR3 is unused) 0x84: 0x00000000 (PR4 is unused) 0x90: 0x84 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xf94240 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=4, DBC=2, SME=0, SCF=1 0x94: 0x0006 (PREOP) 0x96: 0x043b (OPTYPE) 0x98: 0x05200302 (OPMENU) 0x9C: 0x0000019f (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x00802005 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xC8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20 0xD0: 0x00000000 (FPB) Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. === Content Section === FLVALSIG 0x0ff0a55a FLMAP0 0x02040003 FLMAP1 0x12100206 FLMAP2 0x00210120 --- Details --- NR (Number of Regions): 3 FRBA (Flash Region Base Address): 0x040 NC (Number of Components): 1 FCBA (Flash Component Base Address): 0x030 ISL (ICH/PCH Strap Length): 18 FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100 NM (Number of Masters): 3 FMBA (Flash Master Base Address): 0x060 MSL/PSL (MCH/PROC Strap Length): 1 FMSBA (Flash MCH/PROC Strap Base Address): 0x200 === Component Section === FLCOMP 0x09300024 FLILL 0x00000000 --- Details --- Component 1 density: 8 MB Component 2 is not used. Read Clock Frequency: 20 MHz Read ID and Status Clock Freq.: 33 MHz Write and Erase Clock Freq.: 33 MHz Fast Read is supported. Fast Read Clock Frequency: 33 MHz Dual Output Fast Read Support: enabled No forbidden opcodes. === Region Section === FLREG0 0x00000000 FLREG1 0x07ff0000 FLREG2 0x04ff0001 FLREG3 0x00001fff FLREG4 0x00001fff --- Details --- Region 0 (Descr.) 0x00000000 - 0x00000fff Region 1 (BIOS ) 0x00000000 - 0x007fffff Region 2 (ME ) 0x00001000 - 0x004fffff Region 3 (GbE ) is unused. Region 4 (Platf.) is unused. === Master Section === FLMSTR1 0xffff0000 FLMSTR2 0xffff0000 FLMSTR3 0xffff0118 --- Details --- Descr. BIOS ME GbE Platf. BIOS rw rw rw rw rw ME rw rw rw rw rw GbE rw rw rw rw rw OK. No IT87* serial flash segment enabled. The following protocols are supported: FWH, SPI. Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Found Macronix flash chip "MX25L6405" (8192 kB, SPI) mapped at physical address 0xff800000. Chip status register is 0x00. Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set Chip status register: Bit 6 is not set Chip status register: Block Protect 3 (BP3) is not set Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Block protection is disabled. Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x00ffff:EFAILED at 0x00001000! Expected=0xff, Found=0x20, failed byte count from 0x00000000-0x0000ffff: 0xb55d ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. Trying erase function 1... 0x000000-0x00ffff:EInvalid OPCODE 0x06, will not execute. spi_block_erase_d8 failed during command execution at address 0x0 Reading current flash chip contents... done. Looking for another erase function. Trying erase function 2... 0x000000-0x7fffff:EInvalid OPCODE 0x06, will not execute. spi_chip_erase_60 failed during command execution Reading current flash chip contents... done. Looking for another erase function. Trying erase function 3... 0x000000-0x7fffff:EInvalid OPCODE 0x06, will not execute. spi_chip_erase_c7 failed during command execution Looking for another erase function. No usable erase functions left. FAILED! Uh oh. Erase/write failed. Checking if anything has changed. Reading current flash chip contents... done. Apparently at least some data has changed. Your flash chip is in an unknown state. Get help on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with the subject "FAILED: <your board name>"! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! Restoring MMIO space at 0xf77988a0 Restoring PCI config space for 00:1f:0 reg 0xdc -- GNU powered it... GPL protect it... God blessing it... regards Shawn

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W836xx:Notebook Acer E5-553G-17ZN: flashrom -V
by Martin Vyšohlíd 17 Dec '16

17 Dec '16

flashrom -V[VV] reports attached...

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W836xx: DG965SS: flashrom -V
by Frank Reischl 16 Dec '16

16 Dec '16

*Flash chip is Atmel 26DF081A, I'm finding that I can't read it in-circuit either, with a TL866A programmer and clip. flashrom v0.9.7-r1782 on Linux 3.16.0-4-586 (i686) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.2.1, GCC 4.8.2, little endian Command line (3 args): flashrom -p internal -V Calibrating delay loop... OS timer resolution is 1 usecs, 2386M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 999 us, 10000 myus = 14067 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. Using Internal DMI decoder. DMI string chassis-type: "Desktop" DMI string system-manufacturer: " " DMI string system-product-name: " " DMI string system-version: " " DMI string baseboard-manufacturer: "Intel Corporation" DMI string baseboard-product-name: "DG965SS" DMI string baseboard-version: "AAD41678-308" W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: f1. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. Found chipset "Intel ICH8/ICH8R" with PCI ID 8086:2810. Enabling flash write... Root Complex Register Block address = 0xfed1c000 GCS = 0x400464: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x1 (SPI) Top Swap : not enabled 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode disabled 0xffe00000/0xffa00000 FWH decode disabled 0xffd80000/0xff980000 FWH decode disabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytesSPI Read Configuration: prefetching disabled, caching enabled, BIOS_CNTL = 0x02: BIOS Lock Enable: enabled, BIOS Write Enable: disabled Warning: Setting Bios Control at 0xdc from 0x02 to 0x01 failed. New value is 0x02. SPIBAR = 0xb77be000 + 0x3020 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 Warning: SPI Configuration Lockdown activated. Reading OPCODES... done 0x06: 0x3f00 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=63, SME=0 0x50: 0x00000a0b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b 0x54: 0x00000000 FREG0: Warning: Flash Descriptor region (0x00000000-0x00000fff) is read-only. 0x58: 0x00ff0035 FREG1: BIOS region (0x00035000-0x000fffff) is read-write. 0x5C: 0x00340003 FREG2: Warning: Management Engine region (0x00003000-0x00034fff) is locked. 0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write. Not all flash regions are freely accessible by flashrom. This is most likely due to an active ME. Please see http://flashrom.org/ME for details. Writes have been disabled for safety reasons. You can enforce write support with the ich_spi_force programmer option, but you will most likely harm your hardware! If you force flashrom you will get no support if something breaks. On a few mainboards it is possible to enable write access by setting a jumper (see its documentation or the board itself). 0x90: 0x00 (SSFS) SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 0x91: 0x004024 (SSFC) SSFC: SCGO=0, ACS=1, SPOP=0, COP=2, DBC=0, SME=0, SCF=0 0x94: 0x0000 (PREOP) 0x96: 0x0008 (OPTYPE) 0x98: 0x0000ab9f (OPMENU) 0x9C: 0x00000000 (OPMENU+4) 0xC1: 0xffffffff (VSCC) VSCC: BES=0x3, WG=1, WSR=1, WEWS=1, EO=0xff, VCL=1 Enabling hardware sequencing because some important opcode is locked. PROBLEMS, continuing anyway The following protocols are supported: FWH, Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Found 1 attached SPI flash chip with a density of 1024 kB. There is only one partition containing the whole address space (0x000000 - 0x0fffff). There are 256 erase blocks with 4096 B each. Found Programmer flash chip "Opaque flash chip" (1024 kB, Programmer-specific) at physical address 0x0. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x77, id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x14, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x77, id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x14, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x77, id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x60, id2 0x7c, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x14, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x14, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x14, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x14, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x77, id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x14, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x14, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x14, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x14, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x77, id2 0x8e, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x14, id2 0xa0, id1 parity violation, id1 is normal flash content, id2 is normal flash content Found Programmer flash chip "Opaque flash chip" (1024 kB, Programmer-specific). No operations were specified. Restoring PCI config space for 00:1f:0 reg 0xdc

1 0

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flashrom December 2016