Hi.
1 I have created a logfile some time ago using
flashrom -p internal -V > flashrom_info.log
2 I have flashed a rom with flashrom some time ago. Works fine :).
3 I have read my flashed rom after some time (and reboots) have passed after flashing.
flashrom -V -p internal -r rom.bin > flashrom_read.log
3 Now I have created a logfile again (I have enabled in bios a network card (Realtek RTL-8110SC/8169SC Gigabit Ethernet built-in into motherboard) rom and wanted to know wheither flashrom is able to detect it and read it, but now i see it isn't)
flashrom -p internal -V > flashrom_log.txt
and got a warning about not supported and not tested microscheme and some other and an advice to write this address which haven't been appeared the previous time.
It is very strange.
The new read log is flashrom_read_log.txt
Hello all!
This is the resubmit of the uISP programmer support patch. A list of
fixes follows:
* Proper protocol versioning support.
* Programmer now reports its name, SPI speed and CPU frequency
* Programmer now allows setting the SPI frequency. While now this
is done using spi_freq=xxx parameter (in Khz)
* Programmer can now have an arbitary number of SPI flashes attached (on
different SPI buses)
and even allows several instances of flashrom to work with each of
these flashes at
the same time (option idx=N specifies the bus number to use, default
is 0).
* Speed improvements due to minor optimizations in firmware.
(2Mib flash read was 2m13s now is only 1m15s)
* Firmware can now be easily extended to add hardware other than uISP,
even based
on other MCUs.
* Code cleaned up
* Firmware code reworked for better portability. Since it's based off
antares, STM32 is
the next target.
A full writeup with hardware pictures and nice benchmark graphs can be
found in my
blog here:
http://ncrmnt.org/wp/2014/06/08/flashrom-benchmark-buspirate-vs-uisp/
Firmware source code can be found on github here:
https://github.com/uISP/uisp-app-flashprog
--
Regards,
Andrew
On Wed, 3 Oct 2012 06:13:00 +0200
Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote:
> This patch set enables us to figure out if transactions will succeed
> without executing them, which allows for a refactoring of
> probe_spi_rdid_generic() which in consequence makes it possible to add
> probe_spi_rdid_edi().
>
Hi Stefan,
was there any development towards the functionality discussed
in this old thread: check_trans() and probe_spi_rdid_edi()?
> The infrastructure code as a whole, but especially the ichspi code
> is heavily modified. Please be aware of that if you test it on
> mainboards.
>
> Antonio: please rebase your Spansion patch on this one and extend it
> to add actually two chips by using the full 32 bit model IDs
> (0x20184d00, 0x20184d01) and .probe = probe_spi_rdid_edi.
>
I am playing with these chips again.
FTR I am able to read and write S25FL129P1 chips using flashrom
v0.9.7-r1782 which is in Debian ubstable, it supports the similar
"S25FL128S......0", but only the bulk erase function worked
(spi_block_erase_60), I wasn't able to do a block or sector erase; can
this depend on the programmer (ft2232_spi)?
I will send a proper log the next time I write a chip.
I have also tried to rebase this old set about check_trans() and
probe_spi_rdid_edi() on top of the latest svn, I will check if the code
still works but I wanted to ask first what the current status
is, and if there is still interest to support rdid EDI.
Thanks,
Antonio
--
Antonio Ospite
http://ao2.it
A: Because it messes up the order in which people normally read text.
See http://en.wikipedia.org/wiki/Posting_style
Q: Why is top-posting such a bad thing?
flashrom asked me to send you this output, so I did. Hope it helps.
/Martin
flashrom v0.9.7-r1782 on Linux 3.14-1-amd64 (x86_64)
flashrom is free software, get the source code at http://www.flashrom.org
flashrom was built with libpci 3.2.1, GCC 4.8.2, little endian
Command line (3 args): flashrom -p internal -V
Calibrating delay loop... OS timer resolution is 1 usecs, 3313M loops per
second, 10 myus = 10 us, 100 myus = 118 us, 1000 myus = 997 us, 10000 myus =
9897 us, 4 myus = 15 us, OK.
Initializing internal programmer
No coreboot table found.
Using Internal DMI decoder.
No DMI table found.
W836xx enter config mode worked or we were already in config mode. W836xx leave
config mode had no effect.
Active config mode, unknown reg 0x20 ID: 00.
Please send the output of "flashrom -V" to
flashrom(a)flashrom.org with W836xx: your board name: flashrom -V
as the subject to help us finish support for your Super I/O. Thanks.
Found chipset "Intel QM87" with PCI ID 8086:8c4f.
This chipset is marked as untested. If you are using an up-to-date version
of flashrom *and* were (not) able to successfully update your firmware with it,
then please email a report to flashrom(a)flashrom.org including a verbose (-V)
log.
Thank you!
Enabling flash write... Root Complex Register Block address = 0xfed1c000
GCS = 0xc21: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI)
Top Swap : not enabled
0xfff80000/0xffb80000 FWH IDSEL: 0x0
0xfff00000/0xffb00000 FWH IDSEL: 0x0
0xffe80000/0xffa80000 FWH IDSEL: 0x1
0xffe00000/0xffa00000 FWH IDSEL: 0x1
0xffd80000/0xff980000 FWH IDSEL: 0x2
0xffd00000/0xff900000 FWH IDSEL: 0x2
0xffc80000/0xff880000 FWH IDSEL: 0x3
0xffc00000/0xff800000 FWH IDSEL: 0x3
0xff700000/0xff300000 FWH IDSEL: 0x4
0xff600000/0xff200000 FWH IDSEL: 0x5
0xff500000/0xff100000 FWH IDSEL: 0x6
0xff400000/0xff000000 FWH IDSEL: 0x7
0xfff80000/0xffb80000 FWH decode enabled
0xfff00000/0xffb00000 FWH decode enabled
0xffe80000/0xffa80000 FWH decode enabled
0xffe00000/0xffa00000 FWH decode enabled
0xffd80000/0xff980000 FWH decode enabled
0xffd00000/0xff900000 FWH decode enabled
0xffc80000/0xff880000 FWH decode enabled
0xffc00000/0xff800000 FWH decode enabled
0xff700000/0xff300000 FWH decode enabled
0xff600000/0xff200000 FWH decode enabled
0xff500000/0xff100000 FWH decode enabled
0xff400000/0xff000000 FWH decode enabled
Maximum FWH chip size: 0x100000 bytesSPI Read Configuration: prefetching
enabled, caching enabled,
BIOS_CNTL = 0x2b: BIOS Lock Enable: enabled, BIOS Write Enable: enabled
Warning: BIOS region SMM protection is enabled!
Warning: Setting Bios Control at 0xdc from 0x2a to 0x09 failed.
New value is 0x2b.
SPIBAR = 0x00007f85a7697000 + 0x3800
0x04: 0xf008 (HSFS)
HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1
Warning: SPI Configuration Lockdown activated.
Reading OPCODES... done
0x06: 0x3f00 (HSFC)
HSFC: FGO=0, FCYCLE=0, FDBC=63, SME=0
0x50: 0x00004a4b (FRAP)
BMWAG 0x00, BMRAG 0x00, BRWA 0x4a, BRRA 0x4b
0x54: 0x00000000 FREG0: Warning: Flash Descriptor region (0x00000000-0x00000fff)
is read-only.
0x58: 0x0bff0500 FREG1: BIOS region (0x00500000-0x00bfffff) is read-write.
0x5C: 0x04ff0003 FREG2: Warning: Management Engine region
(0x00003000-0x004fffff) is locked.
0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is
read-write.
Not all flash regions are freely accessible by flashrom. This is most likely
due to an active ME. Please see http://flashrom.org/ME for details.
0x78: 0x8bff0b40 PR1: Warning: 0x00b40000-0x00bfffff is read-only.
0x7C: 0x8adf0ab1 PR2: Warning: 0x00ab1000-0x00adffff is read-only.
0x80: 0x8ab00ab0 PR3: Warning: 0x00ab0000-0x00ab0fff is read-only.
0x84: 0x8aaf0800 PR4: Warning: 0x00800000-0x00aaffff is read-only.
Writes have been disabled for safety reasons. You can enforce write
support with the ich_spi_force programmer option, but you will most likely
harm your hardware! If you force flashrom you will get no support if
something breaks. On a few mainboards it is possible to enable write
access by setting a jumper (see its documentation or the board itself).
0x90: 0xc0 (SSFS)
SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0
0x91: 0xf94000 (SSFC)
SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=1
0x94: 0x0606 (PREOP)
0x96: 0x3f90 (OPTYPE)
0x98: 0x03013505 (OPMENU)
0x9C: 0x9f20d802 (OPMENU+4)
0xA0: 0x00000000 (BBAR)
0xC4: 0x80802025 (LVSCC)
LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1
0xC8: 0x80002025 (UVSCC)
UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0
0xD0: 0x00f12005 (FPB)
Enabling hardware sequencing due to multiple flash chips detected.
Density of ICH SPI component with index 1 is invalid. Encoded density is 0x6.
OK.
The following protocols are supported: FWH, Programmer-specific.
Probing for Programmer Opaque flash chip, 0 kB: Found 1 attached SPI flash chip
with a density of 8192 kB.
The flash address space (0x000000 - 0x7fffff) is divided at address 0x005000 in
two partitions.
The first partition ranges from 0x000000 to 0x004fff.
In that range are 5 erase blocks with 4096 B each.
The second partition ranges from 0x005000 to 0x7fffff.
In that range are 2043 erase blocks with 4096 B each.
Found Programmer flash chip "Opaque flash chip" (8192 kB, Programmer-specific)
at physical address 0x0.
Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x00, id2 0x00, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x80, id2 0x03, id1 is
normal flash content, id2 is normal flash content
Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x3b, id2 0x04, id1 is
normal flash content, id2 is normal flash content
Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x00, id2 0x00, id1
parity violation, id1 is normal flash content, id2 is normal flash content
Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x80, id2 0x03, id1
is normal flash content, id2 is normal flash content
Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x3b, id2 0x04, id1 is
normal flash content, id2 is normal flash content
Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x00, id2 0x00,
id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x83, id2 0xc4,
id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x80, id2 0x03,
id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x80, id2 0x03, id1 is
normal flash content, id2 is normal flash content
Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0x3b, id2 0x04,
id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x3b, id2 0x04, id1 is
normal flash content, id2 is normal flash content
Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported
size 1024 kB of chipset/board/programmer for FWH interface,
probe/read/erase/write may fail. probe_82802ab: id1 0x70, id2 0xf2, id1 is
normal flash content, id2 is normal flash content
Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x80, id2 0x03, id1 is
normal flash content, id2 is normal flash content
Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x80, id2 0x03, id1 is
normal flash content, id2 is normal flash content
Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x3b, id2 0x04, id1 is
normal flash content, id2 is normal flash content
Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x3b, id2 0x04, id1 is
normal flash content, id2 is normal flash content
Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x00, id2 0x00, id1 parity
violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported
size 1024 kB of chipset/board/programmer for FWH interface,
probe/read/erase/write may fail. probe_82802ab: id1 0x70, id2 0xf2, id1 is
normal flash content, id2 is normal flash content
Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x80, id2 0x03, id1 is
normal flash content, id2 is normal flash content
Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x3b, id2 0x04, id1 is
normal flash content, id2 is normal flash content
Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x80, id2 0x03,
id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x80, id2 0x03,
id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x80, id2 0x03,
id1 is normal flash content, id2 is normal flash content
Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x00, id2 0x00,
id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0x3b, id2 0x04,
id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x80,
id2 0x03, id1 is normal flash content, id2 is normal flash content
Found Programmer flash chip "Opaque flash chip" (8192 kB, Programmer-specific).
No operations were specified.
Restoring MMIO space at 0x7f85a769a8a0
Restoring PCI config space for 00:1f:0 reg 0xdc
flashrom v0.9.7-r1711 on Linux 3.14.6-1-ARCH (i686)
flashrom is free software, get the source code at http://www.flashrom.org
flashrom was built with libpci 3.2.0, GCC 4.8.2, little endian
Command line (3 args): flashrom -V -p internal
Calibrating delay loop... OS timer resolution is 2 usecs, 893M loops per second, delay more than 10% too short (got 85% of expected delay), recalculating... 910M loops per second, delay more than 10% too short (got 87% of expected delay), recalculating... 909M loops per second, delay more than 10% too short (got 86% of expected delay), recalculating... 909M loops per second, delay more than 10% too short (got 86% of expected delay), recalculating... 910M loops per second, delay loop is unreliable, trying to continue 10 myus = 9 us, 100 myus = 86 us, 1000 myus = 856 us, 10000 myus = 10078 us, 8 myus = 8 us, OK.
Initializing internal programmer
No coreboot table found.
DMI string system-manufacturer: "Hewlett-Packard"
DMI string system-product-name: "HP Pavilion dv1000 (PW923EA#ABZ) "
DMI string system-version: "Rev 1 "
DMI string baseboard-manufacturer: "Quanta"
DMI string baseboard-product-name: "09B8"
DMI string baseboard-version: "34.20"
DMI string chassis-type: "Notebook"
Laptop detected via DMI.
W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect.
Active config mode, unknown reg 0x20 ID: ec.
Please send the output of "flashrom -V" to
flashrom(a)flashrom.org with W836xx: your board name: flashrom -V
as the subject to help us finish support for your Super I/O. Thanks.
========================================================================
WARNING! You seem to be running flashrom on an unsupported laptop.
Laptops, notebooks and netbooks are difficult to support and we
recommend to use the vendor flashing utility. The embedded controller
(EC) in these machines often interacts badly with flashing.
See the manpage and http://www.flashrom.org/Laptops for details.
If flash is shared with the EC, erase is guaranteed to brick your laptop
and write may brick your laptop.
Read and probe may irritate your EC and cause fan failure, backlight
failure and sudden poweroff.
You have been warned.
========================================================================
Aborting.
Error: Programmer initialization failed.
I have it loaded on a flash drive along with doslfn (Dos long file name)
so that it doesn't error out with a file not found when it tries to
access DMIDECODE (which with 8.3 convention is DMIDEC~1).
First two boards that I ran this configuration on (with the jumper
closed since these are HP XW9400) backed up the existing ROM without any
problem and then flashed to one with the current boot block as it was
supposed to.
Third board, backed up the existing BIOS and then completed the reflash
with verify and immediately after passing verification threw the error.
This board is now bricked.
Fourth board throws the error immediately after doing a backup of the
flash or even a simple probe. This one I haven't flashed, so it didn't
brick.
So I tried to do a rom backup and probe with one of the first 2 boards
since those passed without any problem, but it also now throws the
error.
It's not memory or processor since I'm using known good components.
>>> Stefan Tauner 06/25/14 3:23 AM >>>
On Tue, 24 Jun 2014 22:31:15 -0400
"John Pohlman" wrote:
> I've got a strange one here flashing an HP XW9400
>
> flashrom 0.9.6 running on FreeDos worked perfectly for reading and
writing a bios but now it throws this error on exit along with an EIP
error.
>
> The problem occurs on multiple boards even when doing something as
simple as writing a bios dump.
>
> Anyone have any ideas?
Hi,
what does "now" mean? Did the flashrom version change, or anything
else? Can you please post a log or at least an excerpt of one?
--
Kind regards/Mit freundlichen Grüßen, Stefan Tauner
I've got a strange one here flashing an HP XW9400
flashrom 0.9.6 running on FreeDos worked perfectly for reading and writing a bios but now it throws this error on exit along with an EIP error.
The problem occurs on multiple boards even when doing something as simple as writing a bios dump.
Anyone have any ideas?
Hi,
I updated Nico's patch[1] for IFD parsing support in flashrom to apply
to the current tree. Just want to put it out there to avoid duplicate work.
Regards,
Patrick
[1] http://patchwork.coreboot.org/patch/3966/
--
Patrick Georgi
Fachbereich SINA-Entwicklung
Public Sector
secunet Security Networks AG
Tel.: +49 201 54 54-3610, Fax: +49 201 54 54-1325
E-Mail: Patrick.Georgi(a)secunet.com
Mergenthalerallee 77, 65760 Eschborn, Deutschland
www.secunet.com
Sitz: Kronprinzenstraße 30, 45128 Essen, Deutschland / Amtsgericht Essen
HRB 13615
Vorstand: Dr. Rainer Baumgart (Vors.), Willem Bulthuis, Thomas Pleines
Aufsichtsratsvorsitzender: Dr. Peter Zattler
On Sun, 22 Jun 2014 21:05:25 -0400
Nicholas Hadler <nicholas.hadler(a)gmail.com> wrote:
> Hi, sorry if this is a dumb question but is there anyway to flash a M24C32
> with flashrom?
No. That's an I2C EEPROM and hence is currently not supported.
--
Kind regards/Mit freundlichen Grüßen, Stefan Tauner