On Tue, 19 Mar 2013 16:12:43 +1100
James Cameron <quozl(a)laptop.org> wrote:
> I'm an Open Firmware developer working for One Laptop per Child.
> We have used the MX25U3235E chip in revision B1 of our XO-4 design,
> and I am trying to use flashrom (r1657) with a Bus Pirate to read from
> a chip.
> I see you pushed a patch for this chip in the past few days. A happy
> coincidence perhaps.
> Is there anything I can do to help you change TEST_UNTESTED to
> something else?
> (Sorry if this is an obvious question, but I have very little
> knowledge of flashrom, having used for the first time yesterday with a
> different chip. Mostly we program the chip from within Open
> I changed TEST_UNTESTED to TEST_OK_PR on my system, and captured the
> attached logs.
> While the identify worked, the read gave errors, and the output file
> contained 0xff only. We have never intentionally enabled any block
> protection on this chip.
the .tested field is only used for QA and telling the user about it.
Changing it does not influence functionality.
If you are in a hurry skip this paragraph. :)
I am a bit puzzled at the moment regarding the (read) log. If you look
at the detailed output of the contents of the status register at line
132 ff. you see that flashrom (mistakenly) reads 0xFF, which leads to
the assumption that a block protection is enabled (see bottom of page
26 in the datasheet of the chip; that's quite a standard layout of a
SPI flash status register...). It then tries to disable the
"protection" and fails because another bit in the status register - the
WIP bit - remains at 1.
I have no idea why it (always) reads 0xFF from the status register... I
have checked the opcode and it is correct, and there is nothing fancy
about... apart from one thing I just noticed which you could test:
in spi_read_status_register() in spi25_statusreg.c replace 2 with 1 in
the array declaration readarr so that this line becomes
unsigned char readarr; /* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */
wbsio is our driver for a very annoying winbond SPI master and as the
fixme in the function says, this hack should not be in the generic code.
If the macronix chip does not repeat the status register contents when
one reads more than one byte after sending the RDSR (read status
register) opcode (which chips usually do) but 0xFF then we have found
PS: please send further mails to flashrom(a)flashrom.org - our mailing
Kind regards/Mit freundlichen Grüßen, Stefan Tauner
thanks for your mail. I have added the flashrom mailing list in CC:
because we should develop a generic way to handle DualBIOS and similar
On 09.04.2010 08:12, Vadim Girlin wrote:
> I'm going to try coreboot on Gigabyte GA-MA770-UD3.
> It's AMD 770 (RX780 / SB700).
> My motherboard supports hardware dual bios - with two chips on it.
> I'm going to try flashing backup chip and boot from it. It seems to be
> possible - I've tested it (flashing at least). Chips on this board could
> be switched by changing bit 0 at undocumented register EF on LDN 7 of
> IT8720. I can use slightly patched flashrom for accessing any chip I
> want without any problems. And this is tested many times.
> My idea is to use backup chip for debugging - that always keeps my
> chance to reboot from main bios chip. And removes the need for
> desoldering etc.
> And second problem is that original bios is checking second chip - and
> trying to recover it by flashing the bios from main chip on reboot?
> rewriting coreboot. AFAICS this could be solved by including some
> signatures etc. It seems to be easy to find out. May be someone is
> working on this?
> BTW I can send the patch for flashrom - but I think that with
> information I mentioned above somebody could make it much better than my
> ugly hack. I hope the regs should be the same for all latest Gigabyte
> MBs using IT8720/18
It would be great if you could send that patch. It will help us make a
flashrom design decision that works for all boards with multiple flash
By the way, some of us have good contacts at ITE, so we can ask ITE for
details about the undocumented registers.
before we change flashrom to work with current layout requirements, we
should summarize the features we need/want, and then decide how to
handle the individual layout regions internally.
"write strategy" describes a combination of erase+write commands with a
given block size, touching some blocks.
"read protected" describes a region which can not be read.
"write protected" describes a region which can not be written.
"write once" describes a region which can be written exactly once in the
If you add a feature to the list, please give it a nickname so we know
which feature people are referring to. Some of the features below might
not be desirable, but I want to list them anyway so we can explicitly
declare them as unsupported if needed.
fullwrite-unrestricted: Write a chip-sized image, no special read/write
restrictions of the chip, no layout file needs to be specified. Default
write case right now.
fullwrite-noread: Write a chip-sized image, reading anything from the
chip is not possible. Many DVD writers fall in that category. No
verification, violates our reliability guarantees.
fullwrite-postread: Write a chip-sized image, reading anything from the
chip is only possible after write. Chips which are read-locked until a
full erase/write fall in that category. Do those exist as standalone
flash chips or only integrated into processors?
fullwrite-partialread: Write a chip-sized image, reading is only
possible in some chip regions. Only partial verification, violates our
fullwrite-partialwrite: Write a chip-sized image, but writing is only
possible in some regions. This is obviously a conflict unless the image
has the same contents as the chip in the write-protected regions and
there is a possible write strategy for the whole image which does not
touch the write-protected regions. Should flashrom always refuse this
scenario, or only refuse it in case of conflicts?
partialwrite-unrestricted: Write only parts of an image, the rest of the
chip contents is kept, no special read/write restrictions.
partialwrite-partialread: Write only parts of an image, the rest of the
chip contents is kept, reading is only possible in some chip regions. If
no read-protected regions are written and a suitable write strategy
exists, should flashrom warn? If a read-protected region is written,
should flashrom warn/refuse due to reliability requirements?
partialwrite-partialwrite: Write only parts of an image, the rest of the
chip contents is kept, writing is only possible in some chip regions. If
no write-protected regions are written and a suitable write strategy
exists, should flashrom warn? flashrom will refuse to write a
fullread-unrestricted: Read the full chip, no special read restrictions
of the chip.
partialread-unrestricted: Read only parts of a chip, no special read
restrictions of the chip.
partialread-partialread: Read only parts of a chip, some regions are
read-protected. flashrom should refuse to read any read-protected regions.
partialread-imagefiller: If only parts of a chip are read and the read
image has full chip size, what should be used as filler for unread
regions? 0x00 or 0xff?
partialread-layout-imagesize: If only parts of a chip are read, should
the read image still have full chip size with all read regions filled in
at the respective locations?
partialread-layout-split: If only parts of a chip are read, should it be
possible to write each region (or a combination thereof) to a separate
image file, and would that mapping be specified in the layout file?
partialwrite-layout-split: If only parts of a chip are written, should
it be possible to collect each part of the new image from a separate
image file, and would that mapping be specified in the layout file?
readwrite-protection-time: Which read protection and write protection
times exist? Temporary lock until unlock, temporary lock until chip soft
reset, temporary lock until chip/programmer hard reset (powerdown or
reset line), permanent eternal lock.
readwrite-protection-type: Which read protection and write protection
types exist? Programmer lock (e.g. Intel SPI), hardware chip lock (WP
pin), software chip lock (chip command).
readwrite-protection-interaction: How should we express this situation:
A region is write-locked with a software chip lock, but to remove that
software chip lock, a hardware chip lock has to be disabled first, then
the software chip lock can be disabled.
partialaccess-crash: Some regions in the chip are really off-limits and
will cause an unrecoverable error (system crash) when accessed (read or
write). That seems to be the case for some EC/flash interactions.
Comments? Any forks of flashrom (e.g. chromium) which need
infrastructure features not mentioned above?
I have added some flashrom and linux logs which might be helpfull:
The USB 3 PCI card has the following system properties:
There is also a PCI NIC Intel 82541PI Gigabit Ethernet Controller
(8086:107c, BDF 02:0a.0) and a PCI soundcard installed.
Tried to read the flash rom out of the 82541PI Intel NIC without problems.
/sys/bus/pci/devices/0000:02:0a.0 of the Intel NIC also gives access to
"rom" which the USB 3 and the soundcard do not. I am not sure if that means
that the rom is not accessible at all or if Ubuntu just does not know how.
Thanks in advance, brgds
Von: Philipp Post [mailto:Post.Philipp@googlemail.com]
Gesendet: Donnerstag, 24. Januar 2013 19:23
Betreff: USB 3 PCI Card support (request to add device)
- USB 3 PCI (not PCI-Express) card with RENESAS uPD720200A(Revision 4) USB
and ATMEL AT25F512B (ATMEL 1138, 25F512B, SSH) rom chip in
- IBM NetVista 8305 Desktop PC - built year 2003
The issue with the card is that it needs a flash rom update to work with
Windows Vista and up, otherwise the device does not work at all in these OS
("device cannot start"). Windows XP with Renesas drivers and Linux Ubuntu
11.3 out of the box works fine.
RENESAS has a rom update for the chip and a flash update tool which however
does not work with PCI cards, but just chips soldered to mainboards. At
least this seems to me the reason why it does not work. Chip is recognized
but the RENESAS tool says "Can not load / access firmware". The tool has the
option to change the device / vendor id as well via .ini file.
The card used is the only PCI USB 3 card on the market and basically works
very well when it works - with max PCI speed of course, which means approx.
double speed of USB 2. The card exists in hardware version 1 (RENESAS chip
uPD720200A) and 2 (RENESAS chip uPD720202). I do just have access to
hardware version 1. The name of the manufacturer behind the card is unknown
to me, but it could be an ADDONICS product. I do not have a technical
drawing of the card and I fear I can not obtain one but I do have the card
My question: would it be possible to incorporate this card into flashrom?
Would be great if someone could do it as I do not have the necessary skills
to do it myself.
In case you need further information, please let me know.
Thanks in advance, brgds
Links and further reading:
Card Information from different sellers (same card):
ATMEL rom specification (contains info how to write rom images):
Renesas USB chip information:
RENESAS rom update 184.108.40.206 with Windows updater (32 + 64 Bit) and drivers:
We need: "Firmware Version 220.127.116.11 pour uPD720200a"
RENESAS MS DOS flash update tool (which did not do the job):
IBM NetVista 8305 Hardware Maintenance Manual:
Renesas Electronics USB 3.0 Host Controller:
Renesas Electronics USB 3.0 Root Hub
I don't suppose anyone has any experience updating or fixing MAC addresses on Nvidea nVIDIA MCP55V-Pro (Supermicro H8DMT+) ?
Following an experimental reflash everything went well, except afterwards we noticed the mac address had been reset
link/ether 66:77:44:22:33:12 brd ff:ff:ff:ff:ff:ff
FidoNet - the internet made simple!
10 - 16 Tiller Road, London, E14 8PX
tel: 0845 004 3050 / fax: 0845 004 3051
I was asked by Idwer to look into this. Since the patch was code reviewed
already I have just some comments:
1) does it work if IMC is disabled?
If not, we should first detect if IMC firmware is active.
2) it writes to reserved bits 7:1
This should be easy fix
3) is there a way to release it back after writes are done?
Alternative way would be to send "go to IDLE/ram command to firmware.
I am using Parted Magic Live CD operation system in my laptop.
I want only *READ *information and use command in Konsole: "flashrom -r
ASUS.def.iso -p internal:this_is_not_laptop >> error.txt"
I have get this error file:
flashrom v0.9.6.1-r1564 on Linux 3.7.9-pmagic (i686)
flashrom is free software, get the source code at http://www.flashrom.org
Calibrating delay loop... OK.
Found chipset "Intel HM65".
This chipset is marked as untested. If you are using an up-to-date version
of flashrom *and* were (not) able to successfully update your firmware
then please email a report to flashrom(a)flashrom.org including a verbose
Enabling flash write... WARNING: BIOS region SMM protection is enabled!
WARNING: SPI Configuration Lockdown activated.
FREG0: WARNING: Flash Descriptor region (0x00000000-0x00000fff) is
FREG2: WARNING: Management Engine region (0x00001000-0x0017ffff) is locked.
Please send a verbose log to flashrom(a)flashrom.org if this board is not
Writes have been disabled. You can enforce write support with the
ich_spi_force programmer option, but it will most likely harm your hardware!
If you force flashrom you will get no support if something breaks.
Found Winbond flash chip "W25Q32" (4096 kB, SPI) at physical address
Reading flash... FAILED.
*What is means???*
I have read "Support chipset" in
http://www.flashrom.org/Supported_hardware and saw *"?"* symbol for
Can I read flash in my laptop by your programm (flashrom v0.9.6.1-r1564)?