flashrom March 2013

flashrom@flashrom.org

47 participants
163 discussions

Re: [flashrom] MX25U1635E (on OLPC XO-4 B1) with flashrom r1657
by Stefan Tauner 26 Aug '13

26 Aug '13

On Tue, 19 Mar 2013 16:12:43 +1100 James Cameron <quozl(a)laptop.org> wrote: > G'day, > > I'm an Open Firmware developer working for One Laptop per Child. > > We have used the MX25U3235E chip in revision B1 of our XO-4 design, > and I am trying to use flashrom (r1657) with a Bus Pirate to read from > a chip. > > I see you pushed a patch for this chip in the past few days. A happy > coincidence perhaps. > > Is there anything I can do to help you change TEST_UNTESTED to > something else? > > (Sorry if this is an obvious question, but I have very little > knowledge of flashrom, having used for the first time yesterday with a > different chip. Mostly we program the chip from within Open > Firmware.) > > I changed TEST_UNTESTED to TEST_OK_PR on my system, and captured the > attached logs. > > While the identify worked, the read gave errors, and the output file > contained 0xff only. We have never intentionally enabled any block > protection on this chip. > Hello James, the .tested field is only used for QA and telling the user about it. Changing it does not influence functionality. If you are in a hurry skip this paragraph. :) I am a bit puzzled at the moment regarding the (read) log. If you look at the detailed output of the contents of the status register at line 132 ff. you see that flashrom (mistakenly) reads 0xFF, which leads to the assumption that a block protection is enabled (see bottom of page 26 in the datasheet of the chip; that's quite a standard layout of a SPI flash status register...). It then tries to disable the "protection" and fails because another bit in the status register - the WIP bit - remains at 1. I have no idea why it (always) reads 0xFF from the status register... I have checked the opcode and it is correct, and there is nothing fancy about... apart from one thing I just noticed which you could test: in spi_read_status_register() in spi25_statusreg.c replace 2 with 1 in the array declaration readarr[2] so that this line becomes unsigned char readarr[1]; /* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */ wbsio is our driver for a very annoying winbond SPI master and as the fixme in the function says, this hack should not be in the generic code. If the macronix chip does not repeat the status register contents when one reads more than one byte after sending the RDSR (read status register) opcode (which chips usually do) but 0xFF then we have found the culprit. PS: please send further mails to flashrom(a)flashrom.org - our mailing list, thanks. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[PATCH] Add git support to the Makefile
by Carl-Daniel Hailfinger 21 Aug '13

21 Aug '13

flashrom relies on svn to export tarballs and only prints the last svn revision in the version message even if flashrom is in a git tree. Print extended version information (version, svn revision, git hash, repository URL). Allow exporting from git trees. This should make git users first-class citizens like svn users. Side note: If anyone has an idea how to make the export target more beautiful (80 column limit etc.), please tell me. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-gitfriendly/Makefile =================================================================== --- flashrom-gitfriendly/Makefile (Revision 1145) +++ flashrom-gitfriendly/Makefile (Arbeitskopie) @@ -97,13 +97,15 @@ # of the checked out flashrom files. # Note to packagers: Any tree exported with "make export" or "make tarball" # will not require subversion. The downloadable snapshots are already exported. -SVNVERSION := $(shell LC_ALL=C svnversion -cn . 2>/dev/null | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/" | grep "[0-9]" || LC_ALL=C svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || LC_ALL=C git svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || echo unknown) +SCMVERSION := $(shell LC_ALL=C svnversion -cn . 2>/dev/null | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/" | grep "[0-9]" || LC_ALL=C svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || LC_ALL=C git svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || echo unknown) +SCMEXTVERSION := $(shell LC_ALL=C git rev-parse HEAD 2>/dev/null | sed 's/^./-\0/') +SCMURL := $(shell LC_ALL=C svn info 2>/dev/null | grep URL: | sed 's/.*URL:[[:blank:]]*//' | grep ^. || LC_ALL=C git remote show origin 2>/dev/null |grep URL: | sed 's/.*URL:[[:blank:]]*//' | grep ^. || echo unknown ) RELEASE := 0.9.2 -VERSION := $(RELEASE)-r$(SVNVERSION) +VERSION := $(RELEASE)-r$(SCMVERSION)$(SCMEXTVERSION) RELEASENAME ?= $(VERSION) -SVNDEF := -D'FLASHROM_VERSION="$(VERSION)"' +SCMDEF := -D'FLASHROM_VERSION="$(VERSION)"' -D'FLASHROM_SCMURL="$(SCMURL)"' # Always enable internal/onboard support for now. CONFIG_INTERNAL ?= yes @@ -310,7 +312,7 @@ TAROPTIONS = $(shell LC_ALL=C tar --version|grep -q GNU && echo "--owner=root --group=root") %.o: %.c .features - $(CC) -MMD $(CFLAGS) $(CPPFLAGS) $(FEATURE_CFLAGS) $(SVNDEF) -o $@ -c $< + $(CC) -MMD $(CFLAGS) $(CPPFLAGS) $(FEATURE_CFLAGS) $(SCMDEF) -o $@ -c $< # Make sure to add all names of generated binaries here. # This includes all frontends and libflashrom. @@ -420,9 +422,12 @@ export: @rm -rf $(EXPORTDIR)/flashrom-$(RELEASENAME) - @svn export -r BASE . $(EXPORTDIR)/flashrom-$(RELEASENAME) - @sed "s/^SVNVERSION.*/SVNVERSION := $(SVNVERSION)/" Makefile >$(EXPORTDIR)/flashrom-$(RELEASENAME)/Makefile - @LC_ALL=C svn log >$(EXPORTDIR)/flashrom-$(RELEASENAME)/ChangeLog + @svn export -r BASE . $(EXPORTDIR)/flashrom-$(RELEASENAME) 2>/dev/null || git checkout-index -a -f --prefix=$(EXPORTDIR)/flashrom-$(RELEASENAME)/ + @# If SCMVERSION or SCMEXTVERSION contain a slash or SCMURL contains a hash, this will explode + @sed "s/^SCMVERSION.*/SCMVERSION := $(SCMVERSION)/;s/^SCMEXTVERSION.*/SCMEXTVERSION := $(SCMEXTVERSION)/;s#^SCMURL.*#SCMURL := $(SCMURL)#" Makefile >$(EXPORTDIR)/flashrom-$(RELEASENAME)/Makefile + @# ChangeLog should be in English, but we want UTF-8 for names. + @( LC_ALL=en_US.UTF-8 svn log 2>/dev/null || LC_ALL=en_US.UTF-8 git log 2>/dev/null || echo "Unable to extract log from SCM" ) >$(EXPORTDIR)/flashrom-$(RELEASENAME)/ChangeLog + @rm -f $(EXPORTDIR)/flashrom-$(RELEASENAME)/.gitignore $(EXPORTDIR)/flashrom-$(RELEASENAME)/.gitattributes $(EXPORTDIR)/flashrom-$(RELEASENAME)/.gitmodules @echo Exported $(EXPORTDIR)/flashrom-$(RELEASENAME)/ tarball: export Index: flashrom-gitfriendly/flashrom.c =================================================================== --- flashrom-gitfriendly/flashrom.c (Revision 1145) +++ flashrom-gitfriendly/flashrom.c (Arbeitskopie) @@ -1355,6 +1355,7 @@ void print_version(void) { msg_ginfo("flashrom v%s", flashrom_version); + msg_ginfo(" from " FLASHROM_SCMURL ","); print_sysinfo(); } @@ -1362,7 +1363,6 @@ { msg_ginfo("flashrom is free software, get the source code at " "http://www.flashrom.org\n"); - msg_ginfo("\n"); } int selfcheck(void) -- http://www.hailfinger.org/

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Re: [flashrom] [coreboot] Dualbios on GA-MA770-UD3
by Carl-Daniel Hailfinger 10 Aug '13

10 Aug '13

Hi Vadim, thanks for your mail. I have added the flashrom mailing list in CC: because we should develop a generic way to handle DualBIOS and similar techniques. On 09.04.2010 08:12, Vadim Girlin wrote: > I'm going to try coreboot on Gigabyte GA-MA770-UD3. > It's AMD 770 (RX780 / SB700). > > My motherboard supports hardware dual bios - with two chips on it. > I'm going to try flashing backup chip and boot from it. It seems to be > possible - I've tested it (flashing at least). Chips on this board could > be switched by changing bit 0 at undocumented register EF on LDN 7 of > IT8720. I can use slightly patched flashrom for accessing any chip I > want without any problems. And this is tested many times. > > My idea is to use backup chip for debugging - that always keeps my > chance to reboot from main bios chip. And removes the need for > desoldering etc. > > And second problem is that original bios is checking second chip - and > trying to recover it by flashing the bios from main chip on reboot? > rewriting coreboot. AFAICS this could be solved by including some > signatures etc. It seems to be easy to find out. May be someone is > working on this? > > BTW I can send the patch for flashrom - but I think that with > information I mentioned above somebody could make it much better than my > ugly hack. I hope the regs should be the same for all latest Gigabyte > MBs using IT8720/18 > It would be great if you could send that patch. It will help us make a flashrom design decision that works for all boards with multiple flash chips. By the way, some of us have good contacts at ITE, so we can ask ITE for details about the undocumented registers. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[RFC] Layout handling...
by Carl-Daniel Hailfinger 12 Jul '13

12 Jul '13

Hi, before we change flashrom to work with current layout requirements, we should summarize the features we need/want, and then decide how to handle the individual layout regions internally. Terms: "write strategy" describes a combination of erase+write commands with a given block size, touching some blocks. "read protected" describes a region which can not be read. "write protected" describes a region which can not be written. "write once" describes a region which can be written exactly once in the chip lifetime. If you add a feature to the list, please give it a nickname so we know which feature people are referring to. Some of the features below might not be desirable, but I want to list them anyway so we can explicitly declare them as unsupported if needed. fullwrite-unrestricted: Write a chip-sized image, no special read/write restrictions of the chip, no layout file needs to be specified. Default write case right now. fullwrite-noread: Write a chip-sized image, reading anything from the chip is not possible. Many DVD writers fall in that category. No verification, violates our reliability guarantees. fullwrite-postread: Write a chip-sized image, reading anything from the chip is only possible after write. Chips which are read-locked until a full erase/write fall in that category. Do those exist as standalone flash chips or only integrated into processors? fullwrite-partialread: Write a chip-sized image, reading is only possible in some chip regions. Only partial verification, violates our reliability guarantees. fullwrite-partialwrite: Write a chip-sized image, but writing is only possible in some regions. This is obviously a conflict unless the image has the same contents as the chip in the write-protected regions and there is a possible write strategy for the whole image which does not touch the write-protected regions. Should flashrom always refuse this scenario, or only refuse it in case of conflicts? partialwrite-unrestricted: Write only parts of an image, the rest of the chip contents is kept, no special read/write restrictions. partialwrite-partialread: Write only parts of an image, the rest of the chip contents is kept, reading is only possible in some chip regions. If no read-protected regions are written and a suitable write strategy exists, should flashrom warn? If a read-protected region is written, should flashrom warn/refuse due to reliability requirements? partialwrite-partialwrite: Write only parts of an image, the rest of the chip contents is kept, writing is only possible in some chip regions. If no write-protected regions are written and a suitable write strategy exists, should flashrom warn? flashrom will refuse to write a write-protected region. fullread-unrestricted: Read the full chip, no special read restrictions of the chip. partialread-unrestricted: Read only parts of a chip, no special read restrictions of the chip. partialread-partialread: Read only parts of a chip, some regions are read-protected. flashrom should refuse to read any read-protected regions. partialread-imagefiller: If only parts of a chip are read and the read image has full chip size, what should be used as filler for unread regions? 0x00 or 0xff? partialread-layout-imagesize: If only parts of a chip are read, should the read image still have full chip size with all read regions filled in at the respective locations? partialread-layout-split: If only parts of a chip are read, should it be possible to write each region (or a combination thereof) to a separate image file, and would that mapping be specified in the layout file? partialwrite-layout-split: If only parts of a chip are written, should it be possible to collect each part of the new image from a separate image file, and would that mapping be specified in the layout file? readwrite-protection-time: Which read protection and write protection times exist? Temporary lock until unlock, temporary lock until chip soft reset, temporary lock until chip/programmer hard reset (powerdown or reset line), permanent eternal lock. readwrite-protection-type: Which read protection and write protection types exist? Programmer lock (e.g. Intel SPI), hardware chip lock (WP pin), software chip lock (chip command). readwrite-protection-interaction: How should we express this situation: A region is write-locked with a software chip lock, but to remove that software chip lock, a hardware chip lock has to be disabled first, then the software chip lock can be disabled. partialaccess-crash: Some regions in the chip are really off-limits and will cause an unrecoverable error (system crash) when accessed (read or write). That seems to be the case for some EC/flash interactions. Comments? Any forks of flashrom (e.g. chromium) which need infrastructure features not mentioned above? Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] USB 3 PCI Card support (request to add device)
by Philipp Post 13 Jun '13

13 Jun '13

I have added some flashrom and linux logs which might be helpfull: The USB 3 PCI card has the following system properties: DRIVER=xhci_hcd PCI_CLASS=C0330 PCI_ID=1033:0194 PCI_SUBSYS_ID=1033:0194 PCI_SLOT_NAME=0000:03:00.0 MODALIAS=pci:v00001033d00000194sv00001033sd00000194bc0Csc03i30 There is also a PCI NIC Intel 82541PI Gigabit Ethernet Controller (8086:107c, BDF 02:0a.0) and a PCI soundcard installed. Tried to read the flash rom out of the 82541PI Intel NIC without problems. /sys/bus/pci/devices/0000:02:0a.0 of the Intel NIC also gives access to "rom" which the USB 3 and the soundcard do not. I am not sure if that means that the rom is not accessible at all or if Ubuntu just does not know how. Thanks in advance, brgds Philipp -----Ursprüngliche Nachricht----- Von: Philipp Post [mailto:Post.Philipp@googlemail.com] Gesendet: Donnerstag, 24. Januar 2013 19:23 An: 'flashrom(a)flashrom.org' Betreff: USB 3 PCI Card support (request to add device) Good day, following configuration: - USB 3 PCI (not PCI-Express) card with RENESAS uPD720200A(Revision 4) USB chip and ATMEL AT25F512B (ATMEL 1138, 25F512B, SSH) rom chip in - IBM NetVista 8305 Desktop PC - built year 2003 The issue with the card is that it needs a flash rom update to work with Windows Vista and up, otherwise the device does not work at all in these OS ("device cannot start"). Windows XP with Renesas drivers and Linux Ubuntu 11.3 out of the box works fine. RENESAS has a rom update for the chip and a flash update tool which however does not work with PCI cards, but just chips soldered to mainboards. At least this seems to me the reason why it does not work. Chip is recognized but the RENESAS tool says "Can not load / access firmware". The tool has the option to change the device / vendor id as well via .ini file. The card used is the only PCI USB 3 card on the market and basically works very well when it works - with max PCI speed of course, which means approx. double speed of USB 2. The card exists in hardware version 1 (RENESAS chip uPD720200A) and 2 (RENESAS chip uPD720202). I do just have access to hardware version 1. The name of the manufacturer behind the card is unknown to me, but it could be an ADDONICS product. I do not have a technical drawing of the card and I fear I can not obtain one but I do have the card itself. My question: would it be possible to incorporate this card into flashrom? Would be great if someone could do it as I do not have the necessary skills to do it myself. In case you need further information, please let me know. Thanks in advance, brgds Philipp Links and further reading: -------------------------- Card Information from different sellers (same card): http://www.addonics.com/products/ad2u3pci.php http://eu.startech.com/Cards-Adapters/USB-3.0/Cards/2-Port-PCI-SuperSpeed-US B-3-Card-Adapter~PCIUSB3S2 http://www.lindy.de/premium-usb-3-karte-2-port-pci/51082.html ATMEL rom specification (contains info how to write rom images): www.atmel.com/Images/doc3689.pdf Renesas USB chip information: http://www.renesas.eu/products/soc/usb_assp/product/upd720200a/index.jsp RENESAS rom update 4.0.2.0 with Windows updater (32 + 64 Bit) and drivers: http://www.station-drivers.com/page/renesas.htm We need: "Firmware Version 4.0.2.0 pour uPD720200a" RENESAS MS DOS flash update tool (which did not do the job): http://www.computerbase.de/forum/attachment.php?attachmentid=283282&d=133832 3319 IBM NetVista 8305 Hardware Maintenance Manual: http://download.lenovo.com/ibmdl/pub/pc/pccbbs/netvista_pdf/24p2969.pdf Hardware Ids: Renesas Electronics USB 3.0 Host Controller: PCI\VEN_1033&DEV_0194&SUBSYS_01941033&REV_04\5&25043F3&0&0048F0 Renesas Electronics USB 3.0 Root Hub NUSB3\ROOT_HUB30\6&2D374EF3&2

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mac address problem with nvidia MCP55V-Pro
by Jon Morby 02 Jun '13

02 Jun '13

hi … I don't suppose anyone has any experience updating or fixing MAC addresses on Nvidea nVIDIA MCP55V-Pro (Supermicro H8DMT+) ? Following an experimental reflash everything went well, except afterwards we noticed the mac address had been reset link/ether 66:77:44:22:33:12 brd ff:ff:ff:ff:ff:ff -- Jon Morby FidoNet - the internet made simple! 10 - 16 Tiller Road, London, E14 8PX tel: 0845 004 3050 / fax: 0845 004 3051

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Asrock Fatal1ty Z77 Performance > unsupported - logs attached
by "Jürgen Dorn" 01 Jun '13

01 Jun '13

regards, Jürgen

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Re: [flashrom] AMD - SP5100 - take SPI ownership (1/2)
by Rudolf Marek 24 May '13

24 May '13

Hi all, I was asked by Idwer to look into this. Since the patch was code reviewed already I have just some comments: 1) does it work if IMC is disabled? If not, we should first detect if IMC firmware is active. 2) it writes to reserved bits 7:1 This should be easy fix 3) is there a way to release it back after writes are done? Alternative way would be to send "go to IDLE/ram command to firmware. Thanks Rudolf

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Re: [flashrom] [PATCH] Enable spi clock setting in dediprog driver
by Nico Huber 06 May '13

06 May '13

Rebased this one, following patches are based on it. This adds a programmer parameter 'spispeed' to the dediprog driver to control the transfer rate on the spi bus. The following rates are available (in Hz): 375k, 750k, 1.5M, 2.18M, 3M, 8M, 12M and 24M The original driver reinitializes the programmer after setting the speed, so the initialization calls have moved into a new function dediprog_setup() which is called twice. Signed-off-by: Nico Huber <nico.huber(a)secunet.com> diff --git a/dediprog.c b/dediprog.c index a81cf83..60067a8 100644 --- a/dediprog.c +++ b/dediprog.c @@ -152,7 +152,23 @@ static int dediprog_set_spi_voltage(int millivolt) return 0; } -#if 0 +struct dediprog_spispeeds { + const char *const name; + const int speed; +}; + +static const struct dediprog_spispeeds spispeeds[] = { + { "24M", 0x0 }, + { "12M", 0x2 }, + { "8M", 0x1 }, + { "3M", 0x3 }, + { "2.18M", 0x4 }, + { "1.5M", 0x5 }, + { "750k", 0x6 }, + { "375k", 0x7 }, + { NULL, 0x0 }, +}; + /* After dediprog_set_spi_speed, the original app always calls * dediprog_set_spi_voltage(0) and then * dediprog_check_devicestring() four times in a row. @@ -160,56 +176,20 @@ static int dediprog_set_spi_voltage(int millivolt) * This looks suspiciously like the microprocessor in the SF100 has to be * restarted/reinitialized in case the speed changes. */ -static int dediprog_set_spi_speed(uint16_t speed) +static int dediprog_set_spi_speed(unsigned int spispeed_idx) { int ret; - unsigned int khz; - /* Case 1 and 2 are in weird order. Probably an organically "grown" - * interface. - * Base frequency is 24000 kHz, divisors are (in order) - * 1, 3, 2, 8, 11, 16, 32, 64. - */ - switch (speed) { - case 0x0: - khz = 24000; - break; - case 0x1: - khz = 8000; - break; - case 0x2: - khz = 12000; - break; - case 0x3: - khz = 3000; - break; - case 0x4: - khz = 2180; - break; - case 0x5: - khz = 1500; - break; - case 0x6: - khz = 750; - break; - case 0x7: - khz = 375; - break; - default: - msg_perr("Unknown frequency selector 0x%x! Aborting.\n", speed); - return 1; - } - msg_pdbg("Setting SPI speed to %u kHz\n", khz); + msg_pdbg("SPI speed is %sHz\n", spispeeds[spispeed_idx].name); - ret = usb_control_msg(dediprog_handle, 0x42, 0x61, speed, 0xff, NULL, - 0x0, DEFAULT_TIMEOUT); + ret = usb_control_msg(dediprog_handle, 0x42, 0x61, spispeeds[spispeed_idx].speed, 0xff, + NULL, 0x0, DEFAULT_TIMEOUT); if (ret != 0x0) { - msg_perr("Command Set SPI Speed 0x%x failed!\n", speed); + msg_perr("Command Set SPI Speed 0x%x failed!\n", spispeeds[spispeed_idx].speed); return 1; } return 0; } -#endif /* Bulk read interface, will read multiple 512 byte chunks aligned to 512 bytes. * @start start address @@ -736,6 +716,28 @@ static int parse_voltage(char *voltage) return millivolt; } +static int dediprog_setup(void) +{ + /* URB 6. Command A. */ + if (dediprog_command_a()) { + return 1; + } + /* URB 7. Command A. */ + if (dediprog_command_a()) { + return 1; + } + /* URB 8. Command Prepare Receive Device String. */ + /* URB 9. Command Receive Device String. */ + if (dediprog_check_devicestring()) { + return 1; + } + /* URB 10. Command C. */ + if (dediprog_command_c()) { + return 1; + } + return 0; +} + static const struct spi_programmer spi_programmer_dediprog = { .type = SPI_CONTROLLER_DEDIPROG, .max_data_read = MAX_DATA_UNSPECIFIED, @@ -777,12 +779,21 @@ static int dediprog_shutdown(void *data) int dediprog_init(void) { struct usb_device *dev; - char *voltage; - int millivolt = 3500; - int ret; + char *voltage, *spispeed; + int spispeed_idx = 2, millivolt = 3500; + int i, ret; msg_pspew("%s\n", __func__); + spispeed = extract_programmer_param("spispeed"); + if (spispeed) { + for (i = 0; spispeeds[i].name; ++i) { + if (!strcasecmp(spispeeds[i].name, spispeed)) { + spispeed_idx = i; + break; + } + } + } voltage = extract_programmer_param("voltage"); if (voltage) { millivolt = parse_voltage(voltage); @@ -821,33 +832,26 @@ int dediprog_init(void) return 1; } dediprog_endpoint = 2; - + if (register_shutdown(dediprog_shutdown, NULL)) return 1; dediprog_set_leds(PASS_ON|BUSY_ON|ERROR_ON); - /* URB 6. Command A. */ - if (dediprog_command_a()) { + /* Perform basic setup. */ + if (dediprog_setup()) { dediprog_set_leds(PASS_OFF|BUSY_OFF|ERROR_ON); return 1; } - /* URB 7. Command A. */ - if (dediprog_command_a()) { - dediprog_set_leds(PASS_OFF|BUSY_OFF|ERROR_ON); - return 1; - } - /* URB 8. Command Prepare Receive Device String. */ - /* URB 9. Command Receive Device String. */ - if (dediprog_check_devicestring()) { - dediprog_set_leds(PASS_OFF|BUSY_OFF|ERROR_ON); - return 1; - } - /* URB 10. Command C. */ - if (dediprog_command_c()) { + + /* After setting voltage and speed, perform setup again. */ + if (dediprog_set_spi_voltage(0) || + dediprog_set_spi_speed(spispeed_idx) || + dediprog_setup()) { dediprog_set_leds(PASS_OFF|BUSY_OFF|ERROR_ON); return 1; } + /* URB 11. Command Set SPI Voltage. */ if (dediprog_set_spi_voltage(millivolt)) { dediprog_set_leds(PASS_OFF|BUSY_OFF|ERROR_ON); diff --git a/flashrom.8 b/flashrom.8 index b054c28..99e064e 100644 --- a/flashrom.8 +++ b/flashrom.8 @@ -651,6 +651,18 @@ where can be .BR 0V ", " 1.8V ", " 2.5V ", " 3.5V or the equivalent in mV. +.sp +An optional +.B spispeed +parameter specifies the frequency of the SPI bus. Syntax is +.sp +.B " flashrom \-p dediprog:spispeed=frequency" +.sp +where +.B frequency +can be +.BR 375k ", " 750k ", " 1.5M ", " 2.18M ", " 3M ", " 8M ", " 12M " or " 24M +(in Hz). The default is a frequency of 12 MHz. .SS .BR "rayer_spi " programmer The default I/O base address used for the parallel port is 0x378 and you can use

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Supporting of Intel HM65
by pavel 04 May '13

04 May '13

Hello! I am using Parted Magic Live CD operation system in my laptop. I want only *READ *information and use command in Konsole: "flashrom -r ASUS.def.iso -p internal:this_is_not_laptop >> error.txt" I have get this error file: *** error.txt **** flashrom v0.9.6.1-r1564 on Linux 3.7.9-pmagic (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "Intel HM65". This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... WARNING: BIOS region SMM protection is enabled! WARNING: SPI Configuration Lockdown activated. FREG0: WARNING: Flash Descriptor region (0x00000000-0x00000fff) is read-only. FREG2: WARNING: Management Engine region (0x00001000-0x0017ffff) is locked. Please send a verbose log to flashrom(a)flashrom.org if this board is not listed on http://flashrom.org/Supported_hardware#Supported_mainboards yet. Writes have been disabled. You can enforce write support with the ich_spi_force programmer option, but it will most likely harm your hardware! If you force flashrom you will get no support if something breaks. OK. Found Winbond flash chip "W25Q32" (4096 kB, SPI) at physical address 0xffc00000. Reading flash... FAILED. *** *What is means???* I have read "Support chipset" in http://www.flashrom.org/Supported_hardware and saw *"?"* symbol for *Intel HM65*. Can I read flash in my laptop by your programm (flashrom v0.9.6.1-r1564)? _________________ Pavel Slipenchoock

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flashrom March 2013