flashrom September 2012

flashrom@flashrom.org

32 participants
137 discussions

[PATCH 1/3] Prepare ichspi for check_trans().
by Stefan Tauner 29 Sep '12

29 Sep '12

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flash.h | 1 + ichspi.c | 247 +++++++++++++++++++++++++++++++++++--------------------------- 2 files changed, 142 insertions(+), 106 deletions(-) diff --git a/flash.h b/flash.h index 4913536..3230849 100644 --- a/flash.h +++ b/flash.h @@ -24,6 +24,7 @@ #ifndef __FLASH_H__ #define __FLASH_H__ 1 +#include <stdbool.h> #include <stdint.h> #include <stddef.h> #ifdef _WIN32 diff --git a/… [View More]ichspi.c b/ichspi.c index 8dd1893..142a122 100644 --- a/ichspi.c +++ b/ichspi.c @@ -370,66 +370,60 @@ static void prettyprint_ich9_reg_ssfc(uint32_t reg_val) pprint_reg(SSFC, SCF, reg_val, "\n"); } -static uint8_t lookup_spi_type(uint8_t opcode) +static uint8_t determine_spitype(uint8_t opcode, unsigned int writecnt, unsigned int readcnt) { - int a; - - for (a = 0; a < ARRAY_SIZE(POSSIBLE_OPCODES); a++) { - if (POSSIBLE_OPCODES[a].opcode == opcode) - return POSSIBLE_OPCODES[a].spi_type; + int i; + for (i = 0; i < ARRAY_SIZE(POSSIBLE_OPCODES); i++) { + if (POSSIBLE_OPCODES[i].opcode == opcode) + return POSSIBLE_OPCODES[i].spi_type; } - return 0xFF; + /* Try to guess spi type from read/write sizes. + * The following valid writecnt/readcnt combinations exist: + * writecnt = 4, readcnt >= 0 + * writecnt = 1, readcnt >= 0 + * writecnt >= 4, readcnt = 0 + * writecnt >= 1, readcnt = 0 + * writecnt >= 1 is guaranteed for all commands. + */ + msg_pspew("Need to guess spitype from payload lengths.\n"); + if (readcnt == 0) + /* if readcnt=0 and writecount >= 4, we don't know if it is WRITE_NO_ADDRESS + * or WRITE_WITH_ADDRESS. But if we use WRITE_NO_ADDRESS and the first 3 data + * bytes are actual the address, they go to the bus anyhow + */ + return SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; + else if (writecnt == 1) // and readcnt is > 0 + return SPI_OPCODE_TYPE_READ_NO_ADDRESS; + else if (writecnt == 4) // and readcnt is > 0 + return SPI_OPCODE_TYPE_READ_WITH_ADDRESS; + else // we have an invalid case + return 0xFF; } -static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt) +/* FIXME: check and use return code of program_opcodes*/ +static int reprogram_opcode_on_the_fly(uint8_t opcode, uint8_t spi_type, unsigned int writecnt, unsigned int readcnt) { - uint8_t spi_type; - - spi_type = lookup_spi_type(opcode); - if (spi_type > 3) { - /* Try to guess spi type from read/write sizes. - * The following valid writecnt/readcnt combinations exist: - * writecnt = 4, readcnt >= 0 - * writecnt = 1, readcnt >= 0 - * writecnt >= 4, readcnt = 0 - * writecnt >= 1, readcnt = 0 - * writecnt >= 1 is guaranteed for all commands. - */ - if (readcnt == 0) - /* if readcnt=0 and writecount >= 4, we don't know if it is WRITE_NO_ADDRESS - * or WRITE_WITH_ADDRESS. But if we use WRITE_NO_ADDRESS and the first 3 data - * bytes are actual the address, they go to the bus anyhow - */ - spi_type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; - else if (writecnt == 1) // and readcnt is > 0 - spi_type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; - else if (writecnt == 4) // and readcnt is > 0 - spi_type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - else // we have an invalid case - return SPI_INVALID_LENGTH; - } - int oppos = 2; // use original JEDEC_BE_D8 offset + const int oppos = 2; // use original JEDEC_BE_D8 offset curopcodes->opcode[oppos].opcode = opcode; curopcodes->opcode[oppos].spi_type = spi_type; program_opcodes(curopcodes, 0); - oppos = find_opcode(curopcodes, opcode); msg_pdbg2("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos); - return oppos; + return 0; } static int find_opcode(OPCODES *op, uint8_t opcode) { - int a; + int i; if (op == NULL) { msg_perr("\n%s: null OPCODES pointer!\n", __func__); return -1; } - for (a = 0; a < 8; a++) { - if (op->opcode[a].opcode == opcode) - return a; + for (i = 0; i < 8; i++) { + if (op->opcode[i].opcode == opcode) + return i; } return -1; @@ -505,6 +499,7 @@ static int generate_opcodes(OPCODES * op) return 0; } +/* FIXME: verify */ static int program_opcodes(OPCODES *op, int enable_undo) { uint8_t a; @@ -720,7 +715,7 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, uint32_t temp32; uint16_t temp16; uint64_t opmenu; - int opcode_index; + int oppos; /* Is it a write command? */ if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) @@ -765,17 +760,17 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, opmenu = REGREAD32(ICH7_REG_OPMENU); opmenu |= ((uint64_t)REGREAD32(ICH7_REG_OPMENU + 4)) << 32; - for (opcode_index = 0; opcode_index < 8; opcode_index++) { + for (oppos = 0; oppos < 8; oppos++) { if ((opmenu & 0xff) == op.opcode) { break; } opmenu >>= 8; } - if (opcode_index == 8) { + if (oppos == 8) { msg_pdbg("Opcode %x not found.\n", op.opcode); return 1; } - temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4; + temp16 |= ((uint16_t) (oppos & 0x07)) << 4; timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ /* Handle Atomic. Atomic commands include three steps: @@ -837,7 +832,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, int timeout; uint32_t temp32; uint64_t opmenu; - int opcode_index; + int oppos; /* Is it a write command? */ if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) @@ -887,17 +882,17 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, opmenu = REGREAD32(ICH9_REG_OPMENU); opmenu |= ((uint64_t)REGREAD32(ICH9_REG_OPMENU + 4)) << 32; - for (opcode_index = 0; opcode_index < 8; opcode_index++) { + for (oppos = 0; oppos < 8; oppos++) { if ((opmenu & 0xff) == op.opcode) { break; } opmenu >>= 8; } - if (opcode_index == 8) { + if (oppos == 8) { msg_pdbg("Opcode %x not found.\n", op.opcode); return 1; } - temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4); + temp32 |= ((uint32_t) (oppos & 0x07)) << (8 + 4); timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ /* Handle Atomic. Atomic commands include three steps: @@ -982,36 +977,56 @@ static int run_opcode(const struct flashctx *flash, OPCODE op, uint32_t offset, } } -static int ich_spi_send_command(struct flashctx *flash, unsigned int writecnt, - unsigned int readcnt, - const unsigned char *writearr, - unsigned char *readarr) +/* flag offsets of prepare_opcode */ +#define ICH_DRYRUN 0 +static int prepare_opcode(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, uint8_t flags, OPCODE **op); + +/* Check command and prepare the appropriate opcode. + * The selected OPCODE will be returned by opcodep if it can be determined. + * If the dryrun flag is set, try do determine opcode sanity and availability only, do not change hw state + * (i.e. do not touch OPMENU). In that case opcodep is undefined. + * Returns 0 on success, or SPI_INVALID_* if the command would not work on this board. */ +static int prepare_opcode(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, uint8_t flags, OPCODE **opcodep) { - int result; - int opcode_index = -1; - const unsigned char cmd = *writearr; - OPCODE *opcode; - uint32_t addr = 0; - uint8_t *data; - int count; + OPCODE *opcode = NULL; + OPCODE emu_op = {0}; + bool dryrun = (flags & (1 << ICH_DRYRUN)); + if (writecnt == 0) + return SPI_INVALID_LENGTH; - /* find cmd in opcodes-table */ - opcode_index = find_opcode(curopcodes, cmd); - if (opcode_index == -1) { - if (!ichspi_lock) - opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt); - if (opcode_index == SPI_INVALID_LENGTH) { - msg_pdbg("OPCODE 0x%02x has unsupported length, will not execute.\n", cmd); + /* ensure that the requested opcode is available */ + int oppos = find_opcode(curopcodes, writearr[0]); + if (oppos >= 0) { + opcode = &(curopcodes->opcode[oppos]); + } else { + uint8_t spi_type = determine_spitype(writearr[0], writecnt, readcnt); + if (spi_type == 0xFF) { + if (!dryrun) + msg_pdbg("Could not determine spitype for opcode 0x%02x.\n", writearr[0]); return SPI_INVALID_LENGTH; - } else if (opcode_index == -1) { - msg_pdbg("Invalid OPCODE 0x%02x, will not execute.\n", - cmd); + } + if (ichspi_lock) { + if (!dryrun) + msg_pdbg("OPCODES locked down and do not contain 0x%02x, can not execute.\n", + writearr[0]); return SPI_INVALID_OPCODE; + } else { + /* In a dryrun we expect that reprogramming works successfully, but we need to create + * an OPCODE object for the tests below. */ + if (dryrun) { + emu_op.opcode = writearr[0]; + emu_op.spi_type = spi_type; + opcode = &emu_op; + } else { + reprogram_opcode_on_the_fly(writearr[0], spi_type, writecnt, readcnt); + oppos = find_opcode(curopcodes, writearr[0]); + opcode = &(curopcodes->opcode[oppos]); + } } } - opcode = &(curopcodes->opcode[opcode_index]); - /* The following valid writecnt/readcnt combinations exist: * writecnt = 4, readcnt >= 0 * writecnt = 1, readcnt >= 0 @@ -1019,49 +1034,66 @@ static int ich_spi_send_command(struct flashctx *flash, unsigned int writecnt, * writecnt >= 1, readcnt = 0 * writecnt >= 1 is guaranteed for all commands. */ - if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) && - (writecnt != 4)) { - msg_perr("%s: Internal command size error for opcode " - "0x%02x, got writecnt=%i, want =4\n", __func__, cmd, - writecnt); + if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) && (writecnt != 4)) { + if (!dryrun) + msg_perr("%s: Internal command size error for opcode 0x%02x, got writecnt=%i, want =4\n", + __func__, writearr[0], writecnt); return SPI_INVALID_LENGTH; } - if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_NO_ADDRESS) && - (writecnt != 1)) { - msg_perr("%s: Internal command size error for opcode " - "0x%02x, got writecnt=%i, want =1\n", __func__, cmd, - writecnt); + if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_NO_ADDRESS) && (writecnt != 1)) { + if (!dryrun) + msg_perr("%s: Internal command size error for opcode 0x%02x, got writecnt=%i, want =1\n", + __func__, writearr[0], writecnt); return SPI_INVALID_LENGTH; } - if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) && - (writecnt < 4)) { - msg_perr("%s: Internal command size error for opcode " - "0x%02x, got writecnt=%i, want >=4\n", __func__, cmd, - writecnt); + if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) && (writecnt < 4)) { + if (!dryrun) + msg_perr("%s: Internal command size error for opcode 0x%02x, got writecnt=%i, want >=4\n", + __func__, writearr[0], writecnt); return SPI_INVALID_LENGTH; } if (((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) || (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) && (readcnt)) { - msg_perr("%s: Internal command size error for opcode " - "0x%02x, got readcnt=%i, want =0\n", __func__, cmd, - readcnt); + if (!dryrun) + msg_perr("%s: Internal command size error for opcode 0x%02x, got readcnt=%i, want =0\n", + __func__, writearr[0], readcnt); return SPI_INVALID_LENGTH; } - /* if opcode-type requires an address */ + /* if opcode-type requires an address we check if it is below the allowed base. */ if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS || opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { - addr = (writearr[1] << 16) | - (writearr[2] << 8) | (writearr[3] << 0); + uint32_t addr = (writearr[1] << 16) | (writearr[2] << 8) | (writearr[3] << 0); if (addr < ichspi_bbar) { - msg_perr("%s: Address 0x%06x below allowed " - "range 0x%06x-0xffffff\n", __func__, - addr, ichspi_bbar); + msg_perr("%s: Address 0x%06x below allowed range 0x%06x-0xffffff\n", + __func__, addr, ichspi_bbar); return SPI_INVALID_ADDRESS; } } + if (opcodep != NULL) + *opcodep = opcode; + return 0; +} + +static int ich_spi_send_command(struct flashctx *flash, unsigned int writecnt, + unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + OPCODE *opcode; + uint32_t addr; + uint8_t *data; + int count; + + int result = prepare_opcode(flash, writecnt, readcnt, writearr, (0 << ICH_DRYRUN), &opcode); + if (result != 0) { + msg_pspew("%s called with an unsupported transaction layout: readcnt = %d, writecnt = %d.\n", + __func__, readcnt, writecnt); + return result; + } + /* Translate read/write array/count. * The maximum data length is identical for the maximum read length and * for the maximum write length excluding opcode and address. Opcode and @@ -1080,6 +1112,7 @@ static int ich_spi_send_command(struct flashctx *flash, unsigned int writecnt, count = readcnt; } + addr = (writearr[1] << 16) | (writearr[2] << 8) | (writearr[3] << 0); result = run_opcode(flash, *opcode, addr, count, data); if (result) { msg_pdbg("Running OPCODE 0x%02x failed ", opcode->opcode); @@ -1358,17 +1391,17 @@ static int ich_hwseq_write(struct flashctx *flash, uint8_t *buf, return 0; } -static int ich_spi_send_multicommand(struct flashctx *flash, - struct spi_command *cmds) +static int ich_spi_send_multicommand(struct flashctx *flash, struct spi_command *cmds) { int ret = 0; int i; int oppos, preoppos; for (; (cmds->writecnt || cmds->readcnt) && !ret; cmds++) { - if ((cmds + 1)->writecnt || (cmds + 1)->readcnt) { + struct spi_command *cmd_nxt = cmds + 1; + if (cmd_nxt->writecnt || cmd_nxt->readcnt) { /* Next command is valid. */ preoppos = find_preop(curopcodes, cmds->writearr[0]); - oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]); + oppos = find_opcode(curopcodes, cmd_nxt->writearr[0]); if ((oppos == -1) && (preoppos != -1)) { /* Current command is listed as preopcode in * ICH struct OPCODES, but next command is not @@ -1376,13 +1409,10 @@ static int ich_spi_send_multicommand(struct flashctx *flash, * Check for command sanity, then * try to reprogram the ICH opcode list. */ - if (find_preop(curopcodes, - (cmds + 1)->writearr[0]) != -1) { - msg_perr("%s: Two subsequent " - "preopcodes 0x%02x and 0x%02x, " + if (find_preop(curopcodes, cmd_nxt->writearr[0]) != -1) { + msg_perr("%s: Two subsequent preopcodes 0x%02x and 0x%02x, " "ignoring the first.\n", - __func__, cmds->writearr[0], - (cmds + 1)->writearr[0]); + __func__, cmds->writearr[0], cmd_nxt->writearr[0]); continue; } /* If the chipset is locked down, we'll fail @@ -1390,7 +1420,12 @@ static int ich_spi_send_multicommand(struct flashctx *flash, * No need to bother with fixups. */ if (!ichspi_lock) { - oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt); + uint8_t spi_type = determine_spitype(cmd_nxt->writearr[0], cmd_nxt->writecnt, cmd_nxt->readcnt); + if (spi_type == 0xFF) { + msg_pdbg("Could not determine spitype for opcode 0x%02x.\n", cmd_nxt->writearr[0]); + return SPI_INVALID_LENGTH; + } + oppos = reprogram_opcode_on_the_fly(cmd_nxt->writearr[0], spi_type, cmd_nxt->writecnt, cmd_nxt->readcnt); if (oppos == -1) continue; curopcodes->opcode[oppos].atomic = preoppos + 1; -- Kind regards, Stefan Tauner [View Less]

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[PATCH 0/3] Add a function to determine the availability of SPI commands on a programmer
by Stefan Tauner 29 Sep '12

29 Sep '12

This is just a preview, but maybe someone want to take a look at it over the weekend. This will be useful to automatically determine working payload sizes on awkward programmers. It is also a good idea to separate the checking from actual hardware state changes IMHO. And the ICH code regarding opcodes should be refactored anyway :) I would welcome any verbose probe logs, especially on the more awkward programmers like wbsio, it87, sb600 etc. Stefan Tauner (3): Prepare ichspi for check_trans(… [View More]

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Re: [flashrom] flashrom -V result for an MSI K9N6SGM-V
by Stefan Tauner 28 Sep '12

28 Sep '12

On Fri, 28 Sep 2012 15:10:05 +0200 "PoLyOpAtH [2.5Go GmAiL]" <polyo.path(a)gmail.com> wrote: > Hi, > Here is the result of "flashrom -V --programmer internal" command with an > MSI K9N6SGM-V motherboard for a BIOS flashing. > > Thanks for your help. Hi! Thanks for the log. Your board uses a superio chip that is not supported by flashrom yet. Carl-Daniel is working on a patch for it, but it does (or should) only detect that chip at the moment - it does not enable read or … [View More]

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flashrom -V result for an MSI K9N6SGM-V
by PoLyOpAtH [2.5Go GmAiL] 28 Sep '12

28 Sep '12

Hi, Here is the result of "flashrom -V --programmer internal" command with an MSI K9N6SGM-V motherboard for a BIOS flashing. Thanks for your help.

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[commit] r1606 - trunk
by repository service 26 Sep '12

26 Sep '12

Author: stefanct Date: Tue Sep 25 23:08:41 2012 New Revision: 1606 URL: http://flashrom.org/trac/flashrom/changeset/1606 Log: Whitelist known working Thinkpads of the T60 and X60 series. This should get rid of the need to specify the laptop force parameter on T60 and X60 series Thinkpads (including T60s and X60s) that are using one of the Intel 94x northbridges and are known to have no interfering EC. Please note that although the EC is no problem, flashrom is not able to access the entire … [View More]flash chip with the vendor BIOS, see the coreboot wiki for details: http://www.coreboot.org/Lenovo_x60x Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Modified: trunk/board_enable.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Mon Sep 24 23:29:29 2012 (r1605) +++ trunk/board_enable.c Tue Sep 25 23:08:41 2012 (r1606) @@ -2243,6 +2243,17 @@ return 0; } +/* + * Suited for all laptops, which are known to *not* have interfering embedded controllers. + */ +static int p2_whitelist_laptop(void) +{ + is_laptop = 1; + laptop_ok = 1; + msg_pdbg("Whitelisted laptop detected.\n"); + return 0; +} + #endif /* @@ -2396,6 +2407,8 @@ {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, P3, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower}, {0x1022, 0x7468, 0, 0, 0x1022, 0x7460, 0, 0, NULL, "iwill", "dk8_htx", P3, "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e}, {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", P3, "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m}, + {0x8086, 0x27a0, 0x17aa, 0x2017, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "Lenovo", "T60(s)", 0, OK, p2_whitelist_laptop}, + {0x8086, 0x27a0, 0x17aa, 0x2017, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad X60", NULL, NULL, P2, "Lenovo", "X60(s)", 0, OK, p2_whitelist_laptop}, {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, P3, "Mitac", "6513WU", 0, OK, board_mitac_6513wu}, {0x8086, 0x8186, 0x8086, 0x8186, 0x8086, 0x8800, 0x0000, 0x0000, "^MSC Vertriebs GmbH$", NULL, NULL, P2, "MSC", "Q7-TCTC", 0, OK, p2_not_a_laptop}, {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, P3, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, /* TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html. */ [View Less]

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ASRock ALiveNF6G-DVI: flashrom -V
by Gregor Hoffleit 26 Sep '12

26 Sep '12

flashrom v0.9.5.2-r1546 on Linux 3.2.0-3-686-pae (i686) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.9, GCC 4.7.1, little endian Command line (1 args): flashrom -V Calibrating delay loop... OS timer resolution is 2 usecs, 498M loops per second, 10 myus = 12 us, 100 myus = 101 us, 1000 myus = 1011 us, 10000 myus = 9946 us, 8 myus = 9 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "… [View More]To Be Filled By O.E.M." DMI string system-product-name: "To Be Filled By O.E.M." DMI string system-version: "To Be Filled By O.E.M." DMI string baseboard-manufacturer: " " DMI string baseboard-product-name: "ALiveNF6G-DVI" DMI string baseboard-version: " " DMI string chassis-type: "Desktop" Found Winbond Super I/O, id 88 Found chipset "NVIDIA MCP61" with PCI ID 10de:03e0. Enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 Flash bus type is LPC Found SMBus device 10de:03eb at 00:01:1 MCP SPI BAR is at 0x00000000 MCP SPI is not used. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. The following protocols are supported: LPC. Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xda, id2 0x54 Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xc9, id2 0xd9, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xda, id2 0x54 Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xda, id2 0x54 Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xda, id2 0x54 Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xda, id2 0x54 Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xda, id2 0x54 Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xda, id2 0x54 Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xda, id2 0x54 Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xda, id2 0x54 Found Winbond flash chip "W39V040B" (512 kB, LPC) at physical address 0xfff80000. Lockout bits: Hardware bootblock locking (#TBL) is not active. Hardware remaining chip locking (#WP) is not active.. Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xda, id2 0x54 Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xda, id2 0x54 Found Winbond flash chip "W39V040B" (512 kB, LPC). No operations were specified. Restoring PCI config space for 00:01:0 reg 0x90 Restoring PCI config space for 00:01:0 reg 0x8c Restoring PCI config space for 00:01:0 reg 0x88 [View Less]

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Re: [flashrom] [PATCH 3/3] Cleanup ft2322.c
by Stefan Tauner 26 Sep '12

26 Sep '12

On Tue, 4 Sep 2012 01:53:47 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> refined, self-acked and committed in r1610 -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH 2/3] Add support for FT232H.
by Stefan Tauner 26 Sep '12

26 Sep '12

On Tue, 4 Sep 2012 01:53:46 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > For older versions of libftdi we define TYPE_232H ourselves and this > seems to be enough to get at least basic support. > > Signed-off-by: Ilya A. Volynets-Evenbakh <ilya(a)total-knowledge.com> > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> self-acked and committed in r1609. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1610 - trunk
by repository service 26 Sep '12

26 Sep '12

Author: stefanct Date: Wed Sep 26 02:48:16 2012 New Revision: 1610 URL: http://flashrom.org/trac/flashrom/changeset/1610 Log: Cleanup ft2322.c and add more detail to error messages. - Use libftdi's error string to add more detail. - Add full stops to messages. - Minor white space fixes. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/ft2232_spi.c Modified: trunk/ft2232_spi.c … [View More]============================================================================== --- trunk/ft2232_spi.c Wed Sep 26 02:47:09 2012 (r1609) +++ trunk/ft2232_spi.c Wed Sep 26 02:48:16 2012 (r1610) @@ -64,8 +64,7 @@ {FTDI_VID, TIAO_TUMPA_PID, OK, "TIAO", "USB Multi-Protocol Adapter"}, {FTDI_VID, AMONTEC_JTAGKEY_PID, OK, "Amontec", "JTAGkey"}, {GOEPEL_VID, GOEPEL_PICOTAP_PID, OK, "GOEPEL", "PicoTAP"}, - {FIC_VID, OPENMOKO_DBGBOARD_PID, OK, "FIC", - "OpenMoko Neo1973 Debug board (V2+)"}, + {FIC_VID, OPENMOKO_DBGBOARD_PID, OK, "FIC", "OpenMoko Neo1973 Debug board (V2+)"}, {OLIMEX_VID, OLIMEX_ARM_OCD_PID, NT, "Olimex", "ARM-USB-OCD"}, {OLIMEX_VID, OLIMEX_ARM_TINY_PID, OK, "Olimex", "ARM-USB-TINY"}, {OLIMEX_VID, OLIMEX_ARM_OCD_H_PID, NT, "Olimex", "ARM-USB-OCD-H"}, @@ -74,7 +73,6 @@ {0}, }; - #define DEFAULT_DIVISOR 2 #define BITMODE_BITBANG_NORMAL 1 @@ -96,8 +94,7 @@ { int i; for (i = 0; devs_ft2232spi[i].vendor_name != NULL; i++) { - if ((devs_ft2232spi[i].device_id == ft2232_type) - && (devs_ft2232spi[i].vendor_id == ft2232_vid)) + if ((devs_ft2232spi[i].device_id == ft2232_type) && (devs_ft2232spi[i].vendor_id == ft2232_vid)) return devs_ft2232spi[i].device_name; } return "unknown device"; @@ -107,8 +104,7 @@ { int i; for (i = 0; devs_ft2232spi[i].vendor_name != NULL; i++) { - if ((devs_ft2232spi[i].device_id == ft2232_type) - && (devs_ft2232spi[i].vendor_id == ft2232_vid)) + if ((devs_ft2232spi[i].device_id == ft2232_type) && (devs_ft2232spi[i].vendor_id == ft2232_vid)) return devs_ft2232spi[i].vendor_name; } return "unknown vendor"; @@ -120,8 +116,7 @@ int r; r = ftdi_write_data(ftdic, (unsigned char *) buf, size); if (r < 0) { - msg_perr("ftdi_write_data: %d, %s\n", r, - ftdi_get_error_string(ftdic)); + msg_perr("ftdi_write_data: %d, %s\n", r, ftdi_get_error_string(ftdic)); return 1; } return 0; @@ -135,8 +130,7 @@ while (size > 0) { r = ftdi_read_data(ftdic, (unsigned char *) buf, size); if (r < 0) { - msg_perr("ftdi_read_data: %d, %s\n", r, - ftdi_get_error_string(ftdic)); + msg_perr("ftdi_read_data: %d, %s\n", r, ftdi_get_error_string(ftdic)); return 1; } buf += r; @@ -251,6 +245,7 @@ } } free(arg); + arg = extract_programmer_param("port"); if (arg) { switch (toupper((unsigned char)*arg)) { @@ -299,21 +294,22 @@ } } free(arg); + msg_pdbg("Using device type %s %s ", get_ft2232_vendorname(ft2232_vid, ft2232_type), get_ft2232_devicename(ft2232_vid, ft2232_type)); - msg_pdbg("channel %s\n", + msg_pdbg("channel %s.\n", (ft2232_interface == INTERFACE_A) ? "A" : (ft2232_interface == INTERFACE_B) ? "B" : (ft2232_interface == INTERFACE_C) ? "C" : "D"); if (ftdi_init(ftdic) < 0) { - msg_perr("ftdi_init failed\n"); + msg_perr("ftdi_init failed.\n"); return -3; } if (ftdi_set_interface(ftdic, ft2232_interface) < 0) { - msg_perr("Unable to select channel: %s\n", ftdic->error_str); + msg_perr("Unable to select channel (%s).\n", ftdi_get_error_string(ftdic)); } arg = extract_programmer_param("serial"); @@ -321,31 +317,29 @@ free(arg); if (f < 0 && f != -5) { - msg_perr("Unable to open FTDI device: %d (%s)\n", f, - ftdi_get_error_string(ftdic)); + msg_perr("Unable to open FTDI device: %d (%s).\n", f, ftdi_get_error_string(ftdic)); return -4; } if (ftdic->type != TYPE_2232H && ftdic->type != TYPE_4232H && ftdic->type != TYPE_232H) { - msg_pdbg("FTDI chip type %d is not high-speed\n", - ftdic->type); + msg_pdbg("FTDI chip type %d is not high-speed.\n", ftdic->type); clock_5x = 0; } if (ftdi_usb_reset(ftdic) < 0) { - msg_perr("Unable to reset FTDI device\n"); + msg_perr("Unable to reset FTDI device (%s).\n", ftdi_get_error_string(ftdic)); } if (ftdi_set_latency_timer(ftdic, 2) < 0) { - msg_perr("Unable to set latency timer\n"); + msg_perr("Unable to set latency timer (%s).\n", ftdi_get_error_string(ftdic)); } if (ftdi_write_data_set_chunksize(ftdic, 256)) { - msg_perr("Unable to set chunk size\n"); + msg_perr("Unable to set chunk size (%s).\n", ftdi_get_error_string(ftdic)); } if (ftdi_set_bitmode(ftdic, 0x00, BITMODE_BITBANG_SPI) < 0) { - msg_perr("Unable to set bitmode to SPI\n"); + msg_perr("Unable to set bitmode to SPI (%s).\n", ftdi_get_error_string(ftdic)); } if (clock_5x) { @@ -389,18 +383,14 @@ goto ftdi_err; } - // msg_pdbg("\nft2232 chosen\n"); - register_spi_programmer(&spi_programmer_ft2232); return 0; ftdi_err: if ((f = ftdi_usb_close(ftdic)) < 0) { - msg_perr("Unable to close FTDI device: %d (%s)\n", f, - ftdi_get_error_string(ftdic)); + msg_perr("Unable to close FTDI device: %d (%s)\n", f, ftdi_get_error_string(ftdic)); } - return ret; } [View Less]

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Re: [flashrom] [PATCH 1/3] Add support for all 4 possible channels to the ft2232_spi programmer.
by Stefan Tauner 26 Sep '12

26 Sep '12

On Tue, 4 Sep 2012 01:53:45 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > Add a check to validate the selected channel/interface, which not even > libftdi seems to do yet. > This patch changes default behavior: the new default channel/interface is A. > Also, this patch uses the word 'channel' in addition or in place of 'interface' > where possible without too much hassle because it is the term FTDI uses. > > Signed-off-by: Stefan Tauner <… [View More]

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flashrom September 2012