flashrom July 2012

flashrom@flashrom.org

38 participants
156 discussions

Re: [flashrom] [coreboot] Dualbios on GA-MA770-UD3

by Carl-Daniel Hailfinger

Hi Vadim, thanks for your mail. I have added the flashrom mailing list in CC: because we should develop a generic way to handle DualBIOS and similar techniques. On 09.04.2010 08:12, Vadim Girlin wrote: > I'm going to try coreboot on Gigabyte GA-MA770-UD3. > It's AMD 770 (RX780 / SB700). > > My motherboard supports hardware dual bios - with two chips on it. > I'm going to try flashing backup chip and boot from it. It seems to be > possible - I've tested it (flashing at least). Chips on this board could > be switched by changing bit 0 at undocumented register EF on LDN 7 of > IT8720. I can use slightly patched flashrom for accessing any chip I > want without any problems. And this is tested many times. > > My idea is to use backup chip for debugging - that always keeps my > chance to reboot from main bios chip. And removes the need for > desoldering etc. > > And second problem is that original bios is checking second chip - and > trying to recover it by flashing the bios from main chip on reboot? > rewriting coreboot. AFAICS this could be solved by including some > signatures etc. It seems to be easy to find out. May be someone is > working on this? > > BTW I can send the patch for flashrom - but I think that with > information I mentioned above somebody could make it much better than my > ugly hack. I hope the regs should be the same for all latest Gigabyte > MBs using IT8720/18 > It would be great if you could send that patch. It will help us make a flashrom design decision that works for all boards with multiple flash chips. By the way, some of us have good contacts at ITE, so we can ask ITE for details about the undocumented registers. Regards, Carl-Daniel -- http://www.hailfinger.org/

7 years, 1 month

[RFC] Layout handling...

by Carl-Daniel Hailfinger

Hi, before we change flashrom to work with current layout requirements, we should summarize the features we need/want, and then decide how to handle the individual layout regions internally. Terms: "write strategy" describes a combination of erase+write commands with a given block size, touching some blocks. "read protected" describes a region which can not be read. "write protected" describes a region which can not be written. "write once" describes a region which can be written exactly once in the chip lifetime. If you add a feature to the list, please give it a nickname so we know which feature people are referring to. Some of the features below might not be desirable, but I want to list them anyway so we can explicitly declare them as unsupported if needed. fullwrite-unrestricted: Write a chip-sized image, no special read/write restrictions of the chip, no layout file needs to be specified. Default write case right now. fullwrite-noread: Write a chip-sized image, reading anything from the chip is not possible. Many DVD writers fall in that category. No verification, violates our reliability guarantees. fullwrite-postread: Write a chip-sized image, reading anything from the chip is only possible after write. Chips which are read-locked until a full erase/write fall in that category. Do those exist as standalone flash chips or only integrated into processors? fullwrite-partialread: Write a chip-sized image, reading is only possible in some chip regions. Only partial verification, violates our reliability guarantees. fullwrite-partialwrite: Write a chip-sized image, but writing is only possible in some regions. This is obviously a conflict unless the image has the same contents as the chip in the write-protected regions and there is a possible write strategy for the whole image which does not touch the write-protected regions. Should flashrom always refuse this scenario, or only refuse it in case of conflicts? partialwrite-unrestricted: Write only parts of an image, the rest of the chip contents is kept, no special read/write restrictions. partialwrite-partialread: Write only parts of an image, the rest of the chip contents is kept, reading is only possible in some chip regions. If no read-protected regions are written and a suitable write strategy exists, should flashrom warn? If a read-protected region is written, should flashrom warn/refuse due to reliability requirements? partialwrite-partialwrite: Write only parts of an image, the rest of the chip contents is kept, writing is only possible in some chip regions. If no write-protected regions are written and a suitable write strategy exists, should flashrom warn? flashrom will refuse to write a write-protected region. fullread-unrestricted: Read the full chip, no special read restrictions of the chip. partialread-unrestricted: Read only parts of a chip, no special read restrictions of the chip. partialread-partialread: Read only parts of a chip, some regions are read-protected. flashrom should refuse to read any read-protected regions. partialread-imagefiller: If only parts of a chip are read and the read image has full chip size, what should be used as filler for unread regions? 0x00 or 0xff? partialread-layout-imagesize: If only parts of a chip are read, should the read image still have full chip size with all read regions filled in at the respective locations? partialread-layout-split: If only parts of a chip are read, should it be possible to write each region (or a combination thereof) to a separate image file, and would that mapping be specified in the layout file? partialwrite-layout-split: If only parts of a chip are written, should it be possible to collect each part of the new image from a separate image file, and would that mapping be specified in the layout file? readwrite-protection-time: Which read protection and write protection times exist? Temporary lock until unlock, temporary lock until chip soft reset, temporary lock until chip/programmer hard reset (powerdown or reset line), permanent eternal lock. readwrite-protection-type: Which read protection and write protection types exist? Programmer lock (e.g. Intel SPI), hardware chip lock (WP pin), software chip lock (chip command). readwrite-protection-interaction: How should we express this situation: A region is write-locked with a software chip lock, but to remove that software chip lock, a hardware chip lock has to be disabled first, then the software chip lock can be disabled. partialaccess-crash: Some regions in the chip are really off-limits and will cause an unrecoverable error (system crash) when accessed (read or write). That seems to be the case for some EC/flash interactions. Comments? Any forks of flashrom (e.g. chromium) which need infrastructure features not mentioned above? Regards, Carl-Daniel -- http://www.hailfinger.org/

7 years, 2 months

flashrom -p gfxnvidia detect my atheros ath9k wifi card

by Denis 'GNUtoo' Carikli

Hi, Here are the logs: # ./flashrom -p gfxnvidia -VVV flashrom v0.9.5.2-r1546 on Linux 3.0.0-19-generic-pae (i686) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.1.7, GCC 4.6.1, little endian Command line (3 args): ./flashrom -p gfxnvidia -VVV Calibrating delay loop... OS timer resolution is 1 usecs, 1503M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1000 us, 10000 myus = 10007 us, 4 myus = 4 us, OK. Initializing gfxnvidia programmer Found "NVIDIA RIVA TNT2 Ultra" (168c:0029, BDF 03:06.0). PCI header type 0x00 Requested BAR is MEM, 32bit, not prefetchable === This PCI device is UNTESTED. Please report the 'flashrom -p xxxx' output to flashrom(a)flashrom.org if it works for you. Please add the name of your PCI device to the subject. Thank you for your help! === Detected NVIDIA I/O base address: 0xd8600000. The following protocols are supported: Parallel. Probing for AMD Am29F010A/B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BB, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV001BT, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BB, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV002BT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BB, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV004BT, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BB, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV008BT, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C512, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C010A, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C040A, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49BV512, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49F002(N), 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49F002(N)T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49F020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49F040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Catalyst CAT28F512, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Bright BM29F040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for EMST F49B002UA, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29LV640B, 8192 kB: probe_en29lv640b: id1 0xffff, id2 0x00ff Probing for Fujitsu MBM29F004BC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Fujitsu MBM29F400TC, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for Hyundai HY29F002T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Hyundai HY29F002B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Hyundai HY29F040A, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BN/BX-B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BN/BX-T, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F002BC/BL/BV/BX-T, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F008S3/S5/SC, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-T, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-T, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002(N)B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002(N)T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51000B, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51000T, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51400B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51400T, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29LC51000, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29LC51001, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29LC51002, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002T, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV512, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LH28F008BJT-BTLZ1, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST28SF040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29LE010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE020A, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29LE020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF512, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF010A, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF020A, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF512, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF010, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF080, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BB, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29F400BT, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff Probing for ST M29W010B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RB, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012-old, 128 kB: Old Winbond W29* probe method disabled because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29C010(M)/W29C011A/W29EE011/W29EE012-old' if you have a board with such a chip. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C020(C)/W29C022, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C040/P, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39L040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U/N, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F020, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. Restoring PCI config space for 03:06:0 reg 0x50 # lspci -n 00:00.0 0600: 1022:9601 00:01.0 0604: 1022:9602 00:0a.0 0604: 1022:9609 00:11.0 0106: 1002:4390 00:12.0 0c03: 1002:4397 00:12.1 0c03: 1002:4398 00:12.2 0c03: 1002:4396 00:13.0 0c03: 1002:4397 00:13.1 0c03: 1002:4398 00:13.2 0c03: 1002:4396 00:14.0 0c05: 1002:4385 (rev 3c) 00:14.1 0101: 1002:439c 00:14.2 0403: 1002:4383 00:14.3 0601: 1002:439d 00:14.4 0604: 1002:4384 00:14.5 0c03: 1002:4399 00:18.0 0600: 1022:1200 00:18.1 0600: 1022:1201 00:18.2 0600: 1022:1202 00:18.3 0600: 1022:1203 00:18.4 0600: 1022:1204 01:05.0 0300: 1002:9710 01:05.1 0403: 1002:970f 02:00.0 0200: 10ec:8168 (rev 03) 03:06.0 0280: 168c:0029 (rev 01) # lspci 00:00.0 Host bridge: Advanced Micro Devices [AMD] RS880 Host Bridge 00:01.0 PCI bridge: Advanced Micro Devices [AMD] RS780/RS880 PCI to PCI bridge (int gfx) 00:0a.0 PCI bridge: Advanced Micro Devices [AMD] RS780/RS880 PCI to PCI bridge (PCIE port 5) 00:11.0 SATA controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 SATA Controller [IDE mode] 00:12.0 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI0 Controller 00:12.1 USB Controller: ATI Technologies Inc SB7x0 USB OHCI1 Controller 00:12.2 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB EHCI Controller 00:13.0 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI0 Controller 00:13.1 USB Controller: ATI Technologies Inc SB7x0 USB OHCI1 Controller 00:13.2 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB EHCI Controller 00:14.0 SMBus: ATI Technologies Inc SBx00 SMBus Controller (rev 3c) 00:14.1 IDE interface: ATI Technologies Inc SB7x0/SB8x0/SB9x0 IDE Controller 00:14.2 Audio device: ATI Technologies Inc SBx00 Azalia (Intel HDA) 00:14.3 ISA bridge: ATI Technologies Inc SB7x0/SB8x0/SB9x0 LPC host controller 00:14.4 PCI bridge: ATI Technologies Inc SBx00 PCI to PCI Bridge 00:14.5 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 00:18.0 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor HyperTransport Configuration 00:18.1 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Address Map 00:18.2 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Miscellaneous Control 00:18.4 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor Link Control 01:05.0 VGA compatible controller: ATI Technologies Inc RS880 [Radeon HD 4200] 01:05.1 Audio device: ATI Technologies Inc RS880 Audio Device [Radeon HD 4200] 02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller (rev 03) 03:06.0 Network controller: Atheros Communications Inc. AR922X Wireless Network Adapter (rev 01) Denis.

7 years, 8 months

[PATCH] remove exit call from pcidev_init

by Niklas Söderlund

If the function fails it returns 0. All callers have been made aware of this and are prepared to handle it. Signed-off-by: Niklas Söderlund <niso(a)kth.se> --- atahpt.c | 2 ++ drkaiser.c | 2 ++ gfxnvidia.c | 2 ++ nic3com.c | 2 ++ nicintel.c | 7 +++---- nicintel_spi.c | 2 ++ nicnatsemi.c | 2 ++ nicrealtek.c | 2 ++ ogp_spi.c | 2 ++ pcidev.c | 6 +++--- satamv.c | 5 ++--- satasii.c | 3 ++- 12 files changed, 26 insertions(+), 11 deletions(-) diff --git a/atahpt.c b/atahpt.c index b692b88..4c1b13e 100644 --- a/atahpt.c +++ b/atahpt.c @@ -71,6 +71,8 @@ int atahpt_init(void) return 1; io_base_addr = pcidev_init(PCI_BASE_ADDRESS_4, ata_hpt); + if (!io_base_addr) + return 1; /* Enable flash access. */ reg32 = pci_read_long(pcidev_dev, REG_FLASH_ACCESS); diff --git a/drkaiser.c b/drkaiser.c index d4b6120..ffabf9b 100644 --- a/drkaiser.c +++ b/drkaiser.c @@ -71,6 +71,8 @@ int drkaiser_init(void) return 1; addr = pcidev_init(PCI_BASE_ADDRESS_2, drkaiser_pcidev); + if (!addr) + return 1; /* Write magic register to enable flash write. */ rpci_write_word(pcidev_dev, PCI_MAGIC_DRKAISER_ADDR, diff --git a/gfxnvidia.c b/gfxnvidia.c index 457172d..fe2362a 100644 --- a/gfxnvidia.c +++ b/gfxnvidia.c @@ -95,6 +95,8 @@ int gfxnvidia_init(void) return 1; io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, gfx_nvidia); + if (!io_base_addr) + return 1; io_base_addr += 0x300000; msg_pinfo("Detected NVIDIA I/O base address: 0x%x.\n", io_base_addr); diff --git a/nic3com.c b/nic3com.c index 4df720f..27d9506 100644 --- a/nic3com.c +++ b/nic3com.c @@ -91,6 +91,8 @@ int nic3com_init(void) return 1; io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_3com); + if (!io_base_addr) + return 1; id = pcidev_dev->device_id; diff --git a/nicintel.c b/nicintel.c index f2d4529..7d6fa94 100644 --- a/nicintel.c +++ b/nicintel.c @@ -77,11 +77,10 @@ int nicintel_init(void) if (get_io_perms()) return 1; - /* No need to check for errors, pcidev_init() will not return in case - * of errors. - * FIXME: BAR2 is not available if the device uses the CardBus function. - */ + /* FIXME: BAR2 is not available if the device uses the CardBus function. */ addr = pcidev_init(PCI_BASE_ADDRESS_2, nics_intel); + if (!addr) + return 1; nicintel_bar = physmap("Intel NIC flash", addr, NICINTEL_MEMMAP_SIZE); if (nicintel_bar == ERROR_PTR) diff --git a/nicintel_spi.c b/nicintel_spi.c index 7eb3af3..af7347b 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -171,6 +171,8 @@ int nicintel_spi_init(void) return 1; io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_intel_spi); + if (!io_base_addr) + return 1; nicintel_spibar = physmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, 4096); diff --git a/nicnatsemi.c b/nicnatsemi.c index c39637a..d16984d 100644 --- a/nicnatsemi.c +++ b/nicnatsemi.c @@ -63,6 +63,8 @@ int nicnatsemi_init(void) return 1; io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_natsemi); + if (!io_base_addr) + return 1; if (register_shutdown(nicnatsemi_shutdown, NULL)) return 1; diff --git a/nicrealtek.c b/nicrealtek.c index f808e06..17a3172 100644 --- a/nicrealtek.c +++ b/nicrealtek.c @@ -65,6 +65,8 @@ int nicrealtek_init(void) return 1; io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_realtek); + if (!io_base_addr) + return 1; if (register_shutdown(nicrealtek_shutdown, NULL)) return 1; diff --git a/ogp_spi.c b/ogp_spi.c index 8502847..dc62d7d 100644 --- a/ogp_spi.c +++ b/ogp_spi.c @@ -132,6 +132,8 @@ int ogp_spi_init(void) return 1; io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, ogp_spi); + if (!io_base_addr) + return 1; ogp_spibar = physmap("OGP registers", io_base_addr, 4096); diff --git a/pcidev.c b/pcidev.c index e8b4dc1..c32027c 100644 --- a/pcidev.c +++ b/pcidev.c @@ -207,7 +207,7 @@ uintptr_t pcidev_init(int bar, const struct pcidev_status *devs) if (pcidev_bdf != NULL) { if ((msg = pci_filter_parse_slot(&filter, pcidev_bdf))) { msg_perr("Error: %s\n", msg); - exit(1); + return 0; } } free(pcidev_bdf); @@ -228,13 +228,13 @@ uintptr_t pcidev_init(int bar, const struct pcidev_status *devs) /* Only continue if exactly one supported PCI dev has been found. */ if (found == 0) { msg_perr("Error: No supported PCI device found.\n"); - exit(1); + return 0; } else if (found > 1) { msg_perr("Error: Multiple supported PCI devices found. " "Use 'flashrom -p xxxx:pci=bb:dd.f' \n" "to explicitly select the card with the given BDF " "(PCI bus, device, function).\n"); - exit(1); + return 0; } return curaddr; diff --git a/satamv.c b/satamv.c index 0b83a14..f23af3b 100644 --- a/satamv.c +++ b/satamv.c @@ -89,10 +89,9 @@ int satamv_init(void) return 1; /* BAR0 has all internal registers memory mapped. */ - /* No need to check for errors, pcidev_init() will not return in case - * of errors. - */ addr = pcidev_init(PCI_BASE_ADDRESS_0, satas_mv); + if (!addr) + return 1; mv_bar = physmap("Marvell 88SX7042 registers", addr, 0x20000); if (mv_bar == ERROR_PTR) diff --git a/satasii.c b/satasii.c index 75378be..ac70129 100644 --- a/satasii.c +++ b/satasii.c @@ -73,7 +73,8 @@ int satasii_init(void) if (get_io_perms()) return 1; - pcidev_init(PCI_BASE_ADDRESS_0, satas_sii); + if (!pcidev_init(PCI_BASE_ADDRESS_0, satas_sii)) + return 1; id = pcidev_dev->device_id; -- 1.7.11.1

7 years, 8 months

[PATCH] Automatic programmer driver writer

by Carl-Daniel Hailfinger

Run ./build_new_driver.sh and recompile. You have a new driver, and it's linked in at the appropriate places. Patch needs work for anything which is not a bitbang SPI driver. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-programmer_template/build_new_driver.sh =================================================================== --- flashrom-programmer_template/build_new_driver.sh (Revision 0) +++ flashrom-programmer_template/build_new_driver.sh (Revision 0) @@ -0,0 +1,232 @@ +#!/bin/bash +# flashrom programmer driver skeleton builder. +# Copyright 2012 Carl-Daniel Hailfinger +# Licensed under the GNU GPL v2 + +# Fill in all info in the block below, and don't touch anything else. +PROGRAMMERNAME=ezo +PROGRAMMERDESCR="EZo+Willem Programmer" +PROGRAMMERMANUF="EZo and Willem" +PROGRAMMERURL="http://www.$PROGRAMMERNAMEflash.com/" +AUTHORNAME="Carl-Daniel Hailfinger" +# Does the programmer need a map/unmap function? +HAVE_MAP=no +# Does the programmer have its own delay function? +HAVE_DELAY=no +# Does the programmer need some sort of direct hardware access? +NEED_PCI=yes +# Does the programmer need some sort of serial port access? +NEED_SERIAL=no +# Does the programmer use Parallel/LPC/FWH functionality? +NEED_PARLPCFWH=no +# Does the programmer use the bitbanging SPI infrastructure? +NEED_BITBANG_SPI=yes + +# No user serviceable parts below. +if test $HAVE_MAP = yes; then MAPNAME=$PROGRAMMERNAME; else MAPNAME=fallback; fi +if test $HAVE_DELAY = yes; then DELAYNAME=$PROGRAMMERNAME; else DELAYNAME=internal; fi +PROGRAMMERNAMECAPS=$(echo -n $PROGRAMMERNAME|tr "[[:lower:]]" "[[:upper:]]") +CONFIGNAME=CONFIG_$PROGRAMMERNAMECAPS +ENUMNAME=PROGRAMMER_$PROGRAMMERNAMECAPS +BITBANG_SPI_ENUMNAME=BITBANG_SPI_MASTER_$PROGRAMMERNAMECAPS +if test $NEED_PCI = yes; then NEEDS="NEED_PCI := yes\n"; fi +if test $NEED_SERIAL = yes; then NEEDS+="NEED_SERIAL := yes\n"; fi + +sed "s-^//PLACEHOLDER_NEWPROG_PROGRAMMER_ARRAY-\ +#if $CONFIGNAME == 1\n\ + {\n\ + .name = \"${PROGRAMMERNAME}\",\n\ + .init = ${PROGRAMMERNAME}_init,\n\ + .map_flash_region = ${MAPNAME}_map,\n\ + .unmap_flash_region = ${MAPNAME}_unmap,\n\ + .delay = ${DELAYNAME}_delay,\n\ + },\n\ +#endif\n\ +\n\0-" flashrom.c >flashrom.c.mine + +sed -e "s/^#PLACEHOLDER_NEWPROG_DEFAULTCONFIG/\ +# Enable $PROGRAMMERDESCR for now.\n\ +$CONFIGNAME ?= yes\n\ +\n\0/" \ +-e "s/^#PLACEHOLDER_NEWPROG_COMPILERULE/\ +ifeq (\$($CONFIGNAME), yes)\n\ +FEATURE_CFLAGS += -D'$CONFIGNAME=1'\n\ +PROGRAMMER_OBJS += $PROGRAMMERNAME.o\n\ +${NEEDS}\ +endif\n\ +\n\0/" Makefile >Makefile.mine1 + +if test $NEED_BITBANG_SPI = yes; then +sed -e "s/^#PLACEHOLDER_NEWPROG_BITBANGSPICONFIG1/\ +ifeq (\$($CONFIGNAME), yes)\n\ +override CONFIG_BITBANG_SPI = yes\n\ +else\n\ +\0/" \ +-e "s/^#PLACEHOLDER_NEWPROG_BITBANGSPICONFIG2/\ +\0\n\ +endif/;" Makefile.mine1 >Makefile.mine +rm Makefile.mine1 +else +mv Makefile.mine1 Makefile.mine +fi + +sed -e "s-^//PLACEHOLDER_NEWPROG_PROGRAMMER_ENUM-\ +#if $CONFIGNAME == 1\n\ + $ENUMNAME,\n\ +#endif\n\ +\0-" \ +-e "s-//PLACEHOLDER_NEWPROG_PUBLICFUNCTIONS-\ +/* $PROGRAMMERNAME.c */\n\ +#if $CONFIGNAME == 1\n\ +int ${PROGRAMMERNAME}_init(void);\n\ +#endif\n\ +\n\0-" programmer.h >programmer.h.mine1 + +if test $NEED_BITBANG_SPI = yes; then +sed -e "s-^//PLACEHOLDER_NEWPROG_PROGRAMMER_BITBANG_ENUM-\ +#if $CONFIGNAME == 1\n\ + $BITBANG_SPI_ENUMNAME,\n\ +#endif\n\ +\0-" \ +-e "s-//PLACEHOLDER_NEWPROG_SELECT_SPI_BITBANG\$-\ +|| $CONFIGNAME == 1 \0-" programmer.h.mine1 >programmer.h.mine +rm programmer.h.mine1 +else +mv programmer.h.mine1 programmer.h.mine +fi + +sed -e "s-PLACEHOLDER_NEWPROG_CHECK_PROGRAMMERCOUNT-\ +$CONFIGNAME+\0-" \ +-e "s-^//PLACEHOLDER_NEWPROG_PROGRAMMER_ENUMDEFAULT-\ +#if $CONFIGNAME == 1\n\ + $ENUMNAME\n\ +#endif\n\ +\0-" cli_classic.c >cli_classic.c.mine + +cat >$PROGRAMMERNAME.c <<EOF +/* + * This file is part of the flashrom project. + * + * Copyright (C) $(date +%Y) $AUTHORNAME + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Driver for the $PROGRAMMERDESCR hardware by $PROGRAMMERMANUF. + * See $PROGRAMMERURL for more info. + */ + +#include "flash.h" +#include "programmer.h" + +EOF + +if test $NEED_PARLPCFWH = yes; then +cat >>$PROGRAMMERNAME.c <<EOF +static const struct par_programmer par_programmer_${PROGRAMMERNAME} = { + .chip_readb = ${PROGRAMMERNAME}_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = ${PROGRAMMERNAME}_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + +EOF +fi + +if test $NEED_BITBANG_SPI = yes; then +cat >>$PROGRAMMERNAME.c <<EOF +static void ${PROGRAMMERNAME}_bitbang_set_cs(int val) +{ + /* Set/clear the CS# line. */ +} + +static void ${PROGRAMMERNAME}_bitbang_set_sck(int val) +{ + /* Set/clear the SCLK line. */ +} + +static void ${PROGRAMMERNAME}_bitbang_set_mosi(int val) +{ + /* Set/clear the MOSI line. */ +} + +static int ${PROGRAMMERNAME}_bitbang_get_miso(void) +{ + /* Get the state of the MISO line and return it. */ + /* Set it to 1 to get the template to compile. */ + int misoval = 0; + + return misoval; +} + +static void ${PROGRAMMERNAME}_request_spibus(void) +{ +} + +static void ${PROGRAMMERNAME}_release_spibus(void) +{ +} + +static const struct bitbang_spi_master bitbang_spi_master_$PROGRAMMERNAME = { + .type = $BITBANG_SPI_ENUMNAME, + .set_cs = ${PROGRAMMERNAME}_bitbang_set_cs, + .set_sck = ${PROGRAMMERNAME}_bitbang_set_sck, + .set_mosi = ${PROGRAMMERNAME}_bitbang_set_mosi, + .get_miso = ${PROGRAMMERNAME}_bitbang_get_miso, + .request_bus = ${PROGRAMMERNAME}_request_spibus, + .release_bus = ${PROGRAMMERNAME}_release_spibus, + .half_period = 1, +}; + +EOF +fi + +cat >>$PROGRAMMERNAME.c <<EOF +static int ${PROGRAMMERNAME}_shutdown(void *data) +{ + /* Shutdown stuff. */ + return 0; +} + +int ${PROGRAMMERNAME}_init(void) +{ + /* Init stuff (i.e. parameter parsing) here which does not need to be + * undone. + */ + + /* If your shutdown function takes a parameter, replace NULL with it. */ + register_shutdown(${PROGRAMMERNAME}_shutdown, NULL); + + /* Init stuff which needs to be undone on shutdown. */ + +EOF + +if test $NEED_BITBANG_SPI = yes; then +cat >>$PROGRAMMERNAME.c <<EOF + /* 1 usec halfperiod delay, change as needed. */ + if (bitbang_spi_init(&bitbang_spi_master_${PROGRAMMERNAME})) + return 1; + +EOF +fi + +cat >>$PROGRAMMERNAME.c <<EOF + return 0; +} +EOF + EigenschaftsÃ¤nderungen: flashrom-programmer_template/build_new_driver.sh ___________________________________________________________________ HinzugefÃ¼gt: svn:executable + * Index: flashrom-programmer_template/Makefile =================================================================== --- flashrom-programmer_template/Makefile (Revision 1539) +++ flashrom-programmer_template/Makefile (Arbeitskopie) @@ -344,6 +344,8 @@ # Enable Linux spidev interface by default. We disable it on non-Linux targets. CONFIG_LINUX_SPI ?= yes +#PLACEHOLDER_NEWPROG_DEFAULTCONFIG + # Disable wiki printing by default. It is only useful if you have wiki access. CONFIG_PRINT_WIKI ?= no @@ -363,7 +365,9 @@ ifeq ($(CONFIG_OGP_SPI), yes) override CONFIG_BITBANG_SPI = yes else +#PLACEHOLDER_NEWPROG_BITBANGSPICONFIG1 CONFIG_BITBANG_SPI ?= no +#PLACEHOLDER_NEWPROG_BITBANGSPICONFIG2 endif endif endif @@ -503,6 +507,8 @@ PROGRAMMER_OBJS += linux_spi.o endif +#PLACEHOLDER_NEWPROG_COMPILERULE + ifeq ($(NEED_SERIAL), yes) LIB_OBJS += serial.o endif Index: flashrom-programmer_template/cli_classic.c =================================================================== --- flashrom-programmer_template/cli_classic.c (Revision 1539) +++ flashrom-programmer_template/cli_classic.c (Arbeitskopie) @@ -41,7 +41,7 @@ * if more than one of them is selected. If only one is selected, it is clear * that the user wants that one to become the default. */ -#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG+CONFIG_RAYER_SPI+CONFIG_NICINTEL+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV > 1 +#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG+CONFIG_RAYER_SPI+CONFIG_NICINTEL+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV+PLACEHOLDER_NEWPROG_CHECK_PROGRAMMERCOUNT > 1 #error Please enable either CONFIG_DUMMY or CONFIG_INTERNAL or disable support for all programmers except one. #endif static enum programmer default_programmer = @@ -96,6 +96,7 @@ #if CONFIG_LINUX_SPI == 1 PROGRAMMER_LINUX_SPI #endif +//PLACEHOLDER_NEWPROG_PROGRAMMER_ENUMDEFAULT ; #endif Index: flashrom-programmer_template/flashrom.c =================================================================== --- flashrom-programmer_template/flashrom.c (Revision 1539) +++ flashrom-programmer_template/flashrom.c (Arbeitskopie) @@ -261,6 +261,7 @@ }, #endif +//PLACEHOLDER_NEWPROG_PROGRAMMER_ARRAY {}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; Index: flashrom-programmer_template/programmer.h =================================================================== --- flashrom-programmer_template/programmer.h (Revision 1539) +++ flashrom-programmer_template/programmer.h (Arbeitskopie) @@ -87,6 +87,7 @@ #if CONFIG_LINUX_SPI == 1 PROGRAMMER_LINUX_SPI, #endif +//PLACEHOLDER_NEWPROG_PROGRAMMER_ENUM PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -127,6 +128,7 @@ #if CONFIG_OGP_SPI == 1 BITBANG_SPI_MASTER_OGP, #endif +//PLACEHOLDER_NEWPROG_PROGRAMMER_BITBANG_ENUM }; struct bitbang_spi_master { @@ -461,6 +463,8 @@ int dediprog_init(void); #endif +//PLACEHOLDER_NEWPROG_PUBLICFUNCTIONS + /* flashrom.c */ struct decode_sizes { uint32_t parallel; @@ -505,7 +509,7 @@ #if CONFIG_DEDIPROG == 1 SPI_CONTROLLER_DEDIPROG, #endif -#if CONFIG_OGP_SPI == 1 || CONFIG_NICINTEL_SPI == 1 || CONFIG_RAYER_SPI == 1 || CONFIG_PONY_SPI == 1 || (CONFIG_INTERNAL == 1 && (defined(__i386__) || defined(__x86_64__))) +#if CONFIG_OGP_SPI == 1 || CONFIG_NICINTEL_SPI == 1 || CONFIG_RAYER_SPI == 1 || CONFIG_PONY_SPI == 1 || (CONFIG_INTERNAL == 1 && (defined(__i386__) || defined(__x86_64__))) //PLACEHOLDER_NEWPROG_SELECT_SPI_BITBANG SPI_CONTROLLER_BITBANG, #endif #if CONFIG_LINUX_SPI == 1 -- http://www.hailfinger.org/

7 years, 9 months

Re: [flashrom] [PATCH] automatically round address ranges requested from physmap_common to page boundaries

by Stefan Tauner

On Mon, 30 May 2011 02:45:44 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > this patch also changes the display width of all addresses in physmap.c to 16 hex characters. > > FIXME: what about unmappings? > munmap is safe. > djgpp's __dpmi_free_physical_address_mapping: unknown. > DirectHW's unmap_physical: unknown. > > FIXME: jakllsch suggested using PRIx64 instead of x, because it's more portable FIXME: in the case we can not map and 'mayfail' is true we should return ERROR_PTR instead of ERROR_PTR + diff -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

7 years, 9 months

[PATCH] Add Altera USB Blaster SPI programmer

by James Laird

Adds support for the Altera USB Blaster programming dongle in SPI mode. It has only been tested against a cheap clone ($10, unclear origin), and so is marked as not tested. It should also support several variants which are present on Altera dev boards (PID 6002,6003...), although I believe these are hardwired to their targets. Signed-off-by: James Laird <jhl(a)mafipulation.org> Index: Makefile =================================================================== --- Makefile (revision 1548) +++ Makefile (working copy) @@ -84,7 +84,7 @@ else override CONFIG_SERPROG = no endif -# Dediprog and FT2232 are not supported under DOS (missing USB support). +# Dediprog, FT2232 and USB Blaster are not supported under DOS (missing USB support). ifeq ($(CONFIG_DEDIPROG), yes) UNSUPPORTED_FEATURES += CONFIG_DEDIPROG=yes else @@ -95,7 +95,12 @@ else override CONFIG_FT2232_SPI = no endif +ifeq ($(CONFIG_USBBLASTER_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_USBBLASTER_SPI=yes +else +override CONFIG_USBBLASTER_SPI = no endif +endif # FIXME: Should we check for Cygwin/MSVC as well? ifeq ($(TARGET_OS), MinGW) @@ -196,7 +201,7 @@ else override CONFIG_SERPROG = no endif -# Dediprog and FT2232 are not supported with libpayload (missing libusb support) +# Dediprog, FT2232 and USB Blaster are not supported with libpayload (missing libusb support) ifeq ($(CONFIG_DEDIPROG), yes) UNSUPPORTED_FEATURES += CONFIG_DEDIPROG=yes else @@ -207,7 +212,12 @@ else override CONFIG_FT2232_SPI = no endif +ifeq ($(CONFIG_USBBLASTER_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_USBBLASTER_SPI=yes +else +override CONFIG_USBBLASTER_SPI = no endif +endif ifneq ($(TARGET_OS), Linux) ifeq ($(CONFIG_LINUX_SPI), yes) @@ -344,6 +354,9 @@ # Enable Linux spidev interface by default. We disable it on non-Linux targets. CONFIG_LINUX_SPI ?= yes +# Always enable USB Blaster SPI for now. +CONFIG_USBBLASTER_SPI ?= yes + # Disable wiki printing by default. It is only useful if you have wiki access. CONFIG_PRINT_WIKI ?= no @@ -430,14 +443,31 @@ NEED_PCI := yes endif +# This is a totally ugly hack. +WANT_LIBFTDI := no +HAVE_LIBFTDI := $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && echo "yes") ifeq ($(CONFIG_FT2232_SPI), yes) -FTDILIBS := $(shell pkg-config --libs libftdi 2>/dev/null || printf "%s" "-lftdi -lusb") -# This is a totally ugly hack. -FEATURE_CFLAGS += $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "-D'CONFIG_FT2232_SPI=1'") -FEATURE_LIBS += $(shell LC_ALL=C grep -q "FTDISUPPORT := yes" .features && printf "%s" "$(FTDILIBS)") -PROGRAMMER_OBJS += ft2232_spi.o + WANT_LIBFTDI := yes + ifeq ($(HAVE_LIBFTDI), yes) + FEATURE_CFLAGS += -DCONFIG_FT2232_SPI=1 + PROGRAMMER_OBJS += ft2232_spi.o + endif endif +ifeq ($(CONFIG_USBBLASTER_SPI), yes) + WANT_LIBFTDI := yes + ifeq ($(HAVE_LIBFTDI), yes) + FEATURE_CFLAGS += -DCONFIG_USBBLASTER_SPI=1 + PROGRAMMER_OBJS += usbblaster_spi.o + endif +endif +ifeq ($(WANT_LIBFTDI), yes) + ifeq ($(WANT_LIBFTDI), yes) + FTDILIBS := $(shell pkg-config --libs libftdi 2>/dev/null || printf "%s" "-lftdi -lusb") + FEATURE_LIBS += $(FTDILIBS) + endif +endif + ifeq ($(CONFIG_DUMMY), yes) FEATURE_CFLAGS += -D'CONFIG_DUMMY=1' PROGRAMMER_OBJS += dummyflasher.o @@ -700,7 +730,7 @@ features: compiler @echo "FEATURES := yes" > .features.tmp -ifeq ($(CONFIG_FT2232_SPI), yes) +ifeq ($(WANT_LIBFTDI), yes) @printf "Checking for FTDI support... " @echo "$$FTDI_TEST" > .featuretest.c @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) $(FTDILIBS) $(LIBS) >/dev/null 2>&1 && \ Index: README =================================================================== --- README (revision 1548) +++ README (working copy) @@ -45,8 +45,8 @@ To build flashrom you need to install the following software: * pciutils+libpci (if you want support for mainboard or PCI device flashing) - * libusb (if you want FT2232 or Dediprog support) - * libftdi (if you want FT2232 support) + * libusb (if you want FT2232, Dediprog or USB Blaster support) + * libftdi (if you want FT2232 or USB Blaster support) Linux et al: Index: usbblaster_spi.c =================================================================== --- usbblaster_spi.c (revision 0) +++ usbblaster_spi.c (working copy) @@ -0,0 +1,258 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2012 James Laird <jhl(a)mafipulation.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Device should be connected as per "active serial" mode: + * + * +---------+------+-----------+ + * | SPI | Pin | Altera | + * +---------+------+-----------+ + * | SCLK | 1 | DCLK | + * | GND | 2,10 | GND | + * | VCC | 4 | VCC(TRGT) | + * | MISO | 7 | ASDO | + * | /CS | 8 | nCS | + * | MOSI | 9 | ASDI | + * +---------+------+-----------+ + */ + +#if CONFIG_USBBLASTER_SPI == 1 + +#include <stdio.h> +#include <string.h> +#include <stdlib.h> +#include <ctype.h> +#include "flash.h" +#include "programmer.h" +#include "spi.h" +#include <ftdi.h> + +/* Please keep sorted by vendor ID, then device ID. */ + +#define ALTERA_VID 0x09fb +#define ALTERA_USBBLASTER_PID 0x6001 + +const struct usbdev_status devs_usbblasterspi[] = { + {ALTERA_VID, ALTERA_USBBLASTER_PID, NT, "Altera", "USB Blaster"}, + {}, +}; + +static const struct spi_programmer spi_programmer_usbblaster; + +static struct ftdi_context ftdic; + +// command bytes +#define BIT_BYTE (1<<7) // byte mode (rather than bitbang) +#define BIT_READ (1<<6) // read request + +#define BIT_LED (1<<5) +#define BIT_CS (1<<3) +#define BIT_CLK (1<<0) +#define BIT_TMS (1<<1) + +#define BITS_OTHER 0 + +// The programmer shifts bits in the wrong order for SPI. +static unsigned char reverse[] = { + 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, + 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0, + 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8, + 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8, + 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4, + 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4, + 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec, + 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc, + 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2, + 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2, + 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea, + 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa, + 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6, + 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6, + 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee, + 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe, + 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1, + 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1, + 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9, + 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9, + 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5, + 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5, + 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed, + 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd, + 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3, + 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3, + 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb, + 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb, + 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7, + 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7, + 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef, + 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff +}; + + +/* Returns 0 upon success, a negative number upon errors. */ +int usbblaster_spi_init(void) +{ + if (ftdi_init(&ftdic) < 0) + return -1; + + if (ftdi_usb_open(&ftdic, ALTERA_VID, ALTERA_USBBLASTER_PID) < 0) { + msg_perr("Failed to open USB Blaster: %s\n", ftdic.error_str); + return -1; + } + + if (ftdi_usb_reset(&ftdic) < 0) { + msg_perr("Blaster reset failed\n"); + return -1; + } + + if (ftdi_set_latency_timer(&ftdic, 2) < 0) { + msg_perr("Blaster set latency timer failed\n"); + return -1; + } + + if (ftdi_write_data_set_chunksize(&ftdic, 4096) < 0 || + ftdi_read_data_set_chunksize(&ftdic, 64) < 0) { + msg_perr("Blaster set chunk size failed\n"); + return -1; + } + unsigned char buf[65]; + memset(buf, 0, sizeof(buf)); + buf[sizeof(buf)-1] = BIT_LED | BITS_OTHER | BIT_CS; + if (ftdi_write_data(&ftdic, buf, sizeof(buf)) < 0) { + msg_perr("Blaster reset write failed\n"); + return -1; + } + if (ftdi_read_data(&ftdic, buf, sizeof(buf)) < 0) { + msg_perr("Blaster reset read failed\n"); + return -1; + } + + register_spi_programmer(&spi_programmer_usbblaster); + return 0; +} + +/* Returns 0 upon success, a negative number upon errors. */ +static int usbblaster_spi_send_command(struct flashctx *flash, + unsigned int writecnt, unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + unsigned char cmd; + unsigned char buf[64]; + unsigned char tms_state = 0; + int i; + // assert /CS + cmd = BIT_LED | BITS_OTHER; + if (ftdi_write_data(&ftdic, &cmd, 1) < 0) { + msg_perr("Blaster write failed\n"); + return -1; + } + + + while (writecnt) { + unsigned int n_write = writecnt; + if (n_write > 63) + n_write = 63; + + msg_pspew("writing %d-byte packet\n", n_write); + + cmd = BIT_BYTE | (unsigned char)n_write; + buf[0] = cmd; + for (i=0; i<n_write; i++) { + buf[i+1] = reverse[writearr[i]]; + } + if (ftdi_write_data(&ftdic, buf, n_write+1) < 0) { + msg_perr("Blaster write failed\n"); + return -1; + } + + cmd = BIT_LED | BITS_OTHER | (tms_state ^= BIT_TMS); + if (ftdi_write_data(&ftdic, &cmd, 1) < 0) { + msg_perr("Blaster write failed\n"); + return -1; + } + + writearr += n_write; + writecnt -= n_write; + } + + unsigned int n_readout = readcnt; + while (readcnt) { + unsigned int n_read = readcnt; + if (n_read > 63) + n_read = 63; + + cmd = BIT_BYTE | BIT_READ | (unsigned char)n_read; + buf[0] = cmd; + if (ftdi_write_data(&ftdic, buf, n_read + 1) < 0) { + msg_perr("Blaster write failed\n"); + return -1; + } + + cmd = BIT_LED | BITS_OTHER | (tms_state ^= BIT_TMS); + if (ftdi_write_data(&ftdic, &cmd, 1) < 0) { + msg_perr("Blaster write failed\n"); + return -1; + } + + readcnt -= n_read; + msg_pspew("reading %d-byte packet\n", n_read); + }; + + unsigned int n_read = n_readout; + while (n_read) { + int ret = ftdi_read_data(&ftdic, readarr, n_read); + if (ret < 0) { + msg_perr("Blaster read failed\n"); + return -1; + } + for (i=0; i<ret; i++) { + readarr[i] = reverse[readarr[i]]; + } + n_read -= ret; + readarr += ret; + } + + cmd = BIT_LED | BIT_CS | BITS_OTHER; + if (ftdi_write_data(&ftdic, &cmd, 1) < 0) { + msg_perr("Blaster write failed\n"); + return -1; + } + + cmd = BIT_CS | BITS_OTHER; + if (ftdi_write_data(&ftdic, &cmd, 1) < 0) { + msg_perr("Blaster write failed\n"); + return -1; + } + + return 0; +} + + +static const struct spi_programmer spi_programmer_usbblaster = { + .type = SPI_CONTROLLER_USBBLASTER, + .max_data_read = 4096, + .max_data_write = 256, + .command = usbblaster_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, +}; + +#endif Index: programmer.h =================================================================== --- programmer.h (revision 1548) +++ programmer.h (working copy) @@ -87,6 +87,9 @@ #if CONFIG_LINUX_SPI == 1 PROGRAMMER_LINUX_SPI, #endif +#if CONFIG_USBBLASTER_SPI == 1 + PROGRAMMER_USBBLASTER_SPI, +#endif PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -433,6 +436,11 @@ void print_supported_usbdevs(const struct usbdev_status *devs); #endif +/* usbblaster_spi.c */ +#if CONFIG_USBBLASTER_SPI == 1 +int usbblaster_spi_init(void); +#endif + /* rayer_spi.c */ #if CONFIG_RAYER_SPI == 1 int rayer_spi_init(void); @@ -514,6 +522,9 @@ #if CONFIG_SERPROG == 1 SPI_CONTROLLER_SERPROG, #endif +#if CONFIG_USBBLASTER_SPI == 1 + SPI_CONTROLLER_USBBLASTER, +#endif }; #define MAX_DATA_UNSPECIFIED 0 Index: print.c =================================================================== --- print.c (revision 1548) +++ print.c (working copy) @@ -538,6 +538,12 @@ programmer_table[PROGRAMMER_LINUX_SPI].name); msg_ginfo("Device files /dev/spidev*.*\n"); #endif +#if CONFIG_USBBLASTER_SPI == 1 + msg_ginfo("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_USBBLASTER_SPI].name); + /* FIXME */ + msg_ginfo("Altera USB Blaster cable\n"); +#endif } #if CONFIG_INTERNAL == 1 Index: flashrom.c =================================================================== --- flashrom.c (revision 1548) +++ flashrom.c (working copy) @@ -262,6 +262,16 @@ }, #endif +#if CONFIG_USBBLASTER_SPI == 1 + { + .name = "usbblaster_spi", + .init = usbblaster_spi_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + {}, /* This entry corresponds to PROGRAMMER_INVALID. */ };

7 years, 11 months

Re: [flashrom] [PATCH 1/3] Do not read the flash chip twice in verification mode.

by Carl-Daniel Hailfinger

Am 23.07.2012 15:33 schrieb Stefan Tauner: > Kyösti Mälkki noticed that we unnecessarily read the flash chip twice when > called with --verify. The first one is the mandatory read before everything > (to be able to detect the seriousness of errors), but the second one is not > necessary because we can just use the former for the comparison. Indeed. > This introduces a small output change: previously we printed ERASE or > VERIFY depending on the callee. This special case has been dropped > because it is unnecessary to print it (and wrong for the verification > function to need to know why it is verifying exactly). > If an erase fails we mention that fact explicitly already, similar for verify. I'm not convinced yet. I'll try to compare the failure output with and without this patch before I ack. > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > flash.h | 2 +- > flashrom.c | 86 +++++++++++++++++++++++++++--------------------------------- > jedec.c | 2 +- > 3 files changed, 41 insertions(+), 49 deletions(-) > > diff --git a/flash.h b/flash.h > index d669512..5bb1211 100644 > --- a/flash.h > +++ b/flash.h > @@ -241,7 +241,7 @@ int min(int a, int b); > int max(int a, int b); > void tolower_string(char *str); > char *extract_param(char **haystack, const char *needle, const char *delim); > -int verify_range(struct flashctx *flash, uint8_t *cmpbuf, unsigned int start, unsigned int len, const char *message); > +int verify_range(struct flashctx *flash, uint8_t *cmpbuf, unsigned int start, unsigned int len); > int need_erase(uint8_t *have, uint8_t *want, unsigned int len, enum write_granularity gran); > char *strcat_realloc(char *dest, const char *src); > void print_version(void); > diff --git a/flashrom.c b/flashrom.c > index fc52c4a..70687ff 100644 > --- a/flashrom.c > +++ b/flashrom.c > @@ -548,6 +548,26 @@ static unsigned int count_usable_erasers(const struct flashctx *flash) > return usable_erasefunctions; > } > > +int compare_range(uint8_t *wantbuf, uint8_t *havebuf, unsigned int start, unsigned int len) Make this function static? > +{ > + int ret = 0, failcount = 0; > + unsigned int i; > + for (i = 0; i < len; i++) { > + if (wantbuf[i] != havebuf[i]) { > + /* Only print the first failure. */ > + if (!failcount++) > + msg_cerr("FAILED at 0x%08x! Expected=0x%02x, Found=0x%02x,", > + start + i, wantbuf[i], havebuf[i]); > + } > + } > + if (failcount) { > + msg_cerr(" failed byte count from 0x%08x-0x%08x: 0x%x\n", > + start, start + len - 1, failcount); > + ret = -1; > + } > + return ret; > +} > + > /* start is an offset to the base address of the flash chip */ > int check_erased_range(struct flashctx *flash, unsigned int start, > unsigned int len) > @@ -560,7 +580,7 @@ int check_erased_range(struct flashctx *flash, unsigned int start, > exit(1); > } > memset(cmpbuf, 0xff, len); > - ret = verify_range(flash, cmpbuf, start, len, "ERASE"); > + ret = verify_range(flash, cmpbuf, start, len); > free(cmpbuf); > return ret; > } > @@ -570,15 +590,12 @@ int check_erased_range(struct flashctx *flash, unsigned int start, > * flash content at location start > * @start offset to the base address of the flash chip > * @len length of the verified area > - * @message string to print in the "FAILED" message > * @return 0 for success, -1 for failure > */ > -int verify_range(struct flashctx *flash, uint8_t *cmpbuf, unsigned int start, > - unsigned int len, const char *message) > +int verify_range(struct flashctx *flash, uint8_t *cmpbuf, unsigned int start, unsigned int len) > { > - unsigned int i; > uint8_t *readbuf = malloc(len); > - int ret = 0, failcount = 0; > + int ret = 0; > > if (!len) > goto out_free; > @@ -599,8 +616,6 @@ int verify_range(struct flashctx *flash, uint8_t *cmpbuf, unsigned int start, > ret = -1; > goto out_free; > } > - if (!message) > - message = "VERIFY"; > > ret = flash->read(flash, readbuf, start, len); > if (ret) { > @@ -609,22 +624,7 @@ int verify_range(struct flashctx *flash, uint8_t *cmpbuf, unsigned int start, > return ret; > } > > - for (i = 0; i < len; i++) { > - if (cmpbuf[i] != readbuf[i]) { > - /* Only print the first failure. */ > - if (!failcount++) > - msg_cerr("%s FAILED at 0x%08x! " > - "Expected=0x%02x, Read=0x%02x,", > - message, start + i, cmpbuf[i], > - readbuf[i]); > - } > - } > - if (failcount) { > - msg_cerr(" failed byte count from 0x%08x-0x%08x: 0x%x\n", > - start, start + len - 1, failcount); > - ret = -1; > - } > - > + ret = compare_range(cmpbuf, readbuf, start, len); Good idea to refactor this. > out_free: > free(readbuf); > return ret; > @@ -1060,21 +1060,6 @@ notfound: > return flash - flashchips; > } > > -int verify_flash(struct flashctx *flash, uint8_t *buf) > -{ > - int ret; > - unsigned int total_size = flash->total_size * 1024; > - > - msg_cinfo("Verifying flash... "); > - > - ret = verify_range(flash, buf, 0, total_size, NULL); > - > - if (!ret) > - msg_cinfo("VERIFIED. \n"); > - > - return ret; > -} I believe that this hunk conflicts with some of your layout patches. Maybe not a direct patch hunk conflict, but having a standalone function which verifies the flash chip according to some layout rules is a good thing. I'd keep verify_flash for now. OTOH, the hunk below makes it painfully obvious that the current verify_flash abstraction is not the right abstraction. Two functions compare_all_ranges() defaulting to a full chip range and verify_all_ranges() with similar characteristics would IMHO be a good abstraction, especially in light of the pending improved layout support. > - > int read_buf_from_file(unsigned char *buf, unsigned long size, > const char *filename) > { > @@ -1838,15 +1823,22 @@ int doit(struct flashctx *flash, int force, const char *filename, int read_it, > } > > if (verify_it) { > - /* Work around chips which need some time to calm down. */ > - if (write_it) > + msg_cinfo("Verifying flash... "); > + > + if (write_it) { > + /* Work around chips which need some time to calm down. */ > programmer_delay(1000*1000); > - ret = verify_flash(flash, newcontents); > - /* If we tried to write, and verification now fails, we > - * might have an emergency situation. > - */ > - if (ret && write_it) > - emergency_help_message(); > + ret = verify_range(flash, newcontents, 0, size); > + /* If we tried to write, and verification now fails, we > + * might have an emergency situation. > + */ > + if (ret) > + emergency_help_message(); > + } else { > + ret = compare_range(newcontents, oldcontents, 0, size); > + } > + if (!ret) > + msg_cinfo("VERIFIED.\n"); > } > > out: > diff --git a/jedec.c b/jedec.c > index 69c0c0c..1fa1a10 100644 > --- a/jedec.c > +++ b/jedec.c > @@ -409,7 +409,7 @@ retry: > > dst = d; > src = s; > - failed = verify_range(flash, src, start, page_size, NULL); > + failed = verify_range(flash, src, start, page_size); > > if (failed && tried++ < MAX_REFLASH_TRIES) { > msg_cerr("retrying.\n"); I agree with the direction of the patch, I'm just not yet sure about the implementation. Regards, Carl-Daniel -- http://www.hailfinger.org/

7 years, 11 months

[PATCH] Enable VX855 chipset

by John Schmerge

This patch adds support for the Via VX855 chipset

7 years, 11 months

Re: [flashrom] add Numonyx/Micron N25Q128

by Stefan Tauner

On Sat, 9 Jun 2012 14:51:15 +0200 frederic.temporelli(a)bull.net wrote: > Hello > > > Numonyx/Micron N25Q128 is used on new X9 motherboards from Supermicro (X9DRT, ...) > > Specs are availbale on Micron WWW site: > http://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/S… > > Following patch add this chip to flashrom. Probe is OK. > Due to Manageability Engine, some work is required before being able to test READ/ERASE/WRITE... > > ================================================================================= > Signed-off-by: Frederic Temporelli <frederic.temporelli(a)bull.net> > > diff -urN flashrom-0.9.5.2-r1540/flashchips.c flashrom-0.9.5.2-r1540-n25q128/flashchips.c > --- flashrom-0.9.5.2-r1540/flashchips.c 2012-05-20 23:32:32.000000000 +0000 > +++ flashrom-0.9.5.2-r1540-n25q128/flashchips.c 2012-06-09 14:41:07.064141076 +0000 > @@ -5453,6 +5453,37 @@ > }, > > { > + .vendor = "Numonyx", > + .name = "N25Q128", > + .bustype = BUS_SPI, > + .manufacture_id = ST_ID, > + .model_id = ST_N25Q128, > + .total_size = 16384, > + .page_size = 256, > + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, > + .tested = TEST_OK_PROBE, > + .probe = probe_spi_rdid, > + .probe_timing = TIMING_ZERO, > + .block_erasers = > + { > + { > + .eraseblocks = { {4 * 1024, 4096 } }, > + .block_erase = spi_block_erase_20, > + }, { > + .eraseblocks = { {64 * 1024, 256} }, > + .block_erase = spi_block_erase_d8, > + }, { > + .eraseblocks = { {16 * 1024 * 1024, 1} }, > + .block_erase = spi_block_erase_c7, > + } > + }, > + .unlock = spi_disable_blockprotect, > + .write = spi_chip_write_256, > + .read = spi_chip_read, > + }, > + > + > + { > .vendor = "PMC", > .name = "Pm25LV010", > .bustype = BUS_SPI, > diff -urN flashrom-0.9.5.2-r1540/flashchips.h flashrom-0.9.5.2-r1540-n25q128/flashchips.h > --- flashrom-0.9.5.2-r1540/flashchips.h 2012-05-14 01:51:46.000000000 +0000 > +++ flashrom-0.9.5.2-r1540-n25q128/flashchips.h 2012-06-08 20:46:47.225385676 +0000 > @@ -587,6 +587,7 @@ > #define ST_M29W040B 0xE3 > #define ST_M29W512B 0x27 > #define ST_N25Q064 0xBA17 > +#define ST_N25Q128 0xBA18 /* also Numonyx N25Q128 */ > > #define SYNCMOS_MVC_ID 0x40 /* SyncMOS (SM) and Mosel Vitelic Corporation (MVC) */ > #define MVC_V29C51000T 0x00 > ================================================================================= hello and thanks for your patch! this chip is a bit complicated and we cant merge the patch as it is. they have used the same plane RDID for multiple variants of the chip. some attributes are not important for flashrom and can be ignored, but some are very important, namely the boot sector layout. quote from p.52: > The N25Q128 is available in the following architecture versions: > Bottom version, 64 KB uniform sectors plus 8 bottom boot sectors (each with 16 > subsectors), > Top version, 64 KB uniform sectors plus 8 top boot sectors (each with 16 subsectors) > Uniform version, 64 KB uniform sectors without any boot sectors and subsectors. the good news is that this differences can be detected by an extended RDID command in its 5th byte (1 manufacturer, 2 device, 1 length of the following extended data, the first EDID byte we want), see table 15. of this 5th byte we need to look at the first two bits to determine the architecture, see table 16. our current infrastructure (probe_spi_rdid_generic) cant handle that, but should... so we will plan a change, but please dont expect it to happen too soon. the bad news is that i am not even sure if the subsector erase commands work as flashrom expects. flashrom wants to use the same erase opcode for the hole address space, even for non-uniform layouts. this usually works fine, but afaics it is not specified in the datasheet what happens if one uses the subsector erase opcode on a non-subsector *on devices that actually have subsectors* (the emphasis stems from the fact that it *is* defined, that the subsector erase command is ignore by the uniform model: "Any Subsector Erase (SSE) instruction in devices with uniform architecture (meaning no boot sectors with subsectors) is rejected without having any effects on the device." (p. 98). other interesting bits of this chips: - bit#5 of the status register "is used in conjunction with the Block Protect (BP3, BP2, BP1, BP0) bits to determine if the protected area defined by the Block Protect bits starts from the top or the bottom of the memory array" - a flag status register that gives more info than the "legacy spi status register" - a non-volatile configuration register to configure dummy clock cycles, output driver strength and other stuff, and a volatile register that overrides the nvm settings the first two points can be somewhat ignored by us, the generic "write 0 to the status register" is good enough to unlock the device. regarding the ME: are you aware of my layout patches, that enable read, erase and verify on user-definable address ranges? see the patches from 2011-12-25 at http://patchwork.coreboot.org/project/flashrom/list/ -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

7 years, 11 months

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flashrom July 2012