Hi Vadim,
thanks for your mail. I have added the flashrom mailing list in CC:
because we should develop a generic way to handle DualBIOS and similar
techniques.
On 09.04.2010 08:12, Vadim Girlin wrote:
> I'm going to try coreboot on Gigabyte GA-MA770-UD3.
> It's AMD 770 (RX780 / SB700).
>
> My motherboard supports hardware dual bios - with two chips on it.
> I'm going to try flashing backup chip and boot from it. It seems to be
> possible - I've tested it (flashing at least). Chips on this board could
> be switched by changing bit 0 at undocumented register EF on LDN 7 of
> IT8720. I can use slightly patched flashrom for accessing any chip I
> want without any problems. And this is tested many times.
>
> My idea is to use backup chip for debugging - that always keeps my
> chance to reboot from main bios chip. And removes the need for
> desoldering etc.
>
> And second problem is that original bios is checking second chip - and
> trying to recover it by flashing the bios from main chip on reboot?
> rewriting coreboot. AFAICS this could be solved by including some
> signatures etc. It seems to be easy to find out. May be someone is
> working on this?
>
> BTW I can send the patch for flashrom - but I think that with
> information I mentioned above somebody could make it much better than my
> ugly hack. I hope the regs should be the same for all latest Gigabyte
> MBs using IT8720/18
>
It would be great if you could send that patch. It will help us make a
flashrom design decision that works for all boards with multiple flash
chips.
By the way, some of us have good contacts at ITE, so we can ask ITE for
details about the undocumented registers.
Regards,
Carl-Daniel
--
http://www.hailfinger.org/
Hi,
before we change flashrom to work with current layout requirements, we
should summarize the features we need/want, and then decide how to
handle the individual layout regions internally.
Terms:
"write strategy" describes a combination of erase+write commands with a
given block size, touching some blocks.
"read protected" describes a region which can not be read.
"write protected" describes a region which can not be written.
"write once" describes a region which can be written exactly once in the
chip lifetime.
If you add a feature to the list, please give it a nickname so we know
which feature people are referring to. Some of the features below might
not be desirable, but I want to list them anyway so we can explicitly
declare them as unsupported if needed.
fullwrite-unrestricted: Write a chip-sized image, no special read/write
restrictions of the chip, no layout file needs to be specified. Default
write case right now.
fullwrite-noread: Write a chip-sized image, reading anything from the
chip is not possible. Many DVD writers fall in that category. No
verification, violates our reliability guarantees.
fullwrite-postread: Write a chip-sized image, reading anything from the
chip is only possible after write. Chips which are read-locked until a
full erase/write fall in that category. Do those exist as standalone
flash chips or only integrated into processors?
fullwrite-partialread: Write a chip-sized image, reading is only
possible in some chip regions. Only partial verification, violates our
reliability guarantees.
fullwrite-partialwrite: Write a chip-sized image, but writing is only
possible in some regions. This is obviously a conflict unless the image
has the same contents as the chip in the write-protected regions and
there is a possible write strategy for the whole image which does not
touch the write-protected regions. Should flashrom always refuse this
scenario, or only refuse it in case of conflicts?
partialwrite-unrestricted: Write only parts of an image, the rest of the
chip contents is kept, no special read/write restrictions.
partialwrite-partialread: Write only parts of an image, the rest of the
chip contents is kept, reading is only possible in some chip regions. If
no read-protected regions are written and a suitable write strategy
exists, should flashrom warn? If a read-protected region is written,
should flashrom warn/refuse due to reliability requirements?
partialwrite-partialwrite: Write only parts of an image, the rest of the
chip contents is kept, writing is only possible in some chip regions. If
no write-protected regions are written and a suitable write strategy
exists, should flashrom warn? flashrom will refuse to write a
write-protected region.
fullread-unrestricted: Read the full chip, no special read restrictions
of the chip.
partialread-unrestricted: Read only parts of a chip, no special read
restrictions of the chip.
partialread-partialread: Read only parts of a chip, some regions are
read-protected. flashrom should refuse to read any read-protected regions.
partialread-imagefiller: If only parts of a chip are read and the read
image has full chip size, what should be used as filler for unread
regions? 0x00 or 0xff?
partialread-layout-imagesize: If only parts of a chip are read, should
the read image still have full chip size with all read regions filled in
at the respective locations?
partialread-layout-split: If only parts of a chip are read, should it be
possible to write each region (or a combination thereof) to a separate
image file, and would that mapping be specified in the layout file?
partialwrite-layout-split: If only parts of a chip are written, should
it be possible to collect each part of the new image from a separate
image file, and would that mapping be specified in the layout file?
readwrite-protection-time: Which read protection and write protection
times exist? Temporary lock until unlock, temporary lock until chip soft
reset, temporary lock until chip/programmer hard reset (powerdown or
reset line), permanent eternal lock.
readwrite-protection-type: Which read protection and write protection
types exist? Programmer lock (e.g. Intel SPI), hardware chip lock (WP
pin), software chip lock (chip command).
readwrite-protection-interaction: How should we express this situation:
A region is write-locked with a software chip lock, but to remove that
software chip lock, a hardware chip lock has to be disabled first, then
the software chip lock can be disabled.
partialaccess-crash: Some regions in the chip are really off-limits and
will cause an unrecoverable error (system crash) when accessed (read or
write). That seems to be the case for some EC/flash interactions.
Comments? Any forks of flashrom (e.g. chromium) which need
infrastructure features not mentioned above?
Regards,
Carl-Daniel
--
http://www.hailfinger.org/
Hi,
Here are the logs:
# ./flashrom -p gfxnvidia -VVV
flashrom v0.9.5.2-r1546 on Linux 3.0.0-19-generic-pae (i686)
flashrom is free software, get the source code at
http://www.flashrom.org
flashrom was built with libpci 3.1.7, GCC 4.6.1, little endian
Command line (3 args): ./flashrom -p gfxnvidia -VVV
Calibrating delay loop... OS timer resolution is 1 usecs, 1503M loops
per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1000 us,
10000 myus = 10007 us, 4 myus = 4 us, OK.
Initializing gfxnvidia programmer
Found "NVIDIA RIVA TNT2 Ultra" (168c:0029, BDF 03:06.0).
PCI header type 0x00
Requested BAR is MEM, 32bit, not prefetchable
===
This PCI device is UNTESTED. Please report the 'flashrom -p xxxx'
output
to flashrom(a)flashrom.org if it works for you. Please add the name of
your
PCI device to the subject. Thank you for your help!
===
Detected NVIDIA I/O base address: 0xd8600000.
The following protocols are supported: Parallel.
Probing for AMD Am29F010A/B, 128 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for AMD Am29F002(N)BB, 256 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for AMD Am29F002(N)BT, 256 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for AMD Am29F016D, 2048 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for AMD Am29F040B, 512 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for AMD Am29F080B, 1024 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for AMD Am29LV001BB, 128 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for AMD Am29LV001BT, 128 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for AMD Am29LV002BB, 256 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for AMD Am29LV002BT, 256 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for AMD Am29LV004BB, 512 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for AMD Am29LV004BT, 512 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for AMD Am29LV008BB, 1024 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for AMD Am29LV008BT, 1024 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for AMD Am29LV040B, 512 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for AMD Am29LV081B, 1024 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for AMIC A29002B, 256 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for AMIC A29002T, 256 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for AMIC A29040B, 512 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Atmel AT29C512, 64 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Atmel AT29C010A, 128 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Atmel AT29C020, 256 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Atmel AT29C040A, 512 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Atmel AT49BV512, 64 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Atmel AT49F002(N), 256 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Atmel AT49F002(N)T, 256 kB: probe_jedec_common: id1 0xff,
id2 0xff, id1 parity violation, id1 is normal flash content, id2 is
normal flash content
Probing for Atmel AT49F020, 256 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Atmel AT49F040, 512 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Catalyst CAT28F512, 64 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Bright BM29F040, 512 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for EMST F49B002UA, 256 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Eon EN29F010, 128 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Eon EN29F002(A)(N)B, 256 kB: probe_jedec_common: id1 0xff,
id2 0xff, id1 parity violation, id1 is normal flash content, id2 is
normal flash content
Probing for Eon EN29F002(A)(N)T, 256 kB: probe_jedec_common: id1 0xff,
id2 0xff, id1 parity violation, id1 is normal flash content, id2 is
normal flash content
Probing for Eon EN29LV640B, 8192 kB: probe_en29lv640b: id1 0xffff, id2
0x00ff
Probing for Fujitsu MBM29F004BC, 512 kB: probe_jedec_common: id1 0xff,
id2 0xff, id1 parity violation, id1 is normal flash content, id2 is
normal flash content
Probing for Fujitsu MBM29F004TC, 512 kB: probe_jedec_common: id1 0xff,
id2 0xff, id1 parity violation, id1 is normal flash content, id2 is
normal flash content
Probing for Fujitsu MBM29F400BC, 512 kB: probe_m29f400bt: id1 0xff, id2
0xff
Probing for Fujitsu MBM29F400TC, 512 kB: probe_m29f400bt: id1 0xff, id2
0xff
Probing for Hyundai HY29F002T, 256 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Hyundai HY29F002B, 256 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Hyundai HY29F040A, 512 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Intel 28F001BN/BX-B, 128 kB: probe_jedec_common: id1 0xff,
id2 0xff, id1 parity violation, id1 is normal flash content, id2 is
normal flash content
Probing for Intel 28F001BN/BX-T, 128 kB: probe_jedec_common: id1 0xff,
id2 0xff, id1 parity violation, id1 is normal flash content, id2 is
normal flash content
Probing for Intel 28F002BC/BL/BV/BX-T, 256 kB: probe_82802ab: id1 0xff,
id2 0xff, id1 parity violation, id1 is normal flash content, id2 is
normal flash content
Probing for Intel 28F008S3/S5/SC, 512 kB: probe_82802ab: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Intel 28F004B5/BE/BV/BX-B, 512 kB: probe_82802ab: id1 0xff,
id2 0xff, id1 parity violation, id1 is normal flash content, id2 is
normal flash content
Probing for Intel 28F004B5/BE/BV/BX-T, 512 kB: probe_82802ab: id1 0xff,
id2 0xff, id1 parity violation, id1 is normal flash content, id2 is
normal flash content
Probing for Intel 28F400BV/BX/CE/CV-B, 512 kB: probe_82802ab: id1 0xff,
id2 0xff, id1 parity violation, id1 is normal flash content, id2 is
normal flash content
Probing for Intel 28F400BV/BX/CE/CV-T, 512 kB: probe_82802ab: id1 0xff,
id2 0xff, id1 parity violation, id1 is normal flash content, id2 is
normal flash content
Probing for Macronix MX29F001B, 128 kB: probe_jedec_common: id1 0xff,
id2 0xff, id1 parity violation, id1 is normal flash content, id2 is
normal flash content
Probing for Macronix MX29F001T, 128 kB: probe_jedec_common: id1 0xff,
id2 0xff, id1 parity violation, id1 is normal flash content, id2 is
normal flash content
Probing for Macronix MX29F002(N)B, 256 kB: probe_jedec_common: id1 0xff,
id2 0xff, id1 parity violation, id1 is normal flash content, id2 is
normal flash content
Probing for Macronix MX29F002(N)T, 256 kB: probe_jedec_common: id1 0xff,
id2 0xff, id1 parity violation, id1 is normal flash content, id2 is
normal flash content
Probing for Macronix MX29F040, 512 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Macronix MX29LV040, 512 kB: probe_jedec_common: id1 0xff,
id2 0xff, id1 parity violation, id1 is normal flash content, id2 is
normal flash content
Probing for MoselVitelic V29C51000B, 64 kB: probe_jedec_common: id1
0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2
is normal flash content
Probing for MoselVitelic V29C51000T, 64 kB: probe_jedec_common: id1
0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2
is normal flash content
Probing for MoselVitelic V29C51400B, 512 kB: probe_jedec_common: id1
0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2
is normal flash content
Probing for MoselVitelic V29C51400T, 512 kB: probe_jedec_common: id1
0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2
is normal flash content
Probing for MoselVitelic V29LC51000, 64 kB: probe_jedec_common: id1
0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2
is normal flash content
Probing for MoselVitelic V29LC51001, 128 kB: probe_jedec_common: id1
0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2
is normal flash content
Probing for MoselVitelic V29LC51002, 256 kB: probe_jedec_common: id1
0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2
is normal flash content
Probing for PMC Pm29F002T, 256 kB: Chip lacks correct probe timing
information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for PMC Pm29F002B, 256 kB: Chip lacks correct probe timing
information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for PMC Pm39LV010, 128 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for PMC Pm39LV020, 256 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for PMC Pm39LV040, 512 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for PMC Pm39LV512, 64 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Sharp LH28F008BJT-BTLZ1, 1024 kB: probe_82802ab: id1 0xff,
id2 0xff, id1 parity violation, id1 is normal flash content, id2 is
normal flash content
Probing for SST SST28SF040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for SST SST29EE010, 128 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST29LE010, 128 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST29EE020A, 256 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST29LE020, 256 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST39SF512, 64 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST39SF010A, 128 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST39SF020A, 256 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST39SF040, 512 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST39VF512, 64 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST39VF010, 128 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST39VF020, 256 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST39VF040, 512 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for SST SST39VF080, 1024 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for ST M29F002B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for ST M29F002T/NT, 256 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for ST M29F040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for ST M29F400BB, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff
Probing for ST M29F400BT, 512 kB: probe_m29f400bt: id1 0xff, id2 0xff
Probing for ST M29W010B, 128 kB: probe_jedec_common: id1 0xff, id2 0xff,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for ST M29W040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for ST M29W512B, 64 kB: probe_jedec_common: id1 0xff, id2 0xff,
id1 parity violation, id1 is normal flash content, id2 is normal flash
content
Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 kB:
probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is
normal flash content, id2 is normal flash content
Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 kB:
probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is
normal flash content, id2 is normal flash content
Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 kB:
probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is
normal flash content, id2 is normal flash content
Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 kB:
probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is
normal flash content, id2 is normal flash content
Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 kB:
probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is
normal flash content, id2 is normal flash content
Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 kB:
probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is
normal flash content, id2 is normal flash content
Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 kB:
probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is
normal flash content, id2 is normal flash content
Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 kB:
probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is
normal flash content, id2 is normal flash content
Probing for TI TMS29F002RB, 256 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for TI TMS29F002RT, 256 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012-old, 128 kB:
Old Winbond W29* probe method disabled because the probing sequence puts
the AMIC A49LF040A in a funky state. Use 'flashrom -c
W29C010(M)/W29C011A/W29EE011/W29EE012-old' if you have a board with such
a chip.
Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 kB:
probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is
normal flash content, id2 is normal flash content
Probing for Winbond W29C020(C)/W29C022, 256 kB: probe_jedec_common: id1
0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2
is normal flash content
Probing for Winbond W29C040/P, 512 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Winbond W39L040, 512 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
Probing for Winbond W49F002U/N, 256 kB: probe_jedec_common: id1 0xff,
id2 0xff, id1 parity violation, id1 is normal flash content, id2 is
normal flash content
Probing for Winbond W49F020, 256 kB: probe_jedec_common: id1 0xff, id2
0xff, id1 parity violation, id1 is normal flash content, id2 is normal
flash content
No EEPROM/flash device found.
Note: flashrom can never write if the flash chip isn't found
automatically.
Restoring PCI config space for 03:06:0 reg 0x50
# lspci -n
00:00.0 0600: 1022:9601
00:01.0 0604: 1022:9602
00:0a.0 0604: 1022:9609
00:11.0 0106: 1002:4390
00:12.0 0c03: 1002:4397
00:12.1 0c03: 1002:4398
00:12.2 0c03: 1002:4396
00:13.0 0c03: 1002:4397
00:13.1 0c03: 1002:4398
00:13.2 0c03: 1002:4396
00:14.0 0c05: 1002:4385 (rev 3c)
00:14.1 0101: 1002:439c
00:14.2 0403: 1002:4383
00:14.3 0601: 1002:439d
00:14.4 0604: 1002:4384
00:14.5 0c03: 1002:4399
00:18.0 0600: 1022:1200
00:18.1 0600: 1022:1201
00:18.2 0600: 1022:1202
00:18.3 0600: 1022:1203
00:18.4 0600: 1022:1204
01:05.0 0300: 1002:9710
01:05.1 0403: 1002:970f
02:00.0 0200: 10ec:8168 (rev 03)
03:06.0 0280: 168c:0029 (rev 01)
# lspci
00:00.0 Host bridge: Advanced Micro Devices [AMD] RS880 Host Bridge
00:01.0 PCI bridge: Advanced Micro Devices [AMD] RS780/RS880 PCI to PCI
bridge (int gfx)
00:0a.0 PCI bridge: Advanced Micro Devices [AMD] RS780/RS880 PCI to PCI
bridge (PCIE port 5)
00:11.0 SATA controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 SATA
Controller [IDE mode]
00:12.0 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI0
Controller
00:12.1 USB Controller: ATI Technologies Inc SB7x0 USB OHCI1 Controller
00:12.2 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB EHCI
Controller
00:13.0 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI0
Controller
00:13.1 USB Controller: ATI Technologies Inc SB7x0 USB OHCI1 Controller
00:13.2 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB EHCI
Controller
00:14.0 SMBus: ATI Technologies Inc SBx00 SMBus Controller (rev 3c)
00:14.1 IDE interface: ATI Technologies Inc SB7x0/SB8x0/SB9x0 IDE
Controller
00:14.2 Audio device: ATI Technologies Inc SBx00 Azalia (Intel HDA)
00:14.3 ISA bridge: ATI Technologies Inc SB7x0/SB8x0/SB9x0 LPC host
controller
00:14.4 PCI bridge: ATI Technologies Inc SBx00 PCI to PCI Bridge
00:14.5 USB Controller: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI2
Controller
00:18.0 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor
HyperTransport Configuration
00:18.1 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor
Address Map
00:18.2 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor
DRAM Controller
00:18.3 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor
Miscellaneous Control
00:18.4 Host bridge: Advanced Micro Devices [AMD] Family 10h Processor
Link Control
01:05.0 VGA compatible controller: ATI Technologies Inc RS880 [Radeon HD
4200]
01:05.1 Audio device: ATI Technologies Inc RS880 Audio Device [Radeon HD
4200]
02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd.
RTL8111/8168B PCI Express Gigabit Ethernet controller (rev 03)
03:06.0 Network controller: Atheros Communications Inc. AR922X Wireless
Network Adapter (rev 01)
Denis.
Run ./build_new_driver.sh and recompile. You have a new driver, and it's
linked in at the appropriate places. Patch needs work for anything which
is not a bitbang SPI driver.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>
Index: flashrom-programmer_template/build_new_driver.sh
===================================================================
--- flashrom-programmer_template/build_new_driver.sh (Revision 0)
+++ flashrom-programmer_template/build_new_driver.sh (Revision 0)
@@ -0,0 +1,232 @@
+#!/bin/bash
+# flashrom programmer driver skeleton builder.
+# Copyright 2012 Carl-Daniel Hailfinger
+# Licensed under the GNU GPL v2
+
+# Fill in all info in the block below, and don't touch anything else.
+PROGRAMMERNAME=ezo
+PROGRAMMERDESCR="EZo+Willem Programmer"
+PROGRAMMERMANUF="EZo and Willem"
+PROGRAMMERURL="http://www.$PROGRAMMERNAMEflash.com/"
+AUTHORNAME="Carl-Daniel Hailfinger"
+# Does the programmer need a map/unmap function?
+HAVE_MAP=no
+# Does the programmer have its own delay function?
+HAVE_DELAY=no
+# Does the programmer need some sort of direct hardware access?
+NEED_PCI=yes
+# Does the programmer need some sort of serial port access?
+NEED_SERIAL=no
+# Does the programmer use Parallel/LPC/FWH functionality?
+NEED_PARLPCFWH=no
+# Does the programmer use the bitbanging SPI infrastructure?
+NEED_BITBANG_SPI=yes
+
+# No user serviceable parts below.
+if test $HAVE_MAP = yes; then MAPNAME=$PROGRAMMERNAME; else MAPNAME=fallback; fi
+if test $HAVE_DELAY = yes; then DELAYNAME=$PROGRAMMERNAME; else DELAYNAME=internal; fi
+PROGRAMMERNAMECAPS=$(echo -n $PROGRAMMERNAME|tr "[[:lower:]]" "[[:upper:]]")
+CONFIGNAME=CONFIG_$PROGRAMMERNAMECAPS
+ENUMNAME=PROGRAMMER_$PROGRAMMERNAMECAPS
+BITBANG_SPI_ENUMNAME=BITBANG_SPI_MASTER_$PROGRAMMERNAMECAPS
+if test $NEED_PCI = yes; then NEEDS="NEED_PCI := yes\n"; fi
+if test $NEED_SERIAL = yes; then NEEDS+="NEED_SERIAL := yes\n"; fi
+
+sed "s-^//PLACEHOLDER_NEWPROG_PROGRAMMER_ARRAY-\
+#if $CONFIGNAME == 1\n\
+ {\n\
+ .name = \"${PROGRAMMERNAME}\",\n\
+ .init = ${PROGRAMMERNAME}_init,\n\
+ .map_flash_region = ${MAPNAME}_map,\n\
+ .unmap_flash_region = ${MAPNAME}_unmap,\n\
+ .delay = ${DELAYNAME}_delay,\n\
+ },\n\
+#endif\n\
+\n\0-" flashrom.c >flashrom.c.mine
+
+sed -e "s/^#PLACEHOLDER_NEWPROG_DEFAULTCONFIG/\
+# Enable $PROGRAMMERDESCR for now.\n\
+$CONFIGNAME ?= yes\n\
+\n\0/" \
+-e "s/^#PLACEHOLDER_NEWPROG_COMPILERULE/\
+ifeq (\$($CONFIGNAME), yes)\n\
+FEATURE_CFLAGS += -D'$CONFIGNAME=1'\n\
+PROGRAMMER_OBJS += $PROGRAMMERNAME.o\n\
+${NEEDS}\
+endif\n\
+\n\0/" Makefile >Makefile.mine1
+
+if test $NEED_BITBANG_SPI = yes; then
+sed -e "s/^#PLACEHOLDER_NEWPROG_BITBANGSPICONFIG1/\
+ifeq (\$($CONFIGNAME), yes)\n\
+override CONFIG_BITBANG_SPI = yes\n\
+else\n\
+\0/" \
+-e "s/^#PLACEHOLDER_NEWPROG_BITBANGSPICONFIG2/\
+\0\n\
+endif/;" Makefile.mine1 >Makefile.mine
+rm Makefile.mine1
+else
+mv Makefile.mine1 Makefile.mine
+fi
+
+sed -e "s-^//PLACEHOLDER_NEWPROG_PROGRAMMER_ENUM-\
+#if $CONFIGNAME == 1\n\
+ $ENUMNAME,\n\
+#endif\n\
+\0-" \
+-e "s-//PLACEHOLDER_NEWPROG_PUBLICFUNCTIONS-\
+/* $PROGRAMMERNAME.c */\n\
+#if $CONFIGNAME == 1\n\
+int ${PROGRAMMERNAME}_init(void);\n\
+#endif\n\
+\n\0-" programmer.h >programmer.h.mine1
+
+if test $NEED_BITBANG_SPI = yes; then
+sed -e "s-^//PLACEHOLDER_NEWPROG_PROGRAMMER_BITBANG_ENUM-\
+#if $CONFIGNAME == 1\n\
+ $BITBANG_SPI_ENUMNAME,\n\
+#endif\n\
+\0-" \
+-e "s-//PLACEHOLDER_NEWPROG_SELECT_SPI_BITBANG\$-\
+|| $CONFIGNAME == 1 \0-" programmer.h.mine1 >programmer.h.mine
+rm programmer.h.mine1
+else
+mv programmer.h.mine1 programmer.h.mine
+fi
+
+sed -e "s-PLACEHOLDER_NEWPROG_CHECK_PROGRAMMERCOUNT-\
+$CONFIGNAME+\0-" \
+-e "s-^//PLACEHOLDER_NEWPROG_PROGRAMMER_ENUMDEFAULT-\
+#if $CONFIGNAME == 1\n\
+ $ENUMNAME\n\
+#endif\n\
+\0-" cli_classic.c >cli_classic.c.mine
+
+cat >$PROGRAMMERNAME.c <<EOF
+/*
+ * This file is part of the flashrom project.
+ *
+ * Copyright (C) $(date +%Y) $AUTHORNAME
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Driver for the $PROGRAMMERDESCR hardware by $PROGRAMMERMANUF.
+ * See $PROGRAMMERURL for more info.
+ */
+
+#include "flash.h"
+#include "programmer.h"
+
+EOF
+
+if test $NEED_PARLPCFWH = yes; then
+cat >>$PROGRAMMERNAME.c <<EOF
+static const struct par_programmer par_programmer_${PROGRAMMERNAME} = {
+ .chip_readb = ${PROGRAMMERNAME}_chip_readb,
+ .chip_readw = fallback_chip_readw,
+ .chip_readl = fallback_chip_readl,
+ .chip_readn = fallback_chip_readn,
+ .chip_writeb = ${PROGRAMMERNAME}_chip_writeb,
+ .chip_writew = fallback_chip_writew,
+ .chip_writel = fallback_chip_writel,
+ .chip_writen = fallback_chip_writen,
+};
+
+EOF
+fi
+
+if test $NEED_BITBANG_SPI = yes; then
+cat >>$PROGRAMMERNAME.c <<EOF
+static void ${PROGRAMMERNAME}_bitbang_set_cs(int val)
+{
+ /* Set/clear the CS# line. */
+}
+
+static void ${PROGRAMMERNAME}_bitbang_set_sck(int val)
+{
+ /* Set/clear the SCLK line. */
+}
+
+static void ${PROGRAMMERNAME}_bitbang_set_mosi(int val)
+{
+ /* Set/clear the MOSI line. */
+}
+
+static int ${PROGRAMMERNAME}_bitbang_get_miso(void)
+{
+ /* Get the state of the MISO line and return it. */
+ /* Set it to 1 to get the template to compile. */
+ int misoval = 0;
+
+ return misoval;
+}
+
+static void ${PROGRAMMERNAME}_request_spibus(void)
+{
+}
+
+static void ${PROGRAMMERNAME}_release_spibus(void)
+{
+}
+
+static const struct bitbang_spi_master bitbang_spi_master_$PROGRAMMERNAME = {
+ .type = $BITBANG_SPI_ENUMNAME,
+ .set_cs = ${PROGRAMMERNAME}_bitbang_set_cs,
+ .set_sck = ${PROGRAMMERNAME}_bitbang_set_sck,
+ .set_mosi = ${PROGRAMMERNAME}_bitbang_set_mosi,
+ .get_miso = ${PROGRAMMERNAME}_bitbang_get_miso,
+ .request_bus = ${PROGRAMMERNAME}_request_spibus,
+ .release_bus = ${PROGRAMMERNAME}_release_spibus,
+ .half_period = 1,
+};
+
+EOF
+fi
+
+cat >>$PROGRAMMERNAME.c <<EOF
+static int ${PROGRAMMERNAME}_shutdown(void *data)
+{
+ /* Shutdown stuff. */
+ return 0;
+}
+
+int ${PROGRAMMERNAME}_init(void)
+{
+ /* Init stuff (i.e. parameter parsing) here which does not need to be
+ * undone.
+ */
+
+ /* If your shutdown function takes a parameter, replace NULL with it. */
+ register_shutdown(${PROGRAMMERNAME}_shutdown, NULL);
+
+ /* Init stuff which needs to be undone on shutdown. */
+
+EOF
+
+if test $NEED_BITBANG_SPI = yes; then
+cat >>$PROGRAMMERNAME.c <<EOF
+ /* 1 usec halfperiod delay, change as needed. */
+ if (bitbang_spi_init(&bitbang_spi_master_${PROGRAMMERNAME}))
+ return 1;
+
+EOF
+fi
+
+cat >>$PROGRAMMERNAME.c <<EOF
+ return 0;
+}
+EOF
+
Eigenschaftsänderungen: flashrom-programmer_template/build_new_driver.sh
___________________________________________________________________
Hinzugefügt: svn:executable
+ *
Index: flashrom-programmer_template/Makefile
===================================================================
--- flashrom-programmer_template/Makefile (Revision 1539)
+++ flashrom-programmer_template/Makefile (Arbeitskopie)
@@ -344,6 +344,8 @@
# Enable Linux spidev interface by default. We disable it on non-Linux targets.
CONFIG_LINUX_SPI ?= yes
+#PLACEHOLDER_NEWPROG_DEFAULTCONFIG
+
# Disable wiki printing by default. It is only useful if you have wiki access.
CONFIG_PRINT_WIKI ?= no
@@ -363,7 +365,9 @@
ifeq ($(CONFIG_OGP_SPI), yes)
override CONFIG_BITBANG_SPI = yes
else
+#PLACEHOLDER_NEWPROG_BITBANGSPICONFIG1
CONFIG_BITBANG_SPI ?= no
+#PLACEHOLDER_NEWPROG_BITBANGSPICONFIG2
endif
endif
endif
@@ -503,6 +507,8 @@
PROGRAMMER_OBJS += linux_spi.o
endif
+#PLACEHOLDER_NEWPROG_COMPILERULE
+
ifeq ($(NEED_SERIAL), yes)
LIB_OBJS += serial.o
endif
Index: flashrom-programmer_template/cli_classic.c
===================================================================
--- flashrom-programmer_template/cli_classic.c (Revision 1539)
+++ flashrom-programmer_template/cli_classic.c (Arbeitskopie)
@@ -41,7 +41,7 @@
* if more than one of them is selected. If only one is selected, it is clear
* that the user wants that one to become the default.
*/
-#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG+CONFIG_RAYER_SPI+CONFIG_NICINTEL+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV > 1
+#if CONFIG_NIC3COM+CONFIG_NICREALTEK+CONFIG_NICNATSEMI+CONFIG_GFXNVIDIA+CONFIG_DRKAISER+CONFIG_SATASII+CONFIG_ATAHPT+CONFIG_FT2232_SPI+CONFIG_SERPROG+CONFIG_BUSPIRATE_SPI+CONFIG_DEDIPROG+CONFIG_RAYER_SPI+CONFIG_NICINTEL+CONFIG_NICINTEL_SPI+CONFIG_OGP_SPI+CONFIG_SATAMV+PLACEHOLDER_NEWPROG_CHECK_PROGRAMMERCOUNT > 1
#error Please enable either CONFIG_DUMMY or CONFIG_INTERNAL or disable support for all programmers except one.
#endif
static enum programmer default_programmer =
@@ -96,6 +96,7 @@
#if CONFIG_LINUX_SPI == 1
PROGRAMMER_LINUX_SPI
#endif
+//PLACEHOLDER_NEWPROG_PROGRAMMER_ENUMDEFAULT
;
#endif
Index: flashrom-programmer_template/flashrom.c
===================================================================
--- flashrom-programmer_template/flashrom.c (Revision 1539)
+++ flashrom-programmer_template/flashrom.c (Arbeitskopie)
@@ -261,6 +261,7 @@
},
#endif
+//PLACEHOLDER_NEWPROG_PROGRAMMER_ARRAY
{}, /* This entry corresponds to PROGRAMMER_INVALID. */
};
Index: flashrom-programmer_template/programmer.h
===================================================================
--- flashrom-programmer_template/programmer.h (Revision 1539)
+++ flashrom-programmer_template/programmer.h (Arbeitskopie)
@@ -87,6 +87,7 @@
#if CONFIG_LINUX_SPI == 1
PROGRAMMER_LINUX_SPI,
#endif
+//PLACEHOLDER_NEWPROG_PROGRAMMER_ENUM
PROGRAMMER_INVALID /* This must always be the last entry. */
};
@@ -127,6 +128,7 @@
#if CONFIG_OGP_SPI == 1
BITBANG_SPI_MASTER_OGP,
#endif
+//PLACEHOLDER_NEWPROG_PROGRAMMER_BITBANG_ENUM
};
struct bitbang_spi_master {
@@ -461,6 +463,8 @@
int dediprog_init(void);
#endif
+//PLACEHOLDER_NEWPROG_PUBLICFUNCTIONS
+
/* flashrom.c */
struct decode_sizes {
uint32_t parallel;
@@ -505,7 +509,7 @@
#if CONFIG_DEDIPROG == 1
SPI_CONTROLLER_DEDIPROG,
#endif
-#if CONFIG_OGP_SPI == 1 || CONFIG_NICINTEL_SPI == 1 || CONFIG_RAYER_SPI == 1 || CONFIG_PONY_SPI == 1 || (CONFIG_INTERNAL == 1 && (defined(__i386__) || defined(__x86_64__)))
+#if CONFIG_OGP_SPI == 1 || CONFIG_NICINTEL_SPI == 1 || CONFIG_RAYER_SPI == 1 || CONFIG_PONY_SPI == 1 || (CONFIG_INTERNAL == 1 && (defined(__i386__) || defined(__x86_64__))) //PLACEHOLDER_NEWPROG_SELECT_SPI_BITBANG
SPI_CONTROLLER_BITBANG,
#endif
#if CONFIG_LINUX_SPI == 1
--
http://www.hailfinger.org/
On Mon, 30 May 2011 02:45:44 +0200
Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote:
> this patch also changes the display width of all addresses in physmap.c to 16 hex characters.
>
> FIXME: what about unmappings?
> munmap is safe.
> djgpp's __dpmi_free_physical_address_mapping: unknown.
> DirectHW's unmap_physical: unknown.
>
> FIXME: jakllsch suggested using PRIx64 instead of x, because it's more portable
FIXME: in the case we can not map and 'mayfail' is true we should return
ERROR_PTR instead of ERROR_PTR + diff
--
Kind regards/Mit freundlichen Grüßen, Stefan Tauner
Am 23.07.2012 15:33 schrieb Stefan Tauner:
> Kyösti Mälkki noticed that we unnecessarily read the flash chip twice when
> called with --verify. The first one is the mandatory read before everything
> (to be able to detect the seriousness of errors), but the second one is not
> necessary because we can just use the former for the comparison.
Indeed.
> This introduces a small output change: previously we printed ERASE or
> VERIFY depending on the callee. This special case has been dropped
> because it is unnecessary to print it (and wrong for the verification
> function to need to know why it is verifying exactly).
> If an erase fails we mention that fact explicitly already, similar for verify.
I'm not convinced yet. I'll try to compare the failure output with and
without this patch before I ack.
> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at>
> ---
> flash.h | 2 +-
> flashrom.c | 86 +++++++++++++++++++++++++++---------------------------------
> jedec.c | 2 +-
> 3 files changed, 41 insertions(+), 49 deletions(-)
>
> diff --git a/flash.h b/flash.h
> index d669512..5bb1211 100644
> --- a/flash.h
> +++ b/flash.h
> @@ -241,7 +241,7 @@ int min(int a, int b);
> int max(int a, int b);
> void tolower_string(char *str);
> char *extract_param(char **haystack, const char *needle, const char *delim);
> -int verify_range(struct flashctx *flash, uint8_t *cmpbuf, unsigned int start, unsigned int len, const char *message);
> +int verify_range(struct flashctx *flash, uint8_t *cmpbuf, unsigned int start, unsigned int len);
> int need_erase(uint8_t *have, uint8_t *want, unsigned int len, enum write_granularity gran);
> char *strcat_realloc(char *dest, const char *src);
> void print_version(void);
> diff --git a/flashrom.c b/flashrom.c
> index fc52c4a..70687ff 100644
> --- a/flashrom.c
> +++ b/flashrom.c
> @@ -548,6 +548,26 @@ static unsigned int count_usable_erasers(const struct flashctx *flash)
> return usable_erasefunctions;
> }
>
> +int compare_range(uint8_t *wantbuf, uint8_t *havebuf, unsigned int start, unsigned int len)
Make this function static?
> +{
> + int ret = 0, failcount = 0;
> + unsigned int i;
> + for (i = 0; i < len; i++) {
> + if (wantbuf[i] != havebuf[i]) {
> + /* Only print the first failure. */
> + if (!failcount++)
> + msg_cerr("FAILED at 0x%08x! Expected=0x%02x, Found=0x%02x,",
> + start + i, wantbuf[i], havebuf[i]);
> + }
> + }
> + if (failcount) {
> + msg_cerr(" failed byte count from 0x%08x-0x%08x: 0x%x\n",
> + start, start + len - 1, failcount);
> + ret = -1;
> + }
> + return ret;
> +}
> +
> /* start is an offset to the base address of the flash chip */
> int check_erased_range(struct flashctx *flash, unsigned int start,
> unsigned int len)
> @@ -560,7 +580,7 @@ int check_erased_range(struct flashctx *flash, unsigned int start,
> exit(1);
> }
> memset(cmpbuf, 0xff, len);
> - ret = verify_range(flash, cmpbuf, start, len, "ERASE");
> + ret = verify_range(flash, cmpbuf, start, len);
> free(cmpbuf);
> return ret;
> }
> @@ -570,15 +590,12 @@ int check_erased_range(struct flashctx *flash, unsigned int start,
> * flash content at location start
> * @start offset to the base address of the flash chip
> * @len length of the verified area
> - * @message string to print in the "FAILED" message
> * @return 0 for success, -1 for failure
> */
> -int verify_range(struct flashctx *flash, uint8_t *cmpbuf, unsigned int start,
> - unsigned int len, const char *message)
> +int verify_range(struct flashctx *flash, uint8_t *cmpbuf, unsigned int start, unsigned int len)
> {
> - unsigned int i;
> uint8_t *readbuf = malloc(len);
> - int ret = 0, failcount = 0;
> + int ret = 0;
>
> if (!len)
> goto out_free;
> @@ -599,8 +616,6 @@ int verify_range(struct flashctx *flash, uint8_t *cmpbuf, unsigned int start,
> ret = -1;
> goto out_free;
> }
> - if (!message)
> - message = "VERIFY";
>
> ret = flash->read(flash, readbuf, start, len);
> if (ret) {
> @@ -609,22 +624,7 @@ int verify_range(struct flashctx *flash, uint8_t *cmpbuf, unsigned int start,
> return ret;
> }
>
> - for (i = 0; i < len; i++) {
> - if (cmpbuf[i] != readbuf[i]) {
> - /* Only print the first failure. */
> - if (!failcount++)
> - msg_cerr("%s FAILED at 0x%08x! "
> - "Expected=0x%02x, Read=0x%02x,",
> - message, start + i, cmpbuf[i],
> - readbuf[i]);
> - }
> - }
> - if (failcount) {
> - msg_cerr(" failed byte count from 0x%08x-0x%08x: 0x%x\n",
> - start, start + len - 1, failcount);
> - ret = -1;
> - }
> -
> + ret = compare_range(cmpbuf, readbuf, start, len);
Good idea to refactor this.
> out_free:
> free(readbuf);
> return ret;
> @@ -1060,21 +1060,6 @@ notfound:
> return flash - flashchips;
> }
>
> -int verify_flash(struct flashctx *flash, uint8_t *buf)
> -{
> - int ret;
> - unsigned int total_size = flash->total_size * 1024;
> -
> - msg_cinfo("Verifying flash... ");
> -
> - ret = verify_range(flash, buf, 0, total_size, NULL);
> -
> - if (!ret)
> - msg_cinfo("VERIFIED. \n");
> -
> - return ret;
> -}
I believe that this hunk conflicts with some of your layout patches.
Maybe not a direct patch hunk conflict, but having a standalone function
which verifies the flash chip according to some layout rules is a good
thing. I'd keep verify_flash for now. OTOH, the hunk below makes it
painfully obvious that the current verify_flash abstraction is not the
right abstraction.
Two functions compare_all_ranges() defaulting to a full chip range and
verify_all_ranges() with similar characteristics would IMHO be a good
abstraction, especially in light of the pending improved layout support.
> -
> int read_buf_from_file(unsigned char *buf, unsigned long size,
> const char *filename)
> {
> @@ -1838,15 +1823,22 @@ int doit(struct flashctx *flash, int force, const char *filename, int read_it,
> }
>
> if (verify_it) {
> - /* Work around chips which need some time to calm down. */
> - if (write_it)
> + msg_cinfo("Verifying flash... ");
> +
> + if (write_it) {
> + /* Work around chips which need some time to calm down. */
> programmer_delay(1000*1000);
> - ret = verify_flash(flash, newcontents);
> - /* If we tried to write, and verification now fails, we
> - * might have an emergency situation.
> - */
> - if (ret && write_it)
> - emergency_help_message();
> + ret = verify_range(flash, newcontents, 0, size);
> + /* If we tried to write, and verification now fails, we
> + * might have an emergency situation.
> + */
> + if (ret)
> + emergency_help_message();
> + } else {
> + ret = compare_range(newcontents, oldcontents, 0, size);
> + }
> + if (!ret)
> + msg_cinfo("VERIFIED.\n");
> }
>
> out:
> diff --git a/jedec.c b/jedec.c
> index 69c0c0c..1fa1a10 100644
> --- a/jedec.c
> +++ b/jedec.c
> @@ -409,7 +409,7 @@ retry:
>
> dst = d;
> src = s;
> - failed = verify_range(flash, src, start, page_size, NULL);
> + failed = verify_range(flash, src, start, page_size);
>
> if (failed && tried++ < MAX_REFLASH_TRIES) {
> msg_cerr("retrying.\n");
I agree with the direction of the patch, I'm just not yet sure about the
implementation.
Regards,
Carl-Daniel
--
http://www.hailfinger.org/
On Sat, 9 Jun 2012 14:51:15 +0200
frederic.temporelli(a)bull.net wrote:
> Hello
>
>
> Numonyx/Micron N25Q128 is used on new X9 motherboards from Supermicro (X9DRT, ...)
>
> Specs are availbale on Micron WWW site:
> http://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/S…
>
> Following patch add this chip to flashrom. Probe is OK.
> Due to Manageability Engine, some work is required before being able to test READ/ERASE/WRITE...
>
> =================================================================================
> Signed-off-by: Frederic Temporelli <frederic.temporelli(a)bull.net>
>
> diff -urN flashrom-0.9.5.2-r1540/flashchips.c flashrom-0.9.5.2-r1540-n25q128/flashchips.c
> --- flashrom-0.9.5.2-r1540/flashchips.c 2012-05-20 23:32:32.000000000 +0000
> +++ flashrom-0.9.5.2-r1540-n25q128/flashchips.c 2012-06-09 14:41:07.064141076 +0000
> @@ -5453,6 +5453,37 @@
> },
>
> {
> + .vendor = "Numonyx",
> + .name = "N25Q128",
> + .bustype = BUS_SPI,
> + .manufacture_id = ST_ID,
> + .model_id = ST_N25Q128,
> + .total_size = 16384,
> + .page_size = 256,
> + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
> + .tested = TEST_OK_PROBE,
> + .probe = probe_spi_rdid,
> + .probe_timing = TIMING_ZERO,
> + .block_erasers =
> + {
> + {
> + .eraseblocks = { {4 * 1024, 4096 } },
> + .block_erase = spi_block_erase_20,
> + }, {
> + .eraseblocks = { {64 * 1024, 256} },
> + .block_erase = spi_block_erase_d8,
> + }, {
> + .eraseblocks = { {16 * 1024 * 1024, 1} },
> + .block_erase = spi_block_erase_c7,
> + }
> + },
> + .unlock = spi_disable_blockprotect,
> + .write = spi_chip_write_256,
> + .read = spi_chip_read,
> + },
> +
> +
> + {
> .vendor = "PMC",
> .name = "Pm25LV010",
> .bustype = BUS_SPI,
> diff -urN flashrom-0.9.5.2-r1540/flashchips.h flashrom-0.9.5.2-r1540-n25q128/flashchips.h
> --- flashrom-0.9.5.2-r1540/flashchips.h 2012-05-14 01:51:46.000000000 +0000
> +++ flashrom-0.9.5.2-r1540-n25q128/flashchips.h 2012-06-08 20:46:47.225385676 +0000
> @@ -587,6 +587,7 @@
> #define ST_M29W040B 0xE3
> #define ST_M29W512B 0x27
> #define ST_N25Q064 0xBA17
> +#define ST_N25Q128 0xBA18 /* also Numonyx N25Q128 */
>
> #define SYNCMOS_MVC_ID 0x40 /* SyncMOS (SM) and Mosel Vitelic Corporation (MVC) */
> #define MVC_V29C51000T 0x00
> =================================================================================
hello and thanks for your patch!
this chip is a bit complicated and we cant merge the patch as it is.
they have used the same plane RDID for multiple variants of the chip.
some attributes are not important for flashrom and can be ignored, but
some are very important, namely the boot sector layout. quote from p.52:
> The N25Q128 is available in the following architecture versions:
> Bottom version, 64 KB uniform sectors plus 8 bottom boot sectors (each with 16
> subsectors),
> Top version, 64 KB uniform sectors plus 8 top boot sectors (each with 16 subsectors)
> Uniform version, 64 KB uniform sectors without any boot sectors and subsectors.
the good news is that this differences can be detected by an extended
RDID command in its 5th byte (1 manufacturer, 2 device, 1 length of the
following extended data, the first EDID byte we want), see table 15.
of this 5th byte we need to look at the first two bits to determine the
architecture, see table 16.
our current infrastructure (probe_spi_rdid_generic) cant handle that,
but should... so we will plan a change, but please dont expect it to
happen too soon.
the bad news is that i am not even sure if the subsector erase commands
work as flashrom expects. flashrom wants to use the same erase opcode
for the hole address space, even for non-uniform layouts. this usually
works fine, but afaics it is not specified in the datasheet what
happens if one uses the subsector erase opcode on a non-subsector *on
devices that actually have subsectors* (the emphasis stems from the
fact that it *is* defined, that the subsector erase command is ignore
by the uniform model: "Any Subsector Erase (SSE) instruction in devices
with uniform architecture (meaning no boot sectors with subsectors) is
rejected without having any effects on the device." (p. 98).
other interesting bits of this chips:
- bit#5 of the status register "is used in conjunction with the Block
Protect (BP3, BP2, BP1, BP0) bits to determine if the protected area
defined by the Block Protect bits starts from the top or the bottom
of the memory array"
- a flag status register that gives more info than the "legacy spi
status register"
- a non-volatile configuration register to configure dummy clock
cycles, output driver strength and other stuff, and a volatile
register that overrides the nvm settings
the first two points can be somewhat ignored by us, the generic "write 0
to the status register" is good enough to unlock the device.
regarding the ME: are you aware of my layout patches, that enable read,
erase and verify on user-definable address ranges? see the patches from
2011-12-25 at http://patchwork.coreboot.org/project/flashrom/list/
--
Kind regards/Mit freundlichen Grüßen, Stefan Tauner