flashrom April 2012

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Re: [flashrom] [PATCH] Add Documentation regarding unlocking the ME region on Intel chipsets.
by Uwe Hermann 15 Apr '12

15 Apr '12

On Mon, Mar 12, 2012 at 03:11:13AM +0100, Stefan Tauner wrote: > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> This one's trivial, as it's purely doc changes, so: Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> But see the comments below please. > --- > Documentation/mysteries_intel.txt | 81 ++++++++++++++++++++++++++++++++++++- > 1 files changed, 80 insertions(+), 1 deletions(-) > > diff --git a/Documentation/mysteries_intel.txt b/Documentation/mysteries_intel.txt > index d6d3dfb..8a9a113 100644 > --- a/Documentation/mysteries_intel.txt > +++ b/Documentation/mysteries_intel.txt > @@ -15,4 +15,83 @@ > See also http://www.flashrom.org/pipermail/flashrom/2011-August/007606.html > > = Unlocking the ME region = > -TODO > + If the ME region is locked by the FRAP register in descriptor mode, the host > + software is not allowed to read or write any address inside that region. There > + are different ways to unlock access: > + > + - a pin strap: Flash Descriptor Security Override Strap (as indicated by the "a pin" -> "A pin" > + Flash Descriptor Override Pin Strap Status (FDOPSS) in HSFS. That pin is > + probably not accessible to end users on consumer boards (every Intel doc i ^ I > + have seen stresses that this is for debugging in manufacturing only and > + should not be available for end users). > + The ME indicates this in bits [19:16] (Operation Mode) in the HFS register of > + the HECI/MEI PCI device by setting them to 4 (SECOVR_JMPR) [MODE_CTRL]. > + > + - Intel Management Engine BIOS Extension (MEBx) Disable This option may be ^ Missing full stop. > + available to end users on some boards usually accessible by hitting > + ctrl+p after BIOS POST. Quote: "???Disabling??? the Intel ME does not really > + disable it: it causes the Intel ME code to be halted at an early stage of > + the Intel ME???s booting so that the system has no traffic originating from > + the Intel ME on any of the buses." [MEBX] Kill the strange "???" above? > + The ME indicates this in bits [19:16] (Operation Mode) in the HFS register of > + the HECI/MEI PCI device by setting them to 3 (Soft Temporary Disable) > + [MODE_CTRL]. > + > + - Previous to Ibex Peak/5 Series chipsets removing the DIMM from slot (or > + channel?) #0 disables the ME completely, which may give the host access to > + the ME region. > + > + - HMRFPO (Host ME Region Flash Protection Override) Enable MEI command > + This is the most interesting one because it allows to temporarily disable > + the ME region protection by software. The ME indicates this in bits [19:16] > + (Operation Mode) in the HFS register of the HECI/MEI PCI device by setting > + them to 5 (SECOVER_MEI_MSG) [MODE_CTRL]. > + > +== MEI/HECI == > + Communication between the host software and the different services provided by > + the ME is done via a packet-based protocol that uses MMIO transfers to one or > + more virtual PCI devices. Upon this layer there exist various services that can > + be used to read out hardware management values (e.g. temperatures, fan speeds > + etc.). The lower levels of that protocol are well documented: > + The locations/offsets of the PCI MMIO registers are noted in the chipset > + datasheets. The actually communication is documented in a whitepaper [DCMI] and > + an outdated as well as a current Linux kernel implementation (currently in > + staging/ exist [KERNEL]. There exists a patch that re-implements this in user > + space (as part of flashrom). > + > +== Problems == > + The problem is that only very few higher level protocols are documented publicly, > + especially the bunch of messages that contain the HMRFPO commands is probably > + well protected and only documented in ME-specific docs and the BIOS writer's > + guides. We are aware of a few leaked documents though that give us a few hints > + about it, but nothing substantial regarding its implementation. > + > + The documents are somewhat contradicting each other in various points which > + might be due to factual changes in process of time or due to the different > + capabilities of the ME firmwares, example: > + > + Intel's Flash Programming Tool (FPT) "automatically stops ME writing to SPI > + ME Region, to prevent both writing at the same time, causing data corruption." [ME8] > + > + "FPT is not HMRFPO-capable, so needs [the help of the FDOPS pin] HDA_SDO if > + used to update the ME Region." [SPS] > + > + When looking at the various ME firmware editions (and different chipsets), things > + get very unclear. Some docs say that HMRFPO needs to be sent before End-of-POST > + (EOP), others say that the ME region can be updated in the field or that some > + vendor tools use it for updates. This needs to be investigated further before > + drawing any conclusion. > + > +[MODE_CTRL] Client Platform Enabling Tour: Platform Software > + Document Number: 439167, Revision 1.2, page 52 > +[MEBX] Intel?? Management Engine BIOS Extension (MEBX) User???s Guide Kill/fix the "???" stuff. > + Revision 1.2, Section 3.1 and 3.5 > +[DCMI] DCMI Host Interface Specification > + Revision 1.0 > +[KERNEL] http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=tree;f=d… > +[SPI_PROG] Ibex Peak SPI Programming Guide > + Document Number: 403598, Revision 1.3, page 79 > +[ME8] Manufacturing with Intel?? Management Engine (ME) Firmware 8.X on Intel 7 Series Ditto. > + Revision 2.0, page 59 > +[SPS] Manufacturing with Intel?? Management Engine (ME) on Intel?? C600 Series Chipset 1 for Romley Server 2 Platforms using Server Platform Services (SPS) Firmware Ditto. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[commit] r1522 - trunk
by repository service 15 Apr '12

15 Apr '12

Author: uwe Date: Sun Apr 15 15:16:32 2012 New Revision: 1522 URL: http://flashrom.org/trac/flashrom/changeset/1522 Log: Add support for for the Atmel AT49F040 chip. Chip features an optional permanent boot block write protection. Signed-off-by: David Borg <borg.db(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/chipdrivers.h trunk/flashchips.c trunk/flashchips.h trunk/w39.c Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Sun Apr 15 00:51:40 2012 (r1521) +++ trunk/chipdrivers.h Sun Apr 15 15:16:32 2012 (r1522) @@ -149,6 +149,7 @@ int printlock_w39v080fa_dual(struct flashctx *flash); int unlock_w39v040fb(struct flashctx *flash); int unlock_w39v080fa(struct flashctx *flash); +int printlock_at49f(struct flashctx *flash); /* w29ee011.c */ int probe_w29ee011(struct flashctx *flash); Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Sun Apr 15 00:51:40 2012 (r1521) +++ trunk/flashchips.c Sun Apr 15 15:16:32 2012 (r1522) @@ -2226,19 +2226,27 @@ { .vendor = "Atmel", - .name = "AT49F020", + .name = "AT49F002(N)", .bustype = BUS_PARALLEL, .manufacture_id = ATMEL_ID, - .model_id = ATMEL_AT49F020, + .model_id = ATMEL_AT49F002N, .total_size = 256, .page_size = 256, .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_OK_PRE, + .tested = TEST_UNTESTED, .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ .block_erasers = { { + .eraseblocks = { + {16 * 1024, 1}, + {8 * 1024, 2}, + {96 * 1024, 1}, + {128 * 1024, 1}, + }, + .block_erase = erase_sector_jedec, + }, { .eraseblocks = { {256 * 1024, 1} }, .block_erase = erase_chip_block_jedec, } @@ -2250,24 +2258,24 @@ { .vendor = "Atmel", - .name = "AT49F002(N)", + .name = "AT49F002(N)T", .bustype = BUS_PARALLEL, .manufacture_id = ATMEL_ID, - .model_id = ATMEL_AT49F002N, + .model_id = ATMEL_AT49F002NT, .total_size = 256, .page_size = 256, .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PR, .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ .block_erasers = { { .eraseblocks = { - {16 * 1024, 1}, - {8 * 1024, 2}, - {96 * 1024, 1}, {128 * 1024, 1}, + {96 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, }, .block_erase = erase_sector_jedec, }, { @@ -2282,31 +2290,61 @@ { .vendor = "Atmel", - .name = "AT49F002(N)T", + .name = "AT49F020", .bustype = BUS_PARALLEL, .manufacture_id = ATMEL_ID, - .model_id = ATMEL_AT49F002NT, + .model_id = ATMEL_AT49F020, .total_size = 256, .page_size = 256, .feature_bits = FEATURE_EITHER_RESET, - .tested = TEST_OK_PR, + .tested = TEST_OK_PRE, .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ .block_erasers = { { - .eraseblocks = { - {128 * 1024, 1}, - {96 * 1024, 1}, - {8 * 1024, 2}, - {16 * 1024, 1}, - }, - .block_erase = erase_sector_jedec, - }, { .eraseblocks = { {256 * 1024, 1} }, .block_erase = erase_chip_block_jedec, } + /* Chip features an optional permanent write protection + * of the first 8 kB. The erase function is the same as + * above, but 00000H to 01FFFH will not be erased. + * FIXME: add another eraser when partial erasers are + * supported. + */ + }, + .printlock = printlock_at49f, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {4500, 5500}, + }, + + { + .vendor = "Atmel", + .name = "AT49F040", + .bustype = BUS_PARALLEL, + .manufacture_id = ATMEL_ID, + .model_id = ATMEL_AT49F040, + .total_size = 512, + .page_size = 512, + .feature_bits = FEATURE_EITHER_RESET, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ + .block_erasers = + { + { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + } + /* Chip features an optional permanent write protection + * of the first 16 kB. The erase function is the same as + * above, but 00000H to 03FFFH will not be erased. + * FIXME: add another eraser when partial erasers are + * supported. + */ }, + .printlock = printlock_at49f, .write = write_jedec_1, .read = read_memmapped, .voltage = {4500, 5500}, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Sun Apr 15 00:51:40 2012 (r1521) +++ trunk/flashchips.h Sun Apr 15 15:16:32 2012 (r1522) @@ -184,10 +184,11 @@ #define ATMEL_AT45DB642 /* No ID available */ #define ATMEL_AT45DB642D 0x2800 #define ATMEL_AT49BV512 0x03 -#define ATMEL_AT49F020 0x0B #define ATMEL_AT49F002N 0x07 /* for AT49F002(N) */ -#define ATMEL_AT49F002NT 0x08 /* for AT49F002(N)T */ #define ATMEL_AT49LH002 0xE9 +#define ATMEL_AT49F002NT 0x08 /* for AT49F002(N)T */ +#define ATMEL_AT49F020 0x0B +#define ATMEL_AT49F040 0x13 /* Bright Microelectronics has the same manufacturer ID as Hyundai... */ #define BRIGHT_ID 0xAD /* Bright Microelectronics */ Modified: trunk/w39.c ============================================================================== --- trunk/w39.c Sun Apr 15 00:51:40 2012 (r1521) +++ trunk/w39.c Sun Apr 15 15:16:32 2012 (r1522) @@ -278,3 +278,11 @@ return 0; } + +int printlock_at49f(struct flashctx *flash) +{ + uint8_t lock = w39_idmode_readb(flash, 0x00002); + msg_cdbg("Hardware bootblock lockout is %sactive.\n", + (lock & 0x01) ? "" : "not "); + return 0; +}

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Re: [flashrom] [PATCH] Add support for AT49F040
by Uwe Hermann 15 Apr '12

15 Apr '12

On Thu, Aug 11, 2011 at 05:59:42AM +0200, Stefan Tauner wrote: > Chip features an optional permanent boot block write protection. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Signed-off-by: David Borg <borg.db(a)gmail.com> > > --- > diff of flashchips.c looks very odd, this is because i moved AT49F020 down. > - rebased > - voltages added > - FEATURE_ADDR_FULL flag removed > - printlock_at49f040 added (location dubios, but w39_idmode_readb > implements what is needed already (and is static...) > - AT49F020 does also feature a permanent lock (8 kB boot block), which uses > the same detection method... Rebased (again) and committed in r1522, thanks. I changed 'struct flashchip *flash' to 'struct flashctx *flash' so that it compiles. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[commit] r1521 - trunk
by repository service 14 Apr '12

14 Apr '12

Author: uwe Date: Sun Apr 15 00:51:40 2012 New Revision: 1521 URL: http://flashrom.org/trac/flashrom/changeset/1521 Log: Add support for the Eon EN29LV640B chip. This chip needs special command sequences in 8 bit mode. Also, 8 bit programming needs actually 16bit double byte program. The chip is found on the Bifferos Bifferboard, for example. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Added: trunk/en29lv640b.c Modified: trunk/Makefile trunk/chipdrivers.h trunk/flashchips.c trunk/flashchips.h Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Sat Apr 14 23:59:23 2012 (r1520) +++ trunk/Makefile Sun Apr 15 00:51:40 2012 (r1521) @@ -261,7 +261,7 @@ CHIP_OBJS = jedec.o stm50flw0x0x.o w39.o w29ee011.o \ sst28sf040.o m29f400bt.o 82802ab.o pm49fl00x.o \ sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o sharplhf00l04.o \ - a25.o at25.o opaque.o sfdp.o + a25.o at25.o opaque.o sfdp.o en29lv640b.o LIB_OBJS = layout.o Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Sat Apr 14 23:59:23 2012 (r1520) +++ trunk/chipdrivers.h Sun Apr 15 00:51:40 2012 (r1521) @@ -157,4 +157,10 @@ int erase_sector_stm50flw0x0x(struct flashctx *flash, unsigned int block, unsigned int blocksize); int unlock_stm50flw0x0x(struct flashctx *flash); +/* en29lv640b.c */ +int probe_en29lv640b(struct flashctx *flash); +int block_erase_en29lv640b(struct flashctx *flash, unsigned int start, unsigned int len); +int block_erase_chip_en29lv640b(struct flashctx *flash, unsigned int start, unsigned int len); +int write_en29lv640b(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); + #endif /* !__CHIPDRIVERS_H__ */ Added: trunk/en29lv640b.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/en29lv640b.c Sun Apr 15 00:51:40 2012 (r1521) @@ -0,0 +1,138 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2000 Silicon Integrated System Corporation + * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "flash.h" +#include "chipdrivers.h" + +/* + * WARNING! + * This chip uses the standard JEDEC addresses in 16-bit mode as word + * addresses. In byte mode, 0xAAA has to be used instead of 0x555 and + * 0x555 instead of 0x2AA. Do *not* blindly replace with standard JEDEC + * functions. + */ + +/* chunksize is 1 */ +int write_en29lv640b(struct flashctx *flash, uint8_t *src, unsigned int start, + unsigned int len) +{ + int i; + chipaddr bios = flash->virtual_memory; + chipaddr dst = flash->virtual_memory + start; + + for (i = 0; i < len; i += 2) { + chip_writeb(flash, 0xAA, bios + 0xAAA); + chip_writeb(flash, 0x55, bios + 0x555); + chip_writeb(flash, 0xA0, bios + 0xAAA); + + /* Transfer data from source to destination. */ + chip_writew(flash, (*src) | ((*(src + 1)) << 8 ), dst); + toggle_ready_jedec(flash, dst); +#if 0 + /* We only want to print something in the error case. */ + msg_cerr("Value in the flash at address 0x%lx = %#x, want %#x\n", + (dst - bios), chip_readb(flash, dst), *src); +#endif + dst += 2; + src += 2; + } + + /* FIXME: Ignore errors for now. */ + return 0; +} + +int probe_en29lv640b(struct flashctx *flash) +{ + chipaddr bios = flash->virtual_memory; + uint16_t id1, id2; + + chip_writeb(flash, 0xAA, bios + 0xAAA); + chip_writeb(flash, 0x55, bios + 0x555); + chip_writeb(flash, 0x90, bios + 0xAAA); + + programmer_delay(10); + + id1 = chip_readb(flash, bios + 0x200); + id1 |= (chip_readb(flash, bios) << 8); + + id2 = chip_readb(flash, bios + 0x02); + + chip_writeb(flash, 0xF0, bios + 0xAAA); + + programmer_delay(10); + + msg_cdbg("%s: id1 0x%04x, id2 0x%04x\n", __func__, id1, id2); + + if (id1 == flash->manufacture_id && id2 == flash->model_id) + return 1; + + return 0; +} + +int erase_en29lv640b(struct flashctx *flash) +{ + chipaddr bios = flash->virtual_memory; + + chip_writeb(flash, 0xAA, bios + 0xAAA); + chip_writeb(flash, 0x55, bios + 0x555); + chip_writeb(flash, 0x80, bios + 0xAAA); + + chip_writeb(flash, 0xAA, bios + 0xAAA); + chip_writeb(flash, 0x55, bios + 0x555); + chip_writeb(flash, 0x10, bios + 0xAAA); + + programmer_delay(10); + toggle_ready_jedec(flash, bios); + + /* FIXME: Check the status register for errors. */ + return 0; +} + +int block_erase_en29lv640b(struct flashctx *flash, unsigned int start, + unsigned int len) +{ + chipaddr bios = flash->virtual_memory; + chipaddr dst = bios + start; + + chip_writeb(flash, 0xAA, bios + 0xAAA); + chip_writeb(flash, 0x55, bios + 0x555); + chip_writeb(flash, 0x80, bios + 0xAAA); + + chip_writeb(flash, 0xAA, bios + 0xAAA); + chip_writeb(flash, 0x55, bios + 0x555); + chip_writeb(flash, 0x30, dst); + + programmer_delay(10); + toggle_ready_jedec(flash, bios); + + /* FIXME: Check the status register for errors. */ + return 0; +} + +int block_erase_chip_en29lv640b(struct flashctx *flash, unsigned int address, + unsigned int blocklen) +{ + if ((address != 0) || (blocklen != flash->total_size * 1024)) { + msg_cerr("%s called with incorrect arguments\n", __func__); + return -1; + } + return erase_en29lv640b(flash); +} Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Sat Apr 14 23:59:23 2012 (r1520) +++ trunk/flashchips.c Sun Apr 15 00:51:40 2012 (r1521) @@ -3530,7 +3530,7 @@ .block_erasers = { { - .eraseblocks = { + .eraseblocks = { {16 * 1024, 1}, {8 * 1024, 2}, {32 * 1024, 1}, @@ -3562,7 +3562,7 @@ .block_erasers = { { - .eraseblocks = { + .eraseblocks = { {64 * 1024, 3}, {32 * 1024, 1}, {8 * 1024, 2}, @@ -3580,6 +3580,36 @@ }, { + .vendor = "Eon", + .name = "EN29LV640B", + .bustype = BUS_PARALLEL, + .manufacture_id = EON_ID, + .model_id = EON_EN29LV640B, + .total_size = 8192, + .page_size = 8192, + .feature_bits = 0, + .tested = TEST_OK_PREW, + .probe = probe_en29lv640b, + .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ + .block_erasers = + { + { + .eraseblocks = { + {8 * 1024, 8}, + {64 * 1024, 127}, + }, + .block_erase = block_erase_en29lv640b, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = block_erase_chip_en29lv640b, + }, + }, + .write = write_en29lv640b, + .read = read_memmapped, + .voltage = {2700, 3600}, + }, + + { .vendor = "Fujitsu", .name = "MBM29F004BC", .bustype = BUS_PARALLEL, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Sat Apr 14 23:59:23 2012 (r1520) +++ trunk/flashchips.h Sun Apr 15 00:51:40 2012 (r1521) @@ -256,6 +256,7 @@ #define EON_EN29F040A 0x7F04 #define EON_EN29LV010 0x7F6E #define EON_EN29LV040A 0x7F4F /* EN29LV040(A) */ +#define EON_EN29LV640B 0xCB #define EON_EN29F002T 0x7F92 /* Same as EN29F002A */ #define EON_EN29F002B 0x7F97 /* Same as EN29F002AN */

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[commit] r1520 - trunk
by repository service 14 Apr '12

14 Apr '12

Author: uwe Date: Sat Apr 14 23:59:23 2012 New Revision: 1520 URL: http://flashrom.org/trac/flashrom/changeset/1520 Log: Add GigaDevice GD25QXX series support. http://www.gigadevice.com/Product/SPI.php?WebPageTypeId=98&WebPageTypeId2=1… The GD25Q80 has been successfully tested, the other ones are marked as untested for now. http://www.flashrom.org/pipermail/flashrom/2012-March/009028.html Signed-off-by: Justin Chevrier <jchevrier(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Sat Apr 14 23:06:31 2012 (r1519) +++ trunk/flashchips.c Sat Apr 14 23:59:23 2012 (r1520) @@ -3709,6 +3709,268 @@ }, { + .vendor = "GigaDevice", + .name = "GD25Q20", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25Q20, + .total_size = 256, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 64} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 8} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 4} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "GigaDevice", + .name = "GD25Q40", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25Q40, + .total_size = 512, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 16} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "GigaDevice", + .name = "GD25Q80", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25Q80, + .total_size = 1024, + .page_size = 256, + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 32} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "GigaDevice", + .name = "GD25Q16", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25Q16, + .total_size = 2048, + .page_size = 256, + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 64} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "GigaDevice", + .name = "GD25Q32", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25Q32, + .total_size = 4096, + .page_size = 256, + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 128} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, + }, + + { + .vendor = "GigaDevice", + .name = "GD25Q64", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25Q64, + .total_size = 8192, + .page_size = 256, + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 256} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { + .vendor = "GigaDevice", + .name = "GD25Q128", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25Q128, + .total_size = 16384, + .page_size = 256, + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { .vendor = "Hyundai", .name = "HY29F002T", .bustype = BUS_PARALLEL, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Sat Apr 14 23:06:31 2012 (r1519) +++ trunk/flashchips.h Sat Apr 14 23:59:23 2012 (r1520) @@ -290,6 +290,15 @@ #define FUJITSU_MBM29LV800BA 0x5B /* Same as MBM29LV800BE */ #define FUJITSU_MBM29LV800TA 0xDA /* Same as MBM29LV800TE */ +#define GIGADEVICE_ID 0xC8 /* GigaDevice */ +#define GIGADEVICE_GD25Q20 0x4012 +#define GIGADEVICE_GD25Q40 0x4013 +#define GIGADEVICE_GD25Q80 0x4014 +#define GIGADEVICE_GD25Q16 0x4015 +#define GIGADEVICE_GD25Q32 0x4016 +#define GIGADEVICE_GD25Q64 0x4017 +#define GIGADEVICE_GD25Q128 0x4018 + #define HYUNDAI_ID 0xAD /* Hyundai */ #define HYUNDAI_HY29F400T 0x23 /* Same as HY29F400AT */ #define HYUNDAI_HY29F800B 0x58 /* Same as HY29F800AB */

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Re: [flashrom] [PATCH] Add GigaDevice GD25QXX Series Support
by Uwe Hermann 14 Apr '12

14 Apr '12

Hi, On Tue, Mar 27, 2012 at 09:49:45PM -0400, Justin Chevrier wrote: > Signed-off-by: Justin Chevrier <jchevrier(a)gmail.com> Thanks a lot! The patch looks good, committed in r1520. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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Re: [flashrom] Latest version in console
by Uwe Hermann 14 Apr '12

14 Apr '12

Hi, On Mon, Mar 26, 2012 at 12:58:40AM -0700, Cole Byre wrote: > Hello. I used the Linux command sudo apt-get install flashrom to get > flashrom on Linux mint..but when I run sudo flashrom, it tells me its > version 0.9.4..which is outdated. What is the command to download the > latest version of flashrom? Depends on your distribution. If the version is outdated, the package maintainers have to upgrade to a newer flashrom, and/or you have to upgrade to a more recent version of your distribution. Alternatively, you can also build flashrom manually from source code. See http://flashrom.org/Downloads. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[commit] r1519 - trunk
by repository service 14 Apr '12

14 Apr '12

Author: uwe Date: Sat Apr 14 23:06:31 2012 New Revision: 1519 URL: http://flashrom.org/trac/flashrom/changeset/1519 Log: Minor NetBSD/DragonFly/pkgsrc build instruction update. Add -I/usr/pkg/include to NetBSD/Dragon Fly build example CPPFLAGS. This is needed to pick up libftdi. Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/README Modified: trunk/README ============================================================================== --- trunk/README Sat Apr 14 23:04:03 2012 (r1518) +++ trunk/README Sat Apr 14 23:06:31 2012 (r1519) @@ -83,7 +83,8 @@ To compile on NetBSD or DragonFly BSD, use: ln -s /usr/pkg/include/pciutils pci - gmake CPPFLAGS=-I. LDFLAGS="-L/usr/pkg/lib -Wl,-rpath-link,/usr/pkg/lib" + gmake CPPFLAGS="-I. -I/usr/pkg/include" \ + LDFLAGS="-L/usr/pkg/lib -Wl,-rpath-link,/usr/pkg/lib" To compile on OpenBSD, use:

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[PATCH] minor NetBSD/DragonFly/pkgsrc build instruction update
by Jonathan A. Kollasch 14 Apr '12

14 Apr '12

Add -I/usr/pkg/include to NetBSD/Dragon Fly build example CPPFLAGS. This is needed to pick up libftdi. Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net>

2 1

[commit] r1518 - trunk
by repository service 14 Apr '12

14 Apr '12

Author: uwe Date: Sat Apr 14 23:04:03 2012 New Revision: 1518 URL: http://flashrom.org/trac/flashrom/changeset/1518 Log: Add support for the Numonyx N25Q064 chip. All operations were successfully tested. http://www.flashrom.org/pipermail/flashrom/2012-April/009048.html Signed-off-by: Niklas Söderlund <niklas.soderlund(a)ericsson.com> Acked-by: Idwer Vollering <vidwer(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Tue Mar 13 01:18:19 2012 (r1517) +++ trunk/flashchips.c Sat Apr 14 23:04:03 2012 (r1518) @@ -5010,6 +5010,35 @@ }, { + .vendor = "Numonyx", + .name = "N25Q064", + .bustype = BUS_SPI, + .manufacture_id = ST_ID, + .model_id = ST_N25Q064, + .total_size = 8192, + .page_size = 256, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048 } }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + }, + + { .vendor = "PMC", .name = "Pm25LV010", .bustype = BUS_SPI, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Tue Mar 13 01:18:19 2012 (r1517) +++ trunk/flashchips.h Sat Apr 14 23:04:03 2012 (r1518) @@ -574,6 +574,7 @@ #define ST_M29W010B 0x23 #define ST_M29W040B 0xE3 #define ST_M29W512B 0x27 +#define ST_N25Q064 0xBA17 #define SYNCMOS_MVC_ID 0x40 /* SyncMOS (SM) and Mosel Vitelic Corporation (MVC) */ #define MVC_V29C51000T 0x00

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flashrom April 2012