flashrom December 2012

flashrom@flashrom.org

33 participants
119 discussions

80/100/132 column line width policy
by Carl-Daniel Hailfinger 15 Dec '18

15 Dec '18

Hi, we're hitting the 80 column limit in our code in ways which actually reduce readability for the code. Examples are various multiline messages and complicated nested code where refactoring to a separate function doesn't make sense. Keeping the old 80 column limit is not really an option anymore. Standard terminal sizes have one of 80, 100 or 132 columns. Given the monitor resolutions many people have nowadays, I think it is safe to say that you can fit two xterms with 100 columns horizonally next to each other. 100 columns should also be sufficient for a msg_p* of roughly 80 columns of text. 132 columns provide more leeway, but IMHO that would be too wide for good readability (and my screen can't fit two xterms side-by-side anymore). Of course some files have sections where any column limit is not acceptable (board lists etc.), but the column limit violations should be limited to the affected file sections, not whole files. Comments? I'd like to get this decided today or tomorrow so we know where we need line breaks in Stefan Tauner's new struct flashchip patch. Regards, Carl-Daniel -- http://www.hailfinger.org/

7 9

External programmers
by Carl-Daniel Hailfinger 25 Dec '15

25 Dec '15

Hi, I'm trying to find out which external programmers should be supported next. 1. There was talk of an AVR-based new programmer using the serprog protocol on IRC by someone with the nick "coldelectrons", but I have no idea if he/she is reading this mail. IMHO more hardware using the serprog protocol is always a good idea. 2. All those Willem/Sivava variants. People regularly request those, but I don't think anyone in here owns the hardware. 3. RayeR's SPIPGM. I have a preliminary patch which could work, but I don't have the hardware. Will send the patch to the list soon. 4. LPC^2, Milksop, CheapLPC and other programmers from the Xbox modding community. 5. Dozens of SPI programmer hardware projects scattered over the net. Too many to count, and I'm not sure which of them has more than one user. In general, it seems creating a new programmer hardware design is like writing IRC clients: A nice way to get started in the field. I have no problems merging flashrom support for all of them, but I won't implement support for all of them myself. Regards, Carl-Daniel -- http://www.hailfinger.org/

8 13

Re: [flashrom] flashrom on PowerPC
by Stefan Tauner 20 Nov '15

20 Nov '15

On Wed, 27 Jul 2011 18:20:19 +0200 Mattias Mattsson <vitplister(a)gmail.com> wrote: > Hi all, > > I was able to run flashrom under Linux on PPC (big endian) hardware > with two small modifications in internal.c and processor_enable.c (see > attached patch). Not sure if this is the right way to do it but it > seems to work for me. > i am resending this patch (unchanged) because patchwork did not pick it up correctly. please do send one patch per mail only in the future until we have something really working. :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

FAILED: HM77 (Macbook Pro retina)
by Trammell Hudson 29 Dec '14

29 Dec '14

No changes were written to the executable portions of the ROM. The data regions at 0x2000-0x2FFF, 0x6400-0x67FF, 0xC000-0x14FFF, 0x1C000, 0x3C000, 0x40000-0x4BFFF were overwritten correctly. My firmware image differed only in those regions below 0x190000, so it might have successfully written to the entire 0x0-0x4BFFF (or even higher) space. The ROM image that I was writing had changes in the executable firmware volume starting at 0x190000. These were not written to the ROM. I have successfully rebooted and can reflash via external SPI if necessary for further tests. Output log from flashrom -V during the write process: flashrom v0.9.6.1-r1564 on Darwin 12.0.0 (x86_64) flashrom was built with libpci 3.1.7, GCC 4.2.1 (Based on Apple Inc. build 5658) (LLVM build 2336.1.00), little endian Command line (8 args): ./flashrom -p internal -V -f -o /Volumes/NO NAME/write.log -w /Volumes/NO NAME/mbp101.rom Calibrating delay loop... OS timer resolution is 1 usecs, 1597M loops per second, 10 myus = 9 us, 100 myus = 127 us, 1000 myus = 1003 us, 10000 myus = 9928 us, 4 myus = 4 us, OK. Initializing internal programmer Error accessing low megabyte, 0x100000 bytes at 0x00000000 Failed getting access to coreboot low tables. dmidecode execution unsuccessful - continuing without DMI info Found chipset "Intel HM77" with PCI ID 8086:1e57. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 Root Complex Register Block address = 0xfed1c000 GCS = 0xc21: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 WARNING: SPI Configuration Lockdown activated. Reading OPCODES... done OP Type Pre-OP op[0]: 0x9f, read w/o addr, none op[1]: 0x02, write w/ addr, none op[2]: 0x03, read w/ addr, none op[3]: 0x01, write w/o addr, none op[4]: 0x05, read w/o addr, none op[5]: 0x20, write w/ addr, none op[6]: 0xd8, write w/ addr, none op[7]: 0xff, read w/o addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x06 0x06: 0x0004 (HSFC) HSFC: FGO=0, FCYCLE=2, FDBC=0, SME=0 0x08: 0x00000000 (FADDR) 0x50: 0x0000ffff (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-write. 0x58: 0x07ff0190 FREG1: BIOS region (0x00190000-0x007fffff) is read-write. 0x5C: 0x018f0001 FREG2: Management Engine region (0x00001000-0x0018ffff) is read-write. 0x60: 0x00001fff FREG3: Gigabit Ethernet region is unused. 0x64: 0x00001fff FREG4: Platform Data region is unused. 0x74: 0x866f0190 PR0: WARNING: 0x00190000-0x0066ffff is read-only. 0x78: 0x9fff0692 PR1: WARNING: 0x00692000-0x01ffffff is read-only. 0x7C: 0x00000000 (PR2 is unused) 0x80: 0x00000000 (PR3 is unused) 0x84: 0x00000000 (PR4 is unused) Please send a verbose log to flashrom(a)flashrom.org if this board is not listed on http://flashrom.org/Supported_hardware#Supported_mainboards yet. Writes have been disabled. You can enforce write support with the ich_spi_force programmer option, but it will most likely harm your hardware! If you force flashrom you will get no support if something breaks. 0x90: 0xc4 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xfc4200 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=2, SME=0, SCF=4 0x94: 0x0606 (PREOP) 0x96: 0x3c6c (OPTYPE) 0x98: 0x0103029f (OPMENU) 0x9C: 0xffd82005 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x00800000 (LVSCC) LVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x0, VCL=1 0xC8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 0xD0: 0x00000000 (FPB) Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. === Content Section === FLVALSIG 0x0ff0a55a FLMAP0 0x02040003 FLMAP1 0x12100206 FLMAP2 0x00210120 --- Details --- NR (Number of Regions): 3 FRBA (Flash Region Base Address): 0x040 NC (Number of Components): 1 FCBA (Flash Component Base Address): 0x030 ISL (ICH/PCH Strap Length): 18 FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100 NM (Number of Masters): 3 FMBA (Flash Master Base Address): 0x060 MSL/PSL (MCH/PROC Strap Length): 1 FMSBA (Flash MCH/PROC Strap Base Address): 0x200 === Component Section === FLCOMP 0x64900024 FLILL 0x00000000 --- Details --- Component 1 density: 8 MB Component 2 is not used. Read Clock Frequency: 20 MHz Read ID and Status Clock Freq.: 50 MHz Write and Erase Clock Freq.: 50 MHz Fast Read is supported. Fast Read Clock Frequency: 50 MHz No forbidden opcodes. === Region Section === FLREG0 0x00000000 FLREG1 0x07ff0190 FLREG2 0x018f0001 FLREG3 0x00001fff --- Details --- Region 0 (Descr.) 0x00000000 - 0x00000fff Region 1 (BIOS ) 0x00190000 - 0x007fffff Region 2 (ME ) 0x00001000 - 0x0018ffff Region 3 (GbE ) is unused. === Master Section === FLMSTR1 0xffff0000 FLMSTR2 0xffff0000 FLMSTR3 0xffff0118 --- Details --- Descr. BIOS ME GbE Platf. BIOS rw rw rw rw rw ME rw rw rw rw rw GbE rw rw rw rw rw SPI Read Configuration: prefetching disabled, caching enabled, OK. The following protocols are supported: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon EN25QH32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25Q20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for GigaDevice GD25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Block Protect 3 (BP3) is not set Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found Macronix flash chip "MX25L6405" (8192 kB, SPI) at physical address 0xff800000. Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Numonyx N25Q064, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for SST SST25LF040A, 512 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25LF080A, 1024 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25VF010, 128 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for SST SST25VF040, 512 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for SST SST25VF040B.REMS, 512 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P05, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P10, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Unknown SFDP-capable chip, 0 kB: Invalid OPCODE 0x5a, will not execute. Receiving SFDP signature failed. Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Probing for Generic unknown SPI chip (REMS), 0 kB: Invalid OPCODE 0x90, will not execute. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x34, id2 0x34, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x34, id2 0x34, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x34, id2 0x34, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0x34, id2 0x34, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x34, id2 0x34, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x70, id2 0x0e, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x34, id2 0x34, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x34, id2 0x34, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x70, id2 0x0e, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x34, id2 0x34, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0x34, id2 0x34, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xf8, id2 0x80, id1 is normal flash content, id2 is normal flash content Found Macronix flash chip "MX25L6405" (8192 kB, SPI). Write/erase is not working yet on your programmer in its current configuration. Continuing anyway. Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x00ffff:EERASE FAILED at 0x00001000! Expected=0xff, Read=0x20, failed byte count from 0x00000000-0x0000ffff: 0xada4 ERASE FAILED! Reading current flash chip contents... done. Looking for another erase function. Trying erase function 1... 0x000000-0x00ffff:EW, 0x010000-0x01ffff:EW, 0x020000-0x02ffff:S, 0x030000-0x03ffff:EW, 0x040000-0x04ffff:EW, 0x050000-0x05ffff:S, 0x060000-0x06ffff:S, 0x070000-0x07ffff:S, 0x080000-0x08ffff:S, 0x090000-0x09ffff:S, 0x0a0000-0x0affff:S, 0x0b0000-0x0bffff:S, 0x0c0000-0x0cffff:S, 0x0d0000-0x0dffff:S, 0x0e0000-0x0effff:S, 0x0f0000-0x0fffff:S, 0x100000-0x10ffff:S, 0x110000-0x11ffff:S, 0x120000-0x12ffff:S, 0x130000-0x13ffff:S, 0x140000-0x14ffff:S, 0x150000-0x15ffff:S, 0x160000-0x16ffff:S, 0x170000-0x17ffff:S, 0x180000-0x18ffff:S, 0x190000-0x19ffff:ETransaction error! SSFS: SCIP=0, FDONE=1, FCERR=1, AEL=0 SSFC: SCGO=0, ACS=1, SPOP=0, COP=6, DBC=0, SME=0, SCF=4 Running OPCODE 0xd8 failed at address 0x190000 (payload length was 0). spi_block_erase_d8 failed during command execution at address 0x190000 Reading current flash chip contents... done. Looking for another erase function. Trying erase function 2... 0x000000-0x7fffff:EInvalid OPCODE 0x06, will not execute. spi_chip_erase_60 failed during command execution Reading current flash chip contents... done. Looking for another erase function. Trying erase function 3... 0x000000-0x7fffff:EInvalid OPCODE 0x06, will not execute. spi_chip_erase_c7 failed during command execution Looking for another erase function. No usable erase functions left. FAILED! Uh oh. Erase/write failed. Checking if anything changed. Your flash chip is in an unknown state. Get help on IRC at chat.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org with the subject "FAILED: <your board name>"! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! Restoring MMIO space at 0x104cb28a0 Restoring PCI config space for 00:1f:0 reg 0xdc

3 3

[PATCH] Add en29lv640b
by Rudolf Marek 10 Aug '14

10 Aug '14

Hi Following patch adds the en29lv640b which needs special command sequences in 8 bit mode. Also, 8 bit programming needs actually 16bit double byte program. The chip is found on bifferboard. Please check the patch and let me know. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Thanks Rudolf

4 6

[PATCH] Rename programmer registration functions
by Carl-Daniel Hailfinger 19 Jul '14

19 Jul '14

register_programmer suggests that we register a programmer. However, that function registers a master for a given bus type, and a programmer may support multiple masters (e.g. SPI, FWH). Rename a few other functions to be more consistent. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-rename_register_programmer_register_master/ogp_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/ogp_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/ogp_spi.c (Arbeitskopie) @@ -140,7 +140,7 @@ if (register_shutdown(ogp_spi_shutdown, NULL)) return 1; - if (bitbang_spi_init(&bitbang_spi_master_ogp)) + if (register_spi_bitbang_master(&bitbang_spi_master_ogp)) return 1; return 0; Index: flashrom-rename_register_programmer_register_master/flash.h =================================================================== --- flashrom-rename_register_programmer_register_master/flash.h (Revision 1587) +++ flashrom-rename_register_programmer_register_master/flash.h (Arbeitskopie) @@ -154,7 +154,7 @@ chipaddr virtual_memory; /* Some flash devices have an additional register space. */ chipaddr virtual_registers; - struct registered_programmer *pgm; + struct registered_master *pgm; }; #define TEST_UNTESTED 0 @@ -215,7 +215,7 @@ void map_flash_registers(struct flashctx *flash); int read_memmapped(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int erase_flash(struct flashctx *flash); -int probe_flash(struct registered_programmer *pgm, int startchip, struct flashctx *fill_flash, int force); +int probe_flash(struct registered_master *pgm, int startchip, struct flashctx *fill_flash, int force); int read_flash_to_file(struct flashctx *flash, const char *filename); int min(int a, int b); int max(int a, int b); Index: flashrom-rename_register_programmer_register_master/drkaiser.c =================================================================== --- flashrom-rename_register_programmer_register_master/drkaiser.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/drkaiser.c (Arbeitskopie) @@ -45,7 +45,7 @@ chipaddr addr); static uint8_t drkaiser_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_drkaiser = { +static const struct par_master par_programmer_drkaiser = { .chip_readb = drkaiser_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -85,7 +85,7 @@ return 1; max_rom_decode.parallel = 128 * 1024; - register_par_programmer(&par_programmer_drkaiser, BUS_PARALLEL); + register_par_master(&par_programmer_drkaiser, BUS_PARALLEL); return 0; } Index: flashrom-rename_register_programmer_register_master/it87spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/it87spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/it87spi.c (Arbeitskopie) @@ -113,7 +113,7 @@ static int it8716f_spi_chip_write_256(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); -static const struct spi_programmer spi_programmer_it87xx = { +static const struct spi_master spi_programmer_it87xx = { .type = SPI_CONTROLLER_IT87XX, .max_data_read = MAX_DATA_UNSPECIFIED, .max_data_write = MAX_DATA_UNSPECIFIED, @@ -199,7 +199,7 @@ if (internal_buses_supported & BUS_SPI) msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); /* FIXME: Add the SPI bus or replace the other buses with it? */ - register_spi_programmer(&spi_programmer_it87xx); + register_spi_master(&spi_programmer_it87xx); return 0; } Index: flashrom-rename_register_programmer_register_master/gfxnvidia.c =================================================================== --- flashrom-rename_register_programmer_register_master/gfxnvidia.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/gfxnvidia.c (Arbeitskopie) @@ -66,7 +66,7 @@ chipaddr addr); static uint8_t gfxnvidia_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_gfxnvidia = { +static const struct par_master par_programmer_gfxnvidia = { .chip_readb = gfxnvidia_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -112,7 +112,7 @@ /* Write/erase doesn't work. */ programmer_may_write = 0; - register_par_programmer(&par_programmer_gfxnvidia, BUS_PARALLEL); + register_par_master(&par_programmer_gfxnvidia, BUS_PARALLEL); return 0; } Index: flashrom-rename_register_programmer_register_master/nicrealtek.c =================================================================== --- flashrom-rename_register_programmer_register_master/nicrealtek.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/nicrealtek.c (Arbeitskopie) @@ -40,7 +40,7 @@ static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr); static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_nicrealtek = { +static const struct par_master par_programmer_nicrealtek = { .chip_readb = nicrealtek_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -82,7 +82,7 @@ if (register_shutdown(nicrealtek_shutdown, NULL)) return 1; - register_par_programmer(&par_programmer_nicrealtek, BUS_PARALLEL); + register_par_master(&par_programmer_nicrealtek, BUS_PARALLEL); return 0; } Index: flashrom-rename_register_programmer_register_master/serprog.c =================================================================== --- flashrom-rename_register_programmer_register_master/serprog.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/serprog.c (Arbeitskopie) @@ -320,7 +320,7 @@ unsigned char *readarr); static int serprog_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); -static struct spi_programmer spi_programmer_serprog = { +static struct spi_master spi_programmer_serprog = { .type = SPI_CONTROLLER_SERPROG, .max_data_read = MAX_DATA_READ_UNLIMITED, .max_data_write = MAX_DATA_WRITE_UNLIMITED, @@ -337,7 +337,7 @@ const chipaddr addr); static void serprog_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len); -static const struct par_programmer par_programmer_serprog = { +static const struct par_master par_programmer_serprog = { .chip_readb = serprog_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -673,10 +673,9 @@ sp_streamed_transmit_bytes = 0; sp_opbuf_usage = 0; if (serprog_buses_supported & BUS_SPI) - register_spi_programmer(&spi_programmer_serprog); + register_spi_master(&spi_programmer_serprog); if (serprog_buses_supported & BUS_NONSPI) - register_par_programmer(&par_programmer_serprog, - serprog_buses_supported & BUS_NONSPI); + register_par_master(&par_programmer_serprog, serprog_buses_supported & BUS_NONSPI); return 0; } Index: flashrom-rename_register_programmer_register_master/bitbang_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/bitbang_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/bitbang_spi.c (Arbeitskopie) @@ -63,7 +63,7 @@ const unsigned char *writearr, unsigned char *readarr); -static const struct spi_programmer spi_programmer_bitbang = { +static const struct spi_master spi_programmer_bitbang = { .type = SPI_CONTROLLER_BITBANG, .max_data_read = MAX_DATA_READ_UNLIMITED, .max_data_write = MAX_DATA_WRITE_UNLIMITED, @@ -82,9 +82,9 @@ } #endif -int bitbang_spi_init(const struct bitbang_spi_master *master) +int register_spi_bitbang_master(const struct bitbang_spi_master *master) { - struct spi_programmer pgm = spi_programmer_bitbang; + struct spi_master pgm = spi_programmer_bitbang; /* BITBANG_SPI_INVALID is 0, so if someone forgot to initialize ->type, * we catch it here. Same goes for missing initialization of bitbanging * functions. @@ -99,7 +99,7 @@ } pgm.data = master; - register_spi_programmer(&pgm); + register_spi_master(&pgm); /* Only mess with the bus if we're sure nobody else uses it. */ bitbang_spi_request_bus(master); Index: flashrom-rename_register_programmer_register_master/satamv.c =================================================================== --- flashrom-rename_register_programmer_register_master/satamv.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/satamv.c (Arbeitskopie) @@ -46,7 +46,7 @@ chipaddr addr); static uint8_t satamv_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_satamv = { +static const struct par_master par_programmer_satamv = { .chip_readb = satamv_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -156,7 +156,7 @@ /* 512 kByte with two 8-bit latches, and * 4 MByte with additional 3-bit latch. */ max_rom_decode.parallel = 4 * 1024 * 1024; - register_par_programmer(&par_programmer_satamv, BUS_PARALLEL); + register_par_master(&par_programmer_satamv, BUS_PARALLEL); return 0; Index: flashrom-rename_register_programmer_register_master/dummyflasher.c =================================================================== --- flashrom-rename_register_programmer_register_master/dummyflasher.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/dummyflasher.c (Arbeitskopie) @@ -119,7 +119,7 @@ static void dummy_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len); -static const struct spi_programmer spi_programmer_dummyflasher = { +static const struct spi_master spi_programmer_dummyflasher = { .type = SPI_CONTROLLER_DUMMY, .max_data_read = MAX_DATA_READ_UNLIMITED, .max_data_write = MAX_DATA_UNSPECIFIED, @@ -130,7 +130,7 @@ .write_aai = default_spi_write_aai, }; -static const struct par_programmer par_programmer_dummy = { +static const struct par_master par_programmer_dummy = { .chip_readb = dummy_chip_readb, .chip_readw = dummy_chip_readw, .chip_readl = dummy_chip_readl, @@ -401,12 +401,10 @@ return 1; } if (dummy_buses_supported & (BUS_PARALLEL | BUS_LPC | BUS_FWH)) - register_par_programmer(&par_programmer_dummy, - dummy_buses_supported & - (BUS_PARALLEL | BUS_LPC | - BUS_FWH)); + register_par_master(&par_programmer_dummy, + dummy_buses_supported & (BUS_PARALLEL | BUS_LPC | BUS_FWH)); if (dummy_buses_supported & BUS_SPI) - register_spi_programmer(&spi_programmer_dummyflasher); + register_spi_master(&spi_programmer_dummyflasher); return 0; } Index: flashrom-rename_register_programmer_register_master/cli_classic.c =================================================================== --- flashrom-rename_register_programmer_register_master/cli_classic.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/cli_classic.c (Arbeitskopie) @@ -421,10 +421,10 @@ msg_pdbg("The following protocols are supported: %s.\n", tempstr); free(tempstr); - for (j = 0; j < registered_programmer_count; j++) { + for (j = 0; j < registered_master_count; j++) { startchip = 0; while (chipcount < ARRAY_SIZE(flashes)) { - startchip = probe_flash(&registered_programmers[j], startchip, &flashes[chipcount], 0); + startchip = probe_flash(&registered_masters[j], startchip, &flashes[chipcount], 0); if (startchip == -1) break; chipcount++; @@ -446,12 +446,12 @@ "automatically.\n"); } if (force && read_it && chip_to_probe) { - struct registered_programmer *pgm; + struct registered_master *pgm; int compatible_programmers = 0; msg_cinfo("Force read (-f -r -c) requested, pretending the chip is there:\n"); /* This loop just counts compatible controllers. */ - for (j = 0; j < registered_programmer_count; j++) { - pgm = &registered_programmers[j]; + for (j = 0; j < registered_master_count; j++) { + pgm = &registered_masters[j]; /* chip is still set from the chip_to_probe earlier in this function. */ if (pgm->buses_supported & chip->bustype) compatible_programmers++; @@ -464,8 +464,8 @@ if (compatible_programmers > 1) msg_cinfo("More than one compatible controller found for the requested flash " "chip, using the first one.\n"); - for (j = 0; j < registered_programmer_count; j++) { - pgm = &registered_programmers[j]; + for (j = 0; j < registered_master_count; j++) { + pgm = &registered_masters[j]; startchip = probe_flash(pgm, 0, &flashes[0], 1); if (startchip != -1) break; Index: flashrom-rename_register_programmer_register_master/internal.c =================================================================== --- flashrom-rename_register_programmer_register_master/internal.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/internal.c (Arbeitskopie) @@ -145,7 +145,7 @@ const chipaddr addr); static void internal_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len); -static const struct par_programmer par_programmer_internal = { +static const struct par_master par_programmer_internal = { .chip_readb = internal_chip_readb, .chip_readw = internal_chip_readw, .chip_readl = internal_chip_readl, @@ -348,7 +348,7 @@ * The error code might have been a warning only. */ #if defined(__i386__) || defined(__x86_64__) || defined (__mips) - register_par_programmer(&par_programmer_internal, internal_buses_supported); + register_par_master(&par_programmer_internal, internal_buses_supported); return 0; #else msg_perr("Your platform is not supported yet for the internal " Index: flashrom-rename_register_programmer_register_master/ichspi.c =================================================================== --- flashrom-rename_register_programmer_register_master/ichspi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/ichspi.c (Arbeitskopie) @@ -1514,7 +1514,7 @@ msg_gspew("resulted in 0x%08x.\n", mmio_readl(addr)); } -static const struct spi_programmer spi_programmer_ich7 = { +static const struct spi_master spi_programmer_ich7 = { .type = SPI_CONTROLLER_ICH7, .max_data_read = 64, .max_data_write = 64, @@ -1525,7 +1525,7 @@ .write_aai = default_spi_write_aai, }; -static const struct spi_programmer spi_programmer_ich9 = { +static const struct spi_master spi_programmer_ich9 = { .type = SPI_CONTROLLER_ICH9, .max_data_read = 64, .max_data_write = 64, @@ -1536,7 +1536,7 @@ .write_aai = default_spi_write_aai, }; -static const struct opaque_programmer opaque_programmer_ich_hwseq = { +static const struct opaque_master opaque_programmer_ich_hwseq = { .max_data_read = 64, .max_data_write = 64, .probe = ich_hwseq_probe, @@ -1623,7 +1623,7 @@ } ich_init_opcodes(); ich_set_bbar(0); - register_spi_programmer(&spi_programmer_ich7); + register_spi_master(&spi_programmer_ich7); break; case CHIPSET_ICH8: default: /* Future version might behave the same */ @@ -1808,9 +1808,9 @@ } hwseq_data.size_comp0 = getFCBA_component_density(&desc, 0); hwseq_data.size_comp1 = getFCBA_component_density(&desc, 1); - register_opaque_programmer(&opaque_programmer_ich_hwseq); + register_opaque_master(&opaque_programmer_ich_hwseq); } else { - register_spi_programmer(&spi_programmer_ich9); + register_spi_master(&spi_programmer_ich9); } break; } @@ -1833,7 +1833,7 @@ return 0; } -static const struct spi_programmer spi_programmer_via = { +static const struct spi_master spi_programmer_via = { .type = SPI_CONTROLLER_VIA, .max_data_read = 16, .max_data_write = 16, @@ -1854,7 +1854,7 @@ /* Not sure if it speaks all these bus protocols. */ internal_buses_supported = BUS_LPC | BUS_FWH; ich_generation = CHIPSET_ICH7; - register_spi_programmer(&spi_programmer_via); + register_spi_master(&spi_programmer_via); msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2)); Index: flashrom-rename_register_programmer_register_master/nicintel_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/nicintel_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/nicintel_spi.c (Arbeitskopie) @@ -196,7 +196,7 @@ if (register_shutdown(nicintel_spi_shutdown, NULL)) return 1; - if (bitbang_spi_init(&bitbang_spi_master_nicintel)) + if (register_spi_bitbang_master(&bitbang_spi_master_nicintel)) return 1; return 0; Index: flashrom-rename_register_programmer_register_master/opaque.c =================================================================== --- flashrom-rename_register_programmer_register_master/opaque.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/opaque.c (Arbeitskopie) @@ -50,9 +50,9 @@ return flash->pgm->opaque.erase(flash, blockaddr, blocklen); } -int register_opaque_programmer(const struct opaque_programmer *pgm) +int register_opaque_master(const struct opaque_master *pgm) { - struct registered_programmer rpgm; + struct registered_master rpgm; if (!pgm->probe || !pgm->read || !pgm->write || !pgm->erase) { msg_perr("%s called with incomplete programmer definition. " Index: flashrom-rename_register_programmer_register_master/nicnatsemi.c =================================================================== --- flashrom-rename_register_programmer_register_master/nicnatsemi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/nicnatsemi.c (Arbeitskopie) @@ -41,7 +41,7 @@ chipaddr addr); static uint8_t nicnatsemi_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_nicnatsemi = { +static const struct par_master par_programmer_nicnatsemi = { .chip_readb = nicnatsemi_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -75,7 +75,7 @@ * functions below wants to be 0x0000FFFF. */ max_rom_decode.parallel = 131072; - register_par_programmer(&par_programmer_nicnatsemi, BUS_PARALLEL); + register_par_master(&par_programmer_nicnatsemi, BUS_PARALLEL); return 0; } Index: flashrom-rename_register_programmer_register_master/dediprog.c =================================================================== --- flashrom-rename_register_programmer_register_master/dediprog.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/dediprog.c (Arbeitskopie) @@ -736,7 +736,7 @@ return millivolt; } -static const struct spi_programmer spi_programmer_dediprog = { +static const struct spi_master spi_programmer_dediprog = { .type = SPI_CONTROLLER_DEDIPROG, .max_data_read = MAX_DATA_UNSPECIFIED, .max_data_write = MAX_DATA_UNSPECIFIED, @@ -854,7 +854,7 @@ return 1; } - register_spi_programmer(&spi_programmer_dediprog); + register_spi_master(&spi_programmer_dediprog); /* RE leftover, leave in until the driver is complete. */ #if 0 Index: flashrom-rename_register_programmer_register_master/rayer_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/rayer_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/rayer_spi.c (Arbeitskopie) @@ -175,7 +175,7 @@ /* Get the initial value before writing to any line. */ lpt_outbyte = INB(lpt_iobase); - if (bitbang_spi_init(&bitbang_spi_master_rayer)) + if (register_spi_bitbang_master(&bitbang_spi_master_rayer)) return 1; return 0; Index: flashrom-rename_register_programmer_register_master/it85spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/it85spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/it85spi.c (Arbeitskopie) @@ -276,7 +276,7 @@ const unsigned char *writearr, unsigned char *readarr); -static const struct spi_programmer spi_programmer_it85xx = { +static const struct spi_master spi_programmer_it85xx = { .type = SPI_CONTROLLER_IT85XX, .max_data_read = 64, .max_data_write = 64, @@ -312,7 +312,7 @@ * a debug message about it. */ /* Set this as SPI controller. */ - register_spi_programmer(&spi_programmer_it85xx); + register_spi_master(&spi_programmer_it85xx); } return ret; } Index: flashrom-rename_register_programmer_register_master/buspirate_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/buspirate_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/buspirate_spi.c (Arbeitskopie) @@ -132,7 +132,7 @@ static int buspirate_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); -static const struct spi_programmer spi_programmer_buspirate = { +static const struct spi_master spi_programmer_buspirate = { .type = SPI_CONTROLLER_BUSPIRATE, .max_data_read = 12, .max_data_write = 12, @@ -407,7 +407,7 @@ return 1; } - register_spi_programmer(&spi_programmer_buspirate); + register_spi_master(&spi_programmer_buspirate); return 0; } Index: flashrom-rename_register_programmer_register_master/linux_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/linux_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/linux_spi.c (Arbeitskopie) @@ -46,7 +46,7 @@ static int linux_spi_write_256(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); -static const struct spi_programmer spi_programmer_linux = { +static const struct spi_master spi_programmer_linux = { .type = SPI_CONTROLLER_LINUX, .max_data_read = MAX_DATA_UNSPECIFIED, /* TODO? */ .max_data_write = MAX_DATA_UNSPECIFIED, /* TODO? */ @@ -115,7 +115,7 @@ return 1; } - register_spi_programmer(&spi_programmer_linux); + register_spi_master(&spi_programmer_linux); return 0; } Index: flashrom-rename_register_programmer_register_master/atahpt.c =================================================================== --- flashrom-rename_register_programmer_register_master/atahpt.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/atahpt.c (Arbeitskopie) @@ -45,7 +45,7 @@ chipaddr addr); static uint8_t atahpt_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_atahpt = { +static const struct par_master par_programmer_atahpt = { .chip_readb = atahpt_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -80,7 +80,7 @@ if (register_shutdown(atahpt_shutdown, NULL)) return 1; - register_par_programmer(&par_programmer_atahpt, BUS_PARALLEL); + register_par_master(&par_programmer_atahpt, BUS_PARALLEL); return 0; } Index: flashrom-rename_register_programmer_register_master/nic3com.c =================================================================== --- flashrom-rename_register_programmer_register_master/nic3com.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/nic3com.c (Arbeitskopie) @@ -60,7 +60,7 @@ chipaddr addr); static uint8_t nic3com_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_nic3com = { +static const struct par_master par_programmer_nic3com = { .chip_readb = nic3com_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -116,7 +116,7 @@ return 1; max_rom_decode.parallel = 128 * 1024; - register_par_programmer(&par_programmer_nic3com, BUS_PARALLEL); + register_par_master(&par_programmer_nic3com, BUS_PARALLEL); return 0; } Index: flashrom-rename_register_programmer_register_master/spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/spi.c (Arbeitskopie) @@ -167,9 +167,9 @@ return flash->pgm->spi.write_aai(flash, buf, start, len); } -int register_spi_programmer(const struct spi_programmer *pgm) +int register_spi_master(const struct spi_master *pgm) { - struct registered_programmer rpgm; + struct registered_master rpgm; if (!pgm->write_aai || !pgm->write_256 || !pgm->read || !pgm->command || !pgm->multicommand || Index: flashrom-rename_register_programmer_register_master/ft2232_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/ft2232_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/ft2232_spi.c (Arbeitskopie) @@ -142,7 +142,7 @@ const unsigned char *writearr, unsigned char *readarr); -static const struct spi_programmer spi_programmer_ft2232 = { +static const struct spi_master spi_programmer_ft2232 = { .type = SPI_CONTROLLER_FT2232, .max_data_read = 64 * 1024, .max_data_write = 256, @@ -356,7 +356,7 @@ // msg_pdbg("\nft2232 chosen\n"); - register_spi_programmer(&spi_programmer_ft2232); + register_spi_master(&spi_programmer_ft2232); return 0; Index: flashrom-rename_register_programmer_register_master/satasii.c =================================================================== --- flashrom-rename_register_programmer_register_master/satasii.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/satasii.c (Arbeitskopie) @@ -43,7 +43,7 @@ static void satasii_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr); static uint8_t satasii_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_satasii = { +static const struct par_master par_programmer_satasii = { .chip_readb = satasii_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -90,7 +90,7 @@ if (register_shutdown(satasii_shutdown, NULL)) return 1; - register_par_programmer(&par_programmer_satasii, BUS_PARALLEL); + register_par_master(&par_programmer_satasii, BUS_PARALLEL); return 0; } Index: flashrom-rename_register_programmer_register_master/wbsio_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/wbsio_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/wbsio_spi.c (Arbeitskopie) @@ -68,7 +68,7 @@ static int wbsio_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); -static const struct spi_programmer spi_programmer_wbsio = { +static const struct spi_master spi_programmer_wbsio = { .type = SPI_CONTROLLER_WBSIO, .max_data_read = MAX_DATA_UNSPECIFIED, .max_data_write = MAX_DATA_UNSPECIFIED, @@ -90,7 +90,7 @@ msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is " "1024 kB!\n", __func__); max_rom_decode.spi = 1024 * 1024; - register_spi_programmer(&spi_programmer_wbsio); + register_spi_master(&spi_programmer_wbsio); return 0; } Index: flashrom-rename_register_programmer_register_master/pony_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/pony_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/pony_spi.c (Arbeitskopie) @@ -158,7 +158,7 @@ return 1; } - if (bitbang_spi_init(&bitbang_spi_master_pony)) { + if (register_spi_bitbang_master(&bitbang_spi_master_pony)) { return 1; } return 0; Index: flashrom-rename_register_programmer_register_master/nicintel.c =================================================================== --- flashrom-rename_register_programmer_register_master/nicintel.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/nicintel.c (Arbeitskopie) @@ -48,7 +48,7 @@ chipaddr addr); static uint8_t nicintel_chip_readb(const struct flashctx *flash, const chipaddr addr); -static const struct par_programmer par_programmer_nicintel = { +static const struct par_master par_programmer_nicintel = { .chip_readb = nicintel_chip_readb, .chip_readw = fallback_chip_readw, .chip_readl = fallback_chip_readl, @@ -110,7 +110,7 @@ pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR); max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE; - register_par_programmer(&par_programmer_nicintel, BUS_PARALLEL); + register_par_master(&par_programmer_nicintel, BUS_PARALLEL); return 0; Index: flashrom-rename_register_programmer_register_master/sb600spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/sb600spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/sb600spi.c (Arbeitskopie) @@ -194,7 +194,7 @@ return 0; } -static const struct spi_programmer spi_programmer_sb600 = { +static const struct spi_master spi_programmer_sb600 = { .type = SPI_CONTROLLER_SB600, .max_data_read = 8, .max_data_write = 5, @@ -320,7 +320,7 @@ /* Bring the FIFO to a clean state. */ reset_internal_fifo_pointer(); - register_spi_programmer(&spi_programmer_sb600); + register_spi_master(&spi_programmer_sb600); return 0; } Index: flashrom-rename_register_programmer_register_master/mcp6x_spi.c =================================================================== --- flashrom-rename_register_programmer_register_master/mcp6x_spi.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/mcp6x_spi.c (Arbeitskopie) @@ -161,7 +161,7 @@ (status >> MCP6X_SPI_GRANT) & 0x1); mcp_gpiostate = status & 0xff; - if (bitbang_spi_init(&bitbang_spi_master_mcp6x)) { + if (register_spi_bitbang_master(&bitbang_spi_master_mcp6x)) { /* This should never happen. */ msg_perr("MCP6X bitbang SPI master init failed!\n"); return 1; Index: flashrom-rename_register_programmer_register_master/programmer.c =================================================================== --- flashrom-rename_register_programmer_register_master/programmer.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/programmer.c (Arbeitskopie) @@ -96,10 +96,10 @@ return; } -int register_par_programmer(const struct par_programmer *pgm, +int register_par_master(const struct par_master *pgm, const enum chipbustype buses) { - struct registered_programmer rpgm; + struct registered_master rpgm; if (!pgm->chip_writeb || !pgm->chip_writew || !pgm->chip_writel || !pgm->chip_writen || !pgm->chip_readb || !pgm->chip_readw || !pgm->chip_readl || !pgm->chip_readn) { @@ -115,20 +115,20 @@ } /* The limit of 4 is totally arbitrary. */ -#define PROGRAMMERS_MAX 4 -struct registered_programmer registered_programmers[PROGRAMMERS_MAX]; -int registered_programmer_count = 0; +#define MASTERS_MAX 4 +struct registered_master registered_masters[MASTERS_MAX]; +int registered_master_count = 0; -/* This function copies the struct registered_programmer parameter. */ -int register_programmer(struct registered_programmer *pgm) +/* This function copies the struct registered_master parameter. */ +int register_programmer(struct registered_master *pgm) { - if (registered_programmer_count >= PROGRAMMERS_MAX) { + if (registered_master_count >= MASTERS_MAX) { msg_perr("Tried to register more than %i programmer " - "interfaces.\n", PROGRAMMERS_MAX); + "interfaces.\n", MASTERS_MAX); return ERROR_FLASHROM_LIMIT; } - registered_programmers[registered_programmer_count] = *pgm; - registered_programmer_count++; + registered_masters[registered_master_count] = *pgm; + registered_master_count++; return 0; } @@ -138,8 +138,8 @@ int i; enum chipbustype ret = BUS_NONE; - for (i = 0; i < registered_programmer_count; i++) - ret |= registered_programmers[i].buses_supported; + for (i = 0; i < registered_master_count; i++) + ret |= registered_masters[i].buses_supported; return ret; } Index: flashrom-rename_register_programmer_register_master/flashrom.c =================================================================== --- flashrom-rename_register_programmer_register_master/flashrom.c (Revision 1587) +++ flashrom-rename_register_programmer_register_master/flashrom.c (Arbeitskopie) @@ -949,7 +949,7 @@ return 1; } -int probe_flash(struct registered_programmer *pgm, int startchip, struct flashctx *flash, int force) +int probe_flash(struct registered_master *pgm, int startchip, struct flashctx *flash, int force) { const struct flashchip *chip; unsigned long base = 0; Index: flashrom-rename_register_programmer_register_master/programmer.h =================================================================== --- flashrom-rename_register_programmer_register_master/programmer.h (Revision 1587) +++ flashrom-rename_register_programmer_register_master/programmer.h (Arbeitskopie) @@ -445,7 +445,7 @@ #endif /* bitbang_spi.c */ -int bitbang_spi_init(const struct bitbang_spi_master *master); +int register_spi_bitbang_master(const struct bitbang_spi_master *master); /* buspirate_spi.c */ #if CONFIG_BUSPIRATE_SPI == 1 @@ -517,7 +517,7 @@ #define MAX_DATA_UNSPECIFIED 0 #define MAX_DATA_READ_UNLIMITED 64 * 1024 #define MAX_DATA_WRITE_UNLIMITED 256 -struct spi_programmer { +struct spi_master { enum spi_controller type; unsigned int max_data_read; unsigned int max_data_write; @@ -538,7 +538,7 @@ int default_spi_read(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int default_spi_write_256(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); int default_spi_write_aai(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len); -int register_spi_programmer(const struct spi_programmer *programmer); +int register_spi_master(const struct spi_master *programmer); /* The following enum is needed by ich_descriptor_tool and ich* code. */ enum ich_chipset { @@ -580,7 +580,7 @@ #endif /* opaque.c */ -struct opaque_programmer { +struct opaque_master { int max_data_read; int max_data_write; /* Specific functions for this programmer */ @@ -590,7 +590,7 @@ int (*erase) (struct flashctx *flash, unsigned int blockaddr, unsigned int blocklen); const void *data; }; -int register_opaque_programmer(const struct opaque_programmer *pgm); +int register_opaque_master(const struct opaque_master *pgm); /* programmer.c */ int noop_shutdown(void); @@ -603,7 +603,7 @@ uint16_t fallback_chip_readw(const struct flashctx *flash, const chipaddr addr); uint32_t fallback_chip_readl(const struct flashctx *flash, const chipaddr addr); void fallback_chip_readn(const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len); -struct par_programmer { +struct par_master { void (*chip_writeb) (const struct flashctx *flash, uint8_t val, chipaddr addr); void (*chip_writew) (const struct flashctx *flash, uint16_t val, chipaddr addr); void (*chip_writel) (const struct flashctx *flash, uint32_t val, chipaddr addr); @@ -614,18 +614,18 @@ void (*chip_readn) (const struct flashctx *flash, uint8_t *buf, const chipaddr addr, size_t len); const void *data; }; -int register_par_programmer(const struct par_programmer *pgm, const enum chipbustype buses); -struct registered_programmer { +int register_par_master(const struct par_master *pgm, const enum chipbustype buses); +struct registered_master { enum chipbustype buses_supported; union { - struct par_programmer par; - struct spi_programmer spi; - struct opaque_programmer opaque; + struct par_master par; + struct spi_master spi; + struct opaque_master opaque; }; }; -extern struct registered_programmer registered_programmers[]; -extern int registered_programmer_count; -int register_programmer(struct registered_programmer *pgm); +extern struct registered_master registered_masters[]; +extern int registered_master_count; +int register_programmer(struct registered_master *pgm); /* serprog.c */ #if CONFIG_SERPROG == 1 -- http://www.hailfinger.org/

3 4

[PATCH] Add IT8212F as programmer
by Kyösti Mälkki 01 Jun '14

01 Jun '14

This PCI PATA controller can use 3V parallel flash upto 128kB. My card was identified as: PCI 1283:8212, subsystem 1283:0001. and labelled as: Innovision Multimedia LTD. EIO ATA133 RAID (DM-8401 Ver A) This particular card did not require setting of any GPIO signals to enable flash writing. My card has Pm39LV512 in PLCC32 package without socket. Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Index: flashrom-it8212f/Makefile =================================================================== --- flashrom-it8212f/Makefile (revision 1539) +++ flashrom-it8212f/Makefile (working copy) @@ -177,7 +177,12 @@ else override CONFIG_SATAMV = no endif +ifeq ($(CONFIG_IT8212), yes) +UNSUPPORTED_FEATURES += CONFIG_IT8212=yes +else +override CONFIG_IT8212 = no endif +endif ifeq ($(TARGET_OS), libpayload) CPPFLAGS += -DSTANDALONE @@ -344,6 +349,9 @@ # Enable Linux spidev interface by default. We disable it on non-Linux targets. CONFIG_LINUX_SPI ?= yes +# Always enable ITE IT8212F PATA controllers for now. +CONFIG_IT8212 ?= yes + # Disable wiki printing by default. It is only useful if you have wiki access. CONFIG_PRINT_WIKI ?= no @@ -503,6 +511,12 @@ PROGRAMMER_OBJS += linux_spi.o endif +ifeq ($(CONFIG_IT8212), yes) +FEATURE_CFLAGS += -D'CONFIG_IT8212=1' +PROGRAMMER_OBJS += it8212.o +NEED_PCI := yes +endif + ifeq ($(NEED_SERIAL), yes) LIB_OBJS += serial.o endif Index: flashrom-it8212f/print_wiki.c =================================================================== --- flashrom-it8212f/print_wiki.c (revision 1539) +++ flashrom-it8212f/print_wiki.c (working copy) @@ -338,6 +338,9 @@ #if CONFIG_SATAMV == 1 print_supported_pcidevs_wiki(satas_mv); #endif +#if CONFIG_IT8212 == 1 + print_supported_pcidevs_wiki(ata_it82); +#endif printf("\n|}\n"); } Index: flashrom-it8212f/it8212.c =================================================================== --- flashrom-it8212f/it8212.c (revision 0) +++ flashrom-it8212f/it8212.c (revision 0) @@ -0,0 +1,110 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2011 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include "flash.h" +#include "programmer.h" + +static uint8_t *it8212_bar; +static uint8_t it8212_rom_enable = 0; + +#define PCI_VENDOR_ID_ITE 0x1283 + +const struct pcidev_status ata_it82[] = { + {PCI_VENDOR_ID_ITE, 0x8212, OK, "ITE", "8212F PATA RAID"}, + {}, +}; + +#define IT8212_MEMMAP_SIZE (128 * 1024) +#define IT8212_MEMMAP_MASK (IT8212_MEMMAP_SIZE - 1) + +static void it8212_chip_writeb(const struct flashctx *flash, uint8_t val, + chipaddr addr); +static uint8_t it8212_chip_readb(const struct flashctx *flash, + const chipaddr addr); +static const struct par_programmer par_programmer_it8212 = { + .chip_readb = it8212_chip_readb, + .chip_readw = fallback_chip_readw, + .chip_readl = fallback_chip_readl, + .chip_readn = fallback_chip_readn, + .chip_writeb = it8212_chip_writeb, + .chip_writew = fallback_chip_writew, + .chip_writel = fallback_chip_writel, + .chip_writen = fallback_chip_writen, +}; + +static int it8212_shutdown(void *data) +{ + if (! it8212_rom_enable) { + uintptr_t addr = pci_read_long(pcidev_dev, PCI_ROM_ADDRESS); + pci_write_long(pcidev_dev, PCI_ROM_ADDRESS, addr & ~0x01); + } + physunmap(it8212_bar, IT8212_MEMMAP_SIZE); + pci_cleanup(pacc); + release_io_perms(); + return 0; +} + +int it8212_init(void) +{ + uintptr_t addr; + + /* Needed only for PCI accesses on some platforms. + * FIXME: Refactor that into get_mem_perms/get_io_perms/get_pci_perms? + */ + get_io_perms(); + + /* No need to check for errors, pcidev_init() will not return in case + * of errors. + */ + addr = pcidev_init(PCI_ROM_ADDRESS, ata_it82); + + it8212_bar = physmap("IT8212F flash", addr, IT8212_MEMMAP_SIZE); + if (it8212_bar == ERROR_PTR) + goto error_out_unmap; + if (register_shutdown(it8212_shutdown, NULL)) + return 1; + + /* To restore ROM BAR enable once we are done. */ + it8212_rom_enable = addr & 0x01; + if (! it8212_rom_enable) + pci_write_long(pcidev_dev, PCI_ROM_ADDRESS, addr | 0x01); + + max_rom_decode.parallel = IT8212_MEMMAP_SIZE; + register_par_programmer(&par_programmer_it8212, BUS_PARALLEL); + return 0; + +error_out_unmap: + physunmap(it8212_bar, IT8212_MEMMAP_SIZE); + pci_cleanup(pacc); + release_io_perms(); + return 1; +} + +static void it8212_chip_writeb(const struct flashctx *flash, uint8_t val, + chipaddr addr) +{ + pci_mmio_writeb(val, it8212_bar + (addr & IT8212_MEMMAP_MASK)); +} + +static uint8_t it8212_chip_readb(const struct flashctx *flash, + const chipaddr addr) +{ + return pci_mmio_readb(it8212_bar + (addr & IT8212_MEMMAP_MASK)); +} Index: flashrom-it8212f/flashrom.c =================================================================== --- flashrom-it8212f/flashrom.c (revision 1539) +++ flashrom-it8212f/flashrom.c (working copy) @@ -261,6 +261,16 @@ }, #endif +#if CONFIG_IT8212 == 1 + { + .name = "it8212", + .init = it8212_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + {}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; Index: flashrom-it8212f/programmer.h =================================================================== --- flashrom-it8212f/programmer.h (revision 1539) +++ flashrom-it8212f/programmer.h (working copy) @@ -87,6 +87,9 @@ #if CONFIG_LINUX_SPI == 1 PROGRAMMER_LINUX_SPI, #endif +#if CONFIG_IT8212 == 1 + PROGRAMMER_IT8212, +#endif PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -456,6 +459,12 @@ int linux_spi_init(void); #endif +/* it8212.c */ +#if CONFIG_IT8212 == 1 +int it8212_init(void); +extern const struct pcidev_status ata_it82[]; +#endif + /* dediprog.c */ #if CONFIG_DEDIPROG == 1 int dediprog_init(void); Index: flashrom-it8212f/print.c =================================================================== --- flashrom-it8212f/print.c (revision 1539) +++ flashrom-it8212f/print.c (working copy) @@ -538,6 +538,11 @@ programmer_table[PROGRAMMER_LINUX_SPI].name); msg_ginfo("Device files /dev/spidev*.*\n"); #endif +#if CONFIG_IT8212 == 1 + msg_ginfo("\nSupported devices for the %s programmer:\n", + programmer_table[PROGRAMMER_IT8212].name); + print_supported_pcidevs(ata_it82); +#endif } #if CONFIG_INTERNAL == 1

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[PATCH] Unlock ST M50FW002 correctly
by Carl-Daniel Hailfinger 29 May '14

29 May '14

Unlock ST M50FW002 correctly Refactor ST M50 family unlocking TODO: Unify write_lockbits_49fl00x() and unlock_block_stm50() and unlock_w39_fwh_block() and unlock_82802ab() and write_lockbits_block_49lfxxxc(). They all use exactly the same mechanism, but they don't share any code. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-stm50fw002_unlock/flashchips.c =================================================================== --- flashrom-stm50fw002_unlock/flashchips.c (Revision 1437) +++ flashrom-stm50fw002_unlock/flashchips.c (Arbeitskopie) @@ -7523,9 +7523,9 @@ .total_size = 256, .page_size = 64 * 1024, .feature_bits = FEATURE_REGISTERMAP, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_82802ab, - .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (sst49lfxxxc.c) */ + .probe_timing = TIMING_IGNORED, /* routine doesn't use probe_timing (82802ab.c) */ .block_erasers = { { @@ -7536,9 +7536,12 @@ {16 * 1024, 1}, }, .block_erase = erase_block_82802ab, + }, { + .eraseblocks = { {256 * 1024, 1}, }, + .block_erase = NULL, /* Only in A/A mux mode */ } }, - .unlock = unlock_stm50flw0x0x, + .unlock = unlock_stm50fw002, .write = write_82802ab, .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program & erase */ Index: flashrom-stm50fw002_unlock/stm50flw0x0x.c =================================================================== --- flashrom-stm50fw002_unlock/stm50flw0x0x.c (Revision 1437) +++ flashrom-stm50fw002_unlock/stm50flw0x0x.c (Arbeitskopie) @@ -3,6 +3,7 @@ * * Copyright (C) 2008 Claus Gindhart <claus.gindhart(a)kontron.com> * Copyright (C) 2009 Sean Nelson <audiohacked(a)gmail.com> + * Copyright (C) 2011 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -31,6 +32,21 @@ #include "flashchips.h" #include "chipdrivers.h" +#define STM50_UNLOCKED 0x00 + +static int unlock_block_stm50(struct flashchip *flash, int offset) +{ + chipaddr lock = flash->virtual_registers + offset + 2; + + msg_cdbg("Unlocking at 0x%x\n", offset); + chip_writeb(STM50_UNLOCKED, lock); + if (chip_readb(lock) != STM50_UNLOCKED) { + msg_cerr("Cannot unlock at 0x%x\n", offset); + return -1; + } + return 0; +} + /* * claus.gindhart(a)kontron.com * The ST M50FLW080B and STM50FLW080B chips have to be unlocked, @@ -38,8 +54,6 @@ */ static int unlock_block_stm50flw0x0x(struct flashchip *flash, int offset) { - chipaddr wrprotect = flash->virtual_registers + 2; - static const uint8_t unlock_sector = 0x00; int j; /* @@ -58,22 +72,12 @@ || (offset == 0xF0000)) { // unlock each 4k-sector - for (j = 0; j < 0x10000; j += 0x1000) { - msg_cdbg("unlocking at 0x%x\n", offset + j); - chip_writeb(unlock_sector, wrprotect + offset + j); - if (chip_readb(wrprotect + offset + j) != unlock_sector) { - msg_cerr("Cannot unlock sector @ 0x%x\n", - offset + j); + for (j = 0; j < 0x10000; j += 0x1000) + if (unlock_block_stm50(flash, offset + j)) return -1; - } - } } else { - msg_cdbg("unlocking at 0x%x\n", offset); - chip_writeb(unlock_sector, wrprotect + offset); - if (chip_readb(wrprotect + offset) != unlock_sector) { - msg_cerr("Cannot unlock sector @ 0x%x\n", offset); + if (unlock_block_stm50(flash, offset)) return -1; - } } return 0; @@ -93,6 +97,27 @@ return 0; } +/* FIXME: Should this be moved to a generic walk_unlockregions()? */ +int unlock_stm50fw002(struct flashchip *flash) +{ + static const struct eraseblock unlockregions[4] = { + {64 * 1024, 3}, + {32 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}}; + int i, j; + int addr = 0; + + for (i = 0; i < 4; i++) { + for (j = 0; j < unlockregions[i].count; j++) { + if (unlock_block_stm50(flash, addr)) + return 1; + addr += unlockregions[i].size; + } + } + return 0; +} + /* This function is unused. */ int erase_sector_stm50flw0x0x(struct flashchip *flash, unsigned int sector, unsigned int sectorsize) { Index: flashrom-stm50fw002_unlock/chipdrivers.h =================================================================== --- flashrom-stm50fw002_unlock/chipdrivers.h (Revision 1437) +++ flashrom-stm50fw002_unlock/chipdrivers.h (Arbeitskopie) @@ -146,5 +146,6 @@ /* stm50flw0x0x.c */ int erase_sector_stm50flw0x0x(struct flashchip *flash, unsigned int block, unsigned int blocksize); int unlock_stm50flw0x0x(struct flashchip *flash); +int unlock_stm50fw002(struct flashchip *flash); #endif /* !__CHIPDRIVERS_H__ */ -- http://www.hailfinger.org/

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Re: [flashrom] [PATCH] dummyflasher.c: add an "empty" parameter and initialize with random bytes by default
by Carl-Daniel Hailfinger 09 May '14

09 May '14

Am 21.07.2011 17:54 schrieb Stefan Tauner: > previously the dummies were initialized to be empty (all ones), which makes writes skip > erasing altogether. with this patch the default is to fill it with random bytes instead and the > old behavior can be enforced with stating "empty=yes" on the command line. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Does the following not work for you? dd if=/dev/urandom bs=1k count=4k of=oldimage.bin flashrom -p dummy:emulate=SST25VF032B,image=oldimage.bin -w newimage.bin Regards, Carl-Daniel -- http://www.hailfinger.org/

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Add timeout check to SPI bitbang bus request
by Carl-Daniel Hailfinger 29 Apr '14

29 Apr '14

Hi Iain, your Intel 82540EM which hangs on a flashrom run should spew "Timeout!" messages with this patch. It would be nice if you could tell us how long it waits for each chip probe so I can adjust the timeout value. Please note that this patch will _not_ fix the underlying issue, but I believe that an endless loop on possibly broken hardware is worse than aborting. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-bitbang_timeout/flash.h =================================================================== --- flashrom-bitbang_timeout/flash.h (Revision 1185) +++ flashrom-bitbang_timeout/flash.h (Arbeitskopie) @@ -35,6 +35,9 @@ #define ERROR_PTR ((void*)-1) +/* Error codes */ +#define TIMEOUT_ERROR -101 + typedef unsigned long chipaddr; int register_shutdown(void (*function) (void *data), void *data); Index: flashrom-bitbang_timeout/bitbang_spi.c =================================================================== --- flashrom-bitbang_timeout/bitbang_spi.c (Revision 1185) +++ flashrom-bitbang_timeout/bitbang_spi.c (Arbeitskopie) @@ -53,10 +53,11 @@ return bitbang_spi_master->get_miso(); } -static void bitbang_spi_request_bus(void) +static int bitbang_spi_request_bus(void) { if (bitbang_spi_master->request_bus) - bitbang_spi_master->request_bus(); + return bitbang_spi_master->request_bus(); + return 0; } static void bitbang_spi_release_bus(void) @@ -86,7 +87,7 @@ bitbang_spi_master = master; bitbang_spi_half_period = halfperiod; - /* FIXME: Run bitbang_spi_request_bus here or in programmer init? */ + /* FIXME: Run bitbang_spi_request_bus here or per command? */ bitbang_spi_set_cs(1); bitbang_spi_set_sck(0); bitbang_spi_set_mosi(0); @@ -131,13 +132,15 @@ int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr) { - int i; + int i, ret; /* FIXME: Run bitbang_spi_request_bus here or in programmer init? * Requesting and releasing the SPI bus is handled in here to allow the * programmer to use its own SPI engine for native accesses. */ - bitbang_spi_request_bus(); + ret = bitbang_spi_request_bus(); + if (ret) + return ret; bitbang_spi_set_cs(0); for (i = 0; i < writecnt; i++) bitbang_spi_readwrite_byte(writearr[i]); Index: flashrom-bitbang_timeout/nicintel_spi.c =================================================================== --- flashrom-bitbang_timeout/nicintel_spi.c (Revision 1185) +++ flashrom-bitbang_timeout/nicintel_spi.c (Arbeitskopie) @@ -58,6 +58,8 @@ // #define FL_BUSY 30 // #define FL_ER 31 +#define MAX_REQUEST_LOOPS 10000 + uint8_t *nicintel_spibar; const struct pcidev_status nics_intel_spi[] = { @@ -68,16 +70,27 @@ {}, }; -static void nicintel_request_spibus(void) +static void nicintel_release_spibus(void); + +static int nicintel_request_spibus(void) { uint32_t tmp; + int i = 0; tmp = pci_mmio_readl(nicintel_spibar + FLA); tmp |= 1 << FL_REQ; pci_mmio_writel(tmp, nicintel_spibar + FLA); /* Wait until we are allowed to use the SPI bus. */ - while (!(pci_mmio_readl(nicintel_spibar + FLA) & (1 << FL_GNT))) ; + while (!(pci_mmio_readl(nicintel_spibar + FLA) & (1 << FL_GNT))) { + if (i++ > MAX_REQUEST_LOOPS) { + nicintel_release_spibus(); + msg_perr("%s: Timeout! Aborting.\n", __func__); + return TIMEOUT_ERROR; + } + } + + return 0; } static void nicintel_release_spibus(void) Index: flashrom-bitbang_timeout/mcp6x_spi.c =================================================================== --- flashrom-bitbang_timeout/mcp6x_spi.c (Revision 1185) +++ flashrom-bitbang_timeout/mcp6x_spi.c (Arbeitskopie) @@ -40,22 +40,37 @@ #define MCP6X_SPI_REQUEST 0 #define MCP6X_SPI_GRANT 8 +#define MAX_REQUEST_LOOPS 10000 + void *mcp6x_spibar = NULL; /* Cached value of last GPIO state. */ static uint8_t mcp_gpiostate; -static void mcp6x_request_spibus(void) +static void mcp6x_release_spibus(void); + +static int mcp6x_request_spibus(void) { + int i = 0; + mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); mcp_gpiostate |= 1 << MCP6X_SPI_REQUEST; mmio_writeb(mcp_gpiostate, mcp6x_spibar + 0x530); /* Wait until we are allowed to use the SPI bus. */ - while (!(mmio_readw(mcp6x_spibar + 0x530) & (1 << MCP6X_SPI_GRANT))) ; + while (!(mmio_readw(mcp6x_spibar + 0x530) & (1 << MCP6X_SPI_GRANT))) { + if (i++ > MAX_REQUEST_LOOPS) { + /* Update the cache. */ + mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); + mcp6x_release_spibus(); + msg_perr("%s: Timeout! Aborting.\n", __func__); + return TIMEOUT_ERROR; + } + } /* Update the cache. */ mcp_gpiostate = mmio_readb(mcp6x_spibar + 0x530); + return 0; } static void mcp6x_release_spibus(void) Index: flashrom-bitbang_timeout/programmer.h =================================================================== --- flashrom-bitbang_timeout/programmer.h (Revision 1185) +++ flashrom-bitbang_timeout/programmer.h (Arbeitskopie) @@ -131,7 +131,7 @@ void (*set_sck) (int val); void (*set_mosi) (int val); int (*get_miso) (void); - void (*request_bus) (void); + int (*request_bus) (void); void (*release_bus) (void); }; -- http://www.hailfinger.org/

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flashrom December 2012