August 2011 - flashrom - mail.coreboot.org

flashrom -V
by Daniel Housar Aug. 10, 2011

Aug. 10, 2011

MainBoard: MSI K9N Neo V2 (K9N Neo-F V2) NVIDIA nForce 520 (MCP65), socket AM2 (AMD Athlon64/X2) flashrom v0.9.4-r1395 on Linux 3.0.0+ (x86_64), built with libpci 3.1.7, GCC 4.6.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 655M loops per second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 990 us, 10000 myus = 10339 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "MSI" DMI string system-product-name: "MS-7369" DMI string system-version: "1.0" DMI string baseboard-manufacturer: "MSI" DMI string baseboard-product-name: "MS-7369" DMI string baseboard-version: "1.0" DMI string chassis-type: "Desktop" Found chipset "NVIDIA MCP65" with PCI ID 10de:0441. This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Flash bus type is SPI SPI on this chipset is WIP. Please report any success or failure by mailing us the verbose output to flashrom(a)flashrom.org, thanks! Found SMBus device 10de:0446 at 00:01:1 MCP SPI BAR is at 0xfec80000 Mapping NVIDIA MCP6x SPI at 0xfec80000, unaligned size 0x544. SPI control is 0x0002, req=0, gnt=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found Macronix flash chip "MX25L8005" (1024 kB, SPI) at physical address 0xfff00000. Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF010.REMS, 128 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF040.REMS, 512 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25LF040A.RES, 512 kB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P05.RES, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P10.RES, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xc2, id2 0x13 No operations were specified.

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Re: [flashrom] [PATCH 2/4] add ICH/PCH flash descriptor decoding via FDOC/FDOD
by Carl-Daniel Hailfinger Aug. 9, 2011

Aug. 9, 2011

Am 21.07.2011 01:24 schrieb Stefan Tauner: > based on the work of Matthias 'mazzoo' Wenzel this patch adds pretty > printing of those ICH/PCH flash descriptors that are cached/mapped > by the chipset (and which are therefore reachable via FDOC/FDOD > registers). > > this includes the following: > - content descriptor: > describes the image and some generic properties (number of regions, > offset of regions, offset of which regions, or something else? How does this relate to region descriptor(s)? > PCH/ICH and MCH/PROC strap offsets and lengths) > - component descriptor: > identify the different SPI Flash Components and their capabilities. > components==chips? If yes, please say so in the changelog (and maybe code comments). > - region descriptor > similarly to a partition table this describes the different regions > One common descriptor for all regions or one descriptor per region? > - master descriptor > defines access rights of the individual regions > > this is only a part of the data included in the descriptor. other > information can be retreived retrieved > from a complete binary dump of the descriptor image only. > What's a descriptor image? > this patch also adds macros and pretty printing for "Vendor Specific > Component Capabilities" registers: > there are two of them: lower and upper. they describe the properties > of the address space divided by FPBA We really need some place (maybe as comment in ich_decriptor.h?) where all Intel acronyms are expanded and explained. > (which allows to use multiple > flash chips or partitions with different properties). the properties > of flash chips supported by the ME are stored in the same format in > a descriptor table. "a descriptor table" implies there is more than one. Which one is it? > a later patch will uses them outside of ichspi.c > which is also the reason why the prettyprinting function and the > register bit macros are not defined in ichspi.c but ich_descriptors.h. > > TODO: > - file naming and partitioning was not discussed. we may want a ichspi.h. > and/or rename ichspi.c to ich_spi.c or similar... > I'd say naming of the files is the least of our worries. We'll reorganize all flashrom code in a directory structure anyway, and that's when we can rename files if needed. > - straps of ich8 (only) Why not ICH7 (no descriptors?) or ICH9 and later (no datasheets?) > could be printed at runtime via FDOC/FDOD. > worth it? no, imo. Agreed. > but reading out the descriptor region manually and > parsing it with the following patch may be useful? > following patch == 3/4? Once we support true partial reads with the help of layout files, this should be possible. > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Please note that I didn't check the code for correctness against the datasheets nor did I check the code flow. The comments below are what I noticed from reading the patch alone. The message levels of most messages really need to be discussed... a flood of msg_dbg is not necessarily a good idea, downgrading a lot of them to dbg2 may improve said flood. That said, msg_[cpg]dbg2 is now in the tree, so the dbg1 hack can go away. Looking again at your messagelevels, maybe dbg1->dbg2 and dbg2->spew would be in order. All ich specific structs should have an ich_ prefix in the struct name to avoid polluting the global namespace. > --- > Makefile | 3 +- > ich_descriptors.c | 247 +++++++++++++++++++++++++++++++++++++++++++++++++ > ich_descriptors.h | 264 +++++++++++++++++++++++++++++++++++++++++++++++++++++ > ichspi.c | 39 ++++++-- > 4 files changed, 544 insertions(+), 9 deletions(-) > create mode 100644 ich_descriptors.c > create mode 100644 ich_descriptors.h > > diff --git a/Makefile b/Makefile > index a35df06..7f73452 100644 > --- a/Makefile > +++ b/Makefile > @@ -308,7 +308,8 @@ ifeq ($(CONFIG_INTERNAL), yes) > FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' > PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o > ifeq ($(ARCH),"x86") > -PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o > +PROGRAMMER_OBJS += it87spi.o it85spi.o sb600spi.o wbsio_spi.o mcp6x_spi.o > +PROGRAMMER_OBJS += ichspi.o ich_descriptors.o > else > endif > NEED_PCI := yes > diff --git a/ich_descriptors.c b/ich_descriptors.c > new file mode 100644 > index 0000000..cf77601 > --- /dev/null > +++ b/ich_descriptors.c > @@ -0,0 +1,247 @@ > +/* > + * This file is part of the flashrom project. > + * > + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> > + * Copyright (c) 2011 Stefan Tauner > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + */ > + > +#if defined(__i386__) || defined(__x86_64__) > + > +#include "ich_descriptors.h" > +#include "flash.h" /* for msg_* */ > + > +#define getFCBA(cont) (((cont)->FLMAP0 << 4) & 0x00000ff0) > +#define getFRBA(cont) (((cont)->FLMAP0 >> 12) & 0x00000ff0) > +#define getFMBA(cont) (((cont)->FLMAP1 << 4) & 0x00000ff0) > +#define getFISBA(cont) (((cont)->FLMAP1 >> 12) & 0x00000ff0) > +#define getFMSBA(cont) (((cont)->FLMAP2 << 4) & 0x00000ff0) > + > +void prettyprint_ich_descriptors(enum chipset cs, const struct flash_descriptors *desc) > (enum ich_chipset cs, const struct ich_flash_descriptors *desc) > +{ > Please try to handle cs at least somewhat. Check if it has the expected value, and skip descriptor decoding (with a dbg/dbg2 message telling the user about it) if the result would be wrong (i.e. for the wrong ICH family). > + prettyprint_ich_descriptor_content(&desc->content); > + prettyprint_ich_descriptor_component(desc); > + prettyprint_ich_descriptor_region(&desc->region); > + prettyprint_ich_descriptor_master(&desc->master); > +} > + > +void prettyprint_ich_descriptor_content(const struct flash_content *cont) > ich_flash_content Does this work on all chipsets? > +{ > + msg_pdbg1("=== Content Section ===\n"); > + msg_pdbg1("FLVALSIG 0x%08x\n", cont->FLVALSIG); > + msg_pdbg1("FLMAP0 0x%08x\n", cont->FLMAP0); > + msg_pdbg1("FLMAP1 0x%08x\n", cont->FLMAP1); > + msg_pdbg1("FLMAP2 0x%08x\n", cont->FLMAP2); > + msg_pdbg1("\n"); > dbg1->dbg, or maybe ->dbg2 to reduce output. The message level discussion should not hold back this patch. > + > + msg_pdbg2("--- Details ---\n"); > + msg_pdbg2("NR (Number of Regions): %5d\n", > + cont->NR + 1); > + msg_pdbg2("FRBA (Flash Region Base Address): 0x%03x\n", > + getFRBA(cont)); > + msg_pdbg2("NC (Number of Components): %5d\n", > + cont->NC + 1); > + msg_pdbg2("FCBA (Flash Component Base Address): 0x%03x\n", > + getFCBA(cont)); > + msg_pdbg2("ISL (ICH/PCH Strap Length): %5d\n", > + cont->ISL); > + msg_pdbg2("FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x%03x\n", > + getFISBA(cont)); > + msg_pdbg2("NM (Number of Masters): %5d\n", > + cont->NM + 1); > + msg_pdbg2("FMBA (Flash Master Base Address): 0x%03x\n", > + getFMBA(cont)); > + msg_pdbg2("MSL/PSL (MCH/PROC Strap Length): %5d\n", > + cont->MSL); > + msg_pdbg2("FMSBA (Flash MCH/PROC Strap Base Address): 0x%03x\n", > + getFMSBA(cont)); > + msg_pdbg2("\n"); > +} > + > +void prettyprint_ich_descriptor_component(const struct flash_descriptors *desc) > ich_flash_descriptors Which chipset is handled by this function? > +{ > + const char * const str_freq[8] = { > static? Or is that useless here? > + "20 MHz", /* 000 */ > + "33 MHz", /* 001 */ > + "reserved", /* 010 */ > + "reserved", /* 011 */ > + "50 MHz", /* 100 */ > Mh. Is 50 MHz available on all descriptor capable chipsets? > + "reserved", /* 101 */ > + "reserved", /* 110 */ > + "reserved" /* 111 */ > + }; > + const char * const str_mem[8] = { > static? > + "512 kB", /* 000 */ > + " 1 MB", /* 001 */ > + " 2 MB", /* 010 */ > + " 4 MB", /* 011 */ > + " 8 MB", /* 100 */ > + " 16 MB", /* 101 */ > + "reserved", /* 110 */ > + "reserved", /* 111 */ > + }; > + > + msg_pdbg1("=== Component Section ===\n"); > + msg_pdbg1("FLCOMP 0x%08x\n", desc->component.FLCOMP); > + msg_pdbg1("FLILL 0x%08x\n", desc->component.FLILL ); > + msg_pdbg1("\n"); > + > + msg_pdbg2("--- Details ---\n"); > + msg_pdbg2("Component 1 density: %s\n", > + str_mem[desc->component.comp1_density]); > + if (desc->content.NC) > + msg_pdbg2("Component 2 density: %s\n", > + str_mem[desc->component.comp2_density]); > + else > + msg_pdbg2("Component 2 is not used.\n"); > + msg_pdbg2("Read Clock Frequency: %s\n", > + str_freq[desc->component.freq_read]); > + msg_pdbg2("Read ID and Status Clock Freq.: %s\n", > + str_freq[desc->component.freq_read_id]); > + msg_pdbg2("Write and Erase Clock Freq.: %s\n", > + str_freq[desc->component.freq_write]); > + msg_pdbg2("Fast Read is %ssupported.\n", > + desc->component.fastread ? "" : "not "); > + if (desc->component.fastread) > + msg_pdbg2("Fast Read Clock Frequency: %s\n", > + str_freq[desc->component.freq_fastread]); > + if (desc->component.FLILL == 0) > + msg_pdbg2("No forbidden opcodes.\n"); > + else { > + msg_pdbg2("Invalid instruction 0: 0x%02x\n", > + desc->component.invalid_instr0); > + msg_pdbg2("Invalid instruction 1: 0x%02x\n", > + desc->component.invalid_instr1); > + msg_pdbg2("Invalid instruction 2: 0x%02x\n", > + desc->component.invalid_instr2); > + msg_pdbg2("Invalid instruction 3: 0x%02x\n", > + desc->component.invalid_instr3); > + } > + msg_pdbg2("\n"); > +} > + > +static void pprint_freg(const struct flash_region *reg, uint32_t i) > ich_flash_region Which chipset? Or is the code generic? > +{ > + const char *const region_names[5] = { > + "Descr.", "BIOS", "ME", "GbE", "Platf." > + }; > + uint32_t base = ICH_FREG_BASE(reg->FLREGs[i]); > + uint32_t limit = ICH_FREG_LIMIT(reg->FLREGs[i]); > + msg_pdbg2("Region %d (%-6s) ", i, region_names[i]); > + if (base > limit) > + msg_pdbg2("is unused.\n"); > + else > + msg_pdbg2("0x%08x - 0x%08x\n", base, limit | 0x0fff); > +} > + > +void prettyprint_ich_descriptor_region(const struct flash_region *reg) > ich_flash_region Chipset specific or generic? > +{ > + uint8_t i; > + msg_pdbg1("=== Region Section ===\n"); > + for (i = 0; i < 5; i++) > + msg_pdbg1("FLREG%d 0x%08x\n", i, reg->FLREGs[i]); > + msg_pdbg1("\n"); > + > + msg_pdbg2("--- Details ---\n"); > + for (i = 0; i < 5; i++) > + pprint_freg(reg, i); > + msg_pdbg2("\n"); > +} > + > +void prettyprint_ich_descriptor_master(const struct flash_master *mstr) > ich_flash_master > +{ > + msg_pdbg1("=== Master Section ===\n"); > + msg_pdbg1("FLMSTR1 0x%08x\n", mstr->FLMSTR1); > + msg_pdbg1("FLMSTR2 0x%08x\n", mstr->FLMSTR2); > + msg_pdbg1("FLMSTR3 0x%08x\n", mstr->FLMSTR3); > + msg_pdbg1("\n"); > + > + msg_pdbg2("--- Details ---\n"); > + msg_pdbg2(" Descr. BIOS ME GbE Platf.\n"); > + msg_pdbg2("BIOS %c%c %c%c %c%c %c%c %c%c\n", > + (mstr->BIOS_descr_r) ?'r':' ', (mstr->BIOS_descr_w) ?'w':' ', > + (mstr->BIOS_BIOS_r) ?'r':' ', (mstr->BIOS_BIOS_w) ?'w':' ', > + (mstr->BIOS_ME_r) ?'r':' ', (mstr->BIOS_ME_w) ?'w':' ', > + (mstr->BIOS_GbE_r) ?'r':' ', (mstr->BIOS_GbE_w) ?'w':' ', > + (mstr->BIOS_plat_r) ?'r':' ', (mstr->BIOS_plat_w) ?'w':' '); > + msg_pdbg2("ME %c%c %c%c %c%c %c%c %c%c\n", > + (mstr->ME_descr_r) ?'r':' ', (mstr->ME_descr_w) ?'w':' ', > + (mstr->ME_BIOS_r) ?'r':' ', (mstr->ME_BIOS_w) ?'w':' ', > + (mstr->ME_ME_r) ?'r':' ', (mstr->ME_ME_w) ?'w':' ', > + (mstr->ME_GbE_r) ?'r':' ', (mstr->ME_GbE_w) ?'w':' ', > + (mstr->ME_plat_r) ?'r':' ', (mstr->ME_plat_w) ?'w':' '); > + msg_pdbg2("GbE %c%c %c%c %c%c %c%c %c%c\n", > + (mstr->GbE_descr_r) ?'r':' ', (mstr->GbE_descr_w) ?'w':' ', > + (mstr->GbE_BIOS_r) ?'r':' ', (mstr->GbE_BIOS_w) ?'w':' ', > + (mstr->GbE_ME_r) ?'r':' ', (mstr->GbE_ME_w) ?'w':' ', > + (mstr->GbE_GbE_r) ?'r':' ', (mstr->GbE_GbE_w) ?'w':' ', > + (mstr->GbE_plat_r) ?'r':' ', (mstr->GbE_plat_w) ?'w':' '); > + msg_pdbg2("\n"); > +} > + > +void prettyprint_ich9_reg_vscc(uint32_t reg_val) > +{ > + pprint_reg_hex(VSCC, BES, reg_val, ", "); > + pprint_reg(VSCC, WG, reg_val, ", "); > + pprint_reg(VSCC, WSR, reg_val, ", "); > + pprint_reg(VSCC, WEWS, reg_val, ", "); > + pprint_reg_hex(VSCC, EO, reg_val, ", "); > + pprint_reg(VSCC, VCL, reg_val, "\n"); > +} > + > +static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) > +{ > + uint32_t control = 0; > + control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS; > + control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI; > + *(volatile uint32_t *) (spibar + ICH9_REG_FDOC) = control; > volatile is absolutely no-go outside hwaccess.c. Use mmio_write[bwl] or the littleendian variant of mmio_write[bwl] instead. > + return *(volatile uint32_t *)(spibar + ICH9_REG_FDOD); > Same here. Use mmio_read[bwl] instead. > +} > + > +void read_ich_descriptors_via_fdo(void *spibar, struct flash_descriptors *desc) > +{ > + msg_pdbg1("Reading flash descriptors " > + "mapped by the chipset via FDOC/FDOD..."); > + /* content section */ > + desc->content.FLVALSIG = read_descriptor_reg(0, 0, spibar); > + desc->content.FLMAP0 = read_descriptor_reg(0, 1, spibar); > + desc->content.FLMAP1 = read_descriptor_reg(0, 2, spibar); > + desc->content.FLMAP2 = read_descriptor_reg(0, 3, spibar); > + > + /* component section */ > + desc->component.FLCOMP = read_descriptor_reg(1, 0, spibar); > + desc->component.FLILL = read_descriptor_reg(1, 1, spibar); > + desc->component.FLPB = read_descriptor_reg(1, 2, spibar); > + > + /* region section */ > + desc->region.FLREGs[0] = read_descriptor_reg(2, 0, spibar); > + desc->region.FLREGs[1] = read_descriptor_reg(2, 1, spibar); > + desc->region.FLREGs[2] = read_descriptor_reg(2, 2, spibar); > + desc->region.FLREGs[3] = read_descriptor_reg(2, 3, spibar); > + desc->region.FLREGs[4] = read_descriptor_reg(2, 4, spibar); > + > + /* master section */ > + desc->master.FLMSTR1 = read_descriptor_reg(3, 0, spibar); > + desc->master.FLMSTR2 = read_descriptor_reg(3, 1, spibar); > + desc->master.FLMSTR3 = read_descriptor_reg(3, 2, spibar); > + > + /* Accessing the strap section via FDOC/D is only possible on ICH8 and > + * reading the upper map is impossible on all chipsets, so don't bother. > + */ > + > + msg_pdbg1(" done\n"); > This seems to be a true flood of output. dbg2 for all callees maybe? > +} > +#endif // defined(__i386__) || defined(__x86_64__) > diff --git a/ich_descriptors.h b/ich_descriptors.h > new file mode 100644 > index 0000000..f248394 > --- /dev/null > +++ b/ich_descriptors.h > @@ -0,0 +1,264 @@ > +/* > + * This file is part of the flashrom project. > + * > + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> > + * Copyright (c) 2011 Stefan Tauner > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + */ > + > +#if defined(__i386__) || defined(__x86_64__) > +#ifndef __ICH_DESCRIPTORS_H__ > +#define __ICH_DESCRIPTORS_H__ 1 > + > +#include <stdint.h> > + > +/* most of the following should probably be in a new file named ichspi.h */ > +#define msg_pdbg1 msg_pdbg > +#define msg_pdbg2 msg_pspew > + > +#define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */ > + /* 0-1: reserved */ > +#define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */ > +#define FDOC_FDSI (0x3f << FDOC_FDSI_OFF) > +#define FDOC_FDSS_OFF 12 /* 12-14: Flash Descriptor Section Select */ > +#define FDOC_FDSS (0x3 << FDOC_FDSS_OFF) > + /* 15-31: reserved */ > + > +#define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */ > + > +/* Field locations and semantics for LVSCC, UVSCC and related words in the flash > + * descriptor are equal therefore they all share the same macros below. */ > +#define VSCC_BES_OFF 0 /* 0-1: Block/Sector Erase Size */ > +#define VSCC_BES (0x3 << VSCC_BES_OFF) > +#define VSCC_WG_OFF 2 /* 2: Write Granularity */ > +#define VSCC_WG (0x1 << VSCC_WG_OFF) > Whitespace damage or is this caused by the leading + in the patch? > +#define VSCC_WSR_OFF 3 /* 3: Write Status Required */ > +#define VSCC_WSR (0x1 << VSCC_WSR_OFF) > +#define VSCC_WEWS_OFF 4 /* 4: Write Enable on Write Status */ > +#define VSCC_WEWS (0x1 << VSCC_WEWS_OFF) > + /* 5-7: reserved */ > +#define VSCC_EO_OFF 8 /* 8-15: Erase Opcode */ > +#define VSCC_EO (0xff << VSCC_EO_OFF) > + /* 16-22: reserved */ > Whitespace damage? > +#define VSCC_VCL_OFF 23 /* 23: Vendor Component Lock */ > +#define VSCC_VCL (0x1 << VSCC_VCL_OFF) > + /* 24-31: reserved */ > + > +#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) > +#define pprint_reg_hex(reg, bit, val, sep) msg_pdbg("%s=0x%x" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) > Please add () around val at the right hand side. > +void prettyprint_ich9_reg_vscc(uint32_t reg_val); > + > +#define ICH_FREG_BASE(flreg) ((flreg << 12) & 0x01fff000) > +#define ICH_FREG_LIMIT(flreg) ((flreg >> 4) & 0x01fff000) > Please add () around flreg at the right hand side. > + > +/* Used to select the right descriptor printing function. > + * Currently only ICH8 and Ibex Peak are supported. > + */ > +enum chipset { > ich_chipset > + CHIPSET_UNKNOWN, > CHIPSET_ICH_UNKNOWN We may need a CHIPSET_UNKNOWN elsewhere... > + CHIPSET_ICH7 = 7, > + CHIPSET_ICH8, > + CHIPSET_ICH9, > + CHIPSET_ICH10, > + CHIPSET_5_SERIES_IBEX_PEAK, > + CHIPSET_6_SERIES_COUGAR_POINT, > + CHIPSET_7_SERIES_PANTHER_POINT > +}; > + > All structs below probably need __attribute__((packed)). > +struct flash_content { > ich_flash_content > + uint32_t FLVALSIG; /* 0x00 */ > + union { /* 0x04 */ > + uint32_t FLMAP0; > + struct { > + uint32_t FCBA :8; > + uint32_t NC :2; > + uint32_t :6; > + uint32_t FRBA :8; > + uint32_t NR :3; > + uint32_t :5; > + }; > + }; > + union { /* 0x08 */ > + uint32_t FLMAP1; > + struct { > + uint32_t FMBA :8; > + uint32_t NM :3; > + uint32_t :5; > + uint32_t FISBA :8; > + uint32_t ISL :8; > + }; > + }; > + union { /* 0x0c */ > + uint32_t FLMAP2; > + struct { > + uint32_t FMSBA :8; > + uint32_t MSL :8; > + uint32_t :16; > + }; > + }; > +}; > + > +struct flash_component { > ich_flash_component > + union { /* 0x00 */ > + uint32_t FLCOMP; > + struct { > + uint32_t comp1_density :3; > + uint32_t comp2_density :3; > + uint32_t :11; > + uint32_t freq_read :3; > + uint32_t fastread :1; > + uint32_t freq_fastread :3; > + uint32_t freq_write :3; > + uint32_t freq_read_id :3; > + uint32_t :2; > + }; > + }; > + union { /* 0x04 */ > + uint32_t FLILL; > + struct { > + uint32_t invalid_instr0; > Really uint32_t? If FLILL is 32 bits, but all invalid_instr are 32 bits as well, the union members have inconsistent sizes. uint8_t invalid_instr0 maybe? > + uint32_t invalid_instr1; > + uint32_t invalid_instr2; > + uint32_t invalid_instr3; > Dito for the other invalid_instr above. > + }; > + }; > + union { /* 0x08 */ > + uint32_t FLPB; > + struct { > + uint32_t FPBA :13; > + uint32_t :19; > + }; > + }; > All code accessing FLPB/FPBA was broken due to the wrong FLILL union size, so if it worked anyway, you have another bug hidden somewhere. > +}; > + > +struct flash_region { > ich_flash_region > + union { > + uint32_t FLREGs[5]; > + struct { > + /* FLREG0 Flash Descriptor */ > + struct { > + uint32_t reg0_base :13; > Are uint32_t bitfields allowed? I thought bitfields were either signed int or unsigned int, but never uint32_t. > + uint32_t :3; > Are anonymous bitfields allowed? > + uint32_t reg0_limit :13; > + uint32_t :3; > + }; > + /* FLREG1 BIOS */ > + struct { > + uint32_t reg1_base :13; > + uint32_t :3; > + uint32_t reg1_limit :13; > + uint32_t :3; > + }; > + /* FLREG2 ME */ > + struct { > + uint32_t reg2_base :13; > + uint32_t :3; > + uint32_t reg2_limit :13; > + uint32_t :3; > + }; > + /* FLREG3 GbE */ > + struct { > + uint32_t reg3_base :13; > + uint32_t :3; > + uint32_t reg3_limit :13; > + uint32_t :3; > + }; > + /* FLREG4 Platform */ > + struct { > + uint32_t reg4_base :13; > + uint32_t :3; > + uint32_t reg4_limit :13; > + uint32_t :3; > + }; > + }; > + }; > +}; > + > +struct flash_master { > ich_flash_master > + union { > + uint32_t FLMSTR1; > + struct { > + uint32_t BIOS_req_ID :16; > + uint32_t BIOS_descr_r :1; > + uint32_t BIOS_BIOS_r :1; > + uint32_t BIOS_ME_r :1; > + uint32_t BIOS_GbE_r :1; > + uint32_t BIOS_plat_r :1; > + uint32_t :3; > + uint32_t BIOS_descr_w :1; > + uint32_t BIOS_BIOS_w :1; > + uint32_t BIOS_ME_w :1; > + uint32_t BIOS_GbE_w :1; > + uint32_t BIOS_plat_w :1; > + uint32_t :3; > + }; > + }; > + union { > + uint32_t FLMSTR2; > + struct { > + uint32_t ME_req_ID :16; > + uint32_t ME_descr_r :1; > + uint32_t ME_BIOS_r :1; > + uint32_t ME_ME_r :1; > + uint32_t ME_GbE_r :1; > + uint32_t ME_plat_r :1; > + uint32_t :3; > + uint32_t ME_descr_w :1; > + uint32_t ME_BIOS_w :1; > + uint32_t ME_ME_w :1; > + uint32_t ME_GbE_w :1; > + uint32_t ME_plat_w :1; > + uint32_t :3; > + }; > + }; > + union { > + uint32_t FLMSTR3; > + struct { > + uint32_t GbE_req_ID :16; > + uint32_t GbE_descr_r :1; > + uint32_t GbE_BIOS_r :1; > + uint32_t GbE_ME_r :1; > + uint32_t GbE_GbE_r :1; > + uint32_t GbE_plat_r :1; > + uint32_t :3; > + uint32_t GbE_descr_w :1; > + uint32_t GbE_BIOS_w :1; > + uint32_t GbE_ME_w :1; > + uint32_t GbE_GbE_w :1; > + uint32_t GbE_plat_w :1; > + uint32_t :3; > + }; > + }; > +}; > + > +struct flash_descriptors { > ich_flash_descriptors > + struct flash_content content; > ich_flash_content > + struct flash_component component; > ich_flash_component > + struct flash_region region; > ich_flash_region > + struct flash_master master; > ich_flash_master > +}; > + > +void prettyprint_ich_descriptors(enum chipset, const struct flash_descriptors *desc); > Missing parameter name for first parameter, and of course ich_chipset ... ich_flash_descriptors. > + > +void prettyprint_ich_descriptor_content(const struct flash_content *content); > +void prettyprint_ich_descriptor_component(const struct flash_descriptors *desc); > +void prettyprint_ich_descriptor_region(const struct flash_region *region); > +void prettyprint_ich_descriptor_master(const struct flash_master *master); > ich_ for all struct names (not for the variable names) > + > +void read_ich_descriptors_via_fdo(void *spibar, struct flash_descriptors *desc); > ich_flash_descriptors > + > +#endif // __ICH_DESCRIPTORS_H__ > +#endif // defined(__i386__) || defined(__x86_64__) > diff --git a/ichspi.c b/ichspi.c > index 2480fa5..b5ee23a 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -30,6 +30,7 @@ > #include "chipdrivers.h" > #include "programmer.h" > #include "spi.h" > +#include "ich_descriptors.h" > > /* ICH9 controller register definition */ > #define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ > @@ -120,6 +121,14 @@ > #define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */ > #define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */ > > +#define ICH9_REG_LVSCC 0xC4 /* 32 Bits Host Lower Vendor Specific Component Capabilities */ > +#define ICH9_REG_UVSCC 0xC8 /* 32 Bits Host Upper Vendor Specific Component Capabilities */ > +/* The individual fields of the VSCC registers are defined in the file > + * ich_descriptors.h. The reason is that the same fields are also used in the > + * flash descriptors to define the properties of the different flash chips > + * supported by the BIOS image. These descriptors are also the source for the > + * registers above. */ > This comment is a bit unclear to me. > + > #define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */ > #define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */ > #define FPB_FPBA (0x1FFF << FPB_FPBA_OFF) > @@ -302,8 +311,6 @@ static void prettyprint_opcodes(OPCODES *ops) > } > } > > -#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) > - > static void prettyprint_ich9_reg_hsfs(uint16_t reg_val) > { > msg_pdbg("HSFS: "); > @@ -1130,9 +1137,6 @@ static int ich_spi_send_multicommand(struct spi_command *cmds) > #define ICH_BRWA(x) ((x >> 8) & 0xff) > #define ICH_BRRA(x) ((x >> 0) & 0xff) > > -#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff) > -#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff) > - > static void do_ich9_spi_frap(uint32_t frap, int i) > { > static const char *const access_names[4] = { > @@ -1159,9 +1163,8 @@ static void do_ich9_spi_frap(uint32_t frap, int i) > return; > } > > - msg_pdbg("0x%08x-0x%08x is %s\n", > - (base << 12), (limit << 12) | 0x0fff, > - access_names[rwperms]); > + msg_pdbg("0x%08x-0x%08x is %s\n", base, (limit | 0x0fff), > + access_names[rwperms]); > } > > static const struct spi_programmer spi_programmer_ich7 = { > @@ -1191,6 +1194,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > uint8_t old, new; > uint16_t spibar_offset, tmp2; > uint32_t tmp; > + int ichspi_desc = 0; > > switch (ich_generation) { > case 7: > @@ -1262,6 +1266,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); > ichspi_lock = 1; > } > + if (tmp2 & HSFS_FDV) > + ichspi_desc = 1; > > tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); > msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); > @@ -1312,9 +1318,26 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); > msg_pdbg("0xA0: 0x%08x (BBAR)\n", > ichspi_bbar); > + > + tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); > + msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); > + msg_pdbg("LVSCC: "); > + prettyprint_ich9_reg_vscc(tmp); > Does the block above work correctly for all ICH8 and later chipsets? > + > + tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); > + msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); > + msg_pdbg("UVSCC: "); > + prettyprint_ich9_reg_vscc(tmp); > Ditto. > + > tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); > msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); > > + msg_pdbg("\n"); > + if (ichspi_desc) { > + struct flash_descriptors desc = {{ 0 }}; > + read_ich_descriptors_via_fdo(ich_spibar, &desc); > Odd code structure, but I see what you're trying to do. Makes sense. > + prettyprint_ich_descriptors(CHIPSET_UNKNOWN, &desc); > Hmmm... I really would like to see this fixed, but it's OK if you want to do that in a followup patch. > + } > ich_init_opcodes(); > break; > default: > Regards, Carl-Daniel -- http://www.hailfinger.org/

2 2

[PATCH] Be optionally seriously pedantic
by Stefan Tauner Aug. 9, 2011

Aug. 9, 2011

This allows to easily test flashrom with numerous compiler warnings enabled. A new variable "PEDANTIC" is introduced which disables the feature by default, but can be overriden on the CLI. Additionally a new phony target "pedantic" is introduced which disables -Werror, enables the pedantic warnings and calls the default target recursively. It also has 'clean' as prerequisite to create consistent output. --- TODO: - make it possible to execute other targets with make pedantic(?) (something like "make pedantic target=djgpp-dos") - refine warnings used Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- Makefile | 21 +++++++++++++++++++-- 1 files changed, 19 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index c72d10a..7289bed 100644 --- a/Makefile +++ b/Makefile @@ -32,11 +32,22 @@ AR ?= ar RANLIB ?= ranlib WARNERROR ?= yes +PEDANTIC ?= no ifeq ($(WARNERROR), yes) CFLAGS += -Werror endif +ifeq ($(PEDANTIC), yes) +CFLAGS += -std=c99 --pedantic -Wextra -fstrict-aliasing\ + -Wmissing-include-dirs -Winit-self -Wswitch-enum \ + -Wundef -Wbad-function-cast -Wcast-qual -Wcast-align -Wconversion \ + -Wstrict-prototypes -Wmissing-declarations -Wredundant-decls\ + \ + -Wno-unused-parameter + # -Wno-missing-field-initializers -Wno-sign-conversion +endif + # Determine the destination processor architecture override ARCH = $(strip $(shell LC_ALL=C $(CC) -E arch.h|grep -v '^\#')) @@ -248,6 +259,7 @@ CLI_OBJS = flashrom.o cli_classic.o cli_output.o print.o PROGRAMMER_OBJS = udelay.o programmer.o all: pciutils features $(PROGRAM)$(EXEC_SUFFIX) + @echo $(CFLAGS) # Set the flashrom version string from the highest revision number # of the checked out flashrom files. @@ -643,8 +655,13 @@ tarball: export @echo Created $(EXPORTDIR)/flashrom-$(RELEASENAME).tar.bz2 djgpp-dos: clean - make CC=i586-pc-msdosdjgpp-gcc STRIP=i586-pc-msdosdjgpp-strip WARNERROR=no OS_ARCH=DOS + $(MAKE) CC=i586-pc-msdosdjgpp-gcc STRIP=i586-pc-msdosdjgpp-strip WARNERROR=no OS_ARCH=DOS + +pedantic: export WARNERROR=no +pedantic: export PEDANTIC=yes +pedantic: clean + $(MAKE) -.PHONY: all clean distclean compiler pciutils features export tarball dos featuresavailable +.PHONY: all clean distclean compiler pciutils features export tarball dos featuresavailable pedantic -include $(OBJS:.o=.d) -- 1.7.1

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Re: [flashrom] [PATCH 1/4] ichspi.c: refactor filling and reading the fdata/spid registers
by Stefan Tauner Aug. 9, 2011

Aug. 9, 2011

On Thu, 21 Jul 2011 01:24:22 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > - add ich_fill_data to fill the chipset registers from an array > - add ich_read_data to copy the data from the chipset register into an array > - replace the existing code with calls to those functions > - minor cosmetic changes > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> tested by david hendrix and finally committed in r1409 \o/ -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

[commit] r1409 - trunk
by repository service Aug. 9, 2011

Aug. 9, 2011

Author: stefanct Date: Tue Aug 9 03:49:34 2011 New Revision: 1409 URL: http://flashrom.org/trac/flashrom/changeset/1409 Log: ichspi.c: refactor filling and reading the fdata/spid registers - add ich_fill_data to fill the chipset registers from an array - add ich_read_data to copy the data from the chipset register into an array - replace the existing code with calls to those functions - minor cosmetic changes Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Sun Aug 7 15:17:20 2011 (r1408) +++ trunk/ichspi.c Tue Aug 9 03:49:34 2011 (r1409) @@ -6,6 +6,7 @@ * Copyright (C) 2008 Dominik Geyer <dominik.geyer(a)kontron.com> * Copyright (C) 2008 coresystems GmbH <info(a)coresystems.de> * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger + * Copyright (C) 2011 Stefan Tauner * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,18 +23,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* - * This module is designed for supporting the devices - * ST M25P40 - * ST M25P80 - * ST M25P16 - * ST M25P32 already tested - * ST M25P64 - * AT 25DF321 already tested - * ... and many more SPI flash devices - * - */ - #if defined(__i386__) || defined(__x86_64__) #include <string.h> @@ -293,7 +282,7 @@ static OPCODES O_EXISTING = {}; /* pretty printing functions */ -static void pretty_print_opcodes(OPCODES *ops) +static void prettyprint_opcodes(OPCODES *ops) { if(ops == NULL) return; @@ -592,6 +581,51 @@ msg_perr("Setting BBAR failed!\n"); } +/* Read len bytes from the fdata/spid register into the data array. + * + * Note that using len > spi_programmer->max_data_read will return garbage or + * may even crash. + */ + static void ich_read_data(uint8_t *data, int len, int reg0_off) + { + int i; + uint32_t temp32 = 0; + + for (i = 0; i < len; i++) { + if ((i % 4) == 0) + temp32 = REGREAD32(reg0_off + i); + + data[i] = (temp32 >> ((i % 4) * 8)) & 0xff; + } +} + +/* Fill len bytes from the data array into the fdata/spid registers. + * + * Note that using len > spi_programmer->max_data_write will trash the registers + * following the data registers. + */ +static void ich_fill_data(const uint8_t *data, int len, int reg0_off) +{ + uint32_t temp32 = 0; + int i; + + if (len <= 0) + return; + + for (i = 0; i < len; i++) { + if ((i % 4) == 0) + temp32 = 0; + + temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8); + + if ((i % 4) == 3) /* 32 bits are full, write them to regs. */ + REGWRITE32(reg0_off + (i - (i % 4)), temp32); + } + i--; + if ((i % 4) != 3) /* Write remaining data to regs. */ + REGWRITE32(reg0_off + (i - (i % 4)), temp32); +} + /* This function generates OPCODES from or programs OPCODES to ICH according to * the chipset's SPI configuration lock. * @@ -627,7 +661,7 @@ } else { curopcodes = curopcodes_done; msg_pdbg("done\n"); - pretty_print_opcodes(curopcodes); + prettyprint_opcodes(curopcodes); msg_pdbg("\n"); return 0; } @@ -638,9 +672,8 @@ { int write_cmd = 0; int timeout; - uint32_t temp32 = 0; + uint32_t temp32; uint16_t temp16; - uint32_t a; uint64_t opmenu; int opcode_index; @@ -664,26 +697,8 @@ REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF) | temp32); /* Program data into SPID0 to N */ - if (write_cmd && (datalength != 0)) { - temp32 = 0; - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = 0; - } - - temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8); - - if ((a % 4) == 3) { - REGWRITE32(ICH7_REG_SPID0 + (a - (a % 4)), - temp32); - } - } - if (((a - 1) % 4) != 3) { - REGWRITE32(ICH7_REG_SPID0 + - ((a - 1) - ((a - 1) % 4)), temp32); - } - - } + if (write_cmd && (datalength != 0)) + ich_fill_data(data, datalength, ICH7_REG_SPID0); /* Assemble SPIS */ temp16 = REGREAD16(ICH7_REG_SPIS); @@ -764,17 +779,8 @@ return 1; } - if ((!write_cmd) && (datalength != 0)) { - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = REGREAD32(ICH7_REG_SPID0 + (a)); - } - - data[a] = - (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) - >> ((a % 4) * 8); - } - } + if ((!write_cmd) && (datalength != 0)) + ich_read_data(data, datalength, ICH7_REG_SPID0); return 0; } @@ -785,7 +791,6 @@ int write_cmd = 0; int timeout; uint32_t temp32; - uint32_t a; uint64_t opmenu; int opcode_index; @@ -810,25 +815,8 @@ REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32); /* Program data into FDATA0 to N */ - if (write_cmd && (datalength != 0)) { - temp32 = 0; - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = 0; - } - - temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8); - - if ((a % 4) == 3) { - REGWRITE32(ICH9_REG_FDATA0 + (a - (a % 4)), - temp32); - } - } - if (((a - 1) % 4) != 3) { - REGWRITE32(ICH9_REG_FDATA0 + - ((a - 1) - ((a - 1) % 4)), temp32); - } - } + if (write_cmd && (datalength != 0)) + ich_fill_data(data, datalength, ICH9_REG_FDATA0); /* Assemble SSFS + SSFC */ temp32 = REGREAD32(ICH9_REG_SSFS); @@ -916,17 +904,8 @@ return 1; } - if ((!write_cmd) && (datalength != 0)) { - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = REGREAD32(ICH9_REG_FDATA0 + (a)); - } - - data[a] = - (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) - >> ((a % 4) * 8); - } - } + if ((!write_cmd) && (datalength != 0)) + ich_read_data(data, datalength, ICH9_REG_FDATA0); return 0; }

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Re: [flashrom] [PATCH 8/8] Added (N) to the name of MX29F002B/T devices.
by Idwer Vollering Aug. 7, 2011

Aug. 7, 2011

2011/3/15 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at>: > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Idwer Vollering <vidwer(a)gmail.com> But *only* if the probe/read/erase/write status is not affected. > --- > flashchips.c | 4 ++-- > flashchips.h | 4 ++-- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/flashchips.c b/flashchips.c > index 7cb7d39..97aafef 100644 > --- a/flashchips.c > +++ b/flashchips.c > @@ -4209,7 +4209,7 @@ struct flashchip flashchips[] = { > > { > .vendor = "Macronix", > - .name = "MX29F002B", > + .name = "MX29F002(N)B", > .bustype = CHIP_BUSTYPE_PARALLEL, > .manufacture_id = MACRONIX_ID, > .model_id = MACRONIX_MX29F002B, > @@ -4240,7 +4240,7 @@ struct flashchip flashchips[] = { > > { > .vendor = "Macronix", > - .name = "MX29F002T", > + .name = "MX29F002(N)T", > .bustype = CHIP_BUSTYPE_PARALLEL, > .manufacture_id = MACRONIX_ID, > .model_id = MACRONIX_MX29F002T, > diff --git a/flashchips.h b/flashchips.h > index 9b08d25..9782188 100644 > --- a/flashchips.h > +++ b/flashchips.h > @@ -361,8 +361,8 @@ > #define MACRONIX_MX25L3235D 0x5E16 /* MX25L3225D/MX25L3235D/MX25L3237D */ > #define MACRONIX_MX29F001B 0x19 > #define MACRONIX_MX29F001T 0x18 > -#define MACRONIX_MX29F002B 0x34 /* Same as MX29F002NB */ > -#define MACRONIX_MX29F002T 0xB0 /* Same as MX29F002NT */ > +#define MACRONIX_MX29F002B 0x34 /* Same as MX29F002NB; N has reset pin n/c. */ > +#define MACRONIX_MX29F002T 0xB0 /* Same as MX29F002NT; N has reset pin n/c. */ > #define MACRONIX_MX29F004B 0x46 > #define MACRONIX_MX29F004T 0x45 > #define MACRONIX_MX29F022T 0x36 /* Same as MX29F022NT */ > -- > 1.7.1 > > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom >

2 2

A8M2N-LA fail
by Márton Miklós Aug. 7, 2011

Aug. 7, 2011

Hello all, I have just tried to flash my BIOS using the flashrom, and I have ran into the following situation: lucifer@lucifer-desktop:~/Letöltések/flashrom-0.9.4$ sudo ./flashrom -w /tmp/sp35111/3.10 flashrom v0.9.4-r1395 on Linux 2.6.35-28-generic (i686), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "NVIDIA MCP51". This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x23, failed byte count from 0x00000000-0x00000fff: 0xfec ERASE FAILED! Reading current flash chip contents... done. ERASE FAILED at 0x00000000! Expected=0xff, Read=0x23, failed byte count from 0x00000000-0x0000ffff: 0xfef9 ERASE FAILED! Reading current flash chip contents... done. ERASE FAILED at 0x00000000! Expected=0xff, Read=0x23, failed byte count from 0x00000000-0x0007ffff: 0x6494b ERASE FAILED! FAILED! Uh oh. Erase/write failed. Checking if anything changed. Good. It seems nothing was changed. Writing to the flash chip apparently didn't do anything. This means we have to add special support for your board, programmer or flash chip. Please report this on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- You may now reboot or simply leave the machine running. Flashrom info: lucifer@lucifer-desktop:~/Letöltések/flashrom-0.9.4$ sudo ./flashrom flashrom v0.9.4-r1395 on Linux 2.6.35-28-generic (i686), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "NVIDIA MCP51". This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH) at physical address 0xfff80000. No operations were specified. I have tried the latest revision (1402) but it did not works too. Let me know if I should provide any additional information. Regards, Miklós Márton

4 5

[commit] r1408 - trunk
by repository service Aug. 7, 2011

Aug. 7, 2011

Author: stefanct Date: Sun Aug 7 15:17:20 2011 New Revision: 1408 URL: http://flashrom.org/trac/flashrom/changeset/1408 Log: Add a board enable for ASUS A8M2N-LA (HP OEM "NodusM3-GL8E") It is based on Joshua Roys' RE. http://www.flashrom.org/pipermail/flashrom/2011-August/007504.html Tested-by: Márton Miklós Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/chipset_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sat Aug 6 18:16:45 2011 (r1407) +++ trunk/board_enable.c Sun Aug 7 15:17:20 2011 (r1408) @@ -921,6 +921,7 @@ /* * Suited for: + * - ASUS A8M2N-LA (HP OEM "NodusM3-GL8E"): NVIDIA MCP51 * - ASUS A8N-LA (HP OEM "Nagami-GL8E"): NVIDIA MCP51 * - ASUS M2NBP-VM CSM: NVIDIA MCP51 */ @@ -2000,6 +2001,7 @@ {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, P3, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise}, {0x1002, 0x4372, 0x103c, 0x2a26, 0x1002, 0x4377, 0x103c, 0x2a26, NULL, NULL, NULL, P3, "ASUS", "A8AE-LE", 0, OK, amd_sbxxx_gpio9_raise}, {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, P3, "ASUS", "A8Jm", 0, NT, intel_ich_gpio34_raise}, + {0x10DE, 0x0260, 0x103C, 0x2A34, 0x10DE, 0x0264, 0x103C, 0x2A34, "NODUSM3", NULL, NULL, P3, "ASUS", "A8M2N-LA (NodusM3-GL8E)", 0, OK, nvidia_mcp_gpio0_raise}, {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI2L", NULL, NULL, P3, "ASUS", "A8N-LA (Nagami-GL8E)", 0, OK, nvidia_mcp_gpio0_raise}, {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, "^A8N-SLI DELUXE", NULL, NULL, P3, "ASUS", "A8N-SLI Deluxe", 0, NT, board_shuttle_fn25}, {0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, P3, "ASUS", "A8N-VM CSM", 0, OK, w83627ehf_gpio22_raise_2e}, Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Sat Aug 6 18:16:45 2011 (r1407) +++ trunk/chipset_enable.c Sun Aug 7 15:17:20 2011 (r1408) @@ -1096,7 +1096,7 @@ {0x10de, 0x00e0, OK, "NVIDIA", "NForce3", enable_flash_nvidia_nforce2}, /* Slave, should not be here, to fix known bug for A01. */ {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804}, - {0x10de, 0x0260, NT, "NVIDIA", "MCP51", enable_flash_ck804}, + {0x10de, 0x0260, OK, "NVIDIA", "MCP51", enable_flash_ck804}, {0x10de, 0x0261, NT, "NVIDIA", "MCP51", enable_flash_ck804}, {0x10de, 0x0262, NT, "NVIDIA", "MCP51", enable_flash_ck804}, {0x10de, 0x0263, NT, "NVIDIA", "MCP51", enable_flash_ck804}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Sat Aug 6 18:16:45 2011 (r1407) +++ trunk/print.c Sun Aug 7 15:17:20 2011 (r1408) @@ -420,6 +420,7 @@ B("ASUS", "A7V8X-MX SE", 1, "http://www.asus.com/product.aspx?P_ID=1guVBT1qV5oqhHyZ", NULL), B("ASUS", "A7V8X-X", 1, "http://www.asus.com/product.aspx?P_ID=YcXfRrWHZ9RKoVmw", NULL), B("ASUS", "A8Jm", 1, "http://www.asus.com/product.aspx?P_ID=VztICtOgiU6drx4m", NULL), + B("ASUS", "A8M2N-LA (NodusM3-GL8E)", 1, "http://h10010.www1.hp.com/ewfrf/wc/document?docname=c00757531&cc=us&dlc=en&…", "This is an OEM board from HP, the HP name is NodusM3-GL8E."), B("ASUS", "A8N-E", 1, "http://www.asus.com/product.aspx?P_ID=DzbA8hgqchMBOVRz", NULL), B("ASUS", "A8N-LA (Nagami-GL8E)", 1, "http://h10025.www1.hp.com/ewfrf/wc/document?lc=en&cc=us&docname=c00647121&d…", "This is an OEM board from HP, the HP name is Nagami-GL8E."), B("ASUS", "A8N-SLI", 1, "http://www.asus.com/product.aspx?P_ID=J9FKa8z2xVId3pDK", NULL),

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flashrom support for EP-9NPA7I
by Stefan Tauner Aug. 7, 2011

Aug. 7, 2011

hello clr! you have missed carl-daniel or vice-versa one time and you never came back after that. i have dug up some info about the predecessor of your board i.e. 8NPA7I. the board enable that was executed on your machine by mistake is not complete (not even for the 8NPA7I) so it is expected to not work for you. i have not reverse engineered your bios (update tool), so i am not sure at all that the attached patch would help and not reboot/ruin/ignite your machine. but if you are brave you can try it. PS: this patch is not for merge, because we have no idea what 0x92 really does imho. but we could incorporate this into a board enable function, if it really works or do you (fellow flashrom dev) think it is ok to just merge it as is? PPS: this is just a port of http://patchwork.coreboot.org/patch/2125/ -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[PATCH 2/2] Nvidia chipset enables: refactor setting bit 0 in 0x6d
by Stefan Tauner Aug. 7, 2011

Aug. 7, 2011

This also changes semantics: previously failing to set this was interpreted as error by enable_flash_ck804 and enable_flash_mcp55 although the output indicates otherwise. Also, in enable_flash_nvidia_nforce2 there was no check if settings the bit succeeds. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipset_enable.c | 49 ++++++++++++++++++++----------------------------- 1 files changed, 20 insertions(+), 29 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index 294007d..03ccaa2 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -784,16 +784,27 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name) return ret; } -static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name) +/* sets bit 0 in 0x6d */ +static void enable_flash_nvidia_common(struct pci_dev *dev, const char *name) { - uint8_t tmp; + uint8_t old, new; - rpci_write_byte(dev, 0x92, 0); + old = pci_read_byte(dev, 0x6d); + new = old | 0x01; + if (new == old) + return; + rpci_write_byte(dev, 0x6d, new); - tmp = pci_read_byte(dev, 0x6d); - tmp |= 0x01; - rpci_write_byte(dev, 0x6d, tmp); + if (pci_read_byte(dev, 0x6d) != new) { + msg_pinfo("Setting register 0x%x to 0x%x on %s failed " + "(WARNING ONLY).\n", 0x6d, new, name); + } +} +static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name) +{ + rpci_write_byte(dev, 0x92, 0); + enable_flash_nvidia_common(dev, name); return 0; } @@ -859,17 +870,7 @@ ck804_lockbits_done: } } - old = pci_read_byte(dev, 0x6d); - new = old | 0x01; - if (new == old) - return 0; - rpci_write_byte(dev, 0x6d, new); - - if (pci_read_byte(dev, 0x6d) != new) { - msg_pinfo("Setting register 0x%x to 0x%x on %s failed " - "(WARNING ONLY).\n", 0x6d, new, name); - return -1; - } + enable_flash_nvidia_common(dev, name); return 0; } @@ -929,7 +930,7 @@ static int enable_flash_sb400(struct pci_dev *dev, const char *name) static int enable_flash_mcp55(struct pci_dev *dev, const char *name) { - uint8_t old, new, val; + uint8_t val; uint16_t wordval; /* Set the 0-16 MB enable bits. */ @@ -943,17 +944,7 @@ static int enable_flash_mcp55(struct pci_dev *dev, const char *name) wordval |= 0x7fff; /* 16M */ rpci_write_word(dev, 0x90, wordval); - old = pci_read_byte(dev, 0x6d); - new = old | 0x01; - if (new == old) - return 0; - rpci_write_byte(dev, 0x6d, new); - - if (pci_read_byte(dev, 0x6d) != new) { - msg_pinfo("Setting register 0x%x to 0x%x on %s failed " - "(WARNING ONLY).\n", 0x6d, new, name); - return -1; - } + enable_flash_nvidia_common(dev, name); return 0; } -- 1.7.1

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