August 2011 - flashrom - mail.coreboot.org

Re: [flashrom] MSI H55-GD65 (MS-7637) (H55, locked ME region, FLOCKDN=0(!))
by Stefan Tauner 21 Aug '11

21 Aug '11

On Sat, 20 Aug 2011 19:40:55 -0600 Donovan Lavinder <drmario2007(a)gmail.com> wrote: > You guys can also use flashrom utility to be able to write the firmware if > the utility you are using is being stubborn (happens to me too), hi donovan, we are talking about flashrom explicitly here.. because it is the mailing list of flashrom (and not coreboot). to be precise, we are talking about implementing a new feature to flashrom. this has almost nothing to do with coreboot. > […] -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] MSI H55-GD65 (MS-7637) (H55, locked ME region, FLOCKDN=0(!))
by Stefan Tauner 20 Aug '11

20 Aug '11

On Sat, 20 Aug 2011 23:03:16 +0100 (BST) Luzipher McLeod <luziphermcleod(a)yahoo.ie> wrote: > Thanks for your mails ! Good to know that there is something going on (even though you indicate that it'll take quite some time). If I can do anything to help, just let me know. if you are good at REing you could help a lot (because i am a n00b regarding x86 asm, and therefor quite unmotivated to stare at disassembly - especially when i see how fluently others are able to read this :). > That said, it really seems to be a messed up situation. As far as I understood, there are several "units" involved in accessing the flash (or at least granting rights to access the flash). yes. the firmware for the ME, the GbE controller and the host (=BIOS/EFI) are on the same flash chip and all of them can access it via the southbridge. they do also write to it (the ME logs some stuff at least). access restrictions are enforced by the southbridge which acts as a gatekeeper. > Am I right that the major missing thing is support for the embedded controller (ME) ? exactly. usually that is the only real problem. the flash descriptor region is most often read-only, but that's not really an issue (it does not need to be updated normally). i *think* to know how the ME can be told to give us access superficially (using HECI/MEI), but i don't know the exact details. i have a patch already that implements MEI communication in flashrom... the question is just what to send (and what to expect to receive :) > I also do have a flashing utility that works from DOS if that'd be any help (reverse engineering) ? there are various of those and RE is the way to go probably (because intel won't tell us probably). having access to the binary is not the problem though. > > PS: Wir können auch deutsch schreiben, ich hab's mal in Englisch verfasst, weil du erwähnt hast, das das ganze evtl auch der Dokumentation für etwaige Nachfolgerwahnsinnige dient :-) if it is not too hard for you, english is the way to go because it is the least common denominator of those involved. i think i should write together what i know about unlocking the ME. probably a wiki page would be best... -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Update of Gigabyte GA-MA78GM-S2HP motherboard firmware switch
by Donovan Lavinder 20 Aug '11

20 Aug '11

After a day of struggling with bricked firmwares.... I finally ditched FreeDOS. I went with SystemRescueCd distro and burnt coreboot precompiled firmware under the folder /gigabyte_ma78gm/ and the firmware WORKED! But now I am stuck with funny firmware quirks (Windows XP crashing when booting halfway, almost to the point the video card driver is loaded, right after "GIVEIO.SYS" driver is being loaded), even though it loaded Linux CD fine. I guess I should try and ditch PS/2 mouse as it may probably be the cause of strange behavior - I will be using USB mouse / keyboard as well. I am happy with this firmware otherwise. And, the backup BIOS didn't even try to intercept the Linux kernel in the firmware from loading. Thankfully. I will eventually decide to recompile or "submit" the additional payloads such as EFI and memtest86+ as those software will be needed in the future, after I learn more of its capabilities. And, thanks for such a wonderful firmware! That thing's so fast! -- "Mamma-mia, there's Koopa troopa in Mushroom Kingdom!"

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Coreboot failure on GA-MA78GM-S2HP Rev. 2.0 motherboard
by Donovan Lavinder 20 Aug '11

20 Aug '11

I originally wanted EFI and other features that will allow me to use my motherboard for few years out. So, I downloaded archived coreboot firmware package, and I found one "baked" firmware ROM under folder MA78GM as the motherboards under this family seems to be having the same chipsets, so I went to burn my own coreboot in FreeDOS using flashrom. Now, it first exclaimed that it found MXIC MX25L8005 chipset, but it tried 4-bytes RDID and failed, however, I was able to erase the BIOS chip fine. Next, I wrote the firmware - after it said "done", it froze - I reset it, it kept reverting back to oh-so-annoying Award BIOS... No wonder my motherboard is SO picky! Here, I wrote up on the paper: flashrom Ver. 0.9.3 - r1205 (on Freedos boot CD - all I have had, no floppy disk and it won't boot from USB disk.... I may try spare hard drive if needed...) - 4-byte RDID refusal (although erasure was successful) Motherboard: Vendor - Gigabyte / Model - GA-MA78GM-S2HP CPU: AMD Phenom II X940 Black Series 3.0GHz quad-core (Deneb) CPU RAM: Crucial Ballistix DDR-II 800MHz 1GB x2 (2GB) on dual-channel memory bus Video card: Vendor - Gigabyte / Model - GV-R467ZL-1GI - FW Ver. - F12 / VPU - AMD Radeon HD 4670 with 1GB 800MHz GDDR3 on 128-bit bus * I removed my hard drive (with my personal documents and Windows XP) during the firmware flash to ensure the data aren't touched in a way. I would like to know how I can get my motherboard to quit being all so picky - otherwise any other methods known to work perfectly on the GA-MA78GM-S2HP motherboard any of you may have up and running the coreboot firmware. Thanks for your help! -- "Mamma-mia, there's Koopa troopa in Mushroom Kingdom!"

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[PATCH] Makefile: Fix MinGW build, improve output with bogus CC
by Uwe Hermann 20 Aug '11

20 Aug '11

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[commit] r1418 - trunk
by repository service 20 Aug '11

20 Aug '11

Author: uwe Date: Sat Aug 20 16:16:00 2011 New Revision: 1418 URL: http://flashrom.org/trac/flashrom/changeset/1418 Log: Makefile: Fix MinGW build, improve output with bogus CC. As per IRC discussion, the "ARCH :=" line should be moved after any lines which set CC, as it uses CC itself. This fixes the MinGW build. Also, add a "2>/dev/null" in the "ARCH :=" as per suggestion from Stefan Tauner to improve the output in the case CC is bogus: Before: $ make CC=foo /bin/sh: foo: not found Checking for a C compiler... not found. make: *** [compiler] Error 1 After: $ make CC=foo Checking for a C compiler... not found. make: *** [compiler] Error 1 Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/Makefile Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Sat Aug 20 16:14:22 2011 (r1417) +++ trunk/Makefile Sat Aug 20 16:16:00 2011 (r1418) @@ -37,9 +37,6 @@ CFLAGS += -Werror endif -# Determine the destination processor architecture -override ARCH := $(strip $(shell LC_ALL=C $(CC) -E arch.h|grep -v '^\#')) - # FIXME We have to differentiate between host and target OS architecture. OS_ARCH ?= $(shell uname) ifneq ($(OS_ARCH), SunOS) @@ -202,6 +199,12 @@ endif endif +# Determine the destination processor architecture. +# IMPORTANT: The following line must be placed before ARCH is ever used +# (of course), but should come after any lines setting CC because the line +# below uses CC itself. In some cases we set CC based on OS_ARCH, see above. +override ARCH := $(strip $(shell LC_ALL=C $(CC) -E arch.h 2>/dev/null | grep -v '^\#')) + ifeq ($(ARCH), "ppc") # There's no PCI port I/O support on PPC/PowerPC, yet. ifeq ($(CONFIG_NIC3COM), yes)

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[PATCH] Move the main() function from flashrom.c to cli_classic.c
by Uwe Hermann 20 Aug '11

20 Aug '11

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[commit] r1417 - trunk
by repository service 20 Aug '11

20 Aug '11

Author: uwe Date: Sat Aug 20 16:14:22 2011 New Revision: 1417 URL: http://flashrom.org/trac/flashrom/changeset/1417 Log: Move the main() function from flashrom.c to cli_classic.c. The file flashrom.c is part of libflashrom and should thus not contain a main() function, that would break compilation of all frontends using libflashrom. Also, cli_classic.c is the right place anyway, as it's the main() of the CLI tool. Rename the simple wrapper cli_classic() in cli_classic.c to main(), as it's not really needed. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/cli_classic.c trunk/flash.h trunk/flashrom.c Modified: trunk/cli_classic.c ============================================================================== --- trunk/cli_classic.c Thu Aug 18 04:27:19 2011 (r1416) +++ trunk/cli_classic.c Sat Aug 20 16:14:22 2011 (r1417) @@ -96,7 +96,7 @@ exit(1); } -int cli_classic(int argc, char *argv[]) +int main(int argc, char *argv[]) { unsigned long size; /* Probe for up to three flash chips. */ Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Thu Aug 18 04:27:19 2011 (r1416) +++ trunk/flash.h Sat Aug 20 16:14:22 2011 (r1417) @@ -251,9 +251,6 @@ #define msg_pspew(...) print(MSG_BARF, __VA_ARGS__) /* programmer debug barf */ #define msg_cspew(...) print(MSG_BARF, __VA_ARGS__) /* chip debug barf */ -/* cli_classic.c */ -int cli_classic(int argc, char *argv[]); - /* layout.c */ int read_romlayout(char *name); int find_romentry(char *name); Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Thu Aug 18 04:27:19 2011 (r1416) +++ trunk/flashrom.c Sat Aug 20 16:14:22 2011 (r1417) @@ -1796,11 +1796,6 @@ } } -int main(int argc, char *argv[]) -{ - return cli_classic(argc, argv); -} - /* FIXME: This function signature needs to be improved once doit() has a better * function signature. */

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[PATCH] Make the laptop warning less scary if unsure
by Stefan Tauner 20 Aug '11

20 Aug '11

Telling the user to use "force_I_want_a_brick" if it is not even a laptop, is a bit over-the-top. Introduce a new laptop parameter "this_is_not_a_laptop" that allows to force operation, but only if the detection is not sure. --- complicates the whole thing a bit. could do without the extra variable and new part of the if condition, if we allow the this_is_not_a_laptop parameter to always work, not only if the laptop detection is uncertain. it will be undocumented and only visible to the user together with the warning anyway... Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- internal.c | 14 ++++++++------ 1 files changed, 8 insertions(+), 6 deletions(-) diff --git a/internal.c b/internal.c index 846cf1e..5ff605e 100644 --- a/internal.c +++ b/internal.c @@ -139,6 +139,7 @@ int internal_init(void) int ret = 0; #endif int force_laptop = 0; + int not_a_laptop = 0; char *arg; arg = extract_programmer_param("boardenable"); @@ -170,9 +171,11 @@ int internal_init(void) free(arg); arg = extract_programmer_param("laptop"); - if (arg && !strcmp(arg,"force_I_want_a_brick")) { + if (arg && !strcmp(arg,"force_I_want_a_brick")) force_laptop = 1; - } else if (arg && !strlen(arg)) { + else if (arg && !strcmp(arg,"this_is_not_a_laptop")) + not_a_laptop = 1; + else if (arg && !strlen(arg)) { msg_perr("Missing argument for laptop.\n"); free(arg); return 1; @@ -237,7 +240,7 @@ int internal_init(void) msg_perr("WARNING! You may be running flashrom on an unsupported laptop. We could\n" "not detect this for sure because your vendor has not setup the SMBIOS\n" "tables correctly. You can enforce execution by adding\n" - "'-p internal:laptop=force_I_want_a_brick' to the command line, but\n" + "'-p internal:laptop=this_is_not_a_laptop' to the command line, but\n" "please read the following warning if you are not sure.\n\n"); } msg_perr("Laptops, notebooks and netbooks are difficult to support and we\n" @@ -251,9 +254,8 @@ int internal_init(void) "You have been warned.\n" "========================================================================\n"); - if (force_laptop) { - msg_perr("Proceeding anyway because user specified " - "laptop=force_I_want_a_brick\n"); + if (force_laptop || (not_a_laptop && (is_laptop != 1))) { + msg_perr("Proceeding anyway because user forced us to.\n"); } else { msg_perr("Aborting.\n"); exit(1); -- 1.7.1

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[PATCH 8/8] Add ich_descriptor_tool to decode all flash descriptors stored in a flash dump file
by Stefan Tauner 20 Aug '11

20 Aug '11

additionally to what is available via FDOC/FDOD this allows to access: - the softstraps which are used to configure the chipset by flash content without the need for BIOS routines. on ICH8 it is possible to read those with FDOC/FDOC too, but this was removed in later chipsets. - the ME VSCC (Vendor Specific Component Capabilities) table. simply put, this is an SPI chip database used to figure out the flash's capabilities Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ich_descriptors.c | 399 ++++++++++++++++++++++ ich_descriptors.h | 206 +++++++++++- util/ich_descriptors_tool/Makefile | 63 ++++ util/ich_descriptors_tool/TODO | 6 + util/ich_descriptors_tool/ich_descriptors_tool.c | 225 ++++++++++++ 5 files changed, 898 insertions(+), 1 deletions(-) create mode 100644 util/ich_descriptors_tool/Makefile create mode 100644 util/ich_descriptors_tool/TODO create mode 100644 util/ich_descriptors_tool/ich_descriptors_tool.c diff --git a/ich_descriptors.c b/ich_descriptors.c index 8076b09..57c1d51 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -22,9 +22,33 @@ #if defined(__i386__) || defined(__x86_64__) #include "ich_descriptors.h" + +#ifdef ICH_DESCRIPTORS_FROM_DUMP + +#include <stdio.h> +#define msg_perr printf +#define msg_pdbg printf +#define msg_pdbg2 printf +#define msg_pspew printf +#define print(t, ...) printf(__VA_ARGS__) +#define DESCRIPTOR_MODE_SIGNATURE 0x0ff0a55a +/* The upper map is located in the word before the 256B-long OEM section at the + * end of the 4kB-long flash descriptor. + */ +#define UPPER_MAP_OFFSET (4096 - 256 - 4) +#define getVTBA(flumap) (((flumap)->FLUMAP1 << 4) & 0x00000ff0) + +#else /* ICH_DESCRIPTORS_FROM_DUMP */ + #include "flash.h" /* for msg_* */ #include "programmer.h" +#endif /* ICH_DESCRIPTORS_FROM_DUMP */ + +#ifndef min +#define min(a, b) (a < b) ? a : b +#endif + void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity) { print(verbosity, "BES=0x%x, ", (reg_val & VSCC_BES) >> VSCC_BES_OFF); @@ -48,6 +72,12 @@ void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descripto prettyprint_ich_descriptor_component(desc); prettyprint_ich_descriptor_region(desc); prettyprint_ich_descriptor_master(&desc->master); +#ifdef ICH_DESCRIPTORS_FROM_DUMP + if (cs >= CHIPSET_ICH8) { + prettyprint_ich_descriptor_upper_map(&desc->upper); + prettyprint_ich_descriptor_straps(cs, desc); + } +#endif /* ICH_DESCRIPTORS_FROM_DUMP */ } void prettyprint_ich_descriptor_content(const struct ich_desc_content *cont) @@ -214,6 +244,374 @@ void prettyprint_ich_descriptor_master(const struct ich_desc_master *mstr) msg_pdbg2("\n"); } +#ifdef ICH_DESCRIPTORS_FROM_DUMP + +void prettyprint_ich_descriptor_straps_ich8(const struct ich_descriptors *desc) +{ + static const char * const str_GPIO12[4] = { + "GPIO12", + "LAN PHY Power Control Function (Native Output)", + "GLAN_DOCK# (Native Input)", + "invalid configuration", + }; + + + msg_pdbg2("--- MCH details ---\n"); + msg_pdbg2("ME B is %sabled.\n", desc->north.ich8.MDB ? "dis" : "en"); + msg_pdbg2("\n"); + + msg_pdbg2("--- ICH details ---\n"); + msg_pdbg2("ME SMBus Address 1: 0x%02x\n", desc->south.ich8.ASD); + msg_pdbg2("ME SMBus Address 2: 0x%02x\n", desc->south.ich8.ASD2); + msg_pdbg2("ME SMBus Controller is connected to the %s.\n", + desc->south.ich8.MESM2SEL ? "SMLink pins" : "SMBus pins"); + msg_pdbg2("SPI CS1 is used for %s.\n", + desc->south.ich8.SPICS1_LANPHYPC_SEL ? + "LAN PHY Power Control Function" : + "SPI Chip Select"); + msg_pdbg2("GPIO12 Select is used as %s.\n", + str_GPIO12[desc->south.ich8.GPIO12_SEL]); + msg_pdbg2("PCIe Port 6 is used for %s.\n", + desc->south.ich8.GLAN_PCIE_SEL ? "integrated LAN" : "PCI Express"); + msg_pdbg2("%sn BMC Mode: " + "Intel AMT SMBus Controller 1 is connected to %s.\n", + desc->south.ich8.BMCMODE ? "I" : "Not i", + desc->south.ich8.BMCMODE ? "SMLink" : "SMBus"); + msg_pdbg2("TCO is in %s Mode.\n", + desc->south.ich8.TCOMODE ? "Advanced TCO" : "Legacy/Compatible"); + msg_pdbg2("ME A is %sabled.\n", + desc->south.ich8.ME_DISABLE ? "dis" : "en"); + msg_pdbg2("\n"); +} + +static void prettyprint_ich_descriptor_straps_ibex_pciecs(uint8_t conf, uint8_t off) +{ + msg_pdbg2("PCI Express Port Configuration Strap %d: ", off+1); + + off *= 4; + switch(conf){ + case 0: + msg_pdbg2("4x1 Ports %d-%d (x1)", 1+off, 4+off); + break; + case 1: + msg_pdbg2("1x2, 2x1 Port %d (x2), Port %d (disabled), " + "Ports %d, %d (x1)", 1+off, 2+off, 3+off, 4+off); + break; + case 2: + msg_pdbg2("2x2 Port %d (x2), Port %d (x2), Ports " + "%d, %d (disabled)", 1+off, 3+off, 2+off, 4+off); + break; + case 3: + msg_pdbg2("1x4 Port %d (x4), Ports %d-%d (disabled)", + 1+off, 2+off, 4+off); + break; + } + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_straps_ibex(const struct ich_desc_south_strap *s) +{ + static const uint8_t const dec_t209min[4] = { + 100, + 50, + 5, + 1 + }; + + msg_pdbg2("--- PCH ---\n"); + + /* PCHSTRP1 */ + msg_pdbg2("Chipset configuration Softstrap 2: %d\n", s->ibex.cs_ss2); + msg_pdbg2("Intel ME SMBus Select is %sabled.\n", + s->ibex.SMB_EN ? "en" : "dis"); + msg_pdbg2("SMLink0 segment is %sabled.\n", + s->ibex.SML0_EN ? "en" : "dis"); + msg_pdbg2("SMLink1 segment is %sabled.\n", + s->ibex.SML1_EN ? "en" : "dis"); + msg_pdbg2("SMLink1 Frequency: %s\n", + (s->ibex.SML1FRQ == 1) ? "100 kHz" : "reserved"); + msg_pdbg2("Intel ME SMBus Frequency: %s\n", + (s->ibex.SMB0FRQ == 1) ? "100 kHz" : "reserved"); + msg_pdbg2("SMLink0 Frequency: %s\n", + (s->ibex.SML0FRQ == 1) ? "100 kHz" : "reserved"); + msg_pdbg2("GPIO12 is used as %s.\n", s->ibex.LANPHYPC_GP12_SEL ? + "LAN_PHY_PWR_CTRL" : "general purpose output"); + + /* PCHSTRP2 */ + msg_pdbg2("Chipset configuration Softstrap 3: 0x%x\n", s->ibex.cs_ss3); + + /* PCHSTRP3 */ + msg_pdbg2("ME SMBus ASD address is %sabled.\n", + s->ibex.MESMASDEN ? "en" : "dis"); + msg_pdbg2("ME SMBus Controller ASD Target address: 0x%02x\n", + s->ibex.MESMASDA); + msg_pdbg2("ME SMBus I2C address is %sabled.\n", + s->ibex.MESMI2CEN ? "en" : "dis"); + msg_pdbg2("ME SMBus I2C target address: 0x%02x\n", + s->ibex.MESMI2CA); + + /* PCHSTRP4 */ + /* PCHSTRP5 */ + msg_pdbg2("Intel PHY is %s.\n", + (s->ibex.PHYCON == 2) ? "connected" : + (s->ibex.PHYCON == 0) ? "disconnected" : "reserved"); + msg_pdbg2("GbE MAC SMBus address is %sabled.\n", + s->ibex.GBEMAC_SMBUS_ADDR_EN ? "en" : "dis"); + msg_pdbg2("GbE MAC SMBus address: 0x%02x\n", + s->ibex.GBEMAC_SMBUS_ADDR); + msg_pdbg2("GbE PHY SMBus address: 0x%02x\n", + s->ibex.GBEPHY_SMBUS_ADDR); + + /* PCHSTRP6 */ + /* PCHSTRP7 */ + msg_pdbg2("Intel ME SMBus Subsystem Vendor ID: 0x%04x\n", + s->ibex.MESMA2UDID_VENDOR); + msg_pdbg2("Intel ME SMBus Subsystem Device ID: 0x%04x\n", + s->ibex.MESMA2UDID_VENDOR); + + /* PCHSTRP8 */ + /* PCHSTRP9 */ + prettyprint_ich_descriptor_straps_ibex_pciecs(s->ibex.PCIEPCS1, 0); + prettyprint_ich_descriptor_straps_ibex_pciecs(s->ibex.PCIEPCS1, 1); + msg_pdbg2("PCIe Lane Reversal 1: PCIe Lanes 0-3 are %sreserved.\n", + s->ibex.PCIELR1 ? "" : "not "); + msg_pdbg2("PCIe Lane Reversal 2: PCIe Lanes 4-7 are %sreserved.\n", + s->ibex.PCIELR2 ? "" : "not "); + msg_pdbg2("DMI Lane Reversal: DMI Lanes 0-3 are %sreserved.\n", + s->ibex.DMILR ? "" : "not "); + msg_pdbg2("Default PHY PCIe Port is %d.\n", s->ibex.PHY_PCIEPORTSEL+1); + msg_pdbg2("Integrated MAC/PHY communication over PCIe is %sabled.\n", + s->ibex.PHY_PCIE_EN ? "en" : "dis"); + + /* PCHSTRP10 */ + msg_pdbg2("Management Engine will boot from %sflash.\n", + s->ibex.ME_BOOT_FLASH ? "" : "ROM, then "); + msg_pdbg2("Chipset configuration Softstrap 5: %d\n", s->ibex.cs_ss5); + msg_pdbg2("Virtualization Engine Enable 1 is %sabled.\n", + s->ibex.VE_EN ? "en" : "dis"); + msg_pdbg2("ME Memory-attached Debug Display Device is %sabled.\n", + s->ibex.MMDDE ? "en" : "dis"); + msg_pdbg2("ME Memory-attached Debug Display Device address: 0x%02x\n", + s->ibex.MMADDR); + msg_pdbg2("Chipset configuration Softstrap 7: %d\n", s->ibex.cs_ss7); + msg_pdbg2("Integrated Clocking Configuration is %d.\n", + (s->ibex.ICC_SEL == 7) ? 0 : s->ibex.ICC_SEL); + msg_pdbg2("PCH Signal CL_RST1# does %sassert when Intel ME performs a " + "reset.\n", s->ibex.MER_CL1 ? "" : "not "); + + /* PCHSTRP11 */ + msg_pdbg2("SMLink1 GP Address is %sabled.\n", + s->ibex.SML1GPAEN ? "en" : "dis"); + msg_pdbg2("SMLink1 controller General Purpose Target address: 0x%02x\n", + s->ibex.SML1GPA); + msg_pdbg2("SMLink1 I2C Target address is %sabled.\n", + s->ibex.SML1I2CAEN ? "en" : "dis"); + msg_pdbg2("SMLink1 I2C Target address: 0x%02x\n", + s->ibex.SML1I2CA); + + /* PCHSTRP12 */ + /* PCHSTRP13 */ + /* PCHSTRP14 */ + msg_pdbg2("Virtualization Engine Enable 2 is %sabled.\n", + s->ibex.VE_EN2 ? "en" : "dis"); + msg_pdbg2("Virtualization Engine will boot from %sflash.\n", + s->ibex.VE_BOOT_FLASH ? "" : "ROM, then "); + msg_pdbg2("Braidwood SSD functionality is %sabled.\n", + s->ibex.BW_SSD ? "en" : "dis"); + msg_pdbg2("Braidwood NVMHCI functionality is %sabled.\n", + s->ibex.NVMHCI_EN ? "en" : "dis"); + + /* PCHSTRP15 */ + msg_pdbg2("Chipset configuration Softstrap 6: %d\n", s->ibex.cs_ss6); + msg_pdbg2("Integrated wired LAN Solution is %sabled.\n", + s->ibex.IWL_EN ? "en" : "dis"); + msg_pdbg2("t209 min Timing: %d ms\n", + dec_t209min[s->ibex.t209min]); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_straps(enum ich_chipset cs, const struct ich_descriptors *desc) +{ + unsigned int i, max; + msg_pdbg2("=== Softstraps ===\n"); + + if (sizeof(desc->north.STRPs) / 4 + 1 < desc->content.MSL) { + max = sizeof(desc->north.STRPs) / 4 + 1; + msg_pdbg2("MSL (%u) is greater than the current maximum of %u " + "entries.\n", desc->content.MSL, max + 1); + msg_pdbg2("Only the first %u entries will be printed.\n", max); + } else + max = desc->content.MSL; + + msg_pdbg2("--- North/MCH/PROC (%d entries) ---\n", max); + for(i = 0; i < max; i++) + msg_pdbg2("STRP%-2d = 0x%08x\n", i, desc->north.STRPs[i]); + msg_pdbg2("\n"); + + if (sizeof(desc->south.STRPs) / 4 < desc->content.ISL) { + max = sizeof(desc->south.STRPs) / 4; + msg_pdbg2("ISL (%u) is greater than the current maximum of %u " + "entries.\n", desc->content.ISL, max); + msg_pdbg2("Only the first %u entries will be printed.\n", max); + } else + max = desc->content.ISL; + + msg_pdbg2("--- South/ICH/PCH (%d entries) ---\n", max); + for(i = 0; i < max; i++) + msg_pdbg2("STRP%-2d = 0x%08x\n", i, desc->south.STRPs[i]); + msg_pdbg2("\n"); + + switch (cs) { + case CHIPSET_ICH8: + if (sizeof(desc->north.ich8) / 4 != desc->content.MSL) + msg_pdbg2("Detailed North/MCH/PROC information is " + "probably not reliable, printing anyway.\n"); + if (sizeof(desc->south.ich8) / 4 != desc->content.ISL) + msg_pdbg2("Detailed South/ICH/PCH information is " + "probably not reliable, printing anyway.\n"); + prettyprint_ich_descriptor_straps_ich8(desc); + break; + case CHIPSET_5_SERIES_IBEX_PEAK: + /* PCH straps only. PROCSTRPs are unknown. */ + if (sizeof(desc->south.ibex) / 4 != desc->content.ISL) + msg_pdbg2("Detailed South/ICH/PCH information is " + "probably not reliable, printing anyway.\n"); + prettyprint_ich_descriptor_straps_ibex(&desc->south); + break; + case CHIPSET_ICH_UNKNOWN: + break; + default: + msg_pdbg2("The meaning of the descriptor straps are unknown " + "yet.\n\n"); + break; + } +} + +void prettyprint_rdid(uint32_t reg_val) +{ + uint8_t mid = reg_val & 0xFF; + uint16_t did = ((reg_val >> 16) & 0xFF) | (reg_val & 0xFF00); + msg_pdbg2("Manufacturer ID 0x%02x, Device ID 0x%04x\n", mid, did); +} + +void prettyprint_ich_descriptor_upper_map(const struct ich_desc_upper_map *umap) +{ + int i; + msg_pdbg2("=== Upper Map Section ===\n"); + msg_pdbg2("FLUMAP1 0x%08x\n", umap->FLUMAP1); + msg_pdbg2("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2("VTL (length in DWORDS) = %d\n", umap->VTL); + msg_pdbg2("VTBA (base address) = 0x%6.6x\n", getVTBA(umap)); + msg_pdbg2("\n"); + + msg_pdbg2("VSCC Table: %d entries\n", umap->VTL/2); + for (i = 0; i < umap->VTL/2; i++) + { + uint32_t jid = umap->vscc_table[i].JID; + uint32_t vscc = umap->vscc_table[i].VSCC; + msg_pdbg2(" JID%d = 0x%08x\n", i, jid); + msg_pdbg2(" VSCC%d = 0x%08x\n", i, vscc); + msg_pdbg2(" "); /* indention */ + prettyprint_rdid(jid); + msg_pdbg2(" "); /* indention */ + prettyprint_ich_reg_vscc(vscc, 0); + } + msg_pdbg2("\n"); +} + +/* len is the length of dump in bytes */ +int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, enum ich_chipset cs, struct ich_descriptors *desc) +{ + unsigned int i, max; + uint8_t pch_bug_offset = 0; + + if (dump == NULL || desc == NULL) + return RET_PARAM; + + if (dump[0] != DESCRIPTOR_MODE_SIGNATURE) { + if (dump[4] == DESCRIPTOR_MODE_SIGNATURE) + pch_bug_offset = 4; + else + return RET_ERR; + } + + /* map */ + if (len < (4 + pch_bug_offset) * 4 - 1) + return RET_OOB; + desc->content.FLVALSIG = dump[0 + pch_bug_offset]; + desc->content.FLMAP0 = dump[1 + pch_bug_offset]; + desc->content.FLMAP1 = dump[2 + pch_bug_offset]; + desc->content.FLMAP2 = dump[3 + pch_bug_offset]; + + /* component */ + if (len < (getFCBA(&desc->content) + 3 * 4 - 1)) + return RET_OOB; + desc->component.FLCOMP = dump[(getFCBA(&desc->content) >> 2) + 0]; + desc->component.FLILL = dump[(getFCBA(&desc->content) >> 2) + 1]; + desc->component.FLPB = dump[(getFCBA(&desc->content) >> 2) + 2]; + + /* region */ + if (len < (getFRBA(&desc->content) + 5 * 4 - 1)) + return RET_OOB; + desc->region.FLREGs[0] = dump[(getFRBA(&desc->content) >> 2) + 0]; + desc->region.FLREGs[1] = dump[(getFRBA(&desc->content) >> 2) + 1]; + desc->region.FLREGs[2] = dump[(getFRBA(&desc->content) >> 2) + 2]; + desc->region.FLREGs[3] = dump[(getFRBA(&desc->content) >> 2) + 3]; + desc->region.FLREGs[4] = dump[(getFRBA(&desc->content) >> 2) + 4]; + + /* master */ + if (len < (getFMBA(&desc->content) + 3 * 4 - 1)) + return RET_OOB; + desc->master.FLMSTR1 = dump[(getFMBA(&desc->content) >> 2) + 0]; + desc->master.FLMSTR2 = dump[(getFMBA(&desc->content) >> 2) + 1]; + desc->master.FLMSTR3 = dump[(getFMBA(&desc->content) >> 2) + 2]; + + /* upper map */ + desc->upper.FLUMAP1 = dump[(UPPER_MAP_OFFSET >> 2) + 0]; + + /* VTL is 8 bits long. Quote from the Ibex Peak SPI programming guide: + * "Identifies the 1s based number of DWORDS contained in the VSCC + * Table. Each SPI component entry in the table is 2 DWORDS long." So + * the maximum of 255 gives us 127.5 SPI components(!?) 8 bytes each. A + * check ensures that the maximum offset actually accessed is available. + */ + if (len < (getVTBA(&desc->upper) + (desc->upper.VTL / 2 * 8) - 1)) + return RET_OOB; + + for (i = 0; i < desc->upper.VTL/2; i++) { + desc->upper.vscc_table[i].JID = + dump[(getVTBA(&desc->upper) >> 2) + i * 2 + 0]; + desc->upper.vscc_table[i].VSCC = + dump[(getVTBA(&desc->upper) >> 2) + i * 2 + 1]; + } + + /* MCH/PROC (aka. North) straps */ + if (len < getFMSBA(&desc->content) + desc->content.MSL * 4) + return RET_OOB; + + /* limit the range to be written */ + max = min(sizeof(desc->north.STRPs) / 4, desc->content.MSL); + for (i = 0; i < max; i++) + desc->north.STRPs[i] = + dump[(getFMSBA(&desc->content) >> 2) + i]; + + /* ICH/PCH (aka. South) straps */ + if (len < getFISBA(&desc->content) + desc->content.ISL * 4) + return RET_OOB; + + /* limit the range to be written */ + max = min(sizeof(desc->south.STRPs) / 4, desc->content.ISL); + for (i = 0; i < max; i++) + desc->south.STRPs[i] = + dump[(getFISBA(&desc->content) >> 2) + i]; + + return RET_OK; +} + +#else /* ICH_DESCRIPTORS_FROM_DUMP */ + /** Returns the integer representation of the component density with index idx in bytes or 0 if a correct size can not be determined. */ int getFCBA_component_density(uint8_t idx, const struct ich_descriptors *desc) @@ -319,5 +717,6 @@ int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc) msg_pdbg2(" done.\n"); return RET_OK; } +#endif /* ICH_DESCRIPTORS_FROM_DUMP */ #endif /* BITFIELDS == 1 */ #endif /* defined(__i386__) || defined(__x86_64__) */ diff --git a/ich_descriptors.h b/ich_descriptors.h index 8ab798f..56d1b3e 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -240,11 +240,206 @@ struct ich_desc_master { }; }; +#ifdef ICH_DESCRIPTORS_FROM_DUMP +struct ich_desc_north_strap { + union { + uint32_t STRPs[1]; /* current maximum: ich8 */ + struct { /* ich8 */ + struct { /* STRP2 (in the datasheet) */ + uint32_t MDB :1, + :31; + }; + } ich8; + }; +}; + +struct ich_desc_south_strap { + union { + uint32_t STRPs[16]; /* current maximum: ibex peak */ + struct { /* ich8 */ + struct { /* STRP1 */ + uint32_t ME_DISABLE :1, + :6, + TCOMODE :1, + ASD :7, + BMCMODE :1, + :3, + GLAN_PCIE_SEL :1, + GPIO12_SEL :2, + SPICS1_LANPHYPC_SEL :1, + MESM2SEL :1, + :1, + ASD2 :7; + }; + } ich8; + struct { /* ibex peak */ + struct { /* STRP0 */ + uint32_t :1, + cs_ss2 :1, + :5, + SMB_EN :1, + SML0_EN :1, + SML1_EN :1, + SML1FRQ :2, + SMB0FRQ :2, + SML0FRQ :2, + :4, + LANPHYPC_GP12_SEL :1, + cs_ss1 :1, + :2, + DMI_REQID_DIS :1, + :4, + BBBS :2, + :1; + }; + struct { /* STRP1 */ + uint32_t cs_ss3 :4, + :28; + }; + struct { /* STRP2 */ + uint32_t :8, + MESMASDEN :1, + MESMASDA :7, + :8, + MESMI2CEN :1, + MESMI2CA :7; + }; + struct { /* STRP3 */ + uint32_t :32; + }; + struct { /* STRP4 */ + uint32_t PHYCON :2, + :6, + GBEMAC_SMBUS_ADDR_EN :1, + GBEMAC_SMBUS_ADDR :7, + :1, + GBEPHY_SMBUS_ADDR :7, + :8; + }; + struct { /* STRP5 */ + uint32_t :32; + }; + struct { /* STRP6 */ + uint32_t :32; + }; + struct { /* STRP7 */ + uint32_t MESMA2UDID_VENDOR :16, + MESMA2UDID_DEVICE :16; + }; + struct { /* STRP8 */ + uint32_t :32; + }; + struct { /* STRP9 */ + uint32_t PCIEPCS1 :2, + PCIEPCS2 :2, + PCIELR1 :1, + PCIELR2 :1, + DMILR :1, + :1, + PHY_PCIEPORTSEL :3, + PHY_PCIE_EN :1, + :20; + }; + struct { /* STRP10 */ + uint32_t :1, + ME_BOOT_FLASH :1, + cs_ss5 :1, + VE_EN :1, + :4, + MMDDE :1, + MMADDR :7, + cs_ss7 :1, + :1, + ICC_SEL :3, + MER_CL1 :1, + :10; + }; + struct { /* STRP11 */ + uint32_t SML1GPAEN :1, + SML1GPA :7, + :16, + SML1I2CAEN :1, + SML1I2CA :7; + }; + struct { /* STRP12 */ + uint32_t :32; + }; + struct { /* STRP13 */ + uint32_t :32; + }; + struct { /* STRP14 */ + uint32_t :8, + VE_EN2 :1, + :5, + VE_BOOT_FLASH :1, + :1, + BW_SSD :1, + NVMHCI_EN :1, + :14; + }; + struct { /* STRP15 */ + uint32_t :3, + cs_ss6 :2, + :1, + IWL_EN :1, + :1, + t209min :2, + :22; + }; + }ibex; + }; +}; + +struct ich_desc_upper_map { + union { + uint32_t FLUMAP1; /* Flash Upper Map 1 */ + struct { + uint32_t VTBA :8, /* ME VSCC Table Base Address */ + VTL :8, /* ME VSCC Table Length */ + :16; + }; + }; + struct { + union { /* JEDEC-ID Register */ + uint32_t JID; + struct { + uint32_t vid :8, /* Vendor ID */ + cid0 :8, /* Component ID 0 */ + cid1 :8, /* Component ID 1 */ + :8; + }; + }; + union { /* Vendor Specific Component Capabilities */ + uint32_t VSCC; + struct { + uint32_t ubes :2, /* Upper Block/Sector Erase Size */ + uwg :1, /* Upper Write Granularity */ + uwsr :1, /* Upper Write Status Required */ + uwews :1, /* Upper Write Enable on Write Status */ + :3, + ueo :8, /* Upper Erase Opcode */ + lbes :2, /* Lower Block/Sector Erase Size */ + lwg :1, /* Lower Write Granularity */ + lwsr :1, /* Lower Write Status Required */ + lwews :1, /* Lower Write Enable on Write Status */ + :3, + leo :16; /* Lower Erase Opcode */ + }; + }; + } vscc_table[128]; +}; +#endif /* ICH_DESCRIPTORS_FROM_DUMP */ + struct ich_descriptors { struct ich_desc_content content; struct ich_desc_component component; struct ich_desc_region region; struct ich_desc_master master; +#ifdef ICH_DESCRIPTORS_FROM_DUMP + struct ich_desc_north_strap north; + struct ich_desc_south_strap south; + struct ich_desc_upper_map upper; +#endif /* ICH_DESCRIPTORS_FROM_DUMP */ }; void prettyprint_ich_descriptors(enum ich_chipset, const struct ich_descriptors *desc); @@ -254,9 +449,18 @@ void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc); void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc); void prettyprint_ich_descriptor_master(const struct ich_desc_master *master); +#ifdef ICH_DESCRIPTORS_FROM_DUMP + +void prettyprint_ich_descriptor_upper_map(const struct ich_desc_upper_map *umap); +void prettyprint_ich_descriptor_straps(enum ich_chipset cs, const struct ich_descriptors *desc); +int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, enum ich_chipset cs, struct ich_descriptors *desc); + +#else /* ICH_DESCRIPTORS_FROM_DUMP */ + int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc); int getFCBA_component_density(uint8_t idx, const struct ich_descriptors *desc); - + +#endif /* ICH_DESCRIPTORS_FROM_DUMP */ #endif /* BITFIELDS == 1 */ #endif /* __ICH_DESCRIPTORS_H__ */ #endif /* defined(__i386__) || defined(__x86_64__) */ diff --git a/util/ich_descriptors_tool/Makefile b/util/ich_descriptors_tool/Makefile new file mode 100644 index 0000000..3afd480 --- /dev/null +++ b/util/ich_descriptors_tool/Makefile @@ -0,0 +1,63 @@ +CC ?= gcc + +PROGRAM=ich_descriptors_tool +EXTRAINCDIRS = ../../ . +DEPPATH = .dep +OBJATH = .obj +SHAREDSRC = ich_descriptors.c +SHAREDSRCDIR = ../.. + +SRC = $(wildcard *.c) + +CFLAGS += -Wall +CFLAGS += -MMD -MP -MF $(DEPPATH)/$((a)F).d +# enables functions that populate the descriptor structs from plain binary dumps +CFLAGS += -D ICH_DESCRIPTORS_FROM_DUMP +CFLAGS += -D BITFIELDS +CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) + +OBJ = $(OBJATH)/$(SRC:%.c=%.o) + +SHAREDOBJ = $(OBJATH)/$(notdir $(SHAREDSRC:%.c=%.o)) + +all:$(PROGRAM) + +$(OBJ): $(OBJATH)/%.o : %.c + $(CC) $(CFLAGS) -o $@ -c $< + +# this enables us to share source files without simultaneously sharing .o files +# with flashrom, which would lead to unexpected results (w/o running make clean) +$(SHAREDOBJ): $(OBJATH)/%.o : $(SHAREDSRCDIR)/%.c + $(CC) $(CFLAGS) -o $@ -c $< + +$(PROGRAM): bitfields $(OBJ) $(SHAREDOBJ) + $(CC) -o $(PROGRAM) $(OBJ) $(SHAREDOBJ) + +clean: + rm -f $(PROGRAM) + rm -rf $(DEPPATH) $(OBJATH) + +define BITFIELDS_TEST +#include "ich_descriptors.h" +int main(int argc, char **argv) +{ + struct ich_descriptors desc; + (void) argc; + (void) argv; + desc.region.FLREGs[4] = 0x5aa5a55a; + return desc.region.reg4_base; +} +endef +export BITFIELDS_TEST + +bitfields: + @printf "Checking if bit-fields support is sufficient... " + @echo "$$BITFIELDS_TEST" > .test.c + @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) -D BITFIELDS .test.c -o .test$ >/dev/null 2>&1 && \ + ( echo "yes." ; rm -f .test.c .test ) || \ + ( echo "no."; rm -f .test.c .test; exit 1) + +# Include the dependency files. +-include $(shell mkdir -p $(DEPPATH) $(OBJATH) 2>/dev/null) $(wildcard $(DEPPATH)/*) + +.PHONY: all clean bitfields diff --git a/util/ich_descriptors_tool/TODO b/util/ich_descriptors_tool/TODO new file mode 100644 index 0000000..03701bf --- /dev/null +++ b/util/ich_descriptors_tool/TODO @@ -0,0 +1,6 @@ +- reverse the path, as in assemble a descriptormode image from various + blobs (BIOS, GbE, ME, OEM) and a description (xml? custom config? + sane defaults and cmd-line switches?) +- dump 256 OEM bytes +- handle descriptors of various chipsets correctly +- little endian only diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c new file mode 100644 index 0000000..3721eb4 --- /dev/null +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -0,0 +1,225 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (C) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * dump information and binaries from BIOS images that are in descriptor mode + */ +#include <stdio.h> +#include <stdint.h> +#include <stdlib.h> +#include <sys/mman.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <fcntl.h> +#include <unistd.h> +#include <string.h> +#include <errno.h> +#include "ich_descriptors.h" + +static void dump_file(const char *basename, const uint32_t *dump, unsigned int len, struct ich_desc_region *reg, unsigned int i) +{ + int ret; + char *fn; + const char *reg_name; + uint32_t file_len; + const char *const region_names[5] = { + "Descriptor", "BIOS", "ME", "GbE", "Platform" + }; + uint32_t base = ICH_FREG_BASE(reg->FLREGs[i]); + uint32_t limit = ICH_FREG_LIMIT(reg->FLREGs[i]); + + reg_name = region_names[i]; + if (base > limit) { + printf("The %s region is unused and thus not dumped.\n", + reg_name); + return; + } + + limit = limit | 0x0fff; + file_len = limit + 1 - base; + if (base + file_len > len) { + printf("The %s region is spanning 0x%08x-0x%08x, but it is " + "not (fully) included in the image (0-0x%08x), thus not " + "dumped.\n", reg_name, base, limit, len - 1); + return; + } + + fn = malloc(strlen(basename) + strlen(reg_name) + strlen(".bin") + 2); + if (!fn) { + fprintf(stderr, "Out of memory!\n"); + exit(1); + } + snprintf(fn, strlen(basename) + strlen(reg_name) + strlen(".bin") + 2, + "%s.%s.bin", basename, reg_name); + printf("Dumping %u bytes of the %s region from 0x%08x-0x%08x to %s... ", + file_len, region_names[i], base, limit, fn); + int fh = open(fn, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); + free(fn); + if (fh < 0) { + fprintf(stderr, + "ERROR: couldn't open(%s): %s\n", fn, strerror(errno)); + exit(1); + } + + ret = write(fh, &dump[base >> 2], file_len); + if (ret != file_len) { + fprintf(stderr, "FAILED.\n"); + exit(1); + } + + printf("done.\n"); + close(fh); +} + +void dump_files(const char *n, const uint32_t *buf, unsigned int len, struct ich_desc_region *reg) +{ + unsigned int i; + printf("=== Dumping region files ===\n"); + for (i = 0; i < 5; i++) + dump_file(n, buf, len, reg, i); + printf("\n"); +} + +static void usage(char *argv[], char *error) +{ + if (error != NULL) { + fprintf(stderr, "%s\n", error); + } + printf("usage: '%s -f <image file name> [-c <chipset name>] [-d]'\n\n" +"where <image file name> points to an image of the contents of the SPI flash.\n" +"In case that image is really in descriptor mode %s\n" +"will pretty print some of the contained information.\n" +"To also print the data stored in the descriptor strap you have to indicate\n" +"the chipset series with the '-c' parameter and one of the possible arguments:\n" +"\t- \"ich8\",\n" +"\t- \"ich9\",\n" +"\t- \"ich10\",\n" +"\t- \"5\" or \"ibex\" for Intel's 5 series chipsets,\n" +"\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n" +"\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n" +"If '-d' is specified some regions such as the BIOS image as seen by the CPU or\n" +"the GbE blob that is required to initialize the GbE are also dumped to files.\n", + argv[0], argv[0]); + exit(1); +} + +int main(int argc, char *argv[]) +{ + int fd; /* file descriptor to flash file */ + int len; /* file/buffer size in bytes */ + uint32_t *buf; /* mmap'd file */ + + int opt; + int ret; + int dump = 0; + const char *fn = NULL; + const char *csn = NULL; + enum ich_chipset cs = CHIPSET_ICH_UNKNOWN; + struct ich_descriptors desc = {{ 0 }}; + + while ((opt = getopt(argc, argv, "df:c:")) != -1) { + switch (opt) { + case 'd': + dump = 1; + break; + case 'f': + fn = optarg; + break; + case 'c': + csn = optarg; + break; + default: /* '?' */ + usage(argv, NULL); + } + } + if (fn == NULL) + usage(argv, + "Need a file name of a descriptor image to read from."); + + fd = open(fn, O_RDONLY); + if (fd < 0) + usage(argv, "No such file"); + len = lseek(fd, 0, SEEK_END); + if (len < 0) + usage(argv, "Seeking to the end of the file failed"); + + buf = mmap(NULL, len, PROT_READ, MAP_PRIVATE, fd, 0); + if (buf == (void *) -1) { + /* fallback for stupid OSes like cygwin */ + int ret; + buf = malloc(len); + if (!buf) + usage(argv, "Could not allocate memory"); + lseek(fd, 0, SEEK_SET); + ret = read(fd, buf, len); + if (ret != len) + usage(argv, "Seeking to the end of the file failed"); + } + printf("The flash image has a size of %d [0x%x] bytes.\n", len, len); + close(fd); + + if (csn != NULL) { + if (strcmp(csn, "ich8") == 0) + cs = CHIPSET_ICH8; + else if (strcmp(csn, "ich9") == 0) + cs = CHIPSET_ICH9; + else if (strcmp(csn, "ich10") == 0) + cs = CHIPSET_ICH10; + else if ((strcmp(csn, "5") == 0) || + (strcmp(csn, "ibex") == 0)) + cs = CHIPSET_5_SERIES_IBEX_PEAK; + else if ((strcmp(csn, "6") == 0) || + (strcmp(csn, "cougar") == 0)) + cs = CHIPSET_6_SERIES_COUGAR_POINT; + else if ((strcmp(csn, "7") == 0) || + (strcmp(csn, "panther") == 0)) + cs = CHIPSET_7_SERIES_PANTHER_POINT; + } + + ret = read_ich_descriptors_from_dump(buf, len, cs, &desc); + switch (ret) { + case RET_OK: + break; + case RET_ERR: + printf("Image not in descriptor mode.\n"); + exit(1); + case RET_OOB: + printf("Tried to access a location out of bounds of the image. " + "- Corrupt image?\n"); + exit(1); + default: + printf("Unhandled return value at %s:%u, please report this.\n", + __FILE__, __LINE__); + exit(1); + } + + prettyprint_ich_descriptors(cs, &desc); + + //uint8_t *pMAC = (uint8_t *) &buf[r->reg3_base >> 2]; + //printf("The MAC-address might be: %02x:%02x:%02x:%02x:%02x:%02x\n", + //pMAC[0], pMAC[1], pMAC[2], pMAC[3], pMAC[4], pMAC[5]); + + if (dump == 1) + dump_files(fn, buf, len, &desc.region); + + return 0; +} + -- 1.7.1

1 0

[PATCH 7/8] ichspi: unlock PR register restrictions if not locked down
by Stefan Tauner 20 Aug '11

20 Aug '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 22 ++++++++++++++++++++++ 1 files changed, 22 insertions(+), 0 deletions(-) diff --git a/ichspi.c b/ichspi.c index c38fbfc..a9327de 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1507,6 +1507,24 @@ static void prettyprint_ich9_reg_pr(int i) msg_pdbg(", unused)\n"); } +/* Set the read and write protection enable bits of PR register @i according to + * @read_prot and @write_prot. */ +static void ich8_set_pr(int i, int read_prot, int write_prot) +{ + void *addr = ich_spibar + ICH9_REG_PR0 + (i * 4); + uint32_t pr = mmio_readl(addr); + + msg_gspew("PR%u is 0x%08x, ", i, pr); + pr &= ~((1 << PR_RP_OFF) | (1 << PR_WP_OFF)); + if (read_prot) + pr |= (1 << PR_RP_OFF); + if (write_prot) + pr |= (1 << PR_WP_OFF); + msg_gspew("trying to set it to 0x%08x ", pr); + mmio_writel(pr, addr); + msg_gspew("resulted in 0x%08x.\n", mmio_readl(addr)); +} + static const struct spi_programmer spi_programmer_ich7 = { .type = SPI_CONTROLLER_ICH7, .max_data_read = 64, @@ -1648,6 +1666,10 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, for(i = 0; i < 5; i++) do_ich9_spi_frap(tmp, i); + /* try to disable PR locks before printing them */ + if (!ichspi_lock) + for(i = 0; i < 5; i++) + ich8_set_pr(i, 0, 0); for(i = 0; i < 5; i++) prettyprint_ich9_reg_pr(i); -- 1.7.1

1 0

[PATCH 6/8] ichspi: add prettyprinting for PR registers
by Stefan Tauner 20 Aug '11

20 Aug '11

Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 45 +++++++++++++++++++++++++++++++-------------- 1 files changed, 31 insertions(+), 14 deletions(-) diff --git a/ichspi.c b/ichspi.c index 61c0825..c38fbfc 100644 --- a/ichspi.c +++ b/ichspi.c @@ -73,10 +73,8 @@ #define ICH9_REG_FREG0 0x54 /* 32 Bytes Flash Region 0 */ #define ICH9_REG_PR0 0x74 /* 32 Bytes Protected Range 0 */ -#define ICH9_REG_PR1 0x78 /* 32 Bytes Protected Range 1 */ -#define ICH9_REG_PR2 0x7c /* 32 Bytes Protected Range 2 */ -#define ICH9_REG_PR3 0x80 /* 32 Bytes Protected Range 3 */ -#define ICH9_REG_PR4 0x84 /* 32 Bytes Protected Range 4 */ +#define PR_WP_OFF 31 /* 31: write protection enable */ +#define PR_RP_OFF 15 /* 15: read protection enable */ #define ICH9_REG_SSFS 0x90 /* 08 Bits */ #define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */ @@ -1482,6 +1480,33 @@ static void do_ich9_spi_frap(uint32_t frap, int i) } + /* In contrast to FRAP and the master section of the descriptor the bits + * in the PR registers have an inverted meaning. The bits in FRAP + * indicate read and write access _grant_. Here they indicate read + * and write _protection_ respectively. If both bits are 0 the address + * bits are ignored. + */ +#define ICH_PR_PERMS(pr) (((~((pr) >> PR_RP_OFF) & 1) << 0) | \ + ((~((pr) >> PR_WP_OFF) & 1) << 1)) + +static void prettyprint_ich9_reg_pr(int i) +{ + static const char *const access_names[4] = { + "locked", "read-only", "write-only", "read-write" + }; + uint8_t off = ICH9_REG_PR0 + (i * 4); + uint32_t pr = mmio_readl(ich_spibar + off); + int rwperms = ICH_PR_PERMS(pr); + + msg_pdbg("0x%02X: 0x%08x (PR%u", off, pr, i); + if (rwperms != 0x3) + msg_pdbg(")\n0x%08x-0x%08x is %s\n", (ICH_FREG_BASE(pr) << 12), + (ICH_FREG_LIMIT(pr) << 12) | 0x0fff, + access_names[rwperms]); + else + msg_pdbg(", unused)\n"); +} + static const struct spi_programmer spi_programmer_ich7 = { .type = SPI_CONTROLLER_ICH7, .max_data_read = 64, @@ -1623,16 +1648,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, for(i = 0; i < 5; i++) do_ich9_spi_frap(tmp, i); - msg_pdbg("0x74: 0x%08x (PR0)\n", - mmio_readl(ich_spibar + ICH9_REG_PR0)); - msg_pdbg("0x78: 0x%08x (PR1)\n", - mmio_readl(ich_spibar + ICH9_REG_PR1)); - msg_pdbg("0x7C: 0x%08x (PR2)\n", - mmio_readl(ich_spibar + ICH9_REG_PR2)); - msg_pdbg("0x80: 0x%08x (PR3)\n", - mmio_readl(ich_spibar + ICH9_REG_PR3)); - msg_pdbg("0x84: 0x%08x (PR4)\n", - mmio_readl(ich_spibar + ICH9_REG_PR4)); + for(i = 0; i < 5; i++) + prettyprint_ich9_reg_pr(i); tmp = mmio_readl(ich_spibar + ICH9_REG_SSFS); msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff); -- 1.7.1

1 0

[PATCH 5/8] ichspi: add support for Intel Hardware Sequencing
by Stefan Tauner 20 Aug '11

20 Aug '11

todo: - revise hwseq activation: when should hwseq be used, when swseq? in the current version i have added a programmer parameter to tell flashrom when one wants to use hwseq _if it is available_ (i.e. descriptor valid), example: flashrom -p internal:laptop=force_I_want_a_brick,hwseq=yes -VV this needs to be documented in the man page if it gets merged like that. - commit message (is a link to my blog post a good idea (additionally)?) - revise (levels of) prints - revise timeout values (for optimal performance) - build upon the upcoming opaque interface framework instead Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipdrivers.h | 6 + flashchips.c | 23 ++++- flashchips.h | 2 + ich_descriptors.c | 35 +++++ ich_descriptors.h | 3 +- ichspi.c | 357 +++++++++++++++++++++++++++++++++++++++++++++++++++-- programmer.h | 1 + 7 files changed, 414 insertions(+), 13 deletions(-) diff --git a/chipdrivers.h b/chipdrivers.h index 3f5b503..f3781ae 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -86,6 +86,12 @@ void print_status_82802ab(uint8_t status); int unlock_82802ab(struct flashchip *flash); int unlock_28f004s5(struct flashchip *flash); +/* ichspi.c */ +int ich_hwseq_probe(struct flashchip *flash); +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int start, int len); +int ich_hwseq_block_erase(struct flashchip *flash, unsigned int addr, unsigned int blocklen); +int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); + /* jedec.c */ uint8_t oddparity(uint8_t val); void toggle_ready_jedec(chipaddr dst); diff --git a/flashchips.c b/flashchips.c index 4d741a0..20f7197 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8782,7 +8782,27 @@ const struct flashchip flashchips[] = { .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program */ }, - +#if defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) + { + .vendor = "Intel", + .name = "Hardware Sequencing", + .bustype = BUS_SPI, + .manufacture_id = INTEL_ID, + .model_id = INTEL_HWSEQ, + .total_size = 0, + .page_size = 256, + .tested = TEST_OK_PREW, + .probe = ich_hwseq_probe, + .block_erasers = + { + { /* erase blocks will be set by the probing function */ + .block_erase = ich_hwseq_block_erase, + } + }, + .write = ich_hwseq_write_256, + .read = ich_hwseq_read, + }, +#endif // defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) { .vendor = "AMIC", .name = "unknown AMIC SPI chip", @@ -8915,6 +8935,7 @@ const struct flashchip flashchips[] = { .probe = probe_spi_rdid, .write = NULL, }, + { .vendor = "Generic", .name = "unknown SPI chip (REMS)", diff --git a/flashchips.h b/flashchips.h index ff49d31..1374b2f 100644 --- a/flashchips.h +++ b/flashchips.h @@ -346,6 +346,8 @@ #define SHARP_LH28F008SA 0xA2 /* Sharp chip, Intel Vendor ID */ #define SHARP_LH28F008SC 0xA6 /* Sharp chip, Intel Vendor ID */ +#define INTEL_HWSEQ 0xFFFE /* dummy ID for hardware sequencing */ + #define ISSI_ID 0xD5 /* ISSI Integrated Silicon Solutions */ /* diff --git a/ich_descriptors.c b/ich_descriptors.c index ce40d9f..8076b09 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -214,6 +214,41 @@ void prettyprint_ich_descriptor_master(const struct ich_desc_master *mstr) msg_pdbg2("\n"); } +/** Returns the integer representation of the component density with index +idx in bytes or 0 if a correct size can not be determined. */ +int getFCBA_component_density(uint8_t idx, const struct ich_descriptors *desc) +{ + uint8_t size_enc; + static const int const dec_mem[6] = { + 512 * 1024, + 1 * 1024 * 1024, + 2 * 1024 * 1024, + 4 * 1024 * 1024, + 8 * 1024 * 1024, + 16 * 1024 * 1024, + }; + + switch(idx) { + case 0: + size_enc = desc->component.comp1_density; + break; + case 1: + if (desc->content.NC == 0) + return 0; + size_enc = desc->component.comp2_density; + break; + default: + msg_perr("Only component index 0 or 1 are supported yet.\n"); + return 0; + } + if (size_enc > 5) { + msg_perr("Density of component with index %d is invalid. " + "Encoded density is 0x%x.\n", idx, size_enc); + return 0; + } + return dec_mem[size_enc]; +} + static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) { uint32_t control = 0; diff --git a/ich_descriptors.h b/ich_descriptors.h index b1da914..8ab798f 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -255,7 +255,8 @@ void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc); void prettyprint_ich_descriptor_master(const struct ich_desc_master *master); int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc); - +int getFCBA_component_density(uint8_t idx, const struct ich_descriptors *desc); + #endif /* BITFIELDS == 1 */ #endif /* __ICH_DESCRIPTORS_H__ */ #endif /* defined(__i386__) || defined(__x86_64__) */ diff --git a/ichspi.c b/ichspi.c index 2e25d34..61c0825 100644 --- a/ichspi.c +++ b/ichspi.c @@ -26,7 +26,10 @@ #if defined(__i386__) || defined(__x86_64__) #include <string.h> +#include <stdlib.h> #include "flash.h" +#include "flashchips.h" +#include "chipdrivers.h" #include "programmer.h" #include "spi.h" #include "ich_descriptors.h" @@ -1084,6 +1087,298 @@ static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, return result; } +static struct hwseq { + uint32_t size_comp0; + uint32_t size_comp1; +} hwseq; + +static void ich_hwseq_set_addr(uint32_t addr) +{ + uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF; + REGWRITE32(ICH9_REG_FADDR, (addr & 0x01FFFFFF) | addr_old); +} + +/* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes + * of the block containing this address. */ +static uint32_t ich_hwseq_get_erase_block_size(unsigned int addr) +{ + uint8_t enc_berase; + static const uint32_t const dec_berase[4] = { + 256, + 4 * 1024, + 8 * 1024, + 64 * 1024 + }; + + ich_hwseq_set_addr(addr); + enc_berase = (REGREAD16(ICH9_REG_HSFS) & HSFS_BERASE) >> + HSFS_BERASE_OFF; + return dec_berase[enc_berase]; +} + +/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 10 us intervals. + Resets all error flags in HSFS. + Returns 0 if the cycle completes successfully without errors within + timeout us, 1 on errors. */ +static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, + unsigned int len) +{ + uint16_t hsfs; + uint32_t addr; + + while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) & + (HSFS_FDONE | HSFS_FCERR)) == 0) && + --timeout) { + programmer_delay(10); + } + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + if (!timeout) { + addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; + msg_perr("Timeout error between offset 0x%08x and " + "0x%08x + %d (=0x%08x)!\n", + addr, addr, len - 1, addr + len - 1); + prettyprint_ich9_reg_hsfs(hsfs); + prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); + return 1; + } + + if (hsfs & HSFS_FCERR) { + addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; + msg_perr("Transaction error between offset 0x%08x and " + "0x%08x (=0x%08x + %d)!\n", + addr, addr + len - 1, addr, len - 1); + prettyprint_ich9_reg_hsfs(hsfs); + prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); + return 1; + } + return 0; +} + +int ich_hwseq_probe(struct flashchip *flash) +{ + uint32_t total_size, boundary; + uint32_t erase_size_low, size_low, erase_size_high, size_high; + struct block_eraser *eraser; + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_cerr("This chip (%s) is not supported in hardware" + "sequencing mode and should never have been probed.\n", + flash->name); + msg_cerr("%s: Please report a bug at flashrom(a)flashrom.org\n", + __func__); + return 0; + } + + msg_cdbg("Prerequisites for Intel Hardware Sequencing are "); + if (spi_programmer->type != SPI_CONTROLLER_ICH_HWSEQ) { + msg_cdbg("not met.\n"); + return 0; + } + msg_cdbg("met.\n"); + + total_size = hwseq.size_comp0 + hwseq.size_comp1; + msg_cdbg("Found %d attached SPI flash chip", + (hwseq.size_comp1 != 0) ? 2 : 1); + if (hwseq.size_comp1 != 0) + msg_cdbg("s with a combined"); + else + msg_cdbg(" with a"); + msg_cdbg(" density of %d kB.\n", total_size / 1024); + flash->total_size = total_size / 1024; + + eraser = &(flash->block_erasers[0]); + boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12; + size_high = total_size - boundary; + erase_size_high = ich_hwseq_get_erase_block_size(boundary); + + if (boundary == 0) { + msg_cdbg("There is only one partition containing the whole " + "address space (0x%06x - 0x%06x).\n", 0, size_high-1); + eraser->eraseblocks[0].size = erase_size_high; + eraser->eraseblocks[0].count = size_high / erase_size_high; + msg_cdbg("There are %d erase blocks with %d B each.\n", + size_high / erase_size_high, erase_size_high); + } else { + msg_cdbg("The flash address space (0x%06x - 0x%06x) is divided " + "at address 0x%06x in two partitions.\n", + 0, size_high-1, boundary); + size_low = total_size - size_high; + erase_size_low = ich_hwseq_get_erase_block_size(0); + + eraser->eraseblocks[0].size = erase_size_low; + eraser->eraseblocks[0].count = size_low / erase_size_low; + msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n", + 0, size_low-1); + msg_cdbg("In that range are %d erase blocks with %d B each.\n", + size_low / erase_size_low, erase_size_low); + + eraser->eraseblocks[1].size = erase_size_high; + eraser->eraseblocks[1].count = size_high / erase_size_high; + msg_cdbg("The second partition ranges from 0x%06x to 0x%06x.\n", + boundary, size_high-1); + msg_cdbg("In that range are %d erase blocks with %d B each.\n", + size_high / erase_size_high, erase_size_high); + } + return 1; +} + +static int ich_hwseq_send_command(unsigned int writecnt, + unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + msg_pdbg("skipped. Intel Hardware Sequencing does not support sending " + "arbitrary commands."); + return -1; +} + +int ich_hwseq_block_erase(struct flashchip *flash, + unsigned int addr, + unsigned int len) +{ + uint32_t erase_block; + uint16_t hsfc; + uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */ + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode\n", flash->name); + return -1; + } + + erase_block = ich_hwseq_get_erase_block_size(addr); + if (len != erase_block) { + msg_cerr("Erase block size for address 0x%06x is %d B, " + "but requested erase block size is %d B. " + "Not erasing anything.\n", addr, erase_block, len); + return -1; + } + + /* Although the hardware supports this (it would erase the whole block + * containing the address) we play safe here. */ + if (addr % erase_block != 0) { + msg_cerr("Erase address 0x%06x is not aligned to the erase " + "block boundary (any multiple of %d). " + "Not erasing anything.\n", addr, erase_block); + return -1; + } + + if (addr + len > flash->total_size * 1024) { + msg_perr("Request to erase some inaccessible memory address(es)" + " (addr=0x%x, len=%d). " + "Not erasing anything.\n", addr, len); + return -1; + } + + msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr); + + /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ + hsfc |= HSFC_FGO; /* start */ + msg_pdbg("HSFC used for block erasing: "); + prettyprint_ich9_reg_hsfc(hsfc); + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, len)) + return -1; + return 0; +} + +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int addr, int len) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode.\n", flash->name); + return -1; + } + + if (addr < 0 || addr + len > flash->total_size * 1024) { + msg_perr("Request to read from an inaccessible memory address " + "(addr=0x%x, len=%d).\n", addr, len); + return -1; + } + + msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + while (len > 0) { + block_len = min(len, spi_programmer->max_data_read); + ich_hwseq_set_addr(addr); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* set read operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + return 1; + ich_read_data(buf, block_len, ICH9_REG_FDATA0); + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} + +int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, int addr, int len) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode\n", flash->name); + return -1; + } + + if (addr < 0 || addr + len > flash->total_size * 1024) { + msg_perr("Request to write to an inaccessible memory address " + "(addr=0x%x, len=%d).\n", addr, len); + return -1; + } + + msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + while (len > 0) { + ich_hwseq_set_addr(addr); + block_len = min(len, spi_programmer->max_data_write); + ich_fill_data(buf, block_len, ICH9_REG_FDATA0); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + return -1; + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} + static int ich_spi_send_multicommand(struct spi_command *cmds) { int ret = 0; @@ -1207,6 +1502,16 @@ static const struct spi_programmer spi_programmer_ich9 = { .write_256 = default_spi_write_256, }; +static const struct spi_programmer spi_programmer_ich_hwseq = { + .type = SPI_CONTROLLER_ICH_HWSEQ, + .max_data_read = 64, + .max_data_write = 64, + .command = ich_hwseq_send_command, + .multicommand = default_spi_send_multicommand, + .read = ich_hwseq_read, + .write_256 = ich_hwseq_write_256, +}; + int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, int ich_generation) { @@ -1214,21 +1519,20 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, uint8_t old, new; uint16_t spibar_offset, tmp2; uint32_t tmp; + char *arg; int ichspi_desc = 0; + int hwseq_en = 0; switch (ich_generation) { case 7: - register_spi_programmer(&spi_programmer_ich7); spibar_offset = 0x3020; break; case 8: - register_spi_programmer(&spi_programmer_ich9); spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ - register_spi_programmer(&spi_programmer_ich9); spibar_offset = 0x3800; break; } @@ -1239,8 +1543,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, /* Assign Virtual Address */ ich_spibar = rcrb + spibar_offset; - switch (spi_programmer->type) { - case SPI_CONTROLLER_ICH7: + switch (ich_generation) { + case 7: msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", @@ -1277,9 +1581,21 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, ichspi_lock = 1; } ich_set_bbar(ich_generation, 0); + register_spi_programmer(&spi_programmer_ich7); ich_init_opcodes(); break; - case SPI_CONTROLLER_ICH9: + case 8: + case 9: + case 10: + default: /* Future version might behave the same */ + arg = extract_programmer_param("hwseq"); + if (arg && !strcmp(arg, "yes")) + hwseq_en = 1; + else if (arg && !strlen(arg)) + msg_pinfo("Missing argument for hwseq.\n"); + else if (arg) + msg_pinfo("Unknown argument for hwseq: %s\n", arg); + free(arg); tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); prettyprint_ich9_reg_hsfs(tmp2); @@ -1363,18 +1679,37 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pdbg("\n"); #if BITFIELDS == 1 + { /* to be able to declare desc here and avoid another + * "#if BITFIELDS == 1" on top + */ + struct ich_descriptors desc = {{ 0 }}; if (ichspi_desc) { - struct ich_descriptors desc = {{ 0 }}; if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == RET_OK) prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, &desc); + /* If the descriptor is valid and indicates multiple + * flash devices we need to use hwseq to be able to + * access the second flash device. + */ + if (desc.content.NC != 0) + hwseq_en = 1; + } else + hwseq_en = 0; /* disable it even if the user said yes */ + + if (hwseq_en > 0) { + hwseq.size_comp0 = getFCBA_component_density(0, &desc); + hwseq.size_comp1 = getFCBA_component_density(1, &desc); + register_spi_programmer(&spi_programmer_ich_hwseq); + } else { + register_spi_programmer(&spi_programmer_ich9); + ich_init_opcodes(); } -#endif /* BITFIELDS == 1 */ + } +#else /* BITFIELDS == 1 */ + register_spi_programmer(&spi_programmer_ich9); ich_init_opcodes(); - break; - default: - /* Nothing */ +#endif /* BITFIELDS == 1 */ break; } diff --git a/programmer.h b/programmer.h index 6a28dbe..6e316d1 100644 --- a/programmer.h +++ b/programmer.h @@ -517,6 +517,7 @@ enum spi_controller { #if defined(__i386__) || defined(__x86_64__) SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, + SPI_CONTROLLER_ICH_HWSEQ, SPI_CONTROLLER_IT85XX, SPI_CONTROLLER_IT87XX, SPI_CONTROLLER_SB600, -- 1.7.1

1 0

[PATCH 4/8] ichspi: improve prettyprint_opcodes
by Stefan Tauner 20 Aug '11

20 Aug '11

add headers for the columns and some decoding into human readable format. --- before: […] Reading OPCODES... done preop0=0x06, preop1=0x50 op[0]=0x02, 3, 0 op[1]=0x03, 2, 0 op[2]=0x20, 3, 0 op[3]=0x05, 0, 0 op[4]=0x9f, 0, 1 op[5]=0x20, 1, 2 op[6]=0x01, 1, 0 op[7]=0x06, 0, 0 SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: FWH, SPI. […] after: […] Reading OPCODES... done OP Type Pre-OP op[0]: 0x02, write w/ addr, none op[1]: 0x03, read w/ addr, none op[2]: 0x20, write w/ addr, none op[3]: 0x05, read w/o addr, none op[4]: 0x9f, read w/o addr, none op[5]: 0x20, write w/o addr, 1 op[6]: 0x01, write w/o addr, 2 op[7]: 0x06, read w/o addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x50 SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: FWH, SPI. […] i could also print the preops directly in the preop column instead of using that redirection. but i think as debug output it is better to know the index of the two preops too. side note: does it make sense to create an opcode -> string decoder for flashrom-wide usage in user output (in spi25.c)? an erase opcode -> function pointer decoder is used in sfdp, that could also be generalized like that. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 34 +++++++++++++++++++++++----------- 1 files changed, 23 insertions(+), 11 deletions(-) diff --git a/ichspi.c b/ichspi.c index d51a6b2..2e25d34 100644 --- a/ichspi.c +++ b/ichspi.c @@ -294,22 +294,34 @@ static OPCODES O_EXISTING = {}; /* pretty printing functions */ static void prettyprint_opcodes(OPCODES *ops) { - if(ops == NULL) - return; - - msg_pdbg("preop0=0x%02x, preop1=0x%02x\n", ops->preop[0], - ops->preop[1]); - OPCODE oc; + const char *t; + const char *a; uint8_t i; + static const char *const spi_type[4] = { + "read w/o addr", + "write w/o addr", + "read w/ addr", + "write w/ addr" + }; + static const char *const atomic_type[3] = { + "none", + " 0 ", + " 1 " + }; + + if (ops == NULL) + return; + + msg_pdbg(" OP Type Pre-OP\n"); for (i = 0; i < 8; i++) { oc = ops->opcode[i]; - msg_pdbg("op[%d]=0x%02x, %d, %d\n", - i, - oc.opcode, - oc.spi_type, - oc.atomic); + t = (oc.spi_type > 3) ? "invalid" : spi_type[oc.spi_type]; + a = (oc.atomic > 2) ? "invalid" : atomic_type[oc.atomic]; + msg_pdbg("op[%d]: 0x%02x, %s, %s\n", i, oc.opcode, t, a); } + msg_pdbg("Pre-OP 0: 0x%02x, Pre-OP 1: 0x%02x\n", ops->preop[0], + ops->preop[1]); } #define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) -- 1.7.1

1 0

[PATCH 3/8] ichspi: don't touch the nonexistent(?) BBAR register on ICH8
by Stefan Tauner 20 Aug '11

20 Aug '11

There is no sign of BBAR (BIOS Base Address Configuration Register) in the public datasheet (or specification update) of the ICH8. Also, the offset of that register has changed between ICH7 (SPIBAR + 50h) and ICH9 (SPIBAR + A0h), so we have no clue if or where it is on ICH8. Better don't try to touch it at all and assume/hope it is 0. --- Until now we implicitly accessed it via the ICH9 offset. I think this is an evident sign that the naming of the spi controller types in ichspi.c (SPI_CONTROLLER_VIA, SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9) might not cut it and we should think about introducing a special ICH8 one, even if its struct is identical to the ICH9. having most of the ICH8 code path guarded/controlled by SPI_CONTROLLER_ICH7 or SPI_CONTROLLER_ICH9 (depending on which is more similar in one situation), is an open invitation to similar bugs because one easily forgets that ICH8 is very special. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 25 ++++++++++++------------- 1 files changed, 12 insertions(+), 13 deletions(-) diff --git a/ichspi.c b/ichspi.c index 343a0af..d51a6b2 100644 --- a/ichspi.c +++ b/ichspi.c @@ -558,20 +558,19 @@ static int program_opcodes(OPCODES *op, int enable_undo) * Try to set BBAR (BIOS Base Address Register), but read back the value in case * it didn't stick. */ -static void ich_set_bbar(uint32_t min_addr) +static void ich_set_bbar(int ich_generation, uint32_t min_addr) { int bbar_off; - switch (spi_programmer->type) { - case SPI_CONTROLLER_ICH7: - case SPI_CONTROLLER_VIA: + switch (ich_generation) { + case 7: bbar_off = 0x50; break; - case SPI_CONTROLLER_ICH9: + case 8: + msg_perr("BBAR offset is unknown on ICH8!\n"); + return; + default: /* Future version might behave the same */ bbar_off = ICH9_REG_BBAR; break; - default: - msg_perr("Unknown chipset for BBAR setting!\n"); - return; } ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & ~BBAR_MASK; @@ -589,6 +588,8 @@ static void ich_set_bbar(uint32_t min_addr) */ if (ichspi_bbar != min_addr) msg_perr("Setting BBAR failed!\n"); + else + msg_pspew("Setting BBAR succeeded!\n"); } /* Read len bytes from the fdata/spid register into the data array. @@ -657,11 +658,6 @@ static int ich_init_opcodes(void) msg_pdbg("Programming OPCODES... "); curopcodes_done = &O_ST_M25P; rc = program_opcodes(curopcodes_done, 1); - /* Technically not part of opcode init, but it allows opcodes - * to run without transaction errors by setting the lowest - * allowed address to zero. - */ - ich_set_bbar(0); } if (rc) { @@ -1268,6 +1264,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } + ich_set_bbar(ich_generation, 0); ich_init_opcodes(); break; case SPI_CONTROLLER_ICH9: @@ -1349,6 +1346,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + ich_set_bbar(ich_generation, 0); } msg_pdbg("\n"); @@ -1439,6 +1437,7 @@ int via_init_spi(struct pci_dev *dev) ichspi_lock = 1; } + ich_set_bbar(7, 0); ich_init_opcodes(); return 0; -- 1.7.1

1 0

[PATCH 2/8] ichspi: disable writes when locked or read-only regions are detected
by Stefan Tauner 20 Aug '11

20 Aug '11

Until we are able to unlock regions or at least understand better what consequences writing single regions have, disable writing completely whenever a non-writeable region is detected. NB: the registers might not always reflect the real access status. http://www.flashrom.org/pipermail/flashrom/2011-April/006309.html (this is the sole such report i can remember) --- Might not be the best location to do this, but currently i don't recognize a better one. The warnings are repeated for each non-writeable region. We could surpress it by checking if programmer_may_write is already 0 before printing. the output on my thinkpad is: […] Proceeding anyway because user specified laptop=force_I_want_a_brick Found chipset "Intel QS57". Enabling flash write... WARNING: SPI Configuration Lockdown activated. WARNING: Flash Descriptor region is read-only. Disabling writes. WARNING: Management Engine region is locked. Disabling writes. OK. This chipset supports the following protocols: FWH, SPI. Found Winbond flash chip "W25X64" (8192 kB, SPI) at physical address 0xff800000. […] verbose output is: […] 0x54: 0x00000000 (FREG0: Flash Descriptor) 0x00000000-0x00000fff is read-only WARNING: Flash Descriptor region is read-only. Disabling writes. 0x58: 0x07ff0500 (FREG1: BIOS) 0x00500000-0x007fffff is read-write 0x5C: 0x04ff0003 (FREG2: Management Engine) 0x00003000-0x004fffff is locked WARNING: Management Engine region is locked. Disabling writes. 0x60: 0x00020001 (FREG3: Gigabit Ethernet) 0x00001000-0x00002fff is read-write 0x64: 0x00000fff (FREG4: Platform Data) Platform Data region is unused. […] i think that is ok. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/ichspi.c b/ichspi.c index 09af2b3..343a0af 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1168,6 +1168,15 @@ static void do_ich9_spi_frap(uint32_t frap, int i) msg_pdbg("0x%08x-0x%08x is %s\n", base, (limit | 0x0fff), access_names[rwperms]); + if (rwperms <= 0x1) { + msg_pinfo("WARNING: %s region is %s. Disabling writes.\n", + region_names[i], access_names[rwperms]); + /* FIXME: This needs some refinement when we know how unlocking + * of region works. + */ + programmer_may_write = 0; + } + } static const struct spi_programmer spi_programmer_ich7 = { -- 1.7.1

1 0

[PATCH 1/8] ichspi: add ICH/PCH flash descriptor decoding via FDOC/FDOD
by Stefan Tauner 20 Aug '11

20 Aug '11

based on the work of Matthias 'mazzoo' Wenzel this patch adds pretty printing of those ICH/PCH flash descriptor sections that are cached/mapped by the chipset (and which are therefore reachable via FDOC/FDOD registers). this includes the following: - content section: describes the image and some generic properties (number of sections, offset of sections, PCH/ICH and MCH/PROC strap offsets and lengths) - component section: identify the different SPI flash chips and their capabilities. - region section similarly to a partition table this describes the different regions. the content of FLREG* is derived from this section. - master section defines SPI master (host, ME, GbE) access rights of the individual regions. the content of PR* is derived from this section. this is only a part of the data included in the descriptor. other information can be retrieved from a complete binary dump of the descriptor region only. this patch also adds macros and pretty printing for "Vendor Specific Component Capabilities" registers: there are two of them: lower and upper. they describe the properties of the address space divided by FPBA (which allows to use multiple flash chips or partitions with different properties). the properties of all supported flash chips (together with their RDIDs) are stored in the same format in table in a descriptor section (which is used by the ME apparently). a later patch will use the macros outside of ichspi.c which is the reason why the prettyprinting function and the register bit macros are not defined in ichspi.c but ich_descriptors.h (else they would be moved in the follow-up patch). because this patch relies on (compiler) implementation-specific layouting of bit-fields, it checks for basic compiler support in the makefile and for correct layout before taking any action on runtime. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- Makefile | 25 +++++- ich_descriptors.c | 288 +++++++++++++++++++++++++++++++++++++++++++++++++++++ ich_descriptors.h | 261 ++++++++++++++++++++++++++++++++++++++++++++++++ ichspi.c | 60 +++++++++-- 4 files changed, 622 insertions(+), 12 deletions(-) create mode 100644 ich_descriptors.c create mode 100644 ich_descriptors.h diff --git a/Makefile b/Makefile index 26f978f..247a60c 100644 --- a/Makefile +++ b/Makefile @@ -340,9 +340,11 @@ endif ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' +FEATURE_CFLAGS += $(shell LC_ALL=C grep -q "BITFIELDS := yes" .features && printf "%s" "-D'BITFIELDS=1'") PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o ifeq ($(ARCH),"x86") -PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += it87spi.o it85spi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += ichspi.o ich_descriptors.o else endif NEED_PCI := yes @@ -635,6 +637,19 @@ int main(int argc, char **argv) endef export UTSNAME_TEST +define BITFIELDS_TEST +#include "ich_descriptors.h" +int main(int argc, char **argv) +{ + struct ich_descriptors desc; + (void) argc; + (void) argv; + desc.region.FLREGs[4] = 0x5aa5a55a; + return desc.region.reg4_base; +} +endef +export BITFIELDS_TEST + features: compiler @echo "FEATURES := yes" > .features.tmp ifeq ($(CONFIG_FT2232_SPI), yes) @@ -649,6 +664,14 @@ endif @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) >/dev/null 2>&1 && \ ( echo "found."; echo "UTSNAME := yes" >> .features.tmp ) || \ ( echo "not found."; echo "UTSNAME := no" >> .features.tmp ) +# ugly hack to get a logical AND *sigh* +ifeq ($(CONFIG_INTERNAL)$(ARCH), yes"x86") + @printf "Checking if bit-fields support is sufficient... " + @echo "$$BITFIELDS_TEST" > .featuretest.c + @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) -D BITFIELDS .featuretest.c -o .featuretest$(EXEC_SUFFIX) >/dev/null 2>&1 && \ + ( echo "yes."; echo "BITFIELDS := yes" >> .features.tmp ) || \ + ( echo "no."; echo "BITFIELDS := no" >> .features.tmp ) +endif @$(DIFF) -q .features.tmp .features >/dev/null 2>&1 && rm .features.tmp || mv .features.tmp .features @rm -f .featuretest.c .featuretest$(EXEC_SUFFIX) diff --git a/ich_descriptors.c b/ich_descriptors.c new file mode 100644 index 0000000..ce40d9f --- /dev/null +++ b/ich_descriptors.c @@ -0,0 +1,288 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (c) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if defined(__i386__) || defined(__x86_64__) + +#include "ich_descriptors.h" +#include "flash.h" /* for msg_* */ +#include "programmer.h" + +void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity) +{ + print(verbosity, "BES=0x%x, ", (reg_val & VSCC_BES) >> VSCC_BES_OFF); + print(verbosity, "WG=%d, ", (reg_val & VSCC_WG) >> VSCC_WG_OFF); + print(verbosity, "WSR=%d, ", (reg_val & VSCC_WSR) >> VSCC_WSR_OFF); + print(verbosity, "WEWS=%d, ", (reg_val & VSCC_WEWS) >> VSCC_WEWS_OFF); + print(verbosity, "EO=0x%x, ", (reg_val & VSCC_EO) >> VSCC_EO_OFF); + print(verbosity, "VCL=%d\n", (reg_val & VSCC_VCL) >> VSCC_VCL_OFF); +} + +#if BITFIELDS == 1 +#define getFCBA(cont) (((cont)->FLMAP0 << 4) & 0x00000ff0) +#define getFRBA(cont) (((cont)->FLMAP0 >> 12) & 0x00000ff0) +#define getFMBA(cont) (((cont)->FLMAP1 << 4) & 0x00000ff0) +#define getFISBA(cont) (((cont)->FLMAP1 >> 12) & 0x00000ff0) +#define getFMSBA(cont) (((cont)->FLMAP2 << 4) & 0x00000ff0) + +void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc) +{ + prettyprint_ich_descriptor_content(&desc->content); + prettyprint_ich_descriptor_component(desc); + prettyprint_ich_descriptor_region(desc); + prettyprint_ich_descriptor_master(&desc->master); +} + +void prettyprint_ich_descriptor_content(const struct ich_desc_content *cont) +{ + msg_pdbg2("=== Content Section ===\n"); + msg_pdbg2("FLVALSIG 0x%08x\n", cont->FLVALSIG); + msg_pdbg2("FLMAP0 0x%08x\n", cont->FLMAP0); + msg_pdbg2("FLMAP1 0x%08x\n", cont->FLMAP1); + msg_pdbg2("FLMAP2 0x%08x\n", cont->FLMAP2); + msg_pdbg2("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2("NR (Number of Regions): %5d\n", + cont->NR + 1); + msg_pdbg2("FRBA (Flash Region Base Address): 0x%03x\n", + getFRBA(cont)); + msg_pdbg2("NC (Number of Components): %5d\n", + cont->NC + 1); + msg_pdbg2("FCBA (Flash Component Base Address): 0x%03x\n", + getFCBA(cont)); + msg_pdbg2("ISL (ICH/PCH Strap Length): %5d\n", + cont->ISL); + msg_pdbg2("FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x%03x\n", + getFISBA(cont)); + msg_pdbg2("NM (Number of Masters): %5d\n", + cont->NM + 1); + msg_pdbg2("FMBA (Flash Master Base Address): 0x%03x\n", + getFMBA(cont)); + msg_pdbg2("MSL/PSL (MCH/PROC Strap Length): %5d\n", + cont->MSL); + msg_pdbg2("FMSBA (Flash MCH/PROC Strap Base Address): 0x%03x\n", + getFMSBA(cont)); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc) +{ + static const char * const str_freq[8] = { + "20 MHz", /* 000 */ + "33 MHz", /* 001 */ + "reserved", /* 010 */ + "reserved", /* 011 */ + "50 MHz", /* 100 */ + "reserved", /* 101 */ + "reserved", /* 110 */ + "reserved" /* 111 */ + }; + static const char * const str_mem[8] = { + "512 kB", /* 000 */ + " 1 MB", /* 001 */ + " 2 MB", /* 010 */ + " 4 MB", /* 011 */ + " 8 MB", /* 100 */ + " 16 MB", /* 101 */ + "reserved", /* 110 */ + "reserved", /* 111 */ + }; + + msg_pdbg2("=== Component Section ===\n"); + msg_pdbg2("FLCOMP 0x%08x\n", desc->component.FLCOMP); + msg_pdbg2("FLILL 0x%08x\n", desc->component.FLILL ); + msg_pdbg2("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2("Component 1 density: %s\n", + str_mem[desc->component.comp1_density]); + if (desc->content.NC) + msg_pdbg2("Component 2 density: %s\n", + str_mem[desc->component.comp2_density]); + else + msg_pdbg2("Component 2 is not used.\n"); + msg_pdbg2("Read Clock Frequency: %s\n", + str_freq[desc->component.freq_read]); + msg_pdbg2("Read ID and Status Clock Freq.: %s\n", + str_freq[desc->component.freq_read_id]); + msg_pdbg2("Write and Erase Clock Freq.: %s\n", + str_freq[desc->component.freq_write]); + msg_pdbg2("Fast Read is %ssupported.\n", + desc->component.fastread ? "" : "not "); + if (desc->component.fastread) + msg_pdbg2("Fast Read Clock Frequency: %s\n", + str_freq[desc->component.freq_fastread]); + if (desc->component.FLILL == 0) + msg_pdbg2("No forbidden opcodes.\n"); + else { + msg_pdbg2("Invalid instruction 0: 0x%02x\n", + desc->component.invalid_instr0); + msg_pdbg2("Invalid instruction 1: 0x%02x\n", + desc->component.invalid_instr1); + msg_pdbg2("Invalid instruction 2: 0x%02x\n", + desc->component.invalid_instr2); + msg_pdbg2("Invalid instruction 3: 0x%02x\n", + desc->component.invalid_instr3); + } + msg_pdbg2("\n"); +} + +static void pprint_freg(const struct ich_desc_region *reg, uint32_t i) +{ + static const char *const region_names[5] = { + "Descr.", "BIOS", "ME", "GbE", "Platf." + }; + if (i >= 5) { + msg_pdbg2("%s: region index too high.\n", __func__); + return; + } + uint32_t base = ICH_FREG_BASE(reg->FLREGs[i]); + uint32_t limit = ICH_FREG_LIMIT(reg->FLREGs[i]); + msg_pdbg2("Region %d (%-6s) ", i, region_names[i]); + if (base > limit) + msg_pdbg2("is unused.\n"); + else + msg_pdbg2("0x%08x - 0x%08x\n", base, limit | 0x0fff); +} + +void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc) +{ + uint8_t i; + uint8_t nr = desc->content.NR + 1; + msg_pdbg2("=== Region Section ===\n"); + if (nr >= 5) { + msg_pdbg2("%s: number of regions too high (%d).\n", __func__, + nr); + return; + } + for (i = 0; i <= nr; i++) + msg_pdbg2("FLREG%d 0x%08x\n", i, desc->region.FLREGs[i]); + msg_pdbg2("\n"); + + msg_pdbg2("--- Details ---\n"); + for (i = 0; i <= nr; i++) + pprint_freg(&desc->region, i); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_master(const struct ich_desc_master *mstr) +{ + msg_pdbg2("=== Master Section ===\n"); + msg_pdbg2("FLMSTR1 0x%08x\n", mstr->FLMSTR1); + msg_pdbg2("FLMSTR2 0x%08x\n", mstr->FLMSTR2); + msg_pdbg2("FLMSTR3 0x%08x\n", mstr->FLMSTR3); + msg_pdbg2("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2(" Descr. BIOS ME GbE Platf.\n"); + msg_pdbg2("BIOS %c%c %c%c %c%c %c%c %c%c\n", + (mstr->BIOS_descr_r) ?'r':' ', (mstr->BIOS_descr_w) ?'w':' ', + (mstr->BIOS_BIOS_r) ?'r':' ', (mstr->BIOS_BIOS_w) ?'w':' ', + (mstr->BIOS_ME_r) ?'r':' ', (mstr->BIOS_ME_w) ?'w':' ', + (mstr->BIOS_GbE_r) ?'r':' ', (mstr->BIOS_GbE_w) ?'w':' ', + (mstr->BIOS_plat_r) ?'r':' ', (mstr->BIOS_plat_w) ?'w':' '); + msg_pdbg2("ME %c%c %c%c %c%c %c%c %c%c\n", + (mstr->ME_descr_r) ?'r':' ', (mstr->ME_descr_w) ?'w':' ', + (mstr->ME_BIOS_r) ?'r':' ', (mstr->ME_BIOS_w) ?'w':' ', + (mstr->ME_ME_r) ?'r':' ', (mstr->ME_ME_w) ?'w':' ', + (mstr->ME_GbE_r) ?'r':' ', (mstr->ME_GbE_w) ?'w':' ', + (mstr->ME_plat_r) ?'r':' ', (mstr->ME_plat_w) ?'w':' '); + msg_pdbg2("GbE %c%c %c%c %c%c %c%c %c%c\n", + (mstr->GbE_descr_r) ?'r':' ', (mstr->GbE_descr_w) ?'w':' ', + (mstr->GbE_BIOS_r) ?'r':' ', (mstr->GbE_BIOS_w) ?'w':' ', + (mstr->GbE_ME_r) ?'r':' ', (mstr->GbE_ME_w) ?'w':' ', + (mstr->GbE_GbE_r) ?'r':' ', (mstr->GbE_GbE_w) ?'w':' ', + (mstr->GbE_plat_r) ?'r':' ', (mstr->GbE_plat_w) ?'w':' '); + msg_pdbg2("\n"); +} + +static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) +{ + uint32_t control = 0; + control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS; + control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI; + mmio_le_writel(control, spibar + ICH9_REG_FDOC); + return mmio_le_readl(spibar + ICH9_REG_FDOD); +} + +int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc) +{ + uint8_t i; + uint8_t nr; + struct ich_desc_region *r = &desc->region; + + /* Test if bit-fields are working as expected */ + for (i = 0; i < 4; i++) + desc->region.FLREGs[i] = 0x5A << (i * 8); + if (r->reg0_base != 0x005A || r->reg0_limit != 0x0000 || + r->reg1_base != 0x1A00 || r->reg1_limit != 0x0000 || + r->reg2_base != 0x0000 || r->reg2_limit != 0x005A || + r->reg3_base != 0x0000 || r->reg3_limit != 0x1A00) { + msg_pdbg("The combination of compiler and CPU architecture used" + "does not lay out bit-fields as expected, sorry.\n"); + msg_pspew("r->reg0_base = 0x%04X (0x005A)\n", r->reg0_base); + msg_pspew("r->reg0_limit = 0x%04X (0x0000)\n", r->reg0_limit); + msg_pspew("r->reg1_base = 0x%04X (0x1A00)\n", r->reg1_base); + msg_pspew("r->reg1_limit = 0x%04X (0x0000)\n", r->reg1_limit); + msg_pspew("r->reg2_base = 0x%04X (0x0000)\n", r->reg2_base); + msg_pspew("r->reg2_limit = 0x%04X (0x005A)\n", r->reg2_limit); + msg_pspew("r->reg3_base = 0x%04X (0x0000)\n", r->reg3_base); + msg_pspew("r->reg3_limit = 0x%04X (0x1A00)\n", r->reg3_limit); + return RET_ERR; + } + + msg_pdbg2("Reading flash descriptors " + "mapped by the chipset via FDOC/FDOD..."); + /* content section */ + desc->content.FLVALSIG = read_descriptor_reg(0, 0, spibar); + desc->content.FLMAP0 = read_descriptor_reg(0, 1, spibar); + desc->content.FLMAP1 = read_descriptor_reg(0, 2, spibar); + desc->content.FLMAP2 = read_descriptor_reg(0, 3, spibar); + + /* component section */ + desc->component.FLCOMP = read_descriptor_reg(1, 0, spibar); + desc->component.FLILL = read_descriptor_reg(1, 1, spibar); + desc->component.FLPB = read_descriptor_reg(1, 2, spibar); + + /* region section */ + nr = desc->content.NR + 1; + if (nr >= 5) { + msg_pdbg2("%s: number of regions too high (%d) - failed\n", + __func__, nr); + return RET_ERR; + } + for (i = 0; i <= nr; i++) + desc->region.FLREGs[i] = read_descriptor_reg(2, i, spibar); + + /* master section */ + desc->master.FLMSTR1 = read_descriptor_reg(3, 0, spibar); + desc->master.FLMSTR2 = read_descriptor_reg(3, 1, spibar); + desc->master.FLMSTR3 = read_descriptor_reg(3, 2, spibar); + + /* Accessing the strap section via FDOC/D is only possible on ICH8 and + * reading the upper map is impossible on all chipsets, so don't bother. + */ + + msg_pdbg2(" done.\n"); + return RET_OK; +} +#endif /* BITFIELDS == 1 */ +#endif /* defined(__i386__) || defined(__x86_64__) */ diff --git a/ich_descriptors.h b/ich_descriptors.h new file mode 100644 index 0000000..b1da914 --- /dev/null +++ b/ich_descriptors.h @@ -0,0 +1,261 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (c) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if defined(__i386__) || defined(__x86_64__) +#ifndef __ICH_DESCRIPTORS_H__ +#define __ICH_DESCRIPTORS_H__ 1 + +#include <stdint.h> + +#define RET_OK 0 +#define RET_ERR -1 +#define RET_WARN -2 +#define RET_PARAM -3 +#define RET_OOB -4 + +#define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */ + /* 0-1: reserved */ +#define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */ +#define FDOC_FDSI (0x3f << FDOC_FDSI_OFF) +#define FDOC_FDSS_OFF 12 /* 12-14: Flash Descriptor Section Select */ +#define FDOC_FDSS (0x3 << FDOC_FDSS_OFF) + /* 15-31: reserved */ + +#define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */ + +/* Field locations and semantics for LVSCC, UVSCC and related words in the flash + * descriptor are equal therefore they all share the same macros below. */ +#define VSCC_BES_OFF 0 /* 0-1: Block/Sector Erase Size */ +#define VSCC_BES (0x3 << VSCC_BES_OFF) +#define VSCC_WG_OFF 2 /* 2: Write Granularity */ +#define VSCC_WG (0x1 << VSCC_WG_OFF) +#define VSCC_WSR_OFF 3 /* 3: Write Status Required */ +#define VSCC_WSR (0x1 << VSCC_WSR_OFF) +#define VSCC_WEWS_OFF 4 /* 4: Write Enable on Write Status */ +#define VSCC_WEWS (0x1 << VSCC_WEWS_OFF) + /* 5-7: reserved */ +#define VSCC_EO_OFF 8 /* 8-15: Erase Opcode */ +#define VSCC_EO (0xff << VSCC_EO_OFF) + /* 16-22: reserved */ +#define VSCC_VCL_OFF 23 /* 23: Vendor Component Lock */ +#define VSCC_VCL (0x1 << VSCC_VCL_OFF) + /* 24-31: reserved */ + +#define ICH_FREG_BASE(flreg) (((flreg) << 12) & 0x01fff000) +#define ICH_FREG_LIMIT(flreg) (((flreg) >> 4) & 0x01fff000) + +/* Used to select the right descriptor printing function. + * Currently only ICH8 and Ibex Peak are supported. + */ +enum ich_chipset { + CHIPSET_ICH_UNKNOWN, + CHIPSET_ICH7 = 7, + CHIPSET_ICH8, + CHIPSET_ICH9, + CHIPSET_ICH10, + CHIPSET_5_SERIES_IBEX_PEAK, + CHIPSET_6_SERIES_COUGAR_POINT, + CHIPSET_7_SERIES_PANTHER_POINT +}; + +void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity); + +#if BITFIELDS == 1 +struct ich_desc_content { + uint32_t FLVALSIG; /* 0x00 */ + union { /* 0x04 */ + uint32_t FLMAP0; + struct { + uint32_t FCBA :8, /* Flash Component Base Address */ + NC :2, /* Number Of Components */ + :6, + FRBA :8, /* Flash Region Base Address */ + NR :3, /* Number Of Regions */ + :5; + }; + }; + union { /* 0x08 */ + uint32_t FLMAP1; + struct { + uint32_t FMBA :8, /* Flash Master Base Address */ + NM :3, /* Number Of Masters */ + :5, + FISBA :8, /* Flash ICH Strap Base Address */ + ISL :8; /* ICH Strap Length */ + }; + }; + union { /* 0x0c */ + uint32_t FLMAP2; + struct { + uint32_t FMSBA :8, /* Flash (G)MCH Strap Base Addr. */ + MSL :8, /* MCH Strap Length */ + :16; + }; + }; +}; + +struct ich_desc_component { + union { /* 0x00 */ + uint32_t FLCOMP; /* Flash Components Register */ + struct { + uint32_t comp1_density :3, + comp2_density :3, + :11, + freq_read :3, + fastread :1, + freq_fastread :3, + freq_write :3, + freq_read_id :3, + :2; + }; + }; + union { /* 0x04 */ + uint32_t FLILL; /* Flash Invalid Instructions Register */ + struct { + uint32_t invalid_instr0 :8, + invalid_instr1 :8, + invalid_instr2 :8, + invalid_instr3 :8; + }; + }; + union { /* 0x08 */ + uint32_t FLPB; /* Flash Partition Boundary Register */ + struct { + uint32_t FPBA :13, /* Flash Partition Boundary Addr */ + :19; + }; + }; +}; + +struct ich_desc_region { + union { + uint32_t FLREGs[5]; + struct { + struct { /* FLREG0 Flash Descriptor */ + uint32_t reg0_base :13, + :3, + reg0_limit :13, + :3; + }; + struct { /* FLREG1 BIOS */ + uint32_t reg1_base :13, + :3, + reg1_limit :13, + :3; + }; + struct { /* FLREG2 ME */ + uint32_t reg2_base :13, + :3, + reg2_limit :13, + :3; + }; + struct { /* FLREG3 GbE */ + uint32_t reg3_base :13, + :3, + reg3_limit :13, + :3; + }; + struct { /* FLREG4 Platform */ + uint32_t reg4_base :13, + :3, + reg4_limit :13, + :3; + }; + }; + }; +}; + +struct ich_desc_master { + union { + uint32_t FLMSTR1; + struct { + uint32_t BIOS_req_ID :16, + BIOS_descr_r :1, + BIOS_BIOS_r :1, + BIOS_ME_r :1, + BIOS_GbE_r :1, + BIOS_plat_r :1, + :3, + BIOS_descr_w :1, + BIOS_BIOS_w :1, + BIOS_ME_w :1, + BIOS_GbE_w :1, + BIOS_plat_w :1, + :3; + }; + }; + union { + uint32_t FLMSTR2; + struct { + uint32_t ME_req_ID :16, + ME_descr_r :1, + ME_BIOS_r :1, + ME_ME_r :1, + ME_GbE_r :1, + ME_plat_r :1, + :3, + ME_descr_w :1, + ME_BIOS_w :1, + ME_ME_w :1, + ME_GbE_w :1, + ME_plat_w :1, + :3; + }; + }; + union { + uint32_t FLMSTR3; + struct { + uint32_t GbE_req_ID :16, + GbE_descr_r :1, + GbE_BIOS_r :1, + GbE_ME_r :1, + GbE_GbE_r :1, + GbE_plat_r :1, + :3, + GbE_descr_w :1, + GbE_BIOS_w :1, + GbE_ME_w :1, + GbE_GbE_w :1, + GbE_plat_w :1, + :3; + }; + }; +}; + +struct ich_descriptors { + struct ich_desc_content content; + struct ich_desc_component component; + struct ich_desc_region region; + struct ich_desc_master master; +}; + +void prettyprint_ich_descriptors(enum ich_chipset, const struct ich_descriptors *desc); + +void prettyprint_ich_descriptor_content(const struct ich_desc_content *content); +void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc); +void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc); +void prettyprint_ich_descriptor_master(const struct ich_desc_master *master); + +int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc); + +#endif /* BITFIELDS == 1 */ +#endif /* __ICH_DESCRIPTORS_H__ */ +#endif /* defined(__i386__) || defined(__x86_64__) */ diff --git a/ichspi.c b/ichspi.c index 8b4210e..09af2b3 100644 --- a/ichspi.c +++ b/ichspi.c @@ -29,6 +29,7 @@ #include "flash.h" #include "programmer.h" #include "spi.h" +#include "ich_descriptors.h" /* ICH9 controller register definition */ #define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ @@ -119,6 +120,16 @@ #define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */ #define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */ +#define ICH8_REG_VSCC 0xC1 /* 32 Bits Vendor Specific Component Capabilities */ +#define ICH9_REG_LVSCC 0xC4 /* 32 Bits Host Lower Vendor Specific Component Capabilities */ +#define ICH9_REG_UVSCC 0xC8 /* 32 Bits Host Upper Vendor Specific Component Capabilities */ +/* The individual fields of the VSCC registers are defined in the file + * ich_descriptors.h. The reason is that the same layout is also used in the + * flash descriptor to define the properties of the different flash chips + * supported. The BIOS (or the ME?) is responsible to populate the ICH registers + * with the information from the descriptor on startup depending on the actual + * chip(s) detected. */ + #define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */ #define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */ #define FPB_FPBA (0x1FFF << FPB_FPBA_OFF) @@ -1129,9 +1140,6 @@ static int ich_spi_send_multicommand(struct spi_command *cmds) #define ICH_BRWA(x) ((x >> 8) & 0xff) #define ICH_BRRA(x) ((x >> 0) & 0xff) -#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff) -#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff) - static void do_ich9_spi_frap(uint32_t frap, int i) { static const char *const access_names[4] = { @@ -1158,9 +1166,8 @@ static void do_ich9_spi_frap(uint32_t frap, int i) return; } - msg_pdbg("0x%08x-0x%08x is %s\n", - (base << 12), (limit << 12) | 0x0fff, - access_names[rwperms]); + msg_pdbg("0x%08x-0x%08x is %s\n", base, (limit | 0x0fff), + access_names[rwperms]); } static const struct spi_programmer spi_programmer_ich7 = { @@ -1190,6 +1197,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, uint8_t old, new; uint16_t spibar_offset, tmp2; uint32_t tmp; + int ichspi_desc = 0; switch (ich_generation) { case 7: @@ -1261,6 +1269,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } + if (tmp2 & HSFS_FDV) + ichspi_desc = 1; tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); @@ -1308,12 +1318,40 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, mmio_readl(ich_spibar + ICH9_REG_OPMENU)); msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + ICH9_REG_OPMENU + 4)); - ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); - msg_pdbg("0xA0: 0x%08x (BBAR)\n", - ichspi_bbar); - tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); - msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + if (ich_generation == 8) { + tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC); + msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp); + msg_pdbg("VSCC: "); + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); + } else { + ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); + msg_pdbg("0xA0: 0x%08x (BBAR)\n", + ichspi_bbar); + + tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); + msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); + msg_pdbg("LVSCC: "); + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); + + tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); + msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); + msg_pdbg("UVSCC: "); + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); + + tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); + msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + } + msg_pdbg("\n"); +#if BITFIELDS == 1 + if (ichspi_desc) { + struct ich_descriptors desc = {{ 0 }}; + if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == + RET_OK) + prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, + &desc); + } +#endif /* BITFIELDS == 1 */ ich_init_opcodes(); break; default: -- 1.7.1

1 0

[PATCH 0/8] ichspi 8.1
by Stefan Tauner 20 Aug '11

20 Aug '11

i made a few mistakes while reordering the patches (so that the unrelated and kinda unimportant ich_descriptor_tool is the last to apply (and review)). also, i have added two patches regarding PR registers. Stefan Tauner (8): ichspi: add ICH/PCH flash descriptor decoding via FDOC/FDOD ichspi: disable writes when locked or read-only regions are detected ichspi: don't touch the nonexistent(?) BBAR register on ICH8 ichspi: improve prettyprint_opcodes ichspi: add support for Intel Hardware Sequencing ichspi: add prettyprinting for PR registers ichspi: unlock PR register restrictions if not locked down Add ich_descriptor_tool to decode all flash descriptors stored in a flash dump file Makefile | 25 +- chipdrivers.h | 6 + flashchips.c | 23 +- flashchips.h | 2 + ich_descriptors.c | 722 ++++++++++++++++++++++ ich_descriptors.h | 466 ++++++++++++++ ichspi.c | 548 +++++++++++++++-- programmer.h | 1 + util/ich_descriptors_tool/Makefile | 63 ++ util/ich_descriptors_tool/TODO | 6 + util/ich_descriptors_tool/ich_descriptors_tool.c | 225 +++++++ 11 files changed, 2027 insertions(+), 60 deletions(-) create mode 100644 ich_descriptors.c create mode 100644 ich_descriptors.h create mode 100644 util/ich_descriptors_tool/Makefile create mode 100644 util/ich_descriptors_tool/TODO create mode 100644 util/ich_descriptors_tool/ich_descriptors_tool.c

1 0

needs board enable: jetway 865gdmp rev 1.0
by Stefan Tauner 20 Aug '11

20 Aug '11

http://paste.flashrom.org/view.php?id=770 superio http://paste.flashrom.org/view.php?id=769 lspci http://paste.flashrom.org/view.php?id=768 flash http://paste.flashrom.org/view.php?id=767 bin board owned by Андрей толстов aka andrei. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

Re: [flashrom] [PATCH 3/7] layout: Add -i <image>[:<file>] support
by David Hendricks 19 Aug '11

19 Aug '11

one minor nit On Fri, Aug 19, 2011 at 8:00 AM, Stefan Tauner < stefan.tauner(a)student.tuwien.ac.at> wrote: > +static int read_content_from_file(romlayout_t *entry, uint8_t > *newcontents) > +{ > + char *file; > + FILE *fp; > + int len; > + > + file = entry->file; > + len = entry->end - entry->start + 1; > + if (file[0] != '\0') { > + int numbytes; > + if ((fp = fopen(file, "rb")) == NULL) { > + perror(file); > Hmmmm, I'm not sure why we used perror()... Perhaps it would be better to use msg_gerr(strerror(errno))? > + return 1; > + } > + numbytes = fread(newcontents + entry->start, 1, len, fp); > + fclose(fp); > + if (numbytes != len) { > + perror(file); > same as above. -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

1 0

Re: [flashrom] [PATCH 2/7] Add deferred -i processing
by David Hendricks 19 Aug '11

19 Aug '11

Oops, disregard that last message. I was looking at find_romentry() and indeed it makes sense to return a negative value to indicate error since it returns an index otherwise. Acked-by: David Hendricks <dhendrix(a)google.com> On Fri, Aug 19, 2011 at 2:53 PM, David Hendricks <dhendrix(a)google.com>wrote: > Did you want to fix the inconsistent use of -1 instead of 1 as the return > code for some functions? > > Other than that it looks good (i'm biased, of course :-)) > > -- > David Hendricks (dhendrix) > Systems Software Engineer, Google Inc. > -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

1 0

Re: [flashrom] [PATCH 2/7] Add deferred -i processing
by David Hendricks 19 Aug '11

19 Aug '11

Did you want to fix the inconsistent use of -1 instead of 1 as the return code for some functions? Other than that it looks good (i'm biased, of course :-)) -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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[PATCH 7/7] (not for merge) Fix the "Use layout for verify operations too" patch in a hacky way
by Stefan Tauner 19 Aug '11

19 Aug '11

if you look at the second half of doit with this patch applied, it is quite clear, that most of it should be guarded by a huge if(write_it) clause. maybe move this into a function? Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flashrom.c | 7 ++++--- 1 files changed, 4 insertions(+), 3 deletions(-) diff --git a/flashrom.c b/flashrom.c index 7a1a7ec..85135c2 100644 --- a/flashrom.c +++ b/flashrom.c @@ -1992,7 +1992,7 @@ int doit(struct flashchip *flash, int force, const char *filename, int read_it, goto out; } - if (write_it || verify_it) { + if (write_it || verify_it) { /* always true: erase and read already goto'ed */ if (read_buf_from_file(newcontents, size, filename)) { ret = 1; goto out; @@ -2010,7 +2010,7 @@ int doit(struct flashchip *flash, int force, const char *filename, int read_it, * preserved, but in that case we might perform unneeded erase which * takes time as well. */ - if (read_all_first) { + if (read_all_first && write_it) { msg_cinfo("Reading old flash chip contents... "); if (flash->read(flash, oldcontents, 0, size)) { ret = 1; @@ -2021,7 +2021,8 @@ int doit(struct flashchip *flash, int force, const char *filename, int read_it, msg_cinfo("done.\n"); /* Build a new image from the given layout. */ - build_new_image(flash, read_all_first, oldcontents, newcontents); + if (write_it) + build_new_image(flash, read_all_first, oldcontents, newcontents); if (write_it && erase_and_write_flash(flash, oldcontents, newcontents)) { msg_cerr("Uh oh. Erase/write failed."); -- 1.7.1

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[PATCH 6/7] Use layout for verify operations too
by Stefan Tauner 19 Aug '11

19 Aug '11

--- this still reads the whole image in at start... Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flashrom.c | 29 +++++++++++++++++++++-------- 1 files changed, 21 insertions(+), 8 deletions(-) diff --git a/flashrom.c b/flashrom.c index 6e946ba..7a1a7ec 100644 --- a/flashrom.c +++ b/flashrom.c @@ -1220,16 +1220,29 @@ notfound: int verify_flash(struct flashchip *flash, uint8_t *buf) { - int ret; int total_size = flash->total_size * 1024; + int ret = 0; + romlayout_t *l; - msg_cinfo("Verifying flash... "); - - ret = verify_range(flash, buf, 0, total_size, NULL); + msg_cinfo("Verifying... "); - if (!ret) - msg_cinfo("VERIFIED. \n"); + l = get_next_included_romentry(0); + /* No included rom entries. Assume complete verify wanted. */ + if (l == NULL) + ret = verify_range(flash, buf, 0, total_size, NULL); + else do { + unsigned int len = l->end - l->start + 1; + msg_gdbg2("Verifying \"%s\" 0x%08x - 0x%08x (%uB)... ", l->name, + l->start, l->end, len); + if(verify_range(flash, buf + l->start, l->start, len, NULL)) { + return 1; + } + msg_gdbg2("done. "); + l = get_next_included_romentry(l->end + 1); + } while (l != NULL); + if (ret == 0) + msg_cinfo("VERIFIED.\n"); return ret; } -- 1.7.1

1 0

[PATCH 5/7] Use layout for read operations too
by Stefan Tauner 19 Aug '11

19 Aug '11

Previously using layout files was useful for write operations only, for reads it was ignored. This patch added layout handling for reads. Based on the "Add -i <image>[:<file>] support" patch this one will output the selected regions to files. If the optional argument is given it is used as a file name, else the image name will be used. --- TODO: man page side note: the execution path of forced reads is wrong or at least worth a look. it does not use doit() but calls read_flash_to_file() directly. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- flash.h | 8 ++++++ flashrom.c | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++++-------- layout.c | 8 ------ 3 files changed, 73 insertions(+), 18 deletions(-) diff --git a/flash.h b/flash.h index eb5f144..50e10b9 100644 --- a/flash.h +++ b/flash.h @@ -39,6 +39,13 @@ #define TIMEOUT_ERROR -101 typedef unsigned long chipaddr; +typedef struct { + unsigned int start; + unsigned int end; + unsigned int included; + char name[256]; + char file[256]; /* file == "" means not specified. */ +} romlayout_t; int register_shutdown(int (*function) (void *data), void *data); void *programmer_map_flash_region(const char *descr, unsigned long phys_addr, @@ -258,6 +265,7 @@ int cli_classic(int argc, char *argv[]); int register_include_arg(char *name); int process_include_args(void); int read_romlayout(char *name); +romlayout_t *get_next_included_romentry(unsigned int start); int build_new_image(struct flashchip *flash, int oldcontents_valid, uint8_t *oldcontents, uint8_t *newcontents); /* spi.c */ diff --git a/flashrom.c b/flashrom.c index 564d815..6e946ba 100644 --- a/flashrom.c +++ b/flashrom.c @@ -1267,7 +1267,7 @@ int read_buf_from_file(unsigned char *buf, unsigned long size, return 0; } -int write_buf_to_file(unsigned char *buf, unsigned long size, +int write_dump_to_file(unsigned char *buf, unsigned long size, const char *filename) { unsigned long numbytes; @@ -1292,26 +1292,81 @@ int write_buf_to_file(unsigned char *buf, unsigned long size, return 0; } +int write_buf_to_file(unsigned char *buf, unsigned long size, + const char *filename) +{ + romlayout_t *l; + int ret = 0; + + ret = write_dump_to_file(buf, size, filename); + if (ret) + return ret; + + l = get_next_included_romentry(0); + + while (l != NULL) { + const char* name = (l->file[0] == '\0') ? l->name : l->file; + unsigned int len = l->end - l->start + 1; + msg_gdbg2("Writing \"%s\" to \"%s\" 0x%08x - 0x%08x (%uB)... ", + l->name, l->file, l->start, l->end, len); + if(write_dump_to_file(buf + l->start, len, name)) { + msg_gdbg2("failed. "); + return 1; + } + msg_gdbg2("done. "); + l = get_next_included_romentry(l->end + 1); + }; + + return 0; +} + +int read_flash_to_buf(struct flashchip *flash, uint8_t *buf) +{ + romlayout_t *l; + + if (!flash->read) { + msg_cerr("No read function available for this flash chip.\n"); + return 1; + } + + l = get_next_included_romentry(0); + /* No included rom entries. Assume complete readout wanted. */ + if (l == NULL) + return flash->read(flash, buf, 0, flash->total_size * 1024); + + do { + unsigned int len = l->end - l->start + 1; + msg_gdbg2("Reading \"%s\" 0x%08x - 0x%08x (%uB)... ", l->name, + l->start, l->end, len); + if(flash->read(flash, buf + l->start, l->start, len)) { + msg_gdbg2("failed. "); + return 1; + } + msg_gdbg2("done. "); + l = get_next_included_romentry(l->end + 1); + } while (l != NULL); + + return 0; +} + int read_flash_to_file(struct flashchip *flash, const char *filename) { unsigned long size = flash->total_size * 1024; - unsigned char *buf = calloc(size, sizeof(char)); int ret = 0; + uint8_t *buf; msg_cinfo("Reading flash... "); - if (!buf) { + + buf = calloc(size, sizeof(uint8_t)); + if (buf == NULL) { msg_gerr("Memory allocation failed!\n"); - msg_cinfo("FAILED.\n"); - return 1; - } - if (!flash->read) { - msg_cerr("No read function available for this flash chip.\n"); ret = 1; goto out_free; } - if (flash->read(flash, buf, 0, size)) { + + ret = read_flash_to_buf(flash, buf); + if (ret != 0) { msg_cerr("Read operation failed!\n"); - ret = 1; goto out_free; } diff --git a/layout.c b/layout.c index 2e386d6..ac1fa0d 100644 --- a/layout.c +++ b/layout.c @@ -34,14 +34,6 @@ static int romimages = 0; #define MAX_ROMLAYOUT 32 -typedef struct { - unsigned int start; - unsigned int end; - unsigned int included; - char name[256]; - char file[256]; /* file == "" means not specified. */ -} romlayout_t; - /* include_args lists arguments specified at the command line with -i. They * must be processed at some point so that desired regions are marked as * "included" in the rom_entries list. -- 1.7.1

1 0

[PATCH 4/7] Make read before write configurable (infrastructure part)
by Stefan Tauner 19 Aug '11

19 Aug '11

- Introduce a variable in doit() that allows to influence read-before-write and its consequences. - Rename handle_romentries to build_new_image and a description of its purpose. - Modify build_new_image so that it still works even if the old content is not read before. - Add copy_old_content() to ease the pain for future patches. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> --- TODO: add UI This is completely wrong. When the user wants to skip most of the chip AND wants to avoid the safety net, it makes no sense at all to read most of the chip in build_new_image. This is needed because the write/skip logic works by comparing the old content with the new content. In the case that old content is already known (because we have read the whole chip before), this is no problem and even nice from a architectural point of view. Allowing to skip the reading breaks the concept though. This patch provides the ugly code that is necessary so that this concept does not explode. It does not fix the concept itself. In the case the user wants to write the whole chip, this provides a real benefit. The smaller the region is that he wants to update, the smaller the benefit becomes. The real solution would be to provide the erase and write logic not just a complete image, from which it can deduce what it can and should skip, but also a layout-like map of what the user wants to be changed (or something similar that allows the following). If the old contents are known, then fine, but if not, read only the parts needed due to erase block overheads and not everything unnecessarily. --- flash.h | 2 +- flashrom.c | 42 ++++++++++++++++++++++-------------------- layout.c | 30 +++++++++++++++++++++++++----- 3 files changed, 48 insertions(+), 26 deletions(-) diff --git a/flash.h b/flash.h index f2988bc..eb5f144 100644 --- a/flash.h +++ b/flash.h @@ -258,7 +258,7 @@ int cli_classic(int argc, char *argv[]); int register_include_arg(char *name); int process_include_args(void); int read_romlayout(char *name); -int handle_romentries(struct flashchip *flash, uint8_t *oldcontents, uint8_t *newcontents); +int build_new_image(struct flashchip *flash, int oldcontents_valid, uint8_t *oldcontents, uint8_t *newcontents); /* spi.c */ struct spi_command { diff --git a/flashrom.c b/flashrom.c index ad1e042..564d815 100644 --- a/flashrom.c +++ b/flashrom.c @@ -1871,6 +1871,7 @@ int doit(struct flashchip *flash, int force, const char *filename, int read_it, uint8_t *newcontents; int ret = 0; unsigned long size = flash->total_size * 1024; + int read_all_first = 1; /* FIXME: Make this configurable. */ if (chip_safety_check(flash, force, read_it, write_it, erase_it, verify_it)) { msg_cerr("Aborting.\n"); @@ -1937,28 +1938,27 @@ int doit(struct flashchip *flash, int force, const char *filename, int read_it, /* Read the whole chip to be able to check whether regions need to be * erased and to give better diagnostics in case write fails. - * The alternative would be to read only the regions which are to be + * The alternative is to read only the regions which are to be * preserved, but in that case we might perform unneeded erase which * takes time as well. */ - msg_cinfo("Reading old flash chip contents... "); - if (flash->read(flash, oldcontents, 0, size)) { - ret = 1; - msg_cinfo("FAILED.\n"); - goto out; + if (read_all_first) { + msg_cinfo("Reading old flash chip contents... "); + if (flash->read(flash, oldcontents, 0, size)) { + ret = 1; + msg_cinfo("FAILED.\n"); + goto out; + } } msg_cinfo("done.\n"); - // This should be moved into each flash part's code to do it - // cleanly. This does the job. - handle_romentries(flash, oldcontents, newcontents); + /* Build a new image from the given layout. */ + build_new_image(flash, read_all_first, oldcontents, newcontents); - // //////////////////////////////////////////////////////////// - - if (write_it) { - if (erase_and_write_flash(flash, oldcontents, newcontents)) { - msg_cerr("Uh oh. Erase/write failed. Checking if " - "anything changed.\n"); + if (write_it && erase_and_write_flash(flash, oldcontents, newcontents)) { + msg_cerr("Uh oh. Erase/write failed."); + if (read_all_first) { + msg_cerr("Checking if anything changed... "); if (!flash->read(flash, newcontents, 0, size)) { if (!memcmp(oldcontents, newcontents, size)) { msg_cinfo("Good. It seems nothing was " @@ -1967,11 +1967,13 @@ int doit(struct flashchip *flash, int force, const char *filename, int read_it, ret = 1; goto out; } - } - emergency_help_message(); - ret = 1; - goto out; - } + } else + msg_cerr("failed.\n"); + } else + msg_cerr("\n"); + emergency_help_message(); + ret = 1; + goto out; } if (verify_it) { diff --git a/layout.c b/layout.c index f5764c5..2e386d6 100644 --- a/layout.c +++ b/layout.c @@ -338,7 +338,26 @@ static int read_content_from_file(romlayout_t *entry, uint8_t *newcontents) return 0; } -int handle_romentries(struct flashchip *flash, uint8_t *oldcontents, uint8_t *newcontents) +static void copy_old_content(struct flashchip *flash, int oldcontents_valid, uint8_t *oldcontents, uint8_t *newcontents, unsigned int start, unsigned int size) +{ + if (!oldcontents_valid) { + /* oldcontents is a zero-filled buffer. By reading into + * oldcontents, we avoid a rewrite of identical regions even if + * an initial full chip read didn't happen. */ + msg_gdbg2("Read a chunk starting from 0x%06x (len=0x%06x).\n", + start, size); + flash->read(flash, oldcontents + start, start, size); + } + memcpy(newcontents + start, oldcontents + start, size); +} + +/** + * Modify @newcontents so that it contains the data that should be on the chip + * eventually. In the case the user wants to update only parts of it, copy + * the chunks to be preserved from @oldcontents to @newcontents. If @oldcontents + * is not valid, we need to fetch the current data from the chip first. + */ +int build_new_image(struct flashchip *flash, int oldcontents_valid, uint8_t *oldcontents, uint8_t *newcontents) { unsigned int start = 0; romlayout_t *entry; @@ -357,14 +376,15 @@ int handle_romentries(struct flashchip *flash, uint8_t *oldcontents, uint8_t *ne entry = get_next_included_romentry(start); /* No more romentries for remaining region? */ if (entry == NULL) { - memcpy(newcontents + start, oldcontents + start, - size - start); + copy_old_content(flash, oldcontents_valid, oldcontents, + newcontents, start, size - start); break; } /* For non-included region, copy from old content. */ if (entry->start > start) - memcpy(newcontents + start, oldcontents + start, - entry->start - start); + copy_old_content(flash, oldcontents_valid, oldcontents, + newcontents, start, + entry->start - start); /* For included region, copy from file if specified. */ if (read_content_from_file(entry, newcontents) < 0) return 1; -- 1.7.1

1 0

[PATCH 3/7] layout: Add -i <image>[:<file>] support
by Stefan Tauner 19 Aug '11

19 Aug '11

Add an optional sub-parameter to the -i parameter to allow building the image to be written from multiple files. This will also allow regions to be read from flash and written to separate image files in a later patch. --- TODO: man page Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- layout.c | 45 ++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 44 insertions(+), 1 deletions(-) diff --git a/layout.c b/layout.c index 3e9fa0e..f5764c5 100644 --- a/layout.c +++ b/layout.c @@ -39,6 +39,7 @@ typedef struct { unsigned int end; unsigned int included; char name[256]; + char file[256]; /* file == "" means not specified. */ } romlayout_t; /* include_args lists arguments specified at the command line with -i. They @@ -183,6 +184,7 @@ int read_romlayout(char *name) rom_entries[romimages].start = strtol(tstr1, (char **)NULL, 16); rom_entries[romimages].end = strtol(tstr2, (char **)NULL, 16); rom_entries[romimages].included = 0; + strcpy(rom_entries[romimages].file, ""); romimages++; } @@ -220,14 +222,24 @@ int register_include_arg(char *name) static int find_romentry(char *name) { int i; + char *file = NULL; if (!romimages) return -1; - msg_gspew("Looking for region \"%s\"... ", name); + /* -i <image>[:<file>] */ + if (strtok(name, ":")) { + file = strtok(NULL, ""); + } + msg_gspew("Looking for region \"%s\" (file=\"%s\")... ", + name, file ? file : "<not specified>"); + for (i = 0; i < romimages; i++) { if (!strcmp(rom_entries[i].name, name)) { rom_entries[i].included = 1; + snprintf(rom_entries[i].file, + sizeof(rom_entries[i].file), + "%s", file ? file : ""); msg_gspew("found.\n"); return i; } @@ -299,6 +311,33 @@ romlayout_t *get_next_included_romentry(unsigned int start) return best_entry; } +/* If a file name is specified for this region, read the file contents and + * overwrite @newcontents in the range specified by @entry. + */ +static int read_content_from_file(romlayout_t *entry, uint8_t *newcontents) +{ + char *file; + FILE *fp; + int len; + + file = entry->file; + len = entry->end - entry->start + 1; + if (file[0] != '\0') { + int numbytes; + if ((fp = fopen(file, "rb")) == NULL) { + perror(file); + return 1; + } + numbytes = fread(newcontents + entry->start, 1, len, fp); + fclose(fp); + if (numbytes != len) { + perror(file); + return 1; + } + } + return 0; +} + int handle_romentries(struct flashchip *flash, uint8_t *oldcontents, uint8_t *newcontents) { unsigned int start = 0; @@ -326,6 +365,10 @@ int handle_romentries(struct flashchip *flash, uint8_t *oldcontents, uint8_t *ne if (entry->start > start) memcpy(newcontents + start, oldcontents + start, entry->start - start); + /* For included region, copy from file if specified. */ + if (read_content_from_file(entry, newcontents) < 0) + return 1; + /* Skip to location after current romentry. */ start = entry->end + 1; /* Catch overflow. */ -- 1.7.1

1 0

[PATCH 2/7] Add deferred -i processing
by Stefan Tauner 19 Aug '11

19 Aug '11

The general idea and most of the code is stolen from chromiumos: 8fc0740356ca15d02fb1c65ab43b10844f148c3b bb9049c66ca55e0dc621dd2c70b5d2cb6e5179bf Signed-off-by: Louis Yung-Chieh Lo <yjlou(a)chromium.org> and the main part: d0ea9ed71e7f86bb8e8db2ca7c32a96de25343d8 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> My implementation does not defer the processing until doit(), but after the argument parsing loop only (doit() should not contain argument checks). This allows to specify -i and -l parameters in any order. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- cli_classic.c | 10 +++---- flash.h | 3 +- layout.c | 85 ++++++++++++++++++++++++++++++++++++++++++++++++--------- 3 files changed, 78 insertions(+), 20 deletions(-) diff --git a/cli_classic.c b/cli_classic.c index 5d35738..1980de4 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -226,14 +226,9 @@ int cli_classic(int argc, char *argv[]) cli_classic_abort_usage(); break; case 'i': - /* FIXME: -l has to be specified before -i. */ tempstr = strdup(optarg); - if (find_romentry(tempstr) < 0) { - fprintf(stderr, "Error: image %s not found in " - "layout file or -i specified before " - "-l\n", tempstr); + if (register_include_arg(tempstr)) cli_classic_abort_usage(); - } break; case 'L': if (++operation_specified > 1) { @@ -318,6 +313,9 @@ int cli_classic(int argc, char *argv[]) cli_classic_abort_usage(); } + if (process_include_args()) + cli_classic_abort_usage(); + /* FIXME: Print the actions flashrom will take. */ if (list_supported) { diff --git a/flash.h b/flash.h index 4b1cca2..f2988bc 100644 --- a/flash.h +++ b/flash.h @@ -255,8 +255,9 @@ int print(int type, const char *fmt, ...) __attribute__((format(printf, 2, 3))); int cli_classic(int argc, char *argv[]); /* layout.c */ +int register_include_arg(char *name); +int process_include_args(void); int read_romlayout(char *name); -int find_romentry(char *name); int handle_romentries(struct flashchip *flash, uint8_t *oldcontents, uint8_t *newcontents); /* spi.c */ diff --git a/layout.c b/layout.c index 247c897..3e9fa0e 100644 --- a/layout.c +++ b/layout.c @@ -41,6 +41,12 @@ typedef struct { char name[256]; } romlayout_t; +/* include_args lists arguments specified at the command line with -i. They + * must be processed at some point so that desired regions are marked as + * "included" in the rom_entries list. + */ +static char *include_args[MAX_ROMLAYOUT]; +static int num_include_args = 0; /* the number of valid entries. */ static romlayout_t rom_entries[MAX_ROMLAYOUT]; #if CONFIG_INTERNAL == 1 /* FIXME: Move the whole block to cbtable.c? */ @@ -156,10 +162,8 @@ int read_romlayout(char *name) if (romimages >= MAX_ROMLAYOUT) { msg_gerr("Maximum number of ROM images (%i) in layout " - "file reached before end of layout file.\n", - MAX_ROMLAYOUT); - msg_gerr("Ignoring the rest of the layout file.\n"); - break; + "file reached.\n", MAX_ROMLAYOUT); + return 1; } if (2 != fscanf(romlayout, "%s %s\n", tempstr, rom_entries[romimages].name)) continue; @@ -194,27 +198,80 @@ int read_romlayout(char *name) } #endif -int find_romentry(char *name) +/* register an include argument (-i) for later processing */ +int register_include_arg(char *name) +{ + if (num_include_args >= MAX_ROMLAYOUT) { + msg_gerr("Too many regions included (%i).\n", num_include_args); + return 1; + } + + if (name == NULL) { + msg_gerr("<NULL> is a bad region name.\n"); + return 1; + } + + include_args[num_include_args] = name; + num_include_args++; + return 0; +} + +/* returns the index of the entry (or a negative value if it is not found) */ +static int find_romentry(char *name) { int i; if (!romimages) return -1; - msg_ginfo("Looking for \"%s\"... ", name); - + msg_gspew("Looking for region \"%s\"... ", name); for (i = 0; i < romimages; i++) { if (!strcmp(rom_entries[i].name, name)) { rom_entries[i].included = 1; - msg_ginfo("found.\n"); + msg_gspew("found.\n"); return i; } } - msg_ginfo("not found.\n"); // Not found. Error. - + msg_gspew("not found.\n"); return -1; } +/* process -i arguments + * returns 0 to indicate success, >0 to indicate failure + */ +int process_include_args(void) +{ + int i; + unsigned int found = 0; + + if (num_include_args == 0) + return 0; + + for (i = 0; i < num_include_args; i++) { + /* User has specified an area, but no layout file is loaded. */ + if (!romimages) { + msg_gerr("Region requested (with -i \"%s\"), " + "but no layout data is available.\n", + include_args[i]); + return 1; + } + + if (find_romentry(include_args[i]) < 0) { + msg_gerr("Invalid region specified: \"%s\"\n", + include_args[i]); + return 1; + } + found++; + } + + msg_ginfo("Using region%s: \"%s\"", num_include_args > 1 ? "s" : "", + include_args[0]); + for (i = 1; i < num_include_args; i++) + msg_ginfo(", \"%s\"", include_args[i]); + msg_ginfo(".\n"); + return 0; +} + romlayout_t *get_next_included_romentry(unsigned int start) { int i; @@ -248,11 +305,12 @@ int handle_romentries(struct flashchip *flash, uint8_t *oldcontents, uint8_t *ne romlayout_t *entry; unsigned int size = flash->total_size * 1024; - /* If no layout file was specified or the layout file was empty, assume - * that the user wants to flash the complete new image. + /* If no regions were specified for inclusion, assume + * that the user wants to write the complete new image. */ - if (!romimages) + if (num_include_args == 0) return 0; + /* Non-included romentries are ignored. * The union of all included romentries is used from the new image. */ @@ -264,6 +322,7 @@ int handle_romentries(struct flashchip *flash, uint8_t *oldcontents, uint8_t *ne size - start); break; } + /* For non-included region, copy from old content. */ if (entry->start > start) memcpy(newcontents + start, oldcontents + start, entry->start - start); -- 1.7.1

1 0

[PATCH 1/7] layout: change return type and name of find_next_included_romentry
by Stefan Tauner 19 Aug '11

19 Aug '11

- rename from find_next_included_romentry to get_next_included_romentry - return a pointer to a rom_entry instead of just its index Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- carl-daniel noted that this makes it impossible to return other failure indications than the NULL pointer. this is correct, but i did not had any problems with it yet. it works very well this way imo. layout.c | 33 +++++++++++++++++---------------- 1 files changed, 17 insertions(+), 16 deletions(-) diff --git a/layout.c b/layout.c index d719a05..247c897 100644 --- a/layout.c +++ b/layout.c @@ -215,26 +215,28 @@ int find_romentry(char *name) return -1; } -int find_next_included_romentry(unsigned int start) +romlayout_t *get_next_included_romentry(unsigned int start) { int i; unsigned int best_start = UINT_MAX; - int best_entry = -1; + romlayout_t *best_entry = NULL; + romlayout_t *cur; /* First come, first serve for overlapping regions. */ for (i = 0; i < romimages; i++) { - if (!rom_entries[i].included) + cur = &rom_entries[i]; + if (!cur->included) continue; /* Already past the current entry? */ - if (start > rom_entries[i].end) + if (start > cur->end) continue; /* Inside the current entry? */ - if (start >= rom_entries[i].start) - return i; + if (start >= cur->start) + return cur; /* Entry begins after start. */ - if (best_start > rom_entries[i].start) { - best_start = rom_entries[i].start; - best_entry = i; + if (best_start > cur->start) { + best_start = cur->start; + best_entry = cur; } } return best_entry; @@ -243,7 +245,7 @@ int find_next_included_romentry(unsigned int start) int handle_romentries(struct flashchip *flash, uint8_t *oldcontents, uint8_t *newcontents) { unsigned int start = 0; - int entry; + romlayout_t *entry; unsigned int size = flash->total_size * 1024; /* If no layout file was specified or the layout file was empty, assume @@ -255,22 +257,21 @@ int handle_romentries(struct flashchip *flash, uint8_t *oldcontents, uint8_t *ne * The union of all included romentries is used from the new image. */ while (start < size) { - entry = find_next_included_romentry(start); + entry = get_next_included_romentry(start); /* No more romentries for remaining region? */ - if (entry < 0) { + if (entry == NULL) { memcpy(newcontents + start, oldcontents + start, size - start); break; } - if (rom_entries[entry].start > start) + if (entry->start > start) memcpy(newcontents + start, oldcontents + start, - rom_entries[entry].start - start); + entry->start - start); /* Skip to location after current romentry. */ - start = rom_entries[entry].end + 1; + start = entry->end + 1; /* Catch overflow. */ if (!start) break; } - return 0; } -- 1.7.1

1 0

[PATCH 0/7] every layout handling feature you ever wanted to see but never cared to implement
by Stefan Tauner 19 Aug '11

19 Aug '11

well the subject is a bit exaggerated and kinky, but i think layouts (not the write/read protection thingy carl-daniel wrote about lately, but the -l option) could be much more useful. especially for systems that are quite locked down (ICH/PCH...). with this patch set it is possible to - use -i and -l parameters in any order - specify a file for each image (so there is no need to create a full image beforehand) - use layout files for reading - use layout files for verifying some may need some refinements, and man page entries of course, but i wanted to post this now. first for thomas from GE because he asked for it and secondly to discuss if it is the right way to do this at all :) things to improve (either in the future or in a refined form of this patches): - reduce the footprint of the romlayout_t struct by not holding the whole strings but only references to strduped strings. - make the file parameter for -w, -r, -v optional if there are -i file names specified. - see 4/7 comments. Stefan Tauner (7): layout: change return type and name of find_next_included_romentry Add deferred -i processing layout: Add -i <image>[:<file>] support Make read before write configurable (infrastructure part) Use layout for read operations too Use layout for verify operations too (not for merge) Fix the "Use layout for verify operations too" patch in a hacky way cli_classic.c | 10 +-- flash.h | 13 +++- flashrom.c | 149 ++++++++++++++++++++++++++++++++------------ layout.c | 193 +++++++++++++++++++++++++++++++++++++++++++++------------ 4 files changed, 279 insertions(+), 86 deletions(-)

1 0

Asus Crosshair IV Extreme: flashrom -V
by Christophe Poncy 19 Aug '11

19 Aug '11

Hi, I would love to replace the bios for my mother board but I didn't find any coreboot suitable for the Asus Crosshair IV Extreme. I just wanted to let you know that I am available to test any builds in development. # Products info: AMD 890FX/SB850 Crosshair IV Extreme (ASUS mobo) http://www.asus.com/Motherboards/AMD_AM3/Crosshair_IV_Extreme/ http://www.amd.com/us/products/desktop/chipsets/8-series-integrated/Pages/a… # ./flashrom -r -L flashrom v0.9.4-r1395 on Linux 2.6.32-5-amd64 (x86_64), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "AMD SB700/SB710/SB750/SB850". Enabling flash write... OK. This chipset supports the following protocols: LPC, FWH, SPI. Found Winbond flash chip "W25Q16" (2048 kB, SPI) at physical address 0xffe00000. Reading flash... done. # ./flashrom -V (results are attached) Best regards, -- Support free software! Join FSF: https://my.fsf.org/associate/support_freedom?referrer=4574

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Re: [flashrom] report for Intel QM67 | Winbond W25Q64 ([PATCH] (not for merge) ichspi: print BFPR (BIOS Flash Primary Region Register))
by Stefan Tauner 19 Aug '11

19 Aug '11

On Fri, 19 Aug 2011 08:37:48 +0200 "Frei, Thomas (GE Germany)" <Thomas.Frei(a)ge.com> wrote: > Hi, > > I patched my flashrom an here is the output of the new code: > > ---snip--- > 0x00: 0x03ff0200 (BFPR) > 0x00200000-0x003fffff > ---snip--- > > Is this, what you expected? yes, it is equal to the bios region of yours: 0x58: 0x03ff0200 (FREG1: BIOS) 0x00200000-0x003fffff is read-write > > If I want to hack my flashrom: > - will it be possible to read the flash, or only to write it? for writing there is no need to hack anything. you can use the layout option for this already (please read the man page, really ;) if you can wait till tomorrow, you wont have to hack anything, because i have a patch already. if it is important please mail me directly and i can send it to you sooner. it needs a bit of work still before i can publish it. > - where will I have to change and what exactly, to have the quick, dirty and ugly hack working? > (I tried to search for "limit" and changed it to 0x3fffff and 0x7fffff - but nothing changed in behavior) there are several options. the easiest hack is probably to change the total_size field of the flash chip in question in flashchips.c around line 7978 to 4096. you need then to change the eraseblocks below that accordingly (else flashrom will detect the imbalance at startup and bail out). the first number is the block size and should stay the same for the first 3 erasers. the second one is the count of blocks and should be halved for those erasers. the last 2 are full chip erasers where you need to cut the size in half instead of the count. you can probably comment all erasers but the first away. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

Fwd: output of flashrom -V
by Michael Pihlblad 19 Aug '11

19 Aug '11

---------- Forwarded message ---------- From: "Michael Pihlblad" <michael.pihlblad(a)gmail.com> Date: Aug 18, 2011 10:19 PM Subject: output of flashrom -V To: <flashrom(a)flashrom.org> Attaching output of flashrom -V regards Michael -- Michael Pihlblad Tel: 073-3561840 e-post: michael.pihlblad(a)gmail.com

1 0

Re: [flashrom] report for Intel QM67 | Winbond W25Q64 ([PATCH] (not for merge) ichspi: print BFPR (BIOS Flash Primary Region Register))
by Stefan Tauner 19 Aug '11

19 Aug '11

On Tue, 16 Aug 2011 15:06:32 +0200 "Frei, Thomas (GE Germany)" <Thomas.Frei(a)ge.com> wrote: hello thomas and thanks for your report! sorry for the lengthy mail... especially because it does not contain a real solution yet, but maybe there will be one when we are done with this thread :) > - Intel QM67 is supported but untested. the basic SPI interface of the 6 series intel chipsets is not different from the earlier series. they have changed a few things behind the curtain though, which we don't understand fully yet. that could be the cause here. > - Mainboard flash write protection is not existant i beg to differ. there is a chipset protection in place, but we don't know how it works exactly. :) > […] > > First I tried to read the flashcontent -> ERROR!!! > > I didn't try to write jet - and I will not until the read is solved. good idea, because it most certainly will fail. > Please help me - I will provide you all information you will need. that would be great, but i fear you just don't have the information we need, or if you do you would be violating an NDA. :) > flashrom v0.9.4-r1395 on Linux 2.6.34-TSW (i686), built with libpci 3.1.7, GCC 4.5.0 20100604 [gcc-4_5-branch revision 160292], little endian > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OS timer resolution is 1 usecs, 1496M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1001 us, 10000 myus = 10005 us, 4 myus = 4 us, OK. > Initializing internal programmer > No coreboot table found. > DMI string system-manufacturer: "" > DMI string system-product-name: "" > DMI string system-version: "" > DMI string baseboard-manufacturer: "" > DMI string baseboard-product-name: "" > DMI string baseboard-version: "" > DMI string chassis-type: "" > DMI chassis-type is not specific enough. > Found chipset "Intel QM67" with PCI ID 8086:1c4f. > This chipset is marked as untested. If you are using an up-to-date version > of flashrom please email a report to flashrom(a)flashrom.org including a > verbose (-V) log. Thank you! i guess you are working on a prototype for GE? in general we try to detect laptops because we don't support them very well yet. please see http://flashrom.org/Laptops for details why we care to detect them. your DMI table seems to not indicate explicitly enough if it is a laptop or not. that is not necessarily a problem in general, i just wanted to mention it in case you are involved in the firmware design. in case you know it, could you please tell us a bit about the hardware design regarding the chipset<->flash connection? main question: is the flash chip directly connected to the qm67? are there any (external) ECs involved? > Enabling flash write... > […] > BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x8 > > Root Complex Register Block address = 0xfed1c000 > GCS = 0xc21: BIOS Interface Lock-Down: enabled, BOOT BIOS Straps: 0x3 (LPC) that's actually a bug. intel has changed the meaning of the bits in the GCS *again*. i'll look into it. afaics it is cosmetic only on all chipsets except ICH7, so it is not a problem for you thomas. > Top Swap : not enabled > SPIBAR = 0xfed1c000 + 0x3800 > 0x04: 0xe008 (HSFS) > HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 > WARNING: SPI Configuration Lockdown activated. this is the first sign of the real problem. FDV=1 means the descriptor in the flash is valid and FLOCKDN=1 means that we are restricted in changing most of the relevant SPI settings. this is (officially) required since at least ibex peak (5 series). alone, it is not a problem. FDOPSS=1 is an override bit (Flash Descriptor Override Pin-Strap Status), that is set by a hardware strap. is this accessible to you by a switch of some sort (e.g. jumper)? > 0x06: 0x0f00 (HSFC) > HSFC: FGO=0, FCYCLE=0, FDBC=15, SME=0 > 0x08: 0x00400000 (FADDR) > 0x50: 0x0000ffff (FRAP) > BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff 0xffff comes from the FDOPSS=1 and (should) indicate that we are allowed to access all regions of the flash (read and write). > 0x54: 0x00000000 (FREG0: Flash Descriptor) > 0x00000000-0x00000fff is read-write > 0x58: 0x03ff0200 (FREG1: BIOS) > 0x00200000-0x003fffff is read-write > 0x5C: 0x01ff0001 (FREG2: Management Engine) > 0x00001000-0x001fffff is read-write > 0x60: 0x00000fff (FREG3: Gigabit Ethernet) > Gigabit Ethernet region is unused. > 0x64: 0x00000fff (FREG4: Platform Data) > Platform Data region is unused. the following registers indicate no protected address regions either. > 0x74: 0x00000000 (PR0) > 0x78: 0x00000000 (PR1) > 0x7C: 0x00000000 (PR2) > 0x80: 0x00000000 (PR3) > 0x84: 0x00000000 (PR4) > 0x90: 0x84 (SSFS) > SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 > 0x91: 0xf80000 (SSFC) > SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=0 > 0x94: 0x0006 (PREOP) > 0x96: 0x043b (OPTYPE) > 0x98: 0x05200302 (OPMENU) > 0x9C: 0x0000019f (OPMENU+4) > 0xA0: 0x00000000 (BBAR) > 0xD0: 0x00000000 (FPB) > Reading OPCODES... done > preop0=0x06, preop1=0x00 > op[0]=0x02, 3, 0 > op[1]=0x03, 2, 0 > op[2]=0x20, 3, 0 > op[3]=0x05, 0, 0 > op[4]=0x9f, 0, 0 > op[5]=0x01, 1, 0 > op[6]=0x00, 0, 0 > op[7]=0x00, 0, 0 > > SPI Read Configuration: prefetching enabled, caching enabled, OK. > This chipset supports the following protocols: FWH, SPI. > […] > Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 > Chip status register is 00 > […] > Reading flash... SSFS: SCIP=0, FDONE=1, FCERR=1, AEL=0 > SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=63, SME=0, SCF=0 > Running OPCODE 0x03 failed at address 0x400000 (payload length was 64). > FAILED. now the interesting part. let's repeat the output of the FREGs ordered by address range: > 0x54: 0x00000000 (FREG0: Flash Descriptor) > 0x00000000-0x00000fff is read-write > 0x5C: 0x01ff0001 (FREG2: Management Engine) > 0x00001000-0x001fffff is read-write > 0x58: 0x03ff0200 (FREG1: BIOS) > 0x00200000-0x003fffff is read-write transaction err.@400000 so the first transaction after the bios region fails. not that this is also the first address that is not described by any FREG. i can't remember right now if this was ever a problem. my suspicion is that the chipset prohibits any access to addresses that are not mentioned/described by the FREGs. i have "only" two (retail) boards with intel chipsets for testing. both have the whole address range covered by the FREGs (but have other problems.. namely the known write protection by FRAP/PR*). i will need to look into this further (searching for other reports). how big is the image you want to write? (it is obviously 8MB because else flashrom would not continue, but did you modify it and was it 4MB before?) are you able to write the flash with intel's tool (iirc it is called FIT) under windows/dos? do you have access to the firmware modules that are combined to the full image and can you modify the descriptor part? if so it would be interesting to see what happens when you increase the FREG1.limit bits from 0x003fffff to 0x007fffff so that the bios region covers the second half of the flash too (this can be done by modifying the descriptor afaik). if i am right this would allow flashrom to access the whole flash. another thing you could test are my hardware sequencing patches posted to this list and also accessible via http://patchwork.coreboot.org/bundle/stefanct/hwseq/). but i doubt that hwseq will behave different from swseq in this case. OTOH it would be nice to confirm this. if it is not too inconvenient i would like to see the verbose output of a flashrom version modified by the attached patch to output BFPR. this should be equal to FREG1 and therefor we do not print it normally. it will certainly not change the general behavior in your case, i just want to be sure we know every possible detail. a workaround for your problem would be to change flashrom in a way that it does not try to access addresses > 0x003fffff. currently this is only possible while writing (see layout option in the manpage). so you would probably want to hardcode the limit in flashrom to solve the problem quickly but ugly. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 3

MSI H55-GD65 (MS-7637) (H55, locked ME region, FLOCKDN=0(!))
by Stefan Tauner 19 Aug '11

19 Aug '11

hi there i have read the log on IRC. thanks for your report! ICH/PCH boards are problematic due to their locks which can't be unlocked by flashrom (yet). please see my mails and blog posts of the last months for details. that said, your board is a bit special because although it has a locked (and a r/o) region, these locks are not locked (as indicated by FLOCKDN=0. if that sounds a bit complicated then you got it ;). this means that we could (try to) just set the correct access rights (something which is usually impossible due to the lock down). OTOH we had also reports in the past where the access rights SEEMED to be correct, but accessing the flash failed nonetheless. this is still a bit of too much guesswork... blame intel, sorry :) i will put a "set PR* to read/write if FLOCKDN==0" on my todo list and will inform you about its progress. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 1

Intel 82557/8/9/0/1 Ethernet Pro 100 - TESTED
by Антон Кочков 18 Aug '11

18 Aug '11

Intel 82557/8/9/0/1 Ethernet Pro 100 flashrom v0.9.4-r1395 on MS-DOS 8 (i786), built with libpci 3.1.5, GCC 4.3.2, little endian PROBE TESTED http://paste.flashrom.org/view.php?id=761 Best regards, Anton Kochkov.

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flashrom accepts its command line parameters as a file name to read to
by Idwer Vollering 18 Aug '11

18 Aug '11

2011/8/18 Christophe Poncy <cp(a)canaxis.org>: > Hi, > ... > # ./flashrom -r -L This shouldn't be allowed. What about disallowing the creation of files that have a name listed in cli_classic.c's optstring[] and/or long_options[] ? What's funny (or not..) is that running "flashrom -r -r" is allowed as well.

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Re: [flashrom] [PATCH 1/3] layout: change return type and name of find_next_included_romentry
by Tadas Slotkus 18 Aug '11

18 Aug '11

On Pr, 2011-08-15 at 06:43 +0200, Stefan Tauner wrote: > - rename from find_next_included_romentry to get_next_included_romentry > - return a pointer to a rom_entry instead of just its index > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Tadas Slotkus <devtadas(a)gmail.com>

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ASUS P5N-D
by Guillaume Poirier-Morency 18 Aug '11

18 Aug '11

I've been told, after an unsuccessful flashing, to send you these outputs about my motherboard. My board remained intact! If you are interested into enabling it and developing patches to make it compatible, I do not mind giving you feedback. Regards, Arteymis

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Zotac GeForce 8200: flashrom -V
by LukenShiro 18 Aug '11

18 Aug '11

I've used successfully flashrom 0.9.4 with my mainboard, reading (with -r) and writing (with -w) Zotac stock BIOS (updating it to last available version). No special flag were needed. # ./flashrom -V (results are attached) Best regards. -- GNU/Linux * Slackware64 current LU #210970 SU #12583 LM #98222/#412913

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Re: [flashrom] flashrom post from info@mingtaofurniture.com requires approval
by Stefan Tauner 18 Aug '11

18 Aug '11

On Thu, 18 Aug 2011 06:53:29 +0200 flashrom-owner(a)flashrom.org wrote: > As list administrator, your authorization is requested for the > following mailing list posting: > > List: flashrom(a)flashrom.org > From: info(a)mingtaofurniture.com > Subject: 3819289?$?$?$?$?$?$?$?uhmms > Reason: Post by non-member to a members-only list > > At your convenience, visit: > > http://www.flashrom.org/mailman/admindb/flashrom > > to approve or deny the request. let's hope mailman does the right thing. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH 1/3] layout: change return type and name of find_next_included_romentry
by Stefan Tauner 18 Aug '11

18 Aug '11

On Mon, 15 Aug 2011 06:43:36 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > -typedef struct { > +static struct rom_entry { > unsigned int start; > unsigned int end; > unsigned int included; > char name[256]; > -} romlayout_t; > - > -static romlayout_t rom_entries[MAX_ROMLAYOUT]; > +} rom_entries[MAX_ROMLAYOUT]; this was a big mistake. this type is very useful - not necessarily in this setup, but in general we want a rom_entry type to pass around functions that operate on parts of the flash only (i am working on making reads obey layouts atm). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH] Makefile: fix and simplify test program compilations
by Carl-Daniel Hailfinger 17 Aug '11

17 Aug '11

Am 12.08.2011 21:38 schrieb Stefan Tauner: > this was totally broken due to the time behavior of make's shell > function's temporal behavior. > quote from the gnu make documentation > http://www.gnu.org/s/hello/manual/make/Shell-Function.html): > "The commands run by calls to the shell function are run when the > function calls are expanded" > we have used the shell function to echo the test programs to a file. > the file name used was equal for all tests and was overwritten for > each test. the result was that all tests (in a single target?) used > the last test program because the echoing of the test programs was > done before all test compilations(!) > Thanks for opening that bug report. Apparently the gnu make documentation was incorrect. > also the branching for testing ifeq ($(CONFIG_FT2232_SPI), yes) was > unnecessary. > Branching never worked for me inside a target, but I also never tried it your way. > in my approach here i am using verbatim variables (allows to define > even complex test programs in the makefile without jumping through > hoops) that get exported to environment variables (via "export", > reference afterwards with "$$<varname>"). > > i have also added the missing redirection of stderr to the compiler test. > Good. > alternatively one could just use different file names of course, but > i think my approach is superior due to the separation and > readability of the tested code and the fact that the temporal > behavior is MUCH clearer now (else this bug would have not crept in > in the first place :P) > > if line count is an issue one could of course compress the test > programs to something unreadable again :) > Haha. > side note: we use $(CC) all over the place before we even check if > it is there. e.g.: > override ARCH = $(strip $(shell LC_ALL=C $(CC) -E arch.h|grep -v '^\#')) > > this creates unwanted output like: > make -j1 CC=eiugthes > /bin/sh: eiugthes: not found > /bin/sh: eiugthes: not found > /bin/sh: eiugthes: not found > /bin/sh: eiugthes: not found > Checking for a C compiler... not found. > Hm yes. > make: *** [compiler] Error 1 > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > Makefile | 91 ++++++++++++++++++++++++++++++++++++++++---------------------- > 1 files changed, 59 insertions(+), 32 deletions(-) > > diff --git a/Makefile b/Makefile > index c72d10a..672a0df 100644 > --- a/Makefile > +++ b/Makefile > @@ -531,11 +531,62 @@ distclean: clean > strip: $(PROGRAM)$(EXEC_SUFFIX) > $(STRIP) $(STRIP_ARGS) $(PROGRAM)$(EXEC_SUFFIX) > > +# below are the definitions of test programs as verbatim variables, which get > +# exported to environment variables and are referenced with $$<varname> later > +define COMPILER_TEST > +int main(int argc, char **argv) > +{ > + (void) argafc; > Typo? > +define UTSNAME_TEST > +#include <sys/utsname.h> > +struct utsname osinfo; > +int main(int argc, char **argv) > +{ > + (void) argc; > + (void) argv; > + uname (&osinfo); > + return 0; > +} > +endef > +export UTSNAME_TEST > Hm... the alternative would be to have each of those C programs in a separate file in a config/ directory or somesuch. I don't have a strong preference either way. Given that you think verbatim variables are superior, please move them directly above the targets which use them. > + > compiler: featuresavailable > @printf "Checking for a C compiler... " > - @$(shell ( echo "int main(int argc, char **argv)"; \ > - echo "{ (void) argc; (void) argv; return 0; }"; ) > .test.c ) > - @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .test.c -o .test$(EXEC_SUFFIX) >/dev/null && \ > + @echo "$$COMPILER_TEST" > .test.c > + @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .test.c -o .test$(EXEC_SUFFIX) >/dev/null 2>&1 && \ > echo "found." || ( echo "not found."; \ > rm -f .test.c .test$(EXEC_SUFFIX); exit 1) > @rm -f .test.c .test$(EXEC_SUFFIX) > @@ -548,12 +599,7 @@ compiler: featuresavailable > ifeq ($(CHECK_LIBPCI), yes) > pciutils: compiler > @printf "Checking for libpci headers... " > - @# Avoid a failing test due to libpci header symbol shadowing breakage > - @$(shell ( echo "#define index shadow_workaround_index"; \ > - echo "#include <pci/pci.h>"; \ > - echo "struct pci_access *pacc;"; \ > - echo "int main(int argc, char **argv)"; \ > - echo "{ (void) argc; (void) argv; pacc = pci_alloc(); return 0; }"; ) > .test.c ) > + @echo "$$LIBPCI_TEST" > .test.c > @$(CC) -c $(CPPFLAGS) $(CFLAGS) .test.c -o .test.o >/dev/null 2>&1 && \ > echo "found." || ( echo "not found."; echo; \ > echo "Please install libpci headers (package pciutils-devel)."; \ > @@ -588,41 +634,22 @@ featuresavailable: > @false > endif > > -ifeq ($(CONFIG_FT2232_SPI), yes) > features: compiler > @echo "FEATURES := yes" > .features.tmp > +ifeq ($(CONFIG_FT2232_SPI), yes) > I'm really surprised that ifeq inside a target works. IIRC I tried this some time ago on my older machine and it did not work. However, if this works reliably, the code is indeed a lot more readable. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Even if we ever decide to use another build system, we need this fix now. Regards, Carl-Daniel

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[commit] r1416 - trunk
by repository service 17 Aug '11

17 Aug '11

Author: stefanct Date: Thu Aug 18 04:27:19 2011 New Revision: 1416 URL: http://flashrom.org/trac/flashrom/changeset/1416 Log: Makefile: fix and simplify test program compilations this was totally broken due to the make's shell function's temporal behavior. quote from the gnu make documentation (http://www.gnu.org/s/hello/manual/make/Shell-Function.html): "The commands run by calls to the shell function are run when the function calls are expanded" we have used the shell function to echo the test programs to a file. the file name used was equal for all tests and was overwritten for each test. the result was that all tests (in a single target?) used the last test program because the echoing of the test programs was done before all test compilations(!) see my mail for details: http://lists.gnu.org/archive/html/bug-make/2011-08/msg00010.html also the branching for testing ifeq ($(CONFIG_FT2232_SPI), yes) was unnecessarily complicated. in my approach here i am using verbatim variables (allows to define even complex test programs in the makefile without jumping through hoops) that get exported to environment variables (via "export", reference afterwards with "$$<varname>"). i have also added the missing redirection of stderr to the compiler test and changed the definition of ARCH to use simple expansion (:=). the latter is still wrong, because it uses $(CC) before we check if a compiler is installed... makes the compiler check pretty much useless. The simple expansion just reduces the number of errors printed to 1. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/Makefile Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Wed Aug 17 11:50:11 2011 (r1415) +++ trunk/Makefile Thu Aug 18 04:27:19 2011 (r1416) @@ -38,7 +38,7 @@ endif # Determine the destination processor architecture -override ARCH = $(strip $(shell LC_ALL=C $(CC) -E arch.h|grep -v '^\#')) +override ARCH := $(strip $(shell LC_ALL=C $(CC) -E arch.h|grep -v '^\#')) # FIXME We have to differentiate between host and target OS architecture. OS_ARCH ?= $(shell uname) @@ -531,11 +531,23 @@ strip: $(PROGRAM)$(EXEC_SUFFIX) $(STRIP) $(STRIP_ARGS) $(PROGRAM)$(EXEC_SUFFIX) +# to define test programs we use verbatim variables, which get exported +# to environment variables and are referenced with $$<varname> later + +define COMPILER_TEST +int main(int argc, char **argv) +{ + (void) argc; + (void) argv; + return 0; +} +endef +export COMPILER_TEST + compiler: featuresavailable @printf "Checking for a C compiler... " - @$(shell ( echo "int main(int argc, char **argv)"; \ - echo "{ (void) argc; (void) argv; return 0; }"; ) > .test.c ) - @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .test.c -o .test$(EXEC_SUFFIX) >/dev/null && \ + @echo "$$COMPILER_TEST" > .test.c + @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .test.c -o .test$(EXEC_SUFFIX) >/dev/null 2>&1 && \ echo "found." || ( echo "not found."; \ rm -f .test.c .test$(EXEC_SUFFIX); exit 1) @rm -f .test.c .test$(EXEC_SUFFIX) @@ -545,15 +557,25 @@ ( echo "unknown. Aborting."; exit 1) @printf "%s\n" '$(ARCH)' +define LIBPCI_TEST +/* Avoid a failing test due to libpci header symbol shadowing breakage */ +#define index shadow_workaround_index +#include <pci/pci.h> +struct pci_access *pacc; +int main(int argc, char **argv) +{ + (void) argc; + (void) argv; + pacc = pci_alloc(); + return 0; +} +endef +export LIBPCI_TEST + ifeq ($(CHECK_LIBPCI), yes) pciutils: compiler @printf "Checking for libpci headers... " - @# Avoid a failing test due to libpci header symbol shadowing breakage - @$(shell ( echo "#define index shadow_workaround_index"; \ - echo "#include <pci/pci.h>"; \ - echo "struct pci_access *pacc;"; \ - echo "int main(int argc, char **argv)"; \ - echo "{ (void) argc; (void) argv; pacc = pci_alloc(); return 0; }"; ) > .test.c ) + @echo "$$LIBPCI_TEST" > .test.c @$(CC) -c $(CPPFLAGS) $(CFLAGS) .test.c -o .test.o >/dev/null 2>&1 && \ echo "found." || ( echo "not found."; echo; \ echo "Please install libpci headers (package pciutils-devel)."; \ @@ -588,41 +610,47 @@ @false endif -ifeq ($(CONFIG_FT2232_SPI), yes) +define FTDI_TEST +#include <ftdi.h> +struct ftdi_context *ftdic = NULL; +int main(int argc, char **argv) +{ + (void) argc; + (void) argv; + return ftdi_init(ftdic); +} +endef +export FTDI_TEST + +define UTSNAME_TEST +#include <sys/utsname.h> +struct utsname osinfo; +int main(int argc, char **argv) +{ + (void) argc; + (void) argv; + uname (&osinfo); + return 0; +} +endef +export UTSNAME_TEST + features: compiler @echo "FEATURES := yes" > .features.tmp +ifeq ($(CONFIG_FT2232_SPI), yes) @printf "Checking for FTDI support... " - @$(shell ( echo "#include <ftdi.h>"; \ - echo "struct ftdi_context *ftdic = NULL;"; \ - echo "int main(int argc, char **argv)"; \ - echo "{ (void) argc; (void) argv; return ftdi_init(ftdic); }"; ) > .featuretest.c ) + @echo "$$FTDI_TEST" > .featuretest.c @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) $(FTDILIBS) $(LIBS) >/dev/null 2>&1 && \ ( echo "found."; echo "FTDISUPPORT := yes" >> .features.tmp ) || \ ( echo "not found."; echo "FTDISUPPORT := no" >> .features.tmp ) +endif @printf "Checking for utsname support... " - @$(shell ( echo "#include <sys/utsname.h>"; \ - echo "struct utsname osinfo;"; \ - echo "int main(int argc, char **argv)"; \ - echo "{ (void) argc; (void) argv; uname (&osinfo); return 0; }"; ) > .featuretest.c ) - @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) >/dev/null 2>&1 && \ - ( echo "found."; echo "UTSNAME := yes" >> .features.tmp ) || \ - ( echo "not found."; echo "UTSNAME := no" >> .features.tmp ) - @$(DIFF) -q .features.tmp .features >/dev/null 2>&1 && rm .features.tmp || mv .features.tmp .features - @rm -f .featuretest.c .featuretest$(EXEC_SUFFIX) -else -features: compiler - @echo "FEATURES := yes" > .features.tmp - @printf "Checking for utsname support... " - @$(shell ( echo "#include <sys/utsname.h>"; \ - echo "struct utsname osinfo;"; \ - echo "int main(int argc, char **argv)"; \ - echo "{ (void) argc; (void) argv; uname (&osinfo); return 0; }"; ) > .featuretest.c ) + @echo "$$UTSNAME_TEST" > .featuretest.c @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) >/dev/null 2>&1 && \ ( echo "found."; echo "UTSNAME := yes" >> .features.tmp ) || \ ( echo "not found."; echo "UTSNAME := no" >> .features.tmp ) @$(DIFF) -q .features.tmp .features >/dev/null 2>&1 && rm .features.tmp || mv .features.tmp .features @rm -f .featuretest.c .featuretest$(EXEC_SUFFIX) -endif install: $(PROGRAM)$(EXEC_SUFFIX) mkdir -p $(DESTDIR)$(PREFIX)/sbin

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qflashrom dutch (nl-NL) translation
by Bernd Blaauw 17 Aug '11

17 Aug '11

I'm currently delaying things I should be doing, so in a boring moment decided to translate qflashrom language file. [ https://gitorious.org/qflashrom/qflashrom/blobs/master/locale/qflashrom_de_… ]. (btw lines 169..171 are confusing, mentioning 'read' but german part says 'write') Textfile attached, no idea if FireFox and MetaPad kept it as UTF8. Entirely untested ofcourse due to running Windows and no development platforms whatsoever (besides VMware for emulation/virtualisation). Likely usable as well for [nl-BE] but who can tell.. Consider it my €0,02 to this project :) with best regards, Bernd Blaauw (license stuff: whatever the original had, or public domain, at your convenience, giving up all rights to copyright, do as you please).

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[Patch] Added SST25LF080A Flash Chip
by Zeus Castro 17 Aug '11

17 Aug '11

Added support for SST25LF080A flash chip, based on public datasheet available here: http://www.sst.com/dotAsset/40316.pdf

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[commit] r1415 - trunk
by repository service 17 Aug '11

17 Aug '11

Author: stefanct Date: Wed Aug 17 11:50:11 2011 New Revision: 1415 URL: http://flashrom.org/trac/flashrom/changeset/1415 Log: Add support for the SST25LF080A flash chip Based on the definition of SST25LF040A and the public datasheet available here: http://www.sst.com/dotAsset/40316.pdf Also, move the SST25LF040A up to keep the list ordered alphabetically (while removing the ".RES" suffix). Signed-off-by: Zeus Castro <thezeusjuice(a)gmail.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/flashchips.c Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Tue Aug 16 14:08:22 2011 (r1414) +++ trunk/flashchips.c Wed Aug 17 11:50:11 2011 (r1415) @@ -5547,6 +5547,66 @@ { .vendor = "SST", + .name = "SST25LF040A", + .bustype = BUS_SPI, + .manufacture_id = SST_ID, + .model_id = SST_SST25VF040_REMS, + .total_size = 512, + .page_size = 256, + .tested = TEST_OK_PROBE, + .probe = probe_spi_res2, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 128} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 16} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_1, /* AAI supported, but opcode is 0xAF */ + .read = spi_chip_read, + .voltage = {3000, 3600}, + }, + + { + .vendor = "SST", + .name = "SST25LF080A", + .bustype = BUS_SPI, + .manufacture_id = SST_ID, + .model_id = SST_SST25VF080_REMS, + .total_size = 1024, + .page_size = 256, + .tested = TEST_UNTESTED, + .probe = probe_spi_res2, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 32} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, + }, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_1, /* AAI supported, but opcode is 0xAF */ + .read = spi_chip_read, + .voltage = {3000, 3600}, + }, + + { + .vendor = "SST", .name = "SST25VF010.REMS", .bustype = BUS_SPI, .manufacture_id = SST_ID, @@ -5750,36 +5810,6 @@ }, { - .vendor = "SST", - .name = "SST25LF040A.RES", - .bustype = BUS_SPI, - .manufacture_id = SST_ID, - .model_id = SST_SST25VF040_REMS, - .total_size = 512, - .page_size = 256, - .tested = TEST_OK_PROBE, - .probe = probe_spi_res2, - .probe_timing = TIMING_ZERO, - .block_erasers = - { - { - .eraseblocks = { {4 * 1024, 128} }, - .block_erase = spi_block_erase_20, - }, { - .eraseblocks = { {32 * 1024, 16} }, - .block_erase = spi_block_erase_52, - }, { - .eraseblocks = { {512 * 1024, 1} }, - .block_erase = spi_block_erase_60, - }, - }, - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_1, /* AAI supported, but opcode is 0xAF */ - .read = spi_chip_read, - .voltage = {3000, 3600}, - }, - - { .vendor = "SST", .name = "SST25VF040B.REMS", .bustype = BUS_SPI,

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Re: [flashrom] report for Intel QM67 | Winbond W25Q64
by Stefan Tauner 17 Aug '11

17 Aug '11

On Wed, 17 Aug 2011 09:16:05 +0200 "Frei, Thomas (GE Germany)" <Thomas.Frei(a)ge.com> wrote: > Hi Stefan, > > First of all: thank you for the quick response. > Yes I work on a prototype from GE :-) > > OK - now to your questions: > - the flashchip is connected as follows: SPI_CLK + SPI_MOSI are connected via a FET_busswitch, and SPI_MISI is connected directly to the chipset. > - I can use FPT.EXE from intel, and it successfully reads the content of the flashchip - but only 4MB!!! > - the file, I got from the hardware development, that should be used here, also has 4MB!!!??? moin! very interesting. this endorses my theory somewhat that the chipset prohibits writes outside the address ranges of the regions defined by the FREGs completely. this is rather bad because it does not work well with the current concept of flashrom, which basically is founded on the idea that we can access the whole under normal circumstances - or at least that the programmer (in your case the chipset) does not get in our way by unexpected means. this would be a very good use case for a layout file... if it would work for reading :/ or a parameter that would tell flashrom to not throw away the data read, if there is an error later... which does not exist either. that said, writing could work quite normally with a layout file. you would need to make the image match the size of the chip though, so that flashrom accepts it in the first place. i think cp image.bin test.bin ; cat image.bin >> test.bin would work. even without a layout file this would probably write correctly... but flashrom would scream when accessing the second half of the chip. please see the manpage for details about the layout file option. i will work on this in one way or another, but please don't expect it to be committed or even working soon. i guess that you know helge wagner at GE? he may be able to help you (in hacking something together) too. if you test the method outlined above i would really like to hear if it works. please note though that it may also brick your setup... dont blame me then please :) if you want to help us and have a method to recover bricked boards (i.e. if you have an external programmer that works with your boards), you could also try to play with the FREG1 values in the descriptor with fit.exe (or fitw.exe). that said, i just read an interesting paragraph in the ibex peak SPI programming guide: "Flash Space Allocation FIT/Ftoolc allocates SPI flash space allocation for each region as follows: 1. 2. If after allocation for all regions there is still space left in flash, then the ME region expands to fill the remaining space. 3. If there is leftover space and the ME region is not implemented, then the BIOS region is expands to use the remaining space. 4. If there is leftover space and the BIOS region is not implemented, then the GbE region is expands to contain the remaining space." not sure if that still applies to cougar point, but i would guess so. in this case i am wondering if your hardware engineering team has created the image correctly (or if they have set up the total size incorrectly to 4MB instead of 8). > P.S.: Bist Du etwa ein Student an der TU Wien - sprichst Du also Deutsch? yes i am, but since this is public and some of us do not speak german, we use english exclusively on the mailing list. you can mail me directly though, if it is important. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[PATCH] Fix printing of the Boot BIOS Straps on Intel chipsets
by Stefan Tauner 17 Aug '11

17 Aug '11

The meaning of the bits involved has changed several times in the past. This patch takes these changes into account and hence fixes the output of the pretty printing of GCS on all SPI-supported Intel chipsets that are not ICH7 or NM10 (the latter were unaffected, because the defaults were correct). This patch also allows to differentiate Ibex Peak and Cougar Point chipsets from the earlier chipset series (ICH10) by adding new wrapper functions that set "ich_generation" to 11 and 12 respectively. This should not change behavior outside of enable_flash_ich_dc_spi, because the code path for ich_generation >=9 is equal. --- defining all those arrays is not very elegant, but i think it is at least very readable this way. improvements are welcome! reviewers should have an eye on the codepaths for ich_generation >= 9. i did not spot a problem, but it should be checked again. alternatively we could just remove the pretty printing of GCS and just output the bits involved. i would like to keep the pch differentiation anyway though, because i feel it will become handy in the future. tested on my QS57-based thinkpad (probe + partial read) Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipset_enable.c | 129 ++++++++++++++++++++++++++++++++++-------------------- 1 files changed, 81 insertions(+), 48 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index 687682a..662273b 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -440,11 +440,6 @@ static int enable_flash_poulsbo(struct pci_dev *dev, const char *name) return 0; } -#define ICH_STRAP_RSVD 0x00 -#define ICH_STRAP_SPI 0x01 -#define ICH_STRAP_PCI 0x02 -#define ICH_STRAP_LPC 0x03 - static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name) { /* Do we really need no write enable? */ @@ -458,13 +453,39 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, uint8_t bbs, buc; uint32_t tmp, gcs; void *rcrb; - - /* - * TODO: These names are incorrect for EP80579. For that, the solution - * would look like the commented line below. - */ - // static const char *straps_names[] = {"SPI", "reserved", "reserved", "LPC" }; - static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" }; + const char *const *straps_names; + + static const char *const straps_names_EP80579[] = { "SPI", "reserved", "reserved", "LPC" }; + static const char *const straps_names_ich7_nm10[] = { "reserved", "SPI", "PCI", "LPC" }; + static const char *const straps_names_ich8910[] = { "SPI", "SPI", "PCI", "LPC" }; + static const char *const straps_names_pch56[] = { "LPC", "reserved", "PCI", "SPI" }; + static const char *const straps_names_unknown[] = { "unknown", "unknown", "unknown", "unknown" }; + + switch (ich_generation) { + case 7: + /* EP80579 may need further changes, but this is the least + * intrusive way to get correct BOOT Strap printing without + * changing the rest of its code path) */ + if (strcmp(name, "EP80579") == 0) + straps_names = straps_names_EP80579; + else + straps_names = straps_names_ich7_nm10; + break; + case 8: + case 9: + case 10: + straps_names = straps_names_ich8910; + break; + case 11: + case 12: + straps_names = straps_names_pch56; + break; + default: + msg_gerr("%s: unknown ICH generation. Please report!\n", + __func__); + straps_names = straps_names_unknown; + break; + } /* Enable Flash Writes */ ret = enable_flash_ich_dc(dev, name); @@ -481,7 +502,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, msg_pdbg("BIOS Interface Lock-Down: %sabled, ", (gcs & 0x1) ? "en" : "dis"); bbs = (gcs >> 10) & 0x3; - msg_pdbg("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]); + msg_pdbg("Boot BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]); buc = mmio_readb(rcrb + 0x3414); msg_pdbg("Top Swap : %s\n", @@ -491,11 +512,11 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, * time. At least not with our current code. So we prevent searching * on ICH7 when the southbridge is strapped to LPC */ - buses_supported = BUS_FWH; if (ich_generation == 7) { - if (bbs == ICH_STRAP_LPC) { - /* No further SPI initialization required */ + if (bbs == 0x03) { + /* If strapped to LPC, no further SPI initialization is + * required. */ return ret; } else { /* Disable LPC/FWH if strapped to PCI or SPI */ @@ -532,6 +553,18 @@ static int enable_flash_ich10(struct pci_dev *dev, const char *name) return enable_flash_ich_dc_spi(dev, name, 10); } +/* Ibex Peak aka. 5 series & 3400 series */ +static int enable_flash_pch5(struct pci_dev *dev, const char *name) +{ + return enable_flash_ich_dc_spi(dev, name, 11); +} + +/* Cougar Point aka. 6 series & c200 series */ +static int enable_flash_pch6(struct pci_dev *dev, const char *name) +{ + return enable_flash_ich_dc_spi(dev, name, 12); +} + static int via_no_byte_merge(struct pci_dev *dev, const char *name) { uint8_t val; @@ -1158,21 +1191,21 @@ const struct penable chipset_enables[] = { {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000}, {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4}, {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4}, - {0x8086, 0x1c44, NT, "Intel", "Z68", enable_flash_ich10}, - {0x8086, 0x1c46, NT, "Intel", "P67", enable_flash_ich10}, - {0x8086, 0x1c47, NT, "Intel", "UM67", enable_flash_ich10}, - {0x8086, 0x1c49, NT, "Intel", "HM65", enable_flash_ich10}, - {0x8086, 0x1c4a, NT, "Intel", "H67", enable_flash_ich10}, - {0x8086, 0x1c4b, NT, "Intel", "HM67", enable_flash_ich10}, - {0x8086, 0x1c4c, NT, "Intel", "Q65", enable_flash_ich10}, - {0x8086, 0x1c4d, NT, "Intel", "QS67", enable_flash_ich10}, - {0x8086, 0x1c4e, NT, "Intel", "Q67", enable_flash_ich10}, - {0x8086, 0x1c4f, NT, "Intel", "QM67", enable_flash_ich10}, - {0x8086, 0x1c50, NT, "Intel", "B65", enable_flash_ich10}, - {0x8086, 0x1c52, NT, "Intel", "C202", enable_flash_ich10}, - {0x8086, 0x1c54, NT, "Intel", "C204", enable_flash_ich10}, - {0x8086, 0x1c56, NT, "Intel", "C206", enable_flash_ich10}, - {0x8086, 0x1c5c, NT, "Intel", "H61", enable_flash_ich10}, + {0x8086, 0x1c44, NT, "Intel", "Z68", enable_flash_pch6}, + {0x8086, 0x1c46, NT, "Intel", "P67", enable_flash_pch6}, + {0x8086, 0x1c47, NT, "Intel", "UM67", enable_flash_pch6}, + {0x8086, 0x1c49, NT, "Intel", "HM65", enable_flash_pch6}, + {0x8086, 0x1c4a, NT, "Intel", "H67", enable_flash_pch6}, + {0x8086, 0x1c4b, NT, "Intel", "HM67", enable_flash_pch6}, + {0x8086, 0x1c4c, NT, "Intel", "Q65", enable_flash_pch6}, + {0x8086, 0x1c4d, NT, "Intel", "QS67", enable_flash_pch6}, + {0x8086, 0x1c4e, NT, "Intel", "Q67", enable_flash_pch6}, + {0x8086, 0x1c4f, NT, "Intel", "QM67", enable_flash_pch6}, + {0x8086, 0x1c50, NT, "Intel", "B65", enable_flash_pch6}, + {0x8086, 0x1c52, NT, "Intel", "C202", enable_flash_pch6}, + {0x8086, 0x1c54, NT, "Intel", "C204", enable_flash_pch6}, + {0x8086, 0x1c56, NT, "Intel", "C206", enable_flash_pch6}, + {0x8086, 0x1c5c, NT, "Intel", "H61", enable_flash_pch6}, {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e}, {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e}, {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich_4e}, @@ -1211,23 +1244,23 @@ const struct penable chipset_enables[] = { {0x8086, 0x3a18, OK, "Intel", "ICH10", enable_flash_ich10}, {0x8086, 0x3a1a, OK, "Intel", "ICH10D", enable_flash_ich10}, {0x8086, 0x3a1e, NT, "Intel", "ICH10 Engineering Sample", enable_flash_ich10}, - {0x8086, 0x3b00, NT, "Intel", "3400 Desktop", enable_flash_ich10}, - {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_ich10}, - {0x8086, 0x3b02, NT, "Intel", "P55", enable_flash_ich10}, - {0x8086, 0x3b03, NT, "Intel", "PM55", enable_flash_ich10}, - {0x8086, 0x3b06, NT, "Intel", "H55", enable_flash_ich10}, - {0x8086, 0x3b07, OK, "Intel", "QM57", enable_flash_ich10}, - {0x8086, 0x3b08, NT, "Intel", "H57", enable_flash_ich10}, - {0x8086, 0x3b09, NT, "Intel", "HM55", enable_flash_ich10}, - {0x8086, 0x3b0a, NT, "Intel", "Q57", enable_flash_ich10}, - {0x8086, 0x3b0b, NT, "Intel", "HM57", enable_flash_ich10}, - {0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF", enable_flash_ich10}, - {0x8086, 0x3b0e, NT, "Intel", "B55", enable_flash_ich10}, - {0x8086, 0x3b0f, OK, "Intel", "QS57", enable_flash_ich10}, - {0x8086, 0x3b12, NT, "Intel", "3400", enable_flash_ich10}, - {0x8086, 0x3b14, NT, "Intel", "3420", enable_flash_ich10}, - {0x8086, 0x3b16, NT, "Intel", "3450", enable_flash_ich10}, - {0x8086, 0x3b1e, NT, "Intel", "B55", enable_flash_ich10}, + {0x8086, 0x3b00, NT, "Intel", "3400 Desktop", enable_flash_pch5}, + {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_pch5}, + {0x8086, 0x3b02, NT, "Intel", "P55", enable_flash_pch5}, + {0x8086, 0x3b03, NT, "Intel", "PM55", enable_flash_pch5}, + {0x8086, 0x3b06, NT, "Intel", "H55", enable_flash_pch5}, + {0x8086, 0x3b07, OK, "Intel", "QM57", enable_flash_pch5}, + {0x8086, 0x3b08, NT, "Intel", "H57", enable_flash_pch5}, + {0x8086, 0x3b09, NT, "Intel", "HM55", enable_flash_pch5}, + {0x8086, 0x3b0a, NT, "Intel", "Q57", enable_flash_pch5}, + {0x8086, 0x3b0b, NT, "Intel", "HM57", enable_flash_pch5}, + {0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF", enable_flash_pch5}, + {0x8086, 0x3b0e, NT, "Intel", "B55", enable_flash_pch5}, + {0x8086, 0x3b0f, OK, "Intel", "QS57", enable_flash_pch5}, + {0x8086, 0x3b12, NT, "Intel", "3400", enable_flash_pch5}, + {0x8086, 0x3b14, NT, "Intel", "3420", enable_flash_pch5}, + {0x8086, 0x3b16, NT, "Intel", "3450", enable_flash_pch5}, + {0x8086, 0x3b1e, NT, "Intel", "B55", enable_flash_pch5}, {0x8086, 0x5031, OK, "Intel", "EP80579", enable_flash_ich7}, {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4}, {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4}, -- 1.7.1

1 0

Advent MT22: flashrom -V
by simon jenkins 16 Aug '11

16 Aug '11

Here is the flashrom -V output for the Advent MT22 system: [root@simon ~]# flashrom -V flashrom v0.9.3-r1368 on Linux 2.6.40-4.fc15.i686.PAE (i686), built with libpci 3.1.7, GCC 4.6.0 20110530 (Red Hat 4.6.0-9), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 2183M loops per second, 10 myus = 10 us, 100 myus = 114 us, 1000 myus = 999 us, 10000 myus = 9987 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Advent" DMI string system-product-name: "MT22" DMI string system-version: "100" DMI string baseboard-manufacturer: "To be filled by O.E.M." DMI string baseboard-product-name: "To be filled by O.E.M." DMI string baseboard-version: "To be filled by O.E.M." DMI string chassis-type: "" Found chipset "NVIDIA MCP79", enabling flash write... chipset PCI ID is 10de:0aae, This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Flash bus type is SPI SPI on this chipset is WIP. Write is unsupported! Found SMBus device 10de:0aa2 at 00:03:2 MCP SPI BAR is at 0xfae80000 Mapping NVIDIA MCP6x SPI at 0xfae80000, unaligned size 0x544. SPI control is 0xc105, req=1, gnt=1 Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25D16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found chip "Macronix MX25L8005" (1024 kB, SPI) at physical address 0xfff00000. Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF010.REMS, 128 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF040.REMS, 512 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25LF040A.RES, 512 kB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P05.RES, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P10.RES, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xc2, id2 0x13 No operations were specified.

1 0

SPI. RDID, REMS, RES and other probe variants
by Carl-Daniel Hailfinger 16 Aug '11

16 Aug '11

Hi, Stefan Tauner mentioned that we use probe methods inconsistently: Some SPI chips use RDID, some use REMS, some use RES, and then there are various variants (mostly varied response length) of those probe functions. The reason is that we originally had exactly one possible probe function per chip. With SPI chips, there are up to 5 different probe functions for the same chip, each with a different ID. Fun! We need to revamp the probing architecture, preferably in a future-proof way. Possible solutions: - Handle probing like erase, i.e. an array of ID+function pairs. - Add n variants of each chip, one per probe function. That's what works with the current architecture and what has been done for a few chips in the past. - Something completely different which I haven't thought of. Comments? I once had a prototype patch for the first solution, but it bitrotted and I was not happy with the design back then, but nowadays the flashrom architecture is better and this could be done in a non-ugly way. Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

report for Intel QM67 | Winbond W25Q64
by Frei, Thomas (GE Germany) 16 Aug '11

16 Aug '11

Hello, to step through the FAQ: - Winbond W25Q64 is supported - Intel QM67 is supported but untested. - Mainboard flash write protection is not existant - BIOS flash write protection is disabled - Kernel is 2.6.34 - CONFIG_X86_PAT is set - reset with kernel parameter "nopat" does not change anything - CONFIG_STRICT_DEVMEM is not set First I tried to read the flashcontent -> ERROR!!! I didn't try to write jet - and I will not until the read is solved. Please help me - I will provide you all information you will need. Best regards Thomas Frei

1 0

Re: [flashrom] [PATCH] remove unneeded inclusions of chipdrivers.h
by Stefan Tauner 16 Aug '11

16 Aug '11

On Sun, 10 Jul 2011 14:01:44 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > this is related to the spi split patch as discussed in: > http://www.flashrom.org/pipermail/flashrom/2010-February/thread.html#2364 > the old commit (r914) log notes: > "Some of the spi programmer drivers required chipdrivers.h, needs fixing later: it87spi.c ichspi.c sb600spi.c wbsio_spi.c buspirate_spi.c ft2232spi.c bitbang_spi.c dediprog.c" > > there still remain a few cases where chipdrivers.h is needed: > dediprog.c > it87spi.c > wbsio_spi.c (spi_programmer registration only) > > besides that, there are also non-spi files that do not need it. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> self-acked and committed in r1414 -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

[patch] Include "flash.h" and <inttypes.h> in chipdrivers.h
by David Hendricks 16 Aug '11

16 Aug '11

This patch is intended to avoid compilation issues caused by the ordering of #includes in source files that use chipdrivers.h. Signed-off-by: David Hendricks <dhendrix(a)google.com> -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

2 3

[commit] r1414 - trunk
by repository service 16 Aug '11

16 Aug '11

Author: stefanct Date: Tue Aug 16 14:08:22 2011 New Revision: 1414 URL: http://flashrom.org/trac/flashrom/changeset/1414 Log: Remove unneeded inclusions of chipdrivers.h this is related to the spi split patch as discussed in: http://www.flashrom.org/pipermail/flashrom/2010-February/thread.html#2364 the old commit (r914) log notes: "Some of the spi programmer drivers required chipdrivers.h, needs fixing later: it87spi.c ichspi.c sb600spi.c wbsio_spi.c buspirate_spi.c ft2232spi.c bitbang_spi.c dediprog.c" there still remain a few cases where chipdrivers.h is needed: dediprog.c (spi_read_chunked and spi_write_chunked) it87spi.c (due to spi_write_enable and spi_read_status_register) wbsio_spi.c (spi_programmer registration only) besides that, there are also non-spi files that do not need it. also, add flash.h to chipdrivers.h because it uses some types of it and remove flashchips.h from print.c Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/bitbang_spi.c trunk/buspirate_spi.c trunk/chipdrivers.h trunk/ft2232_spi.c trunk/ichspi.c trunk/it85spi.c trunk/jedec.c trunk/pm49fl00x.c trunk/print.c trunk/sb600spi.c trunk/sst_fwhub.c trunk/w29ee011.c trunk/w39.c Modified: trunk/bitbang_spi.c ============================================================================== --- trunk/bitbang_spi.c Mon Aug 15 21:54:20 2011 (r1413) +++ trunk/bitbang_spi.c Tue Aug 16 14:08:22 2011 (r1414) @@ -22,7 +22,6 @@ #include <stdlib.h> #include <ctype.h> #include "flash.h" -#include "chipdrivers.h" #include "programmer.h" #include "spi.h" Modified: trunk/buspirate_spi.c ============================================================================== --- trunk/buspirate_spi.c Mon Aug 15 21:54:20 2011 (r1413) +++ trunk/buspirate_spi.c Tue Aug 16 14:08:22 2011 (r1414) @@ -23,7 +23,6 @@ #include <ctype.h> #include <unistd.h> #include "flash.h" -#include "chipdrivers.h" #include "programmer.h" #include "spi.h" Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Mon Aug 15 21:54:20 2011 (r1413) +++ trunk/chipdrivers.h Tue Aug 16 14:08:22 2011 (r1414) @@ -25,6 +25,8 @@ #ifndef __CHIPDRIVERS_H__ #define __CHIPDRIVERS_H__ 1 +#include "flash.h" /* for chipaddr and flashchip */ + /* spi.c, should probably be in spi_chip.c */ int probe_spi_rdid(struct flashchip *flash); int probe_spi_rdid4(struct flashchip *flash); Modified: trunk/ft2232_spi.c ============================================================================== --- trunk/ft2232_spi.c Mon Aug 15 21:54:20 2011 (r1413) +++ trunk/ft2232_spi.c Tue Aug 16 14:08:22 2011 (r1414) @@ -25,7 +25,6 @@ #include <stdlib.h> #include <ctype.h> #include "flash.h" -#include "chipdrivers.h" #include "programmer.h" #include "spi.h" #include <ftdi.h> Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Mon Aug 15 21:54:20 2011 (r1413) +++ trunk/ichspi.c Tue Aug 16 14:08:22 2011 (r1414) @@ -27,7 +27,6 @@ #include <string.h> #include "flash.h" -#include "chipdrivers.h" #include "programmer.h" #include "spi.h" Modified: trunk/it85spi.c ============================================================================== --- trunk/it85spi.c Mon Aug 15 21:54:20 2011 (r1413) +++ trunk/it85spi.c Tue Aug 16 14:08:22 2011 (r1414) @@ -30,7 +30,6 @@ #include <stdio.h> #include <stdlib.h> #include "flash.h" -#include "chipdrivers.h" #include "spi.h" #include "programmer.h" Modified: trunk/jedec.c ============================================================================== --- trunk/jedec.c Mon Aug 15 21:54:20 2011 (r1413) +++ trunk/jedec.c Tue Aug 16 14:08:22 2011 (r1414) @@ -23,7 +23,6 @@ */ #include "flash.h" -#include "chipdrivers.h" #define MAX_REFLASH_TRIES 0x10 #define MASK_FULL 0xffff Modified: trunk/pm49fl00x.c ============================================================================== --- trunk/pm49fl00x.c Mon Aug 15 21:54:20 2011 (r1413) +++ trunk/pm49fl00x.c Tue Aug 16 14:08:22 2011 (r1414) @@ -21,7 +21,6 @@ */ #include "flash.h" -#include "chipdrivers.h" static void write_lockbits_49fl00x(chipaddr bios, int size, unsigned char bits, int block_size) Modified: trunk/print.c ============================================================================== --- trunk/print.c Mon Aug 15 21:54:20 2011 (r1413) +++ trunk/print.c Tue Aug 16 14:08:22 2011 (r1414) @@ -23,7 +23,6 @@ #include <string.h> #include <stdlib.h> #include "flash.h" -#include "flashchips.h" #include "programmer.h" /* Modified: trunk/sb600spi.c ============================================================================== --- trunk/sb600spi.c Mon Aug 15 21:54:20 2011 (r1413) +++ trunk/sb600spi.c Tue Aug 16 14:08:22 2011 (r1414) @@ -24,7 +24,6 @@ #if defined(__i386__) || defined(__x86_64__) #include "flash.h" -#include "chipdrivers.h" #include "programmer.h" #include "spi.h" Modified: trunk/sst_fwhub.c ============================================================================== --- trunk/sst_fwhub.c Mon Aug 15 21:54:20 2011 (r1413) +++ trunk/sst_fwhub.c Tue Aug 16 14:08:22 2011 (r1414) @@ -23,7 +23,6 @@ /* Adapted from the Intel FW hub stuff for 82802ax parts. */ #include "flash.h" -#include "chipdrivers.h" static int check_sst_fwhub_block_lock(struct flashchip *flash, int offset) { Modified: trunk/w29ee011.c ============================================================================== --- trunk/w29ee011.c Mon Aug 15 21:54:20 2011 (r1413) +++ trunk/w29ee011.c Tue Aug 16 14:08:22 2011 (r1414) @@ -20,7 +20,6 @@ #include <string.h> #include "flash.h" -#include "chipdrivers.h" /* According to the Winbond W29EE011, W29EE012, W29C010M, W29C011A * datasheets this is the only valid probe function for those chips. Modified: trunk/w39.c ============================================================================== --- trunk/w39.c Mon Aug 15 21:54:20 2011 (r1413) +++ trunk/w39.c Tue Aug 16 14:08:22 2011 (r1414) @@ -20,7 +20,6 @@ */ #include "flash.h" -#include "chipdrivers.h" static int printlock_w39_fwh_block(struct flashchip *flash, int offset) {

1 0

[PATCH] internal dmi decoder
by Sean Nelson 16 Aug '11

16 Aug '11

Here is a new version of the internal dmi decoding. To use the new decoder, the user needs to use "-p internal:dmi=new", to cross-check with the external dmidecode use "-p internal:dmi=check". Hopefully if this is comitted, it will make it easier for people to test the new internal decoder. Signed-off-by: Sean Nelson <audiohacked(a)gmail.com>

5 8

[commit] r1413 - trunk
by repository service 15 Aug '11

15 Aug '11

Author: hailfinger Date: Mon Aug 15 21:54:20 2011 New Revision: 1413 URL: http://flashrom.org/trac/flashrom/changeset/1413 Log: Fixup of r1397: - Mixing uninitialized and initialized local variables leads to confusion. - ft2232_spi error cases should have gotten some error handling, and that's the reason the curly braces were there. - Fixing typos/wording in some places would have been nice given that those places were touched anyway. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/buspirate_spi.c trunk/chipset_enable.c trunk/cli_classic.c trunk/dediprog.c trunk/dmi.c trunk/flashrom.c trunk/ft2232_spi.c trunk/it85spi.c trunk/it87spi.c trunk/physmap.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Fri Aug 12 03:19:32 2011 (r1412) +++ trunk/board_enable.c Mon Aug 15 21:54:20 2011 (r1413) @@ -860,7 +860,7 @@ return -1; } - /* First, check the ISA bridge */ + /* Check for the ISA bridge first. */ dev = pci_dev_find_vendorclass(0x10DE, 0x0601); switch (dev->device_id) { case 0x0030: /* CK804 */ @@ -1129,8 +1129,8 @@ struct pci_dev *dev; uint32_t tmp, base; - /* GPPO {0,8,27,28,30} are always available */ - static const uint32_t nonmuxed_gpos = 0x58000101; + /* GPO{0,8,27,28,30} are always available. */ + static const uint32_t nonmuxed_gpos = 0x58000101; static const struct {unsigned int reg, mask, value; } piix4_gpo[] = { {0}, @@ -1179,10 +1179,9 @@ } if ((((1 << gpo) & nonmuxed_gpos) == 0) && - (pci_read_word(dev, piix4_gpo[gpo].reg) - & piix4_gpo[gpo].mask) != piix4_gpo[gpo].value) { - msg_perr("\nERROR: PIIX4 GPO%d not programmed for output.\n", - gpo); + ((pci_read_word(dev, piix4_gpo[gpo].reg) & piix4_gpo[gpo].mask) != + piix4_gpo[gpo].value)) { + msg_perr("\nERROR: PIIX4 GPO%d not programmed for output.\n", gpo); return -1; } Modified: trunk/buspirate_spi.c ============================================================================== --- trunk/buspirate_spi.c Fri Aug 12 03:19:32 2011 (r1412) +++ trunk/buspirate_spi.c Mon Aug 15 21:54:20 2011 (r1413) @@ -150,9 +150,11 @@ int buspirate_spi_init(void) { unsigned char buf[512]; - int ret = 0, i, spispeed = 0x7; char *dev = NULL; char *speed = NULL; + int spispeed = 0x7; + int ret = 0; + int i; dev = extract_programmer_param("dev"); if (!dev || !strlen(dev)) { Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Fri Aug 12 03:19:32 2011 (r1412) +++ trunk/chipset_enable.c Mon Aug 15 21:54:20 2011 (r1413) @@ -309,8 +309,9 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name) { uint32_t fwh_conf; + int i, tmp; char *idsel = NULL; - int i, tmp, max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0; + int max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0; int contiguous = 1; idsel = extract_programmer_param("fwh_idsel"); @@ -1035,7 +1036,7 @@ } } else { msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. " - "Assuming flash at 4G\n"); + "Assuming flash at 4G.\n"); } /* 4. Clean up */ Modified: trunk/cli_classic.c ============================================================================== --- trunk/cli_classic.c Fri Aug 12 03:19:32 2011 (r1412) +++ trunk/cli_classic.c Mon Aug 15 21:54:20 2011 (r1413) @@ -104,13 +104,14 @@ struct flashchip flashes[3]; struct flashchip *fill_flash; const char *name; - int startchip = 0, chipcount = 0, namelen, opt, option_index = 0; - int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0; - int dont_verify_it = 0, list_supported = 0, force = 0; + int namelen, opt, i; + int startchip = 0, chipcount = 0, option_index = 0, force = 0; #if CONFIG_PRINT_WIKI == 1 int list_supported_wiki = 0; #endif - int operation_specified = 0, i, ret = 0; + int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0; + int dont_verify_it = 0, list_supported = 0, operation_specified = 0; + int ret = 0; static const char optstring[] = "r:Rw:v:nVEfc:m:l:i:p:Lzh"; static const struct option long_options[] = { Modified: trunk/dediprog.c ============================================================================== --- trunk/dediprog.c Fri Aug 12 03:19:32 2011 (r1412) +++ trunk/dediprog.c Mon Aug 15 21:54:20 2011 (r1413) @@ -496,7 +496,8 @@ static int parse_voltage(char *voltage) { char *tmp = NULL; - int i, millivolt, fraction = 0; + int i; + int millivolt = 0, fraction = 0; if (!voltage || !strlen(voltage)) { msg_perr("Empty voltage= specified.\n"); @@ -574,7 +575,8 @@ { struct usb_device *dev; char *voltage; - int millivolt = 3500, ret; + int millivolt = 3500; + int ret; msg_pspew("%s\n", __func__); Modified: trunk/dmi.c ============================================================================== --- trunk/dmi.c Fri Aug 12 03:19:32 2011 (r1412) +++ trunk/dmi.c Mon Aug 15 21:54:20 2011 (r1413) @@ -196,7 +196,8 @@ */ static int dmi_compare(const char *value, const char *pattern) { - int anchored = 0, patternlen; + int anchored = 0; + int patternlen; msg_pspew("matching %s against %s\n", value, pattern); /* The empty string is part of all strings! */ Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Fri Aug 12 03:19:32 2011 (r1412) +++ trunk/flashrom.c Mon Aug 15 21:54:20 2011 (r1413) @@ -600,8 +600,7 @@ size_t size = flash->total_size * 1024; /* Flash registers live 4 MByte below the flash. */ /* FIXME: This is incorrect for nonstandard flashbase. */ - flash->virtual_registers = (chipaddr)programmer_map_flash_region( - "flash chip registers", (0xFFFFFFFF - 0x400000 - size + 1), size); + flash->virtual_registers = (chipaddr)programmer_map_flash_region("flash chip registers", (0xFFFFFFFF - 0x400000 - size + 1), size); } int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len) @@ -753,8 +752,9 @@ int verify_range(struct flashchip *flash, uint8_t *cmpbuf, int start, int len, const char *message) { - int i, ret = 0, failcount = 0; + int i; uint8_t *readbuf = malloc(len); + int ret = 0, failcount = 0; if (!len) goto out_free; @@ -832,7 +832,8 @@ */ int need_erase(uint8_t *have, uint8_t *want, int len, enum write_granularity gran) { - int result = 0, i, j, limit; + int result = 0; + int i, j, limit; switch (gran) { case write_gran_1bit: @@ -898,7 +899,8 @@ static int get_next_write(uint8_t *have, uint8_t *want, int len, int *first_start, enum write_granularity gran) { - int need_write = 0, rel_start = 0, first_len = 0, i, limit, stride; + int need_write = 0, rel_start = 0, first_len = 0; + int i, limit, stride; switch (gran) { case write_gran_1bit: @@ -1326,7 +1328,8 @@ */ static int selfcheck_eraseblocks(const struct flashchip *flash) { - int i, j, k, ret = 0; + int i, j, k; + int ret = 0; for (k = 0; k < NUM_ERASEFUNCTIONS; k++) { unsigned int done = 0; @@ -1451,7 +1454,8 @@ void *param1, void *param2) { int i, j; - unsigned int start = 0, len; + unsigned int start = 0; + unsigned int len; struct block_eraser eraser = flash->block_erasers[erasefunction]; for (i = 0; i < NUM_ERASEREGIONS; i++) { @@ -1603,8 +1607,10 @@ void list_programmers_linebreak(int startcol, int cols, int paren) { const char *pname; - int pnamelen, remaining = 0, firstline = 1, i; + int pnamelen; + int remaining = 0, firstline = 1; enum programmer p; + int i; for (p = 0; p < PROGRAMMER_INVALID; p++) { pname = programmer_table[p].name; Modified: trunk/ft2232_spi.c ============================================================================== --- trunk/ft2232_spi.c Fri Aug 12 03:19:32 2011 (r1412) +++ trunk/ft2232_spi.c Mon Aug 15 21:54:20 2011 (r1413) @@ -252,17 +252,21 @@ ftdic->error_str); } - if (ftdi_usb_reset(ftdic) < 0) + if (ftdi_usb_reset(ftdic) < 0) { msg_perr("Unable to reset FTDI device\n"); + } - if (ftdi_set_latency_timer(ftdic, 2) < 0) + if (ftdi_set_latency_timer(ftdic, 2) < 0) { msg_perr("Unable to set latency timer\n"); + } - if (ftdi_write_data_set_chunksize(ftdic, 256)) + if (ftdi_write_data_set_chunksize(ftdic, 256)) { msg_perr("Unable to set chunk size\n"); + } - if (ftdi_set_bitmode(ftdic, 0x00, BITMODE_BITBANG_SPI) < 0) + if (ftdi_set_bitmode(ftdic, 0x00, BITMODE_BITBANG_SPI) < 0) { msg_perr("Unable to set bitmode to SPI\n"); + } if (clock_5x) { msg_pdbg("Disable divide-by-5 front stage\n"); @@ -329,7 +333,8 @@ struct ftdi_context *ftdic = &ftdic_context; static unsigned char *buf = NULL; /* failed is special. We use bitwise ops, but it is essentially bool. */ - int i = 0, ret = 0, failed = 0, bufsize; + int i = 0, ret = 0, failed = 0; + int bufsize; static int oldbufsize = 0; if (writecnt > 65536 || readcnt > 65536) Modified: trunk/it85spi.c ============================================================================== --- trunk/it85spi.c Fri Aug 12 03:19:32 2011 (r1412) +++ trunk/it85spi.c Mon Aug 15 21:54:20 2011 (r1413) @@ -84,15 +84,15 @@ static int it85xx_scratch_rom_reenter = 0; /* This function will poll the keyboard status register until either - * an expected value shows up, or - * timeout reaches. + * an expected value shows up, or the timeout is reached. + * timeout is in usec. * - * Returns: 0 -- the expected value has shown. - * 1 -- timeout reached. + * Returns: 0 -- the expected value showed up. + * 1 -- timeout. */ static int wait_for(const unsigned int mask, const unsigned int expected_value, - const int timeout /* in usec */, const char *error_message, - const char *function_name, const int lineno) + const int timeout, const char * error_message, + const char * function_name, const int lineno) { int time_passed; @@ -317,8 +317,9 @@ int i; it85xx_enter_scratch_rom(); - /* exit scratch ROM ONLY when programmer shuts down. Otherwise, the - * temporary flash state may halt EC. */ + /* Exit scratch ROM ONLY when programmer shuts down. Otherwise, the + * temporary flash state may halt the EC. + */ #ifdef LPC_IO INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff); Modified: trunk/it87spi.c ============================================================================== --- trunk/it87spi.c Fri Aug 12 03:19:32 2011 (r1412) +++ trunk/it87spi.c Mon Aug 15 21:54:20 2011 (r1413) @@ -203,7 +203,8 @@ int init_superio_ite(void) { - int i, ret = 0; + int i; + int ret = 0; for (i = 0; i < superio_count; i++) { if (superios[i].vendor != SUPERIO_VENDOR_ITE) Modified: trunk/physmap.c ============================================================================== --- trunk/physmap.c Fri Aug 12 03:19:32 2011 (r1412) +++ trunk/physmap.c Mon Aug 15 21:54:20 2011 (r1413) @@ -76,7 +76,7 @@ mi.address = phys_addr; mi.size = len; - ret = __dpmi_physical_address_mapping (&mi); + ret = __dpmi_physical_address_mapping(&mi); if (ret != 0) return ERROR_PTR;

2 1

Re: [flashrom] [PATCH 3/3] an obvious but dubios refactor opportunity
by Tadas Slotkus 15 Aug '11

15 Aug '11

> diff --git a/layout.c b/layout.c > index 8283e36..fe29852 100644 > --- a/layout.c > +++ b/layout.c > @@ -240,6 +240,19 @@ static struct rom_entry *get_next_included_romentry(unsigned int start) > return best_entry; > } > > +static void copy_old_content(struct flashchip *flash, int oldcontents_valid, uint8_t *oldcontents, uint8_t *newcontents, unsigned int start, unsigned int size) Could you split it to multiple lines? Nice work! :) Acked-by: Tadas Slotkus <devtadas(a)gmail.com> Thanks, Tadas

1 0

Re: [flashrom] [PATCH 2/3] Make read before write configurable (infrastructure part)
by Tadas Slotkus 15 Aug '11

15 Aug '11

> @@ -1961,11 +1961,13 @@ int doit(struct flashchip *flash, int force, const char *filename, int read_it, > ret = 1; > goto out; > } > - } > - emergency_help_message(); > - ret = 1; > - goto out; > - } > + } else Could you kill that last curly bracket? :) Acked-by: Tadas Slotkus <devtadas(a)gmail.com>

1 0

wiki output
by Stefan Tauner 15 Aug '11

15 Aug '11

i'd like to improve the wiki output. first of all i'd like to get the voltage printing of chips in. after that i would like to add support for linked footnotes, because our tables are long and right now the user has to scroll a lot to read them. i think those two things are not controversial, so we can discuss them when i am sending the patches (voltage printing has already been posted a few weeks ago actually). the other thing i want to do is to improve the list of supported mainboards. right now - we don't differentiate between revisions (besides adding them to the name as string). - we can't distinguish between not supported at all and untested board enable (we use the note field for this). - we try to link to the vendor... which fails more often than it works over the time imho. i presume the most problematic thing is removal of the urls. basically i don't care if support for them remains, but i will stop adding them myself. it is just a waste of time imho because they change so often or the targets just vanish. if i can persuade all of you to think that too, it would be even better. so... i don't see the reason we do this at all (besides the obvious hypertext argument that one should link as much as possible). i doubt any user will follow those links to find "his" board. why should s/he? what's the use case for those links? carldani replied "identification of supported revisions" (more or less). this is a bogus argument. the URLs don't do that now, and in most of the cases they can't (because there is only one single page for multiple revisions or even models). anyway, we should not be divided by this particular detail, so now to the really important stuff. i'd like to add a ? "icon" to boards with untested board enables (just like we do everywhere else if we are not sure yet). this would require extending the "working" field of struct board_info and using OK, NT and a to-be-defined third macro instead of just 0 and 1 in the table itself (or, an enum... much preferred solution by me). quite easy stuff. then i had the idea to somehow add board revisions more explicitly. just adding additional columns like it is done for the chip statuses won't cut it, because we need to fit the names of the revisions in there too. but maybe it is enough nonetheless: what about - adding n columns where n is the maximum number of revisions of a single board, and - in each column we print the revision name followed by OK, No, or ?; or nothing if there are less revisions to support this we would need to expand the existing struct and macros, but it is doable imho. other ideas are welcome. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 1

[PATCH] Always read chip before writing, avoid emergency messages
by Carl-Daniel Hailfinger 15 Aug '11

15 Aug '11

Always read the flash chip before writing. This will allow flashrom to skip erase of already-erased blocks and to skip write of blocks which already have the wanted contents. Avoid emergency messages by checking if the chip contents after a failed write operation (erase/write) are unchanged. Keep the emergency messages after a failed pure erase. That part is debatable because if someone wants erase, he pretty sure doesn't care about the flash contents anymore. Please note that this introduces additional overhead of a full chip read before write. This is frowned upon by people with slow programmers. Maybe we should make this configurable. Either way, this patch needs a review to make sure I'm not going in the wrong direction. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-always_read_no_scary_warning/flash.h =================================================================== --- flashrom-always_read_no_scary_warning/flash.h (Revision 1212) +++ flashrom-always_read_no_scary_warning/flash.h (Arbeitskopie) @@ -239,7 +239,7 @@ /* layout.c */ int read_romlayout(char *name); int find_romentry(char *name); -int handle_romentries(uint8_t *buffer, struct flashchip *flash); +int handle_romentries(struct flashchip *flash, uint8_t *oldcontents, uint8_t *newcontents); /* spi.c */ struct spi_command { Index: flashrom-always_read_no_scary_warning/layout.c =================================================================== --- flashrom-always_read_no_scary_warning/layout.c (Revision 1212) +++ flashrom-always_read_no_scary_warning/layout.c (Arbeitskopie) @@ -205,7 +205,7 @@ return -1; } -int handle_romentries(uint8_t *buffer, struct flashchip *flash) +int handle_romentries(struct flashchip *flash, uint8_t *oldcontents, uint8_t *newcontents) { int i; @@ -225,13 +225,12 @@ // normal will be updated and the rest will be kept. for (i = 0; i < romimages; i++) { - if (rom_entries[i].included) continue; - flash->read(flash, buffer + rom_entries[i].start, - rom_entries[i].start, - rom_entries[i].end - rom_entries[i].start + 1); + memcpy(newcontents + rom_entries[i].start, + oldcontents + rom_entries[i].start, + rom_entries[i].end - rom_entries[i].start + 1); } return 0; Index: flashrom-always_read_no_scary_warning/flashrom.c =================================================================== --- flashrom-always_read_no_scary_warning/flashrom.c (Revision 1212) +++ flashrom-always_read_no_scary_warning/flashrom.c (Arbeitskopie) @@ -1343,6 +1343,19 @@ return ret; } +void nonfatal_help_message(void) +{ + msg_gerr("Writing to the flash chip apparently didn't do anything.\n" + "This means we have to add special support for your board, " + "programmer or flash chip.\n" + "Please report this on IRC at irc.freenode.net (channel " + "#flashrom) or\n" + "mail flashrom(a)flashrom.org!\n" + "-------------------------------------------------------------" + "------------------\n" + "You may now reboot or simply leave the machine running.\n"); +} + void emergency_help_message(void) { msg_gerr("Your flash chip is in an unknown state.\n" @@ -1602,9 +1615,10 @@ */ int doit(struct flashchip *flash, int force, char *filename, int read_it, int write_it, int erase_it, int verify_it) { - uint8_t *buf; + uint8_t *oldcontents; + uint8_t *newcontents; int ret = 0; - unsigned long size; + unsigned long size = flash->total_size * 1024; if (chip_safety_check(flash, force, filename, read_it, write_it, erase_it, verify_it)) { msg_cerr("Aborting.\n"); @@ -1612,9 +1626,6 @@ return 1; } - size = flash->total_size * 1024; - buf = (uint8_t *) calloc(size, sizeof(char)); - /* Given the existence of read locks, we want to unlock for read, * erase and write. */ @@ -1627,6 +1638,12 @@ return ret; } if (erase_it) { + /* FIXME: Do we really want the scary warning if erase failed? + * After all, after erase the chip is either blank or partially + * blank or it has the old contents. A blank chip won't boot, + * so if the user wanted erase and reboots afterwards, the user + * knows very well that booting won't work. + */ if (erase_flash(flash)) { emergency_help_message(); programmer_shutdown(); @@ -1634,33 +1651,71 @@ } } + newcontents = (uint8_t *) calloc(size, sizeof(char)); + if (write_it || verify_it) { - if (read_buf_from_file(buf, flash->total_size * 1024, filename)) { + if (read_buf_from_file(newcontents, size, filename)) { programmer_shutdown(); return 1; } #if CONFIG_INTERNAL == 1 - show_id(buf, size, force); + if (programmer == PROGRAMMER_INTERNAL) + show_id(newcontents, size, force); #endif } + oldcontents = (uint8_t *) calloc(size, sizeof(char)); + + /* Read the whole chip to be able to check whether regions need to be + * erased and to give better diagnostics in case write fails. + * The alternative would be to read only the regions which are to be + * preserved, but in that case we might perform unneeded erase which + * takes time as well. + */ + msg_cdbg("Reading old flash chip contents...\n"); + if (flash->read(flash, oldcontents, 0, size)) { + programmer_shutdown(); + return 1; + } + // This should be moved into each flash part's code to do it // cleanly. This does the job. - handle_romentries(buf, flash); + handle_romentries(flash, oldcontents, newcontents); // //////////////////////////////////////////////////////////// if (write_it) { if (erase_flash(flash)) { + msg_cerr("Uh oh. Erase failed. Checking if anything " + "changed.\n"); + if (!flash->read(flash, newcontents, 0, size)) { + if (!memcmp(oldcontents, newcontents, size)) { + msg_cinfo("Good. It seems nothing was " + "changed.\n"); + nonfatal_help_message(); + programmer_shutdown(); + return 1; + } + } emergency_help_message(); programmer_shutdown(); return 1; } msg_cinfo("Writing flash chip... "); - ret = flash->write(flash, buf, 0, flash->total_size * 1024); + ret = flash->write(flash, newcontents, 0, size); if (ret) { - msg_cerr("FAILED!\n"); + msg_cerr("Uh oh. Write failed. Checking if anything " + "changed.\n"); + if (!flash->read(flash, newcontents, 0, size)) { + if (!memcmp(oldcontents, newcontents, size)) { + msg_cinfo("Good. It seems nothing was " + "changed.\n"); + nonfatal_help_message(); + programmer_shutdown(); + return 1; + } + } emergency_help_message(); programmer_shutdown(); return 1; @@ -1673,7 +1728,7 @@ /* Work around chips which need some time to calm down. */ if (write_it) programmer_delay(1000*1000); - ret = verify_flash(flash, buf); + ret = verify_flash(flash, newcontents); /* If we tried to write, and verification now fails, we * might have an emergency situation. */ -- http://www.hailfinger.org/

4 8

HP Pavilion dv6-6030er
by pol kh 14 Aug '11

14 Aug '11

# flashrom -VV flashrom v0.9.4-r1394 on Linux 2.6.39-2-amd64 (x86_64), built with libpci 3.1.7, GCC 4.6.1 20110616 (prerelease), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 959M loops per second, 10 myus = 10 us, 100 myus = 116 us, 1000 myus = 1085 us, 10000 myus = 10240 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Hewlett-Packard" DMI string system-product-name: "HP Pavilion dv6 Notebook PC" DMI string system-version: "0596100000244710000010100" DMI string baseboard-manufacturer: "Hewlett-Packard" DMI string baseboard-product-name: "164B" DMI string baseboard-version: "06.1F" DMI string chassis-type: "Notebook" Laptop detected via DMI. Found ITE EC, ID 0x8518,Rev 0x02 on port 0x4e. ======================================================================== WARNING! You seem to be running flashrom on an unsupported laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Aborting. # flashrom -VV -r 01649F20.bin flashrom v0.9.4-r1394 on Linux 2.6.39-2-amd64 (x86_64), built with libpci 3.1.7, GCC 4.6.1 20110616 (prerelease), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 997M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1000 us, 10000 myus = 10005 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Hewlett-Packard" DMI string system-product-name: "HP Pavilion dv6 Notebook PC" DMI string system-version: "0596100000244710000010100" DMI string baseboard-manufacturer: "Hewlett-Packard" DMI string baseboard-product-name: "164B" DMI string baseboard-version: "06.1F" DMI string chassis-type: "Notebook" Laptop detected via DMI. Found ITE EC, ID 0x8518,Rev 0x02 on port 0x4e. ======================================================================== WARNING! You seem to be running flashrom on an unsupported laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Aborting. # lspci -nnvvvxxx 00:00.0 Host bridge [0600]: Advanced Micro Devices [AMD] RS880 Host Bridge [1022:9601] Subsystem: Advanced Micro Devices [AMD] Device [1022:1234] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx- Latency: 0 Capabilities: [c4] HyperTransport: Slave or Primary Interface Command: BaseUnitID=0 UnitCnt=12 MastHost- DefDir- DUL- Link Control 0: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 0: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Link Control 1: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config 1: MLWI=8bit DwFcIn- MLWO=8bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 3.00 Link Frequency 0: [a] Link Error 0: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 0: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC- LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- Link Frequency 1: 200MHz Link Error 1: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability 1: 200MHz- 300MHz- 400MHz- 500MHz- 600MHz- 800MHz- 1.0GHz- 1.2GHz- 1.4GHz- 1.6GHz- Vend- Error Handling: PFlE- OFlE- PFE- OFE- EOCFE- RFE- CRCFE- SERRFE- CF- RE+ PNFE- ONFE- EOCNFE- RNFE- CRCNFE- SERRNFE- Prefetchable memory behind bridge Upper: 00-00 Bus Number: 00 Capabilities: [54] HyperTransport: UnitID Clumping Capabilities: [40] HyperTransport: Retry Mode Capabilities: [9c] HyperTransport: #1a Capabilities: [f8] HyperTransport: #1c 00: 22 10 01 96 06 00 30 22 00 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 34 12 30: 00 00 00 00 c4 00 00 00 00 00 00 00 00 00 00 00 40: 08 9c 00 c0 c1 00 00 00 56 00 00 00 42 20 05 00 50: 22 10 34 12 08 40 00 90 08 10 05 00 00 00 05 00 60: 00 00 00 00 8e 00 00 00 00 02 20 00 0f 80 86 81 70: 00 00 00 00 00 00 00 00 ad 00 01 11 00 00 00 20 80: 00 00 00 00 10 00 06 03 20 c8 00 00 13 26 00 10 90: 00 00 00 d0 3d 01 00 00 47 00 00 00 08 f8 7c d0 a0: 26 00 66 00 00 00 00 82 00 00 00 00 79 01 c0 07 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 80 08 54 80 01 20 00 11 00 d0 00 00 00 d0: 60 0a 75 1e 02 00 00 00 00 00 00 02 00 00 00 00 e0: 00 00 00 00 ff ff ff ff 0d 02 00 00 64 40 05 00 f0: 00 00 00 00 01 00 00 00 08 00 00 e0 00 00 00 00 00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] RS780/RS880 PCI to PCI bridge (int gfx) [1022:9602] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 00004000-00004fff Memory behind bridge: f0500000-f06fffff Prefetchable memory behind bridge: 00000000d0000000-00000000dfffffff Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA+ MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [44] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] Device [1022:1235] 00: 22 10 02 96 07 00 30 02 00 00 04 06 00 40 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 41 41 20 02 20: 50 f0 60 f0 01 d0 f1 df 00 00 00 00 00 00 00 00 30: 00 00 00 00 44 00 00 00 00 00 00 00 ff 00 08 00 40: 00 00 00 00 08 b0 03 a8 00 00 00 00 22 10 35 12 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 0d 00 00 00 22 10 35 12 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:03.0 PCI bridge [0604]: Advanced Micro Devices [AMD] RS780 PCI to PCI bridge (ext gfx port 1) [1022:960b] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 I/O behind bridge: 00003000-00003fff Memory behind bridge: f0400000-f04fffff Prefetchable memory behind bridge: 00000000e0000000-00000000efffffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #1, Speed 5GT/s, Width x8, ASPM L0s L1, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt+ SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Slot #3, PowerLimit 75.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Not Supported, TimeoutDis- ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0300c Data: 4161 Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] Device [1022:1234] Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [110 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Kernel driver in use: pcieport 00: 22 10 0b 96 07 04 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 02 02 00 31 31 00 20 20: 40 f0 40 f0 01 e0 f1 ef 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 03 c8 00 00 00 00 10 a0 42 01 20 80 00 00 60: 10 08 00 00 82 0c 30 01 43 00 82 f0 e0 25 1c 00 70: 00 00 48 01 00 00 01 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 42 00 01 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 b0 01 00 0c 30 e0 fe 61 41 00 00 00 00 00 00 b0: 0d b8 00 00 22 10 34 12 08 00 03 a8 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 ff ff ff ff 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:04.0 PCI bridge [0604]: Advanced Micro Devices [AMD] RS780 PCI to PCI bridge (PCIE port 0) [1022:9604] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=03, subordinate=03, sec-latency=0 I/O behind bridge: 00002000-00002fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: 00000000f0000000-00000000f00fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #1, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #4, PowerLimit 25.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Not Supported, TimeoutDis- ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0300c Data: 4169 Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] Device [1022:1234] Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [110 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Kernel driver in use: pcieport 00: 22 10 04 96 07 04 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 03 03 00 21 21 00 00 20: f0 ff 00 00 01 f0 01 f0 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 03 c8 00 00 00 00 10 a0 42 01 20 80 00 00 60: 10 08 00 00 12 0c 30 01 40 00 11 70 80 0c 24 00 70: 00 00 48 01 00 00 01 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 42 00 01 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 b0 01 00 0c 30 e0 fe 69 41 00 00 00 00 00 00 b0: 0d b8 00 00 22 10 34 12 08 00 03 a8 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 ff ff ff ff 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:05.0 PCI bridge [0604]: Advanced Micro Devices [AMD] RS780 PCI to PCI bridge (PCIE port 1) [1022:9605] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=04, subordinate=04, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: f0300000-f03fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #2, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #5, PowerLimit 25.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Not Supported, TimeoutDis- ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0300c Data: 4171 Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] Device [1022:1234] Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [110 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Kernel driver in use: pcieport 00: 22 10 05 96 07 04 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 04 04 00 f1 01 00 20 20: 30 f0 30 f0 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 03 c8 00 00 00 00 10 a0 42 01 20 80 00 00 60: 10 08 00 00 12 0c 30 02 40 00 11 70 80 0c 2c 00 70: 00 00 48 01 00 00 01 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 42 00 01 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 b0 01 00 0c 30 e0 fe 71 41 00 00 00 00 00 00 b0: 0d b8 00 00 22 10 34 12 08 00 03 a8 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 ff ff ff ff 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:06.0 PCI bridge [0604]: Advanced Micro Devices [AMD] RS780 PCI to PCI bridge (PCIE port 2) [1022:9606] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=05, subordinate=05, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: f0200000-f02fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #3, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #6, PowerLimit 25.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Not Supported, TimeoutDis- ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0300c Data: 4179 Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] Device [1022:1234] Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [110 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Kernel driver in use: pcieport 00: 22 10 06 96 07 04 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 05 05 00 f1 01 00 20 20: 20 f0 20 f0 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 03 c8 00 00 00 00 10 a0 42 01 20 80 00 00 60: 10 08 00 00 12 0c 30 03 40 00 11 70 80 0c 34 00 70: 00 00 48 01 00 00 01 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 42 00 01 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 b0 01 00 0c 30 e0 fe 79 41 00 00 00 00 00 00 b0: 0d b8 00 00 22 10 34 12 08 00 03 a8 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 ff ff ff ff 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:07.0 PCI bridge [0604]: Advanced Micro Devices [AMD] RS780 PCI to PCI bridge (PCIE port 3) [1022:9607] (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Bus: primary=00, secondary=06, subordinate=06, sec-latency=0 I/O behind bridge: 0000f000-00000fff Memory behind bridge: f0100000-f01fffff Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #4, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep+ BwNot+ LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt+ SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- Slot #7, PowerLimit 25.000W; Interlock- NoCompl+ SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- Changed: MRL- PresDet+ LinkState+ RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- DevCap2: Completion Timeout: Not Supported, TimeoutDis- ARIFwd- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- ARIFwd- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -3.5dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit- Address: fee0300c Data: 4181 Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] Device [1022:1234] Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [110 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Kernel driver in use: pcieport 00: 22 10 07 96 07 04 10 00 00 00 04 06 10 00 01 00 10: 00 00 00 00 00 00 00 00 00 06 06 00 f1 01 00 20 20: 10 f0 10 f0 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 03 c8 00 00 00 00 10 a0 42 01 20 80 00 00 60: 10 08 00 00 12 0c 30 04 43 00 12 f0 80 0c 3c 00 70: 00 00 48 01 00 00 01 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 42 00 01 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 b0 01 00 0c 30 e0 fe 81 41 00 00 00 00 00 00 b0: 0d b8 00 00 22 10 34 12 08 00 03 a8 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 ff ff ff ff 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:11.0 SATA controller [0106]: ATI Technologies Inc SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] [1002:4391] (prog-if 01 [AHCI 1.0]) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 19 Region 0: I/O ports at 5038 [size=8] Region 1: I/O ports at 504c [size=4] Region 2: I/O ports at 5030 [size=8] Region 3: I/O ports at 5048 [size=4] Region 4: I/O ports at 5010 [size=16] Region 5: Memory at f070a000 (32-bit, non-prefetchable) [size=1K] Capabilities: [70] SATA HBA v1.0 InCfgSpace Capabilities: [a4] PCI Advanced Features AFCap: TP+ FLR+ AFCtrl: FLR- AFStatus: TP- Kernel driver in use: ahci 00: 02 10 91 43 07 00 30 02 00 01 06 01 10 40 00 00 10: 39 50 00 00 4d 50 00 00 31 50 00 00 49 50 00 00 20: 11 50 00 00 00 a0 70 f0 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 70 00 00 00 00 00 00 00 0b 01 00 00 40: 14 80 b5 00 01 00 20 00 00 00 80 00 00 00 00 00 50: 05 70 84 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 01 50 22 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 12 a4 10 00 0f 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 06 16 14 00 ab 01 08 00 f0 00 00 00 90: 27 60 74 c7 02 45 06 00 08 01 00 00 01 58 11 00 a0: 0c 00 00 00 13 00 06 03 00 00 64 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 20 00 00 e0: 80 00 00 00 00 00 00 00 00 00 00 00 10 00 00 3f f0: 00 00 00 00 00 00 00 00 77 77 77 00 00 00 00 00 00:12.0 USB Controller [0c03]: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397] (prog-if 10 [OHCI]) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 18 Region 0: Memory at f0709000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci_hcd 00: 02 10 97 43 17 00 a0 02 00 10 03 0c 10 40 80 00 10: 00 90 70 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 01 00 00 40: 80 01 00 f0 11 00 00 00 00 00 00 00 00 00 00 00 50: 40 00 00 f0 00 00 00 00 ff ff ff ff 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 ff 00 00 80 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 10 01 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:12.2 USB Controller [0c03]: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396] (prog-if 20 [EHCI]) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin B routed to IRQ 17 Region 0: Memory at f0708000 (32-bit, non-prefetchable) [size=256] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME+ Bridge: PM- B3+ Capabilities: [e4] Debug port: BAR=1 offset=00e0 Kernel driver in use: ehci_hcd 00: 02 10 96 43 17 00 b0 02 00 20 03 0c 10 40 00 00 10: 00 80 70 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 c0 00 00 00 00 00 00 00 05 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 40 21 80 a0 01 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 20 00 00 01 00 00 00 00 00 00 00 00 a0: 01 00 00 01 00 00 08 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 e4 02 7e 00 80 40 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 0a 00 e0 20 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:13.0 USB Controller [0c03]: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397] (prog-if 10 [OHCI]) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 18 Region 0: Memory at f0707000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci_hcd 00: 02 10 97 43 17 00 a0 02 00 10 03 0c 10 40 80 00 10: 00 70 70 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 01 00 00 40: 80 01 00 f0 11 00 00 00 00 00 00 00 00 00 00 00 50: 40 00 00 f0 00 00 00 00 ff ff ff ff 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 ff 00 00 80 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 10 01 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:13.2 USB Controller [0c03]: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396] (prog-if 20 [EHCI]) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin B routed to IRQ 17 Region 0: Memory at f0706000 (32-bit, non-prefetchable) [size=256] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME+ Bridge: PM- B3+ Capabilities: [e4] Debug port: BAR=1 offset=00e0 Kernel driver in use: ehci_hcd 00: 02 10 96 43 17 00 b0 02 00 20 03 0c 10 40 00 00 10: 00 60 70 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 c0 00 00 00 00 00 00 00 05 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 40 21 80 a0 01 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 20 00 00 01 00 00 00 00 00 00 00 00 a0: 01 00 00 01 00 00 08 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 e4 02 7e 00 80 40 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 0a 00 e0 20 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.0 SMBus [0c05]: ATI Technologies Inc SBx00 SMBus Controller [1002:4385] (rev 42) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Kernel driver in use: piix4_smbus 00: 02 10 85 43 03 04 20 02 42 00 05 0c 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.2 Audio device [0403]: ATI Technologies Inc SBx00 Azalia (Intel HDA) [1002:4383] (rev 40) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=slow >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 16 Region 0: Memory at f0700000 (64-bit, non-prefetchable) [size=16K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=55mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: HDA Intel 00: 02 10 83 43 06 00 10 04 40 00 03 04 10 40 00 00 10: 04 00 70 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 50 00 00 00 00 00 00 00 07 01 00 00 40: 00 00 02 00 01 10 00 00 00 00 00 00 01 00 00 00 50: 01 00 42 c8 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.3 ISA bridge [0601]: ATI Technologies Inc SB7x0/SB8x0/SB9x0 LPC host controller [1002:439d] (rev 40) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 00: 02 10 9d 43 0f 00 20 02 40 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 04 00 00 00 d5 ff 03 ff 07 ff 20 01 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 0e 68 00 00 00 0f 00 e0 ff ff ff 70: 67 45 23 00 04 00 00 00 1c 00 00 00 05 0a 00 00 80: 08 00 03 a8 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 10 d6 fe a0: 02 00 c1 fe 2e 01 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 09 39 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.4 PCI bridge [0604]: ATI Technologies Inc SBx00 PCI to PCI Bridge [1002:4384] (rev 40) (prog-if 01 [Subtractive decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 Bus: primary=00, secondary=07, subordinate=07, sec-latency=64 I/O behind bridge: 0000f000-00000fff Memory behind bridge: fff00000-000fffff Prefetchable memory behind bridge: fff00000-000fffff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- 00: 02 10 84 43 07 01 a0 02 40 01 04 06 00 40 81 00 10: 00 00 00 00 00 00 00 00 00 07 07 40 f0 00 80 22 20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 40: 26 00 00 ff 00 00 00 00 0c 0f 3c d1 00 00 00 00 50: 01 00 00 00 08 00 03 a8 00 00 00 00 85 00 ff ff 60: ca 0e 17 00 ba 98 10 02 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 02 06 e0: 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:16.0 USB Controller [0c03]: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB OHCI0 Controller [1002:4397] (prog-if 10 [OHCI]) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 18 Region 0: Memory at f0705000 (32-bit, non-prefetchable) [size=4K] Kernel driver in use: ohci_hcd 00: 02 10 97 43 17 00 a0 02 00 10 03 0c 10 40 80 00 10: 00 50 70 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 01 00 00 40: 80 01 00 f0 11 00 00 00 00 00 00 00 00 00 00 00 50: 40 00 00 f0 00 00 00 00 ff ff ff ff 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 ff 00 00 80 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 10 01 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:16.2 USB Controller [0c03]: ATI Technologies Inc SB7x0/SB8x0/SB9x0 USB EHCI Controller [1002:4396] (prog-if 20 [EHCI]) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin B routed to IRQ 17 Region 0: Memory at f0704000 (32-bit, non-prefetchable) [size=256] Capabilities: [c0] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Bridge: PM- B3+ Capabilities: [e4] Debug port: BAR=1 offset=00e0 Kernel driver in use: ehci_hcd 00: 02 10 96 43 17 00 b0 02 00 20 03 0c 10 40 00 00 10: 00 40 70 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 c0 00 00 00 00 00 00 00 05 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 40 21 80 a0 01 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 20 00 00 01 00 00 00 00 00 00 00 00 a0: 01 00 00 01 00 00 08 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 e4 02 7e 00 00 40 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 0a 00 e0 20 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor HyperTransport Configuration [1022:1200] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn+ ExtCTL- 64b+ Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=8bit DwFcInEn- LWO=8bit DwFcOutEn- Revision ID: 3.00 Link Frequency: [a] Link Error: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz+ 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC+ LDTSTOP+ CRCTM- ECTLT- 64bA+ UIDRD- ExtRS- UCnfE- 00: 22 10 00 12 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 01 02 04 00 01 02 04 00 01 02 04 00 01 02 04 00 50: 01 02 04 00 01 02 04 00 01 02 04 00 01 02 04 00 60: 00 00 01 00 e0 00 00 00 20 a8 2e 01 10 fe 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 00 01 21 20 a0 11 00 60 0a f5 87 13 00 00 00 90: d0 02 85 80 00 00 00 00 07 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.1 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor Address Map [1022:1201] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 01 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 03 00 00 00 00 00 2f 01 00 00 00 00 01 00 00 00 50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00 60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00 70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00 80: 03 00 d0 00 80 ff df 00 03 00 e0 00 00 4f f0 00 90: 03 50 f0 00 80 6f f0 00 03 70 f0 00 00 ff f7 00 a0: 03 00 f8 00 80 ff fb 00 03 00 fc 00 00 bf fe 00 b0: 03 c0 fe 00 80 fe ff 00 03 ff ff 00 00 ff ff 00 c0: 13 00 00 00 00 f0 ff 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 03 00 00 1f 00 00 00 00 00 00 00 00 00 00 00 00 f0: 03 30 00 d0 01 00 00 00 00 00 00 00 00 00 00 00 00:18.2 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor DRAM Controller [1022:1202] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 02 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 04 00 00 0a 00 00 00 00 80: 00 00 00 00 04 00 00 00 00 00 00 ff 00 00 00 00 90: 00 00 01 08 00 41 08 00 0a 00 00 80 e7 88 71 0e a0: 00 02 00 00 00 00 00 00 00 00 01 00 00 00 00 00 b0: 5c 6b 78 84 6b 00 00 00 80 2e f0 07 01 f8 80 36 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: ef 00 10 fb 1f 97 3b 17 fd 00 00 21 33 02 e0 02 e0: 54 7c c4 f1 02 02 a0 f8 1c 01 f0 7d ff 57 26 9b f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.3 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor Miscellaneous Control [1022:1203] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [f0] Secure device <?> Kernel driver in use: k10temp 00: 22 10 03 12 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 00 40: ff ff ff 3f 5c 00 b0 4a 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 05 00 73 3a c0 00 00 30 51 80 01 60 70: 51 11 32 60 01 01 98 00 14 0c 20 00 11 08 07 00 80: 81 f6 0b e6 e6 41 e6 01 08 00 00 00 00 60 58 02 90: 43 00 00 00 60 00 00 00 00 18 18 01 00 00 00 00 a0: a9 0a 19 b0 ef 0f 68 39 70 07 04 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 c6 10 04 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 25 0f 81 c8 15 07 3b 03 45 54 27 70 e0: 00 00 00 00 30 06 40 01 41 5f 07 00 00 00 00 00 f0: 0f 00 10 00 00 00 00 00 00 00 00 00 63 0f 10 00 00:18.4 Host bridge [0600]: Advanced Micro Devices [AMD] Family 10h Processor Link Control [1022:1204] Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 04 12 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:05.0 VGA compatible controller [0300]: ATI Technologies Inc M880G [Mobility Radeon HD 4200] [1002:9712] (prog-if 00 [VGA controller]) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 18 Region 0: Memory at d0000000 (32-bit, prefetchable) [size=256M] Region 1: I/O ports at 4000 [size=256] Region 2: Memory at f0600000 (32-bit, non-prefetchable) [size=64K] Region 5: Memory at f0500000 (32-bit, non-prefetchable) [size=1M] Expansion ROM at <unassigned> [disabled] Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Kernel driver in use: fglrx_pci 00: 02 10 12 97 07 00 10 00 00 00 00 03 10 00 80 00 10: 08 00 00 d0 01 40 00 00 00 00 60 f0 00 00 00 00 20: 00 00 00 00 00 00 50 f0 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 50: 01 a0 03 06 00 00 00 00 10 a0 12 00 a0 8f 00 00 60: 10 08 0a 00 01 0d 00 00 00 00 01 11 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 01 00 01 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:05.1 Audio device [0403]: ATI Technologies Inc RS880 Audio Device [Radeon HD 4200] [1002:970f] Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin B routed to IRQ 19 Region 0: Memory at f0610000 (32-bit, non-prefetchable) [size=16K] Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Kernel driver in use: HDA Intel 00: 02 10 0f 97 07 00 10 00 00 00 03 04 10 00 80 00 10: 00 00 61 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 50: 01 a0 03 06 00 00 00 00 10 a0 12 00 a0 8f 00 00 60: 10 08 0a 00 01 0d 00 00 00 00 01 11 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02:00.0 VGA compatible controller [0300]: ATI Technologies Inc NI Whistler [AMD Radeon HD 6600M Series] [1002:6741] (prog-if 00 [VGA controller]) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 49 Region 0: Memory at e0000000 (64-bit, prefetchable) [size=256M] Region 2: Memory at f0400000 (64-bit, non-prefetchable) [size=128K] Region 4: I/O ports at 3000 [size=256] [virtual] Expansion ROM at f0420000 [disabled] [size=128K] Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Express (v2) Legacy Endpoint, MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <4us, L1 unlimited ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #1, Speed 5GT/s, Width x16, ASPM L0s L1, Latency L0 <64ns, L1 <1us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+ Address: 00000000fee0300c Data: 41a9 Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Capabilities: [150 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap+ ChkEn- Kernel driver in use: fglrx_pci 00: 02 10 41 67 07 04 10 00 00 00 00 03 10 00 00 00 10: 0c 00 00 e0 00 00 00 00 04 00 40 f0 00 00 00 00 20: 01 30 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 50: 01 58 03 06 00 00 00 00 10 a0 12 00 a1 8f 2c 01 60: 10 29 00 00 02 0d 00 01 43 00 82 10 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 02 00 01 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 00 81 00 0c 30 e0 fe 00 00 00 00 a9 41 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168] (rev 06) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 45 Region 0: I/O ports at 2000 [size=256] Region 2: Memory at f0004000 (64-bit, prefetchable) [size=4K] Region 4: Memory at f0000000 (64-bit, prefetchable) [size=16K] Capabilities: [40] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+ Address: 00000000fee0300c Data: 4189 Capabilities: [70] Express (v2) Endpoint, MSI 01 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 4096 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <64us ClockPM+ Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [b0] MSI-X: Enable- Count=4 Masked- Vector table: BAR=4 offset=00000000 PBA: BAR=4 offset=00000800 Capabilities: [d0] Vital Product Data Unknown small resource type 00, will not decode more. Capabilities: [100 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr+ BadTLP- BadDLLP+ Rollover- Timeout- NonFatalErr+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn- Capabilities: [140 v1] Virtual Channel Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 Arb: Fixed- WRR32- WRR64- WRR128- Ctrl: ArbSelect=Fixed Status: InProgress- VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256- Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff Status: NegoPending- InProgress- Capabilities: [160 v1] Device Serial Number 01-00-00-00-68-4c-e0-00 Kernel driver in use: r8169 00: ec 10 68 81 07 04 10 00 06 00 00 02 10 00 00 00 10: 01 20 00 00 00 00 00 00 0c 40 00 f0 00 00 00 00 20: 0c 00 00 f0 00 00 00 00 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 40 00 00 00 00 00 00 00 07 01 00 00 40: 01 50 c3 ff 08 00 00 00 00 00 00 00 00 00 00 00 50: 05 70 81 00 0c 30 e0 fe 00 00 00 00 89 41 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 10 b0 02 02 c1 8c 64 00 10 50 19 00 11 3c 07 00 80: 40 00 11 10 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 11 d0 03 00 04 00 00 00 04 08 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 03 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 04:00.0 Network controller [0280]: Ralink corp. Device [1814:539f] Subsystem: Hewlett-Packard Company Device [103c:1637] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 17 Region 0: Memory at f0300000 (32-bit, non-prefetchable) [size=64K] Capabilities: [40] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable- Count=1/32 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [70] Express (v2) Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 unlimited ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <64us ClockPM+ Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis+ LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [100 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ CEMsk: RxErr+ BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn- Capabilities: [140 v1] Device Serial Number 00-00-5a-8a-65-4e-00-90 Kernel driver in use: rt5390 00: 14 18 9f 53 07 00 10 00 00 00 80 02 10 00 00 00 10: 00 00 30 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 37 16 30: 00 00 00 00 40 00 00 00 00 00 00 00 05 01 00 00 40: 01 50 c3 01 00 00 00 00 00 00 00 00 00 00 00 00 50: 05 70 8a 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 10 00 02 00 c0 8e 64 00 10 20 09 00 11 3c 07 00 80: 40 00 11 10 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 10 00 00 00 10 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 05:00.0 Unassigned class [ff00]: Realtek Semiconductor Co., Ltd. Device [10ec:5209] (rev 01) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 18 Region 0: Memory at f0200000 (32-bit, non-prefetchable) [size=4K] Capabilities: [40] Power Management version 3 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [70] Express (v2) Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <1us, L1 <8us ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 unlimited, L1 <64us ClockPM+ Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB Capabilities: [100 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout+ NonFatalErr+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn- Capabilities: [140 v1] Device Serial Number 00-00-00-01-00-4c-e0-00 Kernel driver in use: rts_pstor 00: ec 10 09 52 07 00 10 00 01 00 00 ff 10 00 00 00 10: 00 00 20 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 01 00 00 40: 01 50 c3 77 00 00 00 00 00 00 00 00 00 00 00 00 50: 05 70 80 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 10 00 02 00 00 87 64 00 10 20 09 00 11 7c 07 00 80: 00 01 11 10 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 10 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 06:00.0 USB Controller [0c03]: NEC Corporation uPD720200 USB 3.0 Host Controller [1033:0194] (rev 04) (prog-if 30 [XHCI]) Subsystem: Hewlett-Packard Company Device [103c:164b] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 19 Region 0: Memory at f0100000 (64-bit, non-prefetchable) [size=8K] Capabilities: [50] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [70] MSI: Enable- Count=1/8 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [90] MSI-X: Enable+ Count=8 Masked- Vector table: BAR=0 offset=00001000 PBA: BAR=0 offset=00001080 Capabilities: [a0] Express (v2) Endpoint, MSI 00 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend- LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <4us, L1 unlimited ClockPM+ Surprise- LLActRep- BwNot- LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt- LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Not Supported, TimeoutDis+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -3.5dB Capabilities: [100 v1] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- Capabilities: [140 v1] Device Serial Number ff-ff-ff-ff-ff-ff-ff-ff Capabilities: [150 v1] #18 Kernel driver in use: xhci_hcd 00: 33 10 94 01 06 04 10 00 04 30 03 0c 10 00 00 00 10: 04 00 10 f0 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 3c 10 4b 16 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 70 c3 c9 08 00 00 00 00 00 00 00 00 00 00 00 60: 30 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 05 90 86 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 11 a0 07 80 00 10 00 00 80 10 00 00 00 00 00 00 a0: 10 00 02 00 c0 8f 00 00 00 28 19 00 12 ec 07 00 b0: 43 01 12 10 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 10 08 00 00 00 00 00 00 00 00 00 00 d0: 02 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: fc 1f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 08 14 60 00 00 00 00 00 00 00 00 00 00 00 00 00 # superiotool -deV superiotool r6637 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0x0001, id=0x1885 Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0x0001, id=0x1885 Probing for ITE Super I/O (init=standard) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0x8518, rev=0x2 Probing for ITE Super I/O (init=it8502e) at 0x4e... Failed. Returned data: id=0x8518, rev=0x2 Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0x8518, rev=0x2 Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0x8518, rev=0x2 Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0x8518, rev=0x2 Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: sid=0x85, srid=0x00 Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x164e... Failed. Returned data: port=0xff, port+1=0xff Probing for Nuvoton Super I/O at 0x164e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x2e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x4e... Failed. Returned data: chip_id=0x8518 Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e... Failed. Returned data: sid=0x85, id=0x8518, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Found SMSC SCH5317 (id=0x85, rev=0x18) at 0x4e No dump available for this Super I/O No extra registers known for this chip. Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0x85/0x00, rev=0x18 Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0x85/0x00, rev=0x18 Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0x85/0x00, rev=0x18 Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0x85/0x00, rev=0x18 Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for VIA Super I/O at 0x3f0... PCI device 1106:0686 not found. Probing for Server Engines Super I/O at 0x2e... Failed. Returned data: id=0xffff, rev=0xff # dmidecode # dmidecode 2.9 SMBIOS 2.6 present. 23 structures occupying 1205 bytes. Table at 0x000E3EE0. Handle 0x0000, DMI type 4, 42 bytes Processor Information Socket Designation: Socket S1G4 Type: Central Processor Family: <OUT OF SPEC> Manufacturer: AMD processor ID: 63 0F 10 00 FF FB 8B 17 Version: AMD Phenom(tm) II N660 Dual-Core Processor Voltage: 1.2 V External Clock: 200 MHz Max Speed: 3000 MHz Current Speed: 3000 MHz Status: Populated, Enabled Upgrade: <OUT OF SPEC> L1 Cache Handle: 0x0001 L2 Cache Handle: 0x0002 L3 Cache Handle: Not Provided Serial Number: NotSupport Asset Tag: FFFF Part Number: FFFF Core Count: 2 Core Enabled: 2 Thread Count: 2 Characteristics: 64-bit capable Handle 0x0001, DMI type 7, 19 bytes Cache Information Socket Designation: L1 Cache Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Write Back Location: Internal Installed Size: 256 KB Maximum Size: 256 KB Supported SRAM Types: Synchronous Installed SRAM Type: Synchronous Speed: Unknown Error Correction Type: Multi-bit ECC System Type: Unified Associativity: 2-way Set-associative Handle 0x0002, DMI type 7, 19 bytes Cache Information Socket Designation: L2 Cache Configuration: Enabled, Not Socketed, Level 2 Operational Mode: Write Back Location: Internal Installed Size: 2048 KB Maximum Size: 2048 KB Supported SRAM Types: Synchronous Installed SRAM Type: Synchronous Speed: Unknown Error Correction Type: Multi-bit ECC System Type: Unified Associativity: 16-way Set-associative Handle 0x0003, DMI type 0, 24 bytes BIOS Information Vendor: Hewlett-Packard Version: F.20 Release Date: 07/13/2011 ROM Size: 2048 kB Characteristics: PCI is supported BIOS is upgradeable BIOS shadowing is allowed Boot from CD is supported Selectable boot is supported BIOS ROM is socketed EDD is supported Japanese floppy for NEC 9800 1.2 MB is supported (int 13h) Japanese floppy for Toshiba 1.2 MB is supported (int 13h) 5.25"/360 KB floppy services are supported (int 13h) 5.25"/1.2 MB floppy services are supported (int 13h) 3.5"/720 KB floppy services are supported (int 13h) 3.5"/2.88 MB floppy services are supported (int 13h) 8042 keyboard services are supported (int 9h) CGA/mono video services are supported (int 10h) ACPI is supported USB legacy is supported Targeted content distribution is supported BIOS Revision: 15.32 Firmware Revision: 6.31 Handle 0x0004, DMI type 1, 27 bytes System Information Manufacturer: Hewlett-Packard Product Name: HP Pavilion dv6 Notebook PC Version: 0596100000244710000010100 Serial Number: 5CH1110E5K UUID: 4D7AD3D7-B40F-9D31-5273-68B599DFAFB0 Wake-up Type: Power Switch SKU Number: LK971EA#ACB Family: 103C_5335KV G=N L=CON B=HP S=PAV Handle 0x0005, DMI type 2, 16 bytes Base Board Information Manufacturer: Hewlett-Packard Product Name: 164B Version: 06.1F Serial Number: PBUME05HT031Y8 Asset Tag: Base Board Asset Tag Features: Board is a hosting board Board is replaceable Location In Chassis: Base Board Chassis Location Chassis Handle: 0x0006 Type: Motherboard Contained Object Handles: 0 Handle 0x0006, DMI type 3, 22 bytes Chassis Information Manufacturer: Hewlett-Packard Type: Notebook Lock: Not Present Version: Chassis Version Serial Number: Chassis Serial Number Asset Tag: Chassis Asset Tag Boot-up State: Safe Power Supply State: Safe Thermal State: Safe Security Status: None OEM Information: 0x00000147 Height: Unspecified Number Of Power Cords: 1 Contained Elements: 0 Handle 0x0007, DMI type 9, 17 bytes System Slot Information Designation: CN_WLAN1 Type: x1 <OUT OF SPEC> Current Usage: Available Length: Short Characteristics: 3.3 V is provided Handle 0x0008, DMI type 11, 5 bytes OEM Strings String 1: $HP$ String 2: LOC# String 3: ABS 70/71 78 79 7A 7B String 4: CNB1 0596100000244710000010100 String 5: HP_Mute_LED_0_0 Handle 0x0009, DMI type 22, 26 bytes Portable Battery Location: Primary Manufacturer: 13DP-SDI Name: MU06055 Chemistry: Lithium Ion Design Capacity: 165240 mWh Design Voltage: 10800 mV SBDS Version: 1.1 Maximum Error: 0% SBDS Serial Number: 6ABA SBDS Manufacture Date: 2011-01-31 OEM-specific Information: 0x0000FFFF Handle 0x000A, DMI type 32, 20 bytes System Boot Information Status: No errors detected Handle 0x000B, DMI type 41, 11 bytes Unknown Type Header and Data: 29 0B 0B 00 01 83 01 00 00 01 28 Strings: ATI iGPU Handle 0x000C, DMI type 16, 15 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: None Maximum Capacity: 16 GB Error Information Handle: No Error Number Of Devices: 2 Handle 0x000D, DMI type 17, 28 bytes Memory Device Array Handle: 0x000C Error Information Handle: Not Provided Total Width: Unknown Data Width: Unknown Size: No Module Installed Form Factor: DIMM Set: None Locator: DIMM1 Bank Locator: BANK0 Type: <OUT OF SPEC> Type Detail: None Speed: Unknown Manufacturer: Not Specified Serial Number: Not Specified Asset Tag: Unknown Part Number: Not Specified Handle 0x000E, DMI type 17, 28 bytes Memory Device Array Handle: 0x000C Error Information Handle: 0x000F Total Width: 64 bits Data Width: 8 bits Size: 4096 MB Form Factor: DIMM Set: None Locator: DIMM2 Bank Locator: BANK0 Type: <OUT OF SPEC> Type Detail: Synchronous Speed: 1333 MHz (0.8 ns) Manufacturer: Micron Technology Serial Number: 3313A3F8 Asset Tag: Unknown Part Number: 16JSF51264HZ-1G4D1 Handle 0x000F, DMI type 18, 23 bytes 32-bit Memory Error Information Type: OK Granularity: Unknown Operation: Unknown Vendor Syndrome: Unknown Memory Array Address: Unknown Device Address: Unknown Resolution: Unknown Handle 0x0010, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00000000000 Ending Address: 0x000FFFFFFFF Range Size: 4 GB Physical Device Handle: 0x000E Memory Array Mapped Address Handle: 0x0012 Partition Row Position: 1 Handle 0x0011, DMI type 18, 23 bytes 32-bit Memory Error Information Type: OK Granularity: Unknown Operation: Unknown Vendor Syndrome: Unknown Memory Array Address: Unknown Device Address: Unknown Resolution: Unknown Handle 0x0012, DMI type 19, 15 bytes Memory Array Mapped Address Starting Address: 0x00000000000 Ending Address: 0x000FFFFFFFF Range Size: 4 GB Physical Array Handle: 0x000C Partition Width: 0 Handle 0x0013, DMI type 41, 11 bytes Unknown Type Header and Data: 29 0B 13 00 01 83 01 00 00 02 00 Strings: ATI Whistler PRO Handle 0x0014, DMI type 41, 11 bytes Unknown Type Header and Data: 29 0B 14 00 01 85 01 00 00 03 00 Strings: Realtek Lan Controller Handle 0x0015, DMI type 41, 11 bytes Unknown Type Header and Data: 29 0B 15 00 01 81 01 00 00 04 00 Strings: Ralink 5390BC8 802.11bgn/BT combo Adapter Handle 0x0016, DMI type 127, 4 bytes End Of Table # biosdecode # biosdecode 2.9 ACPI 2.0 present. OEM Identifier: HPQOEM RSD Table 32-bit Address: 0xCFEF50AC XSD Table 64-bit Address: 0x00000000CFEF5120 PNP BIOS 1.0 present. Event Notification: Not Supported Real Mode 16-bit Code Address: F000:B891 Real Mode 16-bit Data Address: 0040:0000 16-bit Protected Mode Code Address: 0x000FB89C 16-bit Protected Mode Data Address: 0x00000400 OEM Device Identifier: SST2400 SMBIOS 2.6 present. Structure Table Length: 1205 bytes Structure Table Address: 0x000E3EE0 Number Of Structures: 23 Maximum Structure Size: 162 bytes BIOS32 Service Directory present. Revision: 0 Calling Interface Address: 0x000EF735 PCI Interrupt Routing 1.0 present. Router ID: 00:14.0 Exclusive IRQs: None Compatible Router: 1002:4385 Slot Entry 1: ID 00:11, on-board Slot Entry 2: ID 00:12, on-board Slot Entry 3: ID 00:13, on-board Slot Entry 4: ID 00:16, on-board Slot Entry 5: ID 00:14, on-board Slot Entry 6: ID 00:15, on-board Slot Entry 7: ID 01:05, on-board Slot Entry 8: ID ff:00, slot number 1 Slot Entry 9: ID 03:00, slot number 2 Slot Entry 10: ID 04:00, slot number 3 Slot Entry 11: ID 05:00, slot number 4 Slot Entry 12: ID 06:00, slot number 5 Slot Entry 13: ID ff:00, slot number 6 Slot Entry 14: ID ff:00, slot number 7 Slot Entry 15: ID 07:04, slot number 8 Slot Entry 16: ID 07:05, slot number 8 Slot Entry 17: ID 07:06, slot number 9 Slot Entry 18: ID 07:07, slot number 10 Slot Entry 19: ID ff:00, slot number 11 Slot Entry 20: ID ff:00, slot number 12 Slot Entry 21: ID ff:00, slot number 13 Slot Entry 22: ID ff:00, slot number 14 Installed BIOS version is F.20 07/13/2011. It can be found at http://ftp.hp.com/pub/softpaq/sp54001-54500/sp54025.exe

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Re: [flashrom] Initial version of autotools support for Flashrom
by Carl-Daniel Hailfinger 14 Aug '11

14 Aug '11

Am 14.08.2011 09:58 schrieb Peter Lemenkov: > 2011/8/14 Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>: > >> Hi Peter, >> >> thanks for your patch. >> I think your code looks clean. >> It does not work, though: >> > Yes, I forgot to add bootstrap script, which regenerates all necessary > files. You may invoke the following sequence of commands or simply run > autoreconf -ivf : > > aclocal --force > autoconf --force > autoheader --force > automake --add-missing --copy --force-missing > Thanks, it seems to work now. Cosmetic comment: configure is awfully verbose by default, though. Is it possible to silence it without specifying -q manually? We don't want to flood users with useless messages. Bug: configure checks for the presence of MacOSX/SunOS headers under Linux. Does this work on the oldest supported RHEL and the oldest supported SLES (SLES 8)? We have users on those platforms, and at least SLES 8 still has a 2.4 kernel. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[PATCH] [1/n] SPI FAST READ infrastructure
by Carl-Daniel Hailfinger 14 Aug '11

14 Aug '11

SPI FAST READ infrastructure. Add feature bits to allow annotation of SPI flash chips with possible read methods. This includes the not-yet-supported Dual and Quad I/O read operations just in case we ever encounter programmer hardware which can use that feature. An alternative design would be to create a separate spi_chip_fast_read function and have a per-chip array of allowable read functions similar to what we have for erase functions. A similar design problem exists for chips supporting multiple write functions (e.g. classic SPI write and SPI AAI write). Thorough design review appreciated. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_fast_read/flash.h =================================================================== --- flashrom-spi_fast_read/flash.h (Revision 1249) +++ flashrom-spi_fast_read/flash.h (Arbeitskopie) @@ -92,6 +92,11 @@ #define FEATURE_WRSR_EWSR (1 << 6) #define FEATURE_WRSR_WREN (1 << 7) #define FEATURE_WRSR_EITHER (FEATURE_WRSR_EWSR | FEATURE_WRSR_WREN) +#define FEATURE_SPI_FAST_READ (1 << 8) +#define FEATURE_SPI_FAST_READ_DUAL_O (1 << 9) +#define FEATURE_SPI_FAST_READ_DUAL_IO (1 << 10) +#define FEATURE_SPI_FAST_READ_QUAD_O (1 << 11) +#define FEATURE_SPI_FAST_READ_QUAD_IO (1 << 12) struct flashchip { const char *vendor; Index: flashrom-spi_fast_read/dediprog.c =================================================================== --- flashrom-spi_fast_read/dediprog.c (Revision 1249) +++ flashrom-spi_fast_read/dediprog.c (Arbeitskopie) @@ -220,8 +220,15 @@ /* Round down. */ bulklen = (len - residue) / chunksize * chunksize; - ret = dediprog_spi_bulk_read(flash, buf + residue, start + residue, - bulklen); + if (flash->feature_bits & FEATURE_SPI_FAST_READ) { + ret = dediprog_spi_bulk_read(flash, buf + residue, + start + residue, bulklen); + } else { + msg_pdbg("Using slow read because your flash chip is not " + "listed as supporting fast read (yet).\n"); + ret = spi_read_chunked(flash, buf + residue, start + residue, + bulklen, 16); + } if (ret) return ret; Index: flashrom-spi_fast_read/flashchips.c =================================================================== --- flashrom-spi_fast_read/flashchips.c (Revision 1249) +++ flashrom-spi_fast_read/flashchips.c (Arbeitskopie) @@ -282,6 +282,7 @@ .model_id = AMIC_A25L05PT, .total_size = 64, .page_size = 256, + .feature_bits = FEATURE_SPI_FAST_READ | FEATURE_SPI_FAST_READ_DUAL_O | FEATURE_SPI_FAST_READ_DUAL_IO, .tested = TEST_UNTESTED, .probe = probe_spi_rdid4, .probe_timing = TIMING_ZERO, @@ -313,6 +314,7 @@ .model_id = AMIC_A25L05PU, .total_size = 64, .page_size = 256, + .feature_bits = FEATURE_SPI_FAST_READ | FEATURE_SPI_FAST_READ_DUAL_O | FEATURE_SPI_FAST_READ_DUAL_IO, .tested = TEST_UNTESTED, .probe = probe_spi_rdid4, .probe_timing = TIMING_ZERO, @@ -344,6 +346,7 @@ .model_id = AMIC_A25L10PT, .total_size = 128, .page_size = 256, + .feature_bits = FEATURE_SPI_FAST_READ | FEATURE_SPI_FAST_READ_DUAL_O | FEATURE_SPI_FAST_READ_DUAL_IO, .tested = TEST_UNTESTED, .probe = probe_spi_rdid4, .probe_timing = TIMING_ZERO, @@ -376,6 +379,7 @@ .model_id = AMIC_A25L10PU, .total_size = 128, .page_size = 256, + .feature_bits = FEATURE_SPI_FAST_READ | FEATURE_SPI_FAST_READ_DUAL_O | FEATURE_SPI_FAST_READ_DUAL_IO, .tested = TEST_UNTESTED, .probe = probe_spi_rdid4, .probe_timing = TIMING_ZERO, @@ -408,6 +412,7 @@ .model_id = AMIC_A25L20PT, .total_size = 256, .page_size = 256, + .feature_bits = FEATURE_SPI_FAST_READ | FEATURE_SPI_FAST_READ_DUAL_O | FEATURE_SPI_FAST_READ_DUAL_IO, .tested = TEST_UNTESTED, .probe = probe_spi_rdid4, .probe_timing = TIMING_ZERO, @@ -440,6 +445,7 @@ .model_id = AMIC_A25L20PU, .total_size = 256, .page_size = 256, + .feature_bits = FEATURE_SPI_FAST_READ | FEATURE_SPI_FAST_READ_DUAL_O | FEATURE_SPI_FAST_READ_DUAL_IO, .tested = TEST_UNTESTED, .probe = probe_spi_rdid4, .probe_timing = TIMING_ZERO, -- http://www.hailfinger.org/

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Re: [flashrom] Initial version of autotools support for Flashrom
by Carl-Daniel Hailfinger 14 Aug '11

14 Aug '11

Hi Peter, thanks for your patch. Am 13.08.2011 18:23 schrieb Peter Lemenkov: > Some time ago I mentioned that I've got patches for full autotools > support - here is the first patch in a patchset for your further > consideration: > > https://github.com/lemenkov/flashrom/commits/autotools > > It was tested on RHEL 5, 6, Fedora 1x, i386, i586, i686, x86_64 and > ppc (I'm using it for building Flashrom's RPM for a half of the year > at least). > > It's rebased on top of svn1412 and cleaned up to be a full drop-in > replacement for handmade Makefile. Unfortunately I didn't test in on > anything else than Linux, so I must admit that it's not in a very good > shape for MinGW / BSD / DOS / Darwin users (ARM, MIPS users could be > also hurt as well - that's why I didn't touch anything else in this > commit except adding these two files). > I think your code looks clean. It does not work, though: compiler@p35:flashrom-autotools> rm Makefile compiler@p35:flashrom-autotools> make make: *** Keine Targets angegeben und keine »make«-Steuerdatei gefunden. Schluss. (No targets specified, no make control file. Aborting.) compiler@p35:flashrom-autotools> autoconf --version autoconf (GNU Autoconf) 2.65 compiler@p35:flashrom-autotools> automake --version automake (GNU automake) 1.11.1 compiler@p35:flashrom-autotools> automake configure.ac: no proper invocation of AM_INIT_AUTOMAKE was found. configure.ac: You should verify that configure.ac invokes AM_INIT_AUTOMAKE, configure.ac: that aclocal.m4 is present in the top-level directory, configure.ac: and that aclocal.m4 was recently regenerated (using aclocal). configure.ac:5: required file `./config.guess' not found configure.ac:5: `automake --add-missing' can install `config.guess' configure.ac:5: required file `./config.sub' not found configure.ac:5: `automake --add-missing' can install `config.sub' configure.ac:170: required file `./install-sh' not found configure.ac:170: `automake --add-missing' can install `install-sh' Makefile.am:8: HAVE_SYS_UTSNAME does not appear in AM_CONDITIONAL Makefile.am:9: HAVE_UNAME does not appear in AM_CONDITIONAL Makefile.am:14: HAVE_DMIDECODE does not appear in AM_CONDITIONAL Makefile.am:21: HAVE_INTERNAL does not appear in AM_CONDITIONAL Makefile.am:29: HAVE_X86_ONLY_INTERNAL does not appear in AM_CONDITIONAL Makefile.am:41: HAVE_SERPROG does not appear in AM_CONDITIONAL Makefile.am:46: HAVE_RAYER_SPI does not appear in AM_CONDITIONAL Makefile.am:51: HAVE_BITBANG_SPI does not appear in AM_CONDITIONAL Makefile.am:56: HAVE_NIC3COM does not appear in AM_CONDITIONAL Makefile.am:61: HAVE_GFXNVIDIA does not appear in AM_CONDITIONAL Makefile.am:66: HAVE_SATASII does not appear in AM_CONDITIONAL Makefile.am:71: HAVE_ATAHPT does not appear in AM_CONDITIONAL Makefile.am:76: HAVE_FT2232_SPI does not appear in AM_CONDITIONAL Makefile.am:81: HAVE_DUMMY does not appear in AM_CONDITIONAL Makefile.am:86: HAVE_DRKAISER does not appear in AM_CONDITIONAL Makefile.am:91: HAVE_NICREALTEK does not appear in AM_CONDITIONAL Makefile.am:96: HAVE_NICNATSEMI does not appear in AM_CONDITIONAL Makefile.am:101: HAVE_NICINTEL does not appear in AM_CONDITIONAL Makefile.am:106: HAVE_NICINTEL_SPI does not appear in AM_CONDITIONAL Makefile.am:111: HAVE_GFXOGP does not appear in AM_CONDITIONAL Makefile.am:116: HAVE_BUSPIRATE_SPI does not appear in AM_CONDITIONAL Makefile.am:121: HAVE_DEDIPROG does not appear in AM_CONDITIONAL Makefile.am:126: HAVE_SATAMV does not appear in AM_CONDITIONAL Makefile.am:131: HAVE_SERIAL does not appear in AM_CONDITIONAL Makefile.am:135: HAVE_PRINT_WIKI does not appear in AM_CONDITIONAL Makefile.am:140: HAVE_PCI does not appear in AM_CONDITIONAL Makefile.am: required file `./INSTALL' not found Makefile.am: `automake --add-missing' can install `INSTALL' Makefile.am: required file `./NEWS' not found Makefile.am: required file `./AUTHORS' not found Makefile.am: required file `./ChangeLog' not found configure.ac:8: required file `config.h.in' not found Makefile.am: required file `./depcomp' not found Makefile.am: `automake --add-missing' can install `depcomp' /usr/share/automake-1.11/am/depend2.am: am__fastdepCC does not appear in AM_CONDITIONAL /usr/share/automake-1.11/am/depend2.am: The usual way to define `am__fastdepCC' is to add `AC_PROG_CC' /usr/share/automake-1.11/am/depend2.am: to `configure.ac' and run `aclocal' and `autoconf' again. /usr/share/automake-1.11/am/depend2.am: AMDEP does not appear in AM_CONDITIONAL /usr/share/automake-1.11/am/depend2.am: The usual way to define `AMDEP' is to add one of the compiler tests /usr/share/automake-1.11/am/depend2.am: AC_PROG_CC, AC_PROG_CXX, AC_PROG_CXX, AC_PROG_OBJC, /usr/share/automake-1.11/am/depend2.am: AM_PROG_AS, AM_PROG_GCJ, AM_PROG_UPC /usr/share/automake-1.11/am/depend2.am: to `configure.ac' and run `aclocal' and `autoconf' again. compiler@p35:flashrom-autotools> autoconf configure.ac:9: error: possibly undefined macro: AM_INIT_AUTOMAKE If this token and others are legitimate, please use m4_pattern_allow. See the Autoconf documentation. configure.ac:223: error: possibly undefined macro: AM_CONDITIONAL Next try: compiler@p35:flashrom-autotools> aclocal compiler@p35:/sources/tmptrees/ready/flashrom-autotools> autoconf compiler@p35:/sources/tmptrees/ready/flashrom-autotools> automake configure.ac:5: required file `./config.guess' not found configure.ac:5: `automake --add-missing' can install `config.guess' configure.ac:5: required file `./config.sub' not found configure.ac:5: `automake --add-missing' can install `config.sub' configure.ac:9: required file `./install-sh' not found configure.ac:9: `automake --add-missing' can install `install-sh' configure.ac:9: required file `./missing' not found configure.ac:9: `automake --add-missing' can install `missing' configure.ac:8: required file `config.h.in' not found Makefile.am: required file `./depcomp' not found Makefile.am: `automake --add-missing' can install `depcomp' Next try: compiler@p35:flashrom-autotools> automake --add-missing configure.ac:5: installing `./config.guess' configure.ac:5: installing `./config.sub' configure.ac:9: installing `./install-sh' configure.ac:9: installing `./missing' configure.ac:8: required file `config.h.in' not found Makefile.am: installing `./depcomp' compiler@p35:flashrom-autotools> ./configure checking build system type... i686-suse-linux-gnu checking host system type... i686-suse-linux-gnu checking target system type... i686-suse-linux-gnu checking for a BSD-compatible install... /usr/bin/install -c checking whether build environment is sane... yes checking for a thread-safe mkdir -p... /bin/mkdir -p checking for gawk... gawk checking whether make sets $(MAKE)... yes checking for style of include used by make... GNU checking for gcc... gcc checking whether the C compiler works... yes checking for C compiler default output file name... a.out checking for suffix of executables... checking whether we are cross compiling... no checking for suffix of object files... o checking whether we are using the GNU C compiler... yes checking whether gcc accepts -g... yes checking for gcc option to accept ISO C89... none needed checking dependency style of gcc... gcc3 checking how to run the C preprocessor... gcc -E checking for grep that handles long lines and -e... /usr/bin/grep checking for egrep... /usr/bin/grep -E checking for ANSI C header files... yes checking for sys/types.h... yes checking for sys/stat.h... yes checking for stdlib.h... yes checking for string.h... yes checking for memory.h... yes checking for strings.h... yes checking for inttypes.h... yes checking for stdint.h... yes checking for unistd.h... yes checking whether byte ordering is bigendian... no checking for gcc... (cached) gcc checking whether we are using the GNU C compiler... (cached) yes checking whether gcc accepts -g... (cached) yes checking for gcc option to accept ISO C89... (cached) none needed checking dependency style of gcc... (cached) gcc3 checking whether make sets $(MAKE)... (cached) yes checking for dmidecode... /usr/sbin/dmidecode checking DirectIO/darwinio.h usability... no checking DirectIO/darwinio.h presence... no checking for DirectIO/darwinio.h... no checking arpa/inet.h usability... yes checking arpa/inet.h presence... yes checking for arpa/inet.h... yes checking asm/sunddi.h usability... no checking asm/sunddi.h presence... no checking for asm/sunddi.h... no checking fcntl.h usability... yes checking fcntl.h presence... yes checking for fcntl.h... yes checking for inttypes.h... (cached) yes checking limits.h usability... yes checking limits.h presence... yes checking for limits.h... yes checking machine/cpufunc.h usability... no checking machine/cpufunc.h presence... no checking for machine/cpufunc.h... no checking machine/sysarch.h usability... no checking machine/sysarch.h presence... no checking for machine/sysarch.h... no checking netdb.h usability... yes checking netdb.h presence... yes checking for netdb.h... yes checking netinet/in.h usability... yes checking netinet/in.h presence... yes checking for netinet/in.h... yes checking stddef.h usability... yes checking stddef.h presence... yes checking for stddef.h... yes checking for stdint.h... (cached) yes checking for stdlib.h... (cached) yes checking for string.h... (cached) yes checking for strings.h... (cached) yes checking sys/io.h usability... yes checking sys/io.h presence... yes checking for sys/io.h... yes checking sys/ioctl.h usability... yes checking sys/ioctl.h presence... yes checking for sys/ioctl.h... yes checking sys/psw.h usability... no checking sys/psw.h presence... no checking for sys/psw.h... no checking sys/socket.h usability... yes checking sys/socket.h presence... yes checking for sys/socket.h... yes checking sys/sysi86.h usability... no checking sys/sysi86.h presence... no checking for sys/sysi86.h... no checking sys/time.h usability... yes checking sys/time.h presence... yes checking for sys/time.h... yes checking sys/utsname.h usability... yes checking sys/utsname.h presence... yes checking for sys/utsname.h... yes checking termios.h usability... yes checking termios.h presence... yes checking for termios.h... yes checking for unistd.h... (cached) yes checking for inline... inline checking for off_t... yes checking for size_t... yes checking size of int... 4 checking for ssize_t... yes checking for uint8_t... yes checking for uint16_t... yes checking for uint64_t... yes checking for uint32_t... yes checking for stdlib.h... (cached) yes checking for GNU libc compatible malloc... yes checking for stdlib.h... (cached) yes checking for unistd.h... (cached) yes checking for sys/param.h... yes checking for getpagesize... yes checking for working mmap... yes checking for stdlib.h... (cached) yes checking for GNU libc compatible realloc... yes checking for gethostbyaddr... yes checking for gethostbyname... yes checking for getpagesize... (cached) yes checking for gettimeofday... yes checking for memmove... yes checking for memset... yes checking for munmap... yes checking for socket... yes checking for strcasecmp... yes checking for strchr... yes checking for strcspn... yes checking for strdup... yes checking for strerror... yes checking for strncasecmp... yes checking for strspn... yes checking for strstr... yes checking for strtol... yes checking for strtoul... yes checking for uname... yes checking for pci_alloc in -lpci... yes checking for socket in -lsocket... no checking for usb_init in -lusb... yes checking for main in -lftdi... yes configure: creating ./config.status config.status: error: cannot find input file: `Makefile.in' This is openSUSE 11.3 i586. autoconf and automake are installed. Any ideas how to fix this portability problem of autotools or what I'm doing wrong? The autotools branch and fedora-1412 branch in your repository both have that problem. Regards, Carl-Daniel -- http://www.hailfinger.org/

2 1

[PATCH 6/6] Add ich_descriptor_tool to decode all flash descriptors stored in a flash dump file
by Stefan Tauner 14 Aug '11

14 Aug '11

additionally to what is available via FDOC/FDOD this allows to access: - the softstraps which are used to configure the chipset by flash content without the need for BIOS routines. on ICH8 it is possible to read those with FDOC/FDOC too, but this was removed in later chipsets. - the ME VSCC (Vendor Specific Component Capabilities) table. simply put, this is an SPI chip database used to figure out the flash's capabilities Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ich_descriptors.c | 434 ++++++++++++++++++++++ ich_descriptors.h | 205 ++++++++++ util/ich_descriptors_tool/Makefile | 42 ++ util/ich_descriptors_tool/TODO | 6 + util/ich_descriptors_tool/ich_descriptors_tool.c | 225 +++++++++++ 5 files changed, 912 insertions(+), 0 deletions(-) create mode 100644 util/ich_descriptors_tool/Makefile create mode 100644 util/ich_descriptors_tool/TODO create mode 100644 util/ich_descriptors_tool/ich_descriptors_tool.c diff --git a/ich_descriptors.c b/ich_descriptors.c index ce40d9f..57c1d51 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -22,9 +22,33 @@ #if defined(__i386__) || defined(__x86_64__) #include "ich_descriptors.h" + +#ifdef ICH_DESCRIPTORS_FROM_DUMP + +#include <stdio.h> +#define msg_perr printf +#define msg_pdbg printf +#define msg_pdbg2 printf +#define msg_pspew printf +#define print(t, ...) printf(__VA_ARGS__) +#define DESCRIPTOR_MODE_SIGNATURE 0x0ff0a55a +/* The upper map is located in the word before the 256B-long OEM section at the + * end of the 4kB-long flash descriptor. + */ +#define UPPER_MAP_OFFSET (4096 - 256 - 4) +#define getVTBA(flumap) (((flumap)->FLUMAP1 << 4) & 0x00000ff0) + +#else /* ICH_DESCRIPTORS_FROM_DUMP */ + #include "flash.h" /* for msg_* */ #include "programmer.h" +#endif /* ICH_DESCRIPTORS_FROM_DUMP */ + +#ifndef min +#define min(a, b) (a < b) ? a : b +#endif + void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity) { print(verbosity, "BES=0x%x, ", (reg_val & VSCC_BES) >> VSCC_BES_OFF); @@ -48,6 +72,12 @@ void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descripto prettyprint_ich_descriptor_component(desc); prettyprint_ich_descriptor_region(desc); prettyprint_ich_descriptor_master(&desc->master); +#ifdef ICH_DESCRIPTORS_FROM_DUMP + if (cs >= CHIPSET_ICH8) { + prettyprint_ich_descriptor_upper_map(&desc->upper); + prettyprint_ich_descriptor_straps(cs, desc); + } +#endif /* ICH_DESCRIPTORS_FROM_DUMP */ } void prettyprint_ich_descriptor_content(const struct ich_desc_content *cont) @@ -214,6 +244,409 @@ void prettyprint_ich_descriptor_master(const struct ich_desc_master *mstr) msg_pdbg2("\n"); } +#ifdef ICH_DESCRIPTORS_FROM_DUMP + +void prettyprint_ich_descriptor_straps_ich8(const struct ich_descriptors *desc) +{ + static const char * const str_GPIO12[4] = { + "GPIO12", + "LAN PHY Power Control Function (Native Output)", + "GLAN_DOCK# (Native Input)", + "invalid configuration", + }; + + + msg_pdbg2("--- MCH details ---\n"); + msg_pdbg2("ME B is %sabled.\n", desc->north.ich8.MDB ? "dis" : "en"); + msg_pdbg2("\n"); + + msg_pdbg2("--- ICH details ---\n"); + msg_pdbg2("ME SMBus Address 1: 0x%02x\n", desc->south.ich8.ASD); + msg_pdbg2("ME SMBus Address 2: 0x%02x\n", desc->south.ich8.ASD2); + msg_pdbg2("ME SMBus Controller is connected to the %s.\n", + desc->south.ich8.MESM2SEL ? "SMLink pins" : "SMBus pins"); + msg_pdbg2("SPI CS1 is used for %s.\n", + desc->south.ich8.SPICS1_LANPHYPC_SEL ? + "LAN PHY Power Control Function" : + "SPI Chip Select"); + msg_pdbg2("GPIO12 Select is used as %s.\n", + str_GPIO12[desc->south.ich8.GPIO12_SEL]); + msg_pdbg2("PCIe Port 6 is used for %s.\n", + desc->south.ich8.GLAN_PCIE_SEL ? "integrated LAN" : "PCI Express"); + msg_pdbg2("%sn BMC Mode: " + "Intel AMT SMBus Controller 1 is connected to %s.\n", + desc->south.ich8.BMCMODE ? "I" : "Not i", + desc->south.ich8.BMCMODE ? "SMLink" : "SMBus"); + msg_pdbg2("TCO is in %s Mode.\n", + desc->south.ich8.TCOMODE ? "Advanced TCO" : "Legacy/Compatible"); + msg_pdbg2("ME A is %sabled.\n", + desc->south.ich8.ME_DISABLE ? "dis" : "en"); + msg_pdbg2("\n"); +} + +static void prettyprint_ich_descriptor_straps_ibex_pciecs(uint8_t conf, uint8_t off) +{ + msg_pdbg2("PCI Express Port Configuration Strap %d: ", off+1); + + off *= 4; + switch(conf){ + case 0: + msg_pdbg2("4x1 Ports %d-%d (x1)", 1+off, 4+off); + break; + case 1: + msg_pdbg2("1x2, 2x1 Port %d (x2), Port %d (disabled), " + "Ports %d, %d (x1)", 1+off, 2+off, 3+off, 4+off); + break; + case 2: + msg_pdbg2("2x2 Port %d (x2), Port %d (x2), Ports " + "%d, %d (disabled)", 1+off, 3+off, 2+off, 4+off); + break; + case 3: + msg_pdbg2("1x4 Port %d (x4), Ports %d-%d (disabled)", + 1+off, 2+off, 4+off); + break; + } + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_straps_ibex(const struct ich_desc_south_strap *s) +{ + static const uint8_t const dec_t209min[4] = { + 100, + 50, + 5, + 1 + }; + + msg_pdbg2("--- PCH ---\n"); + + /* PCHSTRP1 */ + msg_pdbg2("Chipset configuration Softstrap 2: %d\n", s->ibex.cs_ss2); + msg_pdbg2("Intel ME SMBus Select is %sabled.\n", + s->ibex.SMB_EN ? "en" : "dis"); + msg_pdbg2("SMLink0 segment is %sabled.\n", + s->ibex.SML0_EN ? "en" : "dis"); + msg_pdbg2("SMLink1 segment is %sabled.\n", + s->ibex.SML1_EN ? "en" : "dis"); + msg_pdbg2("SMLink1 Frequency: %s\n", + (s->ibex.SML1FRQ == 1) ? "100 kHz" : "reserved"); + msg_pdbg2("Intel ME SMBus Frequency: %s\n", + (s->ibex.SMB0FRQ == 1) ? "100 kHz" : "reserved"); + msg_pdbg2("SMLink0 Frequency: %s\n", + (s->ibex.SML0FRQ == 1) ? "100 kHz" : "reserved"); + msg_pdbg2("GPIO12 is used as %s.\n", s->ibex.LANPHYPC_GP12_SEL ? + "LAN_PHY_PWR_CTRL" : "general purpose output"); + + /* PCHSTRP2 */ + msg_pdbg2("Chipset configuration Softstrap 3: 0x%x\n", s->ibex.cs_ss3); + + /* PCHSTRP3 */ + msg_pdbg2("ME SMBus ASD address is %sabled.\n", + s->ibex.MESMASDEN ? "en" : "dis"); + msg_pdbg2("ME SMBus Controller ASD Target address: 0x%02x\n", + s->ibex.MESMASDA); + msg_pdbg2("ME SMBus I2C address is %sabled.\n", + s->ibex.MESMI2CEN ? "en" : "dis"); + msg_pdbg2("ME SMBus I2C target address: 0x%02x\n", + s->ibex.MESMI2CA); + + /* PCHSTRP4 */ + /* PCHSTRP5 */ + msg_pdbg2("Intel PHY is %s.\n", + (s->ibex.PHYCON == 2) ? "connected" : + (s->ibex.PHYCON == 0) ? "disconnected" : "reserved"); + msg_pdbg2("GbE MAC SMBus address is %sabled.\n", + s->ibex.GBEMAC_SMBUS_ADDR_EN ? "en" : "dis"); + msg_pdbg2("GbE MAC SMBus address: 0x%02x\n", + s->ibex.GBEMAC_SMBUS_ADDR); + msg_pdbg2("GbE PHY SMBus address: 0x%02x\n", + s->ibex.GBEPHY_SMBUS_ADDR); + + /* PCHSTRP6 */ + /* PCHSTRP7 */ + msg_pdbg2("Intel ME SMBus Subsystem Vendor ID: 0x%04x\n", + s->ibex.MESMA2UDID_VENDOR); + msg_pdbg2("Intel ME SMBus Subsystem Device ID: 0x%04x\n", + s->ibex.MESMA2UDID_VENDOR); + + /* PCHSTRP8 */ + /* PCHSTRP9 */ + prettyprint_ich_descriptor_straps_ibex_pciecs(s->ibex.PCIEPCS1, 0); + prettyprint_ich_descriptor_straps_ibex_pciecs(s->ibex.PCIEPCS1, 1); + msg_pdbg2("PCIe Lane Reversal 1: PCIe Lanes 0-3 are %sreserved.\n", + s->ibex.PCIELR1 ? "" : "not "); + msg_pdbg2("PCIe Lane Reversal 2: PCIe Lanes 4-7 are %sreserved.\n", + s->ibex.PCIELR2 ? "" : "not "); + msg_pdbg2("DMI Lane Reversal: DMI Lanes 0-3 are %sreserved.\n", + s->ibex.DMILR ? "" : "not "); + msg_pdbg2("Default PHY PCIe Port is %d.\n", s->ibex.PHY_PCIEPORTSEL+1); + msg_pdbg2("Integrated MAC/PHY communication over PCIe is %sabled.\n", + s->ibex.PHY_PCIE_EN ? "en" : "dis"); + + /* PCHSTRP10 */ + msg_pdbg2("Management Engine will boot from %sflash.\n", + s->ibex.ME_BOOT_FLASH ? "" : "ROM, then "); + msg_pdbg2("Chipset configuration Softstrap 5: %d\n", s->ibex.cs_ss5); + msg_pdbg2("Virtualization Engine Enable 1 is %sabled.\n", + s->ibex.VE_EN ? "en" : "dis"); + msg_pdbg2("ME Memory-attached Debug Display Device is %sabled.\n", + s->ibex.MMDDE ? "en" : "dis"); + msg_pdbg2("ME Memory-attached Debug Display Device address: 0x%02x\n", + s->ibex.MMADDR); + msg_pdbg2("Chipset configuration Softstrap 7: %d\n", s->ibex.cs_ss7); + msg_pdbg2("Integrated Clocking Configuration is %d.\n", + (s->ibex.ICC_SEL == 7) ? 0 : s->ibex.ICC_SEL); + msg_pdbg2("PCH Signal CL_RST1# does %sassert when Intel ME performs a " + "reset.\n", s->ibex.MER_CL1 ? "" : "not "); + + /* PCHSTRP11 */ + msg_pdbg2("SMLink1 GP Address is %sabled.\n", + s->ibex.SML1GPAEN ? "en" : "dis"); + msg_pdbg2("SMLink1 controller General Purpose Target address: 0x%02x\n", + s->ibex.SML1GPA); + msg_pdbg2("SMLink1 I2C Target address is %sabled.\n", + s->ibex.SML1I2CAEN ? "en" : "dis"); + msg_pdbg2("SMLink1 I2C Target address: 0x%02x\n", + s->ibex.SML1I2CA); + + /* PCHSTRP12 */ + /* PCHSTRP13 */ + /* PCHSTRP14 */ + msg_pdbg2("Virtualization Engine Enable 2 is %sabled.\n", + s->ibex.VE_EN2 ? "en" : "dis"); + msg_pdbg2("Virtualization Engine will boot from %sflash.\n", + s->ibex.VE_BOOT_FLASH ? "" : "ROM, then "); + msg_pdbg2("Braidwood SSD functionality is %sabled.\n", + s->ibex.BW_SSD ? "en" : "dis"); + msg_pdbg2("Braidwood NVMHCI functionality is %sabled.\n", + s->ibex.NVMHCI_EN ? "en" : "dis"); + + /* PCHSTRP15 */ + msg_pdbg2("Chipset configuration Softstrap 6: %d\n", s->ibex.cs_ss6); + msg_pdbg2("Integrated wired LAN Solution is %sabled.\n", + s->ibex.IWL_EN ? "en" : "dis"); + msg_pdbg2("t209 min Timing: %d ms\n", + dec_t209min[s->ibex.t209min]); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_straps(enum ich_chipset cs, const struct ich_descriptors *desc) +{ + unsigned int i, max; + msg_pdbg2("=== Softstraps ===\n"); + + if (sizeof(desc->north.STRPs) / 4 + 1 < desc->content.MSL) { + max = sizeof(desc->north.STRPs) / 4 + 1; + msg_pdbg2("MSL (%u) is greater than the current maximum of %u " + "entries.\n", desc->content.MSL, max + 1); + msg_pdbg2("Only the first %u entries will be printed.\n", max); + } else + max = desc->content.MSL; + + msg_pdbg2("--- North/MCH/PROC (%d entries) ---\n", max); + for(i = 0; i < max; i++) + msg_pdbg2("STRP%-2d = 0x%08x\n", i, desc->north.STRPs[i]); + msg_pdbg2("\n"); + + if (sizeof(desc->south.STRPs) / 4 < desc->content.ISL) { + max = sizeof(desc->south.STRPs) / 4; + msg_pdbg2("ISL (%u) is greater than the current maximum of %u " + "entries.\n", desc->content.ISL, max); + msg_pdbg2("Only the first %u entries will be printed.\n", max); + } else + max = desc->content.ISL; + + msg_pdbg2("--- South/ICH/PCH (%d entries) ---\n", max); + for(i = 0; i < max; i++) + msg_pdbg2("STRP%-2d = 0x%08x\n", i, desc->south.STRPs[i]); + msg_pdbg2("\n"); + + switch (cs) { + case CHIPSET_ICH8: + if (sizeof(desc->north.ich8) / 4 != desc->content.MSL) + msg_pdbg2("Detailed North/MCH/PROC information is " + "probably not reliable, printing anyway.\n"); + if (sizeof(desc->south.ich8) / 4 != desc->content.ISL) + msg_pdbg2("Detailed South/ICH/PCH information is " + "probably not reliable, printing anyway.\n"); + prettyprint_ich_descriptor_straps_ich8(desc); + break; + case CHIPSET_5_SERIES_IBEX_PEAK: + /* PCH straps only. PROCSTRPs are unknown. */ + if (sizeof(desc->south.ibex) / 4 != desc->content.ISL) + msg_pdbg2("Detailed South/ICH/PCH information is " + "probably not reliable, printing anyway.\n"); + prettyprint_ich_descriptor_straps_ibex(&desc->south); + break; + case CHIPSET_ICH_UNKNOWN: + break; + default: + msg_pdbg2("The meaning of the descriptor straps are unknown " + "yet.\n\n"); + break; + } +} + +void prettyprint_rdid(uint32_t reg_val) +{ + uint8_t mid = reg_val & 0xFF; + uint16_t did = ((reg_val >> 16) & 0xFF) | (reg_val & 0xFF00); + msg_pdbg2("Manufacturer ID 0x%02x, Device ID 0x%04x\n", mid, did); +} + +void prettyprint_ich_descriptor_upper_map(const struct ich_desc_upper_map *umap) +{ + int i; + msg_pdbg2("=== Upper Map Section ===\n"); + msg_pdbg2("FLUMAP1 0x%08x\n", umap->FLUMAP1); + msg_pdbg2("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2("VTL (length in DWORDS) = %d\n", umap->VTL); + msg_pdbg2("VTBA (base address) = 0x%6.6x\n", getVTBA(umap)); + msg_pdbg2("\n"); + + msg_pdbg2("VSCC Table: %d entries\n", umap->VTL/2); + for (i = 0; i < umap->VTL/2; i++) + { + uint32_t jid = umap->vscc_table[i].JID; + uint32_t vscc = umap->vscc_table[i].VSCC; + msg_pdbg2(" JID%d = 0x%08x\n", i, jid); + msg_pdbg2(" VSCC%d = 0x%08x\n", i, vscc); + msg_pdbg2(" "); /* indention */ + prettyprint_rdid(jid); + msg_pdbg2(" "); /* indention */ + prettyprint_ich_reg_vscc(vscc, 0); + } + msg_pdbg2("\n"); +} + +/* len is the length of dump in bytes */ +int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, enum ich_chipset cs, struct ich_descriptors *desc) +{ + unsigned int i, max; + uint8_t pch_bug_offset = 0; + + if (dump == NULL || desc == NULL) + return RET_PARAM; + + if (dump[0] != DESCRIPTOR_MODE_SIGNATURE) { + if (dump[4] == DESCRIPTOR_MODE_SIGNATURE) + pch_bug_offset = 4; + else + return RET_ERR; + } + + /* map */ + if (len < (4 + pch_bug_offset) * 4 - 1) + return RET_OOB; + desc->content.FLVALSIG = dump[0 + pch_bug_offset]; + desc->content.FLMAP0 = dump[1 + pch_bug_offset]; + desc->content.FLMAP1 = dump[2 + pch_bug_offset]; + desc->content.FLMAP2 = dump[3 + pch_bug_offset]; + + /* component */ + if (len < (getFCBA(&desc->content) + 3 * 4 - 1)) + return RET_OOB; + desc->component.FLCOMP = dump[(getFCBA(&desc->content) >> 2) + 0]; + desc->component.FLILL = dump[(getFCBA(&desc->content) >> 2) + 1]; + desc->component.FLPB = dump[(getFCBA(&desc->content) >> 2) + 2]; + + /* region */ + if (len < (getFRBA(&desc->content) + 5 * 4 - 1)) + return RET_OOB; + desc->region.FLREGs[0] = dump[(getFRBA(&desc->content) >> 2) + 0]; + desc->region.FLREGs[1] = dump[(getFRBA(&desc->content) >> 2) + 1]; + desc->region.FLREGs[2] = dump[(getFRBA(&desc->content) >> 2) + 2]; + desc->region.FLREGs[3] = dump[(getFRBA(&desc->content) >> 2) + 3]; + desc->region.FLREGs[4] = dump[(getFRBA(&desc->content) >> 2) + 4]; + + /* master */ + if (len < (getFMBA(&desc->content) + 3 * 4 - 1)) + return RET_OOB; + desc->master.FLMSTR1 = dump[(getFMBA(&desc->content) >> 2) + 0]; + desc->master.FLMSTR2 = dump[(getFMBA(&desc->content) >> 2) + 1]; + desc->master.FLMSTR3 = dump[(getFMBA(&desc->content) >> 2) + 2]; + + /* upper map */ + desc->upper.FLUMAP1 = dump[(UPPER_MAP_OFFSET >> 2) + 0]; + + /* VTL is 8 bits long. Quote from the Ibex Peak SPI programming guide: + * "Identifies the 1s based number of DWORDS contained in the VSCC + * Table. Each SPI component entry in the table is 2 DWORDS long." So + * the maximum of 255 gives us 127.5 SPI components(!?) 8 bytes each. A + * check ensures that the maximum offset actually accessed is available. + */ + if (len < (getVTBA(&desc->upper) + (desc->upper.VTL / 2 * 8) - 1)) + return RET_OOB; + + for (i = 0; i < desc->upper.VTL/2; i++) { + desc->upper.vscc_table[i].JID = + dump[(getVTBA(&desc->upper) >> 2) + i * 2 + 0]; + desc->upper.vscc_table[i].VSCC = + dump[(getVTBA(&desc->upper) >> 2) + i * 2 + 1]; + } + + /* MCH/PROC (aka. North) straps */ + if (len < getFMSBA(&desc->content) + desc->content.MSL * 4) + return RET_OOB; + + /* limit the range to be written */ + max = min(sizeof(desc->north.STRPs) / 4, desc->content.MSL); + for (i = 0; i < max; i++) + desc->north.STRPs[i] = + dump[(getFMSBA(&desc->content) >> 2) + i]; + + /* ICH/PCH (aka. South) straps */ + if (len < getFISBA(&desc->content) + desc->content.ISL * 4) + return RET_OOB; + + /* limit the range to be written */ + max = min(sizeof(desc->south.STRPs) / 4, desc->content.ISL); + for (i = 0; i < max; i++) + desc->south.STRPs[i] = + dump[(getFISBA(&desc->content) >> 2) + i]; + + return RET_OK; +} + +#else /* ICH_DESCRIPTORS_FROM_DUMP */ + +/** Returns the integer representation of the component density with index +idx in bytes or 0 if a correct size can not be determined. */ +int getFCBA_component_density(uint8_t idx, const struct ich_descriptors *desc) +{ + uint8_t size_enc; + static const int const dec_mem[6] = { + 512 * 1024, + 1 * 1024 * 1024, + 2 * 1024 * 1024, + 4 * 1024 * 1024, + 8 * 1024 * 1024, + 16 * 1024 * 1024, + }; + + switch(idx) { + case 0: + size_enc = desc->component.comp1_density; + break; + case 1: + if (desc->content.NC == 0) + return 0; + size_enc = desc->component.comp2_density; + break; + default: + msg_perr("Only component index 0 or 1 are supported yet.\n"); + return 0; + } + if (size_enc > 5) { + msg_perr("Density of component with index %d is invalid. " + "Encoded density is 0x%x.\n", idx, size_enc); + return 0; + } + return dec_mem[size_enc]; +} + static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) { uint32_t control = 0; @@ -284,5 +717,6 @@ int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc) msg_pdbg2(" done.\n"); return RET_OK; } +#endif /* ICH_DESCRIPTORS_FROM_DUMP */ #endif /* BITFIELDS == 1 */ #endif /* defined(__i386__) || defined(__x86_64__) */ diff --git a/ich_descriptors.h b/ich_descriptors.h index b1da914..56d1b3e 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -240,11 +240,206 @@ struct ich_desc_master { }; }; +#ifdef ICH_DESCRIPTORS_FROM_DUMP +struct ich_desc_north_strap { + union { + uint32_t STRPs[1]; /* current maximum: ich8 */ + struct { /* ich8 */ + struct { /* STRP2 (in the datasheet) */ + uint32_t MDB :1, + :31; + }; + } ich8; + }; +}; + +struct ich_desc_south_strap { + union { + uint32_t STRPs[16]; /* current maximum: ibex peak */ + struct { /* ich8 */ + struct { /* STRP1 */ + uint32_t ME_DISABLE :1, + :6, + TCOMODE :1, + ASD :7, + BMCMODE :1, + :3, + GLAN_PCIE_SEL :1, + GPIO12_SEL :2, + SPICS1_LANPHYPC_SEL :1, + MESM2SEL :1, + :1, + ASD2 :7; + }; + } ich8; + struct { /* ibex peak */ + struct { /* STRP0 */ + uint32_t :1, + cs_ss2 :1, + :5, + SMB_EN :1, + SML0_EN :1, + SML1_EN :1, + SML1FRQ :2, + SMB0FRQ :2, + SML0FRQ :2, + :4, + LANPHYPC_GP12_SEL :1, + cs_ss1 :1, + :2, + DMI_REQID_DIS :1, + :4, + BBBS :2, + :1; + }; + struct { /* STRP1 */ + uint32_t cs_ss3 :4, + :28; + }; + struct { /* STRP2 */ + uint32_t :8, + MESMASDEN :1, + MESMASDA :7, + :8, + MESMI2CEN :1, + MESMI2CA :7; + }; + struct { /* STRP3 */ + uint32_t :32; + }; + struct { /* STRP4 */ + uint32_t PHYCON :2, + :6, + GBEMAC_SMBUS_ADDR_EN :1, + GBEMAC_SMBUS_ADDR :7, + :1, + GBEPHY_SMBUS_ADDR :7, + :8; + }; + struct { /* STRP5 */ + uint32_t :32; + }; + struct { /* STRP6 */ + uint32_t :32; + }; + struct { /* STRP7 */ + uint32_t MESMA2UDID_VENDOR :16, + MESMA2UDID_DEVICE :16; + }; + struct { /* STRP8 */ + uint32_t :32; + }; + struct { /* STRP9 */ + uint32_t PCIEPCS1 :2, + PCIEPCS2 :2, + PCIELR1 :1, + PCIELR2 :1, + DMILR :1, + :1, + PHY_PCIEPORTSEL :3, + PHY_PCIE_EN :1, + :20; + }; + struct { /* STRP10 */ + uint32_t :1, + ME_BOOT_FLASH :1, + cs_ss5 :1, + VE_EN :1, + :4, + MMDDE :1, + MMADDR :7, + cs_ss7 :1, + :1, + ICC_SEL :3, + MER_CL1 :1, + :10; + }; + struct { /* STRP11 */ + uint32_t SML1GPAEN :1, + SML1GPA :7, + :16, + SML1I2CAEN :1, + SML1I2CA :7; + }; + struct { /* STRP12 */ + uint32_t :32; + }; + struct { /* STRP13 */ + uint32_t :32; + }; + struct { /* STRP14 */ + uint32_t :8, + VE_EN2 :1, + :5, + VE_BOOT_FLASH :1, + :1, + BW_SSD :1, + NVMHCI_EN :1, + :14; + }; + struct { /* STRP15 */ + uint32_t :3, + cs_ss6 :2, + :1, + IWL_EN :1, + :1, + t209min :2, + :22; + }; + }ibex; + }; +}; + +struct ich_desc_upper_map { + union { + uint32_t FLUMAP1; /* Flash Upper Map 1 */ + struct { + uint32_t VTBA :8, /* ME VSCC Table Base Address */ + VTL :8, /* ME VSCC Table Length */ + :16; + }; + }; + struct { + union { /* JEDEC-ID Register */ + uint32_t JID; + struct { + uint32_t vid :8, /* Vendor ID */ + cid0 :8, /* Component ID 0 */ + cid1 :8, /* Component ID 1 */ + :8; + }; + }; + union { /* Vendor Specific Component Capabilities */ + uint32_t VSCC; + struct { + uint32_t ubes :2, /* Upper Block/Sector Erase Size */ + uwg :1, /* Upper Write Granularity */ + uwsr :1, /* Upper Write Status Required */ + uwews :1, /* Upper Write Enable on Write Status */ + :3, + ueo :8, /* Upper Erase Opcode */ + lbes :2, /* Lower Block/Sector Erase Size */ + lwg :1, /* Lower Write Granularity */ + lwsr :1, /* Lower Write Status Required */ + lwews :1, /* Lower Write Enable on Write Status */ + :3, + leo :16; /* Lower Erase Opcode */ + }; + }; + } vscc_table[128]; +}; +#endif /* ICH_DESCRIPTORS_FROM_DUMP */ + struct ich_descriptors { struct ich_desc_content content; struct ich_desc_component component; struct ich_desc_region region; struct ich_desc_master master; +#ifdef ICH_DESCRIPTORS_FROM_DUMP + struct ich_desc_north_strap north; + struct ich_desc_south_strap south; + struct ich_desc_upper_map upper; +#endif /* ICH_DESCRIPTORS_FROM_DUMP */ }; void prettyprint_ich_descriptors(enum ich_chipset, const struct ich_descriptors *desc); @@ -254,8 +449,18 @@ void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc); void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc); void prettyprint_ich_descriptor_master(const struct ich_desc_master *master); +#ifdef ICH_DESCRIPTORS_FROM_DUMP + +void prettyprint_ich_descriptor_upper_map(const struct ich_desc_upper_map *umap); +void prettyprint_ich_descriptor_straps(enum ich_chipset cs, const struct ich_descriptors *desc); +int read_ich_descriptors_from_dump(const uint32_t *dump, unsigned int len, enum ich_chipset cs, struct ich_descriptors *desc); + +#else /* ICH_DESCRIPTORS_FROM_DUMP */ + int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc); +int getFCBA_component_density(uint8_t idx, const struct ich_descriptors *desc); +#endif /* ICH_DESCRIPTORS_FROM_DUMP */ #endif /* BITFIELDS == 1 */ #endif /* __ICH_DESCRIPTORS_H__ */ #endif /* defined(__i386__) || defined(__x86_64__) */ diff --git a/util/ich_descriptors_tool/Makefile b/util/ich_descriptors_tool/Makefile new file mode 100644 index 0000000..1af90ce --- /dev/null +++ b/util/ich_descriptors_tool/Makefile @@ -0,0 +1,42 @@ +CC ?= gcc + +PROGRAM=ich_descriptors_tool +EXTRAINCDIRS = ../../ . +DEPPATH = .dep +OBJATH = .obj +SHAREDSRC = ich_descriptors.c +SHAREDSRCDIR = ../.. + +SRC = $(wildcard *.c) + +CFLAGS += -Wall +CFLAGS += -MMD -MP -MF $(DEPPATH)/$((a)F).d +# enables functions that populate the descriptor structs from plain binary dumps +CFLAGS += -D ICH_DESCRIPTORS_FROM_DUMP +CFLAGS += $(patsubst %,-I%,$(EXTRAINCDIRS)) + +OBJ = $(OBJATH)/$(SRC:%.c=%.o) + +SHAREDOBJ = $(OBJATH)/$(notdir $(SHAREDSRC:%.c=%.o)) + +all:$(PROGRAM) + +$(OBJ): $(OBJATH)/%.o : %.c + $(CC) $(CFLAGS) -o $@ -c $< + +# this enables us to share source files without simultaneously sharing .o files +# with flashrom, which would lead to unexpected results (w/o running make clean) +$(SHAREDOBJ): $(OBJATH)/%.o : $(SHAREDSRCDIR)/%.c + $(CC) $(CFLAGS) -o $@ -c $< + +$(PROGRAM): $(OBJ) $(SHAREDOBJ) + $(CC) -o $(PROGRAM) $(OBJ) $(SHAREDOBJ) + +clean: + rm -f $(PROGRAM) + rm -rf $(DEPPATH) $(OBJATH) + +# Include the dependency files. +-include $(shell mkdir -p $(DEPPATH) $(OBJATH) 2>/dev/null) $(wildcard $(DEPPATH)/*) + +.PHONY: all clean diff --git a/util/ich_descriptors_tool/TODO b/util/ich_descriptors_tool/TODO new file mode 100644 index 0000000..03701bf --- /dev/null +++ b/util/ich_descriptors_tool/TODO @@ -0,0 +1,6 @@ +- reverse the path, as in assemble a descriptormode image from various + blobs (BIOS, GbE, ME, OEM) and a description (xml? custom config? + sane defaults and cmd-line switches?) +- dump 256 OEM bytes +- handle descriptors of various chipsets correctly +- little endian only diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c new file mode 100644 index 0000000..3721eb4 --- /dev/null +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -0,0 +1,225 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (C) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * dump information and binaries from BIOS images that are in descriptor mode + */ +#include <stdio.h> +#include <stdint.h> +#include <stdlib.h> +#include <sys/mman.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <fcntl.h> +#include <unistd.h> +#include <string.h> +#include <errno.h> +#include "ich_descriptors.h" + +static void dump_file(const char *basename, const uint32_t *dump, unsigned int len, struct ich_desc_region *reg, unsigned int i) +{ + int ret; + char *fn; + const char *reg_name; + uint32_t file_len; + const char *const region_names[5] = { + "Descriptor", "BIOS", "ME", "GbE", "Platform" + }; + uint32_t base = ICH_FREG_BASE(reg->FLREGs[i]); + uint32_t limit = ICH_FREG_LIMIT(reg->FLREGs[i]); + + reg_name = region_names[i]; + if (base > limit) { + printf("The %s region is unused and thus not dumped.\n", + reg_name); + return; + } + + limit = limit | 0x0fff; + file_len = limit + 1 - base; + if (base + file_len > len) { + printf("The %s region is spanning 0x%08x-0x%08x, but it is " + "not (fully) included in the image (0-0x%08x), thus not " + "dumped.\n", reg_name, base, limit, len - 1); + return; + } + + fn = malloc(strlen(basename) + strlen(reg_name) + strlen(".bin") + 2); + if (!fn) { + fprintf(stderr, "Out of memory!\n"); + exit(1); + } + snprintf(fn, strlen(basename) + strlen(reg_name) + strlen(".bin") + 2, + "%s.%s.bin", basename, reg_name); + printf("Dumping %u bytes of the %s region from 0x%08x-0x%08x to %s... ", + file_len, region_names[i], base, limit, fn); + int fh = open(fn, O_WRONLY | O_CREAT, S_IRUSR | S_IWUSR); + free(fn); + if (fh < 0) { + fprintf(stderr, + "ERROR: couldn't open(%s): %s\n", fn, strerror(errno)); + exit(1); + } + + ret = write(fh, &dump[base >> 2], file_len); + if (ret != file_len) { + fprintf(stderr, "FAILED.\n"); + exit(1); + } + + printf("done.\n"); + close(fh); +} + +void dump_files(const char *n, const uint32_t *buf, unsigned int len, struct ich_desc_region *reg) +{ + unsigned int i; + printf("=== Dumping region files ===\n"); + for (i = 0; i < 5; i++) + dump_file(n, buf, len, reg, i); + printf("\n"); +} + +static void usage(char *argv[], char *error) +{ + if (error != NULL) { + fprintf(stderr, "%s\n", error); + } + printf("usage: '%s -f <image file name> [-c <chipset name>] [-d]'\n\n" +"where <image file name> points to an image of the contents of the SPI flash.\n" +"In case that image is really in descriptor mode %s\n" +"will pretty print some of the contained information.\n" +"To also print the data stored in the descriptor strap you have to indicate\n" +"the chipset series with the '-c' parameter and one of the possible arguments:\n" +"\t- \"ich8\",\n" +"\t- \"ich9\",\n" +"\t- \"ich10\",\n" +"\t- \"5\" or \"ibex\" for Intel's 5 series chipsets,\n" +"\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n" +"\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n" +"If '-d' is specified some regions such as the BIOS image as seen by the CPU or\n" +"the GbE blob that is required to initialize the GbE are also dumped to files.\n", + argv[0], argv[0]); + exit(1); +} + +int main(int argc, char *argv[]) +{ + int fd; /* file descriptor to flash file */ + int len; /* file/buffer size in bytes */ + uint32_t *buf; /* mmap'd file */ + + int opt; + int ret; + int dump = 0; + const char *fn = NULL; + const char *csn = NULL; + enum ich_chipset cs = CHIPSET_ICH_UNKNOWN; + struct ich_descriptors desc = {{ 0 }}; + + while ((opt = getopt(argc, argv, "df:c:")) != -1) { + switch (opt) { + case 'd': + dump = 1; + break; + case 'f': + fn = optarg; + break; + case 'c': + csn = optarg; + break; + default: /* '?' */ + usage(argv, NULL); + } + } + if (fn == NULL) + usage(argv, + "Need a file name of a descriptor image to read from."); + + fd = open(fn, O_RDONLY); + if (fd < 0) + usage(argv, "No such file"); + len = lseek(fd, 0, SEEK_END); + if (len < 0) + usage(argv, "Seeking to the end of the file failed"); + + buf = mmap(NULL, len, PROT_READ, MAP_PRIVATE, fd, 0); + if (buf == (void *) -1) { + /* fallback for stupid OSes like cygwin */ + int ret; + buf = malloc(len); + if (!buf) + usage(argv, "Could not allocate memory"); + lseek(fd, 0, SEEK_SET); + ret = read(fd, buf, len); + if (ret != len) + usage(argv, "Seeking to the end of the file failed"); + } + printf("The flash image has a size of %d [0x%x] bytes.\n", len, len); + close(fd); + + if (csn != NULL) { + if (strcmp(csn, "ich8") == 0) + cs = CHIPSET_ICH8; + else if (strcmp(csn, "ich9") == 0) + cs = CHIPSET_ICH9; + else if (strcmp(csn, "ich10") == 0) + cs = CHIPSET_ICH10; + else if ((strcmp(csn, "5") == 0) || + (strcmp(csn, "ibex") == 0)) + cs = CHIPSET_5_SERIES_IBEX_PEAK; + else if ((strcmp(csn, "6") == 0) || + (strcmp(csn, "cougar") == 0)) + cs = CHIPSET_6_SERIES_COUGAR_POINT; + else if ((strcmp(csn, "7") == 0) || + (strcmp(csn, "panther") == 0)) + cs = CHIPSET_7_SERIES_PANTHER_POINT; + } + + ret = read_ich_descriptors_from_dump(buf, len, cs, &desc); + switch (ret) { + case RET_OK: + break; + case RET_ERR: + printf("Image not in descriptor mode.\n"); + exit(1); + case RET_OOB: + printf("Tried to access a location out of bounds of the image. " + "- Corrupt image?\n"); + exit(1); + default: + printf("Unhandled return value at %s:%u, please report this.\n", + __FILE__, __LINE__); + exit(1); + } + + prettyprint_ich_descriptors(cs, &desc); + + //uint8_t *pMAC = (uint8_t *) &buf[r->reg3_base >> 2]; + //printf("The MAC-address might be: %02x:%02x:%02x:%02x:%02x:%02x\n", + //pMAC[0], pMAC[1], pMAC[2], pMAC[3], pMAC[4], pMAC[5]); + + if (dump == 1) + dump_files(fn, buf, len, &desc.region); + + return 0; +} + -- 1.7.1

1 0

[PATCH 5/6] ichspi: add support for Intel Hardware Sequencing
by Stefan Tauner 14 Aug '11

14 Aug '11

todo: - revise hwseq activation: when should hwseq be used, when swseq? in the current version i have added a programmer parameter to tell flashrom when one wants to use hwseq _if it is available_ (i.e. descriptor valid), example: flashrom -p internal:laptop=force_I_want_a_brick,hwseq=yes -VV this needs to be documented in the man page if it gets merged like that. - commit message (is a link to my blog post a good idea (additionally)?) - revise (levels of) prints - revise timeout values (for optimal performance) - build upon the upcoming opaque interface framework instead Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipdrivers.h | 6 + flashchips.c | 23 ++++- flashchips.h | 2 + ichspi.c | 352 +++++++++++++++++++++++++++++++++++++++++++++++++++++++-- programmer.h | 1 + 5 files changed, 373 insertions(+), 11 deletions(-) diff --git a/chipdrivers.h b/chipdrivers.h index 92ddbea..f97e2ad 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -84,6 +84,12 @@ void print_status_82802ab(uint8_t status); int unlock_82802ab(struct flashchip *flash); int unlock_28f004s5(struct flashchip *flash); +/* ichspi.c */ +int ich_hwseq_probe(struct flashchip *flash); +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int start, int len); +int ich_hwseq_block_erase(struct flashchip *flash, unsigned int addr, unsigned int blocklen); +int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); + /* jedec.c */ uint8_t oddparity(uint8_t val); void toggle_ready_jedec(chipaddr dst); diff --git a/flashchips.c b/flashchips.c index 1a5622f..041b9a5 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8752,7 +8752,27 @@ const struct flashchip flashchips[] = { .read = read_memmapped, .voltage = {3000, 3600}, /* Also has 12V fast program */ }, - +#if defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) + { + .vendor = "Intel", + .name = "Hardware Sequencing", + .bustype = BUS_SPI, + .manufacture_id = INTEL_ID, + .model_id = INTEL_HWSEQ, + .total_size = 0, + .page_size = 256, + .tested = TEST_OK_PREW, + .probe = ich_hwseq_probe, + .block_erasers = + { + { /* erase blocks will be set by the probing function */ + .block_erase = ich_hwseq_block_erase, + } + }, + .write = ich_hwseq_write_256, + .read = ich_hwseq_read, + }, +#endif // defined(CONFIG_INTERNAL) && (defined(__i386__) || defined(__x86_64__)) { .vendor = "AMIC", .name = "unknown AMIC SPI chip", @@ -8885,6 +8905,7 @@ const struct flashchip flashchips[] = { .probe = probe_spi_rdid, .write = NULL, }, + { .vendor = "Generic", .name = "unknown SPI chip (REMS)", diff --git a/flashchips.h b/flashchips.h index ff49d31..1374b2f 100644 --- a/flashchips.h +++ b/flashchips.h @@ -346,6 +346,8 @@ #define SHARP_LH28F008SA 0xA2 /* Sharp chip, Intel Vendor ID */ #define SHARP_LH28F008SC 0xA6 /* Sharp chip, Intel Vendor ID */ +#define INTEL_HWSEQ 0xFFFE /* dummy ID for hardware sequencing */ + #define ISSI_ID 0xD5 /* ISSI Integrated Silicon Solutions */ /* diff --git a/ichspi.c b/ichspi.c index 737613b..eaaf98e 100644 --- a/ichspi.c +++ b/ichspi.c @@ -26,7 +26,9 @@ #if defined(__i386__) || defined(__x86_64__) #include <string.h> +#include <stdlib.h> #include "flash.h" +#include "flashchips.h" #include "chipdrivers.h" #include "programmer.h" #include "spi.h" @@ -1084,6 +1086,298 @@ static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, return result; } +static struct hwseq { + uint32_t size_comp0; + uint32_t size_comp1; +} hwseq; + +static void ich_hwseq_set_addr(uint32_t addr) +{ + uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF; + REGWRITE32(ICH9_REG_FADDR, (addr & 0x01FFFFFF) | addr_old); +} + +/* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes + * of the block containing this address. */ +static uint32_t ich_hwseq_get_erase_block_size(unsigned int addr) +{ + uint8_t enc_berase; + static const uint32_t const dec_berase[4] = { + 256, + 4 * 1024, + 8 * 1024, + 64 * 1024 + }; + + ich_hwseq_set_addr(addr); + enc_berase = (REGREAD16(ICH9_REG_HSFS) & HSFS_BERASE) >> + HSFS_BERASE_OFF; + return dec_berase[enc_berase]; +} + +/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 10 us intervals. + Resets all error flags in HSFS. + Returns 0 if the cycle completes successfully without errors within + timeout us, 1 on errors. */ +static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, + unsigned int len) +{ + uint16_t hsfs; + uint32_t addr; + + while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) & + (HSFS_FDONE | HSFS_FCERR)) == 0) && + --timeout) { + programmer_delay(10); + } + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + if (!timeout) { + addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; + msg_perr("Timeout error between offset 0x%08x and " + "0x%08x + %d (=0x%08x)!\n", + addr, addr, len - 1, addr + len - 1); + prettyprint_ich9_reg_hsfs(hsfs); + prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); + return 1; + } + + if (hsfs & HSFS_FCERR) { + addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF; + msg_perr("Transaction error between offset 0x%08x and " + "0x%08x (=0x%08x + %d)!\n", + addr, addr + len - 1, addr, len - 1); + prettyprint_ich9_reg_hsfs(hsfs); + prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); + return 1; + } + return 0; +} + +int ich_hwseq_probe(struct flashchip *flash) +{ + uint32_t total_size, boundary; + uint32_t erase_size_low, size_low, erase_size_high, size_high; + struct block_eraser *eraser; + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_cerr("This chip (%s) is not supported in hardware" + "sequencing mode and should never have been probed.\n", + flash->name); + msg_cerr("%s: Please report a bug at flashrom(a)flashrom.org\n", + __func__); + return 0; + } + + msg_cdbg("Prerequisites for Intel Hardware Sequencing are "); + if (spi_programmer->type != SPI_CONTROLLER_ICH_HWSEQ) { + msg_cdbg("not met.\n"); + return 0; + } + msg_cdbg("met.\n"); + + total_size = hwseq.size_comp0 + hwseq.size_comp1; + msg_cdbg("Found %d attached SPI flash chip", + (hwseq.size_comp1 != 0) ? 2 : 1); + if (hwseq.size_comp1 != 0) + msg_cdbg("s with a combined"); + else + msg_cdbg(" with a"); + msg_cdbg(" density of %d kB.\n", total_size / 1024); + flash->total_size = total_size / 1024; + + eraser = &(flash->block_erasers[0]); + boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12; + size_high = total_size - boundary; + erase_size_high = ich_hwseq_get_erase_block_size(boundary); + + if (boundary == 0) { + msg_cdbg("There is only one partition containing the whole " + "address space (0x%06x - 0x%06x).\n", 0, size_high-1); + eraser->eraseblocks[0].size = erase_size_high; + eraser->eraseblocks[0].count = size_high / erase_size_high; + msg_cdbg("There are %d erase blocks with %d B each.\n", + size_high / erase_size_high, erase_size_high); + } else { + msg_cdbg("The flash address space (0x%06x - 0x%06x) is divided " + "at address 0x%06x in two partitions.\n", + 0, size_high-1, boundary); + size_low = total_size - size_high; + erase_size_low = ich_hwseq_get_erase_block_size(0); + + eraser->eraseblocks[0].size = erase_size_low; + eraser->eraseblocks[0].count = size_low / erase_size_low; + msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n", + 0, size_low-1); + msg_cdbg("In that range are %d erase blocks with %d B each.\n", + size_low / erase_size_low, erase_size_low); + + eraser->eraseblocks[1].size = erase_size_high; + eraser->eraseblocks[1].count = size_high / erase_size_high; + msg_cdbg("The second partition ranges from 0x%06x to 0x%06x.\n", + boundary, size_high-1); + msg_cdbg("In that range are %d erase blocks with %d B each.\n", + size_high / erase_size_high, erase_size_high); + } + return 1; +} + +static int ich_hwseq_send_command(unsigned int writecnt, + unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + msg_pdbg("skipped. Intel Hardware Sequencing does not support sending " + "arbitrary commands."); + return -1; +} + +int ich_hwseq_block_erase(struct flashchip *flash, + unsigned int addr, + unsigned int len) +{ + uint32_t erase_block; + uint16_t hsfc; + uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */ + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode\n", flash->name); + return -1; + } + + erase_block = ich_hwseq_get_erase_block_size(addr); + if (len != erase_block) { + msg_cerr("Erase block size for address 0x%06x is %d B, " + "but requested erase block size is %d B. " + "Not erasing anything.\n", addr, erase_block, len); + return -1; + } + + /* Although the hardware supports this (it would erase the whole block + * containing the address) we play safe here. */ + if (addr % erase_block != 0) { + msg_cerr("Erase address 0x%06x is not aligned to the erase " + "block boundary (any multiple of %d). " + "Not erasing anything.\n", addr, erase_block); + return -1; + } + + if (addr + len > flash->total_size * 1024) { + msg_perr("Request to erase some inaccessible memory address(es)" + " (addr=0x%x, len=%d). " + "Not erasing anything.\n", addr, len); + return -1; + } + + msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr); + + /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ + hsfc |= HSFC_FGO; /* start */ + msg_pdbg("HSFC used for block erasing: "); + prettyprint_ich9_reg_hsfc(hsfc); + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, len)) + return -1; + return 0; +} + +int ich_hwseq_read(struct flashchip *flash, uint8_t *buf, int addr, int len) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode.\n", flash->name); + return -1; + } + + if (addr < 0 || addr + len > flash->total_size * 1024) { + msg_perr("Request to read from an inaccessible memory address " + "(addr=0x%x, len=%d).\n", addr, len); + return -1; + } + + msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + while (len > 0) { + block_len = min(len, spi_programmer->max_data_read); + ich_hwseq_set_addr(addr); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* set read operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + return 1; + ich_read_data(buf, block_len, ICH9_REG_FDATA0); + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} + +int ich_hwseq_write_256(struct flashchip *flash, uint8_t *buf, int addr, int len) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; + uint8_t block_len; + + if (flash->manufacture_id != INTEL_ID || + flash->model_id != INTEL_HWSEQ) { + msg_perr("This chip (%s) is not supported in hardware" + "sequencing mode\n", flash->name); + return -1; + } + + if (addr < 0 || addr + len > flash->total_size * 1024) { + msg_perr("Request to write to an inaccessible memory address " + "(addr=0x%x, len=%d).\n", addr, len); + return -1; + } + + msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); + + while (len > 0) { + ich_hwseq_set_addr(addr); + block_len = min(len, spi_programmer->max_data_write); + ich_fill_data(buf, block_len, ICH9_REG_FDATA0); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc); + + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + return -1; + addr += block_len; + buf += block_len; + len -= block_len; + } + return 0; +} + static int ich_spi_send_multicommand(struct spi_command *cmds) { int ret = 0; @@ -1207,6 +1501,16 @@ static const struct spi_programmer spi_programmer_ich9 = { .write_256 = default_spi_write_256, }; +static const struct spi_programmer spi_programmer_ich_hwseq = { + .type = SPI_CONTROLLER_ICH_HWSEQ, + .max_data_read = 64, + .max_data_write = 64, + .command = ich_hwseq_send_command, + .multicommand = default_spi_send_multicommand, + .read = ich_hwseq_read, + .write_256 = ich_hwseq_write_256, +}; + int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, int ich_generation) { @@ -1214,21 +1518,20 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, uint8_t old, new; uint16_t spibar_offset, tmp2; uint32_t tmp; + char *arg; int ichspi_desc = 0; + int hwseq_en = 0; switch (ich_generation) { case 7: - register_spi_programmer(&spi_programmer_ich7); spibar_offset = 0x3020; break; case 8: - register_spi_programmer(&spi_programmer_ich9); spibar_offset = 0x3020; break; case 9: case 10: default: /* Future version might behave the same */ - register_spi_programmer(&spi_programmer_ich9); spibar_offset = 0x3800; break; } @@ -1239,8 +1542,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, /* Assign Virtual Address */ ich_spibar = rcrb + spibar_offset; - switch (spi_programmer->type) { - case SPI_CONTROLLER_ICH7: + switch (ich_generation) { + case 7: msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", @@ -1277,9 +1580,21 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, ichspi_lock = 1; } ich_set_bbar(0); + register_spi_programmer(&spi_programmer_ich7); ich_init_opcodes(); break; - case SPI_CONTROLLER_ICH9: + case 8: + case 9: + case 10: + default: /* Future version might behave the same */ + arg = extract_programmer_param("hwseq"); + if (arg && !strcmp(arg, "yes")) + hwseq_en = 1; + else if (arg && !strlen(arg)) + msg_pinfo("Missing argument for hwseq.\n"); + else if (arg) + msg_pinfo("Unknown argument for hwseq: %s\n", arg); + free(arg); tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); prettyprint_ich9_reg_hsfs(tmp2); @@ -1363,19 +1678,36 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pdbg("\n"); #if BITFIELDS == 1 + { /* to be able to declare desc here and avoid another + * "#if BITFIELDS == 1" on top + */ + struct ich_descriptors desc = {{ 0 }}; if (ichspi_desc) { - struct ich_descriptors desc = {{ 0 }}; if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == RET_OK) prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, &desc); + /* If the descriptor is valid and indicates multiple + * flash devices we need to use hwseq to be able to + * access the second flash device. + */ + if (desc.content.NC != 0) + hwseq_en = 1; + } else + hwseq_en = 0; /* disable it even if the user said yes */ + + if (hwseq_en > 0) { + hwseq.size_comp0 = getFCBA_component_density(0, &desc); + hwseq.size_comp1 = getFCBA_component_density(1, &desc); + register_spi_programmer(&spi_programmer_ich_hwseq); + } else { + register_spi_programmer(&spi_programmer_ich9); + ich_init_opcodes(); + } } #endif /* BITFIELDS == 1 */ ich_init_opcodes(); break; - default: - /* Nothing */ - break; } old = pci_read_byte(dev, 0xdc); diff --git a/programmer.h b/programmer.h index 6a28dbe..6e316d1 100644 --- a/programmer.h +++ b/programmer.h @@ -517,6 +517,7 @@ enum spi_controller { #if defined(__i386__) || defined(__x86_64__) SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, + SPI_CONTROLLER_ICH_HWSEQ, SPI_CONTROLLER_IT85XX, SPI_CONTROLLER_IT87XX, SPI_CONTROLLER_SB600, -- 1.7.1

1 0

[PATCH 4/6] ichspi: improve prettyprint_opcodes
by Stefan Tauner 14 Aug '11

14 Aug '11

add headers for the columns and some decoding into human readable format. --- before: […] Reading OPCODES... done preop0=0x06, preop1=0x50 op[0]=0x02, 3, 0 op[1]=0x03, 2, 0 op[2]=0x20, 3, 0 op[3]=0x05, 0, 0 op[4]=0x9f, 0, 1 op[5]=0x20, 1, 2 op[6]=0x01, 1, 0 op[7]=0x06, 0, 0 SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: FWH, SPI. […] after: […] Reading OPCODES... done OP Type Pre-OP op[0]: 0x02, write w/ addr, none op[1]: 0x03, read w/ addr, none op[2]: 0x20, write w/ addr, none op[3]: 0x05, read w/o addr, none op[4]: 0x9f, read w/o addr, none op[5]: 0x20, write w/o addr, 1 op[6]: 0x01, write w/o addr, 2 op[7]: 0x06, read w/o addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x50 SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: FWH, SPI. […] i could also print the preops directly in the preop column instead of using that redirection. but i think as debug output it is better to know the index of the two preops too. side note: does it make sense to create an opcode -> string decoder for flashrom-wide usage in user output (in spi25.c)? an erase opcode -> function pointer decoder is used in sfdp, that could also be generalized like that. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 34 +++++++++++++++++++++++----------- 1 files changed, 23 insertions(+), 11 deletions(-) diff --git a/ichspi.c b/ichspi.c index daa4a8a..737613b 100644 --- a/ichspi.c +++ b/ichspi.c @@ -295,22 +295,34 @@ static OPCODES O_EXISTING = {}; /* pretty printing functions */ static void prettyprint_opcodes(OPCODES *ops) { - if(ops == NULL) - return; - - msg_pdbg("preop0=0x%02x, preop1=0x%02x\n", ops->preop[0], - ops->preop[1]); - OPCODE oc; + const char *t; + const char *a; uint8_t i; + static const char *const spi_type[4] = { + "read w/o addr", + "write w/o addr", + "read w/ addr", + "write w/ addr" + }; + static const char *const atomic_type[3] = { + "none", + " 0 ", + " 1 " + }; + + if (ops == NULL) + return; + + msg_pdbg(" OP Type Pre-OP\n"); for (i = 0; i < 8; i++) { oc = ops->opcode[i]; - msg_pdbg("op[%d]=0x%02x, %d, %d\n", - i, - oc.opcode, - oc.spi_type, - oc.atomic); + t = (oc.spi_type > 3) ? "invalid" : spi_type[oc.spi_type]; + a = (oc.atomic > 2) ? "invalid" : atomic_type[oc.atomic]; + msg_pdbg("op[%d]: 0x%02x, %s, %s\n", i, oc.opcode, t, a); } + msg_pdbg("Pre-OP 0: 0x%02x, Pre-OP 1: 0x%02x\n", ops->preop[0], + ops->preop[1]); } #define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) -- 1.7.1

1 0

[PATCH 3/6] ichspi: don't touch the nonexistent(?) BBAR register on ICH8
by Stefan Tauner 14 Aug '11

14 Aug '11

There is no sign of BBAR (BIOS Base Address Configuration Register) in the public datasheet (or specification update) of the ICH8. Also, the offset of that register has changed between ICH7 (SPIBAR + 50h) and ICH9 (SPIBAR + A0h), so we have no clue if or where it is on ICH8. Better don't try to touch it at all and assume/hope it is 0. --- Until now we implicitly accessed it via the ICH9 offset. I think this is an evident sign that the naming of the spi controller types in ichspi.c (SPI_CONTROLLER_VIA, SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9) might not cut it and we should think about introducing a special ICH8 one, even if its struct is identical to the ICH9. having most of the ICH8 code path guarded/controlled by SPI_CONTROLLER_ICH7 or SPI_CONTROLLER_ICH9 (depending on which is more similar in one situation), is an open invitation to similar bugs because one easily forgets that ICH8 is very special. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 8 +++----- 1 files changed, 3 insertions(+), 5 deletions(-) diff --git a/ichspi.c b/ichspi.c index 85f82fa..daa4a8a 100644 --- a/ichspi.c +++ b/ichspi.c @@ -658,11 +658,6 @@ static int ich_init_opcodes(void) msg_pdbg("Programming OPCODES... "); curopcodes_done = &O_ST_M25P; rc = program_opcodes(curopcodes_done, 1); - /* Technically not part of opcode init, but it allows opcodes - * to run without transaction errors by setting the lowest - * allowed address to zero. - */ - ich_set_bbar(0); } if (rc) { @@ -1269,6 +1264,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } + ich_set_bbar(0); ich_init_opcodes(); break; case SPI_CONTROLLER_ICH9: @@ -1350,6 +1346,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + ich_set_bbar(0); } msg_pdbg("\n"); @@ -1440,6 +1437,7 @@ int via_init_spi(struct pci_dev *dev) ichspi_lock = 1; } + ich_set_bbar(0); ich_init_opcodes(); return 0; -- 1.7.1

1 0

[PATCH 2/6] ichspi: disable writes when locked or read-only regions are detected
by Stefan Tauner 14 Aug '11

14 Aug '11

Until we are able to unlock regions or at least understand better what consequences writing single regions have, disable writing completely whenever a non-writeable region is detected. NB: the registers might not always reflect the real access status. http://www.flashrom.org/pipermail/flashrom/2011-April/006309.html (this is the sole such report i can remember) --- Might not be the best location to do this, but currently i don't recognize a better one. The warnings are repeated for each non-writeable region. We could surpress it by checking if programmer_may_write is already 0 before printing. the output on my thinkpad is: […] Proceeding anyway because user specified laptop=force_I_want_a_brick Found chipset "Intel QS57". Enabling flash write... WARNING: SPI Configuration Lockdown activated. WARNING: Flash Descriptor region is read-only. Disabling writes. WARNING: Management Engine region is locked. Disabling writes. OK. This chipset supports the following protocols: FWH, SPI. Found Winbond flash chip "W25X64" (8192 kB, SPI) at physical address 0xff800000. […] verbose output is: […] 0x54: 0x00000000 (FREG0: Flash Descriptor) 0x00000000-0x00000fff is read-only WARNING: Flash Descriptor region is read-only. Disabling writes. 0x58: 0x07ff0500 (FREG1: BIOS) 0x00500000-0x007fffff is read-write 0x5C: 0x04ff0003 (FREG2: Management Engine) 0x00003000-0x004fffff is locked WARNING: Management Engine region is locked. Disabling writes. 0x60: 0x00020001 (FREG3: Gigabit Ethernet) 0x00001000-0x00002fff is read-write 0x64: 0x00000fff (FREG4: Platform Data) Platform Data region is unused. […] i think that is ok. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- ichspi.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/ichspi.c b/ichspi.c index 611f054..85f82fa 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1169,6 +1169,15 @@ static void do_ich9_spi_frap(uint32_t frap, int i) msg_pdbg("0x%08x-0x%08x is %s\n", base, (limit | 0x0fff), access_names[rwperms]); + if (rwperms <= 0x1) { + msg_pinfo("WARNING: %s region is %s. Disabling writes.\n", + region_names[i], access_names[rwperms]); + /* FIXME: This needs some refinement when we know how unlocking + * of region works. + */ + programmer_may_write = 0; + } + } static const struct spi_programmer spi_programmer_ich7 = { -- 1.7.1

1 0

[PATCH 1/6] ichspi: add ICH/PCH flash descriptor decoding via FDOC/FDOD
by Stefan Tauner 14 Aug '11

14 Aug '11

based on the work of Matthias 'mazzoo' Wenzel this patch adds pretty printing of those ICH/PCH flash descriptor sections that are cached/mapped by the chipset (and which are therefore reachable via FDOC/FDOD registers). this includes the following: - content section: describes the image and some generic properties (number of sections, offset of sections, PCH/ICH and MCH/PROC strap offsets and lengths) - component section: identify the different SPI flash chips and their capabilities. - region section similarly to a partition table this describes the different regions. the content of FLREG* is derived from this section. - master section defines SPI master (host, ME, GbE) access rights of the individual regions. the content of PR* is derived from this section. this is only a part of the data included in the descriptor. other information can be retrieved from a complete binary dump of the descriptor region only. this patch also adds macros and pretty printing for "Vendor Specific Component Capabilities" registers: there are two of them: lower and upper. they describe the properties of the address space divided by FPBA (which allows to use multiple flash chips or partitions with different properties). the properties of all supported flash chips (together with their RDIDs) are stored in the same format in table in a descriptor section (which is used by the ME apparently). a later patch will use the macros outside of ichspi.c which is the reason why the prettyprinting function and the register bit macros are not defined in ichspi.c but ich_descriptors.h (else they would be moved in the follow-up patch). because this patch relies on (compiler) implementation-specific layouting of bit-fields, it checks for basic compiler support in the makefile and for correct layout before taking any action on runtime. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- Makefile | 22 ++++- ich_descriptors.c | 288 +++++++++++++++++++++++++++++++++++++++++++++++++++++ ich_descriptors.h | 261 ++++++++++++++++++++++++++++++++++++++++++++++++ ichspi.c | 60 +++++++++-- 4 files changed, 619 insertions(+), 12 deletions(-) create mode 100644 ich_descriptors.c create mode 100644 ich_descriptors.h diff --git a/Makefile b/Makefile index e0b45ec..930ea4a 100644 --- a/Makefile +++ b/Makefile @@ -340,9 +340,11 @@ endif ifeq ($(CONFIG_INTERNAL), yes) FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' +FEATURE_CFLAGS += $(shell LC_ALL=C grep -q "BITFIELDS := yes" .features && printf "%s" "-D'BITFIELDS=1'") PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o ifeq ($(ARCH),"x86") -PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += it87spi.o it85spi.o sb600spi.o wbsio_spi.o mcp6x_spi.o +PROGRAMMER_OBJS += ichspi.o ich_descriptors.o else endif NEED_PCI := yes @@ -583,6 +585,19 @@ int main(int argc, char **argv) endef export UTSNAME_TEST +define BITFIELDS_TEST +#include "ich_descriptors.h" +int main(int argc, char **argv) +{ + struct ich_descriptors desc; + (void) argc; + (void) argv; + desc.region.FLREGs[4] = 0x5aa5a55a; + return desc.region.reg4_base; +} +endef +export BITFIELDS_TEST + compiler: featuresavailable @printf "Checking for a C compiler... " @echo "$$COMPILER_TEST" > .test.c @@ -648,6 +663,11 @@ endif @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) >/dev/null 2>&1 && \ ( echo "found."; echo "UTSNAME := yes" >> .features.tmp ) || \ ( echo "not found."; echo "UTSNAME := no" >> .features.tmp ) + @printf "Checking if bit-fields support is sufficient... " + @echo "$$BITFIELDS_TEST" > .featuretest.c + @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) -D BITFIELDS .featuretest.c -o .featuretest$(EXEC_SUFFIX) >/dev/null 2>&1 && \ + ( echo "yes."; echo "BITFIELDS := yes" >> .features.tmp ) || \ + ( echo "no."; echo "BITFIELDS := no" >> .features.tmp ) @$(DIFF) -q .features.tmp .features >/dev/null 2>&1 && rm .features.tmp || mv .features.tmp .features @rm -f .featuretest.c .featuretest$(EXEC_SUFFIX) diff --git a/ich_descriptors.c b/ich_descriptors.c new file mode 100644 index 0000000..ce40d9f --- /dev/null +++ b/ich_descriptors.c @@ -0,0 +1,288 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (c) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if defined(__i386__) || defined(__x86_64__) + +#include "ich_descriptors.h" +#include "flash.h" /* for msg_* */ +#include "programmer.h" + +void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity) +{ + print(verbosity, "BES=0x%x, ", (reg_val & VSCC_BES) >> VSCC_BES_OFF); + print(verbosity, "WG=%d, ", (reg_val & VSCC_WG) >> VSCC_WG_OFF); + print(verbosity, "WSR=%d, ", (reg_val & VSCC_WSR) >> VSCC_WSR_OFF); + print(verbosity, "WEWS=%d, ", (reg_val & VSCC_WEWS) >> VSCC_WEWS_OFF); + print(verbosity, "EO=0x%x, ", (reg_val & VSCC_EO) >> VSCC_EO_OFF); + print(verbosity, "VCL=%d\n", (reg_val & VSCC_VCL) >> VSCC_VCL_OFF); +} + +#if BITFIELDS == 1 +#define getFCBA(cont) (((cont)->FLMAP0 << 4) & 0x00000ff0) +#define getFRBA(cont) (((cont)->FLMAP0 >> 12) & 0x00000ff0) +#define getFMBA(cont) (((cont)->FLMAP1 << 4) & 0x00000ff0) +#define getFISBA(cont) (((cont)->FLMAP1 >> 12) & 0x00000ff0) +#define getFMSBA(cont) (((cont)->FLMAP2 << 4) & 0x00000ff0) + +void prettyprint_ich_descriptors(enum ich_chipset cs, const struct ich_descriptors *desc) +{ + prettyprint_ich_descriptor_content(&desc->content); + prettyprint_ich_descriptor_component(desc); + prettyprint_ich_descriptor_region(desc); + prettyprint_ich_descriptor_master(&desc->master); +} + +void prettyprint_ich_descriptor_content(const struct ich_desc_content *cont) +{ + msg_pdbg2("=== Content Section ===\n"); + msg_pdbg2("FLVALSIG 0x%08x\n", cont->FLVALSIG); + msg_pdbg2("FLMAP0 0x%08x\n", cont->FLMAP0); + msg_pdbg2("FLMAP1 0x%08x\n", cont->FLMAP1); + msg_pdbg2("FLMAP2 0x%08x\n", cont->FLMAP2); + msg_pdbg2("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2("NR (Number of Regions): %5d\n", + cont->NR + 1); + msg_pdbg2("FRBA (Flash Region Base Address): 0x%03x\n", + getFRBA(cont)); + msg_pdbg2("NC (Number of Components): %5d\n", + cont->NC + 1); + msg_pdbg2("FCBA (Flash Component Base Address): 0x%03x\n", + getFCBA(cont)); + msg_pdbg2("ISL (ICH/PCH Strap Length): %5d\n", + cont->ISL); + msg_pdbg2("FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x%03x\n", + getFISBA(cont)); + msg_pdbg2("NM (Number of Masters): %5d\n", + cont->NM + 1); + msg_pdbg2("FMBA (Flash Master Base Address): 0x%03x\n", + getFMBA(cont)); + msg_pdbg2("MSL/PSL (MCH/PROC Strap Length): %5d\n", + cont->MSL); + msg_pdbg2("FMSBA (Flash MCH/PROC Strap Base Address): 0x%03x\n", + getFMSBA(cont)); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc) +{ + static const char * const str_freq[8] = { + "20 MHz", /* 000 */ + "33 MHz", /* 001 */ + "reserved", /* 010 */ + "reserved", /* 011 */ + "50 MHz", /* 100 */ + "reserved", /* 101 */ + "reserved", /* 110 */ + "reserved" /* 111 */ + }; + static const char * const str_mem[8] = { + "512 kB", /* 000 */ + " 1 MB", /* 001 */ + " 2 MB", /* 010 */ + " 4 MB", /* 011 */ + " 8 MB", /* 100 */ + " 16 MB", /* 101 */ + "reserved", /* 110 */ + "reserved", /* 111 */ + }; + + msg_pdbg2("=== Component Section ===\n"); + msg_pdbg2("FLCOMP 0x%08x\n", desc->component.FLCOMP); + msg_pdbg2("FLILL 0x%08x\n", desc->component.FLILL ); + msg_pdbg2("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2("Component 1 density: %s\n", + str_mem[desc->component.comp1_density]); + if (desc->content.NC) + msg_pdbg2("Component 2 density: %s\n", + str_mem[desc->component.comp2_density]); + else + msg_pdbg2("Component 2 is not used.\n"); + msg_pdbg2("Read Clock Frequency: %s\n", + str_freq[desc->component.freq_read]); + msg_pdbg2("Read ID and Status Clock Freq.: %s\n", + str_freq[desc->component.freq_read_id]); + msg_pdbg2("Write and Erase Clock Freq.: %s\n", + str_freq[desc->component.freq_write]); + msg_pdbg2("Fast Read is %ssupported.\n", + desc->component.fastread ? "" : "not "); + if (desc->component.fastread) + msg_pdbg2("Fast Read Clock Frequency: %s\n", + str_freq[desc->component.freq_fastread]); + if (desc->component.FLILL == 0) + msg_pdbg2("No forbidden opcodes.\n"); + else { + msg_pdbg2("Invalid instruction 0: 0x%02x\n", + desc->component.invalid_instr0); + msg_pdbg2("Invalid instruction 1: 0x%02x\n", + desc->component.invalid_instr1); + msg_pdbg2("Invalid instruction 2: 0x%02x\n", + desc->component.invalid_instr2); + msg_pdbg2("Invalid instruction 3: 0x%02x\n", + desc->component.invalid_instr3); + } + msg_pdbg2("\n"); +} + +static void pprint_freg(const struct ich_desc_region *reg, uint32_t i) +{ + static const char *const region_names[5] = { + "Descr.", "BIOS", "ME", "GbE", "Platf." + }; + if (i >= 5) { + msg_pdbg2("%s: region index too high.\n", __func__); + return; + } + uint32_t base = ICH_FREG_BASE(reg->FLREGs[i]); + uint32_t limit = ICH_FREG_LIMIT(reg->FLREGs[i]); + msg_pdbg2("Region %d (%-6s) ", i, region_names[i]); + if (base > limit) + msg_pdbg2("is unused.\n"); + else + msg_pdbg2("0x%08x - 0x%08x\n", base, limit | 0x0fff); +} + +void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc) +{ + uint8_t i; + uint8_t nr = desc->content.NR + 1; + msg_pdbg2("=== Region Section ===\n"); + if (nr >= 5) { + msg_pdbg2("%s: number of regions too high (%d).\n", __func__, + nr); + return; + } + for (i = 0; i <= nr; i++) + msg_pdbg2("FLREG%d 0x%08x\n", i, desc->region.FLREGs[i]); + msg_pdbg2("\n"); + + msg_pdbg2("--- Details ---\n"); + for (i = 0; i <= nr; i++) + pprint_freg(&desc->region, i); + msg_pdbg2("\n"); +} + +void prettyprint_ich_descriptor_master(const struct ich_desc_master *mstr) +{ + msg_pdbg2("=== Master Section ===\n"); + msg_pdbg2("FLMSTR1 0x%08x\n", mstr->FLMSTR1); + msg_pdbg2("FLMSTR2 0x%08x\n", mstr->FLMSTR2); + msg_pdbg2("FLMSTR3 0x%08x\n", mstr->FLMSTR3); + msg_pdbg2("\n"); + + msg_pdbg2("--- Details ---\n"); + msg_pdbg2(" Descr. BIOS ME GbE Platf.\n"); + msg_pdbg2("BIOS %c%c %c%c %c%c %c%c %c%c\n", + (mstr->BIOS_descr_r) ?'r':' ', (mstr->BIOS_descr_w) ?'w':' ', + (mstr->BIOS_BIOS_r) ?'r':' ', (mstr->BIOS_BIOS_w) ?'w':' ', + (mstr->BIOS_ME_r) ?'r':' ', (mstr->BIOS_ME_w) ?'w':' ', + (mstr->BIOS_GbE_r) ?'r':' ', (mstr->BIOS_GbE_w) ?'w':' ', + (mstr->BIOS_plat_r) ?'r':' ', (mstr->BIOS_plat_w) ?'w':' '); + msg_pdbg2("ME %c%c %c%c %c%c %c%c %c%c\n", + (mstr->ME_descr_r) ?'r':' ', (mstr->ME_descr_w) ?'w':' ', + (mstr->ME_BIOS_r) ?'r':' ', (mstr->ME_BIOS_w) ?'w':' ', + (mstr->ME_ME_r) ?'r':' ', (mstr->ME_ME_w) ?'w':' ', + (mstr->ME_GbE_r) ?'r':' ', (mstr->ME_GbE_w) ?'w':' ', + (mstr->ME_plat_r) ?'r':' ', (mstr->ME_plat_w) ?'w':' '); + msg_pdbg2("GbE %c%c %c%c %c%c %c%c %c%c\n", + (mstr->GbE_descr_r) ?'r':' ', (mstr->GbE_descr_w) ?'w':' ', + (mstr->GbE_BIOS_r) ?'r':' ', (mstr->GbE_BIOS_w) ?'w':' ', + (mstr->GbE_ME_r) ?'r':' ', (mstr->GbE_ME_w) ?'w':' ', + (mstr->GbE_GbE_r) ?'r':' ', (mstr->GbE_GbE_w) ?'w':' ', + (mstr->GbE_plat_r) ?'r':' ', (mstr->GbE_plat_w) ?'w':' '); + msg_pdbg2("\n"); +} + +static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) +{ + uint32_t control = 0; + control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS; + control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI; + mmio_le_writel(control, spibar + ICH9_REG_FDOC); + return mmio_le_readl(spibar + ICH9_REG_FDOD); +} + +int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc) +{ + uint8_t i; + uint8_t nr; + struct ich_desc_region *r = &desc->region; + + /* Test if bit-fields are working as expected */ + for (i = 0; i < 4; i++) + desc->region.FLREGs[i] = 0x5A << (i * 8); + if (r->reg0_base != 0x005A || r->reg0_limit != 0x0000 || + r->reg1_base != 0x1A00 || r->reg1_limit != 0x0000 || + r->reg2_base != 0x0000 || r->reg2_limit != 0x005A || + r->reg3_base != 0x0000 || r->reg3_limit != 0x1A00) { + msg_pdbg("The combination of compiler and CPU architecture used" + "does not lay out bit-fields as expected, sorry.\n"); + msg_pspew("r->reg0_base = 0x%04X (0x005A)\n", r->reg0_base); + msg_pspew("r->reg0_limit = 0x%04X (0x0000)\n", r->reg0_limit); + msg_pspew("r->reg1_base = 0x%04X (0x1A00)\n", r->reg1_base); + msg_pspew("r->reg1_limit = 0x%04X (0x0000)\n", r->reg1_limit); + msg_pspew("r->reg2_base = 0x%04X (0x0000)\n", r->reg2_base); + msg_pspew("r->reg2_limit = 0x%04X (0x005A)\n", r->reg2_limit); + msg_pspew("r->reg3_base = 0x%04X (0x0000)\n", r->reg3_base); + msg_pspew("r->reg3_limit = 0x%04X (0x1A00)\n", r->reg3_limit); + return RET_ERR; + } + + msg_pdbg2("Reading flash descriptors " + "mapped by the chipset via FDOC/FDOD..."); + /* content section */ + desc->content.FLVALSIG = read_descriptor_reg(0, 0, spibar); + desc->content.FLMAP0 = read_descriptor_reg(0, 1, spibar); + desc->content.FLMAP1 = read_descriptor_reg(0, 2, spibar); + desc->content.FLMAP2 = read_descriptor_reg(0, 3, spibar); + + /* component section */ + desc->component.FLCOMP = read_descriptor_reg(1, 0, spibar); + desc->component.FLILL = read_descriptor_reg(1, 1, spibar); + desc->component.FLPB = read_descriptor_reg(1, 2, spibar); + + /* region section */ + nr = desc->content.NR + 1; + if (nr >= 5) { + msg_pdbg2("%s: number of regions too high (%d) - failed\n", + __func__, nr); + return RET_ERR; + } + for (i = 0; i <= nr; i++) + desc->region.FLREGs[i] = read_descriptor_reg(2, i, spibar); + + /* master section */ + desc->master.FLMSTR1 = read_descriptor_reg(3, 0, spibar); + desc->master.FLMSTR2 = read_descriptor_reg(3, 1, spibar); + desc->master.FLMSTR3 = read_descriptor_reg(3, 2, spibar); + + /* Accessing the strap section via FDOC/D is only possible on ICH8 and + * reading the upper map is impossible on all chipsets, so don't bother. + */ + + msg_pdbg2(" done.\n"); + return RET_OK; +} +#endif /* BITFIELDS == 1 */ +#endif /* defined(__i386__) || defined(__x86_64__) */ diff --git a/ich_descriptors.h b/ich_descriptors.h new file mode 100644 index 0000000..b1da914 --- /dev/null +++ b/ich_descriptors.h @@ -0,0 +1,261 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> + * Copyright (c) 2011 Stefan Tauner + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if defined(__i386__) || defined(__x86_64__) +#ifndef __ICH_DESCRIPTORS_H__ +#define __ICH_DESCRIPTORS_H__ 1 + +#include <stdint.h> + +#define RET_OK 0 +#define RET_ERR -1 +#define RET_WARN -2 +#define RET_PARAM -3 +#define RET_OOB -4 + +#define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */ + /* 0-1: reserved */ +#define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */ +#define FDOC_FDSI (0x3f << FDOC_FDSI_OFF) +#define FDOC_FDSS_OFF 12 /* 12-14: Flash Descriptor Section Select */ +#define FDOC_FDSS (0x3 << FDOC_FDSS_OFF) + /* 15-31: reserved */ + +#define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */ + +/* Field locations and semantics for LVSCC, UVSCC and related words in the flash + * descriptor are equal therefore they all share the same macros below. */ +#define VSCC_BES_OFF 0 /* 0-1: Block/Sector Erase Size */ +#define VSCC_BES (0x3 << VSCC_BES_OFF) +#define VSCC_WG_OFF 2 /* 2: Write Granularity */ +#define VSCC_WG (0x1 << VSCC_WG_OFF) +#define VSCC_WSR_OFF 3 /* 3: Write Status Required */ +#define VSCC_WSR (0x1 << VSCC_WSR_OFF) +#define VSCC_WEWS_OFF 4 /* 4: Write Enable on Write Status */ +#define VSCC_WEWS (0x1 << VSCC_WEWS_OFF) + /* 5-7: reserved */ +#define VSCC_EO_OFF 8 /* 8-15: Erase Opcode */ +#define VSCC_EO (0xff << VSCC_EO_OFF) + /* 16-22: reserved */ +#define VSCC_VCL_OFF 23 /* 23: Vendor Component Lock */ +#define VSCC_VCL (0x1 << VSCC_VCL_OFF) + /* 24-31: reserved */ + +#define ICH_FREG_BASE(flreg) (((flreg) << 12) & 0x01fff000) +#define ICH_FREG_LIMIT(flreg) (((flreg) >> 4) & 0x01fff000) + +/* Used to select the right descriptor printing function. + * Currently only ICH8 and Ibex Peak are supported. + */ +enum ich_chipset { + CHIPSET_ICH_UNKNOWN, + CHIPSET_ICH7 = 7, + CHIPSET_ICH8, + CHIPSET_ICH9, + CHIPSET_ICH10, + CHIPSET_5_SERIES_IBEX_PEAK, + CHIPSET_6_SERIES_COUGAR_POINT, + CHIPSET_7_SERIES_PANTHER_POINT +}; + +void prettyprint_ich_reg_vscc(uint32_t reg_val, int verbosity); + +#if BITFIELDS == 1 +struct ich_desc_content { + uint32_t FLVALSIG; /* 0x00 */ + union { /* 0x04 */ + uint32_t FLMAP0; + struct { + uint32_t FCBA :8, /* Flash Component Base Address */ + NC :2, /* Number Of Components */ + :6, + FRBA :8, /* Flash Region Base Address */ + NR :3, /* Number Of Regions */ + :5; + }; + }; + union { /* 0x08 */ + uint32_t FLMAP1; + struct { + uint32_t FMBA :8, /* Flash Master Base Address */ + NM :3, /* Number Of Masters */ + :5, + FISBA :8, /* Flash ICH Strap Base Address */ + ISL :8; /* ICH Strap Length */ + }; + }; + union { /* 0x0c */ + uint32_t FLMAP2; + struct { + uint32_t FMSBA :8, /* Flash (G)MCH Strap Base Addr. */ + MSL :8, /* MCH Strap Length */ + :16; + }; + }; +}; + +struct ich_desc_component { + union { /* 0x00 */ + uint32_t FLCOMP; /* Flash Components Register */ + struct { + uint32_t comp1_density :3, + comp2_density :3, + :11, + freq_read :3, + fastread :1, + freq_fastread :3, + freq_write :3, + freq_read_id :3, + :2; + }; + }; + union { /* 0x04 */ + uint32_t FLILL; /* Flash Invalid Instructions Register */ + struct { + uint32_t invalid_instr0 :8, + invalid_instr1 :8, + invalid_instr2 :8, + invalid_instr3 :8; + }; + }; + union { /* 0x08 */ + uint32_t FLPB; /* Flash Partition Boundary Register */ + struct { + uint32_t FPBA :13, /* Flash Partition Boundary Addr */ + :19; + }; + }; +}; + +struct ich_desc_region { + union { + uint32_t FLREGs[5]; + struct { + struct { /* FLREG0 Flash Descriptor */ + uint32_t reg0_base :13, + :3, + reg0_limit :13, + :3; + }; + struct { /* FLREG1 BIOS */ + uint32_t reg1_base :13, + :3, + reg1_limit :13, + :3; + }; + struct { /* FLREG2 ME */ + uint32_t reg2_base :13, + :3, + reg2_limit :13, + :3; + }; + struct { /* FLREG3 GbE */ + uint32_t reg3_base :13, + :3, + reg3_limit :13, + :3; + }; + struct { /* FLREG4 Platform */ + uint32_t reg4_base :13, + :3, + reg4_limit :13, + :3; + }; + }; + }; +}; + +struct ich_desc_master { + union { + uint32_t FLMSTR1; + struct { + uint32_t BIOS_req_ID :16, + BIOS_descr_r :1, + BIOS_BIOS_r :1, + BIOS_ME_r :1, + BIOS_GbE_r :1, + BIOS_plat_r :1, + :3, + BIOS_descr_w :1, + BIOS_BIOS_w :1, + BIOS_ME_w :1, + BIOS_GbE_w :1, + BIOS_plat_w :1, + :3; + }; + }; + union { + uint32_t FLMSTR2; + struct { + uint32_t ME_req_ID :16, + ME_descr_r :1, + ME_BIOS_r :1, + ME_ME_r :1, + ME_GbE_r :1, + ME_plat_r :1, + :3, + ME_descr_w :1, + ME_BIOS_w :1, + ME_ME_w :1, + ME_GbE_w :1, + ME_plat_w :1, + :3; + }; + }; + union { + uint32_t FLMSTR3; + struct { + uint32_t GbE_req_ID :16, + GbE_descr_r :1, + GbE_BIOS_r :1, + GbE_ME_r :1, + GbE_GbE_r :1, + GbE_plat_r :1, + :3, + GbE_descr_w :1, + GbE_BIOS_w :1, + GbE_ME_w :1, + GbE_GbE_w :1, + GbE_plat_w :1, + :3; + }; + }; +}; + +struct ich_descriptors { + struct ich_desc_content content; + struct ich_desc_component component; + struct ich_desc_region region; + struct ich_desc_master master; +}; + +void prettyprint_ich_descriptors(enum ich_chipset, const struct ich_descriptors *desc); + +void prettyprint_ich_descriptor_content(const struct ich_desc_content *content); +void prettyprint_ich_descriptor_component(const struct ich_descriptors *desc); +void prettyprint_ich_descriptor_region(const struct ich_descriptors *desc); +void prettyprint_ich_descriptor_master(const struct ich_desc_master *master); + +int read_ich_descriptors_via_fdo(void *spibar, struct ich_descriptors *desc); + +#endif /* BITFIELDS == 1 */ +#endif /* __ICH_DESCRIPTORS_H__ */ +#endif /* defined(__i386__) || defined(__x86_64__) */ diff --git a/ichspi.c b/ichspi.c index 34f0891..611f054 100644 --- a/ichspi.c +++ b/ichspi.c @@ -30,6 +30,7 @@ #include "chipdrivers.h" #include "programmer.h" #include "spi.h" +#include "ich_descriptors.h" /* ICH9 controller register definition */ #define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ @@ -120,6 +121,16 @@ #define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */ #define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */ +#define ICH8_REG_VSCC 0xC1 /* 32 Bits Vendor Specific Component Capabilities */ +#define ICH9_REG_LVSCC 0xC4 /* 32 Bits Host Lower Vendor Specific Component Capabilities */ +#define ICH9_REG_UVSCC 0xC8 /* 32 Bits Host Upper Vendor Specific Component Capabilities */ +/* The individual fields of the VSCC registers are defined in the file + * ich_descriptors.h. The reason is that the same layout is also used in the + * flash descriptor to define the properties of the different flash chips + * supported. The BIOS (or the ME?) is responsible to populate the ICH registers + * with the information from the descriptor on startup depending on the actual + * chip(s) detected. */ + #define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */ #define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */ #define FPB_FPBA (0x1FFF << FPB_FPBA_OFF) @@ -1130,9 +1141,6 @@ static int ich_spi_send_multicommand(struct spi_command *cmds) #define ICH_BRWA(x) ((x >> 8) & 0xff) #define ICH_BRRA(x) ((x >> 0) & 0xff) -#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff) -#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff) - static void do_ich9_spi_frap(uint32_t frap, int i) { static const char *const access_names[4] = { @@ -1159,9 +1167,8 @@ static void do_ich9_spi_frap(uint32_t frap, int i) return; } - msg_pdbg("0x%08x-0x%08x is %s\n", - (base << 12), (limit << 12) | 0x0fff, - access_names[rwperms]); + msg_pdbg("0x%08x-0x%08x is %s\n", base, (limit | 0x0fff), + access_names[rwperms]); } static const struct spi_programmer spi_programmer_ich7 = { @@ -1191,6 +1198,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, uint8_t old, new; uint16_t spibar_offset, tmp2; uint32_t tmp; + int ichspi_desc = 0; switch (ich_generation) { case 7: @@ -1262,6 +1270,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } + if (tmp2 & HSFS_FDV) + ichspi_desc = 1; tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); @@ -1309,12 +1319,40 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, mmio_readl(ich_spibar + ICH9_REG_OPMENU)); msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + ICH9_REG_OPMENU + 4)); - ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); - msg_pdbg("0xA0: 0x%08x (BBAR)\n", - ichspi_bbar); - tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); - msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + if (ich_generation == 8) { + tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC); + msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp); + msg_pdbg("VSCC: "); + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); + } else { + ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); + msg_pdbg("0xA0: 0x%08x (BBAR)\n", + ichspi_bbar); + + tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); + msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); + msg_pdbg("LVSCC: "); + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); + + tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); + msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); + msg_pdbg("UVSCC: "); + prettyprint_ich_reg_vscc(tmp, MSG_DEBUG); + + tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); + msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); + } + msg_pdbg("\n"); +#if BITFIELDS == 1 + if (ichspi_desc) { + struct ich_descriptors desc = {{ 0 }}; + if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == + RET_OK) + prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN, + &desc); + } +#endif /* BITFIELDS == 1 */ ich_init_opcodes(); break; default: -- 1.7.1

1 0

[PATCH 0/6] ichspi 8.0
by Stefan Tauner 14 Aug '11

14 Aug '11

this is based on my makefile patch "Makefile: fix and simplify test program compilations" not sure if it applies without that. 2/6 and 3/6 are new; 4/6 and 5/6 are ~unchanged iirc 1/6 was modified based on carldani's review 6/6 got also a few improvements Stefan Tauner (6): ichspi: add ICH/PCH flash descriptor decoding via FDOC/FDOD ichspi: disable writes when locked or read-only regions are detected ichspi: don't touch the nonexistent(?) BBAR register on ICH8 ichspi: improve prettyprint_opcodes ichspi: add support for Intel Hardware Sequencing Add ich_descriptor_tool to decode all flash descriptors stored in a flash dump file Makefile | 22 +- chipdrivers.h | 6 + flashchips.c | 23 +- flashchips.h | 2 + ich_descriptors.c | 722 ++++++++++++++++++++++ ich_descriptors.h | 466 ++++++++++++++ ichspi.c | 461 +++++++++++++-- programmer.h | 1 + util/ich_descriptors_tool/Makefile | 42 ++ util/ich_descriptors_tool/TODO | 6 + util/ich_descriptors_tool/ich_descriptors_tool.c | 225 +++++++ 11 files changed, 1938 insertions(+), 38 deletions(-) create mode 100644 ich_descriptors.c create mode 100644 ich_descriptors.h create mode 100644 util/ich_descriptors_tool/Makefile create mode 100644 util/ich_descriptors_tool/TODO create mode 100644 util/ich_descriptors_tool/ich_descriptors_tool.c

1 0

MSI k9N6GM-V flashrom -V
by Roman Fuks 14 Aug '11

14 Aug '11

[root@Archlinux romanarch]# flashrom flashrom v0.9.4-r1395 on Linux 3.0-ARCH (x86_64), built with libpci 3.1.7, GCC 4.6.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. sh: dmidecode: no se encontró la orden dmidecode execution unsuccessful - continuing without DMI info Found chipset "NVIDIA MCP61". This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... This chipset is not really supported yet. Guesswork... Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: LPC. No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. [root@Archlinux romanarch]# flashrom -V flashrom v0.9.4-r1395 on Linux 3.0-ARCH (x86_64), built with libpci 3.1.7, GCC 4.6.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 870M loops per second, 10 myus = 11 us, 100 myus = 100 us, 1000 myus = 1010 us, 10000 myus = 10016 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. sh: dmidecode: no se encontró la orden dmidecode execution unsuccessful - continuing without DMI info Found chipset "NVIDIA MCP61" with PCI ID 10de:03e0. This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 Flash bus type is LPC Found SMBus device 10de:03eb at 00:01:1 MCP SPI BAR is at 0xfec80000 Strange. MCP SPI BAR is valid, but chipset apparently doesn't have SPI enabled. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: LPC. Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2 0x06, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0xff, id2 0x06, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0xff, id2 0x06, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0xff, id2 0x06, id1 parity violation, id1 is normal flash content, id2 is normal flash content No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. Restoring PCI config space for 00:01:0 reg 0x6d Restoring PCI config space for 00:01:0 reg 0x90 Restoring PCI config space for 00:01:0 reg 0x8c Restoring PCI config space for 00:01:0 reg 0x88

1 0

[PATCH] Warn about unhandled one-time programmable memory
by Daniel Lenski 14 Aug '11

14 Aug '11

Added feature bit FEATURE_UNHANDLED_OTP, and a warning for chips like AMIC A25L032 and A25LQ032 which contain small regions of one-time programmable memory that flashrom can neither read, nor write, nor erase. Signed-off-by: Daniel Lenski <dlenski(a)gmail.com> --- flash.h | 1 + flashchips.c | 2 ++ flashrom.c | 8 ++++++++ 3 files changed, 11 insertions(+), 0 deletions(-) diff --git a/flash.h b/flash.h index 6f0d7c0..6db4c48 100644 --- a/flash.h +++ b/flash.h @@ -85,6 +85,7 @@ enum chipbustype { #define FEATURE_ADDR_SHIFTED (1 << 5) #define FEATURE_WRSR_EWSR (1 << 6) #define FEATURE_WRSR_WREN (1 << 7) +#define FEATURE_UNHANDLED_OTP (1 << 8) #define FEATURE_WRSR_EITHER (FEATURE_WRSR_EWSR | FEATURE_WRSR_WREN) struct flashchip { diff --git a/flashchips.c b/flashchips.c index efd7599..07b9635 100644 --- a/flashchips.c +++ b/flashchips.c @@ -817,6 +817,7 @@ struct flashchip flashchips[] = { .model_id = AMIC_A25L032, .total_size = 4096, .page_size = 256, + .feature_bits = FEATURE_UNHANDLED_OTP, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -852,6 +853,7 @@ struct flashchip flashchips[] = { .model_id = AMIC_A25LQ032, .total_size = 4096, .page_size = 256, + .feature_bits = FEATURE_UNHANDLED_OTP, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, diff --git a/flashrom.c b/flashrom.c index 2690151..a7471a6 100644 --- a/flashrom.c +++ b/flashrom.c @@ -1434,6 +1434,14 @@ void check_chip_supported(struct flashchip *flash) "Thanks for your help!\n" "===\n"); } + if (flash->feature_bits & FEATURE_UNHANDLED_OTP) { + msg_cinfo("===\n" + "This flash part contains a region of one-time programmable memory\n" + "which flashrom cannot read, and may never be able to write or\n" + "erase. flashrom may not be able to completely backup and rewrite\n" + "the contents of this chip.\n" + "===\n"); + } } int main(int argc, char *argv[]) -- 1.7.0.4

2 1

Re: [flashrom] flashrom on PowerPC
by Peter Lemenkov 13 Aug '11

13 Aug '11

2011/7/27 Mattias Mattsson <vitplister(a)gmail.com>: > Hi all, > > I was able to run flashrom under Linux on PPC (big endian) hardware > with two small modifications in internal.c and processor_enable.c (see > attached patch). Not sure if this is the right way to do it but it > seems to work for me. > > Note that for Apple hardware you have to use a special power on method > to make the flash chip accessible (hold power button until beep). On > some models you have to press and hold an additional button on the > machine ("programmer's button") or keyboard ("Command"). > http://support.apple.com/kb/HT2322 > http://support.apple.com/kb/DL1284 > http://support.apple.com/kb/DL1126 > > I have tested this on two pieces of Apple hardware: "Mac Mini" (model > ID: PowerMac10,1) and "Mac mini (Late 2005)" (model ID: PowerMac10,2): > http://support.apple.com/kb/ht3476 > > By taking the hardware apart I can confirm they have the following flash chips: > > PowerMac10,1: AMD Am29LV008BB-90EC > PowerMac10,2: SHARP LH28F008BJT-BTLZ1 > > Flash chips seem to be mapped top-aligned in the 4GB address space. > Looking at the Open Firmware forth code inside Apple's own firmware > updates also suggests this is the case. > > I was able to probe, read, write and erase on both machines. Read > files seem to contain valid data. > > Added support for LH28F008BJT-BTLZ1 and marked Am29LV008B as fully tested. What's the status of these patches? Could anyone ACK them? -- With best regards, Peter Lemenkov.

1 0

Initial version of autotools support for Flashrom
by Peter Lemenkov 13 Aug '11

13 Aug '11

Hello All. Some time ago I mentioned that I've got patches for full autotools support - here is the first patch in a patchset for your further consideration: https://github.com/lemenkov/flashrom/commits/autotools It was tested on RHEL 5, 6, Fedora 1x, i386, i586, i686, x86_64 and ppc (I'm using it for building Flashrom's RPM for a half of the year at least). It's rebased on top of svn1412 and cleaned up to be a full drop-in replacement for handmade Makefile. Unfortunately I didn't test in on anything else than Linux, so I must admit that it's not in a very good shape for MinGW / BSD / DOS / Darwin users (ARM, MIPS users could be also hurt as well - that's why I didn't touch anything else in this commit except adding these two files). -- With best regards, Peter Lemenkov.

1 0

Re: [flashrom] [PATCH] Makefile: fix and simplify test program compilations
by Stefan Tauner 13 Aug '11

13 Aug '11

On Fri, 12 Aug 2011 21:38:37 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > side note: we use $(CC) all over the place before we even check if > it is there. e.g.: > override ARCH = $(strip $(shell LC_ALL=C $(CC) -E arch.h|grep -v '^\#')) > > this creates unwanted output like: > make -j1 CC=eiugthes > /bin/sh: eiugthes: not found > /bin/sh: eiugthes: not found > /bin/sh: eiugthes: not found > /bin/sh: eiugthes: not found > Checking for a C compiler... not found. > make: *** [compiler] Error 1 actually it is only this one line that creates the output. the reason it executes the command 4 times instead of caching it is the use of "=" instead of ":=", see http://www.gnu.org/s/hello/manual/make/Flavors.html#Flavors i have added the : to the ARCH definition, but it does not solve the underlying problem that it is executed before the compiler test: make -j1 CC=eiugthes /bin/sh: eiugthes: not found Checking for a C compiler... not found. make: *** [compiler] Error 1 -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

Re: [flashrom] [PATCH] Makefile: fix and simplify test program compilations
by Stefan Tauner 13 Aug '11

13 Aug '11

On Fri, 12 Aug 2011 21:38:37 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > +define COMPILER_TEST > +int main(int argc, char **argv) > +{ > + (void) argafc; testing leftovers, fixed locally... -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

Message levels and content
by Carl-Daniel Hailfinger 12 Aug '11

12 Aug '11

Hi, it has become quite obvious that there are different views about how much output flashrom should provide at default verbosity. I'd like to keep line count down, but at the same time I acknowledge that long-running operations need some user feedback. Those goals are not easily reconcilable and there will be some friction. Others would like to upgrade the message levels of quite a few messages and introduce a separate quiet mode which is less verbose than default mode. Given that this dicussion revolves around the UI and different people expect different things, I don't want to "solve" this by decree. Instead, I hope for consensus. We definitely need to reach a decision, but maybe we can do this with the help of use cases and by examining typical flashrom output. I'm sure there is some low-hanging fruit where the message content/level can be adjusted and where people agree on the changes. Regards, Carl-Daniel -- http://www.hailfinger.org/

3 8

[PATCH] Fix all ASUS P5GD* board enables
by Stefan Tauner 12 Aug '11

12 Aug '11

Changes related to P5GD1 variants: - Reorder "P5GD1 Pro" in print.c and include a DMI patter to its board enable - Add an untested "P5GD1(-VM)" board enable and add an entry to print.c Changes related to P5GD(2/C) variants: - Fix the name of "P5GDC-V Deluxe" board enable and add a DMI pattern and print.c entry. NB: there is no "P5GDC-V" board. - Add a generic match for P5GD(2/C)* boards with a not tested tag. This are the potential targets for this according to the asus ftp: ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/ Unsupported variants of the P5GD2: P5GD2, P5GD2 Deluxe, P5GD2 Pro, P5GD2-X (P5GD2 Premium is already tested) (there seems to be also a P5GD2-TVM/GB/SI in the wild, which is not known to asus :) Unsupported variants of the P5GDC: P5GDC Pro, P5GDC-MX (P5GDC Deluxe and P5GDC-V Deluxe are already tested) References: P5GD1 PRO (dmi "P5GD1 PRO") smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, *0x814e* http://www.coreboot.org/pipermail/flashrom/2010-August/004539.html P5GD1 (dmi "P5GD1") The non-pro version seems to match the pro pci pattern, but could be distinguished by the SATA ID of 1043:2604 vs. 1043:2601: https://launchpadlibrarian.net/62167576/Lspci.txt or a DMI pattern of course. P5GD1-VM (dmi "P5GD1-VM") This does also match the current PCI IDs. https://bugs.launchpad.net/ubuntu/+source/linux/+bug/465379 - P5GD2 Premium (dmi "P5GD2-Premium") smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, 0x813d http://www.flashrom.org/pipermail/flashrom/2010-August/004555.html - P5GDC-V Deluxe (dmi "P5GDC-V") smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, 0x813d http://www.flashrom.org/pipermail/flashrom/2010-September/004939.html - P5GDC Deluxe (dmi "P5GDC") smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, 0x813d http://www.flashrom.org/pipermail/flashrom/2010-September/004684.html - P5GDC Pro, P5GDC-MX, P5GD2-X, P5GD2 Pro, P5GD2 no useful logs found - P5GD2-Deluxe (dmi "P5GD2-Deluxe") smbus: 0x8086, 0x266a, 0x1043, 0x80a6; audio: 0x8086, 0x2668, 0x1043, 0x813d https://bugs.launchpad.net/ubuntu/+source/foomatic-filters/+bug/572514 - P5GD2-TVM/GB/SI (dmi "P5GD2-TVM/GB/SI") smbus: 0x8086, 0x266a, 0x1043, 0x266a; audio: 0x8086, 0x2668, 0x1043, *0x81a7* https://bugs.launchpad.net/ubuntu/+source/linux/+bug/462500 Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- adding tested board enable with exact matches for identified and tested boards and NT board enables for potentially compatible boards should be the scheme to be used in the future for all mainboard families instead of adding an uncertain generic board enable or none at all (just because the user does not reply). The policy should be to add board enables as soon as they become available or at least no longer than a week after posting it, even without success reports. Rationale: This scheme guarantees that we get success reports for untested boards which allows us to combine them later when we are sure (enough). OTOH it allows users to easily test the yet unsupported boards without recompiling by forcing the generic board enables. And it keeps the patch queue short. Investigating all of the above was certainly not worth it on its own and id suggest to avoid similar efforts in the future by following the scheme :) --- board_enable.c | 7 +++++-- print.c | 5 ++++- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/board_enable.c b/board_enable.c index aba6f38..ab9aff4 100644 --- a/board_enable.c +++ b/board_enable.c @@ -2022,9 +2022,12 @@ const struct board_pciid_enable board_pciid_enables[] = { {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, P3, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise}, {0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x5513, 0x1043, 0x8087, NULL, NULL, NULL, P3, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", P3, "ASUS", "P5A", 0, OK, board_asus_p5a}, - {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, P3, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, "^P5GD1 PRO$", NULL, NULL, P3, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, P3, "ASUS", "P5GD1(-VM)", 0, NT, intel_ich_gpio21_raise}, {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GD2-Premium$", NULL, NULL, P3, "ASUS", "P5GD2 Premium", 0, OK, intel_ich_gpio21_raise}, - {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, P3, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GDC-V$", NULL, NULL, P3, "ASUS", "P5GDC-V Deluxe", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GDC$", NULL, NULL, P3, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, P3, "ASUS", "P5GD2/C variants", 0, NT, intel_ich_gpio21_raise}, {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, NT, intel_ich_gpio16_raise}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, P3, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, P3, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise}, diff --git a/print.c b/print.c index 21b4570..dfee33d 100644 --- a/print.c +++ b/print.c @@ -479,12 +479,15 @@ const struct board_info boards_known[] = { B("ASUS", "P5B-Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=bswT66IBSb2rEWNa", NULL), B("ASUS", "P5BV-M", 0, "ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/P5B-VM/", "Reported by Bernhard M. Wiedemann <bernhard(a)uml12d.zq1.de> to flashrom(a)coreboot.org, no public archive. Missing board enable and/or SST49LF008A unlocking. May work now."), B("ASUS", "P5GC-MX/1333", 1, "http://www.asus.com/product.aspx?P_ID=PYvbfOokwxUzJky3", NULL), + B("ASUS", "P5GD1 Pro", 1, "http://www.asus.com/product.aspx?P_ID=50M49xQh71EZOeM1", NULL), + B("ASUS", "P5GD1(-VM)", 0, NULL, "Untested board enable."), B("ASUS", "P5GD2 Premium", 1, "http://www.asus.it/product.aspx?P_ID=lRKaz1Rb6Xb0OFM7", NULL), B("ASUS", "P5GDC Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=AbeoopyNpI2TZixg", NULL), + B("ASUS", "P5GDC-V Deluxe", 1, NULL, NULL), + B("ASUS", "P5GD2/C variants", 0, NULL, "Untested board enable."), B("ASUS", "P5KC", 1, "http://www.asus.com/product.aspx?P_ID=fFZ8oUIGmLpwNMjj", NULL), B("ASUS", "P5L-MX", 1, "http://www.asus.com/product.aspx?P_ID=X70d3NCzH2DE9vWH", NULL), B("ASUS", "P5LD2", 0, NULL, "Untested board enable."), - B("ASUS", "P5GD1 Pro", 1, "http://www.asus.com/product.aspx?P_ID=50M49xQh71EZOeM1", NULL), B("ASUS", "P5N-E SLI", 0, "http://www.asus.com/product.aspx?P_ID=KyHOsOKWujC2QguJ", "Needs a board enable (http://patchwork.coreboot.org/patch/3298/)."), B("ASUS", "P5N32-E SLI", 1, "http://www.asus.com/product.aspx?P_ID=vBZLIBtPzYB2bLcb", NULL), B("ASUS", "P5ND2-SLI Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=WY7XroDuUImVbgp5", NULL), -- 1.7.1

1 0

SuperMicro X8DTU-6TF+: flashrom -Vr failed
by Scott Silverman 12 Aug '11

12 Aug '11

# ./flashrom -Vr ../current.bios flashrom v0.9.4-r1412 on Linux 2.6.29.6-sxtickless (x86_64), built with libpci 3.1.7, GCC 4.1.2 20080704 (Red Hat 4.1.2-50), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1523M loops per second, 10 myus = 11 us, 100 myus = 100 us, 1000 myus = 998 us, 10000 myus = 9990 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Supermicro" DMI string system-product-name: "X8DTU-6+" DMI string system-version: "1234567890" DMI string baseboard-manufacturer: "Supermicro" DMI string baseboard-product-name: "X8DTU-6+" DMI string baseboard-version: "2.01" DMI string chassis-type: "Main Server Chassis" Found chipset "Intel ICH10R" with PCI ID 8086:3a16. Enabling flash write... 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x4 0x7fffffff/0x7fffffff FWH IDSEL: 0x5 0x7fffffff/0x7fffffff FWH IDSEL: 0x6 0x7fffffff/0x7fffffff FWH IDSEL: 0x7 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 Root Complex Register Block address = 0xfed1c000 GCS = 0x460: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0x6008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=0 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00002000 (FADDR) 0x50: 0x00001a1b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x1a, BRRA 0x1b 0x54: 0x00010000 (FREG0: Flash Descriptor) 0x00000000-0x00001fff is read-only 0x58: 0x03ff0200 (FREG1: BIOS) 0x00200000-0x003fffff is read-write 0x5C: 0x01ff0002 (FREG2: Management Engine) 0x00002000-0x001fffff is locked 0x60: 0x00001fff (FREG3: Gigabit Ethernet) Gigabit Ethernet region is unused. 0x64: 0x00001fff (FREG4: Platform Data) Platform Data region is unused. 0x74: 0x00000000 (PR0) 0x78: 0x00000000 (PR1) 0x7C: 0x00000000 (PR2) 0x80: 0x00000000 (PR3) 0x84: 0x00000000 (PR4) 0x90: 0x04 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0x000000 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=0 0x94: 0x3906 (PREOP) 0x96: 0xd43b (OPTYPE) 0x98: 0x05200302 (OPMENU) 0x9C: 0x3906019f (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xD0: 0x00000000 (FPB) Programming OPCODES... program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190 done preop0=0x06, preop1=0x50 op[0]=0x02, 3, 0 op[1]=0x03, 2, 0 op[2]=0xd8, 3, 0 op[3]=0x05, 0, 0 op[4]=0x90, 2, 0 op[5]=0x01, 1, 0 op[6]=0x9f, 0, 0 op[7]=0xc7, 1, 0 SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Chip status register is 10 Found Atmel flash chip "AT25DF321A" (4096 kB, SPI) at physical address 0xffc00000. Ignoring security lockdown (if present) Ignoring status register byte 2 Chip status register is 10 Chip status register: Sector Protection Register Lock (SRPL) is not set Chip status register: Bit 6 is not set Chip status register: Erase/Program Error (EPE) is not set Chip status register: WP# pin (WPP) is not asserted Chip status register: Software Protection Status (SWP): no sectors are protected Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x2f, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x2f, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for SST SST25VF010.REMS, 128 kB: probe_spi_rems: id1 0xff, id2 0xff Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for SST SST25VF040.REMS, 512 kB: probe_spi_rems: id1 0xff, id2 0xff Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for SST SST25LF040A.RES, 512 kB: program_opcodes: preop=5006 optype=462b opmenu=05ab0302c79f0190 on-the-fly OPCODE (0xAB) re-programmed, op-pos=2 probe_spi_res2: id1 0xff, id2 0xff Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xff, id2 0xff Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x2f, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x2f, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x80, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for ST M25P05.RES, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for ST M25P10.RES, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x2f, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x2f, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0x80, id2 0x00, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x2f, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x2f, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x2f, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x2f, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x41, id2 0x4d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x2f, id2 0x57, id1 is normal flash content, id2 is normal flash content Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4701 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xff, id2 0xff === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Ignoring security lockdown (if present) Reading flash... Transaction error! SSFS: SCIP=0, FDONE=1, FCERR=1, AEL=0 SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=63, SME=0, SCF=0 Running OPCODE 0x03 failed at address 0x002000 (payload length was 64). Read operation failed! FAILED. Restoring MMIO space at 0x7fe44a3648a0 Restoring MMIO space at 0x7fe44a36489c Restoring MMIO space at 0x7fe44a364898 Restoring MMIO space at 0x7fe44a364896 Restoring MMIO space at 0x7fe44a364894 Restoring PCI config space for 00:1f:0 reg 0xdc

1 0

[PATCH] Makefile: fix and simplify test program compilations
by Stefan Tauner 12 Aug '11

12 Aug '11

this was totally broken due to the time behavior of make's shell function's temporal behavior. quote from the gnu make documentation http://www.gnu.org/s/hello/manual/make/Shell-Function.html): "The commands run by calls to the shell function are run when the function calls are expanded" we have used the shell function to echo the test programs to a file. the file name used was equal for all tests and was overwritten for each test. the result was that all tests (in a single target?) used the last test program because the echoing of the test programs was done before all test compilations(!) also the branching for testing ifeq ($(CONFIG_FT2232_SPI), yes) was unnecessary. in my approach here i am using verbatim variables (allows to define even complex test programs in the makefile without jumping through hoops) that get exported to environment variables (via "export", reference afterwards with "$$<varname>"). i have also added the missing redirection of stderr to the compiler test. --- alternatively one could just use different file names of course, but i think my approach is superior due to the separation and readability of the tested code and the fact that the temporal behavior is MUCH clearer now (else this bug would have not crept in in the first place :P) if line count is an issue one could of course compress the test programs to something unreadable again :) side note: we use $(CC) all over the place before we even check if it is there. e.g.: override ARCH = $(strip $(shell LC_ALL=C $(CC) -E arch.h|grep -v '^\#')) this creates unwanted output like: make -j1 CC=eiugthes /bin/sh: eiugthes: not found /bin/sh: eiugthes: not found /bin/sh: eiugthes: not found /bin/sh: eiugthes: not found Checking for a C compiler... not found. make: *** [compiler] Error 1 Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- Makefile | 91 ++++++++++++++++++++++++++++++++++++++++---------------------- 1 files changed, 59 insertions(+), 32 deletions(-) diff --git a/Makefile b/Makefile index c72d10a..672a0df 100644 --- a/Makefile +++ b/Makefile @@ -531,11 +531,62 @@ distclean: clean strip: $(PROGRAM)$(EXEC_SUFFIX) $(STRIP) $(STRIP_ARGS) $(PROGRAM)$(EXEC_SUFFIX) +# below are the definitions of test programs as verbatim variables, which get +# exported to environment variables and are referenced with $$<varname> later +define COMPILER_TEST +int main(int argc, char **argv) +{ + (void) argafc; + (void) argv; + return 0; +} +endef +export COMPILER_TEST + +define LIBPCI_TEST +/* Avoid a failing test due to libpci header symbol shadowing breakage */ +#define index shadow_workaround_index +#include <pci/pci.h> +struct pci_access *pacc; +int main(int argc, char **argv) +{ + (void) argc; + (void) argv; + pacc = pci_alloc(); + return 0; +} +endef +export LIBPCI_TEST + +define FTDI_TEST +#include <ftdi.h> +struct ftdi_context *ftdic = NULL; +int main(int argc, char **argv) +{ + (void) argc; + (void) argv; + return ftdi_init(ftdic); +} +endef +export FTDI_TEST + +define UTSNAME_TEST +#include <sys/utsname.h> +struct utsname osinfo; +int main(int argc, char **argv) +{ + (void) argc; + (void) argv; + uname (&osinfo); + return 0; +} +endef +export UTSNAME_TEST + compiler: featuresavailable @printf "Checking for a C compiler... " - @$(shell ( echo "int main(int argc, char **argv)"; \ - echo "{ (void) argc; (void) argv; return 0; }"; ) > .test.c ) - @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .test.c -o .test$(EXEC_SUFFIX) >/dev/null && \ + @echo "$$COMPILER_TEST" > .test.c + @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .test.c -o .test$(EXEC_SUFFIX) >/dev/null 2>&1 && \ echo "found." || ( echo "not found."; \ rm -f .test.c .test$(EXEC_SUFFIX); exit 1) @rm -f .test.c .test$(EXEC_SUFFIX) @@ -548,12 +599,7 @@ compiler: featuresavailable ifeq ($(CHECK_LIBPCI), yes) pciutils: compiler @printf "Checking for libpci headers... " - @# Avoid a failing test due to libpci header symbol shadowing breakage - @$(shell ( echo "#define index shadow_workaround_index"; \ - echo "#include <pci/pci.h>"; \ - echo "struct pci_access *pacc;"; \ - echo "int main(int argc, char **argv)"; \ - echo "{ (void) argc; (void) argv; pacc = pci_alloc(); return 0; }"; ) > .test.c ) + @echo "$$LIBPCI_TEST" > .test.c @$(CC) -c $(CPPFLAGS) $(CFLAGS) .test.c -o .test.o >/dev/null 2>&1 && \ echo "found." || ( echo "not found."; echo; \ echo "Please install libpci headers (package pciutils-devel)."; \ @@ -588,41 +634,22 @@ featuresavailable: @false endif -ifeq ($(CONFIG_FT2232_SPI), yes) features: compiler @echo "FEATURES := yes" > .features.tmp +ifeq ($(CONFIG_FT2232_SPI), yes) @printf "Checking for FTDI support... " - @$(shell ( echo "#include <ftdi.h>"; \ - echo "struct ftdi_context *ftdic = NULL;"; \ - echo "int main(int argc, char **argv)"; \ - echo "{ (void) argc; (void) argv; return ftdi_init(ftdic); }"; ) > .featuretest.c ) + @echo "$$FTDI_TEST" > .featuretest.c @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) $(FTDILIBS) $(LIBS) >/dev/null 2>&1 && \ ( echo "found."; echo "FTDISUPPORT := yes" >> .features.tmp ) || \ ( echo "not found."; echo "FTDISUPPORT := no" >> .features.tmp ) +endif @printf "Checking for utsname support... " - @$(shell ( echo "#include <sys/utsname.h>"; \ - echo "struct utsname osinfo;"; \ - echo "int main(int argc, char **argv)"; \ - echo "{ (void) argc; (void) argv; uname (&osinfo); return 0; }"; ) > .featuretest.c ) - @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) >/dev/null 2>&1 && \ - ( echo "found."; echo "UTSNAME := yes" >> .features.tmp ) || \ - ( echo "not found."; echo "UTSNAME := no" >> .features.tmp ) - @$(DIFF) -q .features.tmp .features >/dev/null 2>&1 && rm .features.tmp || mv .features.tmp .features - @rm -f .featuretest.c .featuretest$(EXEC_SUFFIX) -else -features: compiler - @echo "FEATURES := yes" > .features.tmp - @printf "Checking for utsname support... " - @$(shell ( echo "#include <sys/utsname.h>"; \ - echo "struct utsname osinfo;"; \ - echo "int main(int argc, char **argv)"; \ - echo "{ (void) argc; (void) argv; uname (&osinfo); return 0; }"; ) > .featuretest.c ) + @echo "$$UTSNAME_TEST" > .featuretest.c @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) >/dev/null 2>&1 && \ ( echo "found."; echo "UTSNAME := yes" >> .features.tmp ) || \ ( echo "not found."; echo "UTSNAME := no" >> .features.tmp ) @$(DIFF) -q .features.tmp .features >/dev/null 2>&1 && rm .features.tmp || mv .features.tmp .features @rm -f .featuretest.c .featuretest$(EXEC_SUFFIX) -endif install: $(PROGRAM)$(EXEC_SUFFIX) mkdir -p $(DESTDIR)$(PREFIX)/sbin -- 1.7.1

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reading the bios on an asus P5VD2-MX
by Kurt Jaeger 12 Aug '11

12 Aug '11

Hi! See below. flashrom v0.9.3-r1205 on FreeBSD 8.1-RELEASE (i386), built with libpci 3.1.7, GCC 4.2.1 20070719 [FreeBSD], little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 2033M loops per second, 10 myus = 12 us, 100 myus = 101 us, 1000 myus = 1001 us, 10000 myus = 10002 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: " " DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "P5VD2-MX" DMI string baseboard-version: "1.XX" DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8712. Found chipset "VIA VT8237A", enabling flash write... chipset PCI ID is 1106:3337, OK. This chipset supports the following protocols: Non-SPI. Super I/O ID 0x8712 is not on the list of flash capable controllers. Probing for AMD Am29F010A/B, 128 KB: probe_jedec_common: id1 0x00, id2 0x0c, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec_common: id1 0x5a, id2 0xd3, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec_common: id1 0x5a, id2 0xd3, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x21, id2 0x72, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x21, id2 0x72, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A25L05PT, 64 KB: skipped. Probing for AMIC A25L05PU, 64 KB: skipped. Probing for AMIC A25L10PT, 128 KB: skipped. Probing for AMIC A25L10PU, 128 KB: skipped. Probing for AMIC A25L20PT, 256 KB: skipped. Probing for AMIC A25L20PU, 256 KB: skipped. Probing for AMIC A25L40PT, 512 KB: skipped. Probing for AMIC A25L40PU, 512 KB: skipped. Probing for AMIC A25L80P, 1024 KB: skipped. Probing for AMIC A25L16PT, 2048 KB: skipped. Probing for AMIC A25L16PU, 2048 KB: skipped. Probing for AMIC A25L512, 64 KB: skipped. Probing for AMIC A25L010, 128 KB: skipped. Probing for AMIC A25L020, 256 KB: skipped. Probing for AMIC A25L040, 512 KB: skipped. Probing for AMIC A25L080, 1024 KB: skipped. Probing for AMIC A25L016, 2048 KB: skipped. Probing for AMIC A25L032, 4096 KB: skipped. Probing for AMIC A25LQ032, 4096 KB: skipped. Probing for AMIC A29002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x5a, id2 0xd3, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x5a, id2 0xd3, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x21, id2 0x72, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Atmel AT25DF021, 256 KB: skipped. Probing for Atmel AT25DF041A, 512 KB: skipped. Probing for Atmel AT25DF081, 1024 KB: skipped. Probing for Atmel AT25DF081A, 1024 KB: skipped. Probing for Atmel AT25DF161, 2048 KB: skipped. Probing for Atmel AT25DF321, 4096 KB: skipped. Probing for Atmel AT25DF321A, 4096 KB: skipped. Probing for Atmel AT25DF641, 8192 KB: skipped. Probing for Atmel AT25DQ161, 2048 KB: skipped. Probing for Atmel AT25F512B, 64 KB: skipped. Probing for Atmel AT25FS010, 128 KB: skipped. Probing for Atmel AT25FS040, 512 KB: skipped. Probing for Atmel AT26DF041, 512 KB: skipped. Probing for Atmel AT26DF081A, 1024 KB: skipped. Probing for Atmel AT26DF161, 2048 KB: skipped. Probing for Atmel AT26DF161A, 2048 KB: skipped. Probing for Atmel AT26F004, 512 KB: skipped. Probing for Atmel AT29C512, 64 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Atmel AT29C010A, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Atmel AT29C020, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Atmel AT29C040A, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Atmel AT45CS1282, 16896 KB: skipped. Probing for Atmel AT45DB011D, 128 KB: skipped. Probing for Atmel AT45DB021D, 256 KB: skipped. Probing for Atmel AT45DB041D, 512 KB: skipped. Probing for Atmel AT45DB081D, 1024 KB: skipped. Probing for Atmel AT45DB161D, 2048 KB: skipped. Probing for Atmel AT45DB321C, 4224 KB: skipped. Probing for Atmel AT45DB321D, 4096 KB: skipped. Probing for Atmel AT45DB642D, 8192 KB: skipped. Probing for Atmel AT49BV512, 64 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Atmel AT49F020, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Atmel AT49F002(N), 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Bright BM29F040, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for EMST F49B002UA, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for EMST F25L008A, 1024 KB: skipped. Probing for Eon EN25B05, 64 KB: skipped. Probing for Eon EN25B05T, 64 KB: skipped. Probing for Eon EN25B10, 128 KB: skipped. Probing for Eon EN25B10T, 128 KB: skipped. Probing for Eon EN25B20, 256 KB: skipped. Probing for Eon EN25B20T, 256 KB: skipped. Probing for Eon EN25B40, 512 KB: skipped. Probing for Eon EN25B40T, 512 KB: skipped. Probing for Eon EN25B80, 1024 KB: skipped. Probing for Eon EN25B80T, 1024 KB: skipped. Probing for Eon EN25B16, 2048 KB: skipped. Probing for Eon EN25B16T, 2048 KB: skipped. Probing for Eon EN25B32, 4096 KB: skipped. Probing for Eon EN25B32T, 4096 KB: skipped. Probing for Eon EN25B64, 8192 KB: skipped. Probing for Eon EN25B64T, 8192 KB: skipped. Probing for Eon EN25D16, 2048 KB: skipped. Probing for Eon EN25F05, 64 KB: skipped. Probing for Eon EN25F10, 128 KB: skipped. Probing for Eon EN25F20, 256 KB: skipped. Probing for Eon EN25F40, 512 KB: skipped. Probing for Eon EN25F80, 1024 KB: skipped. Probing for Eon EN25F16, 2048 KB: skipped. Probing for Eon EN25F32, 4096 KB: skipped. Probing for Eon EN29F010, 128 KB: probe_jedec_common: id1 0x00, id2 0x0c, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)B, 256 KB: probe_jedec_common: id1 0x5a, id2 0xd3, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN29F002(A)(N)T, 256 KB: probe_jedec_common: id1 0x5a, id2 0xd3, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 KB: probe_jedec_common: id1 0x21, id2 0x72, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 KB: probe_jedec_common: id1 0x21, id2 0x72, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0x21, id2 0x2d Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0x21, id2 0x2d Probing for Hyundai HY29F002T, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Hyundai HY29F002B, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Hyundai HY29F040A, 512 KB: probe_jedec_common: id1 0x21, id2 0x72, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BN/BX-B, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Intel 28F001BN/BX-T, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Intel 28F002BC/BL/BV/BX-T, 256 KB: probe_82802ab: id1 0x5a, id2 0xd3, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F008S3/S5/SC, 512 KB: probe_82802ab: id1 0x21, id2 0x72, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-B, 512 KB: probe_82802ab: id1 0x21, id2 0x72, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004B5/BE/BV/BX-T, 512 KB: probe_82802ab: id1 0x21, id2 0x72, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-B, 512 KB: probe_82802ab: id1 0x21, id2 0x2d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F400BV/BX/CE/CV-T, 512 KB: probe_82802ab: id1 0x21, id2 0x2d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x21, id2 0x72, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 KB: skipped. Probing for Macronix MX25L1005, 128 KB: skipped. Probing for Macronix MX25L2005, 256 KB: skipped. Probing for Macronix MX25L4005, 512 KB: skipped. Probing for Macronix MX25L8005, 1024 KB: skipped. Probing for Macronix MX25L1605, 2048 KB: skipped. Probing for Macronix MX25L1635D, 2048 KB: skipped. Probing for Macronix MX25L1635E, 2048 KB: skipped. Probing for Macronix MX25L3205, 4096 KB: skipped. Probing for Macronix MX25L3235D, 4096 KB: skipped. Probing for Macronix MX25L6405, 8192 KB: skipped. Probing for Macronix MX25L12805, 16384 KB: skipped. Probing for Macronix MX29F001B, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x00, id2 0x0c, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x00, id2 0x0c, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x5a, id2 0xd3, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x5a, id2 0xd3, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F040, 512 KB: probe_jedec_common: id1 0x21, id2 0x72, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x21, id2 0x72, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for MoselVitelic V29C51000B, 64 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for MoselVitelic V29C51000T, 64 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for MoselVitelic V29C51400B, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for MoselVitelic V29C51400T, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for MoselVitelic V29LC51000, 64 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for MoselVitelic V29LC51001, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for MoselVitelic V29LC51002, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Numonyx M25PE10, 128 KB: skipped. Probing for Numonyx M25PE20, 256 KB: skipped. Probing for Numonyx M25PE40, 512 KB: skipped. Probing for Numonyx M25PE80, 1024 KB: skipped. Probing for Numonyx M25PE16, 2048 KB: skipped. Probing for PMC Pm25LV010, 128 KB: skipped. Probing for PMC Pm25LV016B, 2048 KB: skipped. Probing for PMC Pm25LV020, 256 KB: skipped. Probing for PMC Pm25LV040, 512 KB: skipped. Probing for PMC Pm25LV080B, 1024 KB: skipped. Probing for PMC Pm25LV512, 64 KB: skipped. Probing for PMC Pm29F002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x5a, id2 0xd3, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x5a, id2 0xd3, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 KB: probe_jedec_common: id1 0x00, id2 0x0c, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV020, 256 KB: probe_jedec_common: id1 0x5a, id2 0xd3, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV040, 512 KB: probe_jedec_common: id1 0x21, id2 0x72, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Sanyo LF25FW203A, 2048 KB: skipped. Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL008A, 1024 KB: skipped. Probing for Spansion S25FL016A, 2048 KB: skipped. Probing for SST SST25VF016B, 2048 KB: skipped. Probing for SST SST25VF032B, 4096 KB: skipped. Probing for SST SST25VF064C, 8192 KB: skipped. Probing for SST SST25VF040.REMS, 512 KB: skipped. Probing for SST SST25VF040B, 512 KB: skipped. Probing for SST SST25LF040A.RES, 512 KB: skipped. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Probing for SST SST25VF080B, 1024 KB: skipped. Probing for SST SST28SF040A, 512 KB: probe_82802ab: id1 0x21, id2 0x72, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE010, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST29LE010, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST29EE020A, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST29LE020, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST39SF512, 64 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST39SF010A, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST39SF020A, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST39SF040, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST39VF512, 64 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST39VF010, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST39VF020, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST39VF040, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST39VF080, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0x21, id2 0x72, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 KB: skipped. Probing for ST M25P05.RES, 64 KB: skipped. Probing for ST M25P10-A, 128 KB: skipped. Probing for ST M25P10.RES, 128 KB: skipped. Probing for ST M25P20, 256 KB: skipped. Probing for ST M25P40, 512 KB: skipped. Probing for ST M25P40-old, 512 KB: skipped. Probing for ST M25P80, 1024 KB: skipped. Probing for ST M25P16, 2048 KB: skipped. Probing for ST M25P32, 4096 KB: skipped. Probing for ST M25P64, 8192 KB: skipped. Probing for ST M25P128, 16384 KB: skipped. Probing for ST M25PX32, 4096 KB: skipped. Probing for ST M25PX64, 8192 KB: skipped. Probing for ST M29F002B, 256 KB: probe_jedec_common: id1 0x5a, id2 0xd3, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 KB: probe_jedec_common: id1 0x5a, id2 0xd3, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x21, id2 0x72, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BB, 512 KB: probe_m29f400bt: id1 0x21, id2 0x2d Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0x21, id2 0x2d Probing for ST M29W010B, 128 KB: probe_jedec_common: id1 0x00, id2 0x0c, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 KB: probe_jedec_common: id1 0x21, id2 0x72, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 KB: probe_jedec_common: id1 0xea, id2 0x48, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x21, id2 0x72, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x21, id2 0x72, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0x5a, id2 0xd3, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x21, id2 0x72, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for TI TMS29F002RB, 256 KB: probe_jedec_common: id1 0x5a, id2 0xd3, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 KB: probe_jedec_common: id1 0x5a, id2 0xd3, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25Q80, 1024 KB: skipped. Probing for Winbond W25Q16, 2048 KB: skipped. Probing for Winbond W25Q32, 4096 KB: skipped. Probing for Winbond W25Q64, 8192 KB: skipped. Probing for Winbond W25x10, 128 KB: skipped. Probing for Winbond W25x20, 256 KB: skipped. Probing for Winbond W25x40, 512 KB: skipped. Probing for Winbond W25x80, 1024 KB: skipped. Probing for Winbond W25x16, 2048 KB: skipped. Probing for Winbond W25x32, 4096 KB: skipped. Probing for Winbond W25x64, 8192 KB: skipped. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W29C020(C)/W29C022, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W29C040/P, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V040(F)B, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V040(F)C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xda, id2 0x50 Found chip "Winbond W39V040(F)C" (512 KB, LPC) at physical address 0xfff80000. printlock_w39v040c: Boot block #TBL is unlocked, rest of chip #WP is unlocked. Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U/N, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W49F020, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0xda, id2 0x50 Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xda, id2 0x50 Probing for AMIC unknown AMIC SPI chip, 0 KB: skipped. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Probing for Eon unknown Eon SPI chip, 0 KB: skipped. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Probing for SST unknown SST SPI chip, 0 KB: skipped. Probing for ST unknown ST SPI chip, 0 KB: skipped. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Reading flash... done. -- MfG/Best regards, Kurt Jaeger 9 years to go ! Dr.-Ing. Nepustil & Co. GmbH fon +49 7123 93006-0 pi(a)nepustil.net Rathausstr. 3 fax +49 7123 93006-99 72658 Bempflingen mob +49 171 3101372

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[PATCH] ft2232_spi: add support for the Dangerous Prototypes Bus Blaster
by Steve Markgraf 11 Aug '11

11 Aug '11

Add support for the Dangerous Prototypes Bus Blaster (v1/v2). The new type is called "busblaster". So far only v2 has been tested, but since both v1 and v2 emulate a Amontec JTAGKEY in the default configuration, it is assumed that v1 should work fine as well. Information about the Busblaster can be found at: http://dangerousprototypes.com/docs/Bus_Blaster Signed-off-by: Steve Markgraf <steve(a)steve-m.de> --- ft2232_spi.c | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-) diff --git a/ft2232_spi.c b/ft2232_spi.c index 689f276..9d35d27 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -47,6 +47,7 @@ const struct usbdev_status devs_ft2232spi[] = { {FTDI_VID, FTDI_FT2232H_PID, OK, "FTDI", "FT2232H"}, {FTDI_VID, FTDI_FT4232H_PID, OK, "FTDI", "FT4232H"}, + {FTDI_VID, FTDI_FT2232H_PID, OK, "FTDI", "Dual RS232-HS"}, {FTDI_VID, AMONTEC_JTAGKEY_PID, OK, "Amontec", "JTAGkey"}, {FIC_VID, OPENMOKO_DBGBOARD_PID, OK, "FIC", "OpenMoko Neo1973 Debug board (V2+)"}, @@ -168,7 +169,12 @@ int ft2232_spi_init(void) ft2232_type = FTDI_FT2232H_PID; else if (!strcasecmp(arg, "4232H")) ft2232_type = FTDI_FT4232H_PID; - else if (!strcasecmp(arg, "jtagkey")) { + else if (!strcasecmp(arg, "busblaster")) { + ft2232_type = FTDI_FT2232H_PID; + ft2232_interface = INTERFACE_A; + cs_bits = 0x18; /* is a jtagkey clone in its */ + pindir = 0x1b; /* default configuration */ + } else if (!strcasecmp(arg, "jtagkey")) { ft2232_type = AMONTEC_JTAGKEY_PID; ft2232_interface = INTERFACE_A; cs_bits = 0x18; -- 1.7.4.1

2 2

[commit] r1412 - trunk
by repository service 11 Aug '11

11 Aug '11

Author: stefanct Date: Fri Aug 12 03:19:32 2011 New Revision: 1412 URL: http://flashrom.org/trac/flashrom/changeset/1412 Log: ft2232_spi: add support for the Dangerous Prototypes Bus Blaster Add support for the Dangerous Prototypes Bus Blaster (v1/v2). The new model is called "busblaster". So far only v2 has been tested, but since both v1 and v2 emulate a Amontec JTAGKEY in the default configuration, it is assumed that v1 should work fine as well. Information about the Busblaster can be found at: http://dangerousprototypes.com/docs/Bus_Blaster Signed-off-by: Steve Markgraf <steve(a)steve-m.de> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/flashrom.8 trunk/ft2232_spi.c Modified: trunk/flashrom.8 ============================================================================== --- trunk/flashrom.8 Thu Aug 11 07:47:32 2011 (r1411) +++ trunk/flashrom.8 Fri Aug 12 03:19:32 2011 (r1412) @@ -198,8 +198,8 @@ .BR "* ft2232_spi" " (for SPI flash ROMs attached to an FT2232/FT4232H family \ based USB SPI programmer), including the DLP Design DLP-USB1232H, \ FTDI FT2232H Mini-Module, FTDI FT4232H Mini-Module, openbiosprog-spi, Amontec \ -JTAGkey/JTAGkey-tiny/JTAGkey-2, Olimex ARM-USB-TINY/-H, and Olimex \ -ARM-USB-OCD/-H." +JTAGkey/JTAGkey-tiny/JTAGkey-2, Dangerous Prototypes Bus Blaster, \ +Olimex ARM-USB-TINY/-H, and Olimex ARM-USB-OCD/-H." .sp .BR "* serprog" " (for flash ROMs attached to a programmer speaking serprog), \ including AVR flasher by Urja Rannikko, AVR flasher by eightdot, \ @@ -440,8 +440,8 @@ syntax where .B model can be -.BR 2232H ", " 4232H ", " jtagkey ", " openmoko ", " arm-usb-tiny ", " \ -arm-usb-tiny-h ", " arm-usb-ocd " or " arm-usb-ocd-h +.BR 2232H ", " 4232H ", " jtagkey ", " busblaster ", " openmoko ", " \ +arm-usb-tiny ", " arm-usb-tiny-h ", " arm-usb-ocd " or " arm-usb-ocd-h and .B interface can be Modified: trunk/ft2232_spi.c ============================================================================== --- trunk/ft2232_spi.c Thu Aug 11 07:47:32 2011 (r1411) +++ trunk/ft2232_spi.c Fri Aug 12 03:19:32 2011 (r1412) @@ -173,6 +173,12 @@ ft2232_interface = INTERFACE_A; cs_bits = 0x18; pindir = 0x1b; + } else if (!strcasecmp(arg, "busblaster")) { + /* In its default configuration it is a jtagkey clone */ + ft2232_type = FTDI_FT2232H_PID; + ft2232_interface = INTERFACE_A; + cs_bits = 0x18; + pindir = 0x1b; } else if (!strcasecmp(arg, "openmoko")) { ft2232_vid = FIC_VID; ft2232_type = OPENMOKO_DBGBOARD_PID;

1 0

Problems with flashrom
by Benjamin Z. Gregorian 11 Aug '11

11 Aug '11

Hi Guys I run into trouble using flashrom. first I downloaded the ROM to flash then I downloaded flashrom and run the following command ---------- sudo flashrom ---------- Result: flashrom v0.9.1-r946 No coreboot table found. Found chipset "Intel ICH7/ICH7R", enabling flash write... OK. This chipset supports the following protocols: FWH. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. No operations were specified. --------- I assumed that flashrom can burn my BIOS (since there was no warning given) Then I tried --------- sudo flashrom -wv Desktop/Downloads/P5LD2-2002.ROM --------- Result was that two opperations are not permittet or so After studying the man page I ran the following command --------- sudo flashrom -w Desktop/Downloads/P5LD2-2002.ROM --------- and got panic!!!!!!! -------- flashrom v0.9.1-r946 No coreboot table found. Found chipset "Intel ICH7/ICH7R", enabling flash write... OK. This chipset supports the following protocols: FWH. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... Erasing flash chip... ERASE FAILED at 0x000002c8! Expected=0xff, Read=0x4c, failed byte count from 0x00000000-0x00000fff: 0xd12 ERASE FAILED! ERASE FAILED at 0x000002c8! Expected=0xff, Read=0x4c, failed byte count from 0x00000000-0x0000ffff: 0xfc2b ERASE FAILED! FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! ----------------------------------- PLEASE ADVICE what to do next. LOOKING EAGERLY FORWARD to YOUR REPLY Regards Benjamin -- Neu: GMX De-Mail - Einfach wie E-Mail, sicher wie ein Brief! Jetzt De-Mail-Adresse reservieren: http://portal.gmx.net/de/go/demail

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Re: [flashrom] flashrom -V
by Melchior FRANZ 11 Aug '11

11 Aug '11

* Daniel Housar -- Wednesday 10 August 2011: > MainBoard: MSI K9N Neo V2 (K9N Neo-F V2) > flashrom v0.9.4-r1395 I have the same board, and I flashed it successfully with v0.9.3-r1370 about a month ago (-> BIOS v2.9). After booting it first seemed to have gone wrong: early in the boot phase the BIOS rebooted, and I was in an endless loop. I couldn't go into the setup, and I couldn't even read the error message. So I recorded a film with my mobile's cam, and wanted to watch it in slow motion to decipher the message. But in the meantime the BIOS had stopped rebooting and showed a prompt. Unfortunately I didn't note down the text, but after confirming everything went fine. I guess I should have: - reset my BIOS to factory default/"optimal" settings before flashing (Maybe some of the custom settings didn't work well with the new BIOS? Though one would assume that they get reset anyway.) - gone into single-user mode for flashing, with as few apps running as possible (some of them froze, and KDE decided to forget some of my settings) But again, apart from this little adventure everything worked fine. m.

1 0

[commit] r1411 - trunk
by repository service 11 Aug '11

11 Aug '11

Author: stefanct Date: Thu Aug 11 07:47:32 2011 New Revision: 1411 URL: http://flashrom.org/trac/flashrom/changeset/1411 Log: Add board enable for ASUS P5GD2 Premium This is based on Joshua's patch, but with a DMI pattern, contrary to http://www.flashrom.org/pipermail/flashrom/2010-September/004745.html Rationale: although it looks like all P5GD2/C* might use the same board enable (intel_ich_gpio21_raise), we need to add the variants individually as long as we don't have enough reports to make a better guess. This also guarantees correct output of flashrom -L and -z and on activation of the board enable - not like this: http://www.flashrom.org/pipermail/flashrom/attachments/20100930/2286e5d1/at… Success report: http://www.flashrom.org/pipermail/flashrom/2010-August/004555.html Also, fix last commit by adding a missing comma. Tested-by: Roberto Malinverni Signed-off-by: Joshua Roys <roysjosh(a)gmail.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Thu Aug 11 06:21:34 2011 (r1410) +++ trunk/board_enable.c Thu Aug 11 07:47:32 2011 (r1411) @@ -1494,6 +1494,7 @@ * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R * - ASUS P4P800-VM: Intel socket478 + 865PE + ICH5R * - ASUS P5GD1 Pro: Intel LGA 775 + 915P + ICH6R + * - ASUS P5GD2 Premium: Intel LGA775 + 915G + ICH6R * - ASUS P5GDC Deluxe: Intel socket775 + 915P + ICH6R * - ASUS P5PE-VM: Intel LGA775 + 865G + ICH5 * - Samsung Polaris 32: socket478 + 865P + ICH5 @@ -2022,8 +2023,9 @@ {0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x5513, 0x1043, 0x8087, NULL, NULL, NULL, P3, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", P3, "ASUS", "P5A", 0, OK, board_asus_p5a}, {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, P3, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, "^P5GD2-Premium$", NULL, NULL, P3, "ASUS", "P5GD2 Premium", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, P3, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise}, - {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, NT, intel_ich_gpio16_raise}, + {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8, 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, NT, intel_ich_gpio16_raise}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, P3, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, P3, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise}, {0x10b7, 0x9055, 0x1028, 0x0082, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Dell", "OptiPlex GX1", 0, OK, intel_piix4_gpo30_lower}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Thu Aug 11 06:21:34 2011 (r1410) +++ trunk/print.c Thu Aug 11 07:47:32 2011 (r1411) @@ -479,6 +479,7 @@ B("ASUS", "P5B-Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=bswT66IBSb2rEWNa", NULL), B("ASUS", "P5BV-M", 0, "ftp://ftp.asus.com.tw/pub/ASUS/mb/socket775/P5B-VM/", "Reported by Bernhard M. Wiedemann <bernhard(a)uml12d.zq1.de> to flashrom(a)coreboot.org, no public archive. Missing board enable and/or SST49LF008A unlocking. May work now."), B("ASUS", "P5GC-MX/1333", 1, "http://www.asus.com/product.aspx?P_ID=PYvbfOokwxUzJky3", NULL), + B("ASUS", "P5GD2 Premium", 1, "http://www.asus.it/product.aspx?P_ID=lRKaz1Rb6Xb0OFM7", NULL), B("ASUS", "P5GDC Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=AbeoopyNpI2TZixg", NULL), B("ASUS", "P5KC", 1, "http://www.asus.com/product.aspx?P_ID=fFZ8oUIGmLpwNMjj", NULL), B("ASUS", "P5L-MX", 1, "http://www.asus.com/product.aspx?P_ID=X70d3NCzH2DE9vWH", NULL),

1 0

[commit] r1410 - trunk
by repository service 11 Aug '11

11 Aug '11

Author: stefanct Date: Thu Aug 11 06:21:34 2011 New Revision: 1410 URL: http://flashrom.org/trac/flashrom/changeset/1410 Log: Add (untested) board enable for Asus P5LD2 There are numerous other variants of the P5LD2 which vary wildly not only in PCB layout but also in northbridges used, number of PCI, PCI-E and DIMM slots etc. This one is for the plain P5LD2 without any suffixes. This patch is essentially a rebased version of Joshua's patch, which was never tested (user did not reply). I have added additional PCI IDs and the DMI pattern and also changed the status to NT. An entry in the print.c table was also added. http://www.flashrom.org/pipermail/flashrom/2010-October/005080.html Signed-off-by: Joshua Roys <roysjosh(a)gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Tue Aug 9 03:49:34 2011 (r1409) +++ trunk/board_enable.c Thu Aug 11 06:21:34 2011 (r1410) @@ -1461,6 +1461,7 @@ * Suited for: * - abit IP35: Intel P35 + ICH9R * - abit IP35 Pro: Intel P35 + ICH9R + * - ASUS P5LD2 */ static int intel_ich_gpio16_raise(void) { @@ -2022,6 +2023,7 @@ {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", P3, "ASUS", "P5A", 0, OK, board_asus_p5a}, {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, P3, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise}, {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, P3, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise}, + {0x8086, 0x27da, 0x1043, 0x8179, 0x8086, 0x27b8 0x1043, 0x8179, "^P5LD2$", NULL, NULL, P3, "ASUS", "P5LD2", 0, NT, intel_ich_gpio16_raise}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, P3, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, P3, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise}, {0x10b7, 0x9055, 0x1028, 0x0082, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Dell", "OptiPlex GX1", 0, OK, intel_piix4_gpo30_lower}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Tue Aug 9 03:49:34 2011 (r1409) +++ trunk/print.c Thu Aug 11 06:21:34 2011 (r1410) @@ -482,6 +482,7 @@ B("ASUS", "P5GDC Deluxe", 1, "http://www.asus.com/product.aspx?P_ID=AbeoopyNpI2TZixg", NULL), B("ASUS", "P5KC", 1, "http://www.asus.com/product.aspx?P_ID=fFZ8oUIGmLpwNMjj", NULL), B("ASUS", "P5L-MX", 1, "http://www.asus.com/product.aspx?P_ID=X70d3NCzH2DE9vWH", NULL), + B("ASUS", "P5LD2", 0, NULL, "Untested board enable."), B("ASUS", "P5GD1 Pro", 1, "http://www.asus.com/product.aspx?P_ID=50M49xQh71EZOeM1", NULL), B("ASUS", "P5N-E SLI", 0, "http://www.asus.com/product.aspx?P_ID=KyHOsOKWujC2QguJ", "Needs a board enable (http://patchwork.coreboot.org/patch/3298/)."), B("ASUS", "P5N32-E SLI", 1, "http://www.asus.com/product.aspx?P_ID=vBZLIBtPzYB2bLcb", NULL),

1 0

[PATCH] add support for AT49F040
by David Borg 11 Aug '11

11 Aug '11

Hi, I was adding support for the AT49F040 parallel flash chip, but have some questions. This chip has a boot block which once locked cannot be erased / rewritten. Should I add erase functions for both cases? Currently the erase function handles unlocked chips only. In addition, the datasheet specifies no command timings, is the timing something I can infer from the read / program cycle characteristics tables? Regards, David Signed-off-by: David Borg <borg.db(a)gmail.com> datasheet: http://pdf1.alldatasheet.com/datasheet-pdf/view/56184/ATMEL/AT49F040.html Index: flashchips.c =================================================================== --- flashchips.c (revision 1145) +++ flashchips.c (working copy) @@ -1985,6 +1985,29 @@ }, { + .vendor = "Atmel", + .name = "AT49F040", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = ATMEL_ID, + .model_id = AT_49F040, + .total_size = 512, + .page_size = 512, + .feature_bits = FEATURE_EITHER_RESET | FEATURE_ADDR_FULL, + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ + .block_erasers = + { + { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + } + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { .vendor = "EMST", .name = "F49B002UA", .bustype = CHIP_BUSTYPE_PARALLEL, Index: flashchips.h =================================================================== --- flashchips.h (revision 1145) +++ flashchips.h (working copy) @@ -174,6 +174,7 @@ #define AT_49F020 0x0B #define AT_49F002N 0x07 /* for AT49F002(N) */ #define AT_49F002NT 0x08 /* for AT49F002(N)T */ +#define AT_49F040 0x13 #define CATALYST_ID 0x31 /* Catalyst */

3 2

flashrom -V
by Daniel Housar 10 Aug '11

10 Aug '11

MainBoard: MSI K9N Neo V2 (K9N Neo-F V2) NVIDIA nForce 520 (MCP65), socket AM2 (AMD Athlon64/X2) flashrom v0.9.4-r1395 on Linux 3.0.0+ (x86_64), built with libpci 3.1.7, GCC 4.6.1, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 655M loops per second, 10 myus = 10 us, 100 myus = 99 us, 1000 myus = 990 us, 10000 myus = 10339 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "MSI" DMI string system-product-name: "MS-7369" DMI string system-version: "1.0" DMI string baseboard-manufacturer: "MSI" DMI string baseboard-product-name: "MS-7369" DMI string baseboard-version: "1.0" DMI string chassis-type: "Desktop" Found chipset "NVIDIA MCP65" with PCI ID 10de:0441. This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Flash bus type is SPI SPI on this chipset is WIP. Please report any success or failure by mailing us the verbose output to flashrom(a)flashrom.org, thanks! Found SMBus device 10de:0446 at 00:01:1 MCP SPI BAR is at 0xfec80000 Mapping NVIDIA MCP6x SPI at 0xfec80000, unaligned size 0x544. SPI control is 0x0002, req=0, gnt=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Chip status register is 00 Chip status register: Status Register Write Disable (SRWD) is not set Chip status register: Bit 6 is not set Chip status register: Bit 5 / Block Protect 3 (BP3) is not set Chip status register: Bit 4 / Block Protect 2 (BP2) is not set Chip status register: Bit 3 / Block Protect 1 (BP1) is not set Chip status register: Bit 2 / Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found Macronix flash chip "MX25L8005" (1024 kB, SPI) at physical address 0xfff00000. Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF010.REMS, 128 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25VF040.REMS, 512 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST SST25LF040A.RES, 512 kB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xc2, id2 0x13 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P05.RES, 64 kB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P10.RES, 128 kB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2014 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xc2, id2 0x13 No operations were specified.

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Re: [flashrom] [PATCH 2/4] add ICH/PCH flash descriptor decoding via FDOC/FDOD
by Carl-Daniel Hailfinger 09 Aug '11

09 Aug '11

Am 21.07.2011 01:24 schrieb Stefan Tauner: > based on the work of Matthias 'mazzoo' Wenzel this patch adds pretty > printing of those ICH/PCH flash descriptors that are cached/mapped > by the chipset (and which are therefore reachable via FDOC/FDOD > registers). > > this includes the following: > - content descriptor: > describes the image and some generic properties (number of regions, > offset of regions, offset of which regions, or something else? How does this relate to region descriptor(s)? > PCH/ICH and MCH/PROC strap offsets and lengths) > - component descriptor: > identify the different SPI Flash Components and their capabilities. > components==chips? If yes, please say so in the changelog (and maybe code comments). > - region descriptor > similarly to a partition table this describes the different regions > One common descriptor for all regions or one descriptor per region? > - master descriptor > defines access rights of the individual regions > > this is only a part of the data included in the descriptor. other > information can be retreived retrieved > from a complete binary dump of the descriptor image only. > What's a descriptor image? > this patch also adds macros and pretty printing for "Vendor Specific > Component Capabilities" registers: > there are two of them: lower and upper. they describe the properties > of the address space divided by FPBA We really need some place (maybe as comment in ich_decriptor.h?) where all Intel acronyms are expanded and explained. > (which allows to use multiple > flash chips or partitions with different properties). the properties > of flash chips supported by the ME are stored in the same format in > a descriptor table. "a descriptor table" implies there is more than one. Which one is it? > a later patch will uses them outside of ichspi.c > which is also the reason why the prettyprinting function and the > register bit macros are not defined in ichspi.c but ich_descriptors.h. > > TODO: > - file naming and partitioning was not discussed. we may want a ichspi.h. > and/or rename ichspi.c to ich_spi.c or similar... > I'd say naming of the files is the least of our worries. We'll reorganize all flashrom code in a directory structure anyway, and that's when we can rename files if needed. > - straps of ich8 (only) Why not ICH7 (no descriptors?) or ICH9 and later (no datasheets?) > could be printed at runtime via FDOC/FDOD. > worth it? no, imo. Agreed. > but reading out the descriptor region manually and > parsing it with the following patch may be useful? > following patch == 3/4? Once we support true partial reads with the help of layout files, this should be possible. > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Please note that I didn't check the code for correctness against the datasheets nor did I check the code flow. The comments below are what I noticed from reading the patch alone. The message levels of most messages really need to be discussed... a flood of msg_dbg is not necessarily a good idea, downgrading a lot of them to dbg2 may improve said flood. That said, msg_[cpg]dbg2 is now in the tree, so the dbg1 hack can go away. Looking again at your messagelevels, maybe dbg1->dbg2 and dbg2->spew would be in order. All ich specific structs should have an ich_ prefix in the struct name to avoid polluting the global namespace. > --- > Makefile | 3 +- > ich_descriptors.c | 247 +++++++++++++++++++++++++++++++++++++++++++++++++ > ich_descriptors.h | 264 +++++++++++++++++++++++++++++++++++++++++++++++++++++ > ichspi.c | 39 ++++++-- > 4 files changed, 544 insertions(+), 9 deletions(-) > create mode 100644 ich_descriptors.c > create mode 100644 ich_descriptors.h > > diff --git a/Makefile b/Makefile > index a35df06..7f73452 100644 > --- a/Makefile > +++ b/Makefile > @@ -308,7 +308,8 @@ ifeq ($(CONFIG_INTERNAL), yes) > FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1' > PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o > ifeq ($(ARCH),"x86") > -PROGRAMMER_OBJS += it87spi.o it85spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o > +PROGRAMMER_OBJS += it87spi.o it85spi.o sb600spi.o wbsio_spi.o mcp6x_spi.o > +PROGRAMMER_OBJS += ichspi.o ich_descriptors.o > else > endif > NEED_PCI := yes > diff --git a/ich_descriptors.c b/ich_descriptors.c > new file mode 100644 > index 0000000..cf77601 > --- /dev/null > +++ b/ich_descriptors.c > @@ -0,0 +1,247 @@ > +/* > + * This file is part of the flashrom project. > + * > + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> > + * Copyright (c) 2011 Stefan Tauner > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + */ > + > +#if defined(__i386__) || defined(__x86_64__) > + > +#include "ich_descriptors.h" > +#include "flash.h" /* for msg_* */ > + > +#define getFCBA(cont) (((cont)->FLMAP0 << 4) & 0x00000ff0) > +#define getFRBA(cont) (((cont)->FLMAP0 >> 12) & 0x00000ff0) > +#define getFMBA(cont) (((cont)->FLMAP1 << 4) & 0x00000ff0) > +#define getFISBA(cont) (((cont)->FLMAP1 >> 12) & 0x00000ff0) > +#define getFMSBA(cont) (((cont)->FLMAP2 << 4) & 0x00000ff0) > + > +void prettyprint_ich_descriptors(enum chipset cs, const struct flash_descriptors *desc) > (enum ich_chipset cs, const struct ich_flash_descriptors *desc) > +{ > Please try to handle cs at least somewhat. Check if it has the expected value, and skip descriptor decoding (with a dbg/dbg2 message telling the user about it) if the result would be wrong (i.e. for the wrong ICH family). > + prettyprint_ich_descriptor_content(&desc->content); > + prettyprint_ich_descriptor_component(desc); > + prettyprint_ich_descriptor_region(&desc->region); > + prettyprint_ich_descriptor_master(&desc->master); > +} > + > +void prettyprint_ich_descriptor_content(const struct flash_content *cont) > ich_flash_content Does this work on all chipsets? > +{ > + msg_pdbg1("=== Content Section ===\n"); > + msg_pdbg1("FLVALSIG 0x%08x\n", cont->FLVALSIG); > + msg_pdbg1("FLMAP0 0x%08x\n", cont->FLMAP0); > + msg_pdbg1("FLMAP1 0x%08x\n", cont->FLMAP1); > + msg_pdbg1("FLMAP2 0x%08x\n", cont->FLMAP2); > + msg_pdbg1("\n"); > dbg1->dbg, or maybe ->dbg2 to reduce output. The message level discussion should not hold back this patch. > + > + msg_pdbg2("--- Details ---\n"); > + msg_pdbg2("NR (Number of Regions): %5d\n", > + cont->NR + 1); > + msg_pdbg2("FRBA (Flash Region Base Address): 0x%03x\n", > + getFRBA(cont)); > + msg_pdbg2("NC (Number of Components): %5d\n", > + cont->NC + 1); > + msg_pdbg2("FCBA (Flash Component Base Address): 0x%03x\n", > + getFCBA(cont)); > + msg_pdbg2("ISL (ICH/PCH Strap Length): %5d\n", > + cont->ISL); > + msg_pdbg2("FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x%03x\n", > + getFISBA(cont)); > + msg_pdbg2("NM (Number of Masters): %5d\n", > + cont->NM + 1); > + msg_pdbg2("FMBA (Flash Master Base Address): 0x%03x\n", > + getFMBA(cont)); > + msg_pdbg2("MSL/PSL (MCH/PROC Strap Length): %5d\n", > + cont->MSL); > + msg_pdbg2("FMSBA (Flash MCH/PROC Strap Base Address): 0x%03x\n", > + getFMSBA(cont)); > + msg_pdbg2("\n"); > +} > + > +void prettyprint_ich_descriptor_component(const struct flash_descriptors *desc) > ich_flash_descriptors Which chipset is handled by this function? > +{ > + const char * const str_freq[8] = { > static? Or is that useless here? > + "20 MHz", /* 000 */ > + "33 MHz", /* 001 */ > + "reserved", /* 010 */ > + "reserved", /* 011 */ > + "50 MHz", /* 100 */ > Mh. Is 50 MHz available on all descriptor capable chipsets? > + "reserved", /* 101 */ > + "reserved", /* 110 */ > + "reserved" /* 111 */ > + }; > + const char * const str_mem[8] = { > static? > + "512 kB", /* 000 */ > + " 1 MB", /* 001 */ > + " 2 MB", /* 010 */ > + " 4 MB", /* 011 */ > + " 8 MB", /* 100 */ > + " 16 MB", /* 101 */ > + "reserved", /* 110 */ > + "reserved", /* 111 */ > + }; > + > + msg_pdbg1("=== Component Section ===\n"); > + msg_pdbg1("FLCOMP 0x%08x\n", desc->component.FLCOMP); > + msg_pdbg1("FLILL 0x%08x\n", desc->component.FLILL ); > + msg_pdbg1("\n"); > + > + msg_pdbg2("--- Details ---\n"); > + msg_pdbg2("Component 1 density: %s\n", > + str_mem[desc->component.comp1_density]); > + if (desc->content.NC) > + msg_pdbg2("Component 2 density: %s\n", > + str_mem[desc->component.comp2_density]); > + else > + msg_pdbg2("Component 2 is not used.\n"); > + msg_pdbg2("Read Clock Frequency: %s\n", > + str_freq[desc->component.freq_read]); > + msg_pdbg2("Read ID and Status Clock Freq.: %s\n", > + str_freq[desc->component.freq_read_id]); > + msg_pdbg2("Write and Erase Clock Freq.: %s\n", > + str_freq[desc->component.freq_write]); > + msg_pdbg2("Fast Read is %ssupported.\n", > + desc->component.fastread ? "" : "not "); > + if (desc->component.fastread) > + msg_pdbg2("Fast Read Clock Frequency: %s\n", > + str_freq[desc->component.freq_fastread]); > + if (desc->component.FLILL == 0) > + msg_pdbg2("No forbidden opcodes.\n"); > + else { > + msg_pdbg2("Invalid instruction 0: 0x%02x\n", > + desc->component.invalid_instr0); > + msg_pdbg2("Invalid instruction 1: 0x%02x\n", > + desc->component.invalid_instr1); > + msg_pdbg2("Invalid instruction 2: 0x%02x\n", > + desc->component.invalid_instr2); > + msg_pdbg2("Invalid instruction 3: 0x%02x\n", > + desc->component.invalid_instr3); > + } > + msg_pdbg2("\n"); > +} > + > +static void pprint_freg(const struct flash_region *reg, uint32_t i) > ich_flash_region Which chipset? Or is the code generic? > +{ > + const char *const region_names[5] = { > + "Descr.", "BIOS", "ME", "GbE", "Platf." > + }; > + uint32_t base = ICH_FREG_BASE(reg->FLREGs[i]); > + uint32_t limit = ICH_FREG_LIMIT(reg->FLREGs[i]); > + msg_pdbg2("Region %d (%-6s) ", i, region_names[i]); > + if (base > limit) > + msg_pdbg2("is unused.\n"); > + else > + msg_pdbg2("0x%08x - 0x%08x\n", base, limit | 0x0fff); > +} > + > +void prettyprint_ich_descriptor_region(const struct flash_region *reg) > ich_flash_region Chipset specific or generic? > +{ > + uint8_t i; > + msg_pdbg1("=== Region Section ===\n"); > + for (i = 0; i < 5; i++) > + msg_pdbg1("FLREG%d 0x%08x\n", i, reg->FLREGs[i]); > + msg_pdbg1("\n"); > + > + msg_pdbg2("--- Details ---\n"); > + for (i = 0; i < 5; i++) > + pprint_freg(reg, i); > + msg_pdbg2("\n"); > +} > + > +void prettyprint_ich_descriptor_master(const struct flash_master *mstr) > ich_flash_master > +{ > + msg_pdbg1("=== Master Section ===\n"); > + msg_pdbg1("FLMSTR1 0x%08x\n", mstr->FLMSTR1); > + msg_pdbg1("FLMSTR2 0x%08x\n", mstr->FLMSTR2); > + msg_pdbg1("FLMSTR3 0x%08x\n", mstr->FLMSTR3); > + msg_pdbg1("\n"); > + > + msg_pdbg2("--- Details ---\n"); > + msg_pdbg2(" Descr. BIOS ME GbE Platf.\n"); > + msg_pdbg2("BIOS %c%c %c%c %c%c %c%c %c%c\n", > + (mstr->BIOS_descr_r) ?'r':' ', (mstr->BIOS_descr_w) ?'w':' ', > + (mstr->BIOS_BIOS_r) ?'r':' ', (mstr->BIOS_BIOS_w) ?'w':' ', > + (mstr->BIOS_ME_r) ?'r':' ', (mstr->BIOS_ME_w) ?'w':' ', > + (mstr->BIOS_GbE_r) ?'r':' ', (mstr->BIOS_GbE_w) ?'w':' ', > + (mstr->BIOS_plat_r) ?'r':' ', (mstr->BIOS_plat_w) ?'w':' '); > + msg_pdbg2("ME %c%c %c%c %c%c %c%c %c%c\n", > + (mstr->ME_descr_r) ?'r':' ', (mstr->ME_descr_w) ?'w':' ', > + (mstr->ME_BIOS_r) ?'r':' ', (mstr->ME_BIOS_w) ?'w':' ', > + (mstr->ME_ME_r) ?'r':' ', (mstr->ME_ME_w) ?'w':' ', > + (mstr->ME_GbE_r) ?'r':' ', (mstr->ME_GbE_w) ?'w':' ', > + (mstr->ME_plat_r) ?'r':' ', (mstr->ME_plat_w) ?'w':' '); > + msg_pdbg2("GbE %c%c %c%c %c%c %c%c %c%c\n", > + (mstr->GbE_descr_r) ?'r':' ', (mstr->GbE_descr_w) ?'w':' ', > + (mstr->GbE_BIOS_r) ?'r':' ', (mstr->GbE_BIOS_w) ?'w':' ', > + (mstr->GbE_ME_r) ?'r':' ', (mstr->GbE_ME_w) ?'w':' ', > + (mstr->GbE_GbE_r) ?'r':' ', (mstr->GbE_GbE_w) ?'w':' ', > + (mstr->GbE_plat_r) ?'r':' ', (mstr->GbE_plat_w) ?'w':' '); > + msg_pdbg2("\n"); > +} > + > +void prettyprint_ich9_reg_vscc(uint32_t reg_val) > +{ > + pprint_reg_hex(VSCC, BES, reg_val, ", "); > + pprint_reg(VSCC, WG, reg_val, ", "); > + pprint_reg(VSCC, WSR, reg_val, ", "); > + pprint_reg(VSCC, WEWS, reg_val, ", "); > + pprint_reg_hex(VSCC, EO, reg_val, ", "); > + pprint_reg(VSCC, VCL, reg_val, "\n"); > +} > + > +static uint32_t read_descriptor_reg(uint8_t section, uint16_t offset, void *spibar) > +{ > + uint32_t control = 0; > + control |= (section << FDOC_FDSS_OFF) & FDOC_FDSS; > + control |= (offset << FDOC_FDSI_OFF) & FDOC_FDSI; > + *(volatile uint32_t *) (spibar + ICH9_REG_FDOC) = control; > volatile is absolutely no-go outside hwaccess.c. Use mmio_write[bwl] or the littleendian variant of mmio_write[bwl] instead. > + return *(volatile uint32_t *)(spibar + ICH9_REG_FDOD); > Same here. Use mmio_read[bwl] instead. > +} > + > +void read_ich_descriptors_via_fdo(void *spibar, struct flash_descriptors *desc) > +{ > + msg_pdbg1("Reading flash descriptors " > + "mapped by the chipset via FDOC/FDOD..."); > + /* content section */ > + desc->content.FLVALSIG = read_descriptor_reg(0, 0, spibar); > + desc->content.FLMAP0 = read_descriptor_reg(0, 1, spibar); > + desc->content.FLMAP1 = read_descriptor_reg(0, 2, spibar); > + desc->content.FLMAP2 = read_descriptor_reg(0, 3, spibar); > + > + /* component section */ > + desc->component.FLCOMP = read_descriptor_reg(1, 0, spibar); > + desc->component.FLILL = read_descriptor_reg(1, 1, spibar); > + desc->component.FLPB = read_descriptor_reg(1, 2, spibar); > + > + /* region section */ > + desc->region.FLREGs[0] = read_descriptor_reg(2, 0, spibar); > + desc->region.FLREGs[1] = read_descriptor_reg(2, 1, spibar); > + desc->region.FLREGs[2] = read_descriptor_reg(2, 2, spibar); > + desc->region.FLREGs[3] = read_descriptor_reg(2, 3, spibar); > + desc->region.FLREGs[4] = read_descriptor_reg(2, 4, spibar); > + > + /* master section */ > + desc->master.FLMSTR1 = read_descriptor_reg(3, 0, spibar); > + desc->master.FLMSTR2 = read_descriptor_reg(3, 1, spibar); > + desc->master.FLMSTR3 = read_descriptor_reg(3, 2, spibar); > + > + /* Accessing the strap section via FDOC/D is only possible on ICH8 and > + * reading the upper map is impossible on all chipsets, so don't bother. > + */ > + > + msg_pdbg1(" done\n"); > This seems to be a true flood of output. dbg2 for all callees maybe? > +} > +#endif // defined(__i386__) || defined(__x86_64__) > diff --git a/ich_descriptors.h b/ich_descriptors.h > new file mode 100644 > index 0000000..f248394 > --- /dev/null > +++ b/ich_descriptors.h > @@ -0,0 +1,264 @@ > +/* > + * This file is part of the flashrom project. > + * > + * Copyright (c) 2010 Matthias Wenzel <bios at mazzoo dot de> > + * Copyright (c) 2011 Stefan Tauner > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + */ > + > +#if defined(__i386__) || defined(__x86_64__) > +#ifndef __ICH_DESCRIPTORS_H__ > +#define __ICH_DESCRIPTORS_H__ 1 > + > +#include <stdint.h> > + > +/* most of the following should probably be in a new file named ichspi.h */ > +#define msg_pdbg1 msg_pdbg > +#define msg_pdbg2 msg_pspew > + > +#define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */ > + /* 0-1: reserved */ > +#define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */ > +#define FDOC_FDSI (0x3f << FDOC_FDSI_OFF) > +#define FDOC_FDSS_OFF 12 /* 12-14: Flash Descriptor Section Select */ > +#define FDOC_FDSS (0x3 << FDOC_FDSS_OFF) > + /* 15-31: reserved */ > + > +#define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */ > + > +/* Field locations and semantics for LVSCC, UVSCC and related words in the flash > + * descriptor are equal therefore they all share the same macros below. */ > +#define VSCC_BES_OFF 0 /* 0-1: Block/Sector Erase Size */ > +#define VSCC_BES (0x3 << VSCC_BES_OFF) > +#define VSCC_WG_OFF 2 /* 2: Write Granularity */ > +#define VSCC_WG (0x1 << VSCC_WG_OFF) > Whitespace damage or is this caused by the leading + in the patch? > +#define VSCC_WSR_OFF 3 /* 3: Write Status Required */ > +#define VSCC_WSR (0x1 << VSCC_WSR_OFF) > +#define VSCC_WEWS_OFF 4 /* 4: Write Enable on Write Status */ > +#define VSCC_WEWS (0x1 << VSCC_WEWS_OFF) > + /* 5-7: reserved */ > +#define VSCC_EO_OFF 8 /* 8-15: Erase Opcode */ > +#define VSCC_EO (0xff << VSCC_EO_OFF) > + /* 16-22: reserved */ > Whitespace damage? > +#define VSCC_VCL_OFF 23 /* 23: Vendor Component Lock */ > +#define VSCC_VCL (0x1 << VSCC_VCL_OFF) > + /* 24-31: reserved */ > + > +#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) > +#define pprint_reg_hex(reg, bit, val, sep) msg_pdbg("%s=0x%x" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) > Please add () around val at the right hand side. > +void prettyprint_ich9_reg_vscc(uint32_t reg_val); > + > +#define ICH_FREG_BASE(flreg) ((flreg << 12) & 0x01fff000) > +#define ICH_FREG_LIMIT(flreg) ((flreg >> 4) & 0x01fff000) > Please add () around flreg at the right hand side. > + > +/* Used to select the right descriptor printing function. > + * Currently only ICH8 and Ibex Peak are supported. > + */ > +enum chipset { > ich_chipset > + CHIPSET_UNKNOWN, > CHIPSET_ICH_UNKNOWN We may need a CHIPSET_UNKNOWN elsewhere... > + CHIPSET_ICH7 = 7, > + CHIPSET_ICH8, > + CHIPSET_ICH9, > + CHIPSET_ICH10, > + CHIPSET_5_SERIES_IBEX_PEAK, > + CHIPSET_6_SERIES_COUGAR_POINT, > + CHIPSET_7_SERIES_PANTHER_POINT > +}; > + > All structs below probably need __attribute__((packed)). > +struct flash_content { > ich_flash_content > + uint32_t FLVALSIG; /* 0x00 */ > + union { /* 0x04 */ > + uint32_t FLMAP0; > + struct { > + uint32_t FCBA :8; > + uint32_t NC :2; > + uint32_t :6; > + uint32_t FRBA :8; > + uint32_t NR :3; > + uint32_t :5; > + }; > + }; > + union { /* 0x08 */ > + uint32_t FLMAP1; > + struct { > + uint32_t FMBA :8; > + uint32_t NM :3; > + uint32_t :5; > + uint32_t FISBA :8; > + uint32_t ISL :8; > + }; > + }; > + union { /* 0x0c */ > + uint32_t FLMAP2; > + struct { > + uint32_t FMSBA :8; > + uint32_t MSL :8; > + uint32_t :16; > + }; > + }; > +}; > + > +struct flash_component { > ich_flash_component > + union { /* 0x00 */ > + uint32_t FLCOMP; > + struct { > + uint32_t comp1_density :3; > + uint32_t comp2_density :3; > + uint32_t :11; > + uint32_t freq_read :3; > + uint32_t fastread :1; > + uint32_t freq_fastread :3; > + uint32_t freq_write :3; > + uint32_t freq_read_id :3; > + uint32_t :2; > + }; > + }; > + union { /* 0x04 */ > + uint32_t FLILL; > + struct { > + uint32_t invalid_instr0; > Really uint32_t? If FLILL is 32 bits, but all invalid_instr are 32 bits as well, the union members have inconsistent sizes. uint8_t invalid_instr0 maybe? > + uint32_t invalid_instr1; > + uint32_t invalid_instr2; > + uint32_t invalid_instr3; > Dito for the other invalid_instr above. > + }; > + }; > + union { /* 0x08 */ > + uint32_t FLPB; > + struct { > + uint32_t FPBA :13; > + uint32_t :19; > + }; > + }; > All code accessing FLPB/FPBA was broken due to the wrong FLILL union size, so if it worked anyway, you have another bug hidden somewhere. > +}; > + > +struct flash_region { > ich_flash_region > + union { > + uint32_t FLREGs[5]; > + struct { > + /* FLREG0 Flash Descriptor */ > + struct { > + uint32_t reg0_base :13; > Are uint32_t bitfields allowed? I thought bitfields were either signed int or unsigned int, but never uint32_t. > + uint32_t :3; > Are anonymous bitfields allowed? > + uint32_t reg0_limit :13; > + uint32_t :3; > + }; > + /* FLREG1 BIOS */ > + struct { > + uint32_t reg1_base :13; > + uint32_t :3; > + uint32_t reg1_limit :13; > + uint32_t :3; > + }; > + /* FLREG2 ME */ > + struct { > + uint32_t reg2_base :13; > + uint32_t :3; > + uint32_t reg2_limit :13; > + uint32_t :3; > + }; > + /* FLREG3 GbE */ > + struct { > + uint32_t reg3_base :13; > + uint32_t :3; > + uint32_t reg3_limit :13; > + uint32_t :3; > + }; > + /* FLREG4 Platform */ > + struct { > + uint32_t reg4_base :13; > + uint32_t :3; > + uint32_t reg4_limit :13; > + uint32_t :3; > + }; > + }; > + }; > +}; > + > +struct flash_master { > ich_flash_master > + union { > + uint32_t FLMSTR1; > + struct { > + uint32_t BIOS_req_ID :16; > + uint32_t BIOS_descr_r :1; > + uint32_t BIOS_BIOS_r :1; > + uint32_t BIOS_ME_r :1; > + uint32_t BIOS_GbE_r :1; > + uint32_t BIOS_plat_r :1; > + uint32_t :3; > + uint32_t BIOS_descr_w :1; > + uint32_t BIOS_BIOS_w :1; > + uint32_t BIOS_ME_w :1; > + uint32_t BIOS_GbE_w :1; > + uint32_t BIOS_plat_w :1; > + uint32_t :3; > + }; > + }; > + union { > + uint32_t FLMSTR2; > + struct { > + uint32_t ME_req_ID :16; > + uint32_t ME_descr_r :1; > + uint32_t ME_BIOS_r :1; > + uint32_t ME_ME_r :1; > + uint32_t ME_GbE_r :1; > + uint32_t ME_plat_r :1; > + uint32_t :3; > + uint32_t ME_descr_w :1; > + uint32_t ME_BIOS_w :1; > + uint32_t ME_ME_w :1; > + uint32_t ME_GbE_w :1; > + uint32_t ME_plat_w :1; > + uint32_t :3; > + }; > + }; > + union { > + uint32_t FLMSTR3; > + struct { > + uint32_t GbE_req_ID :16; > + uint32_t GbE_descr_r :1; > + uint32_t GbE_BIOS_r :1; > + uint32_t GbE_ME_r :1; > + uint32_t GbE_GbE_r :1; > + uint32_t GbE_plat_r :1; > + uint32_t :3; > + uint32_t GbE_descr_w :1; > + uint32_t GbE_BIOS_w :1; > + uint32_t GbE_ME_w :1; > + uint32_t GbE_GbE_w :1; > + uint32_t GbE_plat_w :1; > + uint32_t :3; > + }; > + }; > +}; > + > +struct flash_descriptors { > ich_flash_descriptors > + struct flash_content content; > ich_flash_content > + struct flash_component component; > ich_flash_component > + struct flash_region region; > ich_flash_region > + struct flash_master master; > ich_flash_master > +}; > + > +void prettyprint_ich_descriptors(enum chipset, const struct flash_descriptors *desc); > Missing parameter name for first parameter, and of course ich_chipset ... ich_flash_descriptors. > + > +void prettyprint_ich_descriptor_content(const struct flash_content *content); > +void prettyprint_ich_descriptor_component(const struct flash_descriptors *desc); > +void prettyprint_ich_descriptor_region(const struct flash_region *region); > +void prettyprint_ich_descriptor_master(const struct flash_master *master); > ich_ for all struct names (not for the variable names) > + > +void read_ich_descriptors_via_fdo(void *spibar, struct flash_descriptors *desc); > ich_flash_descriptors > + > +#endif // __ICH_DESCRIPTORS_H__ > +#endif // defined(__i386__) || defined(__x86_64__) > diff --git a/ichspi.c b/ichspi.c > index 2480fa5..b5ee23a 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -30,6 +30,7 @@ > #include "chipdrivers.h" > #include "programmer.h" > #include "spi.h" > +#include "ich_descriptors.h" > > /* ICH9 controller register definition */ > #define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ > @@ -120,6 +121,14 @@ > #define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */ > #define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */ > > +#define ICH9_REG_LVSCC 0xC4 /* 32 Bits Host Lower Vendor Specific Component Capabilities */ > +#define ICH9_REG_UVSCC 0xC8 /* 32 Bits Host Upper Vendor Specific Component Capabilities */ > +/* The individual fields of the VSCC registers are defined in the file > + * ich_descriptors.h. The reason is that the same fields are also used in the > + * flash descriptors to define the properties of the different flash chips > + * supported by the BIOS image. These descriptors are also the source for the > + * registers above. */ > This comment is a bit unclear to me. > + > #define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */ > #define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */ > #define FPB_FPBA (0x1FFF << FPB_FPBA_OFF) > @@ -302,8 +311,6 @@ static void prettyprint_opcodes(OPCODES *ops) > } > } > > -#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF) > - > static void prettyprint_ich9_reg_hsfs(uint16_t reg_val) > { > msg_pdbg("HSFS: "); > @@ -1130,9 +1137,6 @@ static int ich_spi_send_multicommand(struct spi_command *cmds) > #define ICH_BRWA(x) ((x >> 8) & 0xff) > #define ICH_BRRA(x) ((x >> 0) & 0xff) > > -#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff) > -#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff) > - > static void do_ich9_spi_frap(uint32_t frap, int i) > { > static const char *const access_names[4] = { > @@ -1159,9 +1163,8 @@ static void do_ich9_spi_frap(uint32_t frap, int i) > return; > } > > - msg_pdbg("0x%08x-0x%08x is %s\n", > - (base << 12), (limit << 12) | 0x0fff, > - access_names[rwperms]); > + msg_pdbg("0x%08x-0x%08x is %s\n", base, (limit | 0x0fff), > + access_names[rwperms]); > } > > static const struct spi_programmer spi_programmer_ich7 = { > @@ -1191,6 +1194,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > uint8_t old, new; > uint16_t spibar_offset, tmp2; > uint32_t tmp; > + int ichspi_desc = 0; > > switch (ich_generation) { > case 7: > @@ -1262,6 +1266,8 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); > ichspi_lock = 1; > } > + if (tmp2 & HSFS_FDV) > + ichspi_desc = 1; > > tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); > msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); > @@ -1312,9 +1318,26 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); > msg_pdbg("0xA0: 0x%08x (BBAR)\n", > ichspi_bbar); > + > + tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); > + msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp); > + msg_pdbg("LVSCC: "); > + prettyprint_ich9_reg_vscc(tmp); > Does the block above work correctly for all ICH8 and later chipsets? > + > + tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); > + msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp); > + msg_pdbg("UVSCC: "); > + prettyprint_ich9_reg_vscc(tmp); > Ditto. > + > tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); > msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp); > > + msg_pdbg("\n"); > + if (ichspi_desc) { > + struct flash_descriptors desc = {{ 0 }}; > + read_ich_descriptors_via_fdo(ich_spibar, &desc); > Odd code structure, but I see what you're trying to do. Makes sense. > + prettyprint_ich_descriptors(CHIPSET_UNKNOWN, &desc); > Hmmm... I really would like to see this fixed, but it's OK if you want to do that in a followup patch. > + } > ich_init_opcodes(); > break; > default: > Regards, Carl-Daniel -- http://www.hailfinger.org/

2 2

[PATCH] Be optionally seriously pedantic
by Stefan Tauner 09 Aug '11

09 Aug '11

This allows to easily test flashrom with numerous compiler warnings enabled. A new variable "PEDANTIC" is introduced which disables the feature by default, but can be overriden on the CLI. Additionally a new phony target "pedantic" is introduced which disables -Werror, enables the pedantic warnings and calls the default target recursively. It also has 'clean' as prerequisite to create consistent output. --- TODO: - make it possible to execute other targets with make pedantic(?) (something like "make pedantic target=djgpp-dos") - refine warnings used Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- Makefile | 21 +++++++++++++++++++-- 1 files changed, 19 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index c72d10a..7289bed 100644 --- a/Makefile +++ b/Makefile @@ -32,11 +32,22 @@ AR ?= ar RANLIB ?= ranlib WARNERROR ?= yes +PEDANTIC ?= no ifeq ($(WARNERROR), yes) CFLAGS += -Werror endif +ifeq ($(PEDANTIC), yes) +CFLAGS += -std=c99 --pedantic -Wextra -fstrict-aliasing\ + -Wmissing-include-dirs -Winit-self -Wswitch-enum \ + -Wundef -Wbad-function-cast -Wcast-qual -Wcast-align -Wconversion \ + -Wstrict-prototypes -Wmissing-declarations -Wredundant-decls\ + \ + -Wno-unused-parameter + # -Wno-missing-field-initializers -Wno-sign-conversion +endif + # Determine the destination processor architecture override ARCH = $(strip $(shell LC_ALL=C $(CC) -E arch.h|grep -v '^\#')) @@ -248,6 +259,7 @@ CLI_OBJS = flashrom.o cli_classic.o cli_output.o print.o PROGRAMMER_OBJS = udelay.o programmer.o all: pciutils features $(PROGRAM)$(EXEC_SUFFIX) + @echo $(CFLAGS) # Set the flashrom version string from the highest revision number # of the checked out flashrom files. @@ -643,8 +655,13 @@ tarball: export @echo Created $(EXPORTDIR)/flashrom-$(RELEASENAME).tar.bz2 djgpp-dos: clean - make CC=i586-pc-msdosdjgpp-gcc STRIP=i586-pc-msdosdjgpp-strip WARNERROR=no OS_ARCH=DOS + $(MAKE) CC=i586-pc-msdosdjgpp-gcc STRIP=i586-pc-msdosdjgpp-strip WARNERROR=no OS_ARCH=DOS + +pedantic: export WARNERROR=no +pedantic: export PEDANTIC=yes +pedantic: clean + $(MAKE) -.PHONY: all clean distclean compiler pciutils features export tarball dos featuresavailable +.PHONY: all clean distclean compiler pciutils features export tarball dos featuresavailable pedantic -include $(OBJS:.o=.d) -- 1.7.1

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Re: [flashrom] [PATCH 1/4] ichspi.c: refactor filling and reading the fdata/spid registers
by Stefan Tauner 08 Aug '11

08 Aug '11

On Thu, 21 Jul 2011 01:24:22 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > - add ich_fill_data to fill the chipset registers from an array > - add ich_read_data to copy the data from the chipset register into an array > - replace the existing code with calls to those functions > - minor cosmetic changes > > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> tested by david hendrix and finally committed in r1409 \o/ -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

[commit] r1409 - trunk
by repository service 08 Aug '11

08 Aug '11

Author: stefanct Date: Tue Aug 9 03:49:34 2011 New Revision: 1409 URL: http://flashrom.org/trac/flashrom/changeset/1409 Log: ichspi.c: refactor filling and reading the fdata/spid registers - add ich_fill_data to fill the chipset registers from an array - add ich_read_data to copy the data from the chipset register into an array - replace the existing code with calls to those functions - minor cosmetic changes Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Sun Aug 7 15:17:20 2011 (r1408) +++ trunk/ichspi.c Tue Aug 9 03:49:34 2011 (r1409) @@ -6,6 +6,7 @@ * Copyright (C) 2008 Dominik Geyer <dominik.geyer(a)kontron.com> * Copyright (C) 2008 coresystems GmbH <info(a)coresystems.de> * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger + * Copyright (C) 2011 Stefan Tauner * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,18 +23,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* - * This module is designed for supporting the devices - * ST M25P40 - * ST M25P80 - * ST M25P16 - * ST M25P32 already tested - * ST M25P64 - * AT 25DF321 already tested - * ... and many more SPI flash devices - * - */ - #if defined(__i386__) || defined(__x86_64__) #include <string.h> @@ -293,7 +282,7 @@ static OPCODES O_EXISTING = {}; /* pretty printing functions */ -static void pretty_print_opcodes(OPCODES *ops) +static void prettyprint_opcodes(OPCODES *ops) { if(ops == NULL) return; @@ -592,6 +581,51 @@ msg_perr("Setting BBAR failed!\n"); } +/* Read len bytes from the fdata/spid register into the data array. + * + * Note that using len > spi_programmer->max_data_read will return garbage or + * may even crash. + */ + static void ich_read_data(uint8_t *data, int len, int reg0_off) + { + int i; + uint32_t temp32 = 0; + + for (i = 0; i < len; i++) { + if ((i % 4) == 0) + temp32 = REGREAD32(reg0_off + i); + + data[i] = (temp32 >> ((i % 4) * 8)) & 0xff; + } +} + +/* Fill len bytes from the data array into the fdata/spid registers. + * + * Note that using len > spi_programmer->max_data_write will trash the registers + * following the data registers. + */ +static void ich_fill_data(const uint8_t *data, int len, int reg0_off) +{ + uint32_t temp32 = 0; + int i; + + if (len <= 0) + return; + + for (i = 0; i < len; i++) { + if ((i % 4) == 0) + temp32 = 0; + + temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8); + + if ((i % 4) == 3) /* 32 bits are full, write them to regs. */ + REGWRITE32(reg0_off + (i - (i % 4)), temp32); + } + i--; + if ((i % 4) != 3) /* Write remaining data to regs. */ + REGWRITE32(reg0_off + (i - (i % 4)), temp32); +} + /* This function generates OPCODES from or programs OPCODES to ICH according to * the chipset's SPI configuration lock. * @@ -627,7 +661,7 @@ } else { curopcodes = curopcodes_done; msg_pdbg("done\n"); - pretty_print_opcodes(curopcodes); + prettyprint_opcodes(curopcodes); msg_pdbg("\n"); return 0; } @@ -638,9 +672,8 @@ { int write_cmd = 0; int timeout; - uint32_t temp32 = 0; + uint32_t temp32; uint16_t temp16; - uint32_t a; uint64_t opmenu; int opcode_index; @@ -664,26 +697,8 @@ REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF) | temp32); /* Program data into SPID0 to N */ - if (write_cmd && (datalength != 0)) { - temp32 = 0; - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = 0; - } - - temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8); - - if ((a % 4) == 3) { - REGWRITE32(ICH7_REG_SPID0 + (a - (a % 4)), - temp32); - } - } - if (((a - 1) % 4) != 3) { - REGWRITE32(ICH7_REG_SPID0 + - ((a - 1) - ((a - 1) % 4)), temp32); - } - - } + if (write_cmd && (datalength != 0)) + ich_fill_data(data, datalength, ICH7_REG_SPID0); /* Assemble SPIS */ temp16 = REGREAD16(ICH7_REG_SPIS); @@ -764,17 +779,8 @@ return 1; } - if ((!write_cmd) && (datalength != 0)) { - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = REGREAD32(ICH7_REG_SPID0 + (a)); - } - - data[a] = - (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) - >> ((a % 4) * 8); - } - } + if ((!write_cmd) && (datalength != 0)) + ich_read_data(data, datalength, ICH7_REG_SPID0); return 0; } @@ -785,7 +791,6 @@ int write_cmd = 0; int timeout; uint32_t temp32; - uint32_t a; uint64_t opmenu; int opcode_index; @@ -810,25 +815,8 @@ REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32); /* Program data into FDATA0 to N */ - if (write_cmd && (datalength != 0)) { - temp32 = 0; - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = 0; - } - - temp32 |= ((uint32_t) data[a]) << ((a % 4) * 8); - - if ((a % 4) == 3) { - REGWRITE32(ICH9_REG_FDATA0 + (a - (a % 4)), - temp32); - } - } - if (((a - 1) % 4) != 3) { - REGWRITE32(ICH9_REG_FDATA0 + - ((a - 1) - ((a - 1) % 4)), temp32); - } - } + if (write_cmd && (datalength != 0)) + ich_fill_data(data, datalength, ICH9_REG_FDATA0); /* Assemble SSFS + SSFC */ temp32 = REGREAD32(ICH9_REG_SSFS); @@ -916,17 +904,8 @@ return 1; } - if ((!write_cmd) && (datalength != 0)) { - for (a = 0; a < datalength; a++) { - if ((a % 4) == 0) { - temp32 = REGREAD32(ICH9_REG_FDATA0 + (a)); - } - - data[a] = - (temp32 & (((uint32_t) 0xff) << ((a % 4) * 8))) - >> ((a % 4) * 8); - } - } + if ((!write_cmd) && (datalength != 0)) + ich_read_data(data, datalength, ICH9_REG_FDATA0); return 0; }

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Re: [flashrom] [PATCH 8/8] Added (N) to the name of MX29F002B/T devices.
by Idwer Vollering 07 Aug '11

07 Aug '11

2011/3/15 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at>: > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Idwer Vollering <vidwer(a)gmail.com> But *only* if the probe/read/erase/write status is not affected. > --- > flashchips.c | 4 ++-- > flashchips.h | 4 ++-- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/flashchips.c b/flashchips.c > index 7cb7d39..97aafef 100644 > --- a/flashchips.c > +++ b/flashchips.c > @@ -4209,7 +4209,7 @@ struct flashchip flashchips[] = { > > { > .vendor = "Macronix", > - .name = "MX29F002B", > + .name = "MX29F002(N)B", > .bustype = CHIP_BUSTYPE_PARALLEL, > .manufacture_id = MACRONIX_ID, > .model_id = MACRONIX_MX29F002B, > @@ -4240,7 +4240,7 @@ struct flashchip flashchips[] = { > > { > .vendor = "Macronix", > - .name = "MX29F002T", > + .name = "MX29F002(N)T", > .bustype = CHIP_BUSTYPE_PARALLEL, > .manufacture_id = MACRONIX_ID, > .model_id = MACRONIX_MX29F002T, > diff --git a/flashchips.h b/flashchips.h > index 9b08d25..9782188 100644 > --- a/flashchips.h > +++ b/flashchips.h > @@ -361,8 +361,8 @@ > #define MACRONIX_MX25L3235D 0x5E16 /* MX25L3225D/MX25L3235D/MX25L3237D */ > #define MACRONIX_MX29F001B 0x19 > #define MACRONIX_MX29F001T 0x18 > -#define MACRONIX_MX29F002B 0x34 /* Same as MX29F002NB */ > -#define MACRONIX_MX29F002T 0xB0 /* Same as MX29F002NT */ > +#define MACRONIX_MX29F002B 0x34 /* Same as MX29F002NB; N has reset pin n/c. */ > +#define MACRONIX_MX29F002T 0xB0 /* Same as MX29F002NT; N has reset pin n/c. */ > #define MACRONIX_MX29F004B 0x46 > #define MACRONIX_MX29F004T 0x45 > #define MACRONIX_MX29F022T 0x36 /* Same as MX29F022NT */ > -- > 1.7.1 > > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom >

2 2

A8M2N-LA fail
by Márton Miklós 07 Aug '11

07 Aug '11

Hello all, I have just tried to flash my BIOS using the flashrom, and I have ran into the following situation: lucifer@lucifer-desktop:~/Letöltések/flashrom-0.9.4$ sudo ./flashrom -w /tmp/sp35111/3.10 flashrom v0.9.4-r1395 on Linux 2.6.35-28-generic (i686), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "NVIDIA MCP51". This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x23, failed byte count from 0x00000000-0x00000fff: 0xfec ERASE FAILED! Reading current flash chip contents... done. ERASE FAILED at 0x00000000! Expected=0xff, Read=0x23, failed byte count from 0x00000000-0x0000ffff: 0xfef9 ERASE FAILED! Reading current flash chip contents... done. ERASE FAILED at 0x00000000! Expected=0xff, Read=0x23, failed byte count from 0x00000000-0x0007ffff: 0x6494b ERASE FAILED! FAILED! Uh oh. Erase/write failed. Checking if anything changed. Good. It seems nothing was changed. Writing to the flash chip apparently didn't do anything. This means we have to add special support for your board, programmer or flash chip. Please report this on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- You may now reboot or simply leave the machine running. Flashrom info: lucifer@lucifer-desktop:~/Letöltések/flashrom-0.9.4$ sudo ./flashrom flashrom v0.9.4-r1395 on Linux 2.6.35-28-generic (i686), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "NVIDIA MCP51". This chipset is marked as untested. If you are using an up-to-date version of flashrom please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH) at physical address 0xfff80000. No operations were specified. I have tried the latest revision (1402) but it did not works too. Let me know if I should provide any additional information. Regards, Miklós Márton

4 5

[commit] r1408 - trunk
by repository service 07 Aug '11

07 Aug '11

Author: stefanct Date: Sun Aug 7 15:17:20 2011 New Revision: 1408 URL: http://flashrom.org/trac/flashrom/changeset/1408 Log: Add a board enable for ASUS A8M2N-LA (HP OEM "NodusM3-GL8E") It is based on Joshua Roys' RE. http://www.flashrom.org/pipermail/flashrom/2011-August/007504.html Tested-by: Márton Miklós Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/chipset_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sat Aug 6 18:16:45 2011 (r1407) +++ trunk/board_enable.c Sun Aug 7 15:17:20 2011 (r1408) @@ -921,6 +921,7 @@ /* * Suited for: + * - ASUS A8M2N-LA (HP OEM "NodusM3-GL8E"): NVIDIA MCP51 * - ASUS A8N-LA (HP OEM "Nagami-GL8E"): NVIDIA MCP51 * - ASUS M2NBP-VM CSM: NVIDIA MCP51 */ @@ -2000,6 +2001,7 @@ {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, P3, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise}, {0x1002, 0x4372, 0x103c, 0x2a26, 0x1002, 0x4377, 0x103c, 0x2a26, NULL, NULL, NULL, P3, "ASUS", "A8AE-LE", 0, OK, amd_sbxxx_gpio9_raise}, {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, P3, "ASUS", "A8Jm", 0, NT, intel_ich_gpio34_raise}, + {0x10DE, 0x0260, 0x103C, 0x2A34, 0x10DE, 0x0264, 0x103C, 0x2A34, "NODUSM3", NULL, NULL, P3, "ASUS", "A8M2N-LA (NodusM3-GL8E)", 0, OK, nvidia_mcp_gpio0_raise}, {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI2L", NULL, NULL, P3, "ASUS", "A8N-LA (Nagami-GL8E)", 0, OK, nvidia_mcp_gpio0_raise}, {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, "^A8N-SLI DELUXE", NULL, NULL, P3, "ASUS", "A8N-SLI Deluxe", 0, NT, board_shuttle_fn25}, {0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, P3, "ASUS", "A8N-VM CSM", 0, OK, w83627ehf_gpio22_raise_2e}, Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Sat Aug 6 18:16:45 2011 (r1407) +++ trunk/chipset_enable.c Sun Aug 7 15:17:20 2011 (r1408) @@ -1096,7 +1096,7 @@ {0x10de, 0x00e0, OK, "NVIDIA", "NForce3", enable_flash_nvidia_nforce2}, /* Slave, should not be here, to fix known bug for A01. */ {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804}, - {0x10de, 0x0260, NT, "NVIDIA", "MCP51", enable_flash_ck804}, + {0x10de, 0x0260, OK, "NVIDIA", "MCP51", enable_flash_ck804}, {0x10de, 0x0261, NT, "NVIDIA", "MCP51", enable_flash_ck804}, {0x10de, 0x0262, NT, "NVIDIA", "MCP51", enable_flash_ck804}, {0x10de, 0x0263, NT, "NVIDIA", "MCP51", enable_flash_ck804}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Sat Aug 6 18:16:45 2011 (r1407) +++ trunk/print.c Sun Aug 7 15:17:20 2011 (r1408) @@ -420,6 +420,7 @@ B("ASUS", "A7V8X-MX SE", 1, "http://www.asus.com/product.aspx?P_ID=1guVBT1qV5oqhHyZ", NULL), B("ASUS", "A7V8X-X", 1, "http://www.asus.com/product.aspx?P_ID=YcXfRrWHZ9RKoVmw", NULL), B("ASUS", "A8Jm", 1, "http://www.asus.com/product.aspx?P_ID=VztICtOgiU6drx4m", NULL), + B("ASUS", "A8M2N-LA (NodusM3-GL8E)", 1, "http://h10010.www1.hp.com/ewfrf/wc/document?docname=c00757531&cc=us&dlc=en&…", "This is an OEM board from HP, the HP name is NodusM3-GL8E."), B("ASUS", "A8N-E", 1, "http://www.asus.com/product.aspx?P_ID=DzbA8hgqchMBOVRz", NULL), B("ASUS", "A8N-LA (Nagami-GL8E)", 1, "http://h10025.www1.hp.com/ewfrf/wc/document?lc=en&cc=us&docname=c00647121&d…", "This is an OEM board from HP, the HP name is Nagami-GL8E."), B("ASUS", "A8N-SLI", 1, "http://www.asus.com/product.aspx?P_ID=J9FKa8z2xVId3pDK", NULL),

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flashrom support for EP-9NPA7I
by Stefan Tauner 07 Aug '11

07 Aug '11

hello clr! you have missed carl-daniel or vice-versa one time and you never came back after that. i have dug up some info about the predecessor of your board i.e. 8NPA7I. the board enable that was executed on your machine by mistake is not complete (not even for the 8NPA7I) so it is expected to not work for you. i have not reverse engineered your bios (update tool), so i am not sure at all that the attached patch would help and not reboot/ruin/ignite your machine. but if you are brave you can try it. PS: this patch is not for merge, because we have no idea what 0x92 really does imho. but we could incorporate this into a board enable function, if it really works or do you (fellow flashrom dev) think it is ok to just merge it as is? PPS: this is just a port of http://patchwork.coreboot.org/patch/2125/ -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[PATCH 2/2] Nvidia chipset enables: refactor setting bit 0 in 0x6d
by Stefan Tauner 07 Aug '11

07 Aug '11

This also changes semantics: previously failing to set this was interpreted as error by enable_flash_ck804 and enable_flash_mcp55 although the output indicates otherwise. Also, in enable_flash_nvidia_nforce2 there was no check if settings the bit succeeds. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- chipset_enable.c | 49 ++++++++++++++++++++----------------------------- 1 files changed, 20 insertions(+), 29 deletions(-) diff --git a/chipset_enable.c b/chipset_enable.c index 294007d..03ccaa2 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -784,16 +784,27 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name) return ret; } -static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name) +/* sets bit 0 in 0x6d */ +static void enable_flash_nvidia_common(struct pci_dev *dev, const char *name) { - uint8_t tmp; + uint8_t old, new; - rpci_write_byte(dev, 0x92, 0); + old = pci_read_byte(dev, 0x6d); + new = old | 0x01; + if (new == old) + return; + rpci_write_byte(dev, 0x6d, new); - tmp = pci_read_byte(dev, 0x6d); - tmp |= 0x01; - rpci_write_byte(dev, 0x6d, tmp); + if (pci_read_byte(dev, 0x6d) != new) { + msg_pinfo("Setting register 0x%x to 0x%x on %s failed " + "(WARNING ONLY).\n", 0x6d, new, name); + } +} +static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name) +{ + rpci_write_byte(dev, 0x92, 0); + enable_flash_nvidia_common(dev, name); return 0; } @@ -859,17 +870,7 @@ ck804_lockbits_done: } } - old = pci_read_byte(dev, 0x6d); - new = old | 0x01; - if (new == old) - return 0; - rpci_write_byte(dev, 0x6d, new); - - if (pci_read_byte(dev, 0x6d) != new) { - msg_pinfo("Setting register 0x%x to 0x%x on %s failed " - "(WARNING ONLY).\n", 0x6d, new, name); - return -1; - } + enable_flash_nvidia_common(dev, name); return 0; } @@ -929,7 +930,7 @@ static int enable_flash_sb400(struct pci_dev *dev, const char *name) static int enable_flash_mcp55(struct pci_dev *dev, const char *name) { - uint8_t old, new, val; + uint8_t val; uint16_t wordval; /* Set the 0-16 MB enable bits. */ @@ -943,17 +944,7 @@ static int enable_flash_mcp55(struct pci_dev *dev, const char *name) wordval |= 0x7fff; /* 16M */ rpci_write_word(dev, 0x90, wordval); - old = pci_read_byte(dev, 0x6d); - new = old | 0x01; - if (new == old) - return 0; - rpci_write_byte(dev, 0x6d, new); - - if (pci_read_byte(dev, 0x6d) != new) { - msg_pinfo("Setting register 0x%x to 0x%x on %s failed " - "(WARNING ONLY).\n", 0x6d, new, name); - return -1; - } + enable_flash_nvidia_common(dev, name); return 0; } -- 1.7.1

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flashrom August 2011