March 2011 - flashrom - mail.coreboot.org

Asus P5VD1-X: Instant success
by Olle Gross June 19, 2011

June 19, 2011

Hi, just wanted to tell that i successfully flashed the bios of my old Asus P5VD1-X with flashrom, so i guess it could be added to the supported list. Attaching output of flashrom -V, lspci -nnvvvxxx, superiotool -deV. New bios version 0704 downloaded from asus.com, can't link directly cos they require captcha for download. Everything works just fine, and the bios menu reports the new version. Just one thing that might or might not be of any importance, i noted that lspci reports the board as "ASUSTeK Computer Inc. P4V800D-X Mainboard [1043:8199]". This is wrong, it's a P5VD1-X - at least it says so on the board. You think this could cause any problems, or is it just cosmetic? Regards, Olof

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SST39SF020A write ok, and message question
by Andrew Morgan June 19, 2011

June 19, 2011

Log attached. When running 'flashrom' on its own I got this message: This flash part has status UNTESTED for operations: WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Should the text "Please mention your board in the subject line." in this case say "flash part" or "flash chp" instead of "board"? I'm assuming the board name is important for un-tested boards or board enables, whereas in this case it is the flash chip name which is important? -- Andrew.

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Success report: Tyan S2723
by Uwe Hermann June 19, 2011

June 19, 2011

Hi, I tested flashrom on the Tyan S2723 board, works fine. Logs attached. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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Test results for flashrom on Asus P5N32-E SLI motherboard
by Paul Brookman June 19, 2011

June 19, 2011

This is the output from flashing the bios chip on an Asus P5N32-E motherboard. Flashrom worked without a problem backing up and updating the bios. Many thanks, Paul Brookman

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[PATCH][FIXME] Add missing Intel/VIA chipset IDs
by Carl-Daniel Hailfinger June 13, 2011

June 13, 2011

This patch is unfinished, and _you_ can finish it! Reorder chipset entries by PCI ID instead of by name. Makes it easier to keep track of what's already there. Add VIA VX855. Add countless Intel IDs (unfinished). If you have some spare time, please take a look at all the new Intel entries which have no name and no chipset enable function. They all represent LPC bridges I found in the PCI ID database. Intel may have deleted the names for some of the IDs in the database because these chips were "Engineering samples", but I know of at least one engineering sample which was used in production boards. You can add a comment to the entry or use a name that contains "ICH... Engineering Sample". Your choice. Patch does not compile because the Intel entries are unfinished. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-chipset_support_intel_via/chipset_enable.c =================================================================== --- flashrom-chipset_support_intel_via/chipset_enable.c (Revision 987) +++ flashrom-chipset_support_intel_via/chipset_enable.c (Arbeitskopie) @@ -1285,69 +1285,51 @@ return 0; } -/* Please keep this list alphabetically sorted by vendor/device. */ +/* Please keep this list numerically sorted by vendor/device. */ const struct penable chipset_enables[] = { - {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533}, + {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400}, + {0x1002, 0x438d, OK, "AMD", "SB600", enable_flash_sb600}, + {0x1002, 0x439d, OK, "AMD", "SB700/SB710/SB750", enable_flash_sb600}, + {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100}, + {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536}, + {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536}, + {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520}, {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111}, {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, + {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501}, + {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496}, + {0x1039, 0x0530, NT, "SiS", "530", enable_flash_sis530}, + {0x1039, 0x0540, NT, "SiS", "540", enable_flash_sis540}, + {0x1039, 0x0620, NT, "SiS", "620", enable_flash_sis530}, + {0x1039, 0x0630, NT, "SiS", "630", enable_flash_sis540}, + {0x1039, 0x0635, NT, "SiS", "635", enable_flash_sis540}, + {0x1039, 0x0640, NT, "SiS", "640", enable_flash_sis540}, + {0x1039, 0x0645, NT, "SiS", "645", enable_flash_sis540}, + {0x1039, 0x0646, NT, "SiS", "645DX", enable_flash_sis540}, + {0x1039, 0x0648, NT, "SiS", "648", enable_flash_sis540}, + {0x1039, 0x0650, NT, "SiS", "650", enable_flash_sis540}, + {0x1039, 0x0651, NT, "SiS", "651", enable_flash_sis540}, + {0x1039, 0x0655, NT, "SiS", "655", enable_flash_sis540}, + {0x1039, 0x0730, NT, "SiS", "730", enable_flash_sis540}, + {0x1039, 0x0733, NT, "SiS", "733", enable_flash_sis540}, + {0x1039, 0x0735, OK, "SiS", "735", enable_flash_sis540}, + {0x1039, 0x0740, NT, "SiS", "740", enable_flash_sis540}, + {0x1039, 0x0745, NT, "SiS", "745", enable_flash_sis540}, + {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis540}, + {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis540}, + {0x1039, 0x0755, NT, "SiS", "755", enable_flash_sis540}, + {0x1039, 0x5511, NT, "SiS", "5511", enable_flash_sis5511}, + {0x1039, 0x5571, NT, "SiS", "5571", enable_flash_sis530}, + {0x1039, 0x5591, NT, "SiS", "5591/5592", enable_flash_sis530}, + {0x1039, 0x5596, NT, "SiS", "5596", enable_flash_sis5511}, + {0x1039, 0x5597, NT, "SiS", "5597/5598/5581/5120", enable_flash_sis530}, + {0x1039, 0x5600, NT, "SiS", "600", enable_flash_sis530}, {0x1078, 0x0100, OK, "AMD", "CS5530(A)", enable_flash_cs5530}, - {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536}, - {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536}, - {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520}, - {0x1002, 0x438D, OK, "AMD", "SB600", enable_flash_sb600}, - {0x1002, 0x439d, OK, "AMD", "SB700/SB710/SB750", enable_flash_sb600}, - {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100}, - {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400}, - {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000}, - {0x8086, 0x3b00, NT, "Intel", "3400 Desktop", enable_flash_ich10}, - {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_ich10}, - {0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF", enable_flash_ich10}, - {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4}, - {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich_4e}, - {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich_dc}, - {0x8086, 0x5031, OK, "Intel", "EP80579", enable_flash_ich7}, - {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e}, - {0x8086, 0x3a18, OK, "Intel", "ICH10", enable_flash_ich10}, - {0x8086, 0x3a1a, OK, "Intel", "ICH10D", enable_flash_ich10}, - {0x8086, 0x3a14, OK, "Intel", "ICH10DO", enable_flash_ich10}, - {0x8086, 0x3a16, OK, "Intel", "ICH10R", enable_flash_ich10}, - {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich_4e}, - {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich_4e}, - {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich_4e}, - {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich_4e}, - {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich_4e}, - {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich_4e}, - {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich_4e}, - {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich_dc}, - {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich_dc}, - {0x8086, 0x27b0, OK, "Intel", "ICH7DH", enable_flash_ich7}, - {0x8086, 0x27b8, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7}, - {0x8086, 0x27b9, OK, "Intel", "ICH7M", enable_flash_ich7}, - {0x8086, 0x27bd, OK, "Intel", "ICH7MDH", enable_flash_ich7}, - {0x8086, 0x27bc, OK, "Intel", "NM10", enable_flash_ich7}, - {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e}, - {0x8086, 0x2812, OK, "Intel", "ICH8DH", enable_flash_ich8}, - {0x8086, 0x2814, OK, "Intel", "ICH8DO", enable_flash_ich8}, - {0x8086, 0x2810, OK, "Intel", "ICH8/ICH8R", enable_flash_ich8}, - {0x8086, 0x2815, OK, "Intel", "ICH8M", enable_flash_ich8}, - {0x8086, 0x2811, OK, "Intel", "ICH8M-E", enable_flash_ich8}, - {0x8086, 0x2918, OK, "Intel", "ICH9", enable_flash_ich9}, - {0x8086, 0x2912, OK, "Intel", "ICH9DH", enable_flash_ich9}, - {0x8086, 0x2914, OK, "Intel", "ICH9DO", enable_flash_ich9}, - {0x8086, 0x2919, OK, "Intel", "ICH9M", enable_flash_ich9}, - {0x8086, 0x2917, OK, "Intel", "ICH9M-E", enable_flash_ich9}, - {0x8086, 0x2916, OK, "Intel", "ICH9R", enable_flash_ich9}, - {0x8086, 0x2910, OK, "Intel", "ICH9 Engineering Sample", enable_flash_ich9}, - {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4}, - {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4}, - {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4}, - {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4}, - {0x8086, 0x8119, OK, "Intel", "Poulsbo", enable_flash_poulsbo}, + {0x10b9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533}, {0x10de, 0x0030, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2}, {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */ {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */ {0x10de, 0x0060, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2}, - /* Slave, should not be here, to fix known bug for A01. */ {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804}, {0x10de, 0x0260, NT, "NVIDIA", "MCP51", enable_flash_ck804}, {0x10de, 0x0261, NT, "NVIDIA", "MCP51", enable_flash_ck804}, @@ -1377,46 +1359,105 @@ {0x10de, 0x0aad, NT, "NVIDIA", "MCP79", enable_flash_mcp7x}, {0x10de, 0x0aae, NT, "NVIDIA", "MCP79", enable_flash_mcp7x}, {0x10de, 0x0aaf, NT, "NVIDIA", "MCP79", enable_flash_mcp7x}, - {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496}, - {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501}, - {0x1039, 0x5511, NT, "SiS", "5511", enable_flash_sis5511}, - {0x1039, 0x5596, NT, "SiS", "5596", enable_flash_sis5511}, - {0x1039, 0x5571, NT, "SiS", "5571", enable_flash_sis530}, - {0x1039, 0x5591, NT, "SiS", "5591/5592", enable_flash_sis530}, - {0x1039, 0x5597, NT, "SiS", "5597/5598/5581/5120", enable_flash_sis530}, - {0x1039, 0x0530, NT, "SiS", "530", enable_flash_sis530}, - {0x1039, 0x5600, NT, "SiS", "600", enable_flash_sis530}, - {0x1039, 0x0620, NT, "SiS", "620", enable_flash_sis530}, - {0x1039, 0x0540, NT, "SiS", "540", enable_flash_sis540}, - {0x1039, 0x0630, NT, "SiS", "630", enable_flash_sis540}, - {0x1039, 0x0635, NT, "SiS", "635", enable_flash_sis540}, - {0x1039, 0x0640, NT, "SiS", "640", enable_flash_sis540}, - {0x1039, 0x0645, NT, "SiS", "645", enable_flash_sis540}, - {0x1039, 0x0646, NT, "SiS", "645DX", enable_flash_sis540}, - {0x1039, 0x0648, NT, "SiS", "648", enable_flash_sis540}, - {0x1039, 0x0650, NT, "SiS", "650", enable_flash_sis540}, - {0x1039, 0x0651, NT, "SiS", "651", enable_flash_sis540}, - {0x1039, 0x0655, NT, "SiS", "655", enable_flash_sis540}, - {0x1039, 0x0730, NT, "SiS", "730", enable_flash_sis540}, - {0x1039, 0x0733, NT, "SiS", "733", enable_flash_sis540}, - {0x1039, 0x0735, OK, "SiS", "735", enable_flash_sis540}, - {0x1039, 0x0740, NT, "SiS", "740", enable_flash_sis540}, - {0x1039, 0x0745, NT, "SiS", "745", enable_flash_sis540}, - {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis540}, - {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis540}, - {0x1039, 0x0755, NT, "SiS", "755", enable_flash_sis540}, - {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x}, - {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x}, + {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, + {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111}, + {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111}, {0x1106, 0x3074, NT, "VIA", "VT8233", enable_flash_vt823x}, {0x1106, 0x3147, OK, "VIA", "VT8233A", enable_flash_vt823x}, {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x}, {0x1106, 0x3227, OK, "VIA", "VT8237", enable_flash_vt823x}, {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x}, {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi}, - {0x1106, 0x8353, OK, "VIA", "VX800", enable_flash_vt8237s_spi}, - {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111}, - {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, - {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111}, + {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x}, + {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x}, + {0x1106, 0x8353, OK, "VIA", "VX800/VX820", enable_flash_vt8237s_spi}, + {0x1106, 0x8409, NT, "VIA", "VX855/VX875", enable_flash_vt8237s_spi}, + {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000}, + {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4}, + {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4}, + {0x8086, 0x1c42, NT, "Intel", "", enable_flash_}, + {0x8086, 0x1c43, NT, "Intel", "", enable_flash_}, + {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e}, + {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e}, + {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich_4e}, + {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich_4e}, + {0x8086, 0x2450, NT, "Intel", "", enable_flash_}, + {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich_4e}, + {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich_4e}, + {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich_4e}, + {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich_4e}, + {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich_4e}, + {0x8086, 0x24dc, NT, "Intel", "", enable_flash_}, + {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich_4e}, + {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich_dc}, + {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich_dc}, + {0x8086, 0x2642, NT, "Intel", "", enable_flash_}, + {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich_dc}, + {0x8086, 0x27b0, OK, "Intel", "ICH7DH", enable_flash_ich7}, + {0x8086, 0x27b8, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7}, + {0x8086, 0x27b9, OK, "Intel", "ICH7M", enable_flash_ich7}, + {0x8086, 0x27bc, OK, "Intel", "NM10", enable_flash_ich7}, + {0x8086, 0x27bd, OK, "Intel", "ICH7MDH", enable_flash_ich7}, + {0x8086, 0x2810, OK, "Intel", "ICH8/ICH8R", enable_flash_ich8}, + {0x8086, 0x2811, OK, "Intel", "ICH8M-E", enable_flash_ich8}, + {0x8086, 0x2812, OK, "Intel", "ICH8DH", enable_flash_ich8}, + {0x8086, 0x2814, OK, "Intel", "ICH8DO", enable_flash_ich8}, + {0x8086, 0x2815, OK, "Intel", "ICH8M", enable_flash_ich8}, + {0x8086, 0x2910, OK, "Intel", "ICH9 Engineering Sample", enable_flash_ich9}, + {0x8086, 0x2911, NT, "Intel", "", enable_flash_}, + {0x8086, 0x2912, OK, "Intel", "ICH9DH", enable_flash_ich9}, + {0x8086, 0x2913, NT, "Intel", "", enable_flash_}, + {0x8086, 0x2914, OK, "Intel", "ICH9DO", enable_flash_ich9}, + {0x8086, 0x2915, NT, "Intel", "", enable_flash_}, + {0x8086, 0x2916, OK, "Intel", "ICH9R", enable_flash_ich9}, + {0x8086, 0x2917, OK, "Intel", "ICH9M-E", enable_flash_ich9}, + {0x8086, 0x2918, OK, "Intel", "ICH9", enable_flash_ich9}, + {0x8086, 0x2919, OK, "Intel", "ICH9M", enable_flash_ich9}, + {0x8086, 0x3a10, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3a14, OK, "Intel", "ICH10DO", enable_flash_ich10}, + {0x8086, 0x3a16, OK, "Intel", "ICH10R", enable_flash_ich10}, + {0x8086, 0x3a18, OK, "Intel", "ICH10", enable_flash_ich10}, + {0x8086, 0x3a1a, OK, "Intel", "ICH10D", enable_flash_ich10}, + {0x8086, 0x3a1e, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b00, NT, "Intel", "3400 Desktop", enable_flash_ich10}, + {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_ich10}, + {0x8086, 0x3b02, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b03, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b04, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b05, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b06, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b07, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b08, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b09, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b0a, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b0b, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b0c, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF", enable_flash_ich10}, + {0x8086, 0x3b0e, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b0f, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b10, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b11, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b12, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b13, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b14, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b15, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b16, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b17, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b18, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b19, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b1a, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b1b, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b1c, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b1d, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b1e, NT, "Intel", "", enable_flash_}, + {0x8086, 0x3b1f, NT, "Intel", "", enable_flash_}, + {0x8086, 0x5031, OK, "Intel", "EP80579", enable_flash_ich7}, + {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4}, + {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4}, + {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4}, + {0x8086, 0x7600, NT, "Intel", "", enable_flash_}, + {0x8086, 0x8119, OK, "Intel", "Poulsbo", enable_flash_poulsbo}, + {0x8086, 0x8186, NT, "Intel", "", enable_flash_}, {}, }; -- http://www.hailfinger.org/

3 4

MSI 848P Neo-V (MS-6788-040) flashrom v0.9.3-r1247 on Linux 2.6.26-2-686 (i686)
by Melroy van den Berg June 9, 2011

June 9, 2011

Hi, After this patch applied: http://patchwork.coreboot.org/patch/2452/ And finnaly added " -p internal:boardenable=force" to the command line. It says VERIFIED, I think everything went well using the MSI 848P Neo-V motherboard. server-pc:/home/melroy# flashrom -p internal:boardenable=force -w A6788IMS.610 flashrom v0.9.3-r1247 on Linux 2.6.26-2-686 (i686), built with libpci 3.0.0, GCC 4.3.2, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH5/ICH5R", enabling flash write... OK. This chipset supports the following protocols: FWH. NOTE: Running an untested board enable procedure. Please report success/failure to flashrom(a)flashrom.org with your board name and SUCCESS or FAILURE in the subject. Disabling flash write protection for board "MSI MS-6788-040 (848P NeoV)"... OK. Found chip "Winbond W39V040FA" (512 KB, FWH) at physical address 0xfff80000. === This flash part has status UNTESTED for operations: WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Flash image seems to be a legacy BIOS. Disabling checks. Erasing and writing flash chip... Done. Verifying flash... VERIFIED. The (latest) BIOS can be found at the MSI website. -- Kind regards, Melroy van den Berg

2 1

Board enable for MSI MS-6788-040 (848P Neo-V)
by Maciej Pijanka June 9, 2011

June 9, 2011

Hello Its a boardenable patch based on Michael's work for MSI MS-6788-04. -- Maciej Pijanka I don't fear computers, I fear lack of them -- Isaac Asimov

4 4

Voltage & form-factor spreadsheet
by Steven Zakulec June 4, 2011

June 4, 2011

Hello, some weeks ago I asked carldani what I could do to help the flashrom project, and he mentioned that they could really use someone to go thru all the chips in flashchips.c and get the voltage range and form factor(s) for each chip listed there. This is the result of that project: a spreadsheet with the chip name, voltage range, form factors, connector type (pins, leads, etc). This covers all the chips as of v1143. If anyone else is interested, I also have a short text file with all of the form factor acronyms I came across and what they mean (I grabbed the definition from the datasheet). There's a few missing chips, and some values that I wasn't quite sure about. Comments would be greatly appreciated.

4 19

[PATCH] Lock printing for AMIC A25* and Atmel AT25*
by Carl-Daniel Hailfinger May 19, 2011

May 19, 2011

Add lock printing for AMIC A25L05PT, A25L05PU, A25L10PT, A25L10PU, A25L20PT, A25L20PU, A25L40PT, A25L40PU, A25L80P, A25L16PT, A25L16PU, A25L512, A25L010, A25L020, A25L040, A25L080, A25L016, A25L032, A25LQ032. Add lock printing for Atmel AT26DF081A, AT26DF161, AT26DF161A, AT26DF321. Move Atmel AT25*/AT26* lock related functions from spi25.c to at25.c. That code was originally committed in r1115, but chip specific functions shouldn't live in the generic spi25.c. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_prettyprint_statusreg_a25_at25/a25.c =================================================================== --- flashrom-spi_prettyprint_statusreg_a25_at25/a25.c (Revision 0) +++ flashrom-spi_prettyprint_statusreg_a25_at25/a25.c (Revision 0) @@ -0,0 +1,103 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2010 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "flash.h" +#include "chipdrivers.h" +#include "spi.h" + +/* Prettyprint the status register. Works for AMIC A25L series. */ + +int spi_prettyprint_status_register_amic_a25l05p(struct flashchip *flash) +{ + uint8_t status; + + status = spi_read_status_register(); + msg_cdbg("Chip status register is %02x\n", status); + + msg_cdbg("Chip status register: Status Register Write Disable " + "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); + spi_prettyprint_status_register_bit(status, 6); + spi_prettyprint_status_register_bit(status, 5); + spi_prettyprint_status_register_bit(status, 4); + spi_prettyprint_status_register_bp3210(status, 1); + spi_prettyprint_status_register_welwip(status); + return 0; +} + +int spi_prettyprint_status_register_amic_a25l40p(struct flashchip *flash) +{ + uint8_t status; + + status = spi_read_status_register(); + msg_cdbg("Chip status register is %02x\n", status); + + msg_cdbg("Chip status register: Status Register Write Disable " + "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); + spi_prettyprint_status_register_bit(status, 6); + spi_prettyprint_status_register_bit(status, 5); + spi_prettyprint_status_register_bp3210(status, 2); + spi_prettyprint_status_register_welwip(status); + return 0; +} + +int spi_prettyprint_status_register_amic_a25l032(struct flashchip *flash) +{ + uint8_t status; + + status = spi_read_status_register(); + msg_cdbg("Chip status register is %02x\n", status); + + msg_cdbg("Chip status register: Status Register Write Disable " + "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); + msg_cdbg("Chip status register: Sector Protect Size (SEC) " + "is %i KB\n", (status & (1 << 6)) ? 4 : 64); + msg_cdbg("Chip status register: Top/Bottom (TB) " + "is %s\n", (status & (1 << 5)) ? "bottom" : "top"); + spi_prettyprint_status_register_bp3210(status, 2); + spi_prettyprint_status_register_welwip(status); + msg_cdbg("Chip status register 2 is NOT decoded!\n"); + return 0; +} + +int spi_prettyprint_status_register_amic_a25lq032(struct flashchip *flash) +{ + uint8_t status; + + status = spi_read_status_register(); + msg_cdbg("Chip status register is %02x\n", status); + + msg_cdbg("Chip status register: Status Register Write Disable " + "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); + msg_cdbg("Chip status register: Sector Protect Size (SEC) " + "is %i KB\n", (status & (1 << 6)) ? 4 : 64); + msg_cdbg("Chip status register: Top/Bottom (TB) " + "is %s\n", (status & (1 << 5)) ? "bottom" : "top"); + spi_prettyprint_status_register_bp3210(status, 2); + spi_prettyprint_status_register_welwip(status); + msg_cdbg("Chip status register 2 is NOT decoded!\n"); + return 0; +} + +/* FIXME: spi_disable_blockprotect is incorrect but works fine for chips using + * spi_prettyprint_status_register_amic_a25l05p or + * spi_prettyprint_status_register_amic_a25l40p. + * FIXME: spi_disable_blockprotect is incorrect and will fail randomly for chips + * using spi_prettyprint_status_register_amic_a25l032 or + * spi_prettyprint_status_register_amic_a25lq032. + */ Index: flashrom-spi_prettyprint_statusreg_a25_at25/Makefile =================================================================== --- flashrom-spi_prettyprint_statusreg_a25_at25/Makefile (Revision 1245) +++ flashrom-spi_prettyprint_statusreg_a25_at25/Makefile (Arbeitskopie) @@ -84,7 +84,8 @@ CHIP_OBJS = jedec.o stm50flw0x0x.o w39.o w29ee011.o \ sst28sf040.o m29f400bt.o 82802ab.o pm49fl00x.o \ - sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o sharplhf00l04.o + sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o sharplhf00l04.o \ + a25.o at25.o LIB_OBJS = layout.o Index: flashrom-spi_prettyprint_statusreg_a25_at25/at25.c =================================================================== --- flashrom-spi_prettyprint_statusreg_a25_at25/at25.c (Revision 0) +++ flashrom-spi_prettyprint_statusreg_a25_at25/at25.c (Revision 0) @@ -0,0 +1,287 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2010 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "flash.h" +#include "chipdrivers.h" +#include "spi.h" + +/* Prettyprint the status register. Works for Atmel A25/A26 series. */ + +static void spi_prettyprint_status_register_atmel_at25_srpl(uint8_t status) +{ + msg_cdbg("Chip status register: Sector Protection Register Lock (SRPL) " + "is %sset\n", (status & (1 << 7)) ? "" : "not "); +} + +static void spi_prettyprint_status_register_atmel_at25_epewpp(uint8_t status) +{ + msg_cdbg("Chip status register: Erase/Program Error (EPE) " + "is %sset\n", (status & (1 << 5)) ? "" : "not "); + msg_cdbg("Chip status register: WP# pin (WPP) " + "is %sasserted\n", (status & (1 << 4)) ? "not " : ""); +} + +static void spi_prettyprint_status_register_atmel_at25_swp(uint8_t status) +{ + msg_cdbg("Chip status register: Software Protection Status (SWP): "); + switch (status & (3 << 2)) { + case 0x0 << 2: + msg_cdbg("no sectors are protected\n"); + break; + case 0x1 << 2: + msg_cdbg("some sectors are protected\n"); + /* FIXME: Read individual Sector Protection Registers. */ + break; + case 0x3 << 2: + msg_cdbg("all sectors are protected\n"); + break; + default: + msg_cdbg("reserved for future use\n"); + break; + } +} + +int spi_prettyprint_status_register_at25df(struct flashchip *flash) +{ + uint8_t status; + + status = spi_read_status_register(); + msg_cdbg("Chip status register is %02x\n", status); + + spi_prettyprint_status_register_atmel_at25_srpl(status); + spi_prettyprint_status_register_bit(status, 6); + spi_prettyprint_status_register_atmel_at25_epewpp(status); + spi_prettyprint_status_register_atmel_at25_swp(status); + spi_prettyprint_status_register_welwip(status); + return 0; +} + +int spi_prettyprint_status_register_at25df_sec(struct flashchip *flash) +{ + /* FIXME: We should check the security lockdown. */ + msg_cdbg("Ignoring security lockdown (if present)\n"); + msg_cdbg("Ignoring status register byte 2\n"); + return spi_prettyprint_status_register_at25df(flash); +} + +int spi_prettyprint_status_register_at25f(struct flashchip *flash) +{ + uint8_t status; + + status = spi_read_status_register(); + msg_cdbg("Chip status register is %02x\n", status); + + spi_prettyprint_status_register_atmel_at25_srpl(status); + spi_prettyprint_status_register_bit(status, 6); + spi_prettyprint_status_register_atmel_at25_epewpp(status); + spi_prettyprint_status_register_bit(status, 3); + msg_cdbg("Chip status register: Block Protect 0 (BP0) is " + "%sset, %s sectors are protected\n", + (status & (1 << 2)) ? "" : "not ", + (status & (1 << 2)) ? "all" : "no"); + spi_prettyprint_status_register_welwip(status); + return 0; +} + +int spi_prettyprint_status_register_at25fs010(struct flashchip *flash) +{ + uint8_t status; + + status = spi_read_status_register(); + msg_cdbg("Chip status register is %02x\n", status); + + msg_cdbg("Chip status register: Status Register Write Protect (WPEN) " + "is %sset\n", (status & (1 << 7)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 6 / Block Protect 4 (BP4) is " + "%sset\n", (status & (1 << 6)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) is " + "%sset\n", (status & (1 << 5)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 4 is " + "%sset\n", (status & (1 << 4)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) is " + "%sset\n", (status & (1 << 3)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) is " + "%sset\n", (status & (1 << 2)) ? "" : "not "); + /* FIXME: Pretty-print detailed sector protection status. */ + spi_prettyprint_status_register_welwip(status); + return 0; +} + +int spi_prettyprint_status_register_at25fs040(struct flashchip *flash) +{ + uint8_t status; + + status = spi_read_status_register(); + msg_cdbg("Chip status register is %02x\n", status); + + msg_cdbg("Chip status register: Status Register Write Protect (WPEN) " + "is %sset\n", (status & (1 << 7)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 6 / Block Protect 4 (BP4) is " + "%sset\n", (status & (1 << 6)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) is " + "%sset\n", (status & (1 << 5)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 4 / Block Protect 2 (BP2) is " + "%sset\n", (status & (1 << 4)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) is " + "%sset\n", (status & (1 << 3)) ? "" : "not "); + msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) is " + "%sset\n", (status & (1 << 2)) ? "" : "not "); + /* FIXME: Pretty-print detailed sector protection status. */ + spi_prettyprint_status_register_welwip(status); + return 0; +} + +int spi_prettyprint_status_register_atmel_at26df081a(struct flashchip *flash) +{ + uint8_t status; + + status = spi_read_status_register(); + msg_cdbg("Chip status register is %02x\n", status); + + spi_prettyprint_status_register_atmel_at25_srpl(status); + msg_cdbg("Chip status register: Sequential Program Mode Status (SPM) " + "is %sset\n", (status & (1 << 6)) ? "" : "not "); + spi_prettyprint_status_register_atmel_at25_epewpp(status); + spi_prettyprint_status_register_atmel_at25_swp(status); + spi_prettyprint_status_register_welwip(status); + return 0; +} + +int spi_disable_blockprotect_at25df(struct flashchip *flash) +{ + uint8_t status; + int result; + + status = spi_read_status_register(); + /* If block protection is disabled, stop here. */ + if ((status & (3 << 2)) == 0) + return 0; + + msg_cdbg("Some block protection in effect, disabling\n"); + if (status & (1 << 7)) { + msg_cdbg("Need to disable Sector Protection Register Lock\n"); + if ((status & (1 << 4)) == 0) { + msg_cerr("WP# pin is active, disabling " + "write protection is impossible.\n"); + return 1; + } + /* All bits except bit 7 (SPRL) are readonly. */ + result = spi_write_status_register(flash, status & ~(1 << 7)); + if (result) { + msg_cerr("spi_write_status_register failed\n"); + return result; + } + + } + /* Global unprotect. Make sure to mask SPRL as well. */ + result = spi_write_status_register(flash, status & ~0xbc); + if (result) { + msg_cerr("spi_write_status_register failed\n"); + return result; + } + status = spi_read_status_register(); + if ((status & (3 << 2)) != 0) { + msg_cerr("Block protection could not be disabled!\n"); + return 1; + } + return 0; +} + +int spi_disable_blockprotect_at25df_sec(struct flashchip *flash) +{ + /* FIXME: We should check the security lockdown. */ + msg_cinfo("Ignoring security lockdown (if present)\n"); + return spi_disable_blockprotect_at25df(flash); +} + +int spi_disable_blockprotect_at25f(struct flashchip *flash) +{ + /* spi_disable_blockprotect_at25df is not really the right way to do + * this, but the side effects of said function work here as well. + */ + return spi_disable_blockprotect_at25df(flash); +} + +int spi_disable_blockprotect_at25fs010(struct flashchip *flash) +{ + uint8_t status; + int result; + + status = spi_read_status_register(); + /* If block protection is disabled, stop here. */ + if ((status & 0x6c) == 0) + return 0; + + msg_cdbg("Some block protection in effect, disabling\n"); + if (status & (1 << 7)) { + msg_cdbg("Need to disable Status Register Write Protect\n"); + /* Clear bit 7 (WPEN). */ + result = spi_write_status_register(flash, status & ~(1 << 7)); + if (result) { + msg_cerr("spi_write_status_register failed\n"); + return result; + } + } + /* Global unprotect. Make sure to mask WPEN as well. */ + result = spi_write_status_register(flash, status & ~0xec); + if (result) { + msg_cerr("spi_write_status_register failed\n"); + return result; + } + status = spi_read_status_register(); + if ((status & 0x6c) != 0) { + msg_cerr("Block protection could not be disabled!\n"); + return 1; + } + return 0; +} + +int spi_disable_blockprotect_at25fs040(struct flashchip *flash) +{ + uint8_t status; + int result; + + status = spi_read_status_register(); + /* If block protection is disabled, stop here. */ + if ((status & 0x7c) == 0) + return 0; + + msg_cdbg("Some block protection in effect, disabling\n"); + if (status & (1 << 7)) { + msg_cdbg("Need to disable Status Register Write Protect\n"); + /* Clear bit 7 (WPEN). */ + result = spi_write_status_register(flash, status & ~(1 << 7)); + if (result) { + msg_cerr("spi_write_status_register failed\n"); + return result; + } + } + /* Global unprotect. Make sure to mask WPEN as well. */ + result = spi_write_status_register(flash, status & ~0xfc); + if (result) { + msg_cerr("spi_write_status_register failed\n"); + return result; + } + status = spi_read_status_register(); + if ((status & 0x7c) != 0) { + msg_cerr("Block protection could not be disabled!\n"); + return 1; + } + return 0; +} Index: flashrom-spi_prettyprint_statusreg_a25_at25/spi25.c =================================================================== --- flashrom-spi_prettyprint_statusreg_a25_at25/spi25.c (Revision 1245) +++ flashrom-spi_prettyprint_statusreg_a25_at25/spi25.c (Arbeitskopie) @@ -29,8 +29,6 @@ #include "programmer.h" #include "spi.h" -void spi_prettyprint_status_register(struct flashchip *flash); - static int spi_rdid(unsigned char *readarr, int bytes) { const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID }; @@ -312,7 +310,7 @@ } /* Prettyprint the status register. Common definitions. */ -static void spi_prettyprint_status_register_welwip(uint8_t status) +void spi_prettyprint_status_register_welwip(uint8_t status) { msg_cdbg("Chip status register: Write Enable Latch (WEL) is " "%sset\n", (status & (1 << 1)) ? "" : "not "); @@ -321,144 +319,38 @@ } /* Prettyprint the status register. Common definitions. */ -static void spi_prettyprint_status_register_common(uint8_t status) +void spi_prettyprint_status_register_bp3210(uint8_t status, int bp) { - msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) is " - "%sset\n", (status & (1 << 5)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 4 / Block Protect 2 (BP2) is " - "%sset\n", (status & (1 << 4)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) is " - "%sset\n", (status & (1 << 3)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) is " - "%sset\n", (status & (1 << 2)) ? "" : "not "); - spi_prettyprint_status_register_welwip(status); -} - -/* Prettyprint the status register. Works for - * AMIC A25L series - */ -void spi_prettyprint_status_register_amic_a25l(uint8_t status) -{ - msg_cdbg("Chip status register: Status Register Write Disable " - "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not "); - spi_prettyprint_status_register_common(status); -} - -/* Prettyprint the status register. Common definitions. */ -static void spi_prettyprint_status_register_at25_srplepewpp(uint8_t status) -{ - msg_cdbg("Chip status register: Sector Protection Register Lock (SRPL) " - "is %sset\n", (status & (1 << 7)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 6 " - "is %sset\n", (status & (1 << 6)) ? "" : "not "); - msg_cdbg("Chip status register: Erase/Program Error (EPE) " - "is %sset\n", (status & (1 << 5)) ? "" : "not "); - msg_cdbg("Chip status register: WP# pin (WPP) " - "is %sactive\n", (status & (1 << 4)) ? "not " : ""); -} - -int spi_prettyprint_status_register_at25df(struct flashchip *flash) -{ - uint8_t status; - - status = spi_read_status_register(); - msg_cdbg("Chip status register is %02x\n", status); - - spi_prettyprint_status_register_at25_srplepewpp(status); - msg_cdbg("Chip status register: Software Protection Status (SWP): "); - switch (status & (3 << 2)) { - case 0x0 << 2: - msg_cdbg("no sectors are protected\n"); - break; - case 0x1 << 2: - msg_cdbg("some sectors are protected\n"); - /* FIXME: Read individual Sector Protection Registers. */ - break; - case 0x3 << 2: - msg_cdbg("all sectors are protected\n"); - break; - default: - msg_cdbg("reserved for future use\n"); - break; + switch (bp) { + /* Fall through. */ + case 3: + msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) " + "is %sset\n", (status & (1 << 5)) ? "" : "not "); + case 2: + msg_cdbg("Chip status register: Bit 4 / Block Protect 2 (BP2) " + "is %sset\n", (status & (1 << 4)) ? "" : "not "); + case 1: + msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) " + "is %sset\n", (status & (1 << 3)) ? "" : "not "); + case 0: + msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) " + "is %sset\n", (status & (1 << 2)) ? "" : "not "); } - spi_prettyprint_status_register_welwip(status); - return 0; } -int spi_prettyprint_status_register_at25df_sec(struct flashchip *flash) +/* Prettyprint the status register. Unnamed bits. */ +void spi_prettyprint_status_register_bit(uint8_t status, int bit) { - /* FIXME: We should check the security lockdown. */ - msg_cdbg("Ignoring security lockdown (if present)\n"); - msg_cdbg("Ignoring status register byte 2\n"); - return spi_prettyprint_status_register_at25df(flash); + msg_cdbg("Chip status register: Bit %i " + "is %sset\n", bit, (status & (1 << bit)) ? "" : "not "); } -int spi_prettyprint_status_register_at25f(struct flashchip *flash) +static void spi_prettyprint_status_register_common(uint8_t status) { - uint8_t status; - - status = spi_read_status_register(); - msg_cdbg("Chip status register is %02x\n", status); - - spi_prettyprint_status_register_at25_srplepewpp(status); - msg_cdbg("Chip status register: Bit 3 " - "is %sset\n", (status & (1 << 3)) ? "" : "not "); - msg_cdbg("Chip status register: Block Protect 0 (BP0) is " - "%sset, %s sectors are protected\n", - (status & (1 << 2)) ? "" : "not ", - (status & (1 << 2)) ? "all" : "no"); + spi_prettyprint_status_register_bp3210(status, 3); spi_prettyprint_status_register_welwip(status); - return 0; } -int spi_prettyprint_status_register_at25fs010(struct flashchip *flash) -{ - uint8_t status; - - status = spi_read_status_register(); - msg_cdbg("Chip status register is %02x\n", status); - - msg_cdbg("Chip status register: Status Register Write Protect (WPEN) " - "is %sset\n", (status & (1 << 7)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 6 / Block Protect 4 (BP4) is " - "%sset\n", (status & (1 << 6)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) is " - "%sset\n", (status & (1 << 5)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 4 is " - "%sset\n", (status & (1 << 4)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) is " - "%sset\n", (status & (1 << 3)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) is " - "%sset\n", (status & (1 << 2)) ? "" : "not "); - /* FIXME: Pretty-print detailed sector protection status. */ - spi_prettyprint_status_register_welwip(status); - return 0; -} - -int spi_prettyprint_status_register_at25fs040(struct flashchip *flash) -{ - uint8_t status; - - status = spi_read_status_register(); - msg_cdbg("Chip status register is %02x\n", status); - - msg_cdbg("Chip status register: Status Register Write Protect (WPEN) " - "is %sset\n", (status & (1 << 7)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 6 / Block Protect 4 (BP4) is " - "%sset\n", (status & (1 << 6)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 5 / Block Protect 3 (BP3) is " - "%sset\n", (status & (1 << 5)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 4 / Block Protect 2 (BP2) is " - "%sset\n", (status & (1 << 4)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 3 / Block Protect 1 (BP1) is " - "%sset\n", (status & (1 << 3)) ? "" : "not "); - msg_cdbg("Chip status register: Bit 2 / Block Protect 0 (BP0) is " - "%sset\n", (status & (1 << 2)) ? "" : "not "); - /* FIXME: Pretty-print detailed sector protection status. */ - spi_prettyprint_status_register_welwip(status); - return 0; -} - /* Prettyprint the status register. Works for * ST M25P series * MX MX25L series @@ -514,17 +406,13 @@ bpt[(status & 0x1c) >> 2]); } -void spi_prettyprint_status_register(struct flashchip *flash) +int spi_prettyprint_status_register(struct flashchip *flash) { uint8_t status; status = spi_read_status_register(); msg_cdbg("Chip status register is %02x\n", status); switch (flash->manufacture_id) { - case AMIC_ID: - if ((flash->model_id & 0xff00) == 0x2000) - spi_prettyprint_status_register_amic_a25l(status); - break; case ST_ID: if (((flash->model_id & 0xff00) == 0x2000) || ((flash->model_id & 0xff00) == 0x2500)) @@ -549,6 +437,7 @@ } break; } + return 0; } int spi_chip_erase_60(struct flashchip *flash) @@ -949,7 +838,7 @@ return 0; } -static int spi_write_status_register(struct flashchip *flash, int status) +int spi_write_status_register(struct flashchip *flash, int status) { int ret = 1; @@ -1075,128 +964,6 @@ return 0; } -int spi_disable_blockprotect_at25df(struct flashchip *flash) -{ - uint8_t status; - int result; - - status = spi_read_status_register(); - /* If block protection is disabled, stop here. */ - if ((status & (3 << 2)) == 0) - return 0; - - msg_cdbg("Some block protection in effect, disabling\n"); - if (status & (1 << 7)) { - msg_cdbg("Need to disable Sector Protection Register Lock\n"); - if ((status & (1 << 4)) == 0) { - msg_cerr("WP# pin is active, disabling " - "write protection is impossible.\n"); - return 1; - } - /* All bits except bit 7 (SPRL) are readonly. */ - result = spi_write_status_register(flash, status & ~(1 << 7)); - if (result) { - msg_cerr("spi_write_status_register failed\n"); - return result; - } - - } - /* Global unprotect. Make sure to mask SPRL as well. */ - result = spi_write_status_register(flash, status & ~0xbc); - if (result) { - msg_cerr("spi_write_status_register failed\n"); - return result; - } - status = spi_read_status_register(); - if ((status & (3 << 2)) != 0) { - msg_cerr("Block protection could not be disabled!\n"); - return 1; - } - return 0; -} - -int spi_disable_blockprotect_at25df_sec(struct flashchip *flash) -{ - /* FIXME: We should check the security lockdown. */ - msg_cinfo("Ignoring security lockdown (if present)\n"); - return spi_disable_blockprotect_at25df(flash); -} - -int spi_disable_blockprotect_at25f(struct flashchip *flash) -{ - /* spi_disable_blockprotect_at25df is not really the right way to do - * this, but the side effects of said function work here as well. - */ - return spi_disable_blockprotect_at25df(flash); -} - -int spi_disable_blockprotect_at25fs010(struct flashchip *flash) -{ - uint8_t status; - int result; - - status = spi_read_status_register(); - /* If block protection is disabled, stop here. */ - if ((status & 0x6c) == 0) - return 0; - - msg_cdbg("Some block protection in effect, disabling\n"); - if (status & (1 << 7)) { - msg_cdbg("Need to disable Status Register Write Protect\n"); - /* Clear bit 7 (WPEN). */ - result = spi_write_status_register(flash, status & ~(1 << 7)); - if (result) { - msg_cerr("spi_write_status_register failed\n"); - return result; - } - } - /* Global unprotect. Make sure to mask WPEN as well. */ - result = spi_write_status_register(flash, status & ~0xec); - if (result) { - msg_cerr("spi_write_status_register failed\n"); - return result; - } - status = spi_read_status_register(); - if ((status & 0x6c) != 0) { - msg_cerr("Block protection could not be disabled!\n"); - return 1; - } - return 0; -} -int spi_disable_blockprotect_at25fs040(struct flashchip *flash) -{ - uint8_t status; - int result; - - status = spi_read_status_register(); - /* If block protection is disabled, stop here. */ - if ((status & 0x7c) == 0) - return 0; - - msg_cdbg("Some block protection in effect, disabling\n"); - if (status & (1 << 7)) { - msg_cdbg("Need to disable Status Register Write Protect\n"); - /* Clear bit 7 (WPEN). */ - result = spi_write_status_register(flash, status & ~(1 << 7)); - if (result) { - msg_cerr("spi_write_status_register failed\n"); - return result; - } - } - /* Global unprotect. Make sure to mask WPEN as well. */ - result = spi_write_status_register(flash, status & ~0xfc); - if (result) { - msg_cerr("spi_write_status_register failed\n"); - return result; - } - status = spi_read_status_register(); - if ((status & 0x7c) != 0) { - msg_cerr("Block protection could not be disabled!\n"); - return 1; - } - return 0; -} - int spi_nbyte_read(int address, uint8_t *bytes, int len) { const unsigned char cmd[JEDEC_READ_OUTSIZE] = { Index: flashrom-spi_prettyprint_statusreg_a25_at25/flashchips.c =================================================================== --- flashrom-spi_prettyprint_statusreg_a25_at25/flashchips.c (Revision 1245) +++ flashrom-spi_prettyprint_statusreg_a25_at25/flashchips.c (Arbeitskopie) @@ -300,6 +300,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l05p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -331,6 +332,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l05p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -363,6 +365,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l05p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -395,6 +398,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l05p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -427,6 +431,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l05p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -459,6 +464,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l05p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -496,6 +502,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -528,6 +535,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -560,6 +568,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -595,6 +604,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -630,6 +640,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -660,6 +671,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -690,6 +702,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -720,6 +733,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -750,6 +764,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -780,6 +795,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -810,6 +826,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l40p, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -846,6 +863,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25l032, .unlock = NULL, /* Two status reg bytes (read with 0x35 and 0x05) */ .write = spi_chip_write_256, .read = spi_chip_read, @@ -882,6 +900,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_amic_a25lq032, .unlock = NULL, /* Two status reg bytes (read with 0x35 and 0x05) */ .write = spi_chip_write_256, .read = spi_chip_read, @@ -1499,6 +1518,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_atmel_at26df081a, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1534,6 +1554,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_at25df, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1569,6 +1590,7 @@ .block_erase = spi_block_erase_c7, } }, + .printlock = spi_prettyprint_status_register_atmel_at26df081a, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, @@ -1586,6 +1608,7 @@ .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, + .printlock = spi_prettyprint_status_register_atmel_at26df081a, .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, Index: flashrom-spi_prettyprint_statusreg_a25_at25/chipdrivers.h =================================================================== --- flashrom-spi_prettyprint_statusreg_a25_at25/chipdrivers.h (Revision 1245) +++ flashrom-spi_prettyprint_statusreg_a25_at25/chipdrivers.h (Arbeitskopie) @@ -43,23 +43,37 @@ int spi_chip_write_256(struct flashchip *flash, uint8_t *buf, int start, int len); int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); uint8_t spi_read_status_register(void); +int spi_write_status_register(struct flashchip *flash, int status); +void spi_prettyprint_status_register_bit(uint8_t status, int bit); +void spi_prettyprint_status_register_bp3210(uint8_t status, int bp); +void spi_prettyprint_status_register_welwip(uint8_t status); +int spi_prettyprint_status_register(struct flashchip *flash); +int spi_disable_blockprotect(struct flashchip *flash); +int spi_byte_program(int addr, uint8_t databyte); +int spi_nbyte_program(int addr, uint8_t *bytes, int len); +int spi_nbyte_read(int addr, uint8_t *bytes, int len); +int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); +int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); +int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len); + +/* a25.c */ +int spi_prettyprint_status_register_amic_a25l05p(struct flashchip *flash); +int spi_prettyprint_status_register_amic_a25l40p(struct flashchip *flash); +int spi_prettyprint_status_register_amic_a25l032(struct flashchip *flash); +int spi_prettyprint_status_register_amic_a25lq032(struct flashchip *flash); + +/* at25.c */ int spi_prettyprint_status_register_at25df(struct flashchip *flash); int spi_prettyprint_status_register_at25df_sec(struct flashchip *flash); int spi_prettyprint_status_register_at25f(struct flashchip *flash); int spi_prettyprint_status_register_at25fs010(struct flashchip *flash); int spi_prettyprint_status_register_at25fs040(struct flashchip *flash); -int spi_disable_blockprotect(struct flashchip *flash); +int spi_prettyprint_status_register_atmel_at26df081a(struct flashchip *flash); int spi_disable_blockprotect_at25df(struct flashchip *flash); int spi_disable_blockprotect_at25df_sec(struct flashchip *flash); int spi_disable_blockprotect_at25f(struct flashchip *flash); int spi_disable_blockprotect_at25fs010(struct flashchip *flash); int spi_disable_blockprotect_at25fs040(struct flashchip *flash); -int spi_byte_program(int addr, uint8_t databyte); -int spi_nbyte_program(int addr, uint8_t *bytes, int len); -int spi_nbyte_read(int addr, uint8_t *bytes, int len); -int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); -int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); -int spi_aai_write(struct flashchip *flash, uint8_t *buf, int start, int len); /* 82802ab.c */ uint8_t wait_82802ab(struct flashchip *flash); -- http://www.hailfinger.org/

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GSOC 2011
by Stefan Tauner May 19, 2011

May 19, 2011

hello since no one on irc even replied with "go away intel nazi!!11", i have to propose my idea here ;) i tried to get flashrom to work on my two main computers[1], but they don't work because of the EC/Intel's management engine (ME). i don't know for sure how the vendor tools do the flashing, but i presume that they talk to the ME via HECI to coordinate the process. There _was_ an attempt to get basic HECI and QST (intel quiet system technology) into the kernel to allow temperature readings etc. Intel abandoned it in 2009 [2]. my (project) idea is to try to reverse engineer some vendor tools to see how they work and try to reproduce it in flashrom to eventually support ME enabled motherboards in flashrom. i dunno how big the impact would be, but i guess this would allow even many laptops to be supported? what do you think about this idea and its feasibility? any volunteers for mentoring? :) 1: http://patchwork.coreboot.org/patch/2798/ 2: http://driverdev.linuxdriverproject.org/pipermail/devel/2009-September/0024… also i have some questions about the "official" ideas: UI: - With TUI do you mean (something like) ncurses? - the "current" code is [3]? i have not looked into it yet. - has it to use qt and/or that code (i like java *hide* and have a bit of gdk experience)? recovery stuff: guess it would be mandatory to have a working coreboot setup with real hardware for that? bitbanging support: this would also require available hardware. would i have to buy that myself? can it be borrowed from someone? these projects would probably profit from my open workbench logic analyzer... the infrastructure things sound a bit boring, but from what i saw in the source some refactoring would (also) improve the codebase somewhat. ;) so the infrastructure-related projects may be even the most valuable contribution for longterm goals. ok that was not really a question, sorry. if there are other ideas i would love to hear them (soon). thanks! 3: http://gitorious.org/flashrom/flashrom-gui/commits/master -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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