flashrom November 2011

flashrom@flashrom.org

35 participants
121 discussions

SST49LF080A - ERASE FAILED at 0x000a3d28!
by Rudolf Marek 03 Nov '11

03 Nov '11

Hi all, It worked with this chip some time ago (a year). Erasing with -E also fails but the next one will succeed. If I write back content again and do it all again I can reproduce this. It seems like a timing issue. Log attached. Changing probe_timing to 10000 is not helping. Tried with latest flashrom, older ended with SIGSEGV. Any clue? Thanks Rudolf

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Re: [flashrom] [PATCH 1/2] ichspi: remove dependency on spi_programmer from generate_opcodes and program_opcodes
by Carl-Daniel Hailfinger 03 Nov '11

03 Nov '11

Am 26.10.2011 15:35 schrieb Stefan Tauner: > This allows them to be called before programmer registration. > --- > i think it might be a good idea to get rid of the whole > switch(spi_programmer->type) > pattern and create a file-scope static ich_generation variable instead > of using the type member and the ich_generation parameters everywhere. Absolutely agreed. The only possible generic problem with that approach would be the registration of multiple ICH-style SPI programmers, but unless we see boards with two active ICH-style southbridges I think we can assume the static variable handles it well. (Note that boards with multiple MCP55 southbridges exist, but only one southbridge has an attached flash chip.) There might be an issue for those who want to use flashrom as a standalone tool (e.g. on top of libpayload) where heap allocations for static variables are unwanted, but that's a huge can of worms and I'd rather ignore that issue until either static variables work well in that environment or until someone hacks a way around static variables being a problem there. > the type member is enough most of the time to derive the wanted > information, but > - not always (e.g. ich_set_bbar) > - only available after registration, which we want to delay till the end > of init. > - we really want to distinguish between chipset version-grained > attributes which are not reflected by the registered programmer. Indeed. So if you could rework the patch to use your static variable suggestion, it would reduce patch size and make the code more readable. Regards, Carl-Daniel > Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> > --- > ichspi.c | 44 +++++++++++++++++++++++++++----------------- > 1 files changed, 27 insertions(+), 17 deletions(-) > > diff --git a/ichspi.c b/ichspi.c > index afa420b..bc03554 100644 > --- a/ichspi.c > +++ b/ichspi.c > @@ -225,8 +225,8 @@ static uint16_t REGREAD8(int X) > /* Common SPI functions */ > static int find_opcode(OPCODES *op, uint8_t opcode); > static int find_preop(OPCODES *op, uint8_t preop); > -static int generate_opcodes(OPCODES * op); > -static int program_opcodes(OPCODES *op, int enable_undo); > +static int generate_opcodes(int ich_generation, OPCODES * op); > +static int program_opcodes(int ich_generation, OPCODES *op, int enable_undo); > static int run_opcode(OPCODE op, uint32_t offset, > uint8_t datalength, uint8_t * data); > > @@ -410,7 +410,18 @@ static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, un > int oppos=2; // use original JEDEC_BE_D8 offset > curopcodes->opcode[oppos].opcode = opcode; > curopcodes->opcode[oppos].spi_type = spi_type; > - program_opcodes(curopcodes, 0); > + switch (spi_programmer->type) { > + case SPI_CONTROLLER_ICH7: > + case SPI_CONTROLLER_VIA: > + program_opcodes(7, curopcodes, 0); > + break; > + case SPI_CONTROLLER_ICH9: > + program_opcodes(9, curopcodes, 0); > + break; > + default: > + msg_perr("%s: unsupported chipset\n", __func__); > + return -1; > + } > oppos = find_opcode(curopcodes, opcode); > msg_pdbg ("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos); > return oppos; > @@ -443,7 +454,7 @@ static int find_preop(OPCODES *op, uint8_t preop) > } > > /* Create a struct OPCODES based on what we find in the locked down chipset. */ > -static int generate_opcodes(OPCODES * op) > +static int generate_opcodes(int ich_generation, OPCODES * op) > { > int a; > uint16_t preop, optype; > @@ -498,7 +509,7 @@ static int generate_opcodes(OPCODES * op) > return 0; > } > > -static int program_opcodes(OPCODES *op, int enable_undo) > +static int program_opcodes(int ich_generation, OPCODES *op, int enable_undo) > { > uint8_t a; > uint16_t preop, optype; > @@ -529,9 +540,8 @@ static int program_opcodes(OPCODES *op, int enable_undo) > } > > msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); > - switch (spi_programmer->type) { > - case SPI_CONTROLLER_ICH7: > - case SPI_CONTROLLER_VIA: > + switch (ich_generation) { > + case 7: > /* Register undo only for enable_undo=1, i.e. first call. */ > if (enable_undo) { > rmmio_valw(ich_spibar + ICH7_REG_PREOP); > @@ -544,7 +554,10 @@ static int program_opcodes(OPCODES *op, int enable_undo) > mmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU); > mmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4); > break; > - case SPI_CONTROLLER_ICH9: > + case 8: > + case 9: > + case 10: > + default: /* Future version might behave the same */ > /* Register undo only for enable_undo=1, i.e. first call. */ > if (enable_undo) { > rmmio_valw(ich_spibar + ICH9_REG_PREOP); > @@ -557,9 +570,6 @@ static int program_opcodes(OPCODES *op, int enable_undo) > mmio_writel(opmenu[0], ich_spibar + ICH9_REG_OPMENU); > mmio_writel(opmenu[1], ich_spibar + ICH9_REG_OPMENU + 4); > break; > - default: > - msg_perr("%s: unsupported chipset\n", __func__); > - return -1; > } > > return 0; > @@ -652,7 +662,7 @@ static void ich_fill_data(const uint8_t *data, int len, int reg0_off) > * > * It should be called before ICH sends any spi command. > */ > -static int ich_init_opcodes(void) > +static int ich_init_opcodes(int ich_generation) > { > int rc = 0; > OPCODES *curopcodes_done; > @@ -663,11 +673,11 @@ static int ich_init_opcodes(void) > if (ichspi_lock) { > msg_pdbg("Reading OPCODES... "); > curopcodes_done = &O_EXISTING; > - rc = generate_opcodes(curopcodes_done); > + rc = generate_opcodes(ich_generation, curopcodes_done); > } else { > msg_pdbg("Programming OPCODES... "); > curopcodes_done = &O_ST_M25P; > - rc = program_opcodes(curopcodes_done, 1); > + rc = program_opcodes(ich_generation, curopcodes_done, 1); > } > > if (rc) { > @@ -1343,6 +1353,7 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > > /* Assign Virtual Address */ > ich_spibar = rcrb + spibar_offset; > + ich_init_opcodes(ich_generation); > > switch (ich_generation) { > case 7: > @@ -1383,7 +1394,6 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb, > } > ich_set_bbar(ich_generation, 0); > register_spi_programmer(&spi_programmer_ich7); > - ich_init_opcodes(); > break; > case 8: > case 9: > @@ -1557,7 +1567,7 @@ int via_init_spi(struct pci_dev *dev) > } > > ich_set_bbar(7, 0); > - ich_init_opcodes(); > + ich_init_opcodes(7); > > return 0; > } -- http://www.hailfinger.org/

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Re: [flashrom] Successful test on Asus P5K-VM
by Stefan Tauner 02 Nov '11

02 Nov '11

On Mon, 31 Oct 2011 20:11:54 +0100 Grischa Ebinger <grischa.ebinger(a)gmail.com> wrote: > Hello, > > I was able to successfully reflash the BIOS of a P5K-VM motherboard > with flashrom-0.9.4. It recognized 2 different flash chips (AT25DF081A > and AT26DF081A) at the same address. I selected the first of the two > chipsets. > > I wasn't sure if flashrom did support my hardware. According to your > wiki it wasn't tested before. Luckily, it did its job without a > hiccup. Thank you a lot for providing such a useful tool, I hope I can > help you by sending you this new data. Hello Grischa, Thanks for your report! I have marked the mainboard as supported and will commit that later together with other small changes. > […] > Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 > 0x1f, id2 0x4501 > Chip status register is 00 > Found Atmel flash chip "AT25DF081A" (1024 kB, SPI) at physical address > 0xfff00000. > Ignoring security lockdown (if present) > Ignoring status register byte 2 > Chip status register is 00 > Chip status register: Sector Protection Register Lock (SRPL) is not set > Chip status register: Bit 6 is not set > Chip status register: Erase/Program Error (EPE) is not set > Chip status register: WP# pin (WPP) is asserted > Chip status register: Software Protection Status (SWP): no sectors are protected > Chip status register: Write Enable Latch (WEL) is not set > Chip status register: Write In Progress (WIP/BUSY) is not set > Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 > 0x1f, id2 0x4501 > Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 > 0x1f, id2 0x4501 > Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 > 0x1f, id2 0x4501 > Probing for Atmel AT25DF641, 8192 kB: probe_spi_rdid_generic: id1 > 0x1f, id2 0x4501 > Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 > 0x1f, id2 0x4501 > Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0x1f, id2 0x4501 > Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0x1f, > id2 0x4501 > Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0x1f, > id2 0x4501 > Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0x1f, > id2 0x4501 > Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 > 0x1f, id2 0x4501 > Chip status register is 00 > Found Atmel flash chip "AT26DF081A" (1024 kB, SPI) at physical address > 0xfff00000. > Chip status register is 00 > Chip status register: Sector Protection Register Lock (SRPL) is not set > Chip status register: Sequential Program Mode Status (SPM) is not set > Chip status register: Erase/Program Error (EPE) is not set > Chip status register: WP# pin (WPP) is asserted > Chip status register: Software Protection Status (SWP): no sectors are protected > Chip status register: Write Enable Latch (WEL) is not set > Chip status register: Write In Progress (WIP/BUSY) is not set > […] > Multiple flash chips were detected: "AT25DF081A", "AT26DF081A" the chips are not found "at the same address", but report the same ID when queried. atmel did no give them distinct IDs so we can not distinguish them on our own, hence your help was required*, sorry. * i have not looked at the respective datesheets. it is possible that the other definition would work equally. > […] > > $ lspci -nnvvxxx > […] not needed in this case. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] Flashrom fails to write - Sun Ultra 40 M2
by Stefan Tauner 02 Nov '11

02 Nov '11

On Tue, 25 Oct 2011 11:29:45 -0700 Nick <nochristrequired(a)gmail.com> wrote: > DMI string system-manufacturer: "Sun Microsystems" > DMI string system-product-name: "Sun Ultra 40 M2 Workstation" > DMI string system-version: "11" > DMI string baseboard-manufacturer: "Sun Microsystems" > DMI string baseboard-product-name: "Sun Ultra 40 M2 Workstation" > DMI string baseboard-version: "50" > > nForce Pro 3600 / MCP55, SMSC SuperIO > > Verbose output when flashing coreboot - > http://paste.flashrom.org/view.php?id=880 > Verbose output when flashing original Sun BIOS image - > http://paste.flashrom.org/view.php?id=881 > > lspci -nnvvvxxx output - http://paste.flashrom.org/view.php?id=883 > superiotool -deV output - http://paste.flashrom.org/view.php?id=884 > > Original Sun Ultra 40 M2 BIOS image - > http://paste.flashrom.org/view.php?id=882 hey there, as you know we have a patch to get this working. i have committed it to our repository moments ago so that board will be supported from now (r1458) on. gl with coreboot ;) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH] Add board enable for Sun Ultra 40 M2
by Joshua Roys 02 Nov '11

02 Nov '11

On 11/02/2011 10:15 AM, Stefan Tauner wrote: > Success report: > http://paste.flashrom.org/view.php?id=889 > Signed-off-by: Joshua Roys <roysjosh(a)gmail.com> Stefan, feel free to sign-off also, if you want. > Acked-by: Stefan Tauner<stefan.tauner(a)student.tuwien.ac.at> > --- > board_enable.c | 33 +++++++++++++++++++++++++++++++++ > print.c | 1 + > 2 files changed, 34 insertions(+), 0 deletions(-) > > diff --git a/board_enable.c b/board_enable.c > index 1874459..fe2f021 100644 > --- a/board_enable.c > +++ b/board_enable.c > @@ -1051,6 +1051,38 @@ static int nvidia_mcp_gpio3b_raise(void) > > /* > * Suited for: > + * - Sun Ultra 40 M2: Dual Socket F (1207) + MCP55 > + */ > +static int board_sun_ultra_40_m2(void) > +{ > + int ret; > + uint8_t reg; > + uint16_t base; > + struct pci_dev *dev; > + > + ret = nvidia_mcp_gpio4_lower(); > + if (ret) > + return ret; > + > + dev = pci_dev_find(0x10de, 0x0364); /* NVIDIA MCP55 LPC bridge */ > + if (!dev) { > + msg_perr("\nERROR: NVIDIA MCP55 LPC bridge not found.\n"); > + return -1; > + } > + > + base = pci_read_word(dev, 0xb4); /* some IO BAR? */ > + if (!base) > + return -1; > + > + reg = INB(base + 0x4b); > + reg |= 0x10; > + OUTB(reg, base + 0x4b); > + > + return 0; > +} > + > +/* > + * Suited for: > * - Artec Group DBE61 and DBE62 > */ > static int board_artecgroup_dbe6x(void) > @@ -2109,6 +2141,7 @@ const struct board_match board_matches[] = { > {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, P3, "Shuttle", "AK38N", 256, OK, NULL}, > {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, P3, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, > {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, P3, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower}, > + {0x10de, 0x0364, 0x108e, 0x6676, 0x10de, 0x0369, 0x108e, 0x6676, "^Sun Ultra 40 M2", NULL, NULL, P3, "Sun", "Ultra 40 M2", 0, OK, board_sun_ultra_40_m2}, > {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, P3, "Tekram", "P6Pro-A5", 256, OK, NULL}, > {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, P3, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, > {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, P3, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e}, > diff --git a/print.c b/print.c > index 05eee9f..91288ee 100644 > --- a/print.c > +++ b/print.c > @@ -846,6 +846,7 @@ const struct board_info boards_known[] = { > B("Sun", "Fire x4200", 0, "http://www.sun.com/servers/entry/x4200/", "No public report found. May work now."), > B("Sun", "Fire x4540", 0, "http://www.sun.com/servers/x64/x4540/", "No public report found. May work now."), > B("Sun", "Fire x4600", 0, "http://www.sun.com/servers/x64/x4600/", "No public report found. May work now."), > + B("Sun", "Ultra 40 M2", 1, NULL, NULL), > B("Supermicro", "H8QC8", 1, "http://www.supermicro.com/Aplus/motherboard/Opteron/nforce/H8QC8.cfm", NULL), > B("Supermicro", "X5DP8-G2", 1, "http://www.supermicro.com/products/motherboard/Xeon/E7501/X5DP8-G2.cfm", NULL), > B("Supermicro", "X7DBT-INF", 1, "http://www.supermicro.com/products/motherboard/Xeon1333/5000P/X7DBT-INF.cfm", NULL),

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[commit] r1458 - trunk
by repository service 02 Nov '11

02 Nov '11

Author: stefanct Date: Wed Nov 2 15:31:18 2011 New Revision: 1458 URL: http://flashrom.org/trac/flashrom/changeset/1458 Log: Add board enable for Sun Ultra 40 M2 Failure report with logs: http://www.flashrom.org/pipermail/flashrom/2011-October/008158.html Success report: http://paste.flashrom.org/view.php?id=889 Signed-off-by: Joshua Roys <roysjosh(a)gmail.com> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/board_enable.c trunk/print.c Modified: trunk/board_enable.c ============================================================================== --- trunk/board_enable.c Sun Oct 23 00:01:09 2011 (r1457) +++ trunk/board_enable.c Wed Nov 2 15:31:18 2011 (r1458) @@ -1051,6 +1051,38 @@ /* * Suited for: + * - Sun Ultra 40 M2: Dual Socket F (1207) + MCP55 + */ +static int board_sun_ultra_40_m2(void) +{ + int ret; + uint8_t reg; + uint16_t base; + struct pci_dev *dev; + + ret = nvidia_mcp_gpio4_lower(); + if (ret) + return ret; + + dev = pci_dev_find(0x10de, 0x0364); /* NVIDIA MCP55 LPC bridge */ + if (!dev) { + msg_perr("\nERROR: NVIDIA MCP55 LPC bridge not found.\n"); + return -1; + } + + base = pci_read_word(dev, 0xb4); /* some IO BAR? */ + if (!base) + return -1; + + reg = INB(base + 0x4b); + reg |= 0x10; + OUTB(reg, base + 0x4b); + + return 0; +} + +/* + * Suited for: * - Artec Group DBE61 and DBE62 */ static int board_artecgroup_dbe6x(void) @@ -2109,6 +2141,7 @@ {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, P3, "Shuttle", "AK38N", 256, OK, NULL}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, P3, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, P3, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower}, + {0x10de, 0x0364, 0x108e, 0x6676, 0x10de, 0x0369, 0x108e, 0x6676, "^Sun Ultra 40 M2", NULL, NULL, P3, "Sun", "Ultra 40 M2", 0, OK, board_sun_ultra_40_m2}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, P3, "Tekram", "P6Pro-A5", 256, OK, NULL}, {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, P3, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, P3, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e}, Modified: trunk/print.c ============================================================================== --- trunk/print.c Sun Oct 23 00:01:09 2011 (r1457) +++ trunk/print.c Wed Nov 2 15:31:18 2011 (r1458) @@ -846,6 +846,7 @@ B("Sun", "Fire x4200", 0, "http://www.sun.com/servers/entry/x4200/", "No public report found. May work now."), B("Sun", "Fire x4540", 0, "http://www.sun.com/servers/x64/x4540/", "No public report found. May work now."), B("Sun", "Fire x4600", 0, "http://www.sun.com/servers/x64/x4600/", "No public report found. May work now."), + B("Sun", "Ultra 40 M2", 1, "http://download.oracle.com/docs/cd/E19127-01/ultra40.ws/820-0123-13/intro.h…", NULL), B("Supermicro", "H8QC8", 1, "http://www.supermicro.com/Aplus/motherboard/Opteron/nforce/H8QC8.cfm", NULL), B("Supermicro", "X5DP8-G2", 1, "http://www.supermicro.com/products/motherboard/Xeon/E7501/X5DP8-G2.cfm", NULL), B("Supermicro", "X7DBT-INF", 1, "http://www.supermicro.com/products/motherboard/Xeon1333/5000P/X7DBT-INF.cfm", NULL),

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[PATCH] Add board enable for Sun Ultra 40 M2
by Stefan Tauner 02 Nov '11

02 Nov '11

Success report: http://paste.flashrom.org/view.php?id=889 (mostly) written by Joshua Roy (please add your signed-off tag) and Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> --- board_enable.c | 33 +++++++++++++++++++++++++++++++++ print.c | 1 + 2 files changed, 34 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index 1874459..fe2f021 100644 --- a/board_enable.c +++ b/board_enable.c @@ -1051,6 +1051,38 @@ static int nvidia_mcp_gpio3b_raise(void) /* * Suited for: + * - Sun Ultra 40 M2: Dual Socket F (1207) + MCP55 + */ +static int board_sun_ultra_40_m2(void) +{ + int ret; + uint8_t reg; + uint16_t base; + struct pci_dev *dev; + + ret = nvidia_mcp_gpio4_lower(); + if (ret) + return ret; + + dev = pci_dev_find(0x10de, 0x0364); /* NVIDIA MCP55 LPC bridge */ + if (!dev) { + msg_perr("\nERROR: NVIDIA MCP55 LPC bridge not found.\n"); + return -1; + } + + base = pci_read_word(dev, 0xb4); /* some IO BAR? */ + if (!base) + return -1; + + reg = INB(base + 0x4b); + reg |= 0x10; + OUTB(reg, base + 0x4b); + + return 0; +} + +/* + * Suited for: * - Artec Group DBE61 and DBE62 */ static int board_artecgroup_dbe6x(void) @@ -2109,6 +2141,7 @@ const struct board_match board_matches[] = { {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, P3, "Shuttle", "AK38N", 256, OK, NULL}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, P3, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, P3, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower}, + {0x10de, 0x0364, 0x108e, 0x6676, 0x10de, 0x0369, 0x108e, 0x6676, "^Sun Ultra 40 M2", NULL, NULL, P3, "Sun", "Ultra 40 M2", 0, OK, board_sun_ultra_40_m2}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, P3, "Tekram", "P6Pro-A5", 256, OK, NULL}, {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, P3, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, P3, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e}, diff --git a/print.c b/print.c index 05eee9f..91288ee 100644 --- a/print.c +++ b/print.c @@ -846,6 +846,7 @@ const struct board_info boards_known[] = { B("Sun", "Fire x4200", 0, "http://www.sun.com/servers/entry/x4200/", "No public report found. May work now."), B("Sun", "Fire x4540", 0, "http://www.sun.com/servers/x64/x4540/", "No public report found. May work now."), B("Sun", "Fire x4600", 0, "http://www.sun.com/servers/x64/x4600/", "No public report found. May work now."), + B("Sun", "Ultra 40 M2", 1, NULL, NULL), B("Supermicro", "H8QC8", 1, "http://www.supermicro.com/Aplus/motherboard/Opteron/nforce/H8QC8.cfm", NULL), B("Supermicro", "X5DP8-G2", 1, "http://www.supermicro.com/products/motherboard/Xeon/E7501/X5DP8-G2.cfm", NULL), B("Supermicro", "X7DBT-INF", 1, "http://www.supermicro.com/products/motherboard/Xeon1333/5000P/X7DBT-INF.cfm", NULL), -- 1.7.1

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Re: [flashrom] Programming an A25L40 EEPROM
by Idwer Vollering 02 Nov '11

02 Nov '11

2011/10/27 Arup Basak <arup(a)circuitsdiy.com>: > I have the 512KB bios file, and was trying to program it with flashrom and > buspirate. > Looks like one version of flashrom says "missing libftdi.dll" while another > version says programmer buspirate_spi not supported. Can you find out which version/build showed those messages? > Can you give me link of any latest version. I have tried to copy the > libftdi.dll into the flashrom directory, also tried 'regsrv32 libftdi.dll' > in a command-box (where regsrv32 looks to be absent in Windows 7) This 7z file has (should have) the required dependencies: http://ra.openbios.org/~idwer/flashrom/flashrom_v0.9.4-r1457_mingw_win32_li… If that does not work, install libusb-win32: http://www.libusb.org/wiki/libusb-win32 > > One more thing, when I hooked up the SPI chip to buspirate, if I use > terminal mode of buspirate and set correct mode, then if I try to read some > block using CS enables, I get 0x00 and if I keep CS disabled I get 0xFF. > I've tried to write anything with both CS enabled and disabled. But values > are read as above. > Maybe I've settled up wrong mode while trying to access EEPROM from > buspirate terminal mode. . I've worked with mode 5 spi, 125khz, Clock > polarity:Idle low , Output clock edge:Active to idle, Input sample > phase:middle, Output mode: Normal (H=3.3V, L=GND), W(power supplies on). > I didn't need to do so because for flashing my BIOS chip, I am trying to use > flashrom. > This is the fresh chip I bought for recovery. > http://in.rsdelivers.com/product/amic-technology/a25l040m-f/spi-flash-4mb-s… > Note: The BIOS chips is of my tablet, and not PC, so no problem if it takes > few days to resolve issues and program it. It isn't much serious case when > someone corrupts motherboard's BIOS. I know flashrom's support is free and > takes few hours to get reply. It's not an issue in my case. > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom >

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Re: [flashrom] Flashrom report
by Stefan Tauner 02 Nov '11

02 Nov '11

On Thu, 27 Oct 2011 11:27:57 +0200 Piotr Czepek <piotr.czepek(a)gmail.com> wrote: > Found chipset "VIA VT8601/VT8601A" with PCI ID 1106:0601. > This chipset is marked as untested. If you are using an up-to-date version > of flashrom please email a report to flashrom(a)flashrom.org including a > verbose (-V) log. Thank you! > Enabling flash write... OK - searching further chips. > Found chipset "VIA VT8601T" with PCI ID 1106:8601. > This chipset is marked as untested. If you are using an up-to-date version > of flashrom please email a report to flashrom(a)flashrom.org including a > verbose (-V) log. Thank you! > Enabling flash write... OK - searching further chips. > Found chipset "VIA VT8231" with PCI ID 1106:8231. > This chipset is marked as untested. If you are using an up-to-date version > of flashrom please email a report to flashrom(a)flashrom.org including a > verbose (-V) log. Thank you! can someone please shed some light onto this VIA stuff? i see how this is done in source, but not why. just because we need to write one register in the northbridge(s) to disable "byte merging"? should i just mark all of them as tested? or should i leave the northbridges marked as untested because we did not enter the "if (byte merge enabled)" branch? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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(no subject)
by yarpr＠pochta.ru 02 Nov '11

02 Nov '11

 _ Only here you can find ha.ppiness in personal r_elationships 

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flashrom November 2011