flashrom June 2010

flashrom@flashrom.org

74 participants
219 discussions

[commit] r1056 - trunk
by repository service 21 Jun '10

21 Jun '10

Author: hailfinger Date: Mon Jun 21 18:12:22 2010 New Revision: 1056 URL: http://flashrom.org/trac/coreboot/changeset/1056 Log: Add support for Hyundai HY29F002 and HY29F002B. Signed-off-by: David Borg <borg.db(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Sun Jun 20 13:04:26 2010 (r1055) +++ trunk/flashchips.c Mon Jun 21 18:12:22 2010 (r1056) @@ -2363,6 +2363,68 @@ }, { + .vendor = "Hyundai", + .name = "HY29F002T", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = HYUNDAI_ID, + .model_id = HY_29F002T, + .total_size = 256, + .page_size = 256 * 1024, + .feature_bits = FEATURE_EITHER_RESET, /* Some revisions may need FEATURE_ADDR_2AA */ + .tested = TEST_OK_PREW, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ + .block_erasers = + { + { + .eraseblocks = { + {64 * 1024, 3}, + {32 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { + .vendor = "Hyundai", + .name = "HY29F002B", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = HYUNDAI_ID, + .model_id = HY_29F002B, + .total_size = 256, + .page_size = 256 * 1024, + .feature_bits = FEATURE_EITHER_RESET, /* Some revisions may need FEATURE_ADDR_2AA */ + .tested = TEST_UNTESTED, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ + .block_erasers = + { + { + .eraseblocks = { + {16 * 1024, 1}, + {8 * 1024, 2}, + {32 * 1024, 1}, + {64 * 1024, 3}, + }, + .block_erase = erase_sector_jedec, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + }, + + { .vendor = "Intel", .name = "28F001BX-B", .bustype = CHIP_BUSTYPE_PARALLEL, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Sun Jun 20 13:04:26 2010 (r1055) +++ trunk/flashchips.h Mon Jun 21 18:12:22 2010 (r1056) @@ -242,7 +242,8 @@ #define HY_29LV800B 0x5B #define HY_29F040A 0xA4 #define HY_29F400B 0xAB /* Same as HY_29F400AB */ -#define HY_29F002 0xB0 +#define HY_29F002B 0x34 +#define HY_29F002T 0xB0 #define HY_29LV400T 0xB9 #define HY_29LV400B 0xBA #define HY_29F080 0xD5

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probe for SST20EE010 fails
by Guenter 21 Jun '10

21 Jun '10

Hi, I've a chip which is from SST and labeled as PH29EE010 150-3CF. flashrom doesnt detect this chip although it should as -L stats: flashrom -L | grep 29EE010 SST SST29EE010 P R W 128 Parallel if I check for the chip it still fails and reads flash content: flashrom -V -c SST29EE010 flashrom v0.9.2-r1039 on Linux 2.6.27-3 (i586), built with libpci 2.2.4-pre4, GCC 4.1.2 20061115 (prerelease) (Debian 4.1.1-21), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 9 usecs, 200M loops per second, 10 myus = 17 us, 100 myus = 231 us, 1000 myus = 1042 us, 10000 myus = 10133 us, 36 myus = 45 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System Manufacturer" DMI string system-product-name: "System Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "P5A-B" DMI string baseboard-version: "REV 1.XX" DMI string chassis-type: "Unknown" Found chipset "ALi M1533", enabling flash write... chipset PCI ID is 10b9:1533, OK. This chipset supports the following protocols: Non-SPI. Probing for SST SST29EE010, 128 KB: probe_jedec_common: id1 0x25, id2 0xfb, id1 is normal flash content, id2 is normal flash content No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. but if I now probe for Winbond W29C011 then flashrom of course fails but shows the right flash ID: flashrom -V -c W29EE011 flashrom v0.9.2-r1039 on Linux 2.6.27-3 (i586), built with libpci 2.2.4-pre4, GCC 4.1.2 20061115 (prerelease) (Debian 4.1.1-21), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 8 usecs, 29M loops per second, delay more than 10% too short (got 24% of expected delay), recalculating... 32M loops per second, delay more than 10% too short (got 25% of expected delay), recalculating... 34M loops per second, delay more than 10% too short (got 27% of expected delay), recalculating... 33M loops per second, delay more than 10% too short (got 25% of expected delay), recalculating... 32M loops per second, delay loop is unreliable, trying to continue 10 myus = 11 us, 100 myus = 24 us, 1000 myus = 285 us, 10000 myus = 1605 us, 32 myus = 14 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "System Manufacturer" DMI string system-product-name: "System Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "P5A-B" DMI string baseboard-version: "REV 1.XX" DMI string chassis-type: "Unknown" Found chipset "ALi M1533", enabling flash write... chipset PCI ID is 10b9:1533, OK. This chipset supports the following protocols: Non-SPI. Probing for Winbond W29EE011, 128 KB: probe_w29ee011: id1 0xbf, id2 0x07 No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. so what is obvious is the huge difference with the calibrating loop, and then that the probe for W29EE011 gives "id1 0xbf, id2 0x07" which is exactly what the datasheet from SST outlines for the SST29EE010 ... I really wonder what goes on there sine - as -L shows - this chip is marked as "P R W" ... Gün.

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flashrom -V
by Jim Lunsford 20 Jun '10

20 Jun '10

my first flashrom -V is attached as document jim lunsford do you want others?

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[PATCH] Fill in buses_supported for remaining Intel chipsets
by Carl-Daniel Hailfinger 20 Jun '10

20 Jun '10

Fill in buses_supported for remaining Intel chipsets (ICH0-ICH5, Poulsbo). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-ich_bustype/chipset_enable.c =================================================================== --- flashrom-ich_bustype/chipset_enable.c (revision 1033) +++ flashrom-ich_bustype/chipset_enable.c (working copy) @@ -286,6 +286,7 @@ * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and * FB_DEC_EN2. */ + buses_supported = CHIP_BUSTYPE_FWH; return enable_flash_ich(dev, name, 0x4e); } @@ -399,6 +400,7 @@ if (new != old) pci_write_byte(dev, 0xd9, new); + buses_supported = CHIP_BUSTYPE_FWH; return 0; } -- http://www.hailfinger.org/

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[commit] r1055 - trunk
by repository service 20 Jun '10

20 Jun '10

Author: hailfinger Date: Sun Jun 20 13:04:26 2010 New Revision: 1055 URL: http://flashrom.org/trac/coreboot/changeset/1055 Log: Fill in buses_supported for remaining Intel chipsets (ICH0-ICH5, Poulsbo). Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/chipset_enable.c Modified: trunk/chipset_enable.c ============================================================================== --- trunk/chipset_enable.c Sun Jun 20 13:02:33 2010 (r1054) +++ trunk/chipset_enable.c Sun Jun 20 13:04:26 2010 (r1055) @@ -288,6 +288,7 @@ * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and * FB_DEC_EN2. */ + buses_supported = CHIP_BUSTYPE_FWH; return enable_flash_ich(dev, name, 0x4e); } @@ -401,6 +402,7 @@ if (new != old) pci_write_byte(dev, 0xd9, new); + buses_supported = CHIP_BUSTYPE_FWH; return 0; }

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[PATCH] Kill fake SPI D8 chip erase
by Carl-Daniel Hailfinger 20 Jun '10

20 Jun '10

The SPI opcode 0xd8 is not a chip erase opcode on any chip out there. Besides that, the function as implemented just walks the chip and ignores sector sizes. Sector erase with SPI opcode 0xd8 is of course still supported. Kill a declaration for a nonexisting function while we're at it. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-kill_fake_spi_chip_erase_d8/spi25.c =================================================================== --- flashrom-kill_fake_spi_chip_erase_d8/spi25.c (Revision 1028) +++ flashrom-kill_fake_spi_chip_erase_d8/spi25.c (Arbeitskopie) @@ -652,29 +652,6 @@ return 0; } -int spi_chip_erase_d8(struct flashchip *flash) -{ - int i, rc = 0; - int total_size = flash->total_size * 1024; - int erase_size = 64 * 1024; - - spi_disable_blockprotect(); - - msg_cinfo("Erasing chip: \n"); - - for (i = 0; i < total_size / erase_size; i++) { - rc = spi_block_erase_d8(flash, i * erase_size, erase_size); - if (rc) { - msg_cerr("Error erasing block at 0x%x\n", i); - break; - } - } - - msg_cinfo("\n"); - - return rc; -} - /* Sector size is usually 4k, though Macronix eliteflash has 64k */ int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen) { Index: flashrom-kill_fake_spi_chip_erase_d8/chipdrivers.h =================================================================== --- flashrom-kill_fake_spi_chip_erase_d8/chipdrivers.h (Revision 1028) +++ flashrom-kill_fake_spi_chip_erase_d8/chipdrivers.h (Arbeitskopie) @@ -35,8 +35,6 @@ int spi_write_disable(void); int spi_chip_erase_60(struct flashchip *flash); int spi_chip_erase_c7(struct flashchip *flash); -int spi_chip_erase_60_c7(struct flashchip *flash); -int spi_chip_erase_d8(struct flashchip *flash); int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d7(struct flashchip *flash, unsigned int addr, unsigned int blocklen); -- http://www.hailfinger.org/

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[commit] r1054 - trunk
by repository service 20 Jun '10

20 Jun '10

Author: hailfinger Date: Sun Jun 20 13:02:33 2010 New Revision: 1054 URL: http://flashrom.org/trac/coreboot/changeset/1054 Log: The SPI opcode 0xd8 is not a chip erase opcode on any chip out there. Besides that, the function as implemented just walks the chip and ignores sector sizes. Sector erase with SPI opcode 0xd8 is of course still supported. Kill a declaration for a nonexisting function while we're at it. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/chipdrivers.h trunk/spi25.c Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Sun Jun 20 12:58:32 2010 (r1053) +++ trunk/chipdrivers.h Sun Jun 20 13:02:33 2010 (r1054) @@ -35,8 +35,6 @@ int spi_write_disable(void); int spi_chip_erase_60(struct flashchip *flash); int spi_chip_erase_c7(struct flashchip *flash); -int spi_chip_erase_60_c7(struct flashchip *flash); -int spi_chip_erase_d8(struct flashchip *flash); int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_52(struct flashchip *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_d7(struct flashchip *flash, unsigned int addr, unsigned int blocklen); Modified: trunk/spi25.c ============================================================================== --- trunk/spi25.c Sun Jun 20 12:58:32 2010 (r1053) +++ trunk/spi25.c Sun Jun 20 13:02:33 2010 (r1054) @@ -646,29 +646,6 @@ return 0; } -int spi_chip_erase_d8(struct flashchip *flash) -{ - int i, rc = 0; - int total_size = flash->total_size * 1024; - int erase_size = 64 * 1024; - - spi_disable_blockprotect(); - - msg_cinfo("Erasing chip: \n"); - - for (i = 0; i < total_size / erase_size; i++) { - rc = spi_block_erase_d8(flash, i * erase_size, erase_size); - if (rc) { - msg_cerr("Error erasing block at 0x%x\n", i); - break; - } - } - - msg_cinfo("\n"); - - return rc; -} - /* Sector size is usually 4k, though Macronix eliteflash has 64k */ int spi_block_erase_20(struct flashchip *flash, unsigned int addr, unsigned int blocklen) {

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[PATCH] Add SPI chip read support to dummy flasher
by Carl-Daniel Hailfinger 20 Jun '10

20 Jun '10

Add SPI chip read support to the dummy flasher. This allows using the dummy flasher for SPI read debugging. Tested, works. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-dummy_spi_chip_read/flash.h =================================================================== --- flashrom-dummy_spi_chip_read/flash.h (Revision 1049) +++ flashrom-dummy_spi_chip_read/flash.h (Arbeitskopie) @@ -454,6 +454,7 @@ void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); +int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); #endif /* nic3com.c */ Index: flashrom-dummy_spi_chip_read/spi.c =================================================================== --- flashrom-dummy_spi_chip_read/spi.c (Revision 1049) +++ flashrom-dummy_spi_chip_read/spi.c (Arbeitskopie) @@ -99,7 +99,7 @@ { /* SPI_CONTROLLER_DUMMY */ .command = dummy_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = NULL, + .read = dummy_spi_read, .write_256 = NULL, }, #endif Index: flashrom-dummy_spi_chip_read/dummyflasher.c =================================================================== --- flashrom-dummy_spi_chip_read/dummyflasher.c (Revision 1049) +++ flashrom-dummy_spi_chip_read/dummyflasher.c (Arbeitskopie) @@ -23,6 +23,7 @@ #include <ctype.h> #include <sys/types.h> #include "flash.h" +#include "chipdrivers.h" int dummy_init(void) { @@ -157,3 +158,10 @@ msg_pspew("\n"); return 0; } + +int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + /* Maximum read length is unlimited, use 64kB. */ + return spi_read_chunked(flash, buf, start, len, 64 * 1024); +} + -- http://www.hailfinger.org/

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[commit] r1053 - trunk
by repository service 20 Jun '10

20 Jun '10

Author: hailfinger Date: Sun Jun 20 12:58:32 2010 New Revision: 1053 URL: http://flashrom.org/trac/coreboot/changeset/1053 Log: Add SPI chip read support to the dummy flasher. This allows using the dummy flasher for SPI read debugging. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Sean Nelson <audiohacked(a)gmail.com> Modified: trunk/dummyflasher.c trunk/flash.h trunk/spi.c Modified: trunk/dummyflasher.c ============================================================================== --- trunk/dummyflasher.c Sun Jun 20 12:41:35 2010 (r1052) +++ trunk/dummyflasher.c Sun Jun 20 12:58:32 2010 (r1053) @@ -23,6 +23,7 @@ #include <ctype.h> #include <sys/types.h> #include "flash.h" +#include "chipdrivers.h" int dummy_init(void) { @@ -157,3 +158,10 @@ msg_pspew("\n"); return 0; } + +int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len) +{ + /* Maximum read length is unlimited, use 64kB. */ + return spi_read_chunked(flash, buf, start, len, 64 * 1024); +} + Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Sun Jun 20 12:41:35 2010 (r1052) +++ trunk/flash.h Sun Jun 20 12:58:32 2010 (r1053) @@ -454,6 +454,7 @@ void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); +int dummy_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len); #endif /* nic3com.c */ Modified: trunk/spi.c ============================================================================== --- trunk/spi.c Sun Jun 20 12:41:35 2010 (r1052) +++ trunk/spi.c Sun Jun 20 12:58:32 2010 (r1053) @@ -99,7 +99,7 @@ { /* SPI_CONTROLLER_DUMMY */ .command = dummy_spi_send_command, .multicommand = default_spi_send_multicommand, - .read = NULL, + .read = dummy_spi_read, .write_256 = NULL, }, #endif

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[PATCH] Modernize SPI AAI code
by Carl-Daniel Hailfinger 20 Jun '10

20 Jun '10

Modernize SPI AAI code, blacklist IT87 SPI for AAI, allow AAI to run without warnings on ICH/VIA SPI. Add some code to make conversion to partial write possible for AAI. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-spi_aai_modernize/spi25.c =================================================================== --- flashrom-spi_aai_modernize/spi25.c (Revision 1049) +++ flashrom-spi_aai_modernize/spi25.c (Arbeitskopie) @@ -1018,15 +1018,44 @@ int spi_aai_write(struct flashchip *flash, uint8_t *buf) { - uint32_t pos = 2, size = flash->total_size * 1024; - unsigned char w[6] = {0xad, 0, 0, 0, buf[0], buf[1]}; + uint32_t addr = 0; + uint32_t len = flash->total_size * 1024; + uint32_t pos = addr; int result; + unsigned char cmd[JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE] = { + JEDEC_AAI_WORD_PROGRAM, + }; + struct spi_command cmds[] = { + { + .writecnt = JEDEC_WREN_OUTSIZE, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = JEDEC_AAI_WORD_PROGRAM_OUTSIZE, + .writearr = (const unsigned char[]){ + JEDEC_AAI_WORD_PROGRAM, + (pos >> 16) & 0xff, + (pos >> 8) & 0xff, + (pos & 0xff), + buf[0], + buf[1] + }, + .readcnt = 0, + .readarr = NULL, + }, { + .writecnt = 0, + .writearr = NULL, + .readcnt = 0, + .readarr = NULL, + }}; switch (spi_controller) { #if CONFIG_INTERNAL == 1 #if defined(__i386__) || defined(__x86_64__) + case SPI_CONTROLLER_IT87XX: case SPI_CONTROLLER_WBSIO: - msg_cerr("%s: impossible with Winbond SPI masters," + msg_cerr("%s: impossible with this SPI controller," " degrading to byte program\n", __func__); return spi_chip_write_1(flash, buf); #endif @@ -1034,24 +1063,46 @@ default: break; } + + /* The data sheet requires a start address with the low bit cleared. */ + if (addr % 2) { + msg_cerr("%s: start address not even! Please report a bug at " + "flashrom(a)flashrom.org\n", __func__); + return SPI_GENERIC_ERROR; + } + /* The data sheet requires total AAI write length to be even. */ + if (len % 2) { + msg_cerr("%s: total write length not even! Please report a " + "bug at flashrom(a)flashrom.org\n", __func__); + return SPI_GENERIC_ERROR; + } + if (erase_flash(flash)) { msg_cerr("ERASE FAILED!\n"); return -1; } - /* FIXME: This will fail on ICH/VIA SPI. */ - result = spi_write_enable(); - if (result) + + result = spi_send_multicommand(cmds); + if (result) { + msg_cerr("%s failed during start command execution\n", + __func__); return result; - spi_send_command(6, 0, w, NULL); + } while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - programmer_delay(5); /* SST25VF040B Tbp is max 10us */ - while (pos < size) { - w[1] = buf[pos++]; - w[2] = buf[pos++]; - spi_send_command(3, 0, w, NULL); + programmer_delay(10); + + /* We already wrote 2 bytes in the multicommand step. */ + pos += 2; + + while (pos < addr + len) { + cmd[1] = buf[pos++]; + cmd[2] = buf[pos++]; + spi_send_command(JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE, 0, cmd, NULL); while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - programmer_delay(5); /* SST25VF040B Tbp is max 10us */ + programmer_delay(10); } + + /* Use WRDI to exit AAI mode. */ spi_write_disable(); return 0; } Index: flashrom-spi_aai_modernize/spi.h =================================================================== --- flashrom-spi_aai_modernize/spi.h (Revision 1049) +++ flashrom-spi_aai_modernize/spi.h (Arbeitskopie) @@ -112,6 +112,12 @@ #define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05 #define JEDEC_BYTE_PROGRAM_INSIZE 0x00 +/* Write AAI word (SST25VF080B) */ +#define JEDEC_AAI_WORD_PROGRAM 0xad +#define JEDEC_AAI_WORD_PROGRAM_OUTSIZE 0x06 +#define JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE 0x06 +#define JEDEC_AAI_WORD_PROGRAM_INSIZE 0x00 + /* Error codes */ #define SPI_GENERIC_ERROR -1 #define SPI_INVALID_OPCODE -2 -- http://www.hailfinger.org/

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flashrom June 2010