flashrom June 2010

flashrom@flashrom.org

74 participants
219 discussions

External programmers
by Carl-Daniel Hailfinger 25 Dec '15

25 Dec '15

Hi, I'm trying to find out which external programmers should be supported next. 1. There was talk of an AVR-based new programmer using the serprog protocol on IRC by someone with the nick "coldelectrons", but I have no idea if he/she is reading this mail. IMHO more hardware using the serprog protocol is always a good idea. 2. All those Willem/Sivava variants. People regularly request those, but I don't think anyone in here owns the hardware. 3. RayeR's SPIPGM. I have a preliminary patch which could work, but I don't have the hardware. Will send the patch to the list soon. 4. LPC^2, Milksop, CheapLPC and other programmers from the Xbox modding community. 5. Dozens of SPI programmer hardware projects scattered over the net. Too many to count, and I'm not sure which of them has more than one user. In general, it seems creating a new programmer hardware design is like writing IRC clients: A nice way to get started in the field. I have no problems merging flashrom support for all of them, but I won't implement support for all of them myself. Regards, Carl-Daniel -- http://www.hailfinger.org/

8 13

Re: [flashrom] [coreboot] Dualbios on GA-MA770-UD3
by Carl-Daniel Hailfinger 10 Aug '13

10 Aug '13

Hi Vadim, thanks for your mail. I have added the flashrom mailing list in CC: because we should develop a generic way to handle DualBIOS and similar techniques. On 09.04.2010 08:12, Vadim Girlin wrote: > I'm going to try coreboot on Gigabyte GA-MA770-UD3. > It's AMD 770 (RX780 / SB700). > > My motherboard supports hardware dual bios - with two chips on it. > I'm going to try flashing backup chip and boot from it. It seems to be > possible - I've tested it (flashing at least). Chips on this board could > be switched by changing bit 0 at undocumented register EF on LDN 7 of > IT8720. I can use slightly patched flashrom for accessing any chip I > want without any problems. And this is tested many times. > > My idea is to use backup chip for debugging - that always keeps my > chance to reboot from main bios chip. And removes the need for > desoldering etc. > > And second problem is that original bios is checking second chip - and > trying to recover it by flashing the bios from main chip on reboot? > rewriting coreboot. AFAICS this could be solved by including some > signatures etc. It seems to be easy to find out. May be someone is > working on this? > > BTW I can send the patch for flashrom - but I think that with > information I mentioned above somebody could make it much better than my > ugly hack. I hope the regs should be the same for all latest Gigabyte > MBs using IT8720/18 > It would be great if you could send that patch. It will help us make a flashrom design decision that works for all boards with multiple flash chips. By the way, some of us have good contacts at ITE, so we can ask ITE for details about the undocumented registers. Regards, Carl-Daniel -- http://www.hailfinger.org/

5 12

2 flashes on SPI bus
by Andrei Dolnikov 23 Sep '12

23 Sep '12

Hello folks, I would like to use a flashrom utility to access 2 serial flashes on the SPI bus of my x86 board, but I'm struggling with the second one. So I'm looking for any help, hints or advices which can help me to solve this issue. I have custom x86 board (Atom n450 CPU, ICH8M chipset) which have 2 serial flashes installed on it. The first one is SST25VF016B and the second one is Numonyx M45PE16. The M45PE16 is pretty the similar to the M25PE16. Both this chips are connected to the SPI bus of the ICH8M chipset, the CS (chip select) signal of the SST25VF is routed to the SPI_CS0 and the CS signal of the M45PE16 is routed to the SPI_CS1. I can successfully read, erase and write the SST flash. Trying to figure out if flashrom utility can find the second Numonyx flash I've added the proper description for it to the flashchips.c (actually I've leaved it the same as for M25PE16 but changed model_id field). Unfortunately it didn't help me at all. So I'm wondering if flashrom can't find M45PE16 flash because of cleared SPI_CS1 signal and how can I enable it? Does flashrom utility support such kind of configurations or does it simply searching for the flash on CS0? Probably some of you have some ideas on enabling SPI_CS1 or even some useful links etc. Unfortunately the official Intel ICH8M documentation looks kind of complicated and no so clear to me. I'll of course digg into it but any help, hints or advices are highly appreciated! Thanks in advance, xborodax.

2 1

[PATCH] Add Winbond SuperI/O detection
by Carl-Daniel Hailfinger 06 May '12

06 May '12

Add Winbond Super I/O detection and hook it up to the generic Super I/O detection framework. Incomplete and untested, but at least it shouldn't break anything. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-winbond_superio_detect/flash.h =================================================================== --- flashrom-winbond_superio_detect/flash.h (Revision 1064) +++ flashrom-winbond_superio_detect/flash.h (Arbeitskopie) @@ -350,6 +350,7 @@ /* board_enable.c */ void w836xx_ext_enter(uint16_t port); void w836xx_ext_leave(uint16_t port); +struct superio probe_superio_winbond(void); uint8_t sio_read(uint16_t port, uint8_t reg); void sio_write(uint16_t port, uint8_t reg, uint8_t data); void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask); @@ -388,7 +389,8 @@ }; extern struct superio superio; #define SUPERIO_VENDOR_NONE 0x0 -#define SUPERIO_VENDOR_ITE 0x1 +#define SUPERIO_VENDOR_WINBOND 0x1 +#define SUPERIO_VENDOR_ITE 0x2 struct pci_dev *pci_dev_find_filter(struct pci_filter filter); struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t class); struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device); Index: flashrom-winbond_superio_detect/internal.c =================================================================== --- flashrom-winbond_superio_detect/internal.c (Revision 1064) +++ flashrom-winbond_superio_detect/internal.c (Arbeitskopie) @@ -104,12 +104,14 @@ void probe_superio(void) { - superio = probe_superio_ite(); + superio = probe_superio_winbond(); #if 0 - /* Winbond Super I/O code is not yet available. */ + /* ITE probe causes SMSC LPC47N217 to power off the serial UART. */ if (superio.vendor == SUPERIO_VENDOR_NONE) - superio = probe_superio_winbond(); + superio = probe_superio_smsc(); #endif + if (superio.vendor == SUPERIO_VENDOR_NONE) + superio = probe_superio_ite(); } #endif Index: flashrom-winbond_superio_detect/board_enable.c =================================================================== --- flashrom-winbond_superio_detect/board_enable.c (Revision 1064) +++ flashrom-winbond_superio_detect/board_enable.c (Arbeitskopie) @@ -229,22 +229,59 @@ address, but takes no effort to make sure the chip is really a Winbond Super I/O */ -static const struct winbond_chip * winbond_superio_detect(uint16_t base) +uint8_t probe_id_winbond(uint16_t port) { uint8_t chipid; + + w836xx_ext_enter(port); + chipid = sio_read(port, 0x20); + w836xx_ext_leave(port); + + return chipid; +} + +#define WINBOND_SUPERIO_PORT1 0x2e +#define WINBOND_SUPERIO_PORT2 0x4e + +struct superio probe_superio_winbond(void) +{ + struct superio ret = {}; + uint16_t winbond_ports[] = {WINBOND_SUPERIO_PORT1, WINBOND_SUPERIO_PORT2, 0}; + uint16_t *i = winbond_ports; + + ret.vendor = SUPERIO_VENDOR_WINBOND; + for (; *i; i++) { + ret.port = *i; + ret.model = probe_id_winbond(ret.port); + switch (ret.model) { + case WINBOND_W83627HF_ID: + case WINBOND_W83627EHF_ID: + case WINBOND_W83627THF_ID: + msg_pinfo("Found Winbond Super I/O, id %02hx\n", + ret.model); + return ret; + } + } + + /* No good ID found. */ + ret.vendor = SUPERIO_VENDOR_NONE; + ret.port = 0; + ret.model = 0; + return ret; +} + +static const struct winbond_chip *winbond_superio_chipdef(void) +{ const struct winbond_chip * chip = NULL; int i; - w836xx_ext_enter(base); - chipid = sio_read(base, 0x20); for (i = 0; i < ARRAY_SIZE(winbond_chips); i++) - if (winbond_chips[i].device_id == chipid) + if (winbond_chips[i].device_id == superio.model) { chip = &winbond_chips[i]; break; } - w836xx_ext_leave(base); return chip; } @@ -259,7 +296,7 @@ int port = pin / 10; int bit = pin % 10; - chip = winbond_superio_detect(base); + chip = winbond_superio_chipdef(); if (!chip) { msg_perr("\nERROR: No supported Winbond Super I/O found\n"); return -1; -- http://www.hailfinger.org/

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Re: [flashrom] Trial of ARIMA:HDAMA Motherboard
by Carl-Daniel Hailfinger 09 Feb '12

09 Feb '12

Hi Mike, On 23.02.2010 05:45, Spangler, Mike T wrote: > I can probe with a continuity tester, but would need to know specific > pin locations to try. Do you have any generic info on doing this? Yes (well, I'd have to write up something), but the solution mentioned by Michael is way easier, so I'll wait until Michael has diagnosed the GPIO settings from the flashrom run on factory BIOS. Regards, Carl-Daniel -- "I do consider assignment statements and pointer variables to be among computer science's most valuable treasures." -- Donald E. Knuth

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[PATCH] Confirm EN29LV800 bus, timing, and page size
by TJ 02 Aug '11

02 Aug '11

Uncertain values now confirmed. If you're happy with the new EN29LV800 code I'll submit a combined patch with a Signed-off-by tag. --- flashchips.c | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-) diff --git a/flashchips.c b/flashchips.c index b5be180..10b8dea 100644 --- a/flashchips.c +++ b/flashchips.c @@ -2166,15 +2166,15 @@ struct flashchip flashchips[] = { { .vendor = "EON", .name = "EN29LV800(B)(C)B", - .bustype = CHIP_BUSTYPE_UNKNOWN, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = EON_ID, .model_id = EN_29LV800B, .total_size = 1024, - .page_size = 1024, // TODO: check this + .page_size = 1024, .feature_bits = FEATURE_ADDR_AAA | FEATURE_EITHER_RESET, .tested = TEST_UNTESTED, .probe = probe_jedec, - .probe_timing = TIMING_ZERO, /* TODO: check Datasheet has no timing info specified */ + .probe_timing = TIMING_ZERO, .erase = NULL, .block_erasers = { @@ -2198,15 +2198,15 @@ struct flashchip flashchips[] = { { .vendor = "EON", .name = "EN29LV800(B)(C)T", - .bustype = CHIP_BUSTYPE_UNKNOWN, + .bustype = CHIP_BUSTYPE_PARALLEL, .manufacture_id = EON_ID, .model_id = EN_29LV800T, .total_size = 1024, - .page_size = 1024, // TODO: check this + .page_size = 1024, .feature_bits = FEATURE_ADDR_AAA | FEATURE_EITHER_RESET, .tested = TEST_UNTESTED, .probe = probe_jedec, - .probe_timing = TIMING_ZERO, /* TODO: check Datasheet has no timing info specified */ + .probe_timing = TIMING_ZERO, .erase = NULL, .block_erasers = { -- 1.6.3.3

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Re: [flashrom] [PATCH] Fix NULL pointer reference in board_flash_enable.
by Maciej Pijanka 25 Jul '11

25 Jul '11

On Fri, 12 Mar 2010, Michael Karcher wrote: > Was introduced in r926. Found by Henrik Kretzschmar <henne(a)nachtwindheim.de>. > > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Imo looks sane and should be commited. Acked-by: Maciej Pijanka <maciej.pijanka(a)gmail.com> > --- > board_enable.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/board_enable.c b/board_enable.c > index aa463bc..0e89137 100644 > --- a/board_enable.c > +++ b/board_enable.c > @@ -1445,7 +1445,7 @@ int board_flash_enable(const char *vendor, const char *part) > if (!board) > board = board_match_pci_card_ids(); > > - if (board->status == NT) { > + if (board && board->status == NT) { > if (!force_boardenable) > { > printf("WARNING: Your mainboard is %s %s, but the mainboard-specific\n" > -- -- Maciej Pijanka I don't fear computers, I fear lack of them -- Isaac Asimov

2 1

MSI K9A2 Platinum OK
by Sylvain BERTRAND 12 Jul '11

12 Jul '11

Hi, Successfully flashed BIOS v1.9 on this motherboard. Cheers, Sylvain BERTRAND

2 2

[PATCH] Flush stdout after each message
by Ed Swierk 19 Jun '11

19 Jun '11

Currently messages like "Writing flash chip..." that don't end with a newline are buffered until the operation is complete, unless the particular write function generates status output in the meantime. Flushing stdout after each message ensures that the message appears immediately. Signed-off-by: Ed Swierk <eswierk(a)aristanetworks.com> --- Index: flashrom-0.9.2-r1057/cli_output.c =================================================================== --- flashrom-0.9.2-r1057.orig/cli_output.c +++ flashrom-0.9.2-r1057/cli_output.c @@ -47,5 +47,6 @@ int print(int type, const char *fmt, ... va_start(ap, fmt); ret = vfprintf(output_type, fmt, ap); va_end(ap); + fflush(output_type); return ret; }

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Re: [flashrom] [PATCH] Don't ignore wait_82802ab() return value
by Stefan Reinauer 19 Jun '11

19 Jun '11

On 5/14/10 3:06 PM, Michael Karcher wrote: > Am Freitag, den 14.05.2010, 14:48 +0200 schrieb Stefan Reinauer: > >> On 4/16/10 6:21 PM, Stefan Reinauer wrote: >> >>> Look at the return value of wait_82802ab() >>> Index: sst49lfxxxc.c >>> =================================================================== >>> --- sst49lfxxxc.c (revision 993) >>> +++ sst49lfxxxc.c (working copy) >>> @@ -84,6 +84,7 @@ >>> chip_writeb(0xD0, bios + address); >>> >>> status = wait_82802ab(bios); >>> + print_status_82802ab(status); >>> > [...] > basically a good idea, but printing one status dump per erased block > seems a bit excessive, even in verbose mode, as there are some chips > with 4K sector size. Could you limit status printing to "status != > 0x80", as this is "ready, no error bits"? > That's what the 82802ab and sharp lhf00l04 do, too. So if you think the behavior should be changed, you should change it in all three places. Stefan

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flashrom June 2010