flashrom April 2010

flashrom@flashrom.org

55 participants
102 discussions

bios issue
by admin1 03 Apr '10

03 Apr '10

I just flashed my Gateway m275 Tablet running ubuntu 9.10 with the 480401.bin bios from gateway and I have now been directed to e-mail you the failure report. Can you pleas help me? ifying flash... VERIFY FAILED at 0x00005002! Expected=0x7f, Read=0x3f, failed byte count from 0x00000000-0x0007ffff: 0x4fa18 Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net channel #flashrom or mail flashrom(a)flashrom.org

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Re: [flashrom] [PATCH, v2] Intel 28F004/28F400 support
by Carl-Daniel Hailfinger 03 Apr '10

03 Apr '10

On 01.04.2010 20:12, Michael Karcher wrote: > Remove blockwise write for i82802ab chips. It will be reintroduced > in post-0.9.2 in a generic way. This is needed to fix > FWH-like chips with non-uniform sectors. > > These are: > Intel 28F001 > Sharp LHF00L04 > ST M50FW002 > ST M50LPW116 > > Add IDs for Intel 28F004/28F400 > I have modified the changelog a bit. > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > With the comments below addressed, this is Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> > 82802ab.c | 54 +++++++++------------------- > flash.h | 2 +- > flashchips.c | 110 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > flashchips.h | 4 ++ > 4 files changed, 133 insertions(+), 37 deletions(-) > create mode 100755 dmidecode > > diff --git a/82802ab.c b/82802ab.c > index aa7e45e..0d1bd1a 100644 > --- a/82802ab.c > +++ b/82802ab.c > @@ -48,6 +48,7 @@ int probe_82802ab(struct flashchip *flash) > chipaddr bios = flash->virtual_memory; > uint8_t id1, id2; > uint8_t flashcontent1, flashcontent2; > + int shifted = (flash->feature_bits & FEATURE_ADDR_SHIFTED) != 0; > Can we rely on the compiler to set shifted=1 if the feature bit is set? We assign a boolean value to int shifted, and AFAIK the compiler is free to use pretty much any value here as long as that value gives reliable results (could be 0x2, could be 0xffffffff). What about the following code instead? + int shifted = (flash->feature_bits & FEATURE_ADDR_SHIFTED) ? 1 : 0; > > /* Reset to get a clean state */ > chip_writeb(0xFF, bios); > @@ -178,44 +179,25 @@ void write_page_82802ab(chipaddr bios, uint8_t *src, > int write_82802ab(struct flashchip *flash, uint8_t *buf) > { > int i; > - int total_size = flash->total_size * 1024; > - int page_size = flash->page_size; > chipaddr bios = flash->virtual_memory; > - uint8_t *tmpbuf = malloc(page_size); > > - if (!tmpbuf) { > - msg_cerr("Could not allocate memory!\n"); > - exit(1); > + if (erase_flash(flash)) { > + msg_cerr("ERASE FAILED!\n"); > + return -1; > } > - msg_cinfo("Programming page: \n"); > - for (i = 0; i < total_size / page_size; i++) { > [...] > + msg_cinfo("Programming page: "); > + for (i = 0; i < flash->total_size; i++) { > You change the write chunk size from page_size to 1024. Does "programming page" still make sense, or should it be "programming chunk at"? > diff --git a/dmidecode b/dmidecode > new file mode 100755 > index 0000000..e69de29 > Uhhh. Please make sure you don't commit dmidecode by accident. > diff --git a/flashchips.c b/flashchips.c > index 2dbc1e0..a9b6551 100644 > --- a/flashchips.c > +++ b/flashchips.c > @@ -2385,6 +2385,116 @@ struct flashchip flashchips[] = { > + { > + .vendor = "Intel", > + .name = "28F400BV/CV/CE-B", > + .bustype = CHIP_BUSTYPE_PARALLEL, > + .manufacture_id = INTEL_ID, > + .model_id = P28F400BB, > + }, > + > + { > + .vendor = "Intel", > + .name = "28F400BV/CV/CE-B", > Should be ...CE-T unless I'm mistaken. > + .bustype = CHIP_BUSTYPE_PARALLEL, > + .manufacture_id = INTEL_ID, > + .model_id = P28F400BT, > A compile test and run test with -p dummy (which triggers the automatic chipdefinition selftest) would be appreciated before committing just to make sure I didn't overlook anything problematic. Regards, Carl-Daniel -- http://www.hailfinger.org/

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[commit] r991 - trunk
by repository service 03 Apr '10

03 Apr '10

Author: mkarcher Date: Sat Apr 3 12:27:08 2010 New Revision: 991 URL: http://flashrom.org/trac/coreboot/changeset/991 Log: Intel 28F004/28F400 support Remove blockwise write for i82802ab chips. It will be reintroduced in post-0.9.2 in a generic way. This is needed to fix FWH-like chips with non-uniform sectors. These are: Intel 28F001 Sharp LHF00L04 ST M50FW002 ST M50LPW116 Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/82802ab.c trunk/flash.h trunk/flashchips.c trunk/flashchips.h Modified: trunk/82802ab.c ============================================================================== --- trunk/82802ab.c Thu Apr 1 01:55:06 2010 (r990) +++ trunk/82802ab.c Sat Apr 3 12:27:08 2010 (r991) @@ -48,6 +48,7 @@ chipaddr bios = flash->virtual_memory; uint8_t id1, id2; uint8_t flashcontent1, flashcontent2; + int shifted = (flash->feature_bits & FEATURE_ADDR_SHIFTED) != 0; /* Reset to get a clean state */ chip_writeb(0xFF, bios); @@ -57,8 +58,8 @@ chip_writeb(0x90, bios); programmer_delay(10); - id1 = chip_readb(bios); - id2 = chip_readb(bios + 0x01); + id1 = chip_readb(bios + (0x00 << shifted)); + id2 = chip_readb(bios + (0x01 << shifted)); /* Leave ID mode */ chip_writeb(0xFF, bios); @@ -71,8 +72,8 @@ msg_cdbg(", id1 parity violation"); /* Read the product ID location again. We should now see normal flash contents. */ - flashcontent1 = chip_readb(bios); - flashcontent2 = chip_readb(bios + 0x01); + flashcontent1 = chip_readb(bios + (0x00 << shifted)); + flashcontent2 = chip_readb(bios + (0x01 << shifted)); if (id1 == flashcontent1) msg_cdbg(", id1 is normal flash content"); @@ -178,44 +179,25 @@ int write_82802ab(struct flashchip *flash, uint8_t *buf) { int i; - int total_size = flash->total_size * 1024; - int page_size = flash->page_size; chipaddr bios = flash->virtual_memory; - uint8_t *tmpbuf = malloc(page_size); - if (!tmpbuf) { - msg_cerr("Could not allocate memory!\n"); - exit(1); - } - msg_cinfo("Programming page: \n"); - for (i = 0; i < total_size / page_size; i++) { - msg_cinfo("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); - msg_cinfo("%04d at address: 0x%08x", i, i * page_size); - - /* Auto Skip Blocks, which already contain the desired data - * Faster, because we only write, what has changed - * More secure, because blocks, which are excluded - * (with the exclude or layout feature) - * or not erased and rewritten; their data is retained also in - * sudden power off situations - */ - chip_readn(tmpbuf, bios + i * page_size, page_size); - if (!memcmp((void *)(buf + i * page_size), tmpbuf, page_size)) { - msg_cdbg("SKIPPED\n"); - continue; - } + if (erase_flash(flash)) { + msg_cerr("ERASE FAILED!\n"); + return -1; + } - /* erase block by block and write block by block; this is the most secure way */ - if (erase_block_82802ab(flash, i * page_size, page_size)) { - msg_cerr("ERASE FAILED!\n"); - return -1; - } - write_page_82802ab(bios, buf + i * page_size, - bios + i * page_size, page_size); + msg_cinfo("Programming at: "); + for (i = 0; i < flash->total_size; i++) { + if ((i & 0x3) == 0) + msg_cinfo("address: 0x%08lx", (unsigned long)i * 1024); + + write_page_82802ab(bios, buf + i * 1024, bios + i * 1024, 1024); + + if ((i & 0x3) == 0) + msg_cinfo("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); } - msg_cinfo("DONE!\n"); - free(tmpbuf); + msg_cinfo("DONE!\n"); return 0; } Modified: trunk/flash.h ============================================================================== --- trunk/flash.h Thu Apr 1 01:55:06 2010 (r990) +++ trunk/flash.h Sat Apr 3 12:27:08 2010 (r991) @@ -166,7 +166,7 @@ #define FEATURE_ADDR_MASK (3 << 2) #define FEATURE_ADDR_2AA (1 << 2) #define FEATURE_ADDR_AAA (2 << 2) -#define FEATURE_ADDR_SHIFTED 0 +#define FEATURE_ADDR_SHIFTED (1 << 5) struct flashchip { const char *vendor; Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Thu Apr 1 01:55:06 2010 (r990) +++ trunk/flashchips.c Sat Apr 3 12:27:08 2010 (r991) @@ -2385,6 +2385,116 @@ { .vendor = "Intel", + .name = "28F004BV/BE-B", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = INTEL_ID, + .model_id = P28F004BB, + .total_size = 512, + .page_size = 128 * 1024, /* maximal block size */ + .tested = TEST_UNTESTED, + .probe = probe_82802ab, + .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ + .block_erasers = + { + { + .eraseblocks = { + {16 * 1024, 1}, + {8 * 1024, 2}, + {96 * 1024, 1}, + {128 * 1024, 3}, + }, + .block_erase = erase_block_82802ab, + }, + }, + .write = write_82802ab, + .read = read_memmapped, + }, + + { + .vendor = "Intel", + .name = "28F004BV/BE-T", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = INTEL_ID, + .model_id = P28F004BT, + .total_size = 512, + .page_size = 128 * 1024, /* maximal block size */ + .tested = TEST_UNTESTED, + .probe = probe_82802ab, + .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ + .block_erasers = + { + { + .eraseblocks = { + {128 * 1024, 3}, + {96 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_block_82802ab, + }, + }, + .write = write_82802ab, + .read = read_memmapped, + }, + + { + .vendor = "Intel", + .name = "28F400BV/CV/CE-B", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = INTEL_ID, + .model_id = P28F400BB, + .total_size = 512, + .page_size = 128 * 1024, /* maximal block size */ + .feature_bits = FEATURE_ADDR_SHIFTED, + .tested = TEST_UNTESTED, + .probe = probe_82802ab, + .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ + .block_erasers = + { + { + .eraseblocks = { + {16 * 1024, 1}, + {8 * 1024, 2}, + {96 * 1024, 1}, + {128 * 1024, 3}, + }, + .block_erase = erase_block_82802ab, + }, + }, + .write = write_82802ab, + .read = read_memmapped, + }, + + { + .vendor = "Intel", + .name = "28F400BV/CV/CE-T", + .bustype = CHIP_BUSTYPE_PARALLEL, + .manufacture_id = INTEL_ID, + .model_id = P28F400BT, + .total_size = 512, + .page_size = 128 * 1024, /* maximal block size */ + .feature_bits = FEATURE_ADDR_SHIFTED, + .tested = TEST_UNTESTED, + .probe = probe_82802ab, + .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ + .block_erasers = + { + { + .eraseblocks = { + {128 * 1024, 3}, + {96 * 1024, 1}, + {8 * 1024, 2}, + {16 * 1024, 1}, + }, + .block_erase = erase_block_82802ab, + }, + }, + .write = write_82802ab, + .read = read_memmapped, + }, + + { + .vendor = "Intel", .name = "82802AB", .bustype = CHIP_BUSTYPE_FWH, .manufacture_id = INTEL_ID, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Thu Apr 1 01:55:06 2010 (r990) +++ trunk/flashchips.h Sat Apr 3 12:27:08 2010 (r991) @@ -259,6 +259,10 @@ #define E_28F016S5 0xAA #define P28F001BXT 0x94 /* 28F001BX-T */ #define P28F001BXB 0x95 /* 28F001BX-B */ +#define P28F004BT 0x78 /* 28F004BV/BE-T */ +#define P28F004BB 0x79 /* 28F004BV/BE-B */ +#define P28F400BT 0x70 /* 28F400BV/CV/CE-T */ +#define P28F400BB 0x71 /* 28F400BV/CV/CE-B */ #define SHARP_LH28F008SA 0xA2 /* Sharp chip, Intel Vendor ID */ #define SHARP_LH28F008SC 0xA6 /* Sharp chip, Intel Vendor ID */

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[PATCH, v2, compilable] Board enable for IP530
by Michael Karcher 03 Apr '10

03 Apr '10

Now also leaves conf mode and selects the right logical device number. Autodetection fixed by putting the chip with (bogus) subdevice first. --- board_enable.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 43 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index 26c4d09..d1c09a7 100644 --- a/board_enable.c +++ b/board_enable.c @@ -96,6 +96,48 @@ static int enable_flash_decode_superio(void) #endif /** + * SMSC FDC37B787: Raise GPIO50 + */ + +static int fdc37b787_gpio50_raise(uint16_t port, const char * name) +{ + uint8_t id, val; + + OUTB(0x55, port); /* enter conf mode */ + id = sio_read(port, 0x20); + if (id != 0x44) { + fprintf(stderr, "\nERROR: %s: FDC37B787: Wrong ID 0x%02X.\n", + name, id); + OUTB(0xAA, port); /* leave conf mode */ + return -1; + } + + sio_write(port, 0x07, 0x08); /* Select Aux I/O subdevice */ + + val = sio_read(port, 0xC8); /* GP50 */ + if ((val & 0x1B) != 0x10) /* output, no invert, GPIO */ + { + fprintf(stderr, "\nERROR: %s: GPIO50 mode 0x%02X unexpected.\n", + name, val); + OUTB(0xAA, port); + return -1; + } + + sio_mask(port, 0xF9, 0x01, 0x01); + + OUTB(0xAA, port); /* Leave conf mode */ + return 0; +} + +/** + * Suited for Nokia IP530: Intel 440BX + PIIX4 + FDC37B787 + */ +static int fdc37b787_gpio50_raise_3f0(const char *name) +{ + return fdc37b787_gpio50_raise(0x3f0, name); +} + +/** * Winbond W83627HF: Raise GPIO24. * * Suited for: @@ -1398,6 +1440,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio4_4_raise_4e}, {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8N GM2-L)", 0, NT, nvidia_mcp_gpio2_raise}, {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, + {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0}, {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, -- 1.7.0

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[PATCH, really v2] Board enable for IP530
by Michael Karcher 03 Apr '10

03 Apr '10

Now also leaves conf mode and selects the right logical device number. Autodetection fixed by putting the chip with (bogus) subdevice first. --- board_enable.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 43 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index 26c4d09..c434fc4 100644 --- a/board_enable.c +++ b/board_enable.c @@ -96,6 +96,48 @@ static int enable_flash_decode_superio(void) #endif /** + * SMSC FDC37B787: Raise GPIO50 + */ + +static int fdc37b787_gpio50_raise(uint16_t port, const char * name) +{ + uint8_t id, val; + + OUTB(0x55, port); /* enter conf mode */ + id = sio_read(port, 0x20); + if (id != 0x44) { + fprintf(stderr, "\nERROR: %s: FDC37B787: Wrong ID 0x%02X.\n", + name, id); + OUTB(0xAA, port); /* leave conf mode */ + return -1; + } + + sio_write(0x07, 0x08); /* Select Aux I/O subdevice */ + + val = sio_read(port, 0xC8); /* GP50 */ + if ((val & 0x1B) != 0x10) /* output, no invert, GPIO */ + { + fprintf(stderr, "\nERROR: %s: GPIO50 mode 0x%02X unexpected.\n", + name, val); + OUTB(0xAA, port); + return -1; + } + + sio_mask(port, 0xF9, 0x01, 0x01); + + OUTB(0xAA, port); /* Leave conf mode */ + return 0; +} + +/** + * Suited for Nokia IP530: Intel 440BX + PIIX4 + FDC37B787 + */ +static int fdc37b787_gpio50_raise_3f0(const char *name) +{ + return fdc37b787_gpio50_raise(0x3f0, name); +} + +/** * Winbond W83627HF: Raise GPIO24. * * Suited for: @@ -1398,6 +1440,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio4_4_raise_4e}, {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8N GM2-L)", 0, NT, nvidia_mcp_gpio2_raise}, {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, + {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0}, {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, -- 1.7.0

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[PATCH, v2] Board enable for IP530
by Michael Karcher 03 Apr '10

03 Apr '10

Now also leaves conf mode and selects the right logical device number. --- board_enable.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 files changed, 40 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index 26c4d09..f88b084 100644 --- a/board_enable.c +++ b/board_enable.c @@ -96,6 +96,45 @@ static int enable_flash_decode_superio(void) #endif /** + * SMSC FDC37B787: Raise GPIO50 + */ + +static int fdc37b787_gpio50_raise(uint16_t port, const char * name) +{ + uint8_t id, val; + + OUTB(0x55, port); /* enter conf mode */ + id = sio_read(port, 0x20); + if (id != 0x44) { + fprintf(stderr, "\nERROR: %s: FDC37B787: Wrong ID 0x%02X.\n", + name, id); + OUTB(0xAA, port); /* leave conf mode */ + return -1; + } + + val = sio_read(port, 0xC8); /* GP50 */ + if ((val & 0x1B) != 0x10) /* output, no invert, GPIO */ + { + fprintf(stderr, "\nERROR: %s: GPIO50 mode 0x%02X unexpected.\n", + name, val); + OUTB(0xAA, port); + return -1; + } + + sio_mask(port, 0xF9, 0x01, 0x01); + return 0; +} + +/** + * + * Suited for Nokia IP530: Intel 440BX + PIIX4 + FDC37B787 + */ +static int fdc37b787_gpio50_raise_3f0(const char *name) +{ + return fdc37b787_gpio50_raise(0x3f0, name); +} + +/** * Winbond W83627HF: Raise GPIO24. * * Suited for: @@ -1398,6 +1437,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio4_4_raise_4e}, {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8N GM2-L)", 0, NT, nvidia_mcp_gpio2_raise}, {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, + {0x8086, 0x7190, 0, 0, 0x1011, 0x0019, 0xaa55, 0xaa55, NULL, NULL, NULL, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0}, {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, -- 1.7.0

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flashrom on an Alpha Workstation 433au
by adrian.glaubitz＠googlemail.com 03 Apr '10

03 Apr '10

Hi, as the subject suggests I have run flashrom on a DEC Alpha Digital Personal Workstation [1], model 433au. flashrom itself segfaults but superiotool finds a SuperIO at least. Most DEC Alpha workstations are flashed using a proprietary flash utility which is run from the the SRM console [2]. There are several manuals on the net from DEC and Compaq which describe how to update the firmware using the original utilities, for example [3]. I have no idea so far how to enable/disable writing to the flash rom chips but I think it should not require any more magic than on x86 systems ;). Especially, because many of the Alpha systems are actually using Intel chipsets. Usually those Alpha machines have a jumper onboard which enables/disables flash write so there probably isn't the need for a specific board enable at all. Probably it's just a matter of finding the proper location of the address space of the flash chip in memory. I'm attaching the debug logs for superiotool -dV, lspci -nnvvvxxx and flashrom -V. Adrian [1] http://en.wikipedia.org/wiki/Digital_Personal_Workstation [2] http://www.compaq.com/alphaserver/download/srm_reference.pdf [3] ftp://15.200.2.21/ftp1/pub/alphaserver/firmware/retired_platforms/workstations/ASTN600/alpha500_600_V72_fw_relnote.pdf

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[PATCH] Board enable for IP530
by Michael Karcher 03 Apr '10

03 Apr '10

Definitely post-0.9.2 --- board_enable.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 files changed, 40 insertions(+), 0 deletions(-) diff --git a/board_enable.c b/board_enable.c index 26c4d09..f88b084 100644 --- a/board_enable.c +++ b/board_enable.c @@ -96,6 +96,45 @@ static int enable_flash_decode_superio(void) #endif /** + * SMSC FDC37B787: Raise GPIO50 + */ + +static int fdc37b787_gpio50_raise(uint16_t port, const char * name) +{ + uint8_t id, val; + + OUTB(0x55, port); /* enter conf mode */ + id = sio_read(port, 0x20); + if (id != 0x44) { + fprintf(stderr, "\nERROR: %s: FDC37B787: Wrong ID 0x%02X.\n", + name, id); + OUTB(0xAA, port); /* leave conf mode */ + return -1; + } + + val = sio_read(port, 0xC8); /* GP50 */ + if ((val & 0x1B) != 0x10) /* output, no invert, GPIO */ + { + fprintf(stderr, "\nERROR: %s: GPIO50 mode 0x%02X unexpected.\n", + name, val); + OUTB(0xAA, port); + return -1; + } + + sio_mask(port, 0xF9, 0x01, 0x01); + return 0; +} + +/** + * Suited for Nokia IP530: Intel 440BX + PIIX4 + FDC37B787 + */ +static int fdc37b787_gpio50_raise_3f0(const char *name) +{ + return fdc37b787_gpio50_raise(0x3f0, name); +} + +/** * Winbond W83627HF: Raise GPIO24. * * Suited for: @@ -1398,6 +1437,7 @@ struct board_pciid_enable board_pciid_enables[] = { {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio4_4_raise_4e}, {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8N GM2-L)", 0, NT, nvidia_mcp_gpio2_raise}, {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, + {0x8086, 0x7190, 0, 0, 0x1011, 0x0019, 0xaa55, 0xaa55, NULL, NULL, NULL, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0}, {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, it8705f_write_enable_2e}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, -- 1.7.0

1 0

NVIDIA MCP61
by Free Wind 02 Apr '10

02 Apr '10

flashrom v0.9.1-r946 No coreboot table found. DMI string system-manufacturer: "MSI" DMI string system-product-name: "MS-7309" DMI string system-version: "1.0" DMI string baseboard-manufacturer: "MSI" DMI string baseboard-product-name: "MS-7309" DMI string baseboard-version: "1.0" DMI string chassis-type: "Desktop" Found chipset "NVIDIA MCP61", enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 Guessed flash bus type is LPC Found SMBus device 10de:03eb at 00:01:1 SPI BAR is at 0xfec80000, after clearing low bits BAR is at 0xfec80000 Strange. MCP SPI BAR is valid, but chipset apparently doesn't have SPI enabled. Please send the output of "flashrom -V" to flashrom(a)flashrom.org to help us finish support for your chipset. Thanks. OK. This chipset supports the following protocols: LPC. Calibrating delay loop... 706M loops per second, 100 myus = 201 us. OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F016D, 2048 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29F080B, 1024 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29LV040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMD Am29LV081B, 1024 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ASD AE49F2008, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT29C010A, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT29C020, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT29C040A, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N), 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMIC A25L40PT, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for AMIC A25L40PU, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMIC A29002T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMIC A29040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0x0d, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for EMST F49B002UA, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Eon EN25B05, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B05T, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B10T, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B20T, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B40T, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B80T, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B16T, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B32T, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25B64T, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Eon EN29F010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Intel 28F004S5, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Intel 82802AB, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Intel 82802AC, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Macronix MX25L512, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC Pm29F002T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for PMC Pm29F002B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0x49, id2 0x2c, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0x0d, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Sharp LHF00L04, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Spansion S25FL008A, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST29EE010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST29LE010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST29EE020A, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST29LE020, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39SF512, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39SF010A, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39SF020A, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39SF040, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF512, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF010, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF020, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF040, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST39VF080, 1024 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SST SST49LF002A/B, 256 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF003A/B, 384 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF004A/B, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF004C, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF008A, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF008C, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF016C, 2048 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0x49, id2 0x2c, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0x49, id2 0x2c, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0x0d, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0x0d, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M25P05-A, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29F040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29F400BT, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29W010B, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29W040B, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M29W512B, 64 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x0d, id2 0xfc Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x0d, id2 0xfc Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW002, 256 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for ST M50FW016, 2048 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for ST M50FW040, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for ST M50FW080, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W25x10, 128 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x32, 4096 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W25x64, 8192 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W29C020C, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W29C040P, 512 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W29EE011, 128 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0x0d, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 KB: probe_jedec_common: id1 0x0d, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x0d, id2 0xfc, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: skipped. Host bus type LPC and chip bus type Parallel are incompatible. Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0x49, id2 0x2c, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Winbond W39V080FA, 1024 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Host bus type LPC and chip bus type FWH are incompatible. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. Host bus type LPC and chip bus type SPI are incompatible. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically.

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Re: [flashrom] [PATCH] Intel 28F004/28F400 support
by Carl-Daniel Hailfinger 01 Apr '10

01 Apr '10

On 01.04.2010 00:48, Michael Karcher wrote: > This should also fix broken write for non-uniform sectored FWH-like chips. > These are: > Intel 28F001 > Sharp LHF00L04 > ST M50FW002 > ST M50LPW116 > > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > --- > 82802ab.c | 85 +++++++++++++++++++++++++++++-------------- > chipdrivers.h | 3 ++ > flash.h | 2 +- > flashchips.c | 110 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > flashchips.h | 4 ++ > 5 files changed, 175 insertions(+), 29 deletions(-) > > diff --git a/82802ab.c b/82802ab.c > index aa7e45e..27acaa3 100644 > --- a/82802ab.c > +++ b/82802ab.c > @@ -48,6 +48,12 @@ int probe_82802ab(struct flashchip *flash) > chipaddr bios = flash->virtual_memory; > uint8_t id1, id2; > uint8_t flashcontent1, flashcontent2; > + int id2_offset; > + > + if (flash->feature_bits & FEATURE_ADDR_SHIFTED) > Umm... I'm pretty sure that FEATURE_ADDR_SHIFTED has another meaning (the 0x555 etc shifted left by one bit). The id2_offset may be needed anyway, but I propose to use a variable "shifted" which is 0 for all non-shifted chips and 1 for all shifted chips. It would be used as left shift for every programmatic access to special addresses. Such a change would allow us to kill m29f400bt.c which has buggy write functions anyway. Example for probing: /* Issue JEDEC Product ID Entry command */ chip_writeb(0xAA, bios + (0x5555 & mask) << shifted); chip_writeb(0x55, bios + (0x2AAA & mask) << shifted); chip_writeb(0x90, bios + (0x5555 & mask) << shifted); > + id2_offset = 2; > + else > + id2_offset = 1; > > /* Reset to get a clean state */ > chip_writeb(0xFF, bios); > @@ -58,7 +64,7 @@ int probe_82802ab(struct flashchip *flash) > programmer_delay(10); > > id1 = chip_readb(bios); > Arguably my "shifted" proposal suggests to use the following line for consistency: id1 = chip_readb(bios + 0x00 << shifted); > - id2 = chip_readb(bios + 0x01); > + id2 = chip_readb(bios + id2_offset); > id2 = chip_readb(bios + 0x01 << shifted); > > /* Leave ID mode */ > chip_writeb(0xFF, bios); > @@ -72,7 +78,7 @@ int probe_82802ab(struct flashchip *flash) > > /* Read the product ID location again. We should now see normal flash contents. */ > flashcontent1 = chip_readb(bios); > - flashcontent2 = chip_readb(bios + 0x01); > + flashcontent2 = chip_readb(bios + id2_offset); > > if (id1 == flashcontent1) > msg_cdbg(", id1 is normal flash content"); > @@ -177,41 +183,64 @@ void write_page_82802ab(chipaddr bios, uint8_t *src, > > int write_82802ab(struct flashchip *flash, uint8_t *buf) > { > - int i; > - int total_size = flash->total_size * 1024; > + int i, j, blocknum; > + int blockoffset = 0; > int page_size = flash->page_size; > chipaddr bios = flash->virtual_memory; > uint8_t *tmpbuf = malloc(page_size); > + struct eraseblock * blocks; > + int (*erase) (struct flashchip *flash, unsigned int blockaddr, > + unsigned int blocklen); > + > + /* find first erase layout with a working erase function */ > + for (i = 0; flash->block_erasers[i].block_erase == NULL && > + i < NUM_ERASEFUNCTIONS; i++); > + > + if (i == NUM_ERASEFUNCTIONS) > + { > + msg_perr("No working erase function found - can't write\n"); > + return -1; > + } > + msg_pdbg("Chosing block layout #%d\n", i); > + blocks = flash->block_erasers[i].eraseblocks; > + erase = flash->block_erasers[i].block_erase; > That's too clever to be risked for 0.9.2. I can't see obvious bugs, but this code triggers my "might break if included directly before a release" fear. > > if (!tmpbuf) { > msg_cerr("Could not allocate memory!\n"); > exit(1); > } > - msg_cinfo("Programming page: \n"); > - for (i = 0; i < total_size / page_size; i++) { > - msg_cinfo("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); > - msg_cinfo("%04d at address: 0x%08x", i, i * page_size); > - > - /* Auto Skip Blocks, which already contain the desired data > - * Faster, because we only write, what has changed > - * More secure, because blocks, which are excluded > - * (with the exclude or layout feature) > - * or not erased and rewritten; their data is retained also in > - * sudden power off situations > - */ > - chip_readn(tmpbuf, bios + i * page_size, page_size); > - if (!memcmp((void *)(buf + i * page_size), tmpbuf, page_size)) { > - msg_cdbg("SKIPPED\n"); > - continue; > - } > - > - /* erase block by block and write block by block; this is the most secure way */ > - if (erase_block_82802ab(flash, i * page_size, page_size)) { > - msg_cerr("ERASE FAILED!\n"); > - return -1; > + msg_cinfo("Programming block: \n"); > + blocknum = 0; > + for (i = 0; blocks[i].size != 0; i++) { > This is guaranteed access random data if a chip has NUM_ERASEREGIONS erase regions for a particular erase function. Either check for i<NUM_ERASEREGIONS as well or use the chip size as upper limit. The chip size check is probably more difficult here. > + for(j = 0; j < blocks[i].count; j++) { > + msg_cinfo("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b" > + "\b\b\b\b\b\b\b\b\b\b\b"); > + msg_cinfo("%04d at address: 0x%08x", blocknum, > + blockoffset); > + > + /* Auto Skip Blocks, which already contain the > + * desired data: > + * Faster, because we only write, what has changed > + * More secure, because blocks, which are excluded > + * (with the exclude or layout feature) > + * or not erased and rewritten; their data is > + * retained also in sudden power off situations > + */ > + chip_readn(tmpbuf, bios + blockoffset, blocks[i].size); > + if (!memcmp((void *)(buf + i * page_size), tmpbuf, > + blocks[i].size)) { > + msg_cdbg("SKIPPED\n"); > + } else { > + if (erase(flash, blockoffset, page_size)) { > + msg_cerr("ERASE FAILED!\n"); > + return -1; > + } > + write_page_82802ab(bios, buf + blockoffset, > + bios + blockoffset, blocks[i].size); > + } > + blockoffset += blocks[i].size; > + blocknum++; > } > - write_page_82802ab(bios, buf + i * page_size, > - bios + i * page_size, page_size); > To be honest, I think the current code in write_82802ab() is something that should be ripped out and destroyed. It is essentially special-casing partial writes for a family of chips instead of doing it correctly in the generic code. The conversion to partial writes will happen post 0.9.2 anyway, and then this code will be ripped out completely. Your changes, on the other hand, beat at least some sanity into the code, so it would be desirable to have them in generic code post-0.9.2. Please coordinate with David Hendricks who is working on partial flashing. > } > msg_cinfo("DONE!\n"); > free(tmpbuf); > diff --git a/chipdrivers.h b/chipdrivers.h > index 6d5cef0..816088a 100644 > --- a/chipdrivers.h > +++ b/chipdrivers.h > @@ -53,6 +53,9 @@ int spi_nbyte_read(int addr, uint8_t *bytes, int len); > int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); > int spi_aai_write(struct flashchip *flash, uint8_t *buf); > > +/* i28f00x.c */ > +int write_28f00x(struct flashchip *flash, uint8_t *buf); > I don't see that function anywhere. Did you forget to svn add? Or was this some aborted attempt? > + > /* 82802ab.c */ > uint8_t wait_82802ab(chipaddr bios); > int probe_82802ab(struct flashchip *flash); > diff --git a/flashchips.c b/flashchips.c > index 2dbc1e0..f838ab2 100644 > --- a/flashchips.c > +++ b/flashchips.c > @@ -2385,6 +2385,116 @@ struct flashchip flashchips[] = { > > { > .vendor = "Intel", > + .name = "28F004BV/BE-B", > + .bustype = CHIP_BUSTYPE_PARALLEL, > + }, > + > + { > + .vendor = "Intel", > + .name = "28F004BV/BE-T", > + .bustype = CHIP_BUSTYPE_PARALLEL, > + }, > + > + { > + .vendor = "Intel", > + .name = "28F400BV/CV/CE-B", > + .bustype = CHIP_BUSTYPE_PARALLEL, > + .feature_bits = FEATURE_ADDR_SHIFTED, > + }, > + > + { > + .vendor = "Intel", > + .name = "28F004BV/BE-T", > That name is identical to the one two chips above AFAICS. > + .bustype = CHIP_BUSTYPE_PARALLEL, > + .feature_bits = FEATURE_ADDR_SHIFTED, > So the bottom two chips have the address left-shifted by 1 bit, but use full address size? Suggestions: How about pointing the FEATURE_ADDR_SHIFTED chips to a to-be-fixed m29f400bt.c for now? It would reduce jedec.c changes a bit. How about using erase_flash() in write_82802ab() and dropping any rolling reflash mechanism until post 0.9.2? It should solve all non-uniform sector stuff. While that's a fear-reaching change as well, I believe it makes the code more reviewable, and does allow us to kill more duplicated code. As an added benefit, conversion to partial write will be easier. Regards, Carl-Daniel -- http://www.hailfinger.org/

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flashrom April 2010