flashrom currently doesn't have a coherent policy about failed writes.
Some chip drivers abort on the first failed write, others keep going
until the end. Either variant makes sense, but mixing them is suboptimal.
The following policies are available:
- hardcode abort early (on first error)
- hardcode abort never (ignore all errors until the end)
- switch behaviour based on commandline parameter.
Developer quote of the month:
"We are juggling too many chainsaws and flaming arrows and tigers."
Hello, I was able to successfully flash my board with a new bios.
There was one warning about spi_chip_erase_60 failing, this didn't
affect the outcome and flash was verified.
Board model: DFI Infinity Blood-Iron P35-T2RL
Bios download link: http://img.lanparty.tw/Upload/BIOS/CM/I35RD924.zip
$ sudo flashrom -w I35RD924.BIN
No coreboot table found.
Found chipset "Intel ICH9R", enabling flash write... OK.
This chipset supports the following protocols: LPC,FWH,SPI.
Calibrating delay loop... OK.
Found chip "SST SST25VF080B" (1024 KB, SPI) at physical address 0xfff00000.
Flash image seems to be a legacy BIOS. Disabling checks.
Writing flash chip... Erasing flash before programming...
spi_chip_erase_60 failed during command execution
Verifying flash... VERIFIED.
Requested output attached as files.
Date: 2009-11-25 18:05:52 +0100 (Wed, 25 Nov 2009)
New Revision: 781
Clarify a comment about verification routine usage.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>
--- trunk/flashrom.c 2009-11-25 16:58:17 UTC (rev 780)
+++ trunk/flashrom.c 2009-11-25 17:05:52 UTC (rev 781)
@@ -407,7 +407,8 @@
- * @cmpbuf buffer to compare against
+ * @cmpbuf buffer to compare against, cmpbuf is expected to match the
+ flash content at location start
* @start offset to the base address of the flash chip
* @len length of the verified area
* @message string to print in the "FAILED" message