November 2009 - flashrom - mail.coreboot.org

erase failed on ASUS A8N-SLI Deluxe.
by Andreas Henriksson Dec. 15, 2009

Dec. 15, 2009

Hello everybody! I've been unsuccessful in updating by BIOS on my ASUS A8N-SLI Deluxe motherboard using flashrom. To my novice eyes it looks like the first 768kB has been erased and the rest left as is.... I'll put some information below.... http://paste.debian.net/50883/plain/50883 =================================================== $ sudo flashrom -w 1805.BIN flashrom v0.9.1-r736 No coreboot table found. Found chipset "NVIDIA CK804", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... ERASE FAILED at 0x00060000! Expected=0xff, Read=0xd4, failed byte count from 0x00060000-0x0006ffff: 0xacde ERASE FAILED! ERASE FAILED! ERASE FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net channel #flashrom or mail flashrom(a)flashrom.org ------------------------------------------------------------ DO NOT REBOOT OR POWEROFF! http://paste.debian.net/50884/plain/50884 =================================================== $ sudo flashrom -w backup-bios-1002.bin flashrom v0.9.1-r736 No coreboot table found. Found chipset "NVIDIA CK804", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... ERASE FAILED at 0x00060000! Expected=0xff, Read=0xd4, fail ed byte count from 0x00060000-0x0006ffff: 0xacde ERASE FAILED! ERASE FAILED! ERASE FAILED! ERASE FAILED! FAILED! Your flash chip is in an unknown state. Get help on IRC at irc.freenode.net channel #flashrom or mail flashrom(a)flashrom.org ------------------------------------------------------------ DO NOT REBOOT OR POWEROFF! http://paste.debian.net/50885/plain/50885 =================================================== $ sudo flashrom -v backup-bios-1002.bin flashrom v0.9.1-r736 No coreboot table found. Found chipset "NVIDIA CK804", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "SST SST49LF004A/B" (512 KB, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Verifying flash... VERIFY FAILED at 0x00000000! Expected=0x21, Read=0xff, failed byte count from 0x00000000-0x0007ffff: 0x3fac2 Quotes from IRC: =================================================== 14:42 < carldani> fatal^: AFAICS erase was partially successful. 14:47 < carldani> fatal^: the first 384k are erased. 14:48 < carldani> fatal^: ok, there are two things we can do. 14:49 < carldani> 1. we unlock the test of the chip and then rewrite in full 14:50 < carldani> 2. We only rewrite the erased part. 14:51 < carldani> fatal^: I'll tell you what we need to fix this. 14:53 < carldani> fatal^: Please send a mail with the exact board name (and board version, if your board exists in multiple versions), output of "lspci -nnvvvxxx" (as root), output of "flashrom -V" (as root), output of "superiotool -dV" (as root), and the output of "flashrom -EV" (as root) to flashrom(a)flashrom.org 14:54 < carldani> if you subscribe to that list before posting, your mail will be passed through immediately (otherwise it ends up in the moderator queue) 14:55 < carldani> and mention in the mail that erase partially fails. Requested information: =================================================== Exact board name: ASUS A8N-SLI Deluxe Versions: "Deluxe" is the "full" version, there are budget versions called "Premium" and maybe even more low-budget versions... lspci -nnvvvxxx: attached as "lspci-nnvvvxxx.txt" flashrom -V: attached as "flashrom-V.txt" superiotool -dV: attached as "superiotool-dV.txt" flashrom -EV: attached as "flashrom-EV.txt" Other files: ==================================================== Maybe to large to attach, so as long as I don't reboot you should be able to reach my computer at: http://fatal.se/tmp/bios/ "backup-bios-1002.bin" is what I got from "flashrom -r backup-bios-1002.bin" before I did anything else. "fucked-bios.bin" is what I currently get if I do "flashrom -r fucked-bios.bin" "1805.BIN" is the new bios I tried to update to. Thanks for your interest reading this far! :) -- Regards, Andreas Henriksson

3 2

[Patch] Board: Acorp 6A815EPD autodetectable (v2).
by Luc Verhaegen Dec. 14, 2009

Dec. 14, 2009

Hi Jonathan, I've swapped both id blocks around, so it could actually work this time :) Luc Verhaegen.

3 3

[patch] add intel_piix4_gpo_set()
by Luc Verhaegen Dec. 14, 2009

Dec. 14, 2009

This is code from a an old board enable that i sent in 3 weeks ago. This board enable was not necessary (as flashing worked just fine without it too). But this function was also used to clean up the board enable for the epox ep bx3. I have tracked down the person for whom i wrote this board enable 2 years ago: irc user nyu, aka Robert Millan. Robert, can you verify that this code is not a regression for you? Uwe, in the original mail thread (http://www.coreboot.org/pipermail/coreboot/2009-June/049789.html) you had several suggestions. I have taken over unsigned int and the bitshift, but i do mot like to put "PIIX4{,E,M}" everywhere. "PIIX4{,E,M}" all over clutters up the place, and i fear that printing this to the user will generate more confusion than it will ever remove. Instead i have adjusted the initial function comment to mention this so that developers can rest assured in future that this will also be valid for their future board enables. Luc Verhaegen.

3 9

[PATCH] Fix eraseblock walking
by Carl-Daniel Hailfinger Dec. 13, 2009

Dec. 13, 2009

Fix eraseblock walking and add a few more checks to make sure such bugs get caught in the future. I found this bug during a code review. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-blockerase_walk_fix/flashrom.c =================================================================== --- flashrom-blockerase_walk_fix/flashrom.c (Revision 769) +++ flashrom-blockerase_walk_fix/flashrom.c (Arbeitskopie) @@ -563,10 +563,11 @@ int erase_flash(struct flashchip *flash) { int i, j, k, ret = 0, found = 0; + unsigned int start, len; printf("Erasing flash chip... "); for (k = 0; k < NUM_ERASEFUNCTIONS; k++) { - unsigned long done = 0; + unsigned int done = 0; struct block_eraser eraser = flash->block_erasers[k]; printf_debug("Looking at blockwise erase function %i... ", k); @@ -594,13 +595,23 @@ * members so the loop below won't be executed for them. */ for (j = 0; j < eraser.eraseblocks[i].count; j++) { - ret = eraser.block_erase(flash, done + eraser.eraseblocks[i].size * j, eraser.eraseblocks[i].size); + start = done + eraser.eraseblocks[i].size * j; + len = eraser.eraseblocks[i].size; + printf_debug("0x%06x-0x%06x, ", start, len); + ret = eraser.block_erase(flash, start, len); if (ret) break; } if (ret) break; + done += eraser.eraseblocks[i].count * + eraser.eraseblocks[i].size; } + printf_debug("\n"); + if (done != flash->total_size * 1024) + fprintf(stderr, "ERROR: Erase region walking erased " + "0x%06x bytes total, expected 0x%06x bytes.", + done, flash->total_size * 1024); /* If everything is OK, don't try another erase function. */ if (!ret) break; -- Developer quote of the month: "We are juggling too many chainsaws and flaming arrows and tigers."

2 5

[Patch] Add board match for ASRock P4i65GV.
by Luc Verhaegen Dec. 13, 2009

Dec. 13, 2009

Idwer, please apply the ICH GPIO patch before applying this one. Thanks, Luc Verhaegen.

3 4

[Patch] Shuttle AK31
by Luc Verhaegen Dec. 13, 2009

Dec. 13, 2009

Resending this patch to the newly formed flashrom ml. Ron already kindly acked this patch. Mateusz, the owner of this board gave me a brief comment on irc stating that it didn't work. Which is also the last i heard from him. Mateusz, get back to us and get us at least the flashrom output. Luc Verhaegen.

3 6

[Patch] Yet another way of doing the intel ich gpio set.
by Luc Verhaegen Dec. 13, 2009

Dec. 13, 2009

After last night, i was disgusted to such an extent that i went and did this code that should meet all the (at least) logical demands made earlier. And to think that this started with adding 1 more simple board enable (http://www.flashrom.org/pipermail/flashrom/2009-October/000750.html) Some remarks here: * we do not care about the name of the intel ICH. ICH name was detected and mentioned before anyway. * we do not try to match a specific intel ICH in the board enable. That's what the big table was for to begin with. * This tiny 190 line function is entirely redone if we have a second io line that needs to be toggled. * dell poweredge: comment is useless, use the commit message. There might be a time when 50 boards might need exactly this gpio pin raised. * i might have messed up a bit or so in the gpio line checking masks, but cannot be bothered to go and trawl through everything yet again to verify this. Feel free to go and correct capitalisation. I'm off to do some real code on unichrome. Luc Verhaegen.

4 6

[PATCH] print.c fix - remove empty pcidevs header
by Adam Jurkowski Dec. 13, 2009

Dec. 13, 2009

Don't print out supported PCI devices header if all following lines are excluded from build. Signed-off-by: Adam Jurkowski <adam.jurkowski(a)kontron.pl> --- best regards, Adam Jurkowski

2 4

[PATCH] Make internal/onboard programmer support optional
by Carl-Daniel Hailfinger Dec. 13, 2009

Dec. 13, 2009

Internal (onboard) programming was the only feature which could not be disabled. Make various pieces of code conditional on support for internal programming. Code shared between PCI device programmers and onboard programming is now conditional as well. It is now possible to build only with dummy support: make CONFIG_INTERNAL=no CONFIG_NIC3COM=no CONFIG_SATASII=no CONFIG_DRKAISER=no CONFIG_SERPROG=no CONFIG_FT2232SPI=no This allows building for a specific use case only, and it also facilitates porting to a new architecture because it is possible to focus on highlevel code only. Note: Either internal or dummy programmer needs to be compiled in due to the current behaviour of always picking a default programmer if -p is not specified. Picking an arbitrary external programmer as default wouldn't make sense. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-programmer_internal_optional/flash.h =================================================================== --- flashrom-programmer_internal_optional/flash.h (Revision 768) +++ flashrom-programmer_internal_optional/flash.h (Arbeitskopie) @@ -30,7 +30,9 @@ #include <unistd.h> #include <stdint.h> #include <stdio.h> +#if NEED_PCI == 1 #include <pci/pci.h> +#endif /* for iopl and outb under Solaris */ #if defined (__sun) && (defined(__i386) || defined(__amd64)) @@ -81,7 +83,9 @@ typedef unsigned long chipaddr; enum programmer { +#if INTERNAL_SUPPORT == 1 PROGRAMMER_INTERNAL, +#endif #if DUMMY_SUPPORT == 1 PROGRAMMER_DUMMY, #endif @@ -97,7 +101,9 @@ #if SATASII_SUPPORT == 1 PROGRAMMER_SATASII, #endif +#if INTERNAL_SUPPORT == 1 PROGRAMMER_IT87SPI, +#endif #if FT2232_SPI_SUPPORT == 1 PROGRAMMER_FT2232SPI, #endif @@ -266,6 +272,7 @@ extern struct flashchip flashchips[]; +#if INTERNAL_SUPPORT == 1 struct penable { uint16_t vendor_id; uint16_t device_id; @@ -313,11 +320,13 @@ extern const struct board_info boards_bad[]; extern const struct board_info laptops_ok[]; extern const struct board_info laptops_bad[]; +#endif /* udelay.c */ void myusec_delay(int usecs); void myusec_calibrate_delay(void); +#if NEED_PCI == 1 /* pcidev.c */ #define PCI_OK 0 #define PCI_NT 1 /* Not tested */ @@ -335,11 +344,14 @@ }; uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar, struct pcidev_status *devs); uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar, struct pcidev_status *devs, char *pcidev_bdf); +#endif /* print.c */ char *flashbuses_to_text(enum chipbustype bustype); void print_supported(void); +#if NEED_PCI == 1 /* FIXME: This should be CONFIG_PCIDEV_PROGRAMMER */ void print_supported_pcidevs(struct pcidev_status *devs); +#endif void print_supported_wiki(void); /* board_enable.c */ @@ -350,20 +362,9 @@ void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask); int board_flash_enable(const char *vendor, const char *part); -struct decode_sizes { - uint32_t parallel; - uint32_t lpc; - uint32_t fwh; - uint32_t spi; -}; - /* chipset_enable.c */ -extern enum chipbustype buses_supported; int chipset_flash_enable(void); -extern struct decode_sizes max_rom_decode; -extern unsigned long flashbase; - /* physmap.c */ void *physmap(const char *descr, unsigned long phys_addr, size_t len); void physunmap(void *virt_addr, size_t len); @@ -386,13 +387,16 @@ #endif /* internal.c */ +#if NEED_PCI == 1 struct pci_dev *pci_dev_find_filter(struct pci_filter filter); struct pci_dev *pci_dev_find_vendorclass(uint16_t vendor, uint16_t class); struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device); struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device, uint16_t card_vendor, uint16_t card_device); +#endif void get_io_perms(void); void release_io_perms(void); +#if INTERNAL_SUPPORT == 1 int internal_init(void); int internal_shutdown(void); void internal_chip_writeb(uint8_t val, chipaddr addr); @@ -402,6 +406,7 @@ uint16_t internal_chip_readw(const chipaddr addr); uint32_t internal_chip_readl(const chipaddr addr); void internal_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); +#endif void mmio_writeb(uint8_t val, void *addr); void mmio_writew(uint16_t val, void *addr); void mmio_writel(uint32_t val, void *addr); @@ -425,6 +430,7 @@ #endif /* dummyflasher.c */ +#if DUMMY_SUPPORT == 1 int dummy_init(void); int dummy_shutdown(void); void *dummy_map(const char *descr, unsigned long phys_addr, size_t len); @@ -439,34 +445,43 @@ void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len); int dummy_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); +#endif /* nic3com.c */ +#if NIC3COM_SUPPORT == 1 int nic3com_init(void); int nic3com_shutdown(void); void nic3com_chip_writeb(uint8_t val, chipaddr addr); uint8_t nic3com_chip_readb(const chipaddr addr); extern struct pcidev_status nics_3com[]; +#endif /* gfxnvidia.c */ +#if GFXNVIDIA_SUPPORT == 1 int gfxnvidia_init(void); int gfxnvidia_shutdown(void); void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr); uint8_t gfxnvidia_chip_readb(const chipaddr addr); extern struct pcidev_status gfx_nvidia[]; +#endif /* drkaiser.c */ +#if DRKAISER_SUPPORT == 1 int drkaiser_init(void); int drkaiser_shutdown(void); void drkaiser_chip_writeb(uint8_t val, chipaddr addr); uint8_t drkaiser_chip_readb(const chipaddr addr); extern struct pcidev_status drkaiser_pcidev[]; +#endif /* satasii.c */ +#if SATASII_SUPPORT == 1 int satasii_init(void); int satasii_shutdown(void); void satasii_chip_writeb(uint8_t val, chipaddr addr); uint8_t satasii_chip_readb(const chipaddr addr); extern struct pcidev_status satas_sii[]; +#endif /* ft2232_spi.c */ #define FTDI_FT2232H 0x6010 @@ -485,7 +500,16 @@ int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf); /* flashrom.c */ +extern enum chipbustype buses_supported; +struct decode_sizes { + uint32_t parallel; + uint32_t lpc; + uint32_t fwh; + uint32_t spi; +}; +extern struct decode_sizes max_rom_decode; extern char *programmer_param; +extern unsigned long flashbase; extern int verbose; extern const char *flashrom_version; #define printf_debug(x...) { if (verbose) printf(x); } @@ -508,6 +532,7 @@ int handle_romentries(uint8_t *buffer, struct flashchip *flash); /* cbtable.c */ +void lb_vendor_dev_from_string(char *boardstring); int coreboot_init(void); extern char *lb_part, *lb_vendor; extern int partvendor_from_cbtable; @@ -515,12 +540,14 @@ /* spi.c */ enum spi_controller { SPI_CONTROLLER_NONE, +#if INTERNAL_SUPPORT == 1 SPI_CONTROLLER_ICH7, SPI_CONTROLLER_ICH9, SPI_CONTROLLER_IT87XX, SPI_CONTROLLER_SB600, SPI_CONTROLLER_VIA, SPI_CONTROLLER_WBSIO, +#endif #if FT2232_SPI_SUPPORT == 1 SPI_CONTROLLER_FT2232, #endif Index: flashrom-programmer_internal_optional/spi.c =================================================================== --- flashrom-programmer_internal_optional/spi.c (Revision 768) +++ flashrom-programmer_internal_optional/spi.c (Arbeitskopie) @@ -40,6 +40,7 @@ .write_256 = NULL, }, +#if INTERNAL_SUPPORT == 1 { /* SPI_CONTROLLER_ICH7 */ .command = ich_spi_send_command, .multicommand = ich_spi_send_multicommand, @@ -81,6 +82,7 @@ .read = wbsio_spi_read, .write_256 = wbsio_spi_write_1, }, +#endif #if FT2232_SPI_SUPPORT == 1 { /* SPI_CONTROLLER_FT2232 */ @@ -299,11 +301,13 @@ { /* only some SPI chipsets support 4 bytes commands */ switch (spi_controller) { +#if INTERNAL_SUPPORT == 1 case SPI_CONTROLLER_ICH7: case SPI_CONTROLLER_ICH9: case SPI_CONTROLLER_VIA: case SPI_CONTROLLER_SB600: case SPI_CONTROLLER_WBSIO: +#endif #if FT2232_SPI_SUPPORT == 1 case SPI_CONTROLLER_FT2232: #endif @@ -1030,10 +1034,12 @@ int result; switch (spi_controller) { +#if INTERNAL_SUPPORT == 1 case SPI_CONTROLLER_WBSIO: fprintf(stderr, "%s: impossible with Winbond SPI masters," " degrading to byte program\n", __func__); return spi_chip_write_1(flash, buf); +#endif default: break; } Index: flashrom-programmer_internal_optional/Makefile =================================================================== --- flashrom-programmer_internal_optional/Makefile (Revision 768) +++ flashrom-programmer_internal_optional/Makefile (Arbeitskopie) @@ -43,13 +43,11 @@ LIBS += -lpci -OBJS = chipset_enable.o board_enable.o udelay.o jedec.o stm50flw0x0x.o \ - sst28sf040.o am29f040b.o mx29f002.o m29f400bt.o pm29f002.o \ - w49f002u.o 82802ab.o pm49fl00x.o sst49lf040.o en29f002a.o \ - sst49lfxxxc.o sst_fwhub.o layout.o cbtable.o flashchips.o physmap.o \ - flashrom.o w39v080fa.o sharplhf00l04.o w29ee011.o spi.o it87spi.o \ - ichspi.o w39v040c.o sb600spi.o wbsio_spi.o m29f002.o internal.o \ - pcidev.o print.o +OBJS = jedec.o stm50flw0x0x.o w39v080fa.o sharplhf00l04.o w29ee011.o \ + sst28sf040.o am29f040b.o mx29f002.o m29f400bt.o pm29f002.o w39v040c.o \ + w49f002u.o 82802ab.o pm49fl00x.o sst49lf040.o en29f002a.o m29f002.o \ + sst49lfxxxc.o sst_fwhub.o flashchips.o layout.o spi.o \ + flashrom.o print.o physmap.o internal.o udelay.o all: pciutils features dep $(PROGRAM) @@ -65,6 +63,9 @@ SVNDEF := -D'FLASHROM_VERSION="$(VERSION)"' +# Always enable internal/onboard support for now. +CONFIG_INTERNAL ?= yes + # Always enable serprog for now. Needs to be disabled on Windows. CONFIG_SERPROG ?= yes @@ -92,6 +93,12 @@ # Disable wiki printing by default. It is only useful if you have wiki access. CONFIG_PRINT_WIKI ?= no +ifeq ($(CONFIG_INTERNAL), yes) +FEATURE_CFLAGS += -D'INTERNAL_SUPPORT=1' +OBJS += chipset_enable.o board_enable.o cbtable.o it87spi.o ichspi.o sb600spi.o wbsio_spi.o +NEED_PCI := yes +endif + ifeq ($(CONFIG_SERPROG), yes) FEATURE_CFLAGS += -D'SERPROG_SUPPORT=1' OBJS += serprog.o @@ -108,16 +115,19 @@ ifeq ($(CONFIG_NIC3COM), yes) FEATURE_CFLAGS += -D'NIC3COM_SUPPORT=1' OBJS += nic3com.o +NEED_PCI := yes endif ifeq ($(CONFIG_GFXNVIDIA), yes) FEATURE_CFLAGS += -D'GFXNVIDIA_SUPPORT=1' OBJS += gfxnvidia.o +NEED_PCI := yes endif ifeq ($(CONFIG_SATASII), yes) FEATURE_CFLAGS += -D'SATASII_SUPPORT=1' OBJS += satasii.o +NEED_PCI := yes endif FTDILIBS := $(shell pkg-config --libs libftdi 2>/dev/null || printf "%s" "-lftdi -lusb") @@ -136,8 +146,14 @@ ifeq ($(CONFIG_DRKAISER), yes) FEATURE_CFLAGS += -D'DRKAISER_SUPPORT=1' OBJS += drkaiser.o +NEED_PCI := yes endif +ifeq ($(NEED_PCI), yes) +FEATURE_CFLAGS += -D'NEED_PCI=1' +OBJS += pcidev.o +endif + ifeq ($(CONFIG_PRINT_WIKI), yes) FEATURE_CFLAGS += -D'PRINT_WIKI_SUPPORT=1' OBJS += print_wiki.o Index: flashrom-programmer_internal_optional/chipset_enable.c =================================================================== --- flashrom-programmer_internal_optional/chipset_enable.c (Revision 768) +++ flashrom-programmer_internal_optional/chipset_enable.c (Arbeitskopie) @@ -32,27 +32,6 @@ #include <fcntl.h> #include "flash.h" -unsigned long flashbase = 0; - -/** - * flashrom defaults to Parallel/LPC/FWH flash devices. If a known host - * controller is found, the init routine sets the buses_supported bitfield to - * contain the supported buses for that controller. - */ - -enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI; - -/** - * Programmers supporting multiple buses can have differing size limits on - * each bus. Store the limits for each bus in a common struct. - */ -struct decode_sizes max_rom_decode = { - .parallel = 0xffffffff, - .lpc = 0xffffffff, - .fwh = 0xffffffff, - .spi = 0xffffffff -}; - extern int ichspi_lock; static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) Index: flashrom-programmer_internal_optional/flashrom.c =================================================================== --- flashrom-programmer_internal_optional/flashrom.c (Revision 768) +++ flashrom-programmer_internal_optional/flashrom.c (Arbeitskopie) @@ -33,10 +33,38 @@ const char *flashrom_version = FLASHROM_VERSION; char *chip_to_probe = NULL; int verbose = 0; + +#if INTERNAL_SUPPORT == 1 enum programmer programmer = PROGRAMMER_INTERNAL; +#elif DUMMY_SUPPORT == 1 +enum programmer programmer = PROGRAMMER_DUMMY; +#else +/* Activating the #error explodes on make dep. */ +//#error Neither internal nor dummy selected +#endif + char *programmer_param = NULL; +/** + * flashrom defaults to Parallel/LPC/FWH flash devices. If a known host + * controller is found, the init routine sets the buses_supported bitfield to + * contain the supported buses for that controller. + */ +enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI; + +/** + * Programmers supporting multiple buses can have differing size limits on + * each bus. Store the limits for each bus in a common struct. + */ +struct decode_sizes max_rom_decode = { + .parallel = 0xffffffff, + .lpc = 0xffffffff, + .fwh = 0xffffffff, + .spi = 0xffffffff +}; + const struct programmer_entry programmer_table[] = { +#if INTERNAL_SUPPORT == 1 { .name = "internal", .init = internal_init, @@ -53,6 +81,7 @@ .chip_writen = fallback_chip_writen, .delay = internal_delay, }, +#endif #if DUMMY_SUPPORT == 1 { @@ -149,6 +178,7 @@ }, #endif +#if INTERNAL_SUPPORT == 1 { .name = "it87spi", .init = it87spi_init, @@ -165,6 +195,7 @@ .chip_writen = fallback_chip_writen, .delay = internal_delay, }, +#endif #if FT2232_SPI_SUPPORT == 1 { @@ -289,6 +320,8 @@ return 0; } +unsigned long flashbase = 0; + int min(int a, int b) { return (a < b) ? a : b; @@ -656,7 +689,9 @@ " -E | --erase: erase flash device\n" " -V | --verbose: more verbose output\n" " -c | --chip <chipname>: probe only for specified flash chip\n" +#if INTERNAL_SUPPORT == 1 " -m | --mainboard <[vendor:]part>: override mainboard settings\n" +#endif " -f | --force: force write without checking image\n" " -l | --layout <file.layout>: read ROM layout from file\n" " -i | --image <name>: only flash image name from flash layout\n" @@ -752,7 +787,7 @@ char *filename = NULL; - char *tempstr = NULL, *tempstr2 = NULL; + char *tempstr = NULL; print_version(); @@ -836,18 +871,12 @@ } erase_it = 1; break; +#if INTERNAL_SUPPORT == 1 case 'm': tempstr = strdup(optarg); - strtok(tempstr, ":"); - tempstr2 = strtok(NULL, ":"); - if (tempstr2) { - lb_vendor = tempstr; - lb_part = tempstr2; - } else { - lb_vendor = NULL; - lb_part = tempstr; - } + lb_vendor_dev_from_string(tempstr); break; +#endif case 'f': force = 1; break; @@ -1014,7 +1043,8 @@ "this flash part. Please include the flashrom\noutput " "with the additional -V option for all operations you " "tested (-V, -rV,\n-wV, -EV), and mention which " - "mainboard you tested. Thanks for your help!\n===\n"); + "mainboard or programmer you tested. Thanks for your " + "help!\n===\n"); } size = flash->total_size * 1024; @@ -1108,7 +1138,9 @@ } numbytes = fread(buf, 1, size, image); +#if INTERNAL_SUPPORT == 1 show_id(buf, size, force); +#endif fclose(image); if (numbytes != size) { fprintf(stderr, "Error: Failed to read file. Got %ld bytes, wanted %ld!\n", numbytes, size); Index: flashrom-programmer_internal_optional/internal.c =================================================================== --- flashrom-programmer_internal_optional/internal.c (Revision 768) +++ flashrom-programmer_internal_optional/internal.c (Arbeitskopie) @@ -31,6 +31,7 @@ int io_fd; #endif +#if NEED_PCI == 1 struct pci_dev *pci_dev_find_filter(struct pci_filter filter) { struct pci_dev *temp; @@ -99,6 +100,7 @@ return NULL; } +#endif void get_io_perms(void) { @@ -122,6 +124,7 @@ #endif } +#if INTERNAL_SUPPORT == 1 int internal_init(void) { int ret = 0; @@ -163,6 +166,7 @@ return 0; } +#endif void internal_chip_writeb(uint8_t val, chipaddr addr) { Index: flashrom-programmer_internal_optional/layout.c =================================================================== --- flashrom-programmer_internal_optional/layout.c (Revision 768) +++ flashrom-programmer_internal_optional/layout.c (Arbeitskopie) @@ -23,8 +23,10 @@ #include <ctype.h> #include "flash.h" +#if INTERNAL_SUPPORT == 1 char *mainboard_vendor = NULL; char *mainboard_part = NULL; +#endif int romimages = 0; #define MAX_ROMLAYOUT 16 @@ -38,6 +40,7 @@ romlayout_t rom_entries[MAX_ROMLAYOUT]; +#if INTERNAL_SUPPORT == 1 /* FIXME: Move the whole block to cbtable.c? */ static char *def_name = "DEFAULT"; int show_id(uint8_t *bios, int size, int force) @@ -126,6 +129,7 @@ return 0; } +#endif int read_romlayout(char *name) { Index: flashrom-programmer_internal_optional/cbtable.c =================================================================== --- flashrom-programmer_internal_optional/cbtable.c (Revision 768) +++ flashrom-programmer_internal_optional/cbtable.c (Arbeitskopie) @@ -30,6 +30,20 @@ char *lb_part = NULL, *lb_vendor = NULL; int partvendor_from_cbtable = 0; +void lb_vendor_dev_from_string(char *boardstring) +{ + char *tempstr2 = NULL; + strtok(boardstring, ":"); + tempstr2 = strtok(NULL, ":"); + if (tempstr2) { + lb_vendor = boardstring; + lb_part = tempstr2; + } else { + lb_vendor = NULL; + lb_part = boardstring; + } +} + static unsigned long compute_checksum(void *addr, unsigned long length) { uint8_t *ptr; Index: flashrom-programmer_internal_optional/print.c =================================================================== --- flashrom-programmer_internal_optional/print.c (Revision 768) +++ flashrom-programmer_internal_optional/print.c (Arbeitskopie) @@ -144,6 +144,7 @@ } } +#if INTERNAL_SUPPORT == 1 void print_supported_chipsets(void) { int i, j, chipsetcount = 0; @@ -221,12 +222,15 @@ print_supported_boards_helper(laptops_bad, "Laptops which have been verified to NOT work yet"); } +#endif void print_supported(void) { print_supported_chips(); +#if INTERNAL_SUPPORT == 1 print_supported_chipsets(); print_supported_boards(); +#endif printf("\nSupported PCI devices flashrom can use " "as programmer:\n\n"); #if NIC3COM_SUPPORT == 1 @@ -244,6 +248,7 @@ } +#if INTERNAL_SUPPORT == 1 /* Please keep this list alphabetically ordered by vendor/board. */ const struct board_info boards_ok[] = { /* Verified working boards that don't need write-enables. */ @@ -391,4 +396,5 @@ {}, }; +#endif -- Developer quote of the month: "We are juggling too many chainsaws and flaming arrows and tigers."

2 5

[PATCH] Add support for ASUS M2V-MX board
by David Bartley Dec. 8, 2009

Dec. 8, 2009

The way I figured this out was by picking the chip closest to the BIOS (the VT8237A southbridge) and inverting each of the GPIO lines one at a time. The GPIO stuff was gleaned from the VT8237R datasheet since I couldn't find the 'A one anywhere. All in all, a very fun and educating experience; next step, coreboot! On a related note, reading the flash back seems slightly broken; sometimes the read gets a few bytes wrong. -- David

5 16