flashrom October 2009

flashrom@flashrom.org

33 participants
92 discussions

[PATCH] Silence ICH preop debug message
by Carl-Daniel Hailfinger 22 Oct '09

22 Oct '09

Since we don't have any debug level printing infrastructure yet, I propose to kill the obnoxious debug message in ichspi.c which was added to check for correct PREOP handling. We know the code works fine (after getting a few reports over 100 MB long) and there's no point in keeping it around anymore. If there is any desire, we can reinstate it as print_spew or whatever once the debug level infrastructure is merged, but at that point we probably just are happy that the debug output isn't there anymore. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-ich_preop_silence/ichspi.c =================================================================== --- flashrom-ich_preop_silence/ichspi.c (Revision 752) +++ flashrom-ich_preop_silence/ichspi.c (Arbeitskopie) @@ -756,11 +756,8 @@ * opcode of the next command? */ if ((oppos != -1) && (preoppos != -1) && - (curopcodes->opcode[oppos].atomic - 1 == preoppos)) { - printf_debug("opcode 0x%02x will be run as PREOP\n", - cmds->writearr[0]); + (curopcodes->opcode[oppos].atomic - 1 == preoppos)) continue; - } } ret = ich_spi_send_command(cmds->writecnt, cmds->readcnt, -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers."

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[commit] r753 - trunk
by svn＠flashrom.org 22 Oct '09

22 Oct '09

Author: hailfinger Date: 2009-10-22 17:07:30 +0200 (Thu, 22 Oct 2009) New Revision: 753 Modified: trunk/ichspi.c Log: Since we don't have any debug level printing infrastructure yet, I propose to kill the obnoxious debug message in ichspi.c which was added to check for correct PREOP handling. We know the code works fine (after getting a few reports over 100 MB long) and there's no point in keeping it around anymore. If there is any desire, we can reinstate it as print_spew or whatever once the debug level infrastructure is merged, but at that point we probably just are happy that the debug output isn't there anymore. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Luc Verhaegen <libv(a)skynet.be> Modified: trunk/ichspi.c =================================================================== --- trunk/ichspi.c 2009-10-21 12:05:50 UTC (rev 752) +++ trunk/ichspi.c 2009-10-22 15:07:30 UTC (rev 753) @@ -756,11 +756,8 @@ * opcode of the next command? */ if ((oppos != -1) && (preoppos != -1) && - (curopcodes->opcode[oppos].atomic - 1 == preoppos)) { - printf_debug("opcode 0x%02x will be run as PREOP\n", - cmds->writearr[0]); + ((curopcodes->opcode[oppos].atomic - 1) == preoppos)) continue; - } } ret = ich_spi_send_command(cmds->writecnt, cmds->readcnt,

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bios flash succeeded on ASUS P5L-MX (untested flash part)
by Linda 22 Oct '09

22 Oct '09

Dear coreboot team, I just succesfully flashed my bios on a ASUS P5L-MX motherboard. flashrom detects two flash chips, SST25VF040B and SST25VF040B.REMS with the -c option I chose the first, without the -c option flashrom would not perform any action. I'd be happy to give more information if needed. Thanks for making this very nice tool :-) Kind regards Linda Polman 1. writing: 2. ======================================================================================== 3. 4. linda@tuxbox:~/LMX1103$ sudo flashrom -c SST25VF040B -wV LMX1103.ROM 5. flashrom v0.9.1-r706 6. No coreboot table found. 7. Found chipset "Intel ICH7/ICH7R", enabling flash write... 8. 0xfff80000/0xffb80000 FWH IDSEL: 0x0 9. 0xfff00000/0xffb00000 FWH IDSEL: 0x0 10. 0xffe80000/0xffa80000 FWH IDSEL: 0x1 11. 0xffe00000/0xffa00000 FWH IDSEL: 0x1 12. 0xffd80000/0xff980000 FWH IDSEL: 0x2 13. 0xffd00000/0xff900000 FWH IDSEL: 0x2 14. 0xffc80000/0xff880000 FWH IDSEL: 0x3 15. 0xffc00000/0xff800000 FWH IDSEL: 0x3 16. 0xff700000/0xff300000 FWH IDSEL: 0x4 17. 0xff600000/0xff200000 FWH IDSEL: 0x5 18. 0xff500000/0xff100000 FWH IDSEL: 0x6 19. 0xff400000/0xff000000 FWH IDSEL: 0x7 20. 0xfff80000/0xffb80000 FWH decode enabled 21. 0xfff00000/0xffb00000 FWH decode disabled 22. 0xffe80000/0xffa80000 FWH decode disabled 23. 0xffe00000/0xffa00000 FWH decode disabled 24. 0xffd80000/0xff980000 FWH decode disabled 25. 0xffd00000/0xff900000 FWH decode disabled 26. 0xffc80000/0xff880000 FWH decode disabled 27. 0xffc00000/0xff800000 FWH decode disabled 28. 0xff700000/0xff300000 FWH decode disabled 29. 0xff600000/0xff200000 FWH decode disabled 30. 0xff500000/0xff100000 FWH decode disabled 31. 0xff400000/0xff000000 FWH decode disabled 32. BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1 33. 34. Root Complex Register Block address = 0xfed1c000 35. GCS = 0x464: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) 36. Top Swap : not enabled 37. SPIBAR = 0xfed1c000 + 0x3020 38. 0x00: 0x0004 (SPIS) 39. 0x02: 0x4260 (SPIC) 40. 0x04: 0x00000000 (SPIA) 41. 0x08: 0xbf8d25bf (SPID0) 42. 0x0c: 0x00000000 (SPID0+4) 43. 0x10: 0x00000000 (SPID1) 44. 0x14: 0x0000471d (SPID1+4) 45. 0x18: 0x50120000 (SPID2) 46. 0x1c: 0x00495100 (SPID2+4) 47. 0x20: 0x00000100 (SPID3) 48. 0x24: 0x00000040 (SPID3+4) 49. 0x28: 0x30363041 (SPID4) 50. 0x2c: 0x30303035 (SPID4+4) 51. 0x30: 0x00000000 (SPID5) 52. 0x34: 0x00000000 (SPID5+4) 53. 0x38: 0x00ffaaea (SPID6) 54. 0x3c: 0x2f3830f0 (SPID6+4) 55. 0x40: 0x302f3532 (SPID7) 56. 0x44: 0x00fc0036 (SPID7+4) 57. 0x50: 0x00000000 (BBAR) 58. 0x54: 0x0006 (PREOP) 59. 0x56: 0x463b (OPTYPE) 60. 0x58: 0x05d80302 (OPMENU) 61. 0x5c: 0xc79f0190 (OPMENU+4) 62. 0x60: 0x00000000 (PBR0) 63. 0x64: 0x00000000 (PBR1) 64. 0x68: 0x00000000 (PBR2) 65. 0x6c: 0x00000000 (PBR3) 66. 67. Programming OPCODES... 68. program_opcodes: preop=0006 optype=463b opmenu=05d80302c79f0190 69. done 70. SPI Read Configuration: prefetching disabled, caching enabled, OK. 71. This chipset supports the following protocols: SPI. 72. Calibrating delay loop... 626M loops per second, 100 myus = 157 us. OK. 73. Probing for SST SST25VF040B, 512 KB: RDID returned 0xbf 0x25 0x8d. probe_spi_rdid_generic: id1 0xbf, id2 0x258d 74. Chip status register is 00 75. Chip status register: Block Protect Write Disable (BPL) is not set 76. Chip status register: Auto Address Increment Programming (AAI) is not set 77. Chip status register: Bit 5 / Block Protect 3 (BP3) is not set 78. Chip status register: Bit 4 / Block Protect 2 (BP2) is not set 79. Chip status register: Bit 3 / Block Protect 1 (BP1) is not set 80. Chip status register: Bit 2 / Block Protect 0 (BP0) is not set 81. Chip status register: Write Enable Latch (WEL) is not set 82. Chip status register: Write In Progress (WIP/BUSY) is not set 83. Resulting block protection : none 84. Found chip "SST SST25VF040B" (512 KB, SPI) at physical address 0xfff80000. 85. === 86. This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE 87. Please email a report to flashrom(a)flashrom.org if any of the above operations 88. work correctly for you with this flash part. Please include the flashrom 89. output with the additional -V option for all operations you tested (-V, -rV, 90. -wV, -EV), and mention which mainboard you tested. Thanks for your help! 91. === 92. Flash image seems to be a legacy BIOS. Disabling checks. 93. Writing flash chip... Erasing flash before programming... Invalid OPCODE 0x06 94. due to SPI master limitation, ignoring and hoping it will be run as PREOP 95. done. 96. Invalid OPCODE 0x06 97. due to SPI master limitation, ignoring and hoping it will be run as PREOP 98. Invalid OPCODE 0x06 99. due to SPI master limitation, ignoring and hoping it will be run as PREOP 100. Invalid OPCODE 0x06 101. due to SPI master limitation, ignoring and hoping it will be run as PREOP 102. Invalid OPCODE 0x06 103. due to SPI master limitation, ignoring and hoping it will be run as PREOP 104. Invalid OPCODE 0x06 105. due to SPI master limitation, ignoring and hoping it will be run as PREOP 106. Invalid OPCODE 0x06 107. due to SPI master limitation, ignoring and hoping it will be run as PREOP 108. Invalid OPCODE 0x06 109. due to SPI master limitation, ignoring and hoping it will be run as PREOP 110. Invalid OPCODE 0x06 111. due to SPI master limitation, ignoring and hoping it will be run as PREOP 112. Invalid OPCODE 0x06 113. due to SPI master limitation, ignoring and hoping it will be run as PREOP 114. 115. <few hundred times more the same error line> 116. 117. Invalid OPCODE 0x06 118. due to SPI master limitation, ignoring and hoping it will be run as PREOP 119. Invalid OPCODE 0x06 120. due to SPI master limitation, ignoring and hoping it will be run as PREOP 121. Invalid OPCODE 0x06 122. due to SPI master limitation, ignoring and hoping it will be run as PREOP 123. COMPLETE. 124. Verifying flash... VERIFIED. 125. 126. 127. 128. ====================================================================================== 129. Checking: 130. 131. linda@tuxbox:~/LMX1103$ sudo flashrom -c SST25VF040B -vV LMX1103.ROM 132. flashrom v0.9.1-r706 133. No coreboot table found. 134. Found chipset "Intel ICH7/ICH7R", enabling flash write... 135. 0xfff80000/0xffb80000 FWH IDSEL: 0x0 136. 0xfff00000/0xffb00000 FWH IDSEL: 0x0 137. 0xffe80000/0xffa80000 FWH IDSEL: 0x1 138. 0xffe00000/0xffa00000 FWH IDSEL: 0x1 139. 0xffd80000/0xff980000 FWH IDSEL: 0x2 140. 0xffd00000/0xff900000 FWH IDSEL: 0x2 141. 0xffc80000/0xff880000 FWH IDSEL: 0x3 142. 0xffc00000/0xff800000 FWH IDSEL: 0x3 143. 0xff700000/0xff300000 FWH IDSEL: 0x4 144. 0xff600000/0xff200000 FWH IDSEL: 0x5 145. 0xff500000/0xff100000 FWH IDSEL: 0x6 146. 0xff400000/0xff000000 FWH IDSEL: 0x7 147. 0xfff80000/0xffb80000 FWH decode enabled 148. 0xfff00000/0xffb00000 FWH decode disabled 149. 0xffe80000/0xffa80000 FWH decode disabled 150. 0xffe00000/0xffa00000 FWH decode disabled 151. 0xffd80000/0xff980000 FWH decode disabled 152. 0xffd00000/0xff900000 FWH decode disabled 153. 0xffc80000/0xff880000 FWH decode disabled 154. 0xffc00000/0xff800000 FWH decode disabled 155. 0xff700000/0xff300000 FWH decode disabled 156. 0xff600000/0xff200000 FWH decode disabled 157. 0xff500000/0xff100000 FWH decode disabled 158. 0xff400000/0xff000000 FWH decode disabled 159. BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1 160. 161. Root Complex Register Block address = 0xfed1c000 162. GCS = 0x464: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x1 (SPI) 163. Top Swap : not enabled 164. SPIBAR = 0xfed1c000 + 0x3020 165. 0x00: 0x0004 (SPIS) 166. 0x02: 0x7f10 (SPIC) 167. 0x04: 0x0007ffc0 (SPIA) 168. 0x08: 0x0000004d (SPID0) 169. 0x0c: 0x00000000 (SPID0+4) 170. 0x10: 0x00000000 (SPID1) 171. 0x14: 0x0000471d (SPID1+4) 172. 0x18: 0x50120000 (SPID2) 173. 0x1c: 0x00495100 (SPID2+4) 174. 0x20: 0x00000100 (SPID3) 175. 0x24: 0x00000040 (SPID3+4) 176. 0x28: 0x30363041 (SPID4) 177. 0x2c: 0x30303035 (SPID4+4) 178. 0x30: 0x00000000 (SPID5) 179. 0x34: 0x00000000 (SPID5+4) 180. 0x38: 0x00ffaaea (SPID6) 181. 0x3c: 0x2f3231f0 (SPID6+4) 182. 0x40: 0x302f3231 (SPID7) 183. 0x44: 0x00fc0037 (SPID7+4) 184. 0x50: 0x00000000 (BBAR) 185. 0x54: 0x0006 (PREOP) 186. 0x56: 0x463b (OPTYPE) 187. 0x58: 0x05d80302 (OPMENU) 188. 0x5c: 0xc79f0190 (OPMENU+4) 189. 0x60: 0x00000000 (PBR0) 190. 0x64: 0x00000000 (PBR1) 191. 0x68: 0x00000000 (PBR2) 192. 0x6c: 0x00000000 (PBR3) 193. 194. Programming OPCODES... 195. program_opcodes: preop=0006 optype=463b opmenu=05d80302c79f0190 196. done 197. SPI Read Configuration: prefetching disabled, caching enabled, OK. 198. This chipset supports the following protocols: SPI. 199. Calibrating delay loop... 784M loops per second, 100 myus = 197 us. OK. 200. Probing for SST SST25VF040B, 512 KB: RDID returned 0xbf 0x25 0x8d. probe_spi_rdid_generic: id1 0xbf, id2 0x258d 201. Chip status register is 00 202. Chip status register: Block Protect Write Disable (BPL) is not set 203. Chip status register: Auto Address Increment Programming (AAI) is not set 204. Chip status register: Bit 5 / Block Protect 3 (BP3) is not set 205. Chip status register: Bit 4 / Block Protect 2 (BP2) is not set 206. Chip status register: Bit 3 / Block Protect 1 (BP1) is not set 207. Chip status register: Bit 2 / Block Protect 0 (BP0) is not set 208. Chip status register: Write Enable Latch (WEL) is not set 209. Chip status register: Write In Progress (WIP/BUSY) is not set 210. Resulting block protection : none 211. Found chip "SST SST25VF040B" (512 KB, SPI) at physical address 0xfff80000. 212. === 213. This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE 214. Please email a report to flashrom(a)flashrom.org if any of the above operations 215. work correctly for you with this flash part. Please include the flashrom 216. output with the additional -V option for all operations you tested (-V, -rV, 217. -wV, -EV), and mention which mainboard you tested. Thanks for your help! 218. === 219. Flash image seems to be a legacy BIOS. Disabling checks. 220. Verifying flash... VERIFIED.

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lspci -vvnnxxx for Asrock P4i65GV
by Idwer Vollering 21 Oct '09

21 Oct '09

This pretty much is an attempt to save the board from this thread: http://www.coreboot.org/pipermail/flashrom/2009-October/thread.html#775 --- Sending a lspci -vvnnxxx, as requested by libv on irc. Board: http://www.asrock.com/MB/overview.asp?Model=P4i65GV lspci -vvnnxxx: 00:00.0 Host bridge [0600]: Intel Corporation 82865G/PE/P DRAM Controller/Host-Hub Interface [8086:2570] (rev 02) Subsystem: ASRock Incorporation Device [1849:2570] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx- Latency: 0 Region 0: Memory at fe800000 (32-bit, prefetchable) [size=4M] Capabilities: [e4] Vendor Specific Information <?> Kernel driver in use: agpgart-intel Kernel modules: intel-agp 00: 86 80 70 25 06 00 90 20 02 00 00 06 00 00 00 00 10: 08 00 80 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 49 18 70 25 30: 00 00 00 00 e4 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 34 00 40 80 1c 00 00 00 00 00 00 00 00 00 60: 00 05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 10 11 01 00 00 33 33 00 00 00 00 00 00 0a 38 00 a0: 02 00 30 00 17 42 00 1f 00 00 00 00 00 00 00 00 b0: 00 00 00 00 3f 00 00 00 00 00 00 00 20 10 00 00 c0: 00 00 00 00 80 1f 0e 20 00 01 00 00 00 00 00 00 d0: 02 28 04 0e 0b 0d 00 00 00 00 00 00 00 00 40 01 e0: 00 00 00 00 09 00 06 11 00 02 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 68 0f 03 00 00 00 00 00 00:02.0 VGA compatible controller [0300]: Intel Corporation 82865G Integrated Graphics Controller [8086:2572] (rev 02) Subsystem: ASRock Incorporation Device [1849:2572] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 16 Region 0: Memory at f0000000 (32-bit, prefetchable) [size=128M] Region 1: Memory at fe780000 (32-bit, non-prefetchable) [size=512K] Region 2: I/O ports at ec00 [size=8] Capabilities: [d0] Power Management version 1 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel modules: intelfb 00: 86 80 72 25 07 00 90 00 02 00 00 03 00 00 00 00 10: 08 00 00 f0 00 00 78 fe 01 ec 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 49 18 72 25 30: 00 00 00 00 d0 00 00 00 00 00 00 00 0a 01 00 00 40: 00 00 00 00 e0 23 e0 11 00 00 00 00 00 00 00 00 50: 00 00 34 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 01 00 00 00 00 00 01 02 ff 00 00 00 71 02 10 20 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 51 ff ff 51 ff ff 00 00 b0: 02 04 00 00 44 00 00 00 d5 1b ff 9f 7b 40 59 00 c0: 00 00 00 00 80 1f 0e 20 00 00 00 00 00 00 00 00 d0: 01 00 21 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 01 00 00 00 09 00 06 11 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 68 0f 03 00 00 00 00 00 00:1d.0 USB Controller [0c03]: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #1 [8086:24d2] (rev 02) Subsystem: ASRock Incorporation Device [1849:24d0] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 16 Region 4: I/O ports at dc00 [size=32] Kernel driver in use: uhci_hcd 00: 86 80 d2 24 05 00 80 02 02 00 03 0c 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 dc 00 00 00 00 00 00 00 00 00 00 49 18 d0 24 30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 66 0f 05 00 00 00 00 00 00:1d.1 USB Controller [0c03]: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #2 [8086:24d4] (rev 02) Subsystem: ASRock Incorporation Device [1849:24d0] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 19 Region 4: I/O ports at e000 [size=32] Kernel driver in use: uhci_hcd 00: 86 80 d4 24 05 00 80 02 02 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 e0 00 00 00 00 00 00 00 00 00 00 49 18 d0 24 30: 00 00 00 00 00 00 00 00 00 00 00 00 06 02 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 66 0f 05 00 00 00 00 00 00:1d.2 USB Controller [0c03]: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #3 [8086:24d7] (rev 02) Subsystem: ASRock Incorporation Device [1849:24d0] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin C routed to IRQ 18 Region 4: I/O ports at e400 [size=32] Kernel driver in use: uhci_hcd 00: 86 80 d7 24 05 00 80 02 02 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 e4 00 00 00 00 00 00 00 00 00 00 49 18 d0 24 30: 00 00 00 00 00 00 00 00 00 00 00 00 05 03 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 66 0f 05 00 00 00 00 00 00:1d.3 USB Controller [0c03]: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #4 [8086:24de] (rev 02) Subsystem: ASRock Incorporation Device [1849:24d0] Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 16 Region 4: I/O ports at e800 [size=32] Kernel driver in use: uhci_hcd 00: 86 80 de 24 05 00 80 02 02 00 03 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 e8 00 00 00 00 00 00 00 00 00 00 49 18 d0 24 30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 2f 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 66 0f 05 00 00 00 00 00 00:1d.7 USB Controller [0c03]: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB2 EHCI Controller [8086:24dd] (rev 02) (prog-if 20) Subsystem: ASRock Incorporation Device [1849:24d0] Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin D routed to IRQ 23 Region 0: Memory at fe77bc00 (32-bit, non-prefetchable) [size=1K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Capabilities: [58] Debug port: BAR=1 offset=00a0 Kernel driver in use: ehci_hcd 00: 86 80 dd 24 06 01 90 02 02 20 03 0c 00 00 00 00 10: 00 bc 77 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 49 18 d0 24 30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 04 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 58 c2 c9 00 00 00 00 0a 00 a0 20 00 00 00 00 60: 20 20 ff 01 00 00 00 00 01 00 00 00 00 00 08 c0 70: 00 00 dd 3f 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 55 55 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 80 00 00 88 83 40 00 66 0f 05 00 06 14 00 00 00:1e.0 PCI bridge [0604]: Intel Corporation 82801 PCI Bridge [8086:244e] (rev c2) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=32 I/O behind bridge: 0000b000-0000bfff Memory behind bridge: fe500000-fe5fffff Prefetchable memory behind bridge: 20000000-200fffff Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Kernel modules: shpchp 00: 86 80 4e 24 07 01 80 00 c2 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 20 b0 b0 80 02 20: 50 fe 50 fe 00 20 00 20 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 06 00 40: 02 28 30 76 00 00 00 00 00 00 00 00 00 00 00 00 50: 02 64 73 00 00 00 00 00 50 01 34 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 01 00 02 00 00 00 c0 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 66 0f 05 00 00 00 53 31 00:1f.0 ISA bridge [0601]: Intel Corporation 82801EB/ER (ICH5/ICH5R) LPC Interface Bridge [8086:24d0] (rev 02) Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Kernel modules: iTCO_wdt, intel-rng 00: 86 80 d0 24 0f 00 80 02 02 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 08 00 00 10 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 81 04 00 00 10 00 00 00 60: 8a 8a 85 86 d0 00 00 00 8a 80 8a 8b 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: ff fc 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 20 02 00 00 39 00 00 00 0d 00 00 00 00 03 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 02 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 86 21 02 00 02 00 00 00 04 00 00 00 00 00 00 00 e0: 00 00 00 80 00 00 08 14 33 22 11 00 00 00 67 45 f0: 00 00 44 00 04 00 00 00 66 0f 05 3e 00 00 00 00 00:1f.1 IDE interface [0101]: Intel Corporation 82801EB/ER (ICH5/ICH5R) IDE Controller [8086:24db] (rev 02) (prog-if 8a [Master SecP PriP]) Subsystem: ASRock Incorporation Device [1849:24d0] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 18 Region 0: I/O ports at 01f0 [size=8] Region 1: I/O ports at 03f4 [size=1] Region 2: I/O ports at 0170 [size=8] Region 3: I/O ports at 0374 [size=1] Region 4: I/O ports at fc00 [size=16] Region 5: Memory at 20100000 (32-bit, non-prefetchable) [size=1K] Kernel driver in use: ata_piix 00: 86 80 db 24 07 00 80 02 02 8a 01 01 00 00 00 00 10: 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 20: 01 fc 00 00 00 00 10 20 00 00 00 00 49 18 d0 24 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40: 07 e3 37 e3 b0 00 00 00 0d 00 01 22 00 00 00 00 50: 00 00 00 00 30 10 00 00 00 00 00 00 00 00 00 00 60: 08 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 66 0f 05 00 00 00 00 00 00:1f.3 SMBus [0c05]: Intel Corporation 82801EB/ER (ICH5/ICH5R) SMBus Controller [8086:24d3] (rev 02) Subsystem: ASRock Incorporation Device [1849:24d0] Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Interrupt: pin B routed to IRQ 10 Region 4: I/O ports at 0400 [size=32] Kernel modules: i2c-i801 00: 86 80 d3 24 01 00 80 02 02 00 05 0c 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 01 04 00 00 00 00 00 00 00 00 00 00 49 18 d0 24 30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 02 00 00 40: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 66 0f 05 00 00 00 00 00 00:1f.5 Multimedia audio controller [0401]: Intel Corporation 82801EB/ER (ICH5/ICH5R) AC'97 Audio Controller [8086:24d5] (rev 02) Subsystem: ASRock Incorporation Device [1849:9739] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin B routed to IRQ 17 Region 0: I/O ports at d800 [size=256] Region 1: I/O ports at d400 [size=64] Region 2: Memory at fe77b800 (32-bit, non-prefetchable) [size=512] Region 3: Memory at fe77b400 (32-bit, non-prefetchable) [size=256] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: Intel ICH Kernel modules: snd-intel8x0 00: 86 80 d5 24 07 00 90 02 02 00 01 04 00 00 00 00 10: 01 d8 00 00 01 d4 00 00 00 b8 77 fe 00 b4 77 fe 20: 00 00 00 00 00 00 00 00 00 00 00 00 49 18 39 97 30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 02 00 00 40: 09 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 00 c2 c9 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 66 0f 05 00 00 00 00 00 01:03.0 Ethernet controller [0200]: Intel Corporation 82541PI Gigabit Ethernet Controller [8086:107c] (rev 05) Subsystem: Intel Corporation Device [8086:1376] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (63750ns min), Cache Line Size: 32 bytes Interrupt: pin A routed to IRQ 20 Region 0: Memory at fe5e0000 (32-bit, non-prefetchable) [size=128K] Region 1: Memory at fe5c0000 (32-bit, non-prefetchable) [size=128K] Region 2: I/O ports at bc00 [size=64] Expansion ROM at 20000000 [disabled] [size=128K] Capabilities: [dc] Power Management version 2 Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=1 PME- Capabilities: [e4] PCI-X non-bridge device Command: DPERE- ERO+ RBC=512 OST=1 Status: Dev=00:00.0 64bit- 133MHz- SCD- USC- DC=simple DMMRBC=2048 DMOST=1 DMCRS=8 RSCEM- 266MHz- 533MHz- Kernel driver in use: e1000 Kernel modules: e1000 00: 86 80 7c 10 17 00 30 02 05 00 00 02 08 20 00 00 10: 00 00 5e fe 00 00 5c fe 01 bc 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 76 13 30: 00 00 fe ff dc 00 00 00 00 00 00 00 0a 01 ff 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 e4 22 c8 e0: 00 20 00 28 07 00 02 00 00 00 40 00 00 00 00 00 f0: 05 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 01:05.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ [10ec:8139] (rev 10) Subsystem: ASRock Incorporation Device [1849:8139] Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 32 (8000ns min, 16000ns max) Interrupt: pin A routed to IRQ 22 Region 0: I/O ports at b800 [size=256] Region 1: Memory at fe5bfc00 (32-bit, non-prefetchable) [size=256] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold+) Status: D0 PME-Enable- DSel=0 DScale=0 PME- Kernel driver in use: 8139too Kernel modules: 8139too, 8139cp 00: ec 10 39 81 07 00 90 02 10 00 00 02 00 20 00 00 10: 01 b8 00 00 00 fc 5b fe 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 49 18 39 81 30: 00 00 00 00 50 00 00 00 00 00 00 00 0a 01 20 40 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 00 c2 f7 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

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Re: [flashrom] [Patch] Board enable for Shuttle FN25 (SN25P).
by Luc Verhaegen 21 Oct '09

21 Oct '09

On Sat, Oct 10, 2009 at 09:31:17PM -0300, Ulf Mehlig wrote: > Acked-by: Ulf Mehlig <ulf(a)ufpa.br> > > rebooting worked, also after re-flashing with the latest BIOS from > Shuttles Website; the ethernet address was preserved on reboot. > > Seems to be everything ok, then. > > Thanks again! Ulf > > On Wed, 2009-09-23 at 10:26 -0300, Luc Verhaegen wrote: > > On Wed, Sep 23, 2009 at 10:14:47AM -0300, Ulf Mehlig wrote: > > > Thanks for the patch, and many thanks again for helping me out > > > yesterday! > > > > > > All the best, Ulf > > > > > > > Does it work? If so, reply with: Acked-by: Ulf Mehlig <ulf(a)ufpa.br> > > so that it can be committed. > > > > Also, carldani is about to send in a patch for your bios chip, i am not > > sure how to test this, but he can explain this. > > > > Luc Verhaegen. Thanks: -> r752. Luc Verhaegen.

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[commit] r752 - trunk
by svn＠flashrom.org 21 Oct '09

21 Oct '09

Author: libv Date: 2009-10-21 14:05:50 +0200 (Wed, 21 Oct 2009) New Revision: 752 Modified: trunk/board_enable.c Log: Board enable for Shuttle FN25 (SN25P). Shuttle SFF PC is SN25P, board FN25, AMD socket 939 with an nForce4 chipset. Config register 0x92 on the ISA bridge needs to be cleared for TBL# to be raised. No information about individual bits of this register is currently available. Signed-off-by: Luc Verhaegen <libv(a)skynet.be> Acked-by: Ulf Mehlig <ulf(a)ufpa.br> Modified: trunk/board_enable.c =================================================================== --- trunk/board_enable.c 2009-10-19 18:15:36 UTC (rev 751) +++ trunk/board_enable.c 2009-10-21 12:05:50 UTC (rev 752) @@ -400,6 +400,26 @@ } /** + * Suited for Shuttle FN25 (SN25P): AMD S939 + Nvidia CK804 (nForce4). + */ +static int board_shuttle_fn25(const char *name) +{ + struct pci_dev *dev; + + dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA Bridge. */ + if (!dev) { + fprintf(stderr, + "\nERROR: NVIDIA nForce4 ISA bridge not found.\n"); + return -1; + } + + /* one of those bits seems to be connected to TBL#, but -ENOINFO. */ + pci_write_byte(dev, 0x92, 0); + + return 0; +} + +/** * No docs, so we are just guessing that these might be individual gpio lines. */ static void nvidia_mcp_gpio_raise(struct pci_dev *dev, uint8_t offset) @@ -1086,6 +1106,7 @@ {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", ich6_gpio19_raise}, {0x10de, 0x005e, 0, 0, 0, 0, 0, 0, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", w83627thf_gpio4_4_raise_4e}, {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", it8705f_write_enable_2e}, + {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, "Shuttle", "FN25", board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, "Soyo", "SY-7VCA", board_soyo_sy_7vca}, {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", board_asus_a7v8x_mx}, {0x1106, 0x0314, 0x1106, 0xaa08, 0x1106, 0x3227, 0x1106, 0xAA08, NULL, NULL, "VIA", "EPIA-CN", board_via_epia_sp},

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[commit] r751 - trunk
by svn＠flashrom.org 19 Oct '09

19 Oct '09

Author: hailfinger Date: 2009-10-19 20:15:36 +0200 (Mon, 19 Oct 2009) New Revision: 751 Modified: trunk/jedec.c Log: Remove confusing out-of-date comment. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/jedec.c =================================================================== --- trunk/jedec.c 2009-10-06 20:25:48 UTC (rev 750) +++ trunk/jedec.c 2009-10-19 18:15:36 UTC (rev 751) @@ -114,9 +114,6 @@ chip_writeb(0x55, bios + 0x2AAA); programmer_delay(10); chip_writeb(0x90, bios + 0x5555); - /* Older chips may need up to 100 us to respond. The ATMEL 29C020 - * needs 10 ms according to the data sheet. - */ programmer_delay(probe_timing_enter); /* Read product ID */

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Re: [flashrom] Winbond W25X16 successful programming
by Maurizio Cavalli 19 Oct '09

19 Oct '09

Hi. I downloaded the latest snapshot of flashrom as you suggested, and you will find the new log in the attached file. There is yet a lot of "opcode 0x06 will be run as PREOP" lines: I deleted all of them but the first sequences. If you need them, let me known. I can rerun the program anytime, and if this little job can help you, I will do it. About the code for the PentiumM/82855GME: I'm sorry, but I have nothing to submit. Is was a my personal attempt to port linuxbios, but the activity was (too soon ?) stopped. The development tree was moved into the "old things limbo", from where it was deleted by a mistyped answer during disk maintenance. Anyway, thanks. Regards Maurizio Cavalli Sviluppo Software CONTROL SYSTEMS S.r.l. Via del Brolo, 14 26100 CREMONA (Italy) tel +39 0372 471806 fax +39 0372 471823 www.controlsystems-srl.it -----Original Message----- From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006@gmx.net] Sent: Fri 10/16/2009 12:45 PM To: Maurizio Cavalli Cc: flashrom(a)flashrom.org Subject: Re: [flashrom] Winbond W25X16 successful programming Hi Maurizio, thank you for your report. I will add your chip to the supported list. On 16.10.2009 10:03, Maurizio Cavalli wrote: > I had successfully programmed a Winbond W25X16(BVSSIG) chip with flashrom. > > Board: ROE RIVER Evaluation Board from Intel > (Reference: Intel® AtomTM Processor N270 and Mobile Intel® 945GSE Express Chipset Development Kit User's Manual - Document number: 320436-002) > BIOS: Phoenix Embedded BIOS(R) w/StrongFrame(R) Technology. > Kernel: Linux 2.6.30.2 SMP, compiled from source tree > Host system: Debian 5.0 > The log of your flashrom version had thousands of lines like this: Invalid OPCODE 0x06 due to SPI master limitation, ignoring and hoping it will be run as PREOP I have removed them from your log to make the mail smaller. It would be great if you could test erase and write with the latest flashrom from svn as well. The invalid opcode messages should have disappeared. > (I apologize we cannot use coreboot because lack of chipsets documentation from Intel. We already tried to port linuxBios onto a PentiumM/82855GME platform, but we failed in setting up the integrated graphic controller) > Oh, that is interesting. So you do already have some code, but it is not working yet? Could you please send that code to the coreboot mailing list <coreboot(a)coreboot.org> so other developers can have a look. Maybe someone has good docs for that platform. Regards, Carl-Daniel -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers."

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Flashrom MSI KT4V support.
by Luc Verhaegen 17 Oct '09

17 Oct '09

Hi Sean, I have some questions about your kt4v/kt4ultra board enable: 1) I am about to move some code from many vt823x based board enables to the chipset enable. Your board enable has some "similar" code, but not quite, and it now forms the only anomaly. Can you send me the output of: dd if=/dev/mem of=/tmp/kt4v_system.rom bs=64k count=1 skip=15 so i can have a dig through the top segment of your AMI BIOS to verify this code? 2) I am about to tighten up the board enable matching table. * both the coreboot ids will disappear. * we need a second set for the kt4v. Can you send in lspci -vvnnxxx on both boards? Thanks, Luc Verhaegen.

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Re: [flashrom] Winbond W25X16 successful programming
by Carl-Daniel Hailfinger 16 Oct '09

16 Oct '09

Hi Maurizio, thank you for your report. I will add your chip to the supported list. On 16.10.2009 10:03, Maurizio Cavalli wrote: > I had successfully programmed a Winbond W25X16(BVSSIG) chip with flashrom. > > Board: ROE RIVER Evaluation Board from Intel > (Reference: Intel® AtomTM Processor N270 and Mobile Intel® 945GSE Express Chipset Development Kit User’s Manual - Document number: 320436-002) > BIOS: Phoenix Embedded BIOS(R) w/StrongFrame(R) Technology. > Kernel: Linux 2.6.30.2 SMP, compiled from source tree > Host system: Debian 5.0 > The log of your flashrom version had thousands of lines like this: Invalid OPCODE 0x06 due to SPI master limitation, ignoring and hoping it will be run as PREOP I have removed them from your log to make the mail smaller. It would be great if you could test erase and write with the latest flashrom from svn as well. The invalid opcode messages should have disappeared. > (I apologize we cannot use coreboot because lack of chipsets documentation from Intel. We already tried to port linuxBios onto a PentiumM/82855GME platform, but we failed in setting up the integrated graphic controller) > Oh, that is interesting. So you do already have some code, but it is not working yet? Could you please send that code to the coreboot mailing list <coreboot(a)coreboot.org> so other developers can have a look. Maybe someone has good docs for that platform. Regards, Carl-Daniel -- Developer quote of the week: "We are juggling too many chainsaws and flaming arrows and tigers."

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