Since we don't have any debug level printing infrastructure yet, I
propose to kill the obnoxious debug message in ichspi.c which was added
to check for correct PREOP handling. We know the code works fine (after
getting a few reports over 100 MB long) and there's no point in keeping
it around anymore.
If there is any desire, we can reinstate it as print_spew or whatever
once the debug level infrastructure is merged, but at that point we
probably just are happy that the debug output isn't there anymore.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>
Index: flashrom-ich_preop_silence/ichspi.c
===================================================================
--- flashrom-ich_preop_silence/ichspi.c (Revision 752)
+++ flashrom-ich_preop_silence/ichspi.c (Arbeitskopie)
@@ -756,11 +756,8 @@
* opcode of the next command?
*/
if ((oppos != -1) && (preoppos != -1) &&
- (curopcodes->opcode[oppos].atomic - 1 == preoppos)) {
- printf_debug("opcode 0x%02x will be run as PREOP\n",
- cmds->writearr[0]);
+ (curopcodes->opcode[oppos].atomic - 1 == preoppos))
continue;
- }
}
ret = ich_spi_send_command(cmds->writecnt, cmds->readcnt,
--
Developer quote of the week:
"We are juggling too many chainsaws and flaming arrows and tigers."
Author: hailfinger
Date: 2009-10-22 17:07:30 +0200 (Thu, 22 Oct 2009)
New Revision: 753
Modified:
trunk/ichspi.c
Log:
Since we don't have any debug level printing infrastructure yet, I
propose to kill the obnoxious debug message in ichspi.c which was added
to check for correct PREOP handling. We know the code works fine (after
getting a few reports over 100 MB long) and there's no point in keeping
it around anymore.
If there is any desire, we can reinstate it as print_spew or whatever
once the debug level infrastructure is merged, but at that point we
probably just are happy that the debug output isn't there anymore.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net>
Acked-by: Luc Verhaegen <libv(a)skynet.be>
Modified: trunk/ichspi.c
===================================================================
--- trunk/ichspi.c 2009-10-21 12:05:50 UTC (rev 752)
+++ trunk/ichspi.c 2009-10-22 15:07:30 UTC (rev 753)
@@ -756,11 +756,8 @@
* opcode of the next command?
*/
if ((oppos != -1) && (preoppos != -1) &&
- (curopcodes->opcode[oppos].atomic - 1 == preoppos)) {
- printf_debug("opcode 0x%02x will be run as PREOP\n",
- cmds->writearr[0]);
+ ((curopcodes->opcode[oppos].atomic - 1) == preoppos))
continue;
- }
}
ret = ich_spi_send_command(cmds->writecnt, cmds->readcnt,
Dear coreboot team,
I just succesfully flashed my bios on a ASUS P5L-MX motherboard.
flashrom detects two flash chips, SST25VF040B and SST25VF040B.REMS
with the -c option I chose the first, without the -c option flashrom would
not perform any action.
I'd be happy to give more information if needed.
Thanks for making this very nice tool :-)
Kind regards
Linda Polman
1. writing:
2.
========================================================================================
3.
4. linda@tuxbox:~/LMX1103$ sudo flashrom -c SST25VF040B -wV LMX1103.ROM
5. flashrom v0.9.1-r706
6. No coreboot table found.
7. Found chipset "Intel ICH7/ICH7R", enabling flash write...
8. 0xfff80000/0xffb80000 FWH IDSEL: 0x0
9. 0xfff00000/0xffb00000 FWH IDSEL: 0x0
10. 0xffe80000/0xffa80000 FWH IDSEL: 0x1
11. 0xffe00000/0xffa00000 FWH IDSEL: 0x1
12. 0xffd80000/0xff980000 FWH IDSEL: 0x2
13. 0xffd00000/0xff900000 FWH IDSEL: 0x2
14. 0xffc80000/0xff880000 FWH IDSEL: 0x3
15. 0xffc00000/0xff800000 FWH IDSEL: 0x3
16. 0xff700000/0xff300000 FWH IDSEL: 0x4
17. 0xff600000/0xff200000 FWH IDSEL: 0x5
18. 0xff500000/0xff100000 FWH IDSEL: 0x6
19. 0xff400000/0xff000000 FWH IDSEL: 0x7
20. 0xfff80000/0xffb80000 FWH decode enabled
21. 0xfff00000/0xffb00000 FWH decode disabled
22. 0xffe80000/0xffa80000 FWH decode disabled
23. 0xffe00000/0xffa00000 FWH decode disabled
24. 0xffd80000/0xff980000 FWH decode disabled
25. 0xffd00000/0xff900000 FWH decode disabled
26. 0xffc80000/0xff880000 FWH decode disabled
27. 0xffc00000/0xff800000 FWH decode disabled
28. 0xff700000/0xff300000 FWH decode disabled
29. 0xff600000/0xff200000 FWH decode disabled
30. 0xff500000/0xff100000 FWH decode disabled
31. 0xff400000/0xff000000 FWH decode disabled
32. BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is
0x1
33.
34. Root Complex Register Block address = 0xfed1c000
35. GCS = 0x464: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps:
0x1 (SPI)
36. Top Swap : not enabled
37. SPIBAR = 0xfed1c000 + 0x3020
38. 0x00: 0x0004 (SPIS)
39. 0x02: 0x4260 (SPIC)
40. 0x04: 0x00000000 (SPIA)
41. 0x08: 0xbf8d25bf (SPID0)
42. 0x0c: 0x00000000 (SPID0+4)
43. 0x10: 0x00000000 (SPID1)
44. 0x14: 0x0000471d (SPID1+4)
45. 0x18: 0x50120000 (SPID2)
46. 0x1c: 0x00495100 (SPID2+4)
47. 0x20: 0x00000100 (SPID3)
48. 0x24: 0x00000040 (SPID3+4)
49. 0x28: 0x30363041 (SPID4)
50. 0x2c: 0x30303035 (SPID4+4)
51. 0x30: 0x00000000 (SPID5)
52. 0x34: 0x00000000 (SPID5+4)
53. 0x38: 0x00ffaaea (SPID6)
54. 0x3c: 0x2f3830f0 (SPID6+4)
55. 0x40: 0x302f3532 (SPID7)
56. 0x44: 0x00fc0036 (SPID7+4)
57. 0x50: 0x00000000 (BBAR)
58. 0x54: 0x0006 (PREOP)
59. 0x56: 0x463b (OPTYPE)
60. 0x58: 0x05d80302 (OPMENU)
61. 0x5c: 0xc79f0190 (OPMENU+4)
62. 0x60: 0x00000000 (PBR0)
63. 0x64: 0x00000000 (PBR1)
64. 0x68: 0x00000000 (PBR2)
65. 0x6c: 0x00000000 (PBR3)
66.
67. Programming OPCODES...
68. program_opcodes: preop=0006 optype=463b opmenu=05d80302c79f0190
69. done
70. SPI Read Configuration: prefetching disabled, caching enabled, OK.
71. This chipset supports the following protocols: SPI.
72. Calibrating delay loop... 626M loops per second, 100 myus = 157 us.
OK.
73. Probing for SST SST25VF040B, 512 KB: RDID returned 0xbf 0x25 0x8d.
probe_spi_rdid_generic: id1 0xbf, id2 0x258d
74. Chip status register is 00
75. Chip status register: Block Protect Write Disable (BPL) is not set
76. Chip status register: Auto Address Increment Programming (AAI) is not
set
77. Chip status register: Bit 5 / Block Protect 3 (BP3) is not set
78. Chip status register: Bit 4 / Block Protect 2 (BP2) is not set
79. Chip status register: Bit 3 / Block Protect 1 (BP1) is not set
80. Chip status register: Bit 2 / Block Protect 0 (BP0) is not set
81. Chip status register: Write Enable Latch (WEL) is not set
82. Chip status register: Write In Progress (WIP/BUSY) is not set
83. Resulting block protection : none
84. Found chip "SST SST25VF040B" (512 KB, SPI) at physical address
0xfff80000.
85. ===
86. This flash part has status UNTESTED for operations: PROBE READ ERASE
WRITE
87. Please email a report to flashrom(a)flashrom.org if any of the above
operations
88. work correctly for you with this flash part. Please include the
flashrom
89. output with the additional -V option for all operations you tested
(-V, -rV,
90. -wV, -EV), and mention which mainboard you tested. Thanks for your
help!
91. ===
92. Flash image seems to be a legacy BIOS. Disabling checks.
93. Writing flash chip... Erasing flash before programming... Invalid
OPCODE 0x06
94. due to SPI master limitation, ignoring and hoping it will be run as
PREOP
95. done.
96. Invalid OPCODE 0x06
97. due to SPI master limitation, ignoring and hoping it will be run as
PREOP
98. Invalid OPCODE 0x06
99. due to SPI master limitation, ignoring and hoping it will be run as
PREOP
100. Invalid OPCODE 0x06
101. due to SPI master limitation, ignoring and hoping it will be run as
PREOP
102. Invalid OPCODE 0x06
103. due to SPI master limitation, ignoring and hoping it will be run as
PREOP
104. Invalid OPCODE 0x06
105. due to SPI master limitation, ignoring and hoping it will be run as
PREOP
106. Invalid OPCODE 0x06
107. due to SPI master limitation, ignoring and hoping it will be run as
PREOP
108. Invalid OPCODE 0x06
109. due to SPI master limitation, ignoring and hoping it will be run as
PREOP
110. Invalid OPCODE 0x06
111. due to SPI master limitation, ignoring and hoping it will be run as
PREOP
112. Invalid OPCODE 0x06
113. due to SPI master limitation, ignoring and hoping it will be run as
PREOP
114.
115. <few hundred times more the same error line>
116.
117. Invalid OPCODE 0x06
118. due to SPI master limitation, ignoring and hoping it will be run as
PREOP
119. Invalid OPCODE 0x06
120. due to SPI master limitation, ignoring and hoping it will be run as
PREOP
121. Invalid OPCODE 0x06
122. due to SPI master limitation, ignoring and hoping it will be run as
PREOP
123. COMPLETE.
124. Verifying flash... VERIFIED.
125.
126.
127.
128.
======================================================================================
129. Checking:
130.
131. linda@tuxbox:~/LMX1103$ sudo flashrom -c SST25VF040B -vV LMX1103.ROM
132. flashrom v0.9.1-r706
133. No coreboot table found.
134. Found chipset "Intel ICH7/ICH7R", enabling flash write...
135. 0xfff80000/0xffb80000 FWH IDSEL: 0x0
136. 0xfff00000/0xffb00000 FWH IDSEL: 0x0
137. 0xffe80000/0xffa80000 FWH IDSEL: 0x1
138. 0xffe00000/0xffa00000 FWH IDSEL: 0x1
139. 0xffd80000/0xff980000 FWH IDSEL: 0x2
140. 0xffd00000/0xff900000 FWH IDSEL: 0x2
141. 0xffc80000/0xff880000 FWH IDSEL: 0x3
142. 0xffc00000/0xff800000 FWH IDSEL: 0x3
143. 0xff700000/0xff300000 FWH IDSEL: 0x4
144. 0xff600000/0xff200000 FWH IDSEL: 0x5
145. 0xff500000/0xff100000 FWH IDSEL: 0x6
146. 0xff400000/0xff000000 FWH IDSEL: 0x7
147. 0xfff80000/0xffb80000 FWH decode enabled
148. 0xfff00000/0xffb00000 FWH decode disabled
149. 0xffe80000/0xffa80000 FWH decode disabled
150. 0xffe00000/0xffa00000 FWH decode disabled
151. 0xffd80000/0xff980000 FWH decode disabled
152. 0xffd00000/0xff900000 FWH decode disabled
153. 0xffc80000/0xff880000 FWH decode disabled
154. 0xffc00000/0xff800000 FWH decode disabled
155. 0xff700000/0xff300000 FWH decode disabled
156. 0xff600000/0xff200000 FWH decode disabled
157. 0xff500000/0xff100000 FWH decode disabled
158. 0xff400000/0xff000000 FWH decode disabled
159. BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is
0x1
160.
161. Root Complex Register Block address = 0xfed1c000
162. GCS = 0x464: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps:
0x1 (SPI)
163. Top Swap : not enabled
164. SPIBAR = 0xfed1c000 + 0x3020
165. 0x00: 0x0004 (SPIS)
166. 0x02: 0x7f10 (SPIC)
167. 0x04: 0x0007ffc0 (SPIA)
168. 0x08: 0x0000004d (SPID0)
169. 0x0c: 0x00000000 (SPID0+4)
170. 0x10: 0x00000000 (SPID1)
171. 0x14: 0x0000471d (SPID1+4)
172. 0x18: 0x50120000 (SPID2)
173. 0x1c: 0x00495100 (SPID2+4)
174. 0x20: 0x00000100 (SPID3)
175. 0x24: 0x00000040 (SPID3+4)
176. 0x28: 0x30363041 (SPID4)
177. 0x2c: 0x30303035 (SPID4+4)
178. 0x30: 0x00000000 (SPID5)
179. 0x34: 0x00000000 (SPID5+4)
180. 0x38: 0x00ffaaea (SPID6)
181. 0x3c: 0x2f3231f0 (SPID6+4)
182. 0x40: 0x302f3231 (SPID7)
183. 0x44: 0x00fc0037 (SPID7+4)
184. 0x50: 0x00000000 (BBAR)
185. 0x54: 0x0006 (PREOP)
186. 0x56: 0x463b (OPTYPE)
187. 0x58: 0x05d80302 (OPMENU)
188. 0x5c: 0xc79f0190 (OPMENU+4)
189. 0x60: 0x00000000 (PBR0)
190. 0x64: 0x00000000 (PBR1)
191. 0x68: 0x00000000 (PBR2)
192. 0x6c: 0x00000000 (PBR3)
193.
194. Programming OPCODES...
195. program_opcodes: preop=0006 optype=463b opmenu=05d80302c79f0190
196. done
197. SPI Read Configuration: prefetching disabled, caching enabled, OK.
198. This chipset supports the following protocols: SPI.
199. Calibrating delay loop... 784M loops per second, 100 myus = 197 us.
OK.
200. Probing for SST SST25VF040B, 512 KB: RDID returned 0xbf 0x25 0x8d.
probe_spi_rdid_generic: id1 0xbf, id2 0x258d
201. Chip status register is 00
202. Chip status register: Block Protect Write Disable (BPL) is not set
203. Chip status register: Auto Address Increment Programming (AAI) is
not set
204. Chip status register: Bit 5 / Block Protect 3 (BP3) is not set
205. Chip status register: Bit 4 / Block Protect 2 (BP2) is not set
206. Chip status register: Bit 3 / Block Protect 1 (BP1) is not set
207. Chip status register: Bit 2 / Block Protect 0 (BP0) is not set
208. Chip status register: Write Enable Latch (WEL) is not set
209. Chip status register: Write In Progress (WIP/BUSY) is not set
210. Resulting block protection : none
211. Found chip "SST SST25VF040B" (512 KB, SPI) at physical address
0xfff80000.
212. ===
213. This flash part has status UNTESTED for operations: PROBE READ ERASE
WRITE
214. Please email a report to flashrom(a)flashrom.org if any of the above
operations
215. work correctly for you with this flash part. Please include the
flashrom
216. output with the additional -V option for all operations you tested
(-V, -rV,
217. -wV, -EV), and mention which mainboard you tested. Thanks for your
help!
218. ===
219. Flash image seems to be a legacy BIOS. Disabling checks.
220. Verifying flash... VERIFIED.
On Sat, Oct 10, 2009 at 09:31:17PM -0300, Ulf Mehlig wrote:
> Acked-by: Ulf Mehlig <ulf(a)ufpa.br>
>
> rebooting worked, also after re-flashing with the latest BIOS from
> Shuttles Website; the ethernet address was preserved on reboot.
>
> Seems to be everything ok, then.
>
> Thanks again! Ulf
>
> On Wed, 2009-09-23 at 10:26 -0300, Luc Verhaegen wrote:
> > On Wed, Sep 23, 2009 at 10:14:47AM -0300, Ulf Mehlig wrote:
> > > Thanks for the patch, and many thanks again for helping me out
> > > yesterday!
> > >
> > > All the best, Ulf
> > >
> >
> > Does it work? If so, reply with: Acked-by: Ulf Mehlig <ulf(a)ufpa.br>
> > so that it can be committed.
> >
> > Also, carldani is about to send in a patch for your bios chip, i am not
> > sure how to test this, but he can explain this.
> >
> > Luc Verhaegen.
Thanks: -> r752.
Luc Verhaegen.
Hi.
I downloaded the latest snapshot of flashrom as you suggested, and you will find the new log in the attached file.
There is yet a lot of "opcode 0x06 will be run as PREOP" lines: I deleted all of them but the first sequences.
If you need them, let me known. I can rerun the program anytime, and if this little job can help you, I will do it.
About the code for the PentiumM/82855GME: I'm sorry, but I have nothing to submit. Is was a my personal attempt to port linuxbios, but the activity was (too soon ?) stopped. The development tree was moved into the "old things limbo", from where it was deleted by a mistyped answer during disk maintenance.
Anyway, thanks.
Regards
Maurizio Cavalli
Sviluppo Software
CONTROL SYSTEMS S.r.l.
Via del Brolo, 14
26100 CREMONA (Italy)
tel +39 0372 471806
fax +39 0372 471823
www.controlsystems-srl.it
-----Original Message-----
From: Carl-Daniel Hailfinger [mailto:c-d.hailfinger.devel.2006@gmx.net]
Sent: Fri 10/16/2009 12:45 PM
To: Maurizio Cavalli
Cc: flashrom(a)flashrom.org
Subject: Re: [flashrom] Winbond W25X16 successful programming
Hi Maurizio,
thank you for your report. I will add your chip to the supported list.
On 16.10.2009 10:03, Maurizio Cavalli wrote:
> I had successfully programmed a Winbond W25X16(BVSSIG) chip with flashrom.
>
> Board: ROE RIVER Evaluation Board from Intel
> (Reference: Intel® AtomTM Processor N270 and Mobile Intel® 945GSE Express Chipset Development Kit User's Manual - Document number: 320436-002)
> BIOS: Phoenix Embedded BIOS(R) w/StrongFrame(R) Technology.
> Kernel: Linux 2.6.30.2 SMP, compiled from source tree
> Host system: Debian 5.0
>
The log of your flashrom version had thousands of lines like this:
Invalid OPCODE 0x06
due to SPI master limitation, ignoring and hoping it will be run as PREOP
I have removed them from your log to make the mail smaller.
It would be great if you could test erase and write with the latest
flashrom from svn as well. The invalid opcode messages should have
disappeared.
> (I apologize we cannot use coreboot because lack of chipsets documentation from Intel. We already tried to port linuxBios onto a PentiumM/82855GME platform, but we failed in setting up the integrated graphic controller)
>
Oh, that is interesting. So you do already have some code, but it is not
working yet? Could you please send that code to the coreboot mailing
list <coreboot(a)coreboot.org> so other developers can have a look. Maybe
someone has good docs for that platform.
Regards,
Carl-Daniel
--
Developer quote of the week:
"We are juggling too many chainsaws and flaming arrows and tigers."
Hi Sean,
I have some questions about your kt4v/kt4ultra board enable:
1) I am about to move some code from many vt823x based board
enables to the chipset enable. Your board enable has some "similar"
code, but not quite, and it now forms the only anomaly.
Can you send me the output of:
dd if=/dev/mem of=/tmp/kt4v_system.rom bs=64k count=1 skip=15
so i can have a dig through the top segment of your AMI BIOS to verify
this code?
2) I am about to tighten up the board enable matching table.
* both the coreboot ids will disappear.
* we need a second set for the kt4v.
Can you send in lspci -vvnnxxx on both boards?
Thanks,
Luc Verhaegen.
Hi Maurizio,
thank you for your report. I will add your chip to the supported list.
On 16.10.2009 10:03, Maurizio Cavalli wrote:
> I had successfully programmed a Winbond W25X16(BVSSIG) chip with flashrom.
>
> Board: ROE RIVER Evaluation Board from Intel
> (Reference: Intel® AtomTM Processor N270 and Mobile Intel® 945GSE Express Chipset Development Kit User’s Manual - Document number: 320436-002)
> BIOS: Phoenix Embedded BIOS(R) w/StrongFrame(R) Technology.
> Kernel: Linux 2.6.30.2 SMP, compiled from source tree
> Host system: Debian 5.0
>
The log of your flashrom version had thousands of lines like this:
Invalid OPCODE 0x06
due to SPI master limitation, ignoring and hoping it will be run as PREOP
I have removed them from your log to make the mail smaller.
It would be great if you could test erase and write with the latest
flashrom from svn as well. The invalid opcode messages should have
disappeared.
> (I apologize we cannot use coreboot because lack of chipsets documentation from Intel. We already tried to port linuxBios onto a PentiumM/82855GME platform, but we failed in setting up the integrated graphic controller)
>
Oh, that is interesting. So you do already have some code, but it is not
working yet? Could you please send that code to the coreboot mailing
list <coreboot(a)coreboot.org> so other developers can have a look. Maybe
someone has good docs for that platform.
Regards,
Carl-Daniel
--
Developer quote of the week:
"We are juggling too many chainsaws and flaming arrows and tigers."