- flashrom - mail.coreboot.org

[commit] r1676 - branches/stuge
by repository service June 1, 2013

June 1, 2013

Author: stefanct Date: Sat Jun 1 02:30:31 2013 New Revision: 1676 URL: http://flashrom.org/trac/flashrom/changeset/1676 Log: Remove Peter's obsolete branch. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Deleted: branches/stuge/

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[commit] r1675 - trunk
by repository service June 1, 2013

June 1, 2013

Author: stefanct Date: Sat Jun 1 02:06:12 2013 New Revision: 1675 URL: http://flashrom.org/trac/flashrom/changeset/1675 Log: Change warning regarding protected ICH regions. There is no good reason to collect further log files of locked Intel- based boards. Forward affected users directly to an explanation in the wiki instead. Signed-off-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Thu May 23 23:47:46 2013 (r1674) +++ trunk/ichspi.c Sat Jun 1 02:06:12 2013 (r1675) @@ -1700,6 +1700,10 @@ /* Handle FREGx and FRAP registers */ for (i = 0; i < 5; i++) ich_spi_rw_restricted |= ich9_handle_frap(tmp, i); + if (ich_spi_rw_restricted) + msg_pwarn("Not all flash regions are freely accessible by flashrom. This is " + "most likely\ndue to an active ME. Please see http://flashrom.org/ME " + "for details.\n"); } /* Handle PR registers */ @@ -1711,11 +1715,6 @@ } if (ich_spi_rw_restricted) { - msg_pinfo("Please send a verbose log to " - "flashrom(a)flashrom.org if this board is not " - "listed on\n" - "http://flashrom.org/Supported_hardware#Supported_mainboards " - "yet.\n"); if (!ich_spi_force) programmer_may_write = 0; msg_pinfo("Writes have been disabled for safety reasons. You can enforce write\n"

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Script for collecting flashrom compatibility with motherboards
by Alexey Vazhnov May 31, 2013

May 31, 2013

Hi! Perhaps we can check many hardware for compatibility with Linux. Condition: test must be fast, so no manual intervention. So now I prepare some PXE images for collect hardware information. How do I collect maximum information about motherboards chips compatible with flashrom? Currently I see only one variant — write motherboard name with «flashrom -r /dev/null» stdout. -- Yours respectfully, Alexey Vazhnov Jabber: vazhnov(a)jabber.ru

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Re: [flashrom] Read test - Dell Dimension C521
by Stefan Tauner May 31, 2013

May 31, 2013

On Wed, 15 May 2013 10:39:44 +0200 Gil <agile81(a)gmail.com> wrote: > seems fine > > flashrom v0.9.6.1-r1563 on Linux generic (i686) > flashrom was built with libpci 3.1.9, GCC 4.7.1, little endian > Command line (5 args): flashrom -VVV -p internal -o fl1 > Calibrating delay loop... OS timer resolution is 2 usecs, 948M loops > per second, 10 myus = 12 us, 100 myus = 101 us, 1000 myus = 997 us, > 10000 myus = 10369 us, 8 myus = 9 us, OK. > Initializing internal programmer > No coreboot table found. > DMI string system-manufacturer: "Dell Inc" > DMI string system-product-name: "Dimension C521" > DMI string system-version: " " > DMI string baseboard-manufacturer: "Dell Inc" > DMI string baseboard-product-name: " " > DMI string baseboard-version: " " > DMI string chassis-type: "Desktop" > Found chipset "NVIDIA MCP51" with PCI ID 10de:0260. Enabling flash write... > OK. > ... > The following protocols are supported: Non-SPI. > ... > Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e > Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH) at physical > address 0xfff80000. > ... > Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH). > No operations were specified. > Restoring PCI config space for 00:0a:0 reg 0x6d > > Saved BIOS ROM ok Hi Gil and thanks for your report. We are not really interested in (successful) read tests for boards (because they don't tell anything about writes and we do not keep track of that separately). Also, please do not prune logs even if you think you do us a favor and that there is lots of useless stuff in it. :) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Winbond W25X20 on Tumpa programmer works
by J. Domburg May 31, 2013

May 31, 2013

As subject. Verbose read and write output of flashrom is attached. Cheers, Jeroen

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Asus P8P67 LE works, successfully wrote and verified
by artemis3 May 30, 2013

May 30, 2013

Hello, I checked your wiki matrix, and I'm not sure i quite understand where it says "NO (42)" what exactly means. I have this motherboard, which is a B2. there is a B3 next to it in your hardware table with a green "OK" (P8P67 PRO). I went ahead and tried flashing anyway and it worked!, It could write and verify back an old bios (1104) downloaded from Asus page. This board was nearly bricked by the writing of a B3 bios which made all sort of trouble to it, after several attempts (wouldn't post) i managed to boot linux and went with flashrom. Note 42 has this written: "Probing works (Winbond W25Q32, 4096 kB, SPI), but parts of the flash are problematic: descriptor is r/o (conforming to ICH reqs), ME region is locked." But this is wrong, flashrom identified chip MX25L3205 like the other 2 previous models. I have no idea what this ME and ICH business is to deserve a red NO, but it worked with mine. Asus page happily mentions "Pre-B3 revision motherboard users can also download and use the new B3 revision BIOS, drivers and utilities." http://event.asus.com/2011/mb/Identify_B3_Motherboards/ That is absolutely wrong!, Pre B3 users can't use any B3 BIOS image!. In my case, the bios got all sensor values wrong, and it wanted to shutdown as it thought the processor was over/under temp, voltage etc, i managed to turn off all power setting things i could to be able to post, and the bios would often freeze requiring moving the clear jumper before even wanting to turn the power on again many times. I also learned something about Asus: while their BIOS EZ Flash tool happily allows upgrading to this dangerous B3 bios in a B2 board, it won't let you flash back to the older working version, genius move... I used flashrom 0.9.5.2+r1517-1 from the Ubuntu repository. flashrom v0.9.5.2-r1517 on Linux 3.5.0-28-generic (x86_64), built with libpci 3.1.8, GCC 4.6.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "Intel P67". Enabling flash write... OK. Found Macronix flash chip "MX25L3205" (4096 kB, SPI) at physical address 0xffc00000.

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Re: [flashrom] New board for list
by Stefan Tauner May 30, 2013

May 30, 2013

On Sat, 18 May 2013 15:48:56 -0400 Aurelius R <maxrowsell(a)gmail.com> wrote: > The board from the HP Pavilion a6200n which has the NVIDIA nForce 430 > Chipset works great -- I tested it multiple times reading, writing and > erasing the BIOS chip, no flaws, no errors at all. I'm also going to try > and write the VESA chip (nVidia MCP61-80) which seems to be a separate > chip, because that is the chip that seems to be causing all the trouble on > this board. > > Anyway, just thought you'd like to add that info to your list. I can also > provide the dump from flashrom -V that the program says to email to you, as > support isn't quite complete for my board/chip if you want. Hello Alexander, yes please send a verbose log (probing for the chip is good enough for now, no need to read/write). Can you confirm that this is the board in question? http://h10025.www1.hp.com/ewfrf/wc/document?docname=c01077676&tmp_task=prod… You seem to be under the impression that the graphics core uses a separate flash chip for its firmware. This is probably not the case. Instead it shares it with the "BIOS" chip that flashrom accesses. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Fwd: Re: Added chipsets
by Steven Zakulec May 28, 2013

May 28, 2013

---------- Forwarded message ---------- From: "Николай Николаев" <evrinoma(a)gmail.com> Date: May 28, 2013 1:28 AM Subject: Re: [flashrom] Added chipsets To: "Steven Zakulec" <spzakulec(a)gmail.com> Cc: Hi Steven, Other people can provide more details on the general case, but in this > instance, with only a WREN instruction, the FEATURE line should be: > I've been informed by others that your original idea of dropping the > FEATURE line is actually correct, so you should do that instead of what I > proposed. > i dropped this line because this line for chips fetch Numonyx N25Q00AA13- >>> I'll admit I don't really know how this chip works, but it seems there >>> should be a 3rd eraseblock from the description of the memory organization >>> (datasheet is Rev E, 2/12): >>> >>> Memory Configuration and Block Diagram >>> The memory is a stacked device comprised of four 256Mb chips. Each chip >>> is internally >>> partitioned into two 128Mb segments. Each page of memory can be >>> individually pro- >>> grammed. Bits are programmed from one through zero. The device is >>> subsector, sector, >>> or single 256Mb chip erasable, but not page-erasable. Bits are erased >>> from zero through >>> one. The memory is configured as 134,217,728 bytes (8 bits each); 2048 >>> sectors (64KB >>> each); 32,768 subsectors (4KB each); and 524,288 pages (256 bytes each); >>> and 64 OTP >>> bytes are located outside the main memory array. >>> >>> You've got: >>> + .eraseblocks = { {4 * 1024, 32768 } }, >>> + .block_erase = spi_block_erase_20, >>> + }, { >>> + .eraseblocks = { {64 * 1024, 2048 } }, >>> + .block_erase = spi_block_erase_d8, >>> >>> There's a die erase opcode, which I am unfamiliar with- maybe it handles >>> erasing a single 256Mb chip at a time? >>> >> >> You right this chip used a four 256 Mb chips. And 256 Mb chip has a three >> instruction subsector 20(hex) sector D8(hex) bulk C7(hex) erase commands. >> But chip N25Q00AA13 has a other op-code to initiate die erase command >> C4 (hex) >> >> So, how do you do a single-chip erase for this chip? > I think this function is feature, because use "not general" op-code C4 for die erase command. Also first we need to write a special function feature extended addressing for chips more than 128 mb, after that we will think about how to initiate die erase instruction. What data sheets do you have for those chips? The ones below list the > small sector erase op-code as D7. > LE25FW418A: 61709 SY 20090428-S00004 No.A1432 > LE25FW808: 61009 SY IM 20090319-S00003 No.A0839 > LE25FW806: 70208 SY IM 20070628-S00004 No.A0838 > I have a equivalence data sheets. LE25FW808 has a general op-code 20(hex) to initiate small sector erase. Other chips use a feature op-code as D7. -- With best regards Nikolay Nikolaev

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Please help
by Aaron Brown May 28, 2013

May 28, 2013

Hi . I installed flashrom 9.6.1 but cant find any button that says "write flashrom" please tell me, how exactly I can write the bios ? ------------------------------------------------------------------------------ with big honor. Aaron

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Re: [flashrom] Added chipsets
by Николай Николаев May 28, 2013

May 28, 2013

---------- Forwarded message ---------- From: Николай Николаев <evrinoma(a)gmail.com> Date: 2013/5/28 Subject: Re: [flashrom] Added chipsets To: Steven Zakulec <spzakulec(a)gmail.com> Hi Steven, Other people can provide more details on the general case, but in this > instance, with only a WREN instruction, the FEATURE line should be: > I've been informed by others that your original idea of dropping the > FEATURE line is actually correct, so you should do that instead of what I > proposed. > i dropped this line because this line for chips fetch Numonyx N25Q00AA13- >>> I'll admit I don't really know how this chip works, but it seems there >>> should be a 3rd eraseblock from the description of the memory organization >>> (datasheet is Rev E, 2/12): >>> >>> Memory Configuration and Block Diagram >>> The memory is a stacked device comprised of four 256Mb chips. Each chip >>> is internally >>> partitioned into two 128Mb segments. Each page of memory can be >>> individually pro- >>> grammed. Bits are programmed from one through zero. The device is >>> subsector, sector, >>> or single 256Mb chip erasable, but not page-erasable. Bits are erased >>> from zero through >>> one. The memory is configured as 134,217,728 bytes (8 bits each); 2048 >>> sectors (64KB >>> each); 32,768 subsectors (4KB each); and 524,288 pages (256 bytes each); >>> and 64 OTP >>> bytes are located outside the main memory array. >>> >>> You've got: >>> + .eraseblocks = { {4 * 1024, 32768 } }, >>> + .block_erase = spi_block_erase_20, >>> + }, { >>> + .eraseblocks = { {64 * 1024, 2048 } }, >>> + .block_erase = spi_block_erase_d8, >>> >>> There's a die erase opcode, which I am unfamiliar with- maybe it handles >>> erasing a single 256Mb chip at a time? >>> >> >> You right this chip used a four 256 Mb chips. And 256 Mb chip has a three >> instruction subsector 20(hex) sector D8(hex) bulk C7(hex) erase commands. >> But chip N25Q00AA13 has a other op-code to initiate die erase command >> C4 (hex) >> >> So, how do you do a single-chip erase for this chip? > I think this function is feature, because use "not general" op-code C4 for die erase command. Also first we need to write a special function feature extended addressing for chips more than 128 mb, after that we will think about how to initiate die erase instruction. What data sheets do you have for those chips? The ones below list the > small sector erase op-code as D7. > LE25FW418A: 61709 SY 20090428-S00004 No.A1432 > LE25FW808: 61009 SY IM 20090319-S00003 No.A0839 > LE25FW806: 70208 SY IM 20070628-S00004 No.A0838 > I have a equivalence data sheets. LE25FW808 has a general op-code 20(hex) to initiate small sector erase. Other chips use a feature op-code as D7. -- With best regards Nikolay Nikolaev -- With best regards Nikolay Nikolaev С Уважением Николаев Николай

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