May 2022 - flashrom - mail.coreboot.org

Restructure shutdown functions and remove global state
by Joursoir Aug. 5, 2022

Aug. 5, 2022

Hello everyone, Today I had a first meeting with my mentor Anastasia. And I'm looking forward to see Thomas as soon as possible. We've discussed our project goals, initial tasks and current state of the code. My next tasks: 1) Move all par masters to new API. It includes reducing the use of static global variables by storing them in a specific programmer data structure. 2) Introduce default shutdown function that can be very useful. We already have a patch for it: https://review.coreboot.org/c/flashrom/+/54890 It will be done in small steps/commits. So I hope to send a first patch soon. -- Joursoir

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New chip: GD25Q64C
by janemba June 25, 2022

June 25, 2022

Hello, flashrom can extract the eeprom from a GD25Q64C chip in a generic way. I did it and all worked fine. Also, I check the eeprom and its valid. However, flashrom told me to send you an email with some information which you can find attached. However, this is the output while using "-r" switch along with the verbose mode. I hope it will be fine. Cheers,

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One Build System Working Group
by Thomas Heijligen June 21, 2022

June 21, 2022

Hi folks, we want to meet again to discuss the progress and problems under the One Build Sytem Topic. If you are interested, please participate on the poll [0] to find a suitable date. On Gerrit, relevant patches can be found under the `one_build_system` topic. [1] The working document can be found on Google Docs [3] and gets also posted in plain text to the mailing list after the meeting. -- Thomas [0] https://terminplaner4.dfn.de/Eha1mJJ8jS2z2dkw [1] https://review.coreboot.org/q/project:flashrom+topic:one_build_system [3] https://docs.google.com/document/d/1TVso_VbrLEbGc7BNrYxqlrP8jMxB23TuMqEI3Pn…

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GSOC Project Thread - Optimising Erase Function Selection
by Aarya Chaumal June 16, 2022

June 16, 2022

Hi, Today I had my first meet with my mentors Thomas and Simon, and we discussed a few things involving the timeline and initial tasks for the project. There are mainly two parts to the project : 1. Developing a strategy to optimize the selection of the erase function to reduce the overall time required to do the operation 2. Filtering out the erase functions that the programmer does not support For now, I'm working on the first one. Also, I will be writing a test case to check whether the erase functions in the flashchips struct are sorted according to the block size. Aarya

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Refactor arguments parser - GSOC project thread
by Chinmay Lonkar June 10, 2022

June 10, 2022

Hello, Today I had a meeting with my mentors Felix and Anastasia. The project plan has been broken into phases. I'll work on the first phase, which will entail creating an alternative to extract_programmer_param() that will parse the programmer's sub-arguments according to the data type in which they have to be utilized in the code. So, I'll be reading through the code and working out a solution for this task, as well as analyzing all of the other parameters that the programmers utilize. Regards, Chinmay Lonkar

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Good Afternoon, ( Bios Help )
by RED-LAB ? June 3, 2022

June 3, 2022

Good Afternoon, Can You Guys Help Me I Have A Virus In My Bios My is Computer Booting and executing a code inside computer dell precision t5500 dual xeon my tel 954-305-1626 david

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Spansion S25FL128L readout
by Hilco de Lathouder May 31, 2022

May 31, 2022

Hi All, I have a Spansion chip I want to read but it seems not supported by flashrom. I can connect and read JEDEC ID with BusPirate: it says 01-60-18 which corresponds with the Spansion S25FL128L (specs available online). Flashrom does not detect it. I tried reading it while forcing any of the other 128Mbit Spansion chips, but could not make anything of the rom with Binwalk. What would be the best strategy to get to the contents of this chip? Thanks in advance, Hilco

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Decision making process
by Anastasia Klimchuk May 30, 2022

May 30, 2022

Hello People, The topic initially came up in the “Gatekeeping” thread. However it was suggested that it should be a separate thread, which makes sense so I am starting one. So, straight to the point: it looks like we have a decision making process emerging! (below). What do people think about it? #1 Discuss things on the mailing list first. It could be ongoing for months - so that everyone who is interested has time to read and respond. However, it doesn’t have to be for months. #2 When/if the discussion seems to be settled and people are in agreement, the item can be added to the agenda of the meeting. #3 At the meeting the item can be discussed again, and a decision can be made (or not made, if people disagree). #4 After the meeting we send an email with meeting notes and “Decisions summary” on the top of the email. #5 Since stuff never gets done immediately, there always be some time to react on #4 If someone has objections/concerns, it would be great if you can propose improvements or alternative solutions. Please don’t just say “this is all wrong!” Many thanks for sharing your thoughts! -- Anastasia.

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Request for clarification on "per-region file arguments" issue
by Daniel Campello May 24, 2022

May 24, 2022

Hello, I decided to take a look at https://ticket.coreboot.org/issues/372 and I would like to get a better understanding of what is being requested on the issue tracker. I took a look at the submitted patch (comments and code diff) and everything seems in order to me. I appreciate any assistance you can provide, Regards, Daniel Campello

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new chip - GD25LR256E
by Igor Omelchenko May 24, 2022

May 24, 2022

Hello guys, trying to add a new chip GigaDevices into flashchips.c, without success. Can someone help me to add it. Thanks. trying something like this: { .vendor = "GigaDevice", .name = "GD25LR256E", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, .model_id = GIGADEVICE_GD25LR256E, .total_size = 32768, .page_size = 256, /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { { .eraseblocks = { {4 * 1024, 8192} }, .block_erase = spi_block_erase_20, }, { .eraseblocks = { {32 * 1024, 1024} }, .block_erase = spi_block_erase_52, }, { .eraseblocks = { {64 * 1024, 512} }, .block_erase = spi_block_erase_d8, }, { .eraseblocks = { {32 * 1024 * 1024, 1} }, .block_erase = spi_block_erase_60, }, { .eraseblocks = { {32 * 1024 * 1024, 1} }, .block_erase = spi_block_erase_c7, } }, .printlock = spi_prettyprint_status_register_bp4_srwd, .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1695, 1950},} -- *Omelchenko Igor* *0543-066-855*

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